1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 44;
11using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15 mutable MatcherState State;
16 typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17 typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
19 static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20 static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24 const uint8_t *getMatchTable() const override;
25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
26 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
27 bool testSimplePredicate(unsigned PredicateID) const override;
28 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
29#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
30
31#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32, State(0),
33ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
34#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
35
36#ifdef GET_GLOBALISEL_IMPL
37// LLT Objects.
38enum {
39 GILLT_s16,
40 GILLT_s32,
41 GILLT_s64,
42 GILLT_v2s16,
43 GILLT_v2s64,
44 GILLT_v4s8,
45 GILLT_v4s32,
46 GILLT_v8s16,
47 GILLT_v16s8,
48};
49const static size_t NumTypeObjects = 9;
50const static LLT TypeObjects[] = {
51 LLT::scalar(16),
52 LLT::scalar(32),
53 LLT::scalar(64),
54 LLT::vector(ElementCount::getFixed(2), 16),
55 LLT::vector(ElementCount::getFixed(2), 64),
56 LLT::vector(ElementCount::getFixed(4), 8),
57 LLT::vector(ElementCount::getFixed(4), 32),
58 LLT::vector(ElementCount::getFixed(8), 16),
59 LLT::vector(ElementCount::getFixed(16), 8),
60};
61
62// Bits for subtarget features that participate in instruction matching.
63enum SubtargetFeatureBits : uint8_t {
64 Feature_HasMips2Bit = 7,
65 Feature_HasMips3Bit = 17,
66 Feature_HasMips4_32Bit = 27,
67 Feature_NotMips4_32Bit = 28,
68 Feature_HasMips4_32r2Bit = 18,
69 Feature_HasMips32Bit = 3,
70 Feature_HasMips32r2Bit = 6,
71 Feature_HasMips32r6Bit = 29,
72 Feature_NotMips32r6Bit = 4,
73 Feature_IsGP64bitBit = 22,
74 Feature_IsPTR64bitBit = 24,
75 Feature_HasMips64Bit = 25,
76 Feature_HasMips64r2Bit = 23,
77 Feature_HasMips64r6Bit = 30,
78 Feature_NotMips64r6Bit = 5,
79 Feature_InMips16ModeBit = 31,
80 Feature_NotInMips16ModeBit = 0,
81 Feature_HasCnMipsBit = 26,
82 Feature_NotCnMipsBit = 8,
83 Feature_IsSym32Bit = 38,
84 Feature_IsSym64Bit = 39,
85 Feature_IsN64Bit = 40,
86 Feature_RelocNotPICBit = 9,
87 Feature_RelocPICBit = 37,
88 Feature_NoNaNsFPMathBit = 21,
89 Feature_UseAbsBit = 14,
90 Feature_HasStdEncBit = 1,
91 Feature_NotDSPBit = 11,
92 Feature_InMicroMipsBit = 35,
93 Feature_NotInMicroMipsBit = 2,
94 Feature_IsLEBit = 42,
95 Feature_IsBEBit = 43,
96 Feature_IsNotNaClBit = 19,
97 Feature_HasEVABit = 36,
98 Feature_HasMSABit = 34,
99 Feature_HasMadd4Bit = 20,
100 Feature_UseIndirectJumpsHazardBit = 12,
101 Feature_NoIndirectJumpGuardsBit = 10,
102 Feature_AllowFPOpFusionBit = 41,
103 Feature_IsFP64bitBit = 16,
104 Feature_NotFP64bitBit = 15,
105 Feature_IsNotSoftFloatBit = 13,
106 Feature_HasDSPBit = 32,
107 Feature_HasDSPR2Bit = 33,
108};
109
110PredicateBitset MipsInstructionSelector::
111computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
112 PredicateBitset Features{};
113 if (Subtarget->hasMips2())
114 Features.set(Feature_HasMips2Bit);
115 if (Subtarget->hasMips3())
116 Features.set(Feature_HasMips3Bit);
117 if (Subtarget->hasMips4_32())
118 Features.set(Feature_HasMips4_32Bit);
119 if (!Subtarget->hasMips4_32())
120 Features.set(Feature_NotMips4_32Bit);
121 if (Subtarget->hasMips4_32r2())
122 Features.set(Feature_HasMips4_32r2Bit);
123 if (Subtarget->hasMips32())
124 Features.set(Feature_HasMips32Bit);
125 if (Subtarget->hasMips32r2())
126 Features.set(Feature_HasMips32r2Bit);
127 if (Subtarget->hasMips32r6())
128 Features.set(Feature_HasMips32r6Bit);
129 if (!Subtarget->hasMips32r6())
130 Features.set(Feature_NotMips32r6Bit);
131 if (Subtarget->isGP64bit())
132 Features.set(Feature_IsGP64bitBit);
133 if (Subtarget->isABI_N64())
134 Features.set(Feature_IsPTR64bitBit);
135 if (Subtarget->hasMips64())
136 Features.set(Feature_HasMips64Bit);
137 if (Subtarget->hasMips64r2())
138 Features.set(Feature_HasMips64r2Bit);
139 if (Subtarget->hasMips64r6())
140 Features.set(Feature_HasMips64r6Bit);
141 if (!Subtarget->hasMips64r6())
142 Features.set(Feature_NotMips64r6Bit);
143 if (Subtarget->inMips16Mode())
144 Features.set(Feature_InMips16ModeBit);
145 if (!Subtarget->inMips16Mode())
146 Features.set(Feature_NotInMips16ModeBit);
147 if (Subtarget->hasCnMips())
148 Features.set(Feature_HasCnMipsBit);
149 if (!Subtarget->hasCnMips())
150 Features.set(Feature_NotCnMipsBit);
151 if (Subtarget->hasSym32())
152 Features.set(Feature_IsSym32Bit);
153 if (!Subtarget->hasSym32())
154 Features.set(Feature_IsSym64Bit);
155 if (Subtarget->isABI_N64())
156 Features.set(Feature_IsN64Bit);
157 if (!TM.isPositionIndependent())
158 Features.set(Feature_RelocNotPICBit);
159 if (TM.isPositionIndependent())
160 Features.set(Feature_RelocPICBit);
161 if (TM.Options.NoNaNsFPMath)
162 Features.set(Feature_NoNaNsFPMathBit);
163 if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)
164 Features.set(Feature_UseAbsBit);
165 if (Subtarget->hasStandardEncoding())
166 Features.set(Feature_HasStdEncBit);
167 if (!Subtarget->hasDSP())
168 Features.set(Feature_NotDSPBit);
169 if (Subtarget->inMicroMipsMode())
170 Features.set(Feature_InMicroMipsBit);
171 if (!Subtarget->inMicroMipsMode())
172 Features.set(Feature_NotInMicroMipsBit);
173 if (Subtarget->isLittle())
174 Features.set(Feature_IsLEBit);
175 if (!Subtarget->isLittle())
176 Features.set(Feature_IsBEBit);
177 if (!Subtarget->isTargetNaCl())
178 Features.set(Feature_IsNotNaClBit);
179 if (Subtarget->hasEVA())
180 Features.set(Feature_HasEVABit);
181 if (Subtarget->hasMSA())
182 Features.set(Feature_HasMSABit);
183 if (!Subtarget->disableMadd4())
184 Features.set(Feature_HasMadd4Bit);
185 if (Subtarget->useIndirectJumpsHazard())
186 Features.set(Feature_UseIndirectJumpsHazardBit);
187 if (!Subtarget->useIndirectJumpsHazard())
188 Features.set(Feature_NoIndirectJumpGuardsBit);
189 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
190 Features.set(Feature_AllowFPOpFusionBit);
191 if (Subtarget->isFP64bit())
192 Features.set(Feature_IsFP64bitBit);
193 if (!Subtarget->isFP64bit())
194 Features.set(Feature_NotFP64bitBit);
195 if (!Subtarget->useSoftFloat())
196 Features.set(Feature_IsNotSoftFloatBit);
197 if (Subtarget->hasDSP())
198 Features.set(Feature_HasDSPBit);
199 if (Subtarget->hasDSPR2())
200 Features.set(Feature_HasDSPR2Bit);
201 return Features;
202}
203
204void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
205 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
206}
207PredicateBitset MipsInstructionSelector::
208computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
209 PredicateBitset Features{};
210 return Features;
211}
212
213// Feature bitsets.
214enum {
215 GIFBS_Invalid,
216 GIFBS_HasCnMips,
217 GIFBS_HasDSP,
218 GIFBS_HasDSPR2,
219 GIFBS_HasMSA,
220 GIFBS_InMicroMips,
221 GIFBS_InMips16Mode,
222 GIFBS_IsFP64bit,
223 GIFBS_NotFP64bit,
224 GIFBS_NotInMips16Mode,
225 GIFBS_HasDSP_InMicroMips,
226 GIFBS_HasDSP_NotInMicroMips,
227 GIFBS_HasDSPR2_InMicroMips,
228 GIFBS_HasMSA_HasStdEnc,
229 GIFBS_HasMSA_IsBE,
230 GIFBS_HasMSA_IsLE,
231 GIFBS_HasMips32r6_HasStdEnc,
232 GIFBS_HasMips32r6_InMicroMips,
233 GIFBS_HasMips64r2_HasStdEnc,
234 GIFBS_HasMips64r6_HasStdEnc,
235 GIFBS_HasStdEnc_IsNotSoftFloat,
236 GIFBS_HasStdEnc_NotInMicroMips,
237 GIFBS_HasStdEnc_NotMips4_32,
238 GIFBS_InMicroMips_IsFP64bit,
239 GIFBS_InMicroMips_IsNotSoftFloat,
240 GIFBS_InMicroMips_NotFP64bit,
241 GIFBS_InMicroMips_NotMips32r6,
242 GIFBS_IsGP64bit_NotInMips16Mode,
243 GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
244 GIFBS_HasMSA_HasMips64_HasStdEnc,
245 GIFBS_HasMips3_HasStdEnc_IsGP64bit,
246 GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
247 GIFBS_HasMips32r2_HasStdEnc_IsGP64bit,
248 GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
249 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
250 GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
251 GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
252 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
253 GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
254 GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
255 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
256 GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
257 GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
258 GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
259 GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
260 GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
261 GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
262 GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
263 GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
264 GIFBS_InMicroMips_NotMips32r6_RelocPIC,
265 GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
266 GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
267 GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6,
268 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
269 GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
270 GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
271 GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
272 GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
273 GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
274 GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
275 GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
276 GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
277 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
278 GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6,
279 GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
280 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
281 GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
282 GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
283 GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
284 GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
285 GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
286 GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
287 GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
288 GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
289 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
290 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
291 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
292 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
293 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
294 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
295};
296constexpr static PredicateBitset FeatureBitsets[] {
297 {}, // GIFBS_Invalid
298 {Feature_HasCnMipsBit, },
299 {Feature_HasDSPBit, },
300 {Feature_HasDSPR2Bit, },
301 {Feature_HasMSABit, },
302 {Feature_InMicroMipsBit, },
303 {Feature_InMips16ModeBit, },
304 {Feature_IsFP64bitBit, },
305 {Feature_NotFP64bitBit, },
306 {Feature_NotInMips16ModeBit, },
307 {Feature_HasDSPBit, Feature_InMicroMipsBit, },
308 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
309 {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
310 {Feature_HasMSABit, Feature_HasStdEncBit, },
311 {Feature_HasMSABit, Feature_IsBEBit, },
312 {Feature_HasMSABit, Feature_IsLEBit, },
313 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
314 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
315 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
316 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
317 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
318 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
319 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
320 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
321 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
322 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
323 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
324 {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
325 {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
326 {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
327 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
328 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
329 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
330 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
331 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
332 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
333 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
334 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
335 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
336 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
337 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
338 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
339 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
340 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
341 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
342 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
343 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
344 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
345 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
346 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
347 {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
348 {Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
349 {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, },
350 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
351 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
352 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
353 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
354 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
355 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
356 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
357 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
358 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
359 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
360 {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
361 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
362 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
363 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
364 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
365 {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
366 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
367 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
368 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
369 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
370 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
371 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
372 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
373 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
374 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
375 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
376 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
377};
378
379// ComplexPattern predicates.
380enum {
381 GICP_Invalid,
382};
383// See constructor for table contents
384
385MipsInstructionSelector::ComplexMatcherMemFn
386MipsInstructionSelector::ComplexPredicateFns[] = {
387 nullptr, // GICP_Invalid
388};
389
390// PatFrag predicates.
391bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
392 const MachineFunction &MF = *MI.getParent()->getParent();
393 const MachineRegisterInfo &MRI = MF.getRegInfo();
394 const auto &Operands = State.RecordedOperands;
395 (void)Operands;
396 (void)MRI;
397 llvm_unreachable("Unknown predicate");
398 return false;
399}
400// PatFrag predicates.
401bool MipsInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
402 const auto &Operands = State.RecordedOperands;
403 Register Reg = MO.getReg();
404 (void)Operands;
405 (void)Reg;
406 llvm_unreachable("Unknown predicate");
407 return false;
408}
409// PatFrag predicates.
410enum {
411 GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1,
412 GICXXPred_I64_Predicate_immSExt6,
413 GICXXPred_I64_Predicate_immSExt10,
414 GICXXPred_I64_Predicate_immSExtAddiur2,
415 GICXXPred_I64_Predicate_immSExtAddius5,
416 GICXXPred_I64_Predicate_immZExt1,
417 GICXXPred_I64_Predicate_immZExt1Ptr,
418 GICXXPred_I64_Predicate_immZExt2,
419 GICXXPred_I64_Predicate_immZExt2Lsa,
420 GICXXPred_I64_Predicate_immZExt2Ptr,
421 GICXXPred_I64_Predicate_immZExt2Shift,
422 GICXXPred_I64_Predicate_immZExt3,
423 GICXXPred_I64_Predicate_immZExt3Ptr,
424 GICXXPred_I64_Predicate_immZExt4,
425 GICXXPred_I64_Predicate_immZExt4Ptr,
426 GICXXPred_I64_Predicate_immZExt5,
427 GICXXPred_I64_Predicate_immZExt5_64,
428 GICXXPred_I64_Predicate_immZExt6,
429 GICXXPred_I64_Predicate_immZExt8,
430 GICXXPred_I64_Predicate_immZExt10,
431 GICXXPred_I64_Predicate_immZExtAndi16,
432 GICXXPred_I64_Predicate_immi32Cst7,
433 GICXXPred_I64_Predicate_immi32Cst15,
434 GICXXPred_I64_Predicate_immi32Cst31,
435 GICXXPred_I64_Predicate_timmSExt6,
436 GICXXPred_I64_Predicate_timmZExt1,
437 GICXXPred_I64_Predicate_timmZExt1Ptr,
438 GICXXPred_I64_Predicate_timmZExt2,
439 GICXXPred_I64_Predicate_timmZExt2Ptr,
440 GICXXPred_I64_Predicate_timmZExt3,
441 GICXXPred_I64_Predicate_timmZExt3Ptr,
442 GICXXPred_I64_Predicate_timmZExt4,
443 GICXXPred_I64_Predicate_timmZExt4Ptr,
444 GICXXPred_I64_Predicate_timmZExt5,
445 GICXXPred_I64_Predicate_timmZExt6,
446 GICXXPred_I64_Predicate_timmZExt8,
447 GICXXPred_I64_Predicate_timmZExt10,
448};
449bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
450 switch (PredicateID) {
451 case GICXXPred_I64_Predicate_immLi16: {
452 return Imm >= -1 && Imm <= 126;
453 }
454 case GICXXPred_I64_Predicate_immSExt6: {
455 return isInt<6>(Imm);
456 }
457 case GICXXPred_I64_Predicate_immSExt10: {
458 return isInt<10>(Imm);
459 }
460 case GICXXPred_I64_Predicate_immSExtAddiur2: {
461 return Imm == 1 || Imm == -1 ||
462 ((Imm % 4 == 0) &&
463 Imm < 28 && Imm > 0);
464 }
465 case GICXXPred_I64_Predicate_immSExtAddius5: {
466 return Imm >= -8 && Imm <= 7;
467 }
468 case GICXXPred_I64_Predicate_immZExt1: {
469 return isUInt<1>(Imm);
470 }
471 case GICXXPred_I64_Predicate_immZExt1Ptr: {
472 return isUInt<1>(Imm);
473 }
474 case GICXXPred_I64_Predicate_immZExt2: {
475 return isUInt<2>(Imm);
476 }
477 case GICXXPred_I64_Predicate_immZExt2Lsa: {
478 return isUInt<2>(Imm - 1);
479 }
480 case GICXXPred_I64_Predicate_immZExt2Ptr: {
481 return isUInt<2>(Imm);
482 }
483 case GICXXPred_I64_Predicate_immZExt2Shift: {
484 return Imm >= 1 && Imm <= 8;
485 }
486 case GICXXPred_I64_Predicate_immZExt3: {
487 return isUInt<3>(Imm);
488 }
489 case GICXXPred_I64_Predicate_immZExt3Ptr: {
490 return isUInt<3>(Imm);
491 }
492 case GICXXPred_I64_Predicate_immZExt4: {
493 return isUInt<4>(Imm);
494 }
495 case GICXXPred_I64_Predicate_immZExt4Ptr: {
496 return isUInt<4>(Imm);
497 }
498 case GICXXPred_I64_Predicate_immZExt5: {
499 return Imm == (Imm & 0x1f);
500 }
501 case GICXXPred_I64_Predicate_immZExt5_64: {
502 return Imm == (Imm & 0x1f);
503 }
504 case GICXXPred_I64_Predicate_immZExt6: {
505 return Imm == (Imm & 0x3f);
506 }
507 case GICXXPred_I64_Predicate_immZExt8: {
508 return isUInt<8>(Imm);
509 }
510 case GICXXPred_I64_Predicate_immZExt10: {
511 return isUInt<10>(Imm);
512 }
513 case GICXXPred_I64_Predicate_immZExtAndi16: {
514 return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
515 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
516 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
517 }
518 case GICXXPred_I64_Predicate_immi32Cst7: {
519 return isUInt<32>(Imm) && Imm == 7;
520 }
521 case GICXXPred_I64_Predicate_immi32Cst15: {
522 return isUInt<32>(Imm) && Imm == 15;
523 }
524 case GICXXPred_I64_Predicate_immi32Cst31: {
525 return isUInt<32>(Imm) && Imm == 31;
526 }
527 case GICXXPred_I64_Predicate_timmSExt6: {
528 return isInt<6>(Imm);
529 }
530 case GICXXPred_I64_Predicate_timmZExt1: {
531 return isUInt<1>(Imm);
532 }
533 case GICXXPred_I64_Predicate_timmZExt1Ptr: {
534 return isUInt<1>(Imm);
535 }
536 case GICXXPred_I64_Predicate_timmZExt2: {
537 return isUInt<2>(Imm);
538 }
539 case GICXXPred_I64_Predicate_timmZExt2Ptr: {
540 return isUInt<2>(Imm);
541 }
542 case GICXXPred_I64_Predicate_timmZExt3: {
543 return isUInt<3>(Imm);
544 }
545 case GICXXPred_I64_Predicate_timmZExt3Ptr: {
546 return isUInt<3>(Imm);
547 }
548 case GICXXPred_I64_Predicate_timmZExt4: {
549 return isUInt<4>(Imm);
550 }
551 case GICXXPred_I64_Predicate_timmZExt4Ptr: {
552 return isUInt<4>(Imm);
553 }
554 case GICXXPred_I64_Predicate_timmZExt5: {
555 return Imm == (Imm & 0x1f);
556 }
557 case GICXXPred_I64_Predicate_timmZExt6: {
558 return Imm == (Imm & 0x3f);
559 }
560 case GICXXPred_I64_Predicate_timmZExt8: {
561 return isUInt<8>(Imm);
562 }
563 case GICXXPred_I64_Predicate_timmZExt10: {
564 return isUInt<10>(Imm);
565 }
566 }
567 llvm_unreachable("Unknown predicate");
568 return false;
569}
570// PatFrag predicates.
571bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
572 llvm_unreachable("Unknown predicate");
573 return false;
574}
575// PatFrag predicates.
576enum {
577 GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
578 GICXXPred_APInt_Predicate_imm32ZExt16,
579};
580bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
581 switch (PredicateID) {
582 case GICXXPred_APInt_Predicate_imm32SExt16: {
583 return isInt<16>(Imm.getSExtValue());
584 }
585 case GICXXPred_APInt_Predicate_imm32ZExt16: {
586
587 return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
588
589 }
590 }
591 llvm_unreachable("Unknown predicate");
592 return false;
593}
594bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
595 llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
596 return false;
597}
598// Custom renderers.
599enum {
600 GICR_Invalid,
601};
602MipsInstructionSelector::CustomRendererFn
603MipsInstructionSelector::CustomRenderers[] = {
604 nullptr, // GICR_Invalid
605};
606
607bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
608 const PredicateBitset AvailableFeatures = getAvailableFeatures();
609 MachineIRBuilder B(I);
610 State.MIs.clear();
611 State.MIs.push_back(&I);
612
613 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
614 return true;
615 }
616
617 return false;
618}
619
620bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
621 llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
622}
623#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
624#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8)
625#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24)
626#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56)
627#else
628#define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val)
629#define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val)
630#define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val)
631#endif
632const uint8_t *MipsInstructionSelector::getMatchTable() const {
633 constexpr static uint8_t MatchTable0[] = {
634 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(53), GIMT_Encode2(289), /*)*//*default:*//*Label 79*/ GIMT_Encode4(69777),
635 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(954),
636 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(2252),
637 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(2943),
638 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(3424),
639 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(3693),
640 /* 30 */ /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(3962),
641 /* 34 */ /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(4231), GIMT_Encode4(0), GIMT_Encode4(0),
642 /* 46 */ /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(4500),
643 /* 50 */ /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5056),
644 /* 54 */ /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(5460), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
645 /* 102 */ /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ GIMT_Encode4(6352),
646 /* 106 */ /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ GIMT_Encode4(6425), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
647 /* 126 */ /*TargetOpcode::G_BITCAST*//*Label 12*/ GIMT_Encode4(6766), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
648 /* 170 */ /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(11077),
649 /* 174 */ /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(11142),
650 /* 178 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(11210), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
651 /* 206 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 16*/ GIMT_Encode4(11278),
652 /* 210 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 17*/ GIMT_Encode4(11470),
653 /* 214 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 18*/ GIMT_Encode4(11640),
654 /* 218 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 19*/ GIMT_Encode4(11810),
655 /* 222 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 20*/ GIMT_Encode4(11980),
656 /* 226 */ /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 21*/ GIMT_Encode4(12150),
657 /* 230 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 22*/ GIMT_Encode4(12320),
658 /* 234 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 23*/ GIMT_Encode4(12490),
659 /* 238 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 24*/ GIMT_Encode4(12660),
660 /* 242 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 25*/ GIMT_Encode4(12830),
661 /* 246 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 26*/ GIMT_Encode4(13000),
662 /* 250 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 27*/ GIMT_Encode4(13170), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
663 /* 302 */ /*TargetOpcode::G_BRCOND*//*Label 28*/ GIMT_Encode4(13340), GIMT_Encode4(0), GIMT_Encode4(0),
664 /* 314 */ /*TargetOpcode::G_INTRINSIC*//*Label 29*/ GIMT_Encode4(18061),
665 /* 318 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 30*/ GIMT_Encode4(32326), GIMT_Encode4(0), GIMT_Encode4(0),
666 /* 330 */ /*TargetOpcode::G_ANYEXT*//*Label 31*/ GIMT_Encode4(37420),
667 /* 334 */ /*TargetOpcode::G_TRUNC*//*Label 32*/ GIMT_Encode4(37486),
668 /* 338 */ /*TargetOpcode::G_CONSTANT*//*Label 33*/ GIMT_Encode4(37550), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
669 /* 354 */ /*TargetOpcode::G_SEXT*//*Label 34*/ GIMT_Encode4(37611),
670 /* 358 */ /*TargetOpcode::G_SEXT_INREG*//*Label 35*/ GIMT_Encode4(39075),
671 /* 362 */ /*TargetOpcode::G_ZEXT*//*Label 36*/ GIMT_Encode4(39423),
672 /* 366 */ /*TargetOpcode::G_SHL*//*Label 37*/ GIMT_Encode4(39624),
673 /* 370 */ /*TargetOpcode::G_LSHR*//*Label 38*/ GIMT_Encode4(41421),
674 /* 374 */ /*TargetOpcode::G_ASHR*//*Label 39*/ GIMT_Encode4(43218), GIMT_Encode4(0), GIMT_Encode4(0),
675 /* 386 */ /*TargetOpcode::G_ROTR*//*Label 40*/ GIMT_Encode4(44973), GIMT_Encode4(0),
676 /* 394 */ /*TargetOpcode::G_ICMP*//*Label 41*/ GIMT_Encode4(45261),
677 /* 398 */ /*TargetOpcode::G_FCMP*//*Label 42*/ GIMT_Encode4(47792), GIMT_Encode4(0), GIMT_Encode4(0),
678 /* 410 */ /*TargetOpcode::G_SELECT*//*Label 43*/ GIMT_Encode4(49498), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
679 /* 454 */ /*TargetOpcode::G_UMULH*//*Label 44*/ GIMT_Encode4(61536),
680 /* 458 */ /*TargetOpcode::G_SMULH*//*Label 45*/ GIMT_Encode4(61645), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
681 /* 518 */ /*TargetOpcode::G_FADD*//*Label 46*/ GIMT_Encode4(61754),
682 /* 522 */ /*TargetOpcode::G_FSUB*//*Label 47*/ GIMT_Encode4(62667),
683 /* 526 */ /*TargetOpcode::G_FMUL*//*Label 48*/ GIMT_Encode4(63279),
684 /* 530 */ /*TargetOpcode::G_FMA*//*Label 49*/ GIMT_Encode4(63766), GIMT_Encode4(0),
685 /* 538 */ /*TargetOpcode::G_FDIV*//*Label 50*/ GIMT_Encode4(63872), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
686 /* 558 */ /*TargetOpcode::G_FEXP2*//*Label 51*/ GIMT_Encode4(64171), GIMT_Encode4(0), GIMT_Encode4(0),
687 /* 570 */ /*TargetOpcode::G_FLOG2*//*Label 52*/ GIMT_Encode4(64249), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
688 /* 586 */ /*TargetOpcode::G_FNEG*//*Label 53*/ GIMT_Encode4(64327),
689 /* 590 */ /*TargetOpcode::G_FPEXT*//*Label 54*/ GIMT_Encode4(65696),
690 /* 594 */ /*TargetOpcode::G_FPTRUNC*//*Label 55*/ GIMT_Encode4(65874),
691 /* 598 */ /*TargetOpcode::G_FPTOSI*//*Label 56*/ GIMT_Encode4(66037),
692 /* 602 */ /*TargetOpcode::G_FPTOUI*//*Label 57*/ GIMT_Encode4(66115),
693 /* 606 */ /*TargetOpcode::G_SITOFP*//*Label 58*/ GIMT_Encode4(66193),
694 /* 610 */ /*TargetOpcode::G_UITOFP*//*Label 59*/ GIMT_Encode4(66446), GIMT_Encode4(0), GIMT_Encode4(0),
695 /* 622 */ /*TargetOpcode::G_FABS*//*Label 60*/ GIMT_Encode4(66524), GIMT_Encode4(0), GIMT_Encode4(0),
696 /* 634 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 61*/ GIMT_Encode4(66764),
697 /* 638 */ /*TargetOpcode::G_FMINNUM*//*Label 62*/ GIMT_Encode4(66838),
698 /* 642 */ /*TargetOpcode::G_FMAXNUM*//*Label 63*/ GIMT_Encode4(66910),
699 /* 646 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 64*/ GIMT_Encode4(66982),
700 /* 650 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 65*/ GIMT_Encode4(67054), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
701 /* 702 */ /*TargetOpcode::G_SMIN*//*Label 66*/ GIMT_Encode4(67126),
702 /* 706 */ /*TargetOpcode::G_SMAX*//*Label 67*/ GIMT_Encode4(67294),
703 /* 710 */ /*TargetOpcode::G_UMIN*//*Label 68*/ GIMT_Encode4(67462),
704 /* 714 */ /*TargetOpcode::G_UMAX*//*Label 69*/ GIMT_Encode4(67630), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
705 /* 730 */ /*TargetOpcode::G_BR*//*Label 70*/ GIMT_Encode4(67798), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
706 /* 750 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 71*/ GIMT_Encode4(67922),
707 /* 754 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 72*/ GIMT_Encode4(68486), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
708 /* 782 */ /*TargetOpcode::G_CTLZ*//*Label 73*/ GIMT_Encode4(68538), GIMT_Encode4(0),
709 /* 790 */ /*TargetOpcode::G_CTPOP*//*Label 74*/ GIMT_Encode4(69043),
710 /* 794 */ /*TargetOpcode::G_BSWAP*//*Label 75*/ GIMT_Encode4(69249), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
711 /* 850 */ /*TargetOpcode::G_FSQRT*//*Label 76*/ GIMT_Encode4(69413), GIMT_Encode4(0),
712 /* 858 */ /*TargetOpcode::G_FRINT*//*Label 77*/ GIMT_Encode4(69653), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
713 /* 950 */ /*TargetOpcode::G_TRAP*//*Label 78*/ GIMT_Encode4(69731),
714 /* 954 */ // Label 0: @954
715 /* 954 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 88*/ GIMT_Encode4(2251),
716 /* 965 */ /*GILLT_s32*//*Label 80*/ GIMT_Encode4(997),
717 /* 969 */ /*GILLT_s64*//*Label 81*/ GIMT_Encode4(1405),
718 /* 973 */ /*GILLT_v2s16*//*Label 82*/ GIMT_Encode4(1571),
719 /* 977 */ /*GILLT_v2s64*//*Label 83*/ GIMT_Encode4(1603),
720 /* 981 */ /*GILLT_v4s8*//*Label 84*/ GIMT_Encode4(1757),
721 /* 985 */ /*GILLT_v4s32*//*Label 85*/ GIMT_Encode4(1789),
722 /* 989 */ /*GILLT_v8s16*//*Label 86*/ GIMT_Encode4(1943),
723 /* 993 */ /*GILLT_v16s8*//*Label 87*/ GIMT_Encode4(2097),
724 /* 997 */ // Label 80: @997
725 /* 997 */ GIM_Try, /*On fail goto*//*Label 89*/ GIMT_Encode4(1404),
726 /* 1002 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
727 /* 1005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
728 /* 1008 */ GIM_Try, /*On fail goto*//*Label 90*/ GIMT_Encode4(1075), // Rule ID 2400 //
729 /* 1013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
730 /* 1016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
731 /* 1020 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
732 /* 1024 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
733 /* 1028 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
734 /* 1032 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
735 /* 1036 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
736 /* 1041 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
737 /* 1045 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
738 /* 1049 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
739 /* 1053 */ // MIs[2] Operand 1
740 /* 1053 */ // No operand predicates
741 /* 1053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
742 /* 1057 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
743 /* 1059 */ // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
744 /* 1059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
745 /* 1062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
746 /* 1064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
747 /* 1068 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
748 /* 1070 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
749 /* 1073 */ GIR_RootConstrainSelectedInstOperands,
750 /* 1074 */ // GIR_Coverage, 2400,
751 /* 1074 */ GIR_EraseRootFromParent_Done,
752 /* 1075 */ // Label 90: @1075
753 /* 1075 */ GIM_Try, /*On fail goto*//*Label 91*/ GIMT_Encode4(1142), // Rule ID 834 //
754 /* 1080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
755 /* 1083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
756 /* 1087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
757 /* 1091 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
758 /* 1095 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
759 /* 1099 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
760 /* 1103 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
761 /* 1107 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
762 /* 1112 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
763 /* 1116 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
764 /* 1120 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
765 /* 1124 */ // MIs[2] Operand 1
766 /* 1124 */ // No operand predicates
767 /* 1124 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
768 /* 1126 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
769 /* 1126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
770 /* 1129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
771 /* 1131 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
772 /* 1135 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
773 /* 1137 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
774 /* 1140 */ GIR_RootConstrainSelectedInstOperands,
775 /* 1141 */ // GIR_Coverage, 834,
776 /* 1141 */ GIR_EraseRootFromParent_Done,
777 /* 1142 */ // Label 91: @1142
778 /* 1142 */ GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(1184), // Rule ID 40 //
779 /* 1147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
780 /* 1150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
781 /* 1154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
782 /* 1158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
783 /* 1162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
784 /* 1166 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
785 /* 1170 */ // MIs[1] Operand 1
786 /* 1170 */ // No operand predicates
787 /* 1170 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
788 /* 1172 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
789 /* 1172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDiu),
790 /* 1175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
791 /* 1177 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
792 /* 1179 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
793 /* 1182 */ GIR_RootConstrainSelectedInstOperands,
794 /* 1183 */ // GIR_Coverage, 40,
795 /* 1183 */ GIR_EraseRootFromParent_Done,
796 /* 1184 */ // Label 92: @1184
797 /* 1184 */ GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1226), // Rule ID 2169 //
798 /* 1189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
799 /* 1192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
800 /* 1196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
801 /* 1200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
802 /* 1204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
803 /* 1208 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
804 /* 1212 */ // MIs[1] Operand 1
805 /* 1212 */ // No operand predicates
806 /* 1212 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
807 /* 1214 */ // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
808 /* 1214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUR2_MM),
809 /* 1217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
810 /* 1219 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
811 /* 1221 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
812 /* 1224 */ GIR_RootConstrainSelectedInstOperands,
813 /* 1225 */ // GIR_Coverage, 2169,
814 /* 1225 */ GIR_EraseRootFromParent_Done,
815 /* 1226 */ // Label 93: @1226
816 /* 1226 */ GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1268), // Rule ID 2170 //
817 /* 1231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
818 /* 1234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
819 /* 1238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
820 /* 1242 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
821 /* 1246 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
822 /* 1250 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
823 /* 1254 */ // MIs[1] Operand 1
824 /* 1254 */ // No operand predicates
825 /* 1254 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
826 /* 1256 */ // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
827 /* 1256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUS5_MM),
828 /* 1259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
829 /* 1261 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
830 /* 1263 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
831 /* 1266 */ GIR_RootConstrainSelectedInstOperands,
832 /* 1267 */ // GIR_Coverage, 2170,
833 /* 1267 */ GIR_EraseRootFromParent_Done,
834 /* 1268 */ // Label 94: @1268
835 /* 1268 */ GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1295), // Rule ID 1208 //
836 /* 1273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
837 /* 1276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
838 /* 1280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
839 /* 1284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
840 /* 1288 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
841 /* 1288 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MMR6),
842 /* 1293 */ GIR_RootConstrainSelectedInstOperands,
843 /* 1294 */ // GIR_Coverage, 1208,
844 /* 1294 */ GIR_Done,
845 /* 1295 */ // Label 95: @1295
846 /* 1295 */ GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1322), // Rule ID 46 //
847 /* 1300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
848 /* 1303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
849 /* 1307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
850 /* 1311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
851 /* 1315 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
852 /* 1315 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu),
853 /* 1320 */ GIR_RootConstrainSelectedInstOperands,
854 /* 1321 */ // GIR_Coverage, 46,
855 /* 1321 */ GIR_Done,
856 /* 1322 */ // Label 96: @1322
857 /* 1322 */ GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1349), // Rule ID 1060 //
858 /* 1327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
859 /* 1330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
860 /* 1334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
861 /* 1338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
862 /* 1342 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
863 /* 1342 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MM),
864 /* 1347 */ GIR_RootConstrainSelectedInstOperands,
865 /* 1348 */ // GIR_Coverage, 1060,
866 /* 1348 */ GIR_Done,
867 /* 1349 */ // Label 97: @1349
868 /* 1349 */ GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1376), // Rule ID 1072 //
869 /* 1354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
870 /* 1357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
871 /* 1361 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
872 /* 1365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
873 /* 1369 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
874 /* 1369 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu_MM),
875 /* 1374 */ GIR_RootConstrainSelectedInstOperands,
876 /* 1375 */ // GIR_Coverage, 1072,
877 /* 1375 */ GIR_Done,
878 /* 1376 */ // Label 98: @1376
879 /* 1376 */ GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(1403), // Rule ID 1827 //
880 /* 1381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
881 /* 1384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
882 /* 1388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
883 /* 1392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
884 /* 1396 */ // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
885 /* 1396 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AdduRxRyRz16),
886 /* 1401 */ GIR_RootConstrainSelectedInstOperands,
887 /* 1402 */ // GIR_Coverage, 1827,
888 /* 1402 */ GIR_Done,
889 /* 1403 */ // Label 99: @1403
890 /* 1403 */ GIM_Reject,
891 /* 1404 */ // Label 89: @1404
892 /* 1404 */ GIM_Reject,
893 /* 1405 */ // Label 81: @1405
894 /* 1405 */ GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1570),
895 /* 1410 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
896 /* 1413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
897 /* 1416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
898 /* 1420 */ GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(1483), // Rule ID 2401 //
899 /* 1425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
900 /* 1428 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
901 /* 1432 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
902 /* 1436 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
903 /* 1440 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
904 /* 1444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
905 /* 1449 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
906 /* 1453 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
907 /* 1457 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
908 /* 1461 */ // MIs[2] Operand 1
909 /* 1461 */ // No operand predicates
910 /* 1461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
911 /* 1465 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
912 /* 1467 */ // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
913 /* 1467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
914 /* 1470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
915 /* 1472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
916 /* 1476 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
917 /* 1478 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
918 /* 1481 */ GIR_RootConstrainSelectedInstOperands,
919 /* 1482 */ // GIR_Coverage, 2401,
920 /* 1482 */ GIR_EraseRootFromParent_Done,
921 /* 1483 */ // Label 101: @1483
922 /* 1483 */ GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(1546), // Rule ID 835 //
923 /* 1488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
924 /* 1491 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
925 /* 1495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
926 /* 1499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
927 /* 1503 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
928 /* 1507 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
929 /* 1511 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
930 /* 1516 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
931 /* 1520 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
932 /* 1524 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
933 /* 1528 */ // MIs[2] Operand 1
934 /* 1528 */ // No operand predicates
935 /* 1528 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
936 /* 1530 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
937 /* 1530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
938 /* 1533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
939 /* 1535 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
940 /* 1539 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
941 /* 1541 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
942 /* 1544 */ GIR_RootConstrainSelectedInstOperands,
943 /* 1545 */ // GIR_Coverage, 835,
944 /* 1545 */ GIR_EraseRootFromParent_Done,
945 /* 1546 */ // Label 102: @1546
946 /* 1546 */ GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(1569), // Rule ID 202 //
947 /* 1551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
948 /* 1554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
949 /* 1558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
950 /* 1562 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
951 /* 1562 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DADDu),
952 /* 1567 */ GIR_RootConstrainSelectedInstOperands,
953 /* 1568 */ // GIR_Coverage, 202,
954 /* 1568 */ GIR_Done,
955 /* 1569 */ // Label 103: @1569
956 /* 1569 */ GIM_Reject,
957 /* 1570 */ // Label 100: @1570
958 /* 1570 */ GIM_Reject,
959 /* 1571 */ // Label 82: @1571
960 /* 1571 */ GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(1602), // Rule ID 1926 //
961 /* 1576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
962 /* 1579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
963 /* 1582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
964 /* 1585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
965 /* 1589 */ // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
966 /* 1589 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
967 /* 1594 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
968 /* 1600 */ GIR_RootConstrainSelectedInstOperands,
969 /* 1601 */ // GIR_Coverage, 1926,
970 /* 1601 */ GIR_Done,
971 /* 1602 */ // Label 104: @1602
972 /* 1602 */ GIM_Reject,
973 /* 1603 */ // Label 83: @1603
974 /* 1603 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(1756),
975 /* 1608 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
976 /* 1611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
977 /* 1614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
978 /* 1618 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1675), // Rule ID 2405 //
979 /* 1623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
980 /* 1626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
981 /* 1630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
982 /* 1634 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
983 /* 1638 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
984 /* 1642 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
985 /* 1647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
986 /* 1652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
987 /* 1656 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
988 /* 1658 */ // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
989 /* 1658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
990 /* 1661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
991 /* 1663 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
992 /* 1665 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
993 /* 1669 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
994 /* 1673 */ GIR_RootConstrainSelectedInstOperands,
995 /* 1674 */ // GIR_Coverage, 2405,
996 /* 1674 */ GIR_EraseRootFromParent_Done,
997 /* 1675 */ // Label 106: @1675
998 /* 1675 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1732), // Rule ID 843 //
999 /* 1680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1000 /* 1683 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1001 /* 1687 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1002 /* 1691 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1003 /* 1695 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1004 /* 1699 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1005 /* 1703 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1006 /* 1708 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1007 /* 1713 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1008 /* 1715 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1009 /* 1715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1010 /* 1718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1011 /* 1720 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1012 /* 1722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1013 /* 1726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1014 /* 1730 */ GIR_RootConstrainSelectedInstOperands,
1015 /* 1731 */ // GIR_Coverage, 843,
1016 /* 1731 */ GIR_EraseRootFromParent_Done,
1017 /* 1732 */ // Label 107: @1732
1018 /* 1732 */ GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(1755), // Rule ID 510 //
1019 /* 1737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1020 /* 1740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1021 /* 1744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1022 /* 1748 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1023 /* 1748 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_D),
1024 /* 1753 */ GIR_RootConstrainSelectedInstOperands,
1025 /* 1754 */ // GIR_Coverage, 510,
1026 /* 1754 */ GIR_Done,
1027 /* 1755 */ // Label 108: @1755
1028 /* 1755 */ GIM_Reject,
1029 /* 1756 */ // Label 105: @1756
1030 /* 1756 */ GIM_Reject,
1031 /* 1757 */ // Label 84: @1757
1032 /* 1757 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1788), // Rule ID 1932 //
1033 /* 1762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1034 /* 1765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1035 /* 1768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1036 /* 1771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1037 /* 1775 */ // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1038 /* 1775 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
1039 /* 1780 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
1040 /* 1786 */ GIR_RootConstrainSelectedInstOperands,
1041 /* 1787 */ // GIR_Coverage, 1932,
1042 /* 1787 */ GIR_Done,
1043 /* 1788 */ // Label 109: @1788
1044 /* 1788 */ GIM_Reject,
1045 /* 1789 */ // Label 85: @1789
1046 /* 1789 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1942),
1047 /* 1794 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1048 /* 1797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1049 /* 1800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1050 /* 1804 */ GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(1861), // Rule ID 2404 //
1051 /* 1809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1052 /* 1812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1053 /* 1816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1054 /* 1820 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1055 /* 1824 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1056 /* 1828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1057 /* 1833 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1058 /* 1838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1059 /* 1842 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1060 /* 1844 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1061 /* 1844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1062 /* 1847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1063 /* 1849 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1064 /* 1851 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1065 /* 1855 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1066 /* 1859 */ GIR_RootConstrainSelectedInstOperands,
1067 /* 1860 */ // GIR_Coverage, 2404,
1068 /* 1860 */ GIR_EraseRootFromParent_Done,
1069 /* 1861 */ // Label 111: @1861
1070 /* 1861 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1918), // Rule ID 842 //
1071 /* 1866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1072 /* 1869 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1073 /* 1873 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1074 /* 1877 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1075 /* 1881 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1076 /* 1885 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1077 /* 1889 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1078 /* 1894 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1079 /* 1899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1080 /* 1901 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1081 /* 1901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1082 /* 1904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1083 /* 1906 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1084 /* 1908 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1085 /* 1912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1086 /* 1916 */ GIR_RootConstrainSelectedInstOperands,
1087 /* 1917 */ // GIR_Coverage, 842,
1088 /* 1917 */ GIR_EraseRootFromParent_Done,
1089 /* 1918 */ // Label 112: @1918
1090 /* 1918 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(1941), // Rule ID 509 //
1091 /* 1923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1092 /* 1926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1093 /* 1930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1094 /* 1934 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1095 /* 1934 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_W),
1096 /* 1939 */ GIR_RootConstrainSelectedInstOperands,
1097 /* 1940 */ // GIR_Coverage, 509,
1098 /* 1940 */ GIR_Done,
1099 /* 1941 */ // Label 113: @1941
1100 /* 1941 */ GIM_Reject,
1101 /* 1942 */ // Label 110: @1942
1102 /* 1942 */ GIM_Reject,
1103 /* 1943 */ // Label 86: @1943
1104 /* 1943 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(2096),
1105 /* 1948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1106 /* 1951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1107 /* 1954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1108 /* 1958 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(2015), // Rule ID 2403 //
1109 /* 1963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1110 /* 1966 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1111 /* 1970 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1112 /* 1974 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1113 /* 1978 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1114 /* 1982 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1115 /* 1987 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1116 /* 1992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1117 /* 1996 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1118 /* 1998 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1119 /* 1998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1120 /* 2001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1121 /* 2003 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1122 /* 2005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1123 /* 2009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1124 /* 2013 */ GIR_RootConstrainSelectedInstOperands,
1125 /* 2014 */ // GIR_Coverage, 2403,
1126 /* 2014 */ GIR_EraseRootFromParent_Done,
1127 /* 2015 */ // Label 115: @2015
1128 /* 2015 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(2072), // Rule ID 841 //
1129 /* 2020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1130 /* 2023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1131 /* 2027 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1132 /* 2031 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1133 /* 2035 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1134 /* 2039 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1135 /* 2043 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1136 /* 2048 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1137 /* 2053 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1138 /* 2055 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1139 /* 2055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1140 /* 2058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1141 /* 2060 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1142 /* 2062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1143 /* 2066 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1144 /* 2070 */ GIR_RootConstrainSelectedInstOperands,
1145 /* 2071 */ // GIR_Coverage, 841,
1146 /* 2071 */ GIR_EraseRootFromParent_Done,
1147 /* 2072 */ // Label 116: @2072
1148 /* 2072 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(2095), // Rule ID 508 //
1149 /* 2077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1150 /* 2080 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1151 /* 2084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1152 /* 2088 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1153 /* 2088 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_H),
1154 /* 2093 */ GIR_RootConstrainSelectedInstOperands,
1155 /* 2094 */ // GIR_Coverage, 508,
1156 /* 2094 */ GIR_Done,
1157 /* 2095 */ // Label 117: @2095
1158 /* 2095 */ GIM_Reject,
1159 /* 2096 */ // Label 114: @2096
1160 /* 2096 */ GIM_Reject,
1161 /* 2097 */ // Label 87: @2097
1162 /* 2097 */ GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(2250),
1163 /* 2102 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1164 /* 2105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1165 /* 2108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1166 /* 2112 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2169), // Rule ID 2402 //
1167 /* 2117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1168 /* 2120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1169 /* 2124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1170 /* 2128 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1171 /* 2132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1172 /* 2136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1173 /* 2141 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1174 /* 2146 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1175 /* 2150 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1176 /* 2152 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1177 /* 2152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1178 /* 2155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1179 /* 2157 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1180 /* 2159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1181 /* 2163 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1182 /* 2167 */ GIR_RootConstrainSelectedInstOperands,
1183 /* 2168 */ // GIR_Coverage, 2402,
1184 /* 2168 */ GIR_EraseRootFromParent_Done,
1185 /* 2169 */ // Label 119: @2169
1186 /* 2169 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2226), // Rule ID 840 //
1187 /* 2174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1188 /* 2177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1189 /* 2181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1190 /* 2185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1191 /* 2189 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1192 /* 2193 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1193 /* 2197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1194 /* 2202 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1195 /* 2207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1196 /* 2209 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1197 /* 2209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1198 /* 2212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1199 /* 2214 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1200 /* 2216 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1201 /* 2220 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1202 /* 2224 */ GIR_RootConstrainSelectedInstOperands,
1203 /* 2225 */ // GIR_Coverage, 840,
1204 /* 2225 */ GIR_EraseRootFromParent_Done,
1205 /* 2226 */ // Label 120: @2226
1206 /* 2226 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2249), // Rule ID 507 //
1207 /* 2231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1208 /* 2234 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1209 /* 2238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1210 /* 2242 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1211 /* 2242 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_B),
1212 /* 2247 */ GIR_RootConstrainSelectedInstOperands,
1213 /* 2248 */ // GIR_Coverage, 507,
1214 /* 2248 */ GIR_Done,
1215 /* 2249 */ // Label 121: @2249
1216 /* 2249 */ GIM_Reject,
1217 /* 2250 */ // Label 118: @2250
1218 /* 2250 */ GIM_Reject,
1219 /* 2251 */ // Label 88: @2251
1220 /* 2251 */ GIM_Reject,
1221 /* 2252 */ // Label 1: @2252
1222 /* 2252 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 130*/ GIMT_Encode4(2942),
1223 /* 2263 */ /*GILLT_s32*//*Label 122*/ GIMT_Encode4(2295),
1224 /* 2267 */ /*GILLT_s64*//*Label 123*/ GIMT_Encode4(2472),
1225 /* 2271 */ /*GILLT_v2s16*//*Label 124*/ GIMT_Encode4(2506),
1226 /* 2275 */ /*GILLT_v2s64*//*Label 125*/ GIMT_Encode4(2538),
1227 /* 2279 */ /*GILLT_v4s8*//*Label 126*/ GIMT_Encode4(2631),
1228 /* 2283 */ /*GILLT_v4s32*//*Label 127*/ GIMT_Encode4(2663),
1229 /* 2287 */ /*GILLT_v8s16*//*Label 128*/ GIMT_Encode4(2756),
1230 /* 2291 */ /*GILLT_v16s8*//*Label 129*/ GIMT_Encode4(2849),
1231 /* 2295 */ // Label 122: @2295
1232 /* 2295 */ GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(2471),
1233 /* 2300 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1234 /* 2303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1235 /* 2306 */ GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(2335), // Rule ID 1826 //
1236 /* 2311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1237 /* 2314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1238 /* 2318 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
1239 /* 2322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1240 /* 2326 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1241 /* 2326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NegRxRy16),
1242 /* 2329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
1243 /* 2331 */ GIR_RootToRootCopy, /*OpIdx*/2, // r
1244 /* 2333 */ GIR_RootConstrainSelectedInstOperands,
1245 /* 2334 */ // GIR_Coverage, 1826,
1246 /* 2334 */ GIR_EraseRootFromParent_Done,
1247 /* 2335 */ // Label 132: @2335
1248 /* 2335 */ GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(2362), // Rule ID 1210 //
1249 /* 2340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1250 /* 2343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1251 /* 2347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1252 /* 2351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1253 /* 2355 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1254 /* 2355 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MMR6),
1255 /* 2360 */ GIR_RootConstrainSelectedInstOperands,
1256 /* 2361 */ // GIR_Coverage, 1210,
1257 /* 2361 */ GIR_Done,
1258 /* 2362 */ // Label 133: @2362
1259 /* 2362 */ GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(2389), // Rule ID 47 //
1260 /* 2367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
1261 /* 2370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1262 /* 2374 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1263 /* 2378 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1264 /* 2382 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1265 /* 2382 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu),
1266 /* 2387 */ GIR_RootConstrainSelectedInstOperands,
1267 /* 2388 */ // GIR_Coverage, 47,
1268 /* 2388 */ GIR_Done,
1269 /* 2389 */ // Label 134: @2389
1270 /* 2389 */ GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(2416), // Rule ID 1064 //
1271 /* 2394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1272 /* 2397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1273 /* 2401 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1274 /* 2405 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1275 /* 2409 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1276 /* 2409 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MM),
1277 /* 2414 */ GIR_RootConstrainSelectedInstOperands,
1278 /* 2415 */ // GIR_Coverage, 1064,
1279 /* 2415 */ GIR_Done,
1280 /* 2416 */ // Label 135: @2416
1281 /* 2416 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(2443), // Rule ID 1073 //
1282 /* 2421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1283 /* 2424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1284 /* 2428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1285 /* 2432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1286 /* 2436 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1287 /* 2436 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu_MM),
1288 /* 2441 */ GIR_RootConstrainSelectedInstOperands,
1289 /* 2442 */ // GIR_Coverage, 1073,
1290 /* 2442 */ GIR_Done,
1291 /* 2443 */ // Label 136: @2443
1292 /* 2443 */ GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(2470), // Rule ID 1831 //
1293 /* 2448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1294 /* 2451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1295 /* 2455 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1296 /* 2459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1297 /* 2463 */ // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1298 /* 2463 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SubuRxRyRz16),
1299 /* 2468 */ GIR_RootConstrainSelectedInstOperands,
1300 /* 2469 */ // GIR_Coverage, 1831,
1301 /* 2469 */ GIR_Done,
1302 /* 2470 */ // Label 137: @2470
1303 /* 2470 */ GIM_Reject,
1304 /* 2471 */ // Label 131: @2471
1305 /* 2471 */ GIM_Reject,
1306 /* 2472 */ // Label 123: @2472
1307 /* 2472 */ GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(2505), // Rule ID 203 //
1308 /* 2477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
1309 /* 2480 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1310 /* 2483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1311 /* 2486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1312 /* 2490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1313 /* 2494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1314 /* 2498 */ // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1315 /* 2498 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSUBu),
1316 /* 2503 */ GIR_RootConstrainSelectedInstOperands,
1317 /* 2504 */ // GIR_Coverage, 203,
1318 /* 2504 */ GIR_Done,
1319 /* 2505 */ // Label 138: @2505
1320 /* 2505 */ GIM_Reject,
1321 /* 2506 */ // Label 124: @2506
1322 /* 2506 */ GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(2537), // Rule ID 1928 //
1323 /* 2511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1324 /* 2514 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1325 /* 2517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1326 /* 2520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1327 /* 2524 */ // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1328 /* 2524 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
1329 /* 2529 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
1330 /* 2535 */ GIR_RootConstrainSelectedInstOperands,
1331 /* 2536 */ // GIR_Coverage, 1928,
1332 /* 2536 */ GIR_Done,
1333 /* 2537 */ // Label 139: @2537
1334 /* 2537 */ GIM_Reject,
1335 /* 2538 */ // Label 125: @2538
1336 /* 2538 */ GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(2630),
1337 /* 2543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1338 /* 2546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1339 /* 2549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1340 /* 2553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1341 /* 2557 */ GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(2610), // Rule ID 899 //
1342 /* 2562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1343 /* 2565 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1344 /* 2569 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1345 /* 2573 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1346 /* 2577 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1347 /* 2581 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1348 /* 2586 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1349 /* 2591 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1350 /* 2593 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1351 /* 2593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_D),
1352 /* 2596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1353 /* 2598 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1354 /* 2600 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1355 /* 2604 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1356 /* 2608 */ GIR_RootConstrainSelectedInstOperands,
1357 /* 2609 */ // GIR_Coverage, 899,
1358 /* 2609 */ GIR_EraseRootFromParent_Done,
1359 /* 2610 */ // Label 141: @2610
1360 /* 2610 */ GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(2629), // Rule ID 1028 //
1361 /* 2615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1362 /* 2618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1363 /* 2622 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1364 /* 2622 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_D),
1365 /* 2627 */ GIR_RootConstrainSelectedInstOperands,
1366 /* 2628 */ // GIR_Coverage, 1028,
1367 /* 2628 */ GIR_Done,
1368 /* 2629 */ // Label 142: @2629
1369 /* 2629 */ GIM_Reject,
1370 /* 2630 */ // Label 140: @2630
1371 /* 2630 */ GIM_Reject,
1372 /* 2631 */ // Label 126: @2631
1373 /* 2631 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(2662), // Rule ID 1934 //
1374 /* 2636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1375 /* 2639 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1376 /* 2642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1377 /* 2645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1378 /* 2649 */ // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1379 /* 2649 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
1380 /* 2654 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
1381 /* 2660 */ GIR_RootConstrainSelectedInstOperands,
1382 /* 2661 */ // GIR_Coverage, 1934,
1383 /* 2661 */ GIR_Done,
1384 /* 2662 */ // Label 143: @2662
1385 /* 2662 */ GIM_Reject,
1386 /* 2663 */ // Label 127: @2663
1387 /* 2663 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(2755),
1388 /* 2668 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1389 /* 2671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1390 /* 2674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1391 /* 2678 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1392 /* 2682 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(2735), // Rule ID 898 //
1393 /* 2687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1394 /* 2690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1395 /* 2694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1396 /* 2698 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1397 /* 2702 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1398 /* 2706 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1399 /* 2711 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1400 /* 2716 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1401 /* 2718 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1402 /* 2718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_W),
1403 /* 2721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1404 /* 2723 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1405 /* 2725 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1406 /* 2729 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1407 /* 2733 */ GIR_RootConstrainSelectedInstOperands,
1408 /* 2734 */ // GIR_Coverage, 898,
1409 /* 2734 */ GIR_EraseRootFromParent_Done,
1410 /* 2735 */ // Label 145: @2735
1411 /* 2735 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(2754), // Rule ID 1027 //
1412 /* 2740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1413 /* 2743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1414 /* 2747 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1415 /* 2747 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_W),
1416 /* 2752 */ GIR_RootConstrainSelectedInstOperands,
1417 /* 2753 */ // GIR_Coverage, 1027,
1418 /* 2753 */ GIR_Done,
1419 /* 2754 */ // Label 146: @2754
1420 /* 2754 */ GIM_Reject,
1421 /* 2755 */ // Label 144: @2755
1422 /* 2755 */ GIM_Reject,
1423 /* 2756 */ // Label 128: @2756
1424 /* 2756 */ GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(2848),
1425 /* 2761 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1426 /* 2764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1427 /* 2767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1428 /* 2771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1429 /* 2775 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(2828), // Rule ID 897 //
1430 /* 2780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1431 /* 2783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1432 /* 2787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1433 /* 2791 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1434 /* 2795 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1435 /* 2799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1436 /* 2804 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1437 /* 2809 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1438 /* 2811 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1439 /* 2811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_H),
1440 /* 2814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1441 /* 2816 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1442 /* 2818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1443 /* 2822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1444 /* 2826 */ GIR_RootConstrainSelectedInstOperands,
1445 /* 2827 */ // GIR_Coverage, 897,
1446 /* 2827 */ GIR_EraseRootFromParent_Done,
1447 /* 2828 */ // Label 148: @2828
1448 /* 2828 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(2847), // Rule ID 1026 //
1449 /* 2833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1450 /* 2836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1451 /* 2840 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1452 /* 2840 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_H),
1453 /* 2845 */ GIR_RootConstrainSelectedInstOperands,
1454 /* 2846 */ // GIR_Coverage, 1026,
1455 /* 2846 */ GIR_Done,
1456 /* 2847 */ // Label 149: @2847
1457 /* 2847 */ GIM_Reject,
1458 /* 2848 */ // Label 147: @2848
1459 /* 2848 */ GIM_Reject,
1460 /* 2849 */ // Label 129: @2849
1461 /* 2849 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(2941),
1462 /* 2854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1463 /* 2857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1464 /* 2860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1465 /* 2864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1466 /* 2868 */ GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(2921), // Rule ID 896 //
1467 /* 2873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1468 /* 2876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1469 /* 2880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1470 /* 2884 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1471 /* 2888 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1472 /* 2892 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1473 /* 2897 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1474 /* 2902 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1475 /* 2904 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1476 /* 2904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_B),
1477 /* 2907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1478 /* 2909 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1479 /* 2911 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1480 /* 2915 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1481 /* 2919 */ GIR_RootConstrainSelectedInstOperands,
1482 /* 2920 */ // GIR_Coverage, 896,
1483 /* 2920 */ GIR_EraseRootFromParent_Done,
1484 /* 2921 */ // Label 151: @2921
1485 /* 2921 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(2940), // Rule ID 1025 //
1486 /* 2926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1487 /* 2929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1488 /* 2933 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1489 /* 2933 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_B),
1490 /* 2938 */ GIR_RootConstrainSelectedInstOperands,
1491 /* 2939 */ // GIR_Coverage, 1025,
1492 /* 2939 */ GIR_Done,
1493 /* 2940 */ // Label 152: @2940
1494 /* 2940 */ GIM_Reject,
1495 /* 2941 */ // Label 150: @2941
1496 /* 2941 */ GIM_Reject,
1497 /* 2942 */ // Label 130: @2942
1498 /* 2942 */ GIM_Reject,
1499 /* 2943 */ // Label 2: @2943
1500 /* 2943 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 160*/ GIMT_Encode4(3423),
1501 /* 2954 */ /*GILLT_s32*//*Label 153*/ GIMT_Encode4(2986),
1502 /* 2958 */ /*GILLT_s64*//*Label 154*/ GIMT_Encode4(3170),
1503 /* 2962 */ /*GILLT_v2s16*//*Label 155*/ GIMT_Encode4(3255),
1504 /* 2966 */ /*GILLT_v2s64*//*Label 156*/ GIMT_Encode4(3287), GIMT_Encode4(0),
1505 /* 2974 */ /*GILLT_v4s32*//*Label 157*/ GIMT_Encode4(3321),
1506 /* 2978 */ /*GILLT_v8s16*//*Label 158*/ GIMT_Encode4(3355),
1507 /* 2982 */ /*GILLT_v16s8*//*Label 159*/ GIMT_Encode4(3389),
1508 /* 2986 */ // Label 153: @2986
1509 /* 2986 */ GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(3169),
1510 /* 2991 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1511 /* 2994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1512 /* 2997 */ GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(3036), // Rule ID 48 //
1513 /* 3002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
1514 /* 3005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1515 /* 3009 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1516 /* 3013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1517 /* 3017 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1518 /* 3017 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL),
1519 /* 3022 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
1520 /* 3028 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
1521 /* 3034 */ GIR_RootConstrainSelectedInstOperands,
1522 /* 3035 */ // GIR_Coverage, 48,
1523 /* 3035 */ GIR_Done,
1524 /* 3036 */ // Label 162: @3036
1525 /* 3036 */ GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(3063), // Rule ID 332 //
1526 /* 3041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1527 /* 3044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1528 /* 3048 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1529 /* 3052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1530 /* 3056 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1531 /* 3056 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
1532 /* 3061 */ GIR_RootConstrainSelectedInstOperands,
1533 /* 3062 */ // GIR_Coverage, 332,
1534 /* 3062 */ GIR_Done,
1535 /* 3063 */ // Label 163: @3063
1536 /* 3063 */ GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(3102), // Rule ID 1074 //
1537 /* 3068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1538 /* 3071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1539 /* 3075 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1540 /* 3079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1541 /* 3083 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1542 /* 3083 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MM),
1543 /* 3088 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
1544 /* 3094 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
1545 /* 3100 */ GIR_RootConstrainSelectedInstOperands,
1546 /* 3101 */ // GIR_Coverage, 1074,
1547 /* 3101 */ GIR_Done,
1548 /* 3102 */ // Label 164: @3102
1549 /* 3102 */ GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(3129), // Rule ID 1179 //
1550 /* 3107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1551 /* 3110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1552 /* 3114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1553 /* 3118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1554 /* 3122 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1555 /* 3122 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MMR6),
1556 /* 3127 */ GIR_RootConstrainSelectedInstOperands,
1557 /* 3128 */ // GIR_Coverage, 1179,
1558 /* 3128 */ GIR_Done,
1559 /* 3129 */ // Label 165: @3129
1560 /* 3129 */ GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(3168), // Rule ID 1829 //
1561 /* 3134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1562 /* 3137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1563 /* 3141 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1564 /* 3145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1565 /* 3149 */ // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1566 /* 3149 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MultRxRyRz16),
1567 /* 3154 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
1568 /* 3160 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
1569 /* 3166 */ GIR_RootConstrainSelectedInstOperands,
1570 /* 3167 */ // GIR_Coverage, 1829,
1571 /* 3167 */ GIR_Done,
1572 /* 3168 */ // Label 166: @3168
1573 /* 3168 */ GIM_Reject,
1574 /* 3169 */ // Label 161: @3169
1575 /* 3169 */ GIM_Reject,
1576 /* 3170 */ // Label 154: @3170
1577 /* 3170 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3254),
1578 /* 3175 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1579 /* 3178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1580 /* 3181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1581 /* 3185 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1582 /* 3189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1583 /* 3193 */ GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3238), // Rule ID 274 //
1584 /* 3198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
1585 /* 3201 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1586 /* 3201 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL),
1587 /* 3206 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
1588 /* 3212 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
1589 /* 3218 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P0), GIMT_Encode2(RegState::Dead),
1590 /* 3224 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P1), GIMT_Encode2(RegState::Dead),
1591 /* 3230 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P2), GIMT_Encode2(RegState::Dead),
1592 /* 3236 */ GIR_RootConstrainSelectedInstOperands,
1593 /* 3237 */ // GIR_Coverage, 274,
1594 /* 3237 */ GIR_Done,
1595 /* 3238 */ // Label 168: @3238
1596 /* 3238 */ GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(3253), // Rule ID 347 //
1597 /* 3243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1598 /* 3246 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1599 /* 3246 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL_R6),
1600 /* 3251 */ GIR_RootConstrainSelectedInstOperands,
1601 /* 3252 */ // GIR_Coverage, 347,
1602 /* 3252 */ GIR_Done,
1603 /* 3253 */ // Label 169: @3253
1604 /* 3253 */ GIM_Reject,
1605 /* 3254 */ // Label 167: @3254
1606 /* 3254 */ GIM_Reject,
1607 /* 3255 */ // Label 155: @3255
1608 /* 3255 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(3286), // Rule ID 1930 //
1609 /* 3260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
1610 /* 3263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1611 /* 3266 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1612 /* 3269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1613 /* 3273 */ // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1614 /* 3273 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
1615 /* 3278 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(RegState::Dead),
1616 /* 3284 */ GIR_RootConstrainSelectedInstOperands,
1617 /* 3285 */ // GIR_Coverage, 1930,
1618 /* 3285 */ GIR_Done,
1619 /* 3286 */ // Label 170: @3286
1620 /* 3286 */ GIM_Reject,
1621 /* 3287 */ // Label 156: @3287
1622 /* 3287 */ GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3320), // Rule ID 907 //
1623 /* 3292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1624 /* 3295 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1625 /* 3298 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1626 /* 3301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1627 /* 3305 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1628 /* 3309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1629 /* 3313 */ // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1630 /* 3313 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_D),
1631 /* 3318 */ GIR_RootConstrainSelectedInstOperands,
1632 /* 3319 */ // GIR_Coverage, 907,
1633 /* 3319 */ GIR_Done,
1634 /* 3320 */ // Label 171: @3320
1635 /* 3320 */ GIM_Reject,
1636 /* 3321 */ // Label 157: @3321
1637 /* 3321 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3354), // Rule ID 906 //
1638 /* 3326 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1639 /* 3329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1640 /* 3332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1641 /* 3335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1642 /* 3339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1643 /* 3343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1644 /* 3347 */ // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1645 /* 3347 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_W),
1646 /* 3352 */ GIR_RootConstrainSelectedInstOperands,
1647 /* 3353 */ // GIR_Coverage, 906,
1648 /* 3353 */ GIR_Done,
1649 /* 3354 */ // Label 172: @3354
1650 /* 3354 */ GIM_Reject,
1651 /* 3355 */ // Label 158: @3355
1652 /* 3355 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(3388), // Rule ID 905 //
1653 /* 3360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1654 /* 3363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1655 /* 3366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1656 /* 3369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1657 /* 3373 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1658 /* 3377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1659 /* 3381 */ // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1660 /* 3381 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_H),
1661 /* 3386 */ GIR_RootConstrainSelectedInstOperands,
1662 /* 3387 */ // GIR_Coverage, 905,
1663 /* 3387 */ GIR_Done,
1664 /* 3388 */ // Label 173: @3388
1665 /* 3388 */ GIM_Reject,
1666 /* 3389 */ // Label 159: @3389
1667 /* 3389 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(3422), // Rule ID 904 //
1668 /* 3394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1669 /* 3397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1670 /* 3400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1671 /* 3403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1672 /* 3407 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1673 /* 3411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1674 /* 3415 */ // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1675 /* 3415 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_B),
1676 /* 3420 */ GIR_RootConstrainSelectedInstOperands,
1677 /* 3421 */ // GIR_Coverage, 904,
1678 /* 3421 */ GIR_Done,
1679 /* 3422 */ // Label 174: @3422
1680 /* 3422 */ GIM_Reject,
1681 /* 3423 */ // Label 160: @3423
1682 /* 3423 */ GIM_Reject,
1683 /* 3424 */ // Label 3: @3424
1684 /* 3424 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 181*/ GIMT_Encode4(3692),
1685 /* 3435 */ /*GILLT_s32*//*Label 175*/ GIMT_Encode4(3467),
1686 /* 3439 */ /*GILLT_s64*//*Label 176*/ GIMT_Encode4(3522), GIMT_Encode4(0),
1687 /* 3447 */ /*GILLT_v2s64*//*Label 177*/ GIMT_Encode4(3556), GIMT_Encode4(0),
1688 /* 3455 */ /*GILLT_v4s32*//*Label 178*/ GIMT_Encode4(3590),
1689 /* 3459 */ /*GILLT_v8s16*//*Label 179*/ GIMT_Encode4(3624),
1690 /* 3463 */ /*GILLT_v16s8*//*Label 180*/ GIMT_Encode4(3658),
1691 /* 3467 */ // Label 175: @3467
1692 /* 3467 */ GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(3521),
1693 /* 3472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1694 /* 3475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1695 /* 3478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1696 /* 3482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1697 /* 3486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1698 /* 3490 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(3505), // Rule ID 326 //
1699 /* 3495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1700 /* 3498 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1701 /* 3498 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV),
1702 /* 3503 */ GIR_RootConstrainSelectedInstOperands,
1703 /* 3504 */ // GIR_Coverage, 326,
1704 /* 3504 */ GIR_Done,
1705 /* 3505 */ // Label 183: @3505
1706 /* 3505 */ GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(3520), // Rule ID 1172 //
1707 /* 3510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1708 /* 3513 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1709 /* 3513 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_MMR6),
1710 /* 3518 */ GIR_RootConstrainSelectedInstOperands,
1711 /* 3519 */ // GIR_Coverage, 1172,
1712 /* 3519 */ GIR_Done,
1713 /* 3520 */ // Label 184: @3520
1714 /* 3520 */ GIM_Reject,
1715 /* 3521 */ // Label 182: @3521
1716 /* 3521 */ GIM_Reject,
1717 /* 3522 */ // Label 176: @3522
1718 /* 3522 */ GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(3555), // Rule ID 341 //
1719 /* 3527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1720 /* 3530 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1721 /* 3533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1722 /* 3536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1723 /* 3540 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1724 /* 3544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1725 /* 3548 */ // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1726 /* 3548 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIV),
1727 /* 3553 */ GIR_RootConstrainSelectedInstOperands,
1728 /* 3554 */ // GIR_Coverage, 341,
1729 /* 3554 */ GIR_Done,
1730 /* 3555 */ // Label 185: @3555
1731 /* 3555 */ GIM_Reject,
1732 /* 3556 */ // Label 177: @3556
1733 /* 3556 */ GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(3589), // Rule ID 647 //
1734 /* 3561 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1735 /* 3564 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1736 /* 3567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1737 /* 3570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1738 /* 3574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1739 /* 3578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1740 /* 3582 */ // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1741 /* 3582 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_D),
1742 /* 3587 */ GIR_RootConstrainSelectedInstOperands,
1743 /* 3588 */ // GIR_Coverage, 647,
1744 /* 3588 */ GIR_Done,
1745 /* 3589 */ // Label 186: @3589
1746 /* 3589 */ GIM_Reject,
1747 /* 3590 */ // Label 178: @3590
1748 /* 3590 */ GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(3623), // Rule ID 646 //
1749 /* 3595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1750 /* 3598 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1751 /* 3601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1752 /* 3604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1753 /* 3608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1754 /* 3612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1755 /* 3616 */ // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1756 /* 3616 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_W),
1757 /* 3621 */ GIR_RootConstrainSelectedInstOperands,
1758 /* 3622 */ // GIR_Coverage, 646,
1759 /* 3622 */ GIR_Done,
1760 /* 3623 */ // Label 187: @3623
1761 /* 3623 */ GIM_Reject,
1762 /* 3624 */ // Label 179: @3624
1763 /* 3624 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(3657), // Rule ID 645 //
1764 /* 3629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1765 /* 3632 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1766 /* 3635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1767 /* 3638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1768 /* 3642 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1769 /* 3646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1770 /* 3650 */ // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1771 /* 3650 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_H),
1772 /* 3655 */ GIR_RootConstrainSelectedInstOperands,
1773 /* 3656 */ // GIR_Coverage, 645,
1774 /* 3656 */ GIR_Done,
1775 /* 3657 */ // Label 188: @3657
1776 /* 3657 */ GIM_Reject,
1777 /* 3658 */ // Label 180: @3658
1778 /* 3658 */ GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(3691), // Rule ID 644 //
1779 /* 3663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1780 /* 3666 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1781 /* 3669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1782 /* 3672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1783 /* 3676 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1784 /* 3680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1785 /* 3684 */ // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1786 /* 3684 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_B),
1787 /* 3689 */ GIR_RootConstrainSelectedInstOperands,
1788 /* 3690 */ // GIR_Coverage, 644,
1789 /* 3690 */ GIR_Done,
1790 /* 3691 */ // Label 189: @3691
1791 /* 3691 */ GIM_Reject,
1792 /* 3692 */ // Label 181: @3692
1793 /* 3692 */ GIM_Reject,
1794 /* 3693 */ // Label 4: @3693
1795 /* 3693 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 196*/ GIMT_Encode4(3961),
1796 /* 3704 */ /*GILLT_s32*//*Label 190*/ GIMT_Encode4(3736),
1797 /* 3708 */ /*GILLT_s64*//*Label 191*/ GIMT_Encode4(3791), GIMT_Encode4(0),
1798 /* 3716 */ /*GILLT_v2s64*//*Label 192*/ GIMT_Encode4(3825), GIMT_Encode4(0),
1799 /* 3724 */ /*GILLT_v4s32*//*Label 193*/ GIMT_Encode4(3859),
1800 /* 3728 */ /*GILLT_v8s16*//*Label 194*/ GIMT_Encode4(3893),
1801 /* 3732 */ /*GILLT_v16s8*//*Label 195*/ GIMT_Encode4(3927),
1802 /* 3736 */ // Label 190: @3736
1803 /* 3736 */ GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(3790),
1804 /* 3741 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1805 /* 3744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1806 /* 3747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1807 /* 3751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1808 /* 3755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1809 /* 3759 */ GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(3774), // Rule ID 327 //
1810 /* 3764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1811 /* 3767 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1812 /* 3767 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU),
1813 /* 3772 */ GIR_RootConstrainSelectedInstOperands,
1814 /* 3773 */ // GIR_Coverage, 327,
1815 /* 3773 */ GIR_Done,
1816 /* 3774 */ // Label 198: @3774
1817 /* 3774 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(3789), // Rule ID 1173 //
1818 /* 3779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1819 /* 3782 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1820 /* 3782 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU_MMR6),
1821 /* 3787 */ GIR_RootConstrainSelectedInstOperands,
1822 /* 3788 */ // GIR_Coverage, 1173,
1823 /* 3788 */ GIR_Done,
1824 /* 3789 */ // Label 199: @3789
1825 /* 3789 */ GIM_Reject,
1826 /* 3790 */ // Label 197: @3790
1827 /* 3790 */ GIM_Reject,
1828 /* 3791 */ // Label 191: @3791
1829 /* 3791 */ GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(3824), // Rule ID 342 //
1830 /* 3796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1831 /* 3799 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1832 /* 3802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1833 /* 3805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1834 /* 3809 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1835 /* 3813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1836 /* 3817 */ // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1837 /* 3817 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIVU),
1838 /* 3822 */ GIR_RootConstrainSelectedInstOperands,
1839 /* 3823 */ // GIR_Coverage, 342,
1840 /* 3823 */ GIR_Done,
1841 /* 3824 */ // Label 200: @3824
1842 /* 3824 */ GIM_Reject,
1843 /* 3825 */ // Label 192: @3825
1844 /* 3825 */ GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(3858), // Rule ID 651 //
1845 /* 3830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1846 /* 3833 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1847 /* 3836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1848 /* 3839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1849 /* 3843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1850 /* 3847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1851 /* 3851 */ // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1852 /* 3851 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_D),
1853 /* 3856 */ GIR_RootConstrainSelectedInstOperands,
1854 /* 3857 */ // GIR_Coverage, 651,
1855 /* 3857 */ GIR_Done,
1856 /* 3858 */ // Label 201: @3858
1857 /* 3858 */ GIM_Reject,
1858 /* 3859 */ // Label 193: @3859
1859 /* 3859 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(3892), // Rule ID 650 //
1860 /* 3864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1861 /* 3867 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1862 /* 3870 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1863 /* 3873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1864 /* 3877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1865 /* 3881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1866 /* 3885 */ // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1867 /* 3885 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_W),
1868 /* 3890 */ GIR_RootConstrainSelectedInstOperands,
1869 /* 3891 */ // GIR_Coverage, 650,
1870 /* 3891 */ GIR_Done,
1871 /* 3892 */ // Label 202: @3892
1872 /* 3892 */ GIM_Reject,
1873 /* 3893 */ // Label 194: @3893
1874 /* 3893 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(3926), // Rule ID 649 //
1875 /* 3898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1876 /* 3901 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1877 /* 3904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1878 /* 3907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1879 /* 3911 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1880 /* 3915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1881 /* 3919 */ // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1882 /* 3919 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_H),
1883 /* 3924 */ GIR_RootConstrainSelectedInstOperands,
1884 /* 3925 */ // GIR_Coverage, 649,
1885 /* 3925 */ GIR_Done,
1886 /* 3926 */ // Label 203: @3926
1887 /* 3926 */ GIM_Reject,
1888 /* 3927 */ // Label 195: @3927
1889 /* 3927 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(3960), // Rule ID 648 //
1890 /* 3932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1891 /* 3935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1892 /* 3938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1893 /* 3941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1894 /* 3945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1895 /* 3949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1896 /* 3953 */ // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1897 /* 3953 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_B),
1898 /* 3958 */ GIR_RootConstrainSelectedInstOperands,
1899 /* 3959 */ // GIR_Coverage, 648,
1900 /* 3959 */ GIR_Done,
1901 /* 3960 */ // Label 204: @3960
1902 /* 3960 */ GIM_Reject,
1903 /* 3961 */ // Label 196: @3961
1904 /* 3961 */ GIM_Reject,
1905 /* 3962 */ // Label 5: @3962
1906 /* 3962 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 211*/ GIMT_Encode4(4230),
1907 /* 3973 */ /*GILLT_s32*//*Label 205*/ GIMT_Encode4(4005),
1908 /* 3977 */ /*GILLT_s64*//*Label 206*/ GIMT_Encode4(4060), GIMT_Encode4(0),
1909 /* 3985 */ /*GILLT_v2s64*//*Label 207*/ GIMT_Encode4(4094), GIMT_Encode4(0),
1910 /* 3993 */ /*GILLT_v4s32*//*Label 208*/ GIMT_Encode4(4128),
1911 /* 3997 */ /*GILLT_v8s16*//*Label 209*/ GIMT_Encode4(4162),
1912 /* 4001 */ /*GILLT_v16s8*//*Label 210*/ GIMT_Encode4(4196),
1913 /* 4005 */ // Label 205: @4005
1914 /* 4005 */ GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(4059),
1915 /* 4010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1916 /* 4013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1917 /* 4016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1918 /* 4020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1919 /* 4024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1920 /* 4028 */ GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(4043), // Rule ID 328 //
1921 /* 4033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1922 /* 4036 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1923 /* 4036 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD),
1924 /* 4041 */ GIR_RootConstrainSelectedInstOperands,
1925 /* 4042 */ // GIR_Coverage, 328,
1926 /* 4042 */ GIR_Done,
1927 /* 4043 */ // Label 213: @4043
1928 /* 4043 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(4058), // Rule ID 1177 //
1929 /* 4048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1930 /* 4051 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1931 /* 4051 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_MMR6),
1932 /* 4056 */ GIR_RootConstrainSelectedInstOperands,
1933 /* 4057 */ // GIR_Coverage, 1177,
1934 /* 4057 */ GIR_Done,
1935 /* 4058 */ // Label 214: @4058
1936 /* 4058 */ GIM_Reject,
1937 /* 4059 */ // Label 212: @4059
1938 /* 4059 */ GIM_Reject,
1939 /* 4060 */ // Label 206: @4060
1940 /* 4060 */ GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(4093), // Rule ID 343 //
1941 /* 4065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1942 /* 4068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1943 /* 4071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1944 /* 4074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1945 /* 4078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1946 /* 4082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1947 /* 4086 */ // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1948 /* 4086 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMOD),
1949 /* 4091 */ GIR_RootConstrainSelectedInstOperands,
1950 /* 4092 */ // GIR_Coverage, 343,
1951 /* 4092 */ GIR_Done,
1952 /* 4093 */ // Label 215: @4093
1953 /* 4093 */ GIM_Reject,
1954 /* 4094 */ // Label 207: @4094
1955 /* 4094 */ GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(4127), // Rule ID 887 //
1956 /* 4099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1957 /* 4102 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1958 /* 4105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1959 /* 4108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1960 /* 4112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1961 /* 4116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1962 /* 4120 */ // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1963 /* 4120 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_D),
1964 /* 4125 */ GIR_RootConstrainSelectedInstOperands,
1965 /* 4126 */ // GIR_Coverage, 887,
1966 /* 4126 */ GIR_Done,
1967 /* 4127 */ // Label 216: @4127
1968 /* 4127 */ GIM_Reject,
1969 /* 4128 */ // Label 208: @4128
1970 /* 4128 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(4161), // Rule ID 886 //
1971 /* 4133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1972 /* 4136 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1973 /* 4139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1974 /* 4142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1975 /* 4146 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1976 /* 4150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1977 /* 4154 */ // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1978 /* 4154 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_W),
1979 /* 4159 */ GIR_RootConstrainSelectedInstOperands,
1980 /* 4160 */ // GIR_Coverage, 886,
1981 /* 4160 */ GIR_Done,
1982 /* 4161 */ // Label 217: @4161
1983 /* 4161 */ GIM_Reject,
1984 /* 4162 */ // Label 209: @4162
1985 /* 4162 */ GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(4195), // Rule ID 885 //
1986 /* 4167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1987 /* 4170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1988 /* 4173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1989 /* 4176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1990 /* 4180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1991 /* 4184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1992 /* 4188 */ // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1993 /* 4188 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_H),
1994 /* 4193 */ GIR_RootConstrainSelectedInstOperands,
1995 /* 4194 */ // GIR_Coverage, 885,
1996 /* 4194 */ GIR_Done,
1997 /* 4195 */ // Label 218: @4195
1998 /* 4195 */ GIM_Reject,
1999 /* 4196 */ // Label 210: @4196
2000 /* 4196 */ GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(4229), // Rule ID 884 //
2001 /* 4201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2002 /* 4204 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2003 /* 4207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2004 /* 4210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2005 /* 4214 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2006 /* 4218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2007 /* 4222 */ // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2008 /* 4222 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_B),
2009 /* 4227 */ GIR_RootConstrainSelectedInstOperands,
2010 /* 4228 */ // GIR_Coverage, 884,
2011 /* 4228 */ GIR_Done,
2012 /* 4229 */ // Label 219: @4229
2013 /* 4229 */ GIM_Reject,
2014 /* 4230 */ // Label 211: @4230
2015 /* 4230 */ GIM_Reject,
2016 /* 4231 */ // Label 6: @4231
2017 /* 4231 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 226*/ GIMT_Encode4(4499),
2018 /* 4242 */ /*GILLT_s32*//*Label 220*/ GIMT_Encode4(4274),
2019 /* 4246 */ /*GILLT_s64*//*Label 221*/ GIMT_Encode4(4329), GIMT_Encode4(0),
2020 /* 4254 */ /*GILLT_v2s64*//*Label 222*/ GIMT_Encode4(4363), GIMT_Encode4(0),
2021 /* 4262 */ /*GILLT_v4s32*//*Label 223*/ GIMT_Encode4(4397),
2022 /* 4266 */ /*GILLT_v8s16*//*Label 224*/ GIMT_Encode4(4431),
2023 /* 4270 */ /*GILLT_v16s8*//*Label 225*/ GIMT_Encode4(4465),
2024 /* 4274 */ // Label 220: @4274
2025 /* 4274 */ GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(4328),
2026 /* 4279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2027 /* 4282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2028 /* 4285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2029 /* 4289 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2030 /* 4293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2031 /* 4297 */ GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(4312), // Rule ID 329 //
2032 /* 4302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
2033 /* 4305 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2034 /* 4305 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU),
2035 /* 4310 */ GIR_RootConstrainSelectedInstOperands,
2036 /* 4311 */ // GIR_Coverage, 329,
2037 /* 4311 */ GIR_Done,
2038 /* 4312 */ // Label 228: @4312
2039 /* 4312 */ GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(4327), // Rule ID 1178 //
2040 /* 4317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2041 /* 4320 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2042 /* 4320 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU_MMR6),
2043 /* 4325 */ GIR_RootConstrainSelectedInstOperands,
2044 /* 4326 */ // GIR_Coverage, 1178,
2045 /* 4326 */ GIR_Done,
2046 /* 4327 */ // Label 229: @4327
2047 /* 4327 */ GIM_Reject,
2048 /* 4328 */ // Label 227: @4328
2049 /* 4328 */ GIM_Reject,
2050 /* 4329 */ // Label 221: @4329
2051 /* 4329 */ GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(4362), // Rule ID 344 //
2052 /* 4334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
2053 /* 4337 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2054 /* 4340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2055 /* 4343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2056 /* 4347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2057 /* 4351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2058 /* 4355 */ // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2059 /* 4355 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMODU),
2060 /* 4360 */ GIR_RootConstrainSelectedInstOperands,
2061 /* 4361 */ // GIR_Coverage, 344,
2062 /* 4361 */ GIR_Done,
2063 /* 4362 */ // Label 230: @4362
2064 /* 4362 */ GIM_Reject,
2065 /* 4363 */ // Label 222: @4363
2066 /* 4363 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(4396), // Rule ID 891 //
2067 /* 4368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2068 /* 4371 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2069 /* 4374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2070 /* 4377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2071 /* 4381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2072 /* 4385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2073 /* 4389 */ // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2074 /* 4389 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_D),
2075 /* 4394 */ GIR_RootConstrainSelectedInstOperands,
2076 /* 4395 */ // GIR_Coverage, 891,
2077 /* 4395 */ GIR_Done,
2078 /* 4396 */ // Label 231: @4396
2079 /* 4396 */ GIM_Reject,
2080 /* 4397 */ // Label 223: @4397
2081 /* 4397 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(4430), // Rule ID 890 //
2082 /* 4402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2083 /* 4405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2084 /* 4408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2085 /* 4411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2086 /* 4415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2087 /* 4419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2088 /* 4423 */ // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2089 /* 4423 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_W),
2090 /* 4428 */ GIR_RootConstrainSelectedInstOperands,
2091 /* 4429 */ // GIR_Coverage, 890,
2092 /* 4429 */ GIR_Done,
2093 /* 4430 */ // Label 232: @4430
2094 /* 4430 */ GIM_Reject,
2095 /* 4431 */ // Label 224: @4431
2096 /* 4431 */ GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(4464), // Rule ID 889 //
2097 /* 4436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2098 /* 4439 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2099 /* 4442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2100 /* 4445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2101 /* 4449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2102 /* 4453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2103 /* 4457 */ // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2104 /* 4457 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_H),
2105 /* 4462 */ GIR_RootConstrainSelectedInstOperands,
2106 /* 4463 */ // GIR_Coverage, 889,
2107 /* 4463 */ GIR_Done,
2108 /* 4464 */ // Label 233: @4464
2109 /* 4464 */ GIM_Reject,
2110 /* 4465 */ // Label 225: @4465
2111 /* 4465 */ GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(4498), // Rule ID 888 //
2112 /* 4470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2113 /* 4473 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2114 /* 4476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2115 /* 4479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2116 /* 4483 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2117 /* 4487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2118 /* 4491 */ // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2119 /* 4491 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_B),
2120 /* 4496 */ GIR_RootConstrainSelectedInstOperands,
2121 /* 4497 */ // GIR_Coverage, 888,
2122 /* 4497 */ GIR_Done,
2123 /* 4498 */ // Label 234: @4498
2124 /* 4498 */ GIM_Reject,
2125 /* 4499 */ // Label 226: @4499
2126 /* 4499 */ GIM_Reject,
2127 /* 4500 */ // Label 7: @4500
2128 /* 4500 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 241*/ GIMT_Encode4(5055),
2129 /* 4511 */ /*GILLT_s32*//*Label 235*/ GIMT_Encode4(4543),
2130 /* 4515 */ /*GILLT_s64*//*Label 236*/ GIMT_Encode4(4817), GIMT_Encode4(0),
2131 /* 4523 */ /*GILLT_v2s64*//*Label 237*/ GIMT_Encode4(4919), GIMT_Encode4(0),
2132 /* 4531 */ /*GILLT_v4s32*//*Label 238*/ GIMT_Encode4(4953),
2133 /* 4535 */ /*GILLT_v8s16*//*Label 239*/ GIMT_Encode4(4987),
2134 /* 4539 */ /*GILLT_v16s8*//*Label 240*/ GIMT_Encode4(5021),
2135 /* 4543 */ // Label 235: @4543
2136 /* 4543 */ GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(4816),
2137 /* 4548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2138 /* 4551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2139 /* 4554 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(4596), // Rule ID 41 //
2140 /* 4559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2141 /* 4562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2142 /* 4566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2143 /* 4570 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2144 /* 4574 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2145 /* 4578 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2146 /* 4582 */ // MIs[1] Operand 1
2147 /* 4582 */ // No operand predicates
2148 /* 4582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2149 /* 4584 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2150 /* 4584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDi),
2151 /* 4587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2152 /* 4589 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2153 /* 4591 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2154 /* 4594 */ GIR_RootConstrainSelectedInstOperands,
2155 /* 4595 */ // GIR_Coverage, 41,
2156 /* 4595 */ GIR_EraseRootFromParent_Done,
2157 /* 4596 */ // Label 243: @4596
2158 /* 4596 */ GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(4638), // Rule ID 2172 //
2159 /* 4601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2160 /* 4604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2161 /* 4608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2162 /* 4612 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2163 /* 4616 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2164 /* 4620 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2165 /* 4624 */ // MIs[1] Operand 1
2166 /* 4624 */ // No operand predicates
2167 /* 4624 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2168 /* 4626 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2169 /* 4626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MM),
2170 /* 4629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2171 /* 4631 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2172 /* 4633 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2173 /* 4636 */ GIR_RootConstrainSelectedInstOperands,
2174 /* 4637 */ // GIR_Coverage, 2172,
2175 /* 4637 */ GIR_EraseRootFromParent_Done,
2176 /* 4638 */ // Label 244: @4638
2177 /* 4638 */ GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(4680), // Rule ID 2331 //
2178 /* 4643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2179 /* 4646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2180 /* 4650 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2181 /* 4654 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2182 /* 4658 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2183 /* 4662 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2184 /* 4666 */ // MIs[1] Operand 1
2185 /* 4666 */ // No operand predicates
2186 /* 4666 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2187 /* 4668 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2188 /* 4668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MMR6),
2189 /* 4671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2190 /* 4673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2191 /* 4675 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2192 /* 4678 */ GIR_RootConstrainSelectedInstOperands,
2193 /* 4679 */ // GIR_Coverage, 2331,
2194 /* 4679 */ GIR_EraseRootFromParent_Done,
2195 /* 4680 */ // Label 245: @4680
2196 /* 4680 */ GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(4707), // Rule ID 51 //
2197 /* 4685 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2198 /* 4688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2199 /* 4692 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2200 /* 4696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2201 /* 4700 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2202 /* 4700 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND),
2203 /* 4705 */ GIR_RootConstrainSelectedInstOperands,
2204 /* 4706 */ // GIR_Coverage, 51,
2205 /* 4706 */ GIR_Done,
2206 /* 4707 */ // Label 246: @4707
2207 /* 4707 */ GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(4734), // Rule ID 1061 //
2208 /* 4712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2209 /* 4715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2210 /* 4719 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2211 /* 4723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2212 /* 4727 */ // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2213 /* 4727 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND16_MM),
2214 /* 4732 */ GIR_RootConstrainSelectedInstOperands,
2215 /* 4733 */ // GIR_Coverage, 1061,
2216 /* 4733 */ GIR_Done,
2217 /* 4734 */ // Label 247: @4734
2218 /* 4734 */ GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(4761), // Rule ID 1077 //
2219 /* 4739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2220 /* 4742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2221 /* 4746 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2222 /* 4750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2223 /* 4754 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2224 /* 4754 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MM),
2225 /* 4759 */ GIR_RootConstrainSelectedInstOperands,
2226 /* 4760 */ // GIR_Coverage, 1077,
2227 /* 4760 */ GIR_Done,
2228 /* 4761 */ // Label 248: @4761
2229 /* 4761 */ GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(4788), // Rule ID 1170 //
2230 /* 4766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2231 /* 4769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2232 /* 4773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2233 /* 4777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2234 /* 4781 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2235 /* 4781 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MMR6),
2236 /* 4786 */ GIR_RootConstrainSelectedInstOperands,
2237 /* 4787 */ // GIR_Coverage, 1170,
2238 /* 4787 */ GIR_Done,
2239 /* 4788 */ // Label 249: @4788
2240 /* 4788 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(4815), // Rule ID 1828 //
2241 /* 4793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2242 /* 4796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2243 /* 4800 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2244 /* 4804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2245 /* 4808 */ // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2246 /* 4808 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AndRxRxRy16),
2247 /* 4813 */ GIR_RootConstrainSelectedInstOperands,
2248 /* 4814 */ // GIR_Coverage, 1828,
2249 /* 4814 */ GIR_Done,
2250 /* 4815 */ // Label 250: @4815
2251 /* 4815 */ GIM_Reject,
2252 /* 4816 */ // Label 242: @4816
2253 /* 4816 */ GIM_Reject,
2254 /* 4817 */ // Label 236: @4817
2255 /* 4817 */ GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(4918),
2256 /* 4822 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2257 /* 4825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2258 /* 4828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2259 /* 4832 */ GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(4894), // Rule ID 269 //
2260 /* 4837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
2261 /* 4840 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2262 /* 4844 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
2263 /* 4848 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2264 /* 4852 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2265 /* 4856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2266 /* 4861 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2267 /* 4866 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
2268 /* 4877 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2269 /* 4879 */ // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2270 /* 4879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BADDu),
2271 /* 4882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2272 /* 4884 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2273 /* 4888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2274 /* 4892 */ GIR_RootConstrainSelectedInstOperands,
2275 /* 4893 */ // GIR_Coverage, 269,
2276 /* 4893 */ GIR_EraseRootFromParent_Done,
2277 /* 4894 */ // Label 252: @4894
2278 /* 4894 */ GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(4917), // Rule ID 206 //
2279 /* 4899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2280 /* 4902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2281 /* 4906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2282 /* 4910 */ // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2283 /* 4910 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND64),
2284 /* 4915 */ GIR_RootConstrainSelectedInstOperands,
2285 /* 4916 */ // GIR_Coverage, 206,
2286 /* 4916 */ GIR_Done,
2287 /* 4917 */ // Label 253: @4917
2288 /* 4917 */ GIM_Reject,
2289 /* 4918 */ // Label 251: @4918
2290 /* 4918 */ GIM_Reject,
2291 /* 4919 */ // Label 237: @4919
2292 /* 4919 */ GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(4952), // Rule ID 518 //
2293 /* 4924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2294 /* 4927 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2295 /* 4930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2296 /* 4933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2297 /* 4937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2298 /* 4941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2299 /* 4945 */ // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2300 /* 4945 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
2301 /* 4950 */ GIR_RootConstrainSelectedInstOperands,
2302 /* 4951 */ // GIR_Coverage, 518,
2303 /* 4951 */ GIR_Done,
2304 /* 4952 */ // Label 254: @4952
2305 /* 4952 */ GIM_Reject,
2306 /* 4953 */ // Label 238: @4953
2307 /* 4953 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(4986), // Rule ID 517 //
2308 /* 4958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2309 /* 4961 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2310 /* 4964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2311 /* 4967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2312 /* 4971 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2313 /* 4975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2314 /* 4979 */ // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2315 /* 4979 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
2316 /* 4984 */ GIR_RootConstrainSelectedInstOperands,
2317 /* 4985 */ // GIR_Coverage, 517,
2318 /* 4985 */ GIR_Done,
2319 /* 4986 */ // Label 255: @4986
2320 /* 4986 */ GIM_Reject,
2321 /* 4987 */ // Label 239: @4987
2322 /* 4987 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(5020), // Rule ID 516 //
2323 /* 4992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2324 /* 4995 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2325 /* 4998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2326 /* 5001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2327 /* 5005 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2328 /* 5009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2329 /* 5013 */ // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2330 /* 5013 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
2331 /* 5018 */ GIR_RootConstrainSelectedInstOperands,
2332 /* 5019 */ // GIR_Coverage, 516,
2333 /* 5019 */ GIR_Done,
2334 /* 5020 */ // Label 256: @5020
2335 /* 5020 */ GIM_Reject,
2336 /* 5021 */ // Label 240: @5021
2337 /* 5021 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(5054), // Rule ID 515 //
2338 /* 5026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2339 /* 5029 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2340 /* 5032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2341 /* 5035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2342 /* 5039 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2343 /* 5043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2344 /* 5047 */ // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2345 /* 5047 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V),
2346 /* 5052 */ GIR_RootConstrainSelectedInstOperands,
2347 /* 5053 */ // GIR_Coverage, 515,
2348 /* 5053 */ GIR_Done,
2349 /* 5054 */ // Label 257: @5054
2350 /* 5054 */ GIM_Reject,
2351 /* 5055 */ // Label 241: @5055
2352 /* 5055 */ GIM_Reject,
2353 /* 5056 */ // Label 8: @5056
2354 /* 5056 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 264*/ GIMT_Encode4(5459),
2355 /* 5067 */ /*GILLT_s32*//*Label 258*/ GIMT_Encode4(5099),
2356 /* 5071 */ /*GILLT_s64*//*Label 259*/ GIMT_Encode4(5289), GIMT_Encode4(0),
2357 /* 5079 */ /*GILLT_v2s64*//*Label 260*/ GIMT_Encode4(5323), GIMT_Encode4(0),
2358 /* 5087 */ /*GILLT_v4s32*//*Label 261*/ GIMT_Encode4(5357),
2359 /* 5091 */ /*GILLT_v8s16*//*Label 262*/ GIMT_Encode4(5391),
2360 /* 5095 */ /*GILLT_v16s8*//*Label 263*/ GIMT_Encode4(5425),
2361 /* 5099 */ // Label 258: @5099
2362 /* 5099 */ GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(5288),
2363 /* 5104 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2364 /* 5107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2365 /* 5110 */ GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(5152), // Rule ID 42 //
2366 /* 5115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2367 /* 5118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2368 /* 5122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2369 /* 5126 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2370 /* 5130 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2371 /* 5134 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2372 /* 5138 */ // MIs[1] Operand 1
2373 /* 5138 */ // No operand predicates
2374 /* 5138 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2375 /* 5140 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2376 /* 5140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ORi),
2377 /* 5143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2378 /* 5145 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2379 /* 5147 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2380 /* 5150 */ GIR_RootConstrainSelectedInstOperands,
2381 /* 5151 */ // GIR_Coverage, 42,
2382 /* 5151 */ GIR_EraseRootFromParent_Done,
2383 /* 5152 */ // Label 266: @5152
2384 /* 5152 */ GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(5179), // Rule ID 52 //
2385 /* 5157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2386 /* 5160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2387 /* 5164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2388 /* 5168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2389 /* 5172 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2390 /* 5172 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR),
2391 /* 5177 */ GIR_RootConstrainSelectedInstOperands,
2392 /* 5178 */ // GIR_Coverage, 52,
2393 /* 5178 */ GIR_Done,
2394 /* 5179 */ // Label 267: @5179
2395 /* 5179 */ GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(5206), // Rule ID 1063 //
2396 /* 5184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2397 /* 5187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2398 /* 5191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2399 /* 5195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2400 /* 5199 */ // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2401 /* 5199 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR16_MM),
2402 /* 5204 */ GIR_RootConstrainSelectedInstOperands,
2403 /* 5205 */ // GIR_Coverage, 1063,
2404 /* 5205 */ GIR_Done,
2405 /* 5206 */ // Label 268: @5206
2406 /* 5206 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(5233), // Rule ID 1078 //
2407 /* 5211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2408 /* 5214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2409 /* 5218 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2410 /* 5222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2411 /* 5226 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2412 /* 5226 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
2413 /* 5231 */ GIR_RootConstrainSelectedInstOperands,
2414 /* 5232 */ // GIR_Coverage, 1078,
2415 /* 5232 */ GIR_Done,
2416 /* 5233 */ // Label 269: @5233
2417 /* 5233 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(5260), // Rule ID 1183 //
2418 /* 5238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2419 /* 5241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2420 /* 5245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2421 /* 5249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2422 /* 5253 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2423 /* 5253 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MMR6),
2424 /* 5258 */ GIR_RootConstrainSelectedInstOperands,
2425 /* 5259 */ // GIR_Coverage, 1183,
2426 /* 5259 */ GIR_Done,
2427 /* 5260 */ // Label 270: @5260
2428 /* 5260 */ GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(5287), // Rule ID 1830 //
2429 /* 5265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2430 /* 5268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2431 /* 5272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2432 /* 5276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2433 /* 5280 */ // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2434 /* 5280 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OrRxRxRy16),
2435 /* 5285 */ GIR_RootConstrainSelectedInstOperands,
2436 /* 5286 */ // GIR_Coverage, 1830,
2437 /* 5286 */ GIR_Done,
2438 /* 5287 */ // Label 271: @5287
2439 /* 5287 */ GIM_Reject,
2440 /* 5288 */ // Label 265: @5288
2441 /* 5288 */ GIM_Reject,
2442 /* 5289 */ // Label 259: @5289
2443 /* 5289 */ GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(5322), // Rule ID 207 //
2444 /* 5294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2445 /* 5297 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2446 /* 5300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2447 /* 5303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2448 /* 5307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2449 /* 5311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2450 /* 5315 */ // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2451 /* 5315 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR64),
2452 /* 5320 */ GIR_RootConstrainSelectedInstOperands,
2453 /* 5321 */ // GIR_Coverage, 207,
2454 /* 5321 */ GIR_Done,
2455 /* 5322 */ // Label 272: @5322
2456 /* 5322 */ GIM_Reject,
2457 /* 5323 */ // Label 260: @5323
2458 /* 5323 */ GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(5356), // Rule ID 924 //
2459 /* 5328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2460 /* 5331 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2461 /* 5334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2462 /* 5337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2463 /* 5341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2464 /* 5345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2465 /* 5349 */ // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2466 /* 5349 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
2467 /* 5354 */ GIR_RootConstrainSelectedInstOperands,
2468 /* 5355 */ // GIR_Coverage, 924,
2469 /* 5355 */ GIR_Done,
2470 /* 5356 */ // Label 273: @5356
2471 /* 5356 */ GIM_Reject,
2472 /* 5357 */ // Label 261: @5357
2473 /* 5357 */ GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(5390), // Rule ID 923 //
2474 /* 5362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2475 /* 5365 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2476 /* 5368 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2477 /* 5371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2478 /* 5375 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2479 /* 5379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2480 /* 5383 */ // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2481 /* 5383 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
2482 /* 5388 */ GIR_RootConstrainSelectedInstOperands,
2483 /* 5389 */ // GIR_Coverage, 923,
2484 /* 5389 */ GIR_Done,
2485 /* 5390 */ // Label 274: @5390
2486 /* 5390 */ GIM_Reject,
2487 /* 5391 */ // Label 262: @5391
2488 /* 5391 */ GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(5424), // Rule ID 922 //
2489 /* 5396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2490 /* 5399 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2491 /* 5402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2492 /* 5405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2493 /* 5409 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2494 /* 5413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2495 /* 5417 */ // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2496 /* 5417 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
2497 /* 5422 */ GIR_RootConstrainSelectedInstOperands,
2498 /* 5423 */ // GIR_Coverage, 922,
2499 /* 5423 */ GIR_Done,
2500 /* 5424 */ // Label 275: @5424
2501 /* 5424 */ GIM_Reject,
2502 /* 5425 */ // Label 263: @5425
2503 /* 5425 */ GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(5458), // Rule ID 921 //
2504 /* 5430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2505 /* 5433 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2506 /* 5436 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2507 /* 5439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2508 /* 5443 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2509 /* 5447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2510 /* 5451 */ // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2511 /* 5451 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V),
2512 /* 5456 */ GIR_RootConstrainSelectedInstOperands,
2513 /* 5457 */ // GIR_Coverage, 921,
2514 /* 5457 */ GIR_Done,
2515 /* 5458 */ // Label 276: @5458
2516 /* 5458 */ GIM_Reject,
2517 /* 5459 */ // Label 264: @5459
2518 /* 5459 */ GIM_Reject,
2519 /* 5460 */ // Label 9: @5460
2520 /* 5460 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 283*/ GIMT_Encode4(6351),
2521 /* 5471 */ /*GILLT_s32*//*Label 277*/ GIMT_Encode4(5503),
2522 /* 5475 */ /*GILLT_s64*//*Label 278*/ GIMT_Encode4(6120), GIMT_Encode4(0),
2523 /* 5483 */ /*GILLT_v2s64*//*Label 279*/ GIMT_Encode4(6215), GIMT_Encode4(0),
2524 /* 5491 */ /*GILLT_v4s32*//*Label 280*/ GIMT_Encode4(6249),
2525 /* 5495 */ /*GILLT_v8s16*//*Label 281*/ GIMT_Encode4(6283),
2526 /* 5499 */ /*GILLT_v16s8*//*Label 282*/ GIMT_Encode4(6317),
2527 /* 5503 */ // Label 277: @5503
2528 /* 5503 */ GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(6119),
2529 /* 5508 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2530 /* 5511 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2531 /* 5514 */ GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(5573), // Rule ID 54 //
2532 /* 5519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2533 /* 5522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2534 /* 5526 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2535 /* 5530 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2536 /* 5534 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2537 /* 5538 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2538 /* 5542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2539 /* 5547 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2540 /* 5552 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2541 /* 5556 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2542 /* 5558 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2543 /* 5558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2544 /* 5561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2545 /* 5563 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2546 /* 5567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2547 /* 5571 */ GIR_RootConstrainSelectedInstOperands,
2548 /* 5572 */ // GIR_Coverage, 54,
2549 /* 5572 */ GIR_EraseRootFromParent_Done,
2550 /* 5573 */ // Label 285: @5573
2551 /* 5573 */ GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(5632), // Rule ID 1080 //
2552 /* 5578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2553 /* 5581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2554 /* 5585 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2555 /* 5589 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2556 /* 5593 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2557 /* 5597 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2558 /* 5601 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2559 /* 5606 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2560 /* 5611 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2561 /* 5615 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2562 /* 5617 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2563 /* 5617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2564 /* 5620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2565 /* 5622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2566 /* 5626 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2567 /* 5630 */ GIR_RootConstrainSelectedInstOperands,
2568 /* 5631 */ // GIR_Coverage, 1080,
2569 /* 5631 */ GIR_EraseRootFromParent_Done,
2570 /* 5632 */ // Label 286: @5632
2571 /* 5632 */ GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(5691), // Rule ID 1182 //
2572 /* 5637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2573 /* 5640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2574 /* 5644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2575 /* 5648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2576 /* 5652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2577 /* 5656 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2578 /* 5660 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2579 /* 5665 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2580 /* 5670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2581 /* 5674 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2582 /* 5676 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2583 /* 5676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2584 /* 5679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2585 /* 5681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2586 /* 5685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2587 /* 5689 */ GIR_RootConstrainSelectedInstOperands,
2588 /* 5690 */ // GIR_Coverage, 1182,
2589 /* 5690 */ GIR_EraseRootFromParent_Done,
2590 /* 5691 */ // Label 287: @5691
2591 /* 5691 */ GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(5720), // Rule ID 1209 //
2592 /* 5696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2593 /* 5699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2594 /* 5703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2595 /* 5707 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2596 /* 5711 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2597 /* 5711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2598 /* 5714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2599 /* 5716 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2600 /* 5718 */ GIR_RootConstrainSelectedInstOperands,
2601 /* 5719 */ // GIR_Coverage, 1209,
2602 /* 5719 */ GIR_EraseRootFromParent_Done,
2603 /* 5720 */ // Label 288: @5720
2604 /* 5720 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(5749), // Rule ID 1062 //
2605 /* 5725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2606 /* 5728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2607 /* 5732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2608 /* 5736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2609 /* 5740 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2610 /* 5740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2611 /* 5743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2612 /* 5745 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2613 /* 5747 */ GIR_RootConstrainSelectedInstOperands,
2614 /* 5748 */ // GIR_Coverage, 1062,
2615 /* 5748 */ GIR_EraseRootFromParent_Done,
2616 /* 5749 */ // Label 289: @5749
2617 /* 5749 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(5784), // Rule ID 1397 //
2618 /* 5754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2619 /* 5757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2620 /* 5761 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2621 /* 5765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2622 /* 5769 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2623 /* 5769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2624 /* 5772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2625 /* 5774 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2626 /* 5776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2627 /* 5782 */ GIR_RootConstrainSelectedInstOperands,
2628 /* 5783 */ // GIR_Coverage, 1397,
2629 /* 5783 */ GIR_EraseRootFromParent_Done,
2630 /* 5784 */ // Label 290: @5784
2631 /* 5784 */ GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(5813), // Rule ID 1825 //
2632 /* 5789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2633 /* 5792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2634 /* 5796 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2635 /* 5800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2636 /* 5804 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2637 /* 5804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NotRxRy16),
2638 /* 5807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
2639 /* 5809 */ GIR_RootToRootCopy, /*OpIdx*/1, // r
2640 /* 5811 */ GIR_RootConstrainSelectedInstOperands,
2641 /* 5812 */ // GIR_Coverage, 1825,
2642 /* 5812 */ GIR_EraseRootFromParent_Done,
2643 /* 5813 */ // Label 291: @5813
2644 /* 5813 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(5842), // Rule ID 2167 //
2645 /* 5818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2646 /* 5821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2647 /* 5825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2648 /* 5829 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2649 /* 5833 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2650 /* 5833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2651 /* 5836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2652 /* 5838 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2653 /* 5840 */ GIR_RootConstrainSelectedInstOperands,
2654 /* 5841 */ // GIR_Coverage, 2167,
2655 /* 5841 */ GIR_EraseRootFromParent_Done,
2656 /* 5842 */ // Label 292: @5842
2657 /* 5842 */ GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(5877), // Rule ID 2168 //
2658 /* 5847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2659 /* 5850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2660 /* 5854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2661 /* 5858 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2662 /* 5862 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2663 /* 5862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2664 /* 5865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2665 /* 5867 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2666 /* 5869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2667 /* 5875 */ GIR_RootConstrainSelectedInstOperands,
2668 /* 5876 */ // GIR_Coverage, 2168,
2669 /* 5876 */ GIR_EraseRootFromParent_Done,
2670 /* 5877 */ // Label 293: @5877
2671 /* 5877 */ GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(5906), // Rule ID 2334 //
2672 /* 5882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2673 /* 5885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2674 /* 5889 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2675 /* 5893 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2676 /* 5897 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2677 /* 5897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2678 /* 5900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2679 /* 5902 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2680 /* 5904 */ GIR_RootConstrainSelectedInstOperands,
2681 /* 5905 */ // GIR_Coverage, 2334,
2682 /* 5905 */ GIR_EraseRootFromParent_Done,
2683 /* 5906 */ // Label 294: @5906
2684 /* 5906 */ GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(5941), // Rule ID 2335 //
2685 /* 5911 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2686 /* 5914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2687 /* 5918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2688 /* 5922 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2689 /* 5926 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2690 /* 5926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2691 /* 5929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2692 /* 5931 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2693 /* 5933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2694 /* 5939 */ GIR_RootConstrainSelectedInstOperands,
2695 /* 5940 */ // GIR_Coverage, 2335,
2696 /* 5940 */ GIR_EraseRootFromParent_Done,
2697 /* 5941 */ // Label 295: @5941
2698 /* 5941 */ GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(5983), // Rule ID 43 //
2699 /* 5946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2700 /* 5949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2701 /* 5953 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2702 /* 5957 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2703 /* 5961 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2704 /* 5965 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2705 /* 5969 */ // MIs[1] Operand 1
2706 /* 5969 */ // No operand predicates
2707 /* 5969 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2708 /* 5971 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2709 /* 5971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
2710 /* 5974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2711 /* 5976 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2712 /* 5978 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2713 /* 5981 */ GIR_RootConstrainSelectedInstOperands,
2714 /* 5982 */ // GIR_Coverage, 43,
2715 /* 5982 */ GIR_EraseRootFromParent_Done,
2716 /* 5983 */ // Label 296: @5983
2717 /* 5983 */ GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(6010), // Rule ID 53 //
2718 /* 5988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2719 /* 5991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2720 /* 5995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2721 /* 5999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2722 /* 6003 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2723 /* 6003 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR),
2724 /* 6008 */ GIR_RootConstrainSelectedInstOperands,
2725 /* 6009 */ // GIR_Coverage, 53,
2726 /* 6009 */ GIR_Done,
2727 /* 6010 */ // Label 297: @6010
2728 /* 6010 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(6037), // Rule ID 1065 //
2729 /* 6015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2730 /* 6018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2731 /* 6022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2732 /* 6026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2733 /* 6030 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2734 /* 6030 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR16_MM),
2735 /* 6035 */ GIR_RootConstrainSelectedInstOperands,
2736 /* 6036 */ // GIR_Coverage, 1065,
2737 /* 6036 */ GIR_Done,
2738 /* 6037 */ // Label 298: @6037
2739 /* 6037 */ GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(6064), // Rule ID 1079 //
2740 /* 6042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2741 /* 6045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2742 /* 6049 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2743 /* 6053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2744 /* 6057 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2745 /* 6057 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
2746 /* 6062 */ GIR_RootConstrainSelectedInstOperands,
2747 /* 6063 */ // GIR_Coverage, 1079,
2748 /* 6063 */ GIR_Done,
2749 /* 6064 */ // Label 299: @6064
2750 /* 6064 */ GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(6091), // Rule ID 1186 //
2751 /* 6069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2752 /* 6072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2753 /* 6076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2754 /* 6080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2755 /* 6084 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2756 /* 6084 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MMR6),
2757 /* 6089 */ GIR_RootConstrainSelectedInstOperands,
2758 /* 6090 */ // GIR_Coverage, 1186,
2759 /* 6090 */ GIR_Done,
2760 /* 6091 */ // Label 300: @6091
2761 /* 6091 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(6118), // Rule ID 1832 //
2762 /* 6096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2763 /* 6099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2764 /* 6103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2765 /* 6107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2766 /* 6111 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2767 /* 6111 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
2768 /* 6116 */ GIR_RootConstrainSelectedInstOperands,
2769 /* 6117 */ // GIR_Coverage, 1832,
2770 /* 6117 */ GIR_Done,
2771 /* 6118 */ // Label 301: @6118
2772 /* 6118 */ GIM_Reject,
2773 /* 6119 */ // Label 284: @6119
2774 /* 6119 */ GIM_Reject,
2775 /* 6120 */ // Label 278: @6120
2776 /* 6120 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(6214),
2777 /* 6125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2778 /* 6128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2779 /* 6131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2780 /* 6135 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(6190), // Rule ID 209 //
2781 /* 6140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2782 /* 6143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2783 /* 6147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2784 /* 6151 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2785 /* 6155 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2786 /* 6159 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2787 /* 6164 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2788 /* 6169 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2789 /* 6173 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2790 /* 6175 */ // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2791 /* 6175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR64),
2792 /* 6178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2793 /* 6180 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2794 /* 6184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2795 /* 6188 */ GIR_RootConstrainSelectedInstOperands,
2796 /* 6189 */ // GIR_Coverage, 209,
2797 /* 6189 */ GIR_EraseRootFromParent_Done,
2798 /* 6190 */ // Label 303: @6190
2799 /* 6190 */ GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(6213), // Rule ID 208 //
2800 /* 6195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2801 /* 6198 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2802 /* 6202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2803 /* 6206 */ // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2804 /* 6206 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR64),
2805 /* 6211 */ GIR_RootConstrainSelectedInstOperands,
2806 /* 6212 */ // GIR_Coverage, 208,
2807 /* 6212 */ GIR_Done,
2808 /* 6213 */ // Label 304: @6213
2809 /* 6213 */ GIM_Reject,
2810 /* 6214 */ // Label 302: @6214
2811 /* 6214 */ GIM_Reject,
2812 /* 6215 */ // Label 279: @6215
2813 /* 6215 */ GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(6248), // Rule ID 1040 //
2814 /* 6220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2815 /* 6223 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2816 /* 6226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2817 /* 6229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2818 /* 6233 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2819 /* 6237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2820 /* 6241 */ // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2821 /* 6241 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
2822 /* 6246 */ GIR_RootConstrainSelectedInstOperands,
2823 /* 6247 */ // GIR_Coverage, 1040,
2824 /* 6247 */ GIR_Done,
2825 /* 6248 */ // Label 305: @6248
2826 /* 6248 */ GIM_Reject,
2827 /* 6249 */ // Label 280: @6249
2828 /* 6249 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(6282), // Rule ID 1039 //
2829 /* 6254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2830 /* 6257 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2831 /* 6260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2832 /* 6263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2833 /* 6267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2834 /* 6271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2835 /* 6275 */ // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2836 /* 6275 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
2837 /* 6280 */ GIR_RootConstrainSelectedInstOperands,
2838 /* 6281 */ // GIR_Coverage, 1039,
2839 /* 6281 */ GIR_Done,
2840 /* 6282 */ // Label 306: @6282
2841 /* 6282 */ GIM_Reject,
2842 /* 6283 */ // Label 281: @6283
2843 /* 6283 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(6316), // Rule ID 1038 //
2844 /* 6288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2845 /* 6291 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2846 /* 6294 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2847 /* 6297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2848 /* 6301 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2849 /* 6305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2850 /* 6309 */ // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2851 /* 6309 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
2852 /* 6314 */ GIR_RootConstrainSelectedInstOperands,
2853 /* 6315 */ // GIR_Coverage, 1038,
2854 /* 6315 */ GIR_Done,
2855 /* 6316 */ // Label 307: @6316
2856 /* 6316 */ GIM_Reject,
2857 /* 6317 */ // Label 282: @6317
2858 /* 6317 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(6350), // Rule ID 1037 //
2859 /* 6322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2860 /* 6325 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2861 /* 6328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2862 /* 6331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2863 /* 6335 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2864 /* 6339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2865 /* 6343 */ // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2866 /* 6343 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V),
2867 /* 6348 */ GIR_RootConstrainSelectedInstOperands,
2868 /* 6349 */ // GIR_Coverage, 1037,
2869 /* 6349 */ GIR_Done,
2870 /* 6350 */ // Label 308: @6350
2871 /* 6350 */ GIM_Reject,
2872 /* 6351 */ // Label 283: @6351
2873 /* 6351 */ GIM_Reject,
2874 /* 6352 */ // Label 10: @6352
2875 /* 6352 */ GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(6424),
2876 /* 6357 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2877 /* 6360 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
2878 /* 6363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2879 /* 6366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2880 /* 6369 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(6396), // Rule ID 180 //
2881 /* 6374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode),
2882 /* 6377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
2883 /* 6381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2884 /* 6385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2885 /* 6389 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2886 /* 6389 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64),
2887 /* 6394 */ GIR_RootConstrainSelectedInstOperands,
2888 /* 6395 */ // GIR_Coverage, 180,
2889 /* 6395 */ GIR_Done,
2890 /* 6396 */ // Label 310: @6396
2891 /* 6396 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(6423), // Rule ID 181 //
2892 /* 6401 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode),
2893 /* 6404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2894 /* 6408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2895 /* 6412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2896 /* 6416 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2897 /* 6416 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_64),
2898 /* 6421 */ GIR_RootConstrainSelectedInstOperands,
2899 /* 6422 */ // GIR_Coverage, 181,
2900 /* 6422 */ GIR_Done,
2901 /* 6423 */ // Label 311: @6423
2902 /* 6423 */ GIM_Reject,
2903 /* 6424 */ // Label 309: @6424
2904 /* 6424 */ GIM_Reject,
2905 /* 6425 */ // Label 11: @6425
2906 /* 6425 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(6496),
2907 /* 6430 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2908 /* 6433 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
2909 /* 6436 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2910 /* 6439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2911 /* 6443 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(6469), // Rule ID 719 //
2912 /* 6448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
2913 /* 6451 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2914 /* 6455 */ // MIs[0] rs
2915 /* 6455 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2916 /* 6460 */ // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) => (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
2917 /* 6460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_D),
2918 /* 6463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2919 /* 6465 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2920 /* 6467 */ GIR_RootConstrainSelectedInstOperands,
2921 /* 6468 */ // GIR_Coverage, 719,
2922 /* 6468 */ GIR_EraseRootFromParent_Done,
2923 /* 6469 */ // Label 313: @6469
2924 /* 6469 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(6495), // Rule ID 721 //
2925 /* 6474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2926 /* 6477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2927 /* 6481 */ // MIs[0] fs
2928 /* 6481 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2929 /* 6486 */ // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) => (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
2930 /* 6486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
2931 /* 6489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2932 /* 6491 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2933 /* 6493 */ GIR_RootConstrainSelectedInstOperands,
2934 /* 6494 */ // GIR_Coverage, 721,
2935 /* 6494 */ GIR_EraseRootFromParent_Done,
2936 /* 6495 */ // Label 314: @6495
2937 /* 6495 */ GIM_Reject,
2938 /* 6496 */ // Label 312: @6496
2939 /* 6496 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(6587),
2940 /* 6501 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2941 /* 6504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
2942 /* 6507 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2943 /* 6510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2944 /* 6514 */ GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(6550), // Rule ID 718 //
2945 /* 6519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2946 /* 6522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2947 /* 6526 */ // MIs[0] rs
2948 /* 6526 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2949 /* 6531 */ // MIs[0] rs
2950 /* 6531 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2951 /* 6536 */ // MIs[0] rs
2952 /* 6536 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2953 /* 6541 */ // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
2954 /* 6541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_W),
2955 /* 6544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2956 /* 6546 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2957 /* 6548 */ GIR_RootConstrainSelectedInstOperands,
2958 /* 6549 */ // GIR_Coverage, 718,
2959 /* 6549 */ GIR_EraseRootFromParent_Done,
2960 /* 6550 */ // Label 316: @6550
2961 /* 6550 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(6586), // Rule ID 720 //
2962 /* 6555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2963 /* 6558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2964 /* 6562 */ // MIs[0] fs
2965 /* 6562 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2966 /* 6567 */ // MIs[0] fs
2967 /* 6567 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2968 /* 6572 */ // MIs[0] fs
2969 /* 6572 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2970 /* 6577 */ // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) => (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
2971 /* 6577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
2972 /* 6580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2973 /* 6582 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2974 /* 6584 */ GIR_RootConstrainSelectedInstOperands,
2975 /* 6585 */ // GIR_Coverage, 720,
2976 /* 6585 */ GIR_EraseRootFromParent_Done,
2977 /* 6586 */ // Label 317: @6586
2978 /* 6586 */ GIM_Reject,
2979 /* 6587 */ // Label 315: @6587
2980 /* 6587 */ GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(6656), // Rule ID 717 //
2981 /* 6592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2982 /* 6595 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
2983 /* 6598 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
2984 /* 6601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2985 /* 6604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2986 /* 6608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2987 /* 6612 */ // MIs[0] rs
2988 /* 6612 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2989 /* 6617 */ // MIs[0] rs
2990 /* 6617 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2991 /* 6622 */ // MIs[0] rs
2992 /* 6622 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2993 /* 6627 */ // MIs[0] rs
2994 /* 6627 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
2995 /* 6632 */ // MIs[0] rs
2996 /* 6632 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
2997 /* 6637 */ // MIs[0] rs
2998 /* 6637 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
2999 /* 6642 */ // MIs[0] rs
3000 /* 6642 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3001 /* 6647 */ // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
3002 /* 6647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_H),
3003 /* 6650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
3004 /* 6652 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
3005 /* 6654 */ GIR_RootConstrainSelectedInstOperands,
3006 /* 6655 */ // GIR_Coverage, 717,
3007 /* 6655 */ GIR_EraseRootFromParent_Done,
3008 /* 6656 */ // Label 318: @6656
3009 /* 6656 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(6765), // Rule ID 716 //
3010 /* 6661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
3011 /* 6664 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
3012 /* 6667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
3013 /* 6670 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3014 /* 6673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3015 /* 6677 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3016 /* 6681 */ // MIs[0] rs
3017 /* 6681 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3018 /* 6686 */ // MIs[0] rs
3019 /* 6686 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3020 /* 6691 */ // MIs[0] rs
3021 /* 6691 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3022 /* 6696 */ // MIs[0] rs
3023 /* 6696 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3024 /* 6701 */ // MIs[0] rs
3025 /* 6701 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3026 /* 6706 */ // MIs[0] rs
3027 /* 6706 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3028 /* 6711 */ // MIs[0] rs
3029 /* 6711 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3030 /* 6716 */ // MIs[0] rs
3031 /* 6716 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
3032 /* 6721 */ // MIs[0] rs
3033 /* 6721 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
3034 /* 6726 */ // MIs[0] rs
3035 /* 6726 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
3036 /* 6731 */ // MIs[0] rs
3037 /* 6731 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
3038 /* 6736 */ // MIs[0] rs
3039 /* 6736 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
3040 /* 6741 */ // MIs[0] rs
3041 /* 6741 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
3042 /* 6746 */ // MIs[0] rs
3043 /* 6746 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
3044 /* 6751 */ // MIs[0] rs
3045 /* 6751 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
3046 /* 6756 */ // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
3047 /* 6756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_B),
3048 /* 6759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
3049 /* 6761 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
3050 /* 6763 */ GIR_RootConstrainSelectedInstOperands,
3051 /* 6764 */ // GIR_Coverage, 716,
3052 /* 6764 */ GIR_EraseRootFromParent_Done,
3053 /* 6765 */ // Label 319: @6765
3054 /* 6765 */ GIM_Reject,
3055 /* 6766 */ // Label 12: @6766
3056 /* 6766 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 328*/ GIMT_Encode4(11076),
3057 /* 6777 */ /*GILLT_s32*//*Label 320*/ GIMT_Encode4(6809),
3058 /* 6781 */ /*GILLT_s64*//*Label 321*/ GIMT_Encode4(7086),
3059 /* 6785 */ /*GILLT_v2s16*//*Label 322*/ GIMT_Encode4(7142),
3060 /* 6789 */ /*GILLT_v2s64*//*Label 323*/ GIMT_Encode4(7202),
3061 /* 6793 */ /*GILLT_v4s8*//*Label 324*/ GIMT_Encode4(8337),
3062 /* 6797 */ /*GILLT_v4s32*//*Label 325*/ GIMT_Encode4(8397),
3063 /* 6801 */ /*GILLT_v8s16*//*Label 326*/ GIMT_Encode4(9466),
3064 /* 6805 */ /*GILLT_v16s8*//*Label 327*/ GIMT_Encode4(10391),
3065 /* 6809 */ // Label 320: @6809
3066 /* 6809 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(6835), // Rule ID 135 //
3067 /* 6814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3068 /* 6817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3069 /* 6820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3070 /* 6824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3071 /* 6828 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3072 /* 6828 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1),
3073 /* 6833 */ GIR_RootConstrainSelectedInstOperands,
3074 /* 6834 */ // GIR_Coverage, 135,
3075 /* 6834 */ GIR_Done,
3076 /* 6835 */ // Label 329: @6835
3077 /* 6835 */ GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(6861), // Rule ID 136 //
3078 /* 6840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3079 /* 6843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3080 /* 6846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3081 /* 6850 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3082 /* 6854 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3083 /* 6854 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1),
3084 /* 6859 */ GIR_RootConstrainSelectedInstOperands,
3085 /* 6860 */ // GIR_Coverage, 136,
3086 /* 6860 */ GIR_Done,
3087 /* 6861 */ // Label 330: @6861
3088 /* 6861 */ GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(6887), // Rule ID 1160 //
3089 /* 6866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
3090 /* 6869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3091 /* 6872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3092 /* 6876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3093 /* 6880 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3094 /* 6880 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MM),
3095 /* 6885 */ GIR_RootConstrainSelectedInstOperands,
3096 /* 6886 */ // GIR_Coverage, 1160,
3097 /* 6886 */ GIR_Done,
3098 /* 6887 */ // Label 331: @6887
3099 /* 6887 */ GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(6913), // Rule ID 1161 //
3100 /* 6892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
3101 /* 6895 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3102 /* 6898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3103 /* 6902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3104 /* 6906 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3105 /* 6906 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MM),
3106 /* 6911 */ GIR_RootConstrainSelectedInstOperands,
3107 /* 6912 */ // GIR_Coverage, 1161,
3108 /* 6912 */ GIR_Done,
3109 /* 6913 */ // Label 332: @6913
3110 /* 6913 */ GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(6939), // Rule ID 1175 //
3111 /* 6918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
3112 /* 6921 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3113 /* 6924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3114 /* 6928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3115 /* 6932 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3116 /* 6932 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MMR6),
3117 /* 6937 */ GIR_RootConstrainSelectedInstOperands,
3118 /* 6938 */ // GIR_Coverage, 1175,
3119 /* 6938 */ GIR_Done,
3120 /* 6939 */ // Label 333: @6939
3121 /* 6939 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(6965), // Rule ID 1176 //
3122 /* 6944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
3123 /* 6947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3124 /* 6950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3125 /* 6954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3126 /* 6958 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3127 /* 6958 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MMR6),
3128 /* 6963 */ GIR_RootConstrainSelectedInstOperands,
3129 /* 6964 */ // GIR_Coverage, 1176,
3130 /* 6964 */ GIR_Done,
3131 /* 6965 */ // Label 334: @6965
3132 /* 6965 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(6995), // Rule ID 1913 //
3133 /* 6970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3134 /* 6973 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
3135 /* 6976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3136 /* 6980 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3137 /* 6984 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
3138 /* 6984 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3139 /* 6989 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3140 /* 6994 */ // GIR_Coverage, 1913,
3141 /* 6994 */ GIR_Done,
3142 /* 6995 */ // Label 335: @6995
3143 /* 6995 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(7025), // Rule ID 1914 //
3144 /* 7000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3145 /* 7003 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
3146 /* 7006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3147 /* 7010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3148 /* 7014 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
3149 /* 7014 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3150 /* 7019 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3151 /* 7024 */ // GIR_Coverage, 1914,
3152 /* 7024 */ GIR_Done,
3153 /* 7025 */ // Label 336: @7025
3154 /* 7025 */ GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(7055), // Rule ID 1917 //
3155 /* 7030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3156 /* 7033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
3157 /* 7036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3158 /* 7040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3159 /* 7044 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
3160 /* 7044 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3161 /* 7049 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3162 /* 7054 */ // GIR_Coverage, 1917,
3163 /* 7054 */ GIR_Done,
3164 /* 7055 */ // Label 337: @7055
3165 /* 7055 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(7085), // Rule ID 1918 //
3166 /* 7060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3167 /* 7063 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
3168 /* 7066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3169 /* 7070 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3170 /* 7074 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
3171 /* 7074 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3172 /* 7079 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3173 /* 7084 */ // GIR_Coverage, 1918,
3174 /* 7084 */ GIR_Done,
3175 /* 7085 */ // Label 338: @7085
3176 /* 7085 */ GIM_Reject,
3177 /* 7086 */ // Label 321: @7086
3178 /* 7086 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(7141),
3179 /* 7091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
3180 /* 7094 */ GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(7117), // Rule ID 137 //
3181 /* 7099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3182 /* 7102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3183 /* 7106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3184 /* 7110 */ // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
3185 /* 7110 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMTC1),
3186 /* 7115 */ GIR_RootConstrainSelectedInstOperands,
3187 /* 7116 */ // GIR_Coverage, 137,
3188 /* 7116 */ GIR_Done,
3189 /* 7117 */ // Label 340: @7117
3190 /* 7117 */ GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(7140), // Rule ID 138 //
3191 /* 7122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3192 /* 7125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3193 /* 7129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3194 /* 7133 */ // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
3195 /* 7133 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMFC1),
3196 /* 7138 */ GIR_RootConstrainSelectedInstOperands,
3197 /* 7139 */ // GIR_Coverage, 138,
3198 /* 7139 */ GIR_Done,
3199 /* 7140 */ // Label 341: @7140
3200 /* 7140 */ GIM_Reject,
3201 /* 7141 */ // Label 339: @7141
3202 /* 7141 */ GIM_Reject,
3203 /* 7142 */ // Label 322: @7142
3204 /* 7142 */ GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(7201),
3205 /* 7147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3206 /* 7150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3207 /* 7154 */ GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(7177), // Rule ID 1915 //
3208 /* 7159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3209 /* 7162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3210 /* 7166 */ // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3211 /* 7166 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3212 /* 7171 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3213 /* 7176 */ // GIR_Coverage, 1915,
3214 /* 7176 */ GIR_Done,
3215 /* 7177 */ // Label 343: @7177
3216 /* 7177 */ GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(7200), // Rule ID 1919 //
3217 /* 7182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3218 /* 7185 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3219 /* 7189 */ // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3220 /* 7189 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3221 /* 7194 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3222 /* 7199 */ // GIR_Coverage, 1919,
3223 /* 7199 */ GIR_Done,
3224 /* 7200 */ // Label 344: @7200
3225 /* 7200 */ GIM_Reject,
3226 /* 7201 */ // Label 342: @7201
3227 /* 7201 */ GIM_Reject,
3228 /* 7202 */ // Label 323: @7202
3229 /* 7202 */ GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(7228), // Rule ID 2000 //
3230 /* 7207 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3231 /* 7210 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3232 /* 7213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3233 /* 7217 */ // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
3234 /* 7217 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3235 /* 7222 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3236 /* 7227 */ // GIR_Coverage, 2000,
3237 /* 7227 */ GIR_Done,
3238 /* 7228 */ // Label 345: @7228
3239 /* 7228 */ GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(7254), // Rule ID 2003 //
3240 /* 7233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3241 /* 7236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3242 /* 7239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3243 /* 7243 */ // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
3244 /* 7243 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3245 /* 7248 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3246 /* 7253 */ // GIR_Coverage, 2003,
3247 /* 7253 */ GIR_Done,
3248 /* 7254 */ // Label 346: @7254
3249 /* 7254 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(7280), // Rule ID 2020 //
3250 /* 7259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3251 /* 7262 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3252 /* 7265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3253 /* 7269 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3254 /* 7269 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3255 /* 7274 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3256 /* 7279 */ // GIR_Coverage, 2020,
3257 /* 7279 */ GIR_Done,
3258 /* 7280 */ // Label 347: @7280
3259 /* 7280 */ GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(7306), // Rule ID 2021 //
3260 /* 7285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3261 /* 7288 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3262 /* 7291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3263 /* 7295 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3264 /* 7295 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3265 /* 7300 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3266 /* 7305 */ // GIR_Coverage, 2021,
3267 /* 7305 */ GIR_Done,
3268 /* 7306 */ // Label 348: @7306
3269 /* 7306 */ GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(7332), // Rule ID 2022 //
3270 /* 7311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3271 /* 7314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3272 /* 7317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3273 /* 7321 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3274 /* 7321 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3275 /* 7326 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3276 /* 7331 */ // GIR_Coverage, 2022,
3277 /* 7331 */ GIR_Done,
3278 /* 7332 */ // Label 349: @7332
3279 /* 7332 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(7358), // Rule ID 2023 //
3280 /* 7337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3281 /* 7340 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3282 /* 7343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3283 /* 7347 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3284 /* 7347 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3285 /* 7352 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3286 /* 7357 */ // GIR_Coverage, 2023,
3287 /* 7357 */ GIR_Done,
3288 /* 7358 */ // Label 350: @7358
3289 /* 7358 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(7384), // Rule ID 2024 //
3290 /* 7363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3291 /* 7366 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3292 /* 7369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3293 /* 7373 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3294 /* 7373 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3295 /* 7378 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3296 /* 7383 */ // GIR_Coverage, 2024,
3297 /* 7383 */ GIR_Done,
3298 /* 7384 */ // Label 351: @7384
3299 /* 7384 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(7410), // Rule ID 2030 //
3300 /* 7389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3301 /* 7392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3302 /* 7395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3303 /* 7399 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3304 /* 7399 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3305 /* 7404 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3306 /* 7409 */ // GIR_Coverage, 2030,
3307 /* 7409 */ GIR_Done,
3308 /* 7410 */ // Label 352: @7410
3309 /* 7410 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(7436), // Rule ID 2031 //
3310 /* 7415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3311 /* 7418 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3312 /* 7421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3313 /* 7425 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3314 /* 7425 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3315 /* 7430 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3316 /* 7435 */ // GIR_Coverage, 2031,
3317 /* 7435 */ GIR_Done,
3318 /* 7436 */ // Label 353: @7436
3319 /* 7436 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(7462), // Rule ID 2032 //
3320 /* 7441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3321 /* 7444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3322 /* 7447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3323 /* 7451 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3324 /* 7451 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3325 /* 7456 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3326 /* 7461 */ // GIR_Coverage, 2032,
3327 /* 7461 */ GIR_Done,
3328 /* 7462 */ // Label 354: @7462
3329 /* 7462 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(7488), // Rule ID 2033 //
3330 /* 7467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3331 /* 7470 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3332 /* 7473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3333 /* 7477 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3334 /* 7477 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3335 /* 7482 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3336 /* 7487 */ // GIR_Coverage, 2033,
3337 /* 7487 */ GIR_Done,
3338 /* 7488 */ // Label 355: @7488
3339 /* 7488 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(7514), // Rule ID 2034 //
3340 /* 7493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3341 /* 7496 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3342 /* 7499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3343 /* 7503 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3344 /* 7503 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3345 /* 7508 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3346 /* 7513 */ // GIR_Coverage, 2034,
3347 /* 7513 */ GIR_Done,
3348 /* 7514 */ // Label 356: @7514
3349 /* 7514 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(7631), // Rule ID 2039 //
3350 /* 7519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3351 /* 7522 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3352 /* 7525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3353 /* 7529 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3354 /* 7529 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3355 /* 7532 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3356 /* 7536 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3357 /* 7541 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3358 /* 7545 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3359 /* 7550 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3360 /* 7553 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3361 /* 7557 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3362 /* 7562 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3363 /* 7565 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3364 /* 7568 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3365 /* 7570 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3366 /* 7573 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3367 /* 7577 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3368 /* 7582 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3369 /* 7585 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3370 /* 7590 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3371 /* 7593 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3372 /* 7597 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3373 /* 7602 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3374 /* 7605 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3375 /* 7615 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3376 /* 7617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3377 /* 7620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3378 /* 7622 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3379 /* 7625 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3380 /* 7630 */ // GIR_Coverage, 2039,
3381 /* 7630 */ GIR_EraseRootFromParent_Done,
3382 /* 7631 */ // Label 357: @7631
3383 /* 7631 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(7748), // Rule ID 2040 //
3384 /* 7636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3385 /* 7639 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3386 /* 7642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3387 /* 7646 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3388 /* 7646 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3389 /* 7649 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3390 /* 7653 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3391 /* 7658 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3392 /* 7662 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3393 /* 7667 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3394 /* 7670 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3395 /* 7674 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3396 /* 7679 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3397 /* 7682 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3398 /* 7685 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3399 /* 7687 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3400 /* 7690 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3401 /* 7694 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3402 /* 7699 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3403 /* 7702 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3404 /* 7707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3405 /* 7710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3406 /* 7714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3407 /* 7719 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3408 /* 7722 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3409 /* 7732 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3410 /* 7734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3411 /* 7737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3412 /* 7739 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3413 /* 7742 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3414 /* 7747 */ // GIR_Coverage, 2040,
3415 /* 7747 */ GIR_EraseRootFromParent_Done,
3416 /* 7748 */ // Label 358: @7748
3417 /* 7748 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(7818), // Rule ID 2044 //
3418 /* 7753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3419 /* 7756 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3420 /* 7759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3421 /* 7763 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3422 /* 7763 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3423 /* 7766 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3424 /* 7770 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3425 /* 7775 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3426 /* 7779 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3427 /* 7784 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3428 /* 7787 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3429 /* 7791 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3430 /* 7796 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3431 /* 7799 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3432 /* 7802 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3433 /* 7804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3434 /* 7807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3435 /* 7809 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3436 /* 7812 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3437 /* 7817 */ // GIR_Coverage, 2044,
3438 /* 7817 */ GIR_EraseRootFromParent_Done,
3439 /* 7818 */ // Label 359: @7818
3440 /* 7818 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(7888), // Rule ID 2045 //
3441 /* 7823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3442 /* 7826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3443 /* 7829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3444 /* 7833 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3445 /* 7833 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3446 /* 7836 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3447 /* 7840 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3448 /* 7845 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3449 /* 7849 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3450 /* 7854 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3451 /* 7857 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3452 /* 7861 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3453 /* 7866 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3454 /* 7869 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3455 /* 7872 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3456 /* 7874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3457 /* 7877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3458 /* 7879 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3459 /* 7882 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3460 /* 7887 */ // GIR_Coverage, 2045,
3461 /* 7887 */ GIR_EraseRootFromParent_Done,
3462 /* 7888 */ // Label 360: @7888
3463 /* 7888 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(7958), // Rule ID 2049 //
3464 /* 7893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3465 /* 7896 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3466 /* 7899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3467 /* 7903 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3468 /* 7903 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3469 /* 7906 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3470 /* 7910 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3471 /* 7915 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3472 /* 7919 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3473 /* 7924 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3474 /* 7927 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3475 /* 7931 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3476 /* 7936 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3477 /* 7939 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3478 /* 7942 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3479 /* 7944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3480 /* 7947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3481 /* 7949 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3482 /* 7952 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3483 /* 7957 */ // GIR_Coverage, 2049,
3484 /* 7957 */ GIR_EraseRootFromParent_Done,
3485 /* 7958 */ // Label 361: @7958
3486 /* 7958 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(8028), // Rule ID 2050 //
3487 /* 7963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3488 /* 7966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3489 /* 7969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3490 /* 7973 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3491 /* 7973 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3492 /* 7976 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3493 /* 7980 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3494 /* 7985 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3495 /* 7989 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3496 /* 7994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3497 /* 7997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3498 /* 8001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3499 /* 8006 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3500 /* 8009 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3501 /* 8012 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3502 /* 8014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3503 /* 8017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3504 /* 8019 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3505 /* 8022 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3506 /* 8027 */ // GIR_Coverage, 2050,
3507 /* 8027 */ GIR_EraseRootFromParent_Done,
3508 /* 8028 */ // Label 362: @8028
3509 /* 8028 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(8105), // Rule ID 2054 //
3510 /* 8033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3511 /* 8036 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3512 /* 8039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3513 /* 8043 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3514 /* 8043 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3515 /* 8046 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3516 /* 8050 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3517 /* 8055 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3518 /* 8059 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3519 /* 8064 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3520 /* 8067 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3521 /* 8071 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3522 /* 8076 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3523 /* 8079 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3524 /* 8089 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3525 /* 8091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3526 /* 8094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3527 /* 8096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3528 /* 8099 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3529 /* 8104 */ // GIR_Coverage, 2054,
3530 /* 8104 */ GIR_EraseRootFromParent_Done,
3531 /* 8105 */ // Label 363: @8105
3532 /* 8105 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(8182), // Rule ID 2055 //
3533 /* 8110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3534 /* 8113 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3535 /* 8116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3536 /* 8120 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3537 /* 8120 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3538 /* 8123 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3539 /* 8127 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3540 /* 8132 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3541 /* 8136 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3542 /* 8141 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3543 /* 8144 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3544 /* 8148 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3545 /* 8153 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3546 /* 8156 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3547 /* 8166 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3548 /* 8168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3549 /* 8171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3550 /* 8173 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3551 /* 8176 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3552 /* 8181 */ // GIR_Coverage, 2055,
3553 /* 8181 */ GIR_EraseRootFromParent_Done,
3554 /* 8182 */ // Label 364: @8182
3555 /* 8182 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(8259), // Rule ID 2059 //
3556 /* 8187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3557 /* 8190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3558 /* 8193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3559 /* 8197 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3560 /* 8197 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3561 /* 8200 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3562 /* 8204 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3563 /* 8209 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3564 /* 8213 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3565 /* 8218 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3566 /* 8221 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3567 /* 8225 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3568 /* 8230 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3569 /* 8233 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3570 /* 8243 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3571 /* 8245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3572 /* 8248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3573 /* 8250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3574 /* 8253 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3575 /* 8258 */ // GIR_Coverage, 2059,
3576 /* 8258 */ GIR_EraseRootFromParent_Done,
3577 /* 8259 */ // Label 365: @8259
3578 /* 8259 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(8336), // Rule ID 2060 //
3579 /* 8264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3580 /* 8267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3581 /* 8270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3582 /* 8274 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3583 /* 8274 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3584 /* 8277 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3585 /* 8281 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3586 /* 8286 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3587 /* 8290 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3588 /* 8295 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3589 /* 8298 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3590 /* 8302 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3591 /* 8307 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3592 /* 8310 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3593 /* 8320 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3594 /* 8322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3595 /* 8325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3596 /* 8327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3597 /* 8330 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3598 /* 8335 */ // GIR_Coverage, 2060,
3599 /* 8335 */ GIR_EraseRootFromParent_Done,
3600 /* 8336 */ // Label 366: @8336
3601 /* 8336 */ GIM_Reject,
3602 /* 8337 */ // Label 324: @8337
3603 /* 8337 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(8396),
3604 /* 8342 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3605 /* 8345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3606 /* 8349 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(8372), // Rule ID 1916 //
3607 /* 8354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3608 /* 8357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3609 /* 8361 */ // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3610 /* 8361 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3611 /* 8366 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3612 /* 8371 */ // GIR_Coverage, 1916,
3613 /* 8371 */ GIR_Done,
3614 /* 8372 */ // Label 368: @8372
3615 /* 8372 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(8395), // Rule ID 1920 //
3616 /* 8377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3617 /* 8380 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3618 /* 8384 */ // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3619 /* 8384 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3620 /* 8389 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3621 /* 8394 */ // GIR_Coverage, 1920,
3622 /* 8394 */ GIR_Done,
3623 /* 8395 */ // Label 369: @8395
3624 /* 8395 */ GIM_Reject,
3625 /* 8396 */ // Label 367: @8396
3626 /* 8396 */ GIM_Reject,
3627 /* 8397 */ // Label 325: @8397
3628 /* 8397 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(8423), // Rule ID 1999 //
3629 /* 8402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3630 /* 8405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3631 /* 8408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3632 /* 8412 */ // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3633 /* 8412 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3634 /* 8417 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3635 /* 8422 */ // GIR_Coverage, 1999,
3636 /* 8422 */ GIR_Done,
3637 /* 8423 */ // Label 370: @8423
3638 /* 8423 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(8449), // Rule ID 2002 //
3639 /* 8428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3640 /* 8431 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3641 /* 8434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3642 /* 8438 */ // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3643 /* 8438 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3644 /* 8443 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3645 /* 8448 */ // GIR_Coverage, 2002,
3646 /* 8448 */ GIR_Done,
3647 /* 8449 */ // Label 371: @8449
3648 /* 8449 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(8475), // Rule ID 2015 //
3649 /* 8454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3650 /* 8457 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3651 /* 8460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3652 /* 8464 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3653 /* 8464 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3654 /* 8469 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3655 /* 8474 */ // GIR_Coverage, 2015,
3656 /* 8474 */ GIR_Done,
3657 /* 8475 */ // Label 372: @8475
3658 /* 8475 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(8501), // Rule ID 2016 //
3659 /* 8480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3660 /* 8483 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3661 /* 8486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3662 /* 8490 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3663 /* 8490 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3664 /* 8495 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3665 /* 8500 */ // GIR_Coverage, 2016,
3666 /* 8500 */ GIR_Done,
3667 /* 8501 */ // Label 373: @8501
3668 /* 8501 */ GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(8527), // Rule ID 2017 //
3669 /* 8506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3670 /* 8509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3671 /* 8512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3672 /* 8516 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3673 /* 8516 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3674 /* 8521 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3675 /* 8526 */ // GIR_Coverage, 2017,
3676 /* 8526 */ GIR_Done,
3677 /* 8527 */ // Label 374: @8527
3678 /* 8527 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(8553), // Rule ID 2018 //
3679 /* 8532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3680 /* 8535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3681 /* 8538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3682 /* 8542 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3683 /* 8542 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3684 /* 8547 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3685 /* 8552 */ // GIR_Coverage, 2018,
3686 /* 8552 */ GIR_Done,
3687 /* 8553 */ // Label 375: @8553
3688 /* 8553 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(8579), // Rule ID 2019 //
3689 /* 8558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3690 /* 8561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3691 /* 8564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3692 /* 8568 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3693 /* 8568 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3694 /* 8573 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3695 /* 8578 */ // GIR_Coverage, 2019,
3696 /* 8578 */ GIR_Done,
3697 /* 8579 */ // Label 376: @8579
3698 /* 8579 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(8605), // Rule ID 2025 //
3699 /* 8584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3700 /* 8587 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3701 /* 8590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3702 /* 8594 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3703 /* 8594 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3704 /* 8599 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3705 /* 8604 */ // GIR_Coverage, 2025,
3706 /* 8604 */ GIR_Done,
3707 /* 8605 */ // Label 377: @8605
3708 /* 8605 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(8631), // Rule ID 2026 //
3709 /* 8610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3710 /* 8613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3711 /* 8616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3712 /* 8620 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3713 /* 8620 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3714 /* 8625 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3715 /* 8630 */ // GIR_Coverage, 2026,
3716 /* 8630 */ GIR_Done,
3717 /* 8631 */ // Label 378: @8631
3718 /* 8631 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(8657), // Rule ID 2027 //
3719 /* 8636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3720 /* 8639 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3721 /* 8642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3722 /* 8646 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3723 /* 8646 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3724 /* 8651 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3725 /* 8656 */ // GIR_Coverage, 2027,
3726 /* 8656 */ GIR_Done,
3727 /* 8657 */ // Label 379: @8657
3728 /* 8657 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(8683), // Rule ID 2028 //
3729 /* 8662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3730 /* 8665 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3731 /* 8668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3732 /* 8672 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3733 /* 8672 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3734 /* 8677 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3735 /* 8682 */ // GIR_Coverage, 2028,
3736 /* 8682 */ GIR_Done,
3737 /* 8683 */ // Label 380: @8683
3738 /* 8683 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(8709), // Rule ID 2029 //
3739 /* 8688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3740 /* 8691 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3741 /* 8694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3742 /* 8698 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3743 /* 8698 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3744 /* 8703 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3745 /* 8708 */ // GIR_Coverage, 2029,
3746 /* 8708 */ GIR_Done,
3747 /* 8709 */ // Label 381: @8709
3748 /* 8709 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(8779), // Rule ID 2037 //
3749 /* 8714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3750 /* 8717 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3751 /* 8720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3752 /* 8724 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3753 /* 8724 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3754 /* 8727 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3755 /* 8731 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3756 /* 8736 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3757 /* 8740 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3758 /* 8745 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3759 /* 8748 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3760 /* 8752 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3761 /* 8757 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3762 /* 8760 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3763 /* 8763 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3764 /* 8765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3765 /* 8768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3766 /* 8770 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3767 /* 8773 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3768 /* 8778 */ // GIR_Coverage, 2037,
3769 /* 8778 */ GIR_EraseRootFromParent_Done,
3770 /* 8779 */ // Label 382: @8779
3771 /* 8779 */ GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(8849), // Rule ID 2038 //
3772 /* 8784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3773 /* 8787 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3774 /* 8790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3775 /* 8794 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3776 /* 8794 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3777 /* 8797 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3778 /* 8801 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3779 /* 8806 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3780 /* 8810 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3781 /* 8815 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3782 /* 8818 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3783 /* 8822 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3784 /* 8827 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3785 /* 8830 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3786 /* 8833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3787 /* 8835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3788 /* 8838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3789 /* 8840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3790 /* 8843 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3791 /* 8848 */ // GIR_Coverage, 2038,
3792 /* 8848 */ GIR_EraseRootFromParent_Done,
3793 /* 8849 */ // Label 383: @8849
3794 /* 8849 */ GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(8926), // Rule ID 2042 //
3795 /* 8854 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3796 /* 8857 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3797 /* 8860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3798 /* 8864 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3799 /* 8864 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3800 /* 8867 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3801 /* 8871 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3802 /* 8876 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3803 /* 8880 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3804 /* 8885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3805 /* 8888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3806 /* 8892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3807 /* 8897 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3808 /* 8900 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3809 /* 8910 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3810 /* 8912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3811 /* 8915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3812 /* 8917 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3813 /* 8920 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3814 /* 8925 */ // GIR_Coverage, 2042,
3815 /* 8925 */ GIR_EraseRootFromParent_Done,
3816 /* 8926 */ // Label 384: @8926
3817 /* 8926 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(9003), // Rule ID 2043 //
3818 /* 8931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3819 /* 8934 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3820 /* 8937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3821 /* 8941 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3822 /* 8941 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3823 /* 8944 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3824 /* 8948 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3825 /* 8953 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3826 /* 8957 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3827 /* 8962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3828 /* 8965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3829 /* 8969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3830 /* 8974 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3831 /* 8977 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3832 /* 8987 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3833 /* 8989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3834 /* 8992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3835 /* 8994 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3836 /* 8997 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3837 /* 9002 */ // GIR_Coverage, 2043,
3838 /* 9002 */ GIR_EraseRootFromParent_Done,
3839 /* 9003 */ // Label 385: @9003
3840 /* 9003 */ GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(9080), // Rule ID 2047 //
3841 /* 9008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3842 /* 9011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3843 /* 9014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3844 /* 9018 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3845 /* 9018 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3846 /* 9021 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3847 /* 9025 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3848 /* 9030 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3849 /* 9034 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3850 /* 9039 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3851 /* 9042 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3852 /* 9046 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3853 /* 9051 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3854 /* 9054 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3855 /* 9064 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3856 /* 9066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3857 /* 9069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3858 /* 9071 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3859 /* 9074 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3860 /* 9079 */ // GIR_Coverage, 2047,
3861 /* 9079 */ GIR_EraseRootFromParent_Done,
3862 /* 9080 */ // Label 386: @9080
3863 /* 9080 */ GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(9157), // Rule ID 2048 //
3864 /* 9085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3865 /* 9088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3866 /* 9091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3867 /* 9095 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3868 /* 9095 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3869 /* 9098 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3870 /* 9102 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3871 /* 9107 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3872 /* 9111 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3873 /* 9116 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3874 /* 9119 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3875 /* 9123 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3876 /* 9128 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3877 /* 9131 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3878 /* 9141 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3879 /* 9143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3880 /* 9146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3881 /* 9148 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3882 /* 9151 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3883 /* 9156 */ // GIR_Coverage, 2048,
3884 /* 9156 */ GIR_EraseRootFromParent_Done,
3885 /* 9157 */ // Label 387: @9157
3886 /* 9157 */ GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(9234), // Rule ID 2064 //
3887 /* 9162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3888 /* 9165 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3889 /* 9168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3890 /* 9172 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3891 /* 9172 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3892 /* 9175 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3893 /* 9179 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3894 /* 9184 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3895 /* 9188 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3896 /* 9193 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3897 /* 9196 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3898 /* 9200 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3899 /* 9205 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3900 /* 9208 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3901 /* 9218 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3902 /* 9220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3903 /* 9223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3904 /* 9225 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3905 /* 9228 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3906 /* 9233 */ // GIR_Coverage, 2064,
3907 /* 9233 */ GIR_EraseRootFromParent_Done,
3908 /* 9234 */ // Label 388: @9234
3909 /* 9234 */ GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(9311), // Rule ID 2065 //
3910 /* 9239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3911 /* 9242 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3912 /* 9245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3913 /* 9249 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3914 /* 9249 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3915 /* 9252 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3916 /* 9256 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3917 /* 9261 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3918 /* 9265 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3919 /* 9270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3920 /* 9273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3921 /* 9277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3922 /* 9282 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3923 /* 9285 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3924 /* 9295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3925 /* 9297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3926 /* 9300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3927 /* 9302 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3928 /* 9305 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3929 /* 9310 */ // GIR_Coverage, 2065,
3930 /* 9310 */ GIR_EraseRootFromParent_Done,
3931 /* 9311 */ // Label 389: @9311
3932 /* 9311 */ GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(9388), // Rule ID 2069 //
3933 /* 9316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3934 /* 9319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3935 /* 9322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3936 /* 9326 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3937 /* 9326 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3938 /* 9329 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3939 /* 9333 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3940 /* 9338 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3941 /* 9342 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3942 /* 9347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3943 /* 9350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3944 /* 9354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3945 /* 9359 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3946 /* 9362 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3947 /* 9372 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3948 /* 9374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3949 /* 9377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3950 /* 9379 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3951 /* 9382 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3952 /* 9387 */ // GIR_Coverage, 2069,
3953 /* 9387 */ GIR_EraseRootFromParent_Done,
3954 /* 9388 */ // Label 390: @9388
3955 /* 9388 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(9465), // Rule ID 2070 //
3956 /* 9393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3957 /* 9396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3958 /* 9399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3959 /* 9403 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3960 /* 9403 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3961 /* 9406 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3962 /* 9410 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3963 /* 9415 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3964 /* 9419 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3965 /* 9424 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3966 /* 9427 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3967 /* 9431 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3968 /* 9436 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3969 /* 9439 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3970 /* 9449 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3971 /* 9451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3972 /* 9454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3973 /* 9456 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3974 /* 9459 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3975 /* 9464 */ // GIR_Coverage, 2070,
3976 /* 9464 */ GIR_EraseRootFromParent_Done,
3977 /* 9465 */ // Label 391: @9465
3978 /* 9465 */ GIM_Reject,
3979 /* 9466 */ // Label 326: @9466
3980 /* 9466 */ GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(9492), // Rule ID 1998 //
3981 /* 9471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3982 /* 9474 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3983 /* 9477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3984 /* 9481 */ // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3985 /* 9481 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3986 /* 9486 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3987 /* 9491 */ // GIR_Coverage, 1998,
3988 /* 9491 */ GIR_Done,
3989 /* 9492 */ // Label 392: @9492
3990 /* 9492 */ GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(9518), // Rule ID 2001 //
3991 /* 9497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3992 /* 9500 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3993 /* 9503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3994 /* 9507 */ // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3995 /* 9507 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3996 /* 9512 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3997 /* 9517 */ // GIR_Coverage, 2001,
3998 /* 9517 */ GIR_Done,
3999 /* 9518 */ // Label 393: @9518
4000 /* 9518 */ GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(9544), // Rule ID 2010 //
4001 /* 9523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4002 /* 9526 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4003 /* 9529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4004 /* 9533 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
4005 /* 9533 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4006 /* 9538 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4007 /* 9543 */ // GIR_Coverage, 2010,
4008 /* 9543 */ GIR_Done,
4009 /* 9544 */ // Label 394: @9544
4010 /* 9544 */ GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(9570), // Rule ID 2011 //
4011 /* 9549 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4012 /* 9552 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4013 /* 9555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4014 /* 9559 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
4015 /* 9559 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4016 /* 9564 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4017 /* 9569 */ // GIR_Coverage, 2011,
4018 /* 9569 */ GIR_Done,
4019 /* 9570 */ // Label 395: @9570
4020 /* 9570 */ GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(9596), // Rule ID 2012 //
4021 /* 9575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4022 /* 9578 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4023 /* 9581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4024 /* 9585 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
4025 /* 9585 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4026 /* 9590 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4027 /* 9595 */ // GIR_Coverage, 2012,
4028 /* 9595 */ GIR_Done,
4029 /* 9596 */ // Label 396: @9596
4030 /* 9596 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(9622), // Rule ID 2013 //
4031 /* 9601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4032 /* 9604 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4033 /* 9607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4034 /* 9611 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
4035 /* 9611 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4036 /* 9616 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4037 /* 9621 */ // GIR_Coverage, 2013,
4038 /* 9621 */ GIR_Done,
4039 /* 9622 */ // Label 397: @9622
4040 /* 9622 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(9648), // Rule ID 2014 //
4041 /* 9627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4042 /* 9630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4043 /* 9633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4044 /* 9637 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
4045 /* 9637 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4046 /* 9642 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4047 /* 9647 */ // GIR_Coverage, 2014,
4048 /* 9647 */ GIR_Done,
4049 /* 9648 */ // Label 398: @9648
4050 /* 9648 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(9725), // Rule ID 2035 //
4051 /* 9653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4052 /* 9656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4053 /* 9659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4054 /* 9663 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4055 /* 9663 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4056 /* 9666 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4057 /* 9670 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4058 /* 9675 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4059 /* 9679 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4060 /* 9684 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4061 /* 9687 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4062 /* 9691 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4063 /* 9696 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4064 /* 9699 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4065 /* 9709 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4066 /* 9711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4067 /* 9714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4068 /* 9716 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4069 /* 9719 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4070 /* 9724 */ // GIR_Coverage, 2035,
4071 /* 9724 */ GIR_EraseRootFromParent_Done,
4072 /* 9725 */ // Label 399: @9725
4073 /* 9725 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(9802), // Rule ID 2036 //
4074 /* 9730 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4075 /* 9733 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4076 /* 9736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4077 /* 9740 */ // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4078 /* 9740 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4079 /* 9743 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4080 /* 9747 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4081 /* 9752 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4082 /* 9756 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4083 /* 9761 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4084 /* 9764 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4085 /* 9768 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4086 /* 9773 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4087 /* 9776 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4088 /* 9786 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4089 /* 9788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4090 /* 9791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4091 /* 9793 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4092 /* 9796 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4093 /* 9801 */ // GIR_Coverage, 2036,
4094 /* 9801 */ GIR_EraseRootFromParent_Done,
4095 /* 9802 */ // Label 400: @9802
4096 /* 9802 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(9879), // Rule ID 2052 //
4097 /* 9807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4098 /* 9810 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4099 /* 9813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4100 /* 9817 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4101 /* 9817 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4102 /* 9820 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4103 /* 9824 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4104 /* 9829 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4105 /* 9833 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4106 /* 9838 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4107 /* 9841 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4108 /* 9845 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4109 /* 9850 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4110 /* 9853 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4111 /* 9863 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4112 /* 9865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4113 /* 9868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4114 /* 9870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4115 /* 9873 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4116 /* 9878 */ // GIR_Coverage, 2052,
4117 /* 9878 */ GIR_EraseRootFromParent_Done,
4118 /* 9879 */ // Label 401: @9879
4119 /* 9879 */ GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(9956), // Rule ID 2053 //
4120 /* 9884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4121 /* 9887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4122 /* 9890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4123 /* 9894 */ // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4124 /* 9894 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4125 /* 9897 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4126 /* 9901 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4127 /* 9906 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4128 /* 9910 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4129 /* 9915 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4130 /* 9918 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4131 /* 9922 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4132 /* 9927 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4133 /* 9930 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4134 /* 9940 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4135 /* 9942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4136 /* 9945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4137 /* 9947 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4138 /* 9950 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4139 /* 9955 */ // GIR_Coverage, 2053,
4140 /* 9955 */ GIR_EraseRootFromParent_Done,
4141 /* 9956 */ // Label 402: @9956
4142 /* 9956 */ GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(10033), // Rule ID 2057 //
4143 /* 9961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4144 /* 9964 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4145 /* 9967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4146 /* 9971 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4147 /* 9971 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4148 /* 9974 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4149 /* 9978 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4150 /* 9983 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4151 /* 9987 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4152 /* 9992 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4153 /* 9995 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4154 /* 9999 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4155 /* 10004 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4156 /* 10007 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4157 /* 10017 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4158 /* 10019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4159 /* 10022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4160 /* 10024 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4161 /* 10027 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4162 /* 10032 */ // GIR_Coverage, 2057,
4163 /* 10032 */ GIR_EraseRootFromParent_Done,
4164 /* 10033 */ // Label 403: @10033
4165 /* 10033 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(10110), // Rule ID 2058 //
4166 /* 10038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4167 /* 10041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4168 /* 10044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4169 /* 10048 */ // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4170 /* 10048 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4171 /* 10051 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4172 /* 10055 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4173 /* 10060 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4174 /* 10064 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4175 /* 10069 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4176 /* 10072 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4177 /* 10076 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4178 /* 10081 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4179 /* 10084 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4180 /* 10094 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4181 /* 10096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4182 /* 10099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4183 /* 10101 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4184 /* 10104 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4185 /* 10109 */ // GIR_Coverage, 2058,
4186 /* 10109 */ GIR_EraseRootFromParent_Done,
4187 /* 10110 */ // Label 404: @10110
4188 /* 10110 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(10180), // Rule ID 2062 //
4189 /* 10115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4190 /* 10118 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4191 /* 10121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4192 /* 10125 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4193 /* 10125 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4194 /* 10128 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4195 /* 10132 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4196 /* 10137 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4197 /* 10141 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4198 /* 10146 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4199 /* 10149 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4200 /* 10153 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4201 /* 10158 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4202 /* 10161 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4203 /* 10164 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4204 /* 10166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4205 /* 10169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4206 /* 10171 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4207 /* 10174 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4208 /* 10179 */ // GIR_Coverage, 2062,
4209 /* 10179 */ GIR_EraseRootFromParent_Done,
4210 /* 10180 */ // Label 405: @10180
4211 /* 10180 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(10250), // Rule ID 2063 //
4212 /* 10185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4213 /* 10188 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4214 /* 10191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4215 /* 10195 */ // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4216 /* 10195 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4217 /* 10198 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4218 /* 10202 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4219 /* 10207 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4220 /* 10211 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4221 /* 10216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4222 /* 10219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4223 /* 10223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4224 /* 10228 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4225 /* 10231 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4226 /* 10234 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4227 /* 10236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4228 /* 10239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4229 /* 10241 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4230 /* 10244 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4231 /* 10249 */ // GIR_Coverage, 2063,
4232 /* 10249 */ GIR_EraseRootFromParent_Done,
4233 /* 10250 */ // Label 406: @10250
4234 /* 10250 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(10320), // Rule ID 2067 //
4235 /* 10255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4236 /* 10258 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4237 /* 10261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4238 /* 10265 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4239 /* 10265 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4240 /* 10268 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4241 /* 10272 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4242 /* 10277 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4243 /* 10281 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4244 /* 10286 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4245 /* 10289 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4246 /* 10293 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4247 /* 10298 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4248 /* 10301 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4249 /* 10304 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4250 /* 10306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4251 /* 10309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4252 /* 10311 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4253 /* 10314 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4254 /* 10319 */ // GIR_Coverage, 2067,
4255 /* 10319 */ GIR_EraseRootFromParent_Done,
4256 /* 10320 */ // Label 407: @10320
4257 /* 10320 */ GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(10390), // Rule ID 2068 //
4258 /* 10325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4259 /* 10328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4260 /* 10331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4261 /* 10335 */ // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4262 /* 10335 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4263 /* 10338 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4264 /* 10342 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4265 /* 10347 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4266 /* 10351 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4267 /* 10356 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4268 /* 10359 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4269 /* 10363 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4270 /* 10368 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4271 /* 10371 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4272 /* 10374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4273 /* 10376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4274 /* 10379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4275 /* 10381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4276 /* 10384 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4277 /* 10389 */ // GIR_Coverage, 2068,
4278 /* 10389 */ GIR_EraseRootFromParent_Done,
4279 /* 10390 */ // Label 408: @10390
4280 /* 10390 */ GIM_Reject,
4281 /* 10391 */ // Label 327: @10391
4282 /* 10391 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(10417), // Rule ID 2004 //
4283 /* 10396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4284 /* 10399 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4285 /* 10402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4286 /* 10406 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
4287 /* 10406 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4288 /* 10411 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4289 /* 10416 */ // GIR_Coverage, 2004,
4290 /* 10416 */ GIR_Done,
4291 /* 10417 */ // Label 409: @10417
4292 /* 10417 */ GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(10443), // Rule ID 2005 //
4293 /* 10422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4294 /* 10425 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4295 /* 10428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4296 /* 10432 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
4297 /* 10432 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4298 /* 10437 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4299 /* 10442 */ // GIR_Coverage, 2005,
4300 /* 10442 */ GIR_Done,
4301 /* 10443 */ // Label 410: @10443
4302 /* 10443 */ GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(10469), // Rule ID 2006 //
4303 /* 10448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4304 /* 10451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4305 /* 10454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4306 /* 10458 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
4307 /* 10458 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4308 /* 10463 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4309 /* 10468 */ // GIR_Coverage, 2006,
4310 /* 10468 */ GIR_Done,
4311 /* 10469 */ // Label 411: @10469
4312 /* 10469 */ GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(10495), // Rule ID 2007 //
4313 /* 10474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4314 /* 10477 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4315 /* 10480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4316 /* 10484 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4317 /* 10484 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4318 /* 10489 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4319 /* 10494 */ // GIR_Coverage, 2007,
4320 /* 10494 */ GIR_Done,
4321 /* 10495 */ // Label 412: @10495
4322 /* 10495 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(10521), // Rule ID 2008 //
4323 /* 10500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4324 /* 10503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4325 /* 10506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4326 /* 10510 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4327 /* 10510 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4328 /* 10515 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4329 /* 10520 */ // GIR_Coverage, 2008,
4330 /* 10520 */ GIR_Done,
4331 /* 10521 */ // Label 413: @10521
4332 /* 10521 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(10547), // Rule ID 2009 //
4333 /* 10526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4334 /* 10529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4335 /* 10532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4336 /* 10536 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4337 /* 10536 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4338 /* 10541 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4339 /* 10546 */ // GIR_Coverage, 2009,
4340 /* 10546 */ GIR_Done,
4341 /* 10547 */ // Label 414: @10547
4342 /* 10547 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(10624), // Rule ID 2041 //
4343 /* 10552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4344 /* 10555 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4345 /* 10558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4346 /* 10562 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4347 /* 10562 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4348 /* 10565 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4349 /* 10569 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4350 /* 10574 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4351 /* 10578 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4352 /* 10583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4353 /* 10586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4354 /* 10590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4355 /* 10595 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4356 /* 10598 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4357 /* 10608 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4358 /* 10610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4359 /* 10613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4360 /* 10615 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4361 /* 10618 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4362 /* 10623 */ // GIR_Coverage, 2041,
4363 /* 10623 */ GIR_EraseRootFromParent_Done,
4364 /* 10624 */ // Label 415: @10624
4365 /* 10624 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(10701), // Rule ID 2046 //
4366 /* 10629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4367 /* 10632 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4368 /* 10635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4369 /* 10639 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4370 /* 10639 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4371 /* 10642 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4372 /* 10646 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4373 /* 10651 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4374 /* 10655 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4375 /* 10660 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4376 /* 10663 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4377 /* 10667 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4378 /* 10672 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4379 /* 10675 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4380 /* 10685 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4381 /* 10687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4382 /* 10690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4383 /* 10692 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4384 /* 10695 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4385 /* 10700 */ // GIR_Coverage, 2046,
4386 /* 10700 */ GIR_EraseRootFromParent_Done,
4387 /* 10701 */ // Label 416: @10701
4388 /* 10701 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(10771), // Rule ID 2051 //
4389 /* 10706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4390 /* 10709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4391 /* 10712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4392 /* 10716 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4393 /* 10716 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4394 /* 10719 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4395 /* 10723 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4396 /* 10728 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4397 /* 10732 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4398 /* 10737 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4399 /* 10740 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4400 /* 10744 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4401 /* 10749 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4402 /* 10752 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4403 /* 10755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4404 /* 10757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4405 /* 10760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4406 /* 10762 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4407 /* 10765 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4408 /* 10770 */ // GIR_Coverage, 2051,
4409 /* 10770 */ GIR_EraseRootFromParent_Done,
4410 /* 10771 */ // Label 417: @10771
4411 /* 10771 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(10841), // Rule ID 2056 //
4412 /* 10776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4413 /* 10779 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4414 /* 10782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4415 /* 10786 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4416 /* 10786 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4417 /* 10789 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4418 /* 10793 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4419 /* 10798 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4420 /* 10802 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4421 /* 10807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4422 /* 10810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4423 /* 10814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4424 /* 10819 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4425 /* 10822 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4426 /* 10825 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4427 /* 10827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4428 /* 10830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4429 /* 10832 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4430 /* 10835 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4431 /* 10840 */ // GIR_Coverage, 2056,
4432 /* 10840 */ GIR_EraseRootFromParent_Done,
4433 /* 10841 */ // Label 418: @10841
4434 /* 10841 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(10958), // Rule ID 2061 //
4435 /* 10846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4436 /* 10849 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4437 /* 10852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4438 /* 10856 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4439 /* 10856 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4440 /* 10859 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4441 /* 10863 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4442 /* 10868 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4443 /* 10872 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4444 /* 10877 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4445 /* 10880 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4446 /* 10884 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4447 /* 10889 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4448 /* 10892 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4449 /* 10895 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4450 /* 10897 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4451 /* 10900 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4452 /* 10904 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4453 /* 10909 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4454 /* 10912 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4455 /* 10917 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4456 /* 10920 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4457 /* 10924 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4458 /* 10929 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4459 /* 10932 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4460 /* 10942 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4461 /* 10944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4462 /* 10947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4463 /* 10949 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4464 /* 10952 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4465 /* 10957 */ // GIR_Coverage, 2061,
4466 /* 10957 */ GIR_EraseRootFromParent_Done,
4467 /* 10958 */ // Label 419: @10958
4468 /* 10958 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(11075), // Rule ID 2066 //
4469 /* 10963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4470 /* 10966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4471 /* 10969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4472 /* 10973 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4473 /* 10973 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4474 /* 10976 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4475 /* 10980 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4476 /* 10985 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4477 /* 10989 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4478 /* 10994 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4479 /* 10997 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4480 /* 11001 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4481 /* 11006 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4482 /* 11009 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4483 /* 11012 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4484 /* 11014 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4485 /* 11017 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4486 /* 11021 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4487 /* 11026 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4488 /* 11029 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4489 /* 11034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4490 /* 11037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4491 /* 11041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4492 /* 11046 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4493 /* 11049 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4494 /* 11059 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4495 /* 11061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4496 /* 11064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4497 /* 11066 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4498 /* 11069 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4499 /* 11074 */ // GIR_Coverage, 2066,
4500 /* 11074 */ GIR_EraseRootFromParent_Done,
4501 /* 11075 */ // Label 420: @11075
4502 /* 11075 */ GIM_Reject,
4503 /* 11076 */ // Label 328: @11076
4504 /* 11076 */ GIM_Reject,
4505 /* 11077 */ // Label 13: @11077
4506 /* 11077 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(11141), // Rule ID 1989 //
4507 /* 11082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4508 /* 11085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4509 /* 11088 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4510 /* 11091 */ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4511 /* 11095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4512 /* 11099 */ // MIs[0] Operand 1
4513 /* 11099 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4514 /* 11103 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4515 /* 11107 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4516 /* 11111 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4517 /* 11115 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4518 /* 11119 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4519 /* 11121 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4520 /* 11121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
4521 /* 11124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4522 /* 11126 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4523 /* 11130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4524 /* 11134 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4525 /* 11139 */ GIR_RootConstrainSelectedInstOperands,
4526 /* 11140 */ // GIR_Coverage, 1989,
4527 /* 11140 */ GIR_EraseRootFromParent_Done,
4528 /* 11141 */ // Label 421: @11141
4529 /* 11141 */ GIM_Reject,
4530 /* 11142 */ // Label 14: @11142
4531 /* 11142 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(11209), // Rule ID 1988 //
4532 /* 11147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4533 /* 11150 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4534 /* 11153 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4535 /* 11156 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4536 /* 11163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4537 /* 11167 */ // MIs[0] Operand 1
4538 /* 11167 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4539 /* 11171 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4540 /* 11175 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4541 /* 11179 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4542 /* 11183 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4543 /* 11187 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4544 /* 11189 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4545 /* 11189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
4546 /* 11192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4547 /* 11194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4548 /* 11198 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4549 /* 11202 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4550 /* 11207 */ GIR_RootConstrainSelectedInstOperands,
4551 /* 11208 */ // GIR_Coverage, 1988,
4552 /* 11208 */ GIR_EraseRootFromParent_Done,
4553 /* 11209 */ // Label 422: @11209
4554 /* 11209 */ GIM_Reject,
4555 /* 11210 */ // Label 15: @11210
4556 /* 11210 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(11277), // Rule ID 1987 //
4557 /* 11215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4558 /* 11218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4559 /* 11221 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4560 /* 11224 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4561 /* 11231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4562 /* 11235 */ // MIs[0] Operand 1
4563 /* 11235 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4564 /* 11239 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4565 /* 11243 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4566 /* 11247 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4567 /* 11251 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4568 /* 11255 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4569 /* 11257 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4570 /* 11257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
4571 /* 11260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4572 /* 11262 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4573 /* 11266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4574 /* 11270 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4575 /* 11275 */ GIR_RootConstrainSelectedInstOperands,
4576 /* 11276 */ // GIR_Coverage, 1987,
4577 /* 11276 */ GIR_EraseRootFromParent_Done,
4578 /* 11277 */ // Label 423: @11277
4579 /* 11277 */ GIM_Reject,
4580 /* 11278 */ // Label 16: @11278
4581 /* 11278 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 426*/ GIMT_Encode4(11469),
4582 /* 11289 */ /*GILLT_s32*//*Label 424*/ GIMT_Encode4(11297),
4583 /* 11293 */ /*GILLT_s64*//*Label 425*/ GIMT_Encode4(11424),
4584 /* 11297 */ // Label 424: @11297
4585 /* 11297 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(11423),
4586 /* 11302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4587 /* 11305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
4588 /* 11308 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(11346), // Rule ID 25 //
4589 /* 11313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4590 /* 11316 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4591 /* 11323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4592 /* 11327 */ // MIs[0] ptr
4593 /* 11327 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4594 /* 11331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4595 /* 11335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4596 /* 11339 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i8>> => (ATOMIC_CMP_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4597 /* 11339 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I8),
4598 /* 11344 */ GIR_RootConstrainSelectedInstOperands,
4599 /* 11345 */ // GIR_Coverage, 25,
4600 /* 11345 */ GIR_Done,
4601 /* 11346 */ // Label 428: @11346
4602 /* 11346 */ GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(11384), // Rule ID 26 //
4603 /* 11351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4604 /* 11354 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4605 /* 11361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4606 /* 11365 */ // MIs[0] ptr
4607 /* 11365 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4608 /* 11369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4609 /* 11373 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4610 /* 11377 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i16>> => (ATOMIC_CMP_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4611 /* 11377 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I16),
4612 /* 11382 */ GIR_RootConstrainSelectedInstOperands,
4613 /* 11383 */ // GIR_Coverage, 26,
4614 /* 11383 */ GIR_Done,
4615 /* 11384 */ // Label 429: @11384
4616 /* 11384 */ GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(11422), // Rule ID 27 //
4617 /* 11389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4618 /* 11392 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4619 /* 11399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4620 /* 11403 */ // MIs[0] ptr
4621 /* 11403 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4622 /* 11407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4623 /* 11411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4624 /* 11415 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i32>> => (ATOMIC_CMP_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4625 /* 11415 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I32),
4626 /* 11420 */ GIR_RootConstrainSelectedInstOperands,
4627 /* 11421 */ // GIR_Coverage, 27,
4628 /* 11421 */ GIR_Done,
4629 /* 11422 */ // Label 430: @11422
4630 /* 11422 */ GIM_Reject,
4631 /* 11423 */ // Label 427: @11423
4632 /* 11423 */ GIM_Reject,
4633 /* 11424 */ // Label 425: @11424
4634 /* 11424 */ GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(11468), // Rule ID 191 //
4635 /* 11429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4636 /* 11432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4637 /* 11435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
4638 /* 11438 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4639 /* 11445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4640 /* 11449 */ // MIs[0] ptr
4641 /* 11449 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4642 /* 11453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4643 /* 11457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4644 /* 11461 */ // (atomic_cmp_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_i64>> => (ATOMIC_CMP_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)
4645 /* 11461 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I64),
4646 /* 11466 */ GIR_RootConstrainSelectedInstOperands,
4647 /* 11467 */ // GIR_Coverage, 191,
4648 /* 11467 */ GIR_Done,
4649 /* 11468 */ // Label 431: @11468
4650 /* 11468 */ GIM_Reject,
4651 /* 11469 */ // Label 426: @11469
4652 /* 11469 */ GIM_Reject,
4653 /* 11470 */ // Label 17: @11470
4654 /* 11470 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 434*/ GIMT_Encode4(11639),
4655 /* 11481 */ /*GILLT_s32*//*Label 432*/ GIMT_Encode4(11489),
4656 /* 11485 */ /*GILLT_s64*//*Label 433*/ GIMT_Encode4(11601),
4657 /* 11489 */ // Label 432: @11489
4658 /* 11489 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(11600),
4659 /* 11494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4660 /* 11497 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(11531), // Rule ID 22 //
4661 /* 11502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4662 /* 11505 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4663 /* 11512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4664 /* 11516 */ // MIs[0] ptr
4665 /* 11516 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4666 /* 11520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4667 /* 11524 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i8>> => (ATOMIC_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4668 /* 11524 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I8),
4669 /* 11529 */ GIR_RootConstrainSelectedInstOperands,
4670 /* 11530 */ // GIR_Coverage, 22,
4671 /* 11530 */ GIR_Done,
4672 /* 11531 */ // Label 436: @11531
4673 /* 11531 */ GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(11565), // Rule ID 23 //
4674 /* 11536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4675 /* 11539 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4676 /* 11546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4677 /* 11550 */ // MIs[0] ptr
4678 /* 11550 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4679 /* 11554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4680 /* 11558 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i16>> => (ATOMIC_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4681 /* 11558 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I16),
4682 /* 11563 */ GIR_RootConstrainSelectedInstOperands,
4683 /* 11564 */ // GIR_Coverage, 23,
4684 /* 11564 */ GIR_Done,
4685 /* 11565 */ // Label 437: @11565
4686 /* 11565 */ GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(11599), // Rule ID 24 //
4687 /* 11570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4688 /* 11573 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4689 /* 11580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4690 /* 11584 */ // MIs[0] ptr
4691 /* 11584 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4692 /* 11588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4693 /* 11592 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i32>> => (ATOMIC_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4694 /* 11592 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I32),
4695 /* 11597 */ GIR_RootConstrainSelectedInstOperands,
4696 /* 11598 */ // GIR_Coverage, 24,
4697 /* 11598 */ GIR_Done,
4698 /* 11599 */ // Label 438: @11599
4699 /* 11599 */ GIM_Reject,
4700 /* 11600 */ // Label 435: @11600
4701 /* 11600 */ GIM_Reject,
4702 /* 11601 */ // Label 433: @11601
4703 /* 11601 */ GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(11638), // Rule ID 190 //
4704 /* 11606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4705 /* 11609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4706 /* 11612 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4707 /* 11619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4708 /* 11623 */ // MIs[0] ptr
4709 /* 11623 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4710 /* 11627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4711 /* 11631 */ // (atomic_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_swap_i64>> => (ATOMIC_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4712 /* 11631 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I64),
4713 /* 11636 */ GIR_RootConstrainSelectedInstOperands,
4714 /* 11637 */ // GIR_Coverage, 190,
4715 /* 11637 */ GIR_Done,
4716 /* 11638 */ // Label 439: @11638
4717 /* 11638 */ GIM_Reject,
4718 /* 11639 */ // Label 434: @11639
4719 /* 11639 */ GIM_Reject,
4720 /* 11640 */ // Label 18: @11640
4721 /* 11640 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 442*/ GIMT_Encode4(11809),
4722 /* 11651 */ /*GILLT_s32*//*Label 440*/ GIMT_Encode4(11659),
4723 /* 11655 */ /*GILLT_s64*//*Label 441*/ GIMT_Encode4(11771),
4724 /* 11659 */ // Label 440: @11659
4725 /* 11659 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(11770),
4726 /* 11664 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4727 /* 11667 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(11701), // Rule ID 4 //
4728 /* 11672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4729 /* 11675 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4730 /* 11682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4731 /* 11686 */ // MIs[0] ptr
4732 /* 11686 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4733 /* 11690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4734 /* 11694 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i8>> => (ATOMIC_LOAD_ADD_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4735 /* 11694 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I8),
4736 /* 11699 */ GIR_RootConstrainSelectedInstOperands,
4737 /* 11700 */ // GIR_Coverage, 4,
4738 /* 11700 */ GIR_Done,
4739 /* 11701 */ // Label 444: @11701
4740 /* 11701 */ GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(11735), // Rule ID 5 //
4741 /* 11706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4742 /* 11709 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4743 /* 11716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4744 /* 11720 */ // MIs[0] ptr
4745 /* 11720 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4746 /* 11724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4747 /* 11728 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i16>> => (ATOMIC_LOAD_ADD_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4748 /* 11728 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I16),
4749 /* 11733 */ GIR_RootConstrainSelectedInstOperands,
4750 /* 11734 */ // GIR_Coverage, 5,
4751 /* 11734 */ GIR_Done,
4752 /* 11735 */ // Label 445: @11735
4753 /* 11735 */ GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(11769), // Rule ID 6 //
4754 /* 11740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4755 /* 11743 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4756 /* 11750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4757 /* 11754 */ // MIs[0] ptr
4758 /* 11754 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4759 /* 11758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4760 /* 11762 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i32>> => (ATOMIC_LOAD_ADD_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4761 /* 11762 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I32),
4762 /* 11767 */ GIR_RootConstrainSelectedInstOperands,
4763 /* 11768 */ // GIR_Coverage, 6,
4764 /* 11768 */ GIR_Done,
4765 /* 11769 */ // Label 446: @11769
4766 /* 11769 */ GIM_Reject,
4767 /* 11770 */ // Label 443: @11770
4768 /* 11770 */ GIM_Reject,
4769 /* 11771 */ // Label 441: @11771
4770 /* 11771 */ GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(11808), // Rule ID 184 //
4771 /* 11776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4772 /* 11779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4773 /* 11782 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4774 /* 11789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4775 /* 11793 */ // MIs[0] ptr
4776 /* 11793 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4777 /* 11797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4778 /* 11801 */ // (atomic_load_add:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_add_i64>> => (ATOMIC_LOAD_ADD_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4779 /* 11801 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I64),
4780 /* 11806 */ GIR_RootConstrainSelectedInstOperands,
4781 /* 11807 */ // GIR_Coverage, 184,
4782 /* 11807 */ GIR_Done,
4783 /* 11808 */ // Label 447: @11808
4784 /* 11808 */ GIM_Reject,
4785 /* 11809 */ // Label 442: @11809
4786 /* 11809 */ GIM_Reject,
4787 /* 11810 */ // Label 19: @11810
4788 /* 11810 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 450*/ GIMT_Encode4(11979),
4789 /* 11821 */ /*GILLT_s32*//*Label 448*/ GIMT_Encode4(11829),
4790 /* 11825 */ /*GILLT_s64*//*Label 449*/ GIMT_Encode4(11941),
4791 /* 11829 */ // Label 448: @11829
4792 /* 11829 */ GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(11940),
4793 /* 11834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4794 /* 11837 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(11871), // Rule ID 7 //
4795 /* 11842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4796 /* 11845 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4797 /* 11852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4798 /* 11856 */ // MIs[0] ptr
4799 /* 11856 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4800 /* 11860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4801 /* 11864 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i8>> => (ATOMIC_LOAD_SUB_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4802 /* 11864 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I8),
4803 /* 11869 */ GIR_RootConstrainSelectedInstOperands,
4804 /* 11870 */ // GIR_Coverage, 7,
4805 /* 11870 */ GIR_Done,
4806 /* 11871 */ // Label 452: @11871
4807 /* 11871 */ GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(11905), // Rule ID 8 //
4808 /* 11876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4809 /* 11879 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4810 /* 11886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4811 /* 11890 */ // MIs[0] ptr
4812 /* 11890 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4813 /* 11894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4814 /* 11898 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i16>> => (ATOMIC_LOAD_SUB_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4815 /* 11898 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I16),
4816 /* 11903 */ GIR_RootConstrainSelectedInstOperands,
4817 /* 11904 */ // GIR_Coverage, 8,
4818 /* 11904 */ GIR_Done,
4819 /* 11905 */ // Label 453: @11905
4820 /* 11905 */ GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(11939), // Rule ID 9 //
4821 /* 11910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4822 /* 11913 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4823 /* 11920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4824 /* 11924 */ // MIs[0] ptr
4825 /* 11924 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4826 /* 11928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4827 /* 11932 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i32>> => (ATOMIC_LOAD_SUB_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4828 /* 11932 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I32),
4829 /* 11937 */ GIR_RootConstrainSelectedInstOperands,
4830 /* 11938 */ // GIR_Coverage, 9,
4831 /* 11938 */ GIR_Done,
4832 /* 11939 */ // Label 454: @11939
4833 /* 11939 */ GIM_Reject,
4834 /* 11940 */ // Label 451: @11940
4835 /* 11940 */ GIM_Reject,
4836 /* 11941 */ // Label 449: @11941
4837 /* 11941 */ GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(11978), // Rule ID 185 //
4838 /* 11946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4839 /* 11949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4840 /* 11952 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4841 /* 11959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4842 /* 11963 */ // MIs[0] ptr
4843 /* 11963 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4844 /* 11967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4845 /* 11971 */ // (atomic_load_sub:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_i64>> => (ATOMIC_LOAD_SUB_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4846 /* 11971 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I64),
4847 /* 11976 */ GIR_RootConstrainSelectedInstOperands,
4848 /* 11977 */ // GIR_Coverage, 185,
4849 /* 11977 */ GIR_Done,
4850 /* 11978 */ // Label 455: @11978
4851 /* 11978 */ GIM_Reject,
4852 /* 11979 */ // Label 450: @11979
4853 /* 11979 */ GIM_Reject,
4854 /* 11980 */ // Label 20: @11980
4855 /* 11980 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 458*/ GIMT_Encode4(12149),
4856 /* 11991 */ /*GILLT_s32*//*Label 456*/ GIMT_Encode4(11999),
4857 /* 11995 */ /*GILLT_s64*//*Label 457*/ GIMT_Encode4(12111),
4858 /* 11999 */ // Label 456: @11999
4859 /* 11999 */ GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(12110),
4860 /* 12004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4861 /* 12007 */ GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(12041), // Rule ID 10 //
4862 /* 12012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4863 /* 12015 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4864 /* 12022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4865 /* 12026 */ // MIs[0] ptr
4866 /* 12026 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4867 /* 12030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4868 /* 12034 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i8>> => (ATOMIC_LOAD_AND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4869 /* 12034 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I8),
4870 /* 12039 */ GIR_RootConstrainSelectedInstOperands,
4871 /* 12040 */ // GIR_Coverage, 10,
4872 /* 12040 */ GIR_Done,
4873 /* 12041 */ // Label 460: @12041
4874 /* 12041 */ GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(12075), // Rule ID 11 //
4875 /* 12046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4876 /* 12049 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4877 /* 12056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4878 /* 12060 */ // MIs[0] ptr
4879 /* 12060 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4880 /* 12064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4881 /* 12068 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i16>> => (ATOMIC_LOAD_AND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4882 /* 12068 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I16),
4883 /* 12073 */ GIR_RootConstrainSelectedInstOperands,
4884 /* 12074 */ // GIR_Coverage, 11,
4885 /* 12074 */ GIR_Done,
4886 /* 12075 */ // Label 461: @12075
4887 /* 12075 */ GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(12109), // Rule ID 12 //
4888 /* 12080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4889 /* 12083 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4890 /* 12090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4891 /* 12094 */ // MIs[0] ptr
4892 /* 12094 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4893 /* 12098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4894 /* 12102 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i32>> => (ATOMIC_LOAD_AND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4895 /* 12102 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I32),
4896 /* 12107 */ GIR_RootConstrainSelectedInstOperands,
4897 /* 12108 */ // GIR_Coverage, 12,
4898 /* 12108 */ GIR_Done,
4899 /* 12109 */ // Label 462: @12109
4900 /* 12109 */ GIM_Reject,
4901 /* 12110 */ // Label 459: @12110
4902 /* 12110 */ GIM_Reject,
4903 /* 12111 */ // Label 457: @12111
4904 /* 12111 */ GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(12148), // Rule ID 186 //
4905 /* 12116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4906 /* 12119 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4907 /* 12122 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4908 /* 12129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4909 /* 12133 */ // MIs[0] ptr
4910 /* 12133 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4911 /* 12137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4912 /* 12141 */ // (atomic_load_and:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_and_i64>> => (ATOMIC_LOAD_AND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4913 /* 12141 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I64),
4914 /* 12146 */ GIR_RootConstrainSelectedInstOperands,
4915 /* 12147 */ // GIR_Coverage, 186,
4916 /* 12147 */ GIR_Done,
4917 /* 12148 */ // Label 463: @12148
4918 /* 12148 */ GIM_Reject,
4919 /* 12149 */ // Label 458: @12149
4920 /* 12149 */ GIM_Reject,
4921 /* 12150 */ // Label 21: @12150
4922 /* 12150 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 466*/ GIMT_Encode4(12319),
4923 /* 12161 */ /*GILLT_s32*//*Label 464*/ GIMT_Encode4(12169),
4924 /* 12165 */ /*GILLT_s64*//*Label 465*/ GIMT_Encode4(12281),
4925 /* 12169 */ // Label 464: @12169
4926 /* 12169 */ GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(12280),
4927 /* 12174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4928 /* 12177 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(12211), // Rule ID 19 //
4929 /* 12182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4930 /* 12185 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4931 /* 12192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4932 /* 12196 */ // MIs[0] ptr
4933 /* 12196 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4934 /* 12200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4935 /* 12204 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i8>> => (ATOMIC_LOAD_NAND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4936 /* 12204 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I8),
4937 /* 12209 */ GIR_RootConstrainSelectedInstOperands,
4938 /* 12210 */ // GIR_Coverage, 19,
4939 /* 12210 */ GIR_Done,
4940 /* 12211 */ // Label 468: @12211
4941 /* 12211 */ GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(12245), // Rule ID 20 //
4942 /* 12216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4943 /* 12219 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4944 /* 12226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4945 /* 12230 */ // MIs[0] ptr
4946 /* 12230 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4947 /* 12234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4948 /* 12238 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i16>> => (ATOMIC_LOAD_NAND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4949 /* 12238 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I16),
4950 /* 12243 */ GIR_RootConstrainSelectedInstOperands,
4951 /* 12244 */ // GIR_Coverage, 20,
4952 /* 12244 */ GIR_Done,
4953 /* 12245 */ // Label 469: @12245
4954 /* 12245 */ GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(12279), // Rule ID 21 //
4955 /* 12250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4956 /* 12253 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4957 /* 12260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4958 /* 12264 */ // MIs[0] ptr
4959 /* 12264 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4960 /* 12268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4961 /* 12272 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>> => (ATOMIC_LOAD_NAND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4962 /* 12272 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I32),
4963 /* 12277 */ GIR_RootConstrainSelectedInstOperands,
4964 /* 12278 */ // GIR_Coverage, 21,
4965 /* 12278 */ GIR_Done,
4966 /* 12279 */ // Label 470: @12279
4967 /* 12279 */ GIM_Reject,
4968 /* 12280 */ // Label 467: @12280
4969 /* 12280 */ GIM_Reject,
4970 /* 12281 */ // Label 465: @12281
4971 /* 12281 */ GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(12318), // Rule ID 189 //
4972 /* 12286 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4973 /* 12289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4974 /* 12292 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4975 /* 12299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4976 /* 12303 */ // MIs[0] ptr
4977 /* 12303 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4978 /* 12307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4979 /* 12311 */ // (atomic_load_nand:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_i64>> => (ATOMIC_LOAD_NAND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4980 /* 12311 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I64),
4981 /* 12316 */ GIR_RootConstrainSelectedInstOperands,
4982 /* 12317 */ // GIR_Coverage, 189,
4983 /* 12317 */ GIR_Done,
4984 /* 12318 */ // Label 471: @12318
4985 /* 12318 */ GIM_Reject,
4986 /* 12319 */ // Label 466: @12319
4987 /* 12319 */ GIM_Reject,
4988 /* 12320 */ // Label 22: @12320
4989 /* 12320 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 474*/ GIMT_Encode4(12489),
4990 /* 12331 */ /*GILLT_s32*//*Label 472*/ GIMT_Encode4(12339),
4991 /* 12335 */ /*GILLT_s64*//*Label 473*/ GIMT_Encode4(12451),
4992 /* 12339 */ // Label 472: @12339
4993 /* 12339 */ GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(12450),
4994 /* 12344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4995 /* 12347 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(12381), // Rule ID 13 //
4996 /* 12352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4997 /* 12355 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4998 /* 12362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4999 /* 12366 */ // MIs[0] ptr
5000 /* 12366 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5001 /* 12370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5002 /* 12374 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i8>> => (ATOMIC_LOAD_OR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5003 /* 12374 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I8),
5004 /* 12379 */ GIR_RootConstrainSelectedInstOperands,
5005 /* 12380 */ // GIR_Coverage, 13,
5006 /* 12380 */ GIR_Done,
5007 /* 12381 */ // Label 476: @12381
5008 /* 12381 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(12415), // Rule ID 14 //
5009 /* 12386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5010 /* 12389 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5011 /* 12396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5012 /* 12400 */ // MIs[0] ptr
5013 /* 12400 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5014 /* 12404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5015 /* 12408 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i16>> => (ATOMIC_LOAD_OR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5016 /* 12408 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I16),
5017 /* 12413 */ GIR_RootConstrainSelectedInstOperands,
5018 /* 12414 */ // GIR_Coverage, 14,
5019 /* 12414 */ GIR_Done,
5020 /* 12415 */ // Label 477: @12415
5021 /* 12415 */ GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(12449), // Rule ID 15 //
5022 /* 12420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5023 /* 12423 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5024 /* 12430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5025 /* 12434 */ // MIs[0] ptr
5026 /* 12434 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5027 /* 12438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5028 /* 12442 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i32>> => (ATOMIC_LOAD_OR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5029 /* 12442 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I32),
5030 /* 12447 */ GIR_RootConstrainSelectedInstOperands,
5031 /* 12448 */ // GIR_Coverage, 15,
5032 /* 12448 */ GIR_Done,
5033 /* 12449 */ // Label 478: @12449
5034 /* 12449 */ GIM_Reject,
5035 /* 12450 */ // Label 475: @12450
5036 /* 12450 */ GIM_Reject,
5037 /* 12451 */ // Label 473: @12451
5038 /* 12451 */ GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(12488), // Rule ID 187 //
5039 /* 12456 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5040 /* 12459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5041 /* 12462 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5042 /* 12469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5043 /* 12473 */ // MIs[0] ptr
5044 /* 12473 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5045 /* 12477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5046 /* 12481 */ // (atomic_load_or:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_or_i64>> => (ATOMIC_LOAD_OR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5047 /* 12481 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I64),
5048 /* 12486 */ GIR_RootConstrainSelectedInstOperands,
5049 /* 12487 */ // GIR_Coverage, 187,
5050 /* 12487 */ GIR_Done,
5051 /* 12488 */ // Label 479: @12488
5052 /* 12488 */ GIM_Reject,
5053 /* 12489 */ // Label 474: @12489
5054 /* 12489 */ GIM_Reject,
5055 /* 12490 */ // Label 23: @12490
5056 /* 12490 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 482*/ GIMT_Encode4(12659),
5057 /* 12501 */ /*GILLT_s32*//*Label 480*/ GIMT_Encode4(12509),
5058 /* 12505 */ /*GILLT_s64*//*Label 481*/ GIMT_Encode4(12621),
5059 /* 12509 */ // Label 480: @12509
5060 /* 12509 */ GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(12620),
5061 /* 12514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5062 /* 12517 */ GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(12551), // Rule ID 16 //
5063 /* 12522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5064 /* 12525 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5065 /* 12532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5066 /* 12536 */ // MIs[0] ptr
5067 /* 12536 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5068 /* 12540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5069 /* 12544 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i8>> => (ATOMIC_LOAD_XOR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5070 /* 12544 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I8),
5071 /* 12549 */ GIR_RootConstrainSelectedInstOperands,
5072 /* 12550 */ // GIR_Coverage, 16,
5073 /* 12550 */ GIR_Done,
5074 /* 12551 */ // Label 484: @12551
5075 /* 12551 */ GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(12585), // Rule ID 17 //
5076 /* 12556 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5077 /* 12559 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5078 /* 12566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5079 /* 12570 */ // MIs[0] ptr
5080 /* 12570 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5081 /* 12574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5082 /* 12578 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i16>> => (ATOMIC_LOAD_XOR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5083 /* 12578 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I16),
5084 /* 12583 */ GIR_RootConstrainSelectedInstOperands,
5085 /* 12584 */ // GIR_Coverage, 17,
5086 /* 12584 */ GIR_Done,
5087 /* 12585 */ // Label 485: @12585
5088 /* 12585 */ GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(12619), // Rule ID 18 //
5089 /* 12590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5090 /* 12593 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5091 /* 12600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5092 /* 12604 */ // MIs[0] ptr
5093 /* 12604 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5094 /* 12608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5095 /* 12612 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i32>> => (ATOMIC_LOAD_XOR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5096 /* 12612 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I32),
5097 /* 12617 */ GIR_RootConstrainSelectedInstOperands,
5098 /* 12618 */ // GIR_Coverage, 18,
5099 /* 12618 */ GIR_Done,
5100 /* 12619 */ // Label 486: @12619
5101 /* 12619 */ GIM_Reject,
5102 /* 12620 */ // Label 483: @12620
5103 /* 12620 */ GIM_Reject,
5104 /* 12621 */ // Label 481: @12621
5105 /* 12621 */ GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(12658), // Rule ID 188 //
5106 /* 12626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5107 /* 12629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5108 /* 12632 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5109 /* 12639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5110 /* 12643 */ // MIs[0] ptr
5111 /* 12643 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5112 /* 12647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5113 /* 12651 */ // (atomic_load_xor:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_xor_i64>> => (ATOMIC_LOAD_XOR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5114 /* 12651 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I64),
5115 /* 12656 */ GIR_RootConstrainSelectedInstOperands,
5116 /* 12657 */ // GIR_Coverage, 188,
5117 /* 12657 */ GIR_Done,
5118 /* 12658 */ // Label 487: @12658
5119 /* 12658 */ GIM_Reject,
5120 /* 12659 */ // Label 482: @12659
5121 /* 12659 */ GIM_Reject,
5122 /* 12660 */ // Label 24: @12660
5123 /* 12660 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 490*/ GIMT_Encode4(12829),
5124 /* 12671 */ /*GILLT_s32*//*Label 488*/ GIMT_Encode4(12679),
5125 /* 12675 */ /*GILLT_s64*//*Label 489*/ GIMT_Encode4(12791),
5126 /* 12679 */ // Label 488: @12679
5127 /* 12679 */ GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(12790),
5128 /* 12684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5129 /* 12687 */ GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(12721), // Rule ID 31 //
5130 /* 12692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5131 /* 12695 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5132 /* 12702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5133 /* 12706 */ // MIs[0] ptr
5134 /* 12706 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5135 /* 12710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5136 /* 12714 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i8>> => (ATOMIC_LOAD_MAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5137 /* 12714 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I8),
5138 /* 12719 */ GIR_RootConstrainSelectedInstOperands,
5139 /* 12720 */ // GIR_Coverage, 31,
5140 /* 12720 */ GIR_Done,
5141 /* 12721 */ // Label 492: @12721
5142 /* 12721 */ GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(12755), // Rule ID 32 //
5143 /* 12726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5144 /* 12729 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5145 /* 12736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5146 /* 12740 */ // MIs[0] ptr
5147 /* 12740 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5148 /* 12744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5149 /* 12748 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i16>> => (ATOMIC_LOAD_MAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5150 /* 12748 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I16),
5151 /* 12753 */ GIR_RootConstrainSelectedInstOperands,
5152 /* 12754 */ // GIR_Coverage, 32,
5153 /* 12754 */ GIR_Done,
5154 /* 12755 */ // Label 493: @12755
5155 /* 12755 */ GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(12789), // Rule ID 33 //
5156 /* 12760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5157 /* 12763 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5158 /* 12770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5159 /* 12774 */ // MIs[0] ptr
5160 /* 12774 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5161 /* 12778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5162 /* 12782 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i32>> => (ATOMIC_LOAD_MAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5163 /* 12782 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I32),
5164 /* 12787 */ GIR_RootConstrainSelectedInstOperands,
5165 /* 12788 */ // GIR_Coverage, 33,
5166 /* 12788 */ GIR_Done,
5167 /* 12789 */ // Label 494: @12789
5168 /* 12789 */ GIM_Reject,
5169 /* 12790 */ // Label 491: @12790
5170 /* 12790 */ GIM_Reject,
5171 /* 12791 */ // Label 489: @12791
5172 /* 12791 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(12828), // Rule ID 193 //
5173 /* 12796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5174 /* 12799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5175 /* 12802 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5176 /* 12809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5177 /* 12813 */ // MIs[0] ptr
5178 /* 12813 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5179 /* 12817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5180 /* 12821 */ // (atomic_load_max:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_max_i64>> => (ATOMIC_LOAD_MAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5181 /* 12821 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I64),
5182 /* 12826 */ GIR_RootConstrainSelectedInstOperands,
5183 /* 12827 */ // GIR_Coverage, 193,
5184 /* 12827 */ GIR_Done,
5185 /* 12828 */ // Label 495: @12828
5186 /* 12828 */ GIM_Reject,
5187 /* 12829 */ // Label 490: @12829
5188 /* 12829 */ GIM_Reject,
5189 /* 12830 */ // Label 25: @12830
5190 /* 12830 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 498*/ GIMT_Encode4(12999),
5191 /* 12841 */ /*GILLT_s32*//*Label 496*/ GIMT_Encode4(12849),
5192 /* 12845 */ /*GILLT_s64*//*Label 497*/ GIMT_Encode4(12961),
5193 /* 12849 */ // Label 496: @12849
5194 /* 12849 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(12960),
5195 /* 12854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5196 /* 12857 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(12891), // Rule ID 28 //
5197 /* 12862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5198 /* 12865 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5199 /* 12872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5200 /* 12876 */ // MIs[0] ptr
5201 /* 12876 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5202 /* 12880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5203 /* 12884 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i8>> => (ATOMIC_LOAD_MIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5204 /* 12884 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I8),
5205 /* 12889 */ GIR_RootConstrainSelectedInstOperands,
5206 /* 12890 */ // GIR_Coverage, 28,
5207 /* 12890 */ GIR_Done,
5208 /* 12891 */ // Label 500: @12891
5209 /* 12891 */ GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(12925), // Rule ID 29 //
5210 /* 12896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5211 /* 12899 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5212 /* 12906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5213 /* 12910 */ // MIs[0] ptr
5214 /* 12910 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5215 /* 12914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5216 /* 12918 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i16>> => (ATOMIC_LOAD_MIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5217 /* 12918 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I16),
5218 /* 12923 */ GIR_RootConstrainSelectedInstOperands,
5219 /* 12924 */ // GIR_Coverage, 29,
5220 /* 12924 */ GIR_Done,
5221 /* 12925 */ // Label 501: @12925
5222 /* 12925 */ GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(12959), // Rule ID 30 //
5223 /* 12930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5224 /* 12933 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5225 /* 12940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5226 /* 12944 */ // MIs[0] ptr
5227 /* 12944 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5228 /* 12948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5229 /* 12952 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i32>> => (ATOMIC_LOAD_MIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5230 /* 12952 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I32),
5231 /* 12957 */ GIR_RootConstrainSelectedInstOperands,
5232 /* 12958 */ // GIR_Coverage, 30,
5233 /* 12958 */ GIR_Done,
5234 /* 12959 */ // Label 502: @12959
5235 /* 12959 */ GIM_Reject,
5236 /* 12960 */ // Label 499: @12960
5237 /* 12960 */ GIM_Reject,
5238 /* 12961 */ // Label 497: @12961
5239 /* 12961 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(12998), // Rule ID 192 //
5240 /* 12966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5241 /* 12969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5242 /* 12972 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5243 /* 12979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5244 /* 12983 */ // MIs[0] ptr
5245 /* 12983 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5246 /* 12987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5247 /* 12991 */ // (atomic_load_min:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_min_i64>> => (ATOMIC_LOAD_MIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5248 /* 12991 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I64),
5249 /* 12996 */ GIR_RootConstrainSelectedInstOperands,
5250 /* 12997 */ // GIR_Coverage, 192,
5251 /* 12997 */ GIR_Done,
5252 /* 12998 */ // Label 503: @12998
5253 /* 12998 */ GIM_Reject,
5254 /* 12999 */ // Label 498: @12999
5255 /* 12999 */ GIM_Reject,
5256 /* 13000 */ // Label 26: @13000
5257 /* 13000 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 506*/ GIMT_Encode4(13169),
5258 /* 13011 */ /*GILLT_s32*//*Label 504*/ GIMT_Encode4(13019),
5259 /* 13015 */ /*GILLT_s64*//*Label 505*/ GIMT_Encode4(13131),
5260 /* 13019 */ // Label 504: @13019
5261 /* 13019 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(13130),
5262 /* 13024 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5263 /* 13027 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(13061), // Rule ID 37 //
5264 /* 13032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5265 /* 13035 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5266 /* 13042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5267 /* 13046 */ // MIs[0] ptr
5268 /* 13046 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5269 /* 13050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5270 /* 13054 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i8>> => (ATOMIC_LOAD_UMAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5271 /* 13054 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I8),
5272 /* 13059 */ GIR_RootConstrainSelectedInstOperands,
5273 /* 13060 */ // GIR_Coverage, 37,
5274 /* 13060 */ GIR_Done,
5275 /* 13061 */ // Label 508: @13061
5276 /* 13061 */ GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(13095), // Rule ID 38 //
5277 /* 13066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5278 /* 13069 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5279 /* 13076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5280 /* 13080 */ // MIs[0] ptr
5281 /* 13080 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5282 /* 13084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5283 /* 13088 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i16>> => (ATOMIC_LOAD_UMAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5284 /* 13088 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I16),
5285 /* 13093 */ GIR_RootConstrainSelectedInstOperands,
5286 /* 13094 */ // GIR_Coverage, 38,
5287 /* 13094 */ GIR_Done,
5288 /* 13095 */ // Label 509: @13095
5289 /* 13095 */ GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(13129), // Rule ID 39 //
5290 /* 13100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5291 /* 13103 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5292 /* 13110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5293 /* 13114 */ // MIs[0] ptr
5294 /* 13114 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5295 /* 13118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5296 /* 13122 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i32>> => (ATOMIC_LOAD_UMAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5297 /* 13122 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I32),
5298 /* 13127 */ GIR_RootConstrainSelectedInstOperands,
5299 /* 13128 */ // GIR_Coverage, 39,
5300 /* 13128 */ GIR_Done,
5301 /* 13129 */ // Label 510: @13129
5302 /* 13129 */ GIM_Reject,
5303 /* 13130 */ // Label 507: @13130
5304 /* 13130 */ GIM_Reject,
5305 /* 13131 */ // Label 505: @13131
5306 /* 13131 */ GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(13168), // Rule ID 195 //
5307 /* 13136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5308 /* 13139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5309 /* 13142 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5310 /* 13149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5311 /* 13153 */ // MIs[0] ptr
5312 /* 13153 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5313 /* 13157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5314 /* 13161 */ // (atomic_load_umax:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umax_i64>> => (ATOMIC_LOAD_UMAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5315 /* 13161 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I64),
5316 /* 13166 */ GIR_RootConstrainSelectedInstOperands,
5317 /* 13167 */ // GIR_Coverage, 195,
5318 /* 13167 */ GIR_Done,
5319 /* 13168 */ // Label 511: @13168
5320 /* 13168 */ GIM_Reject,
5321 /* 13169 */ // Label 506: @13169
5322 /* 13169 */ GIM_Reject,
5323 /* 13170 */ // Label 27: @13170
5324 /* 13170 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 514*/ GIMT_Encode4(13339),
5325 /* 13181 */ /*GILLT_s32*//*Label 512*/ GIMT_Encode4(13189),
5326 /* 13185 */ /*GILLT_s64*//*Label 513*/ GIMT_Encode4(13301),
5327 /* 13189 */ // Label 512: @13189
5328 /* 13189 */ GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(13300),
5329 /* 13194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5330 /* 13197 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(13231), // Rule ID 34 //
5331 /* 13202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5332 /* 13205 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5333 /* 13212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5334 /* 13216 */ // MIs[0] ptr
5335 /* 13216 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5336 /* 13220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5337 /* 13224 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i8>> => (ATOMIC_LOAD_UMIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5338 /* 13224 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I8),
5339 /* 13229 */ GIR_RootConstrainSelectedInstOperands,
5340 /* 13230 */ // GIR_Coverage, 34,
5341 /* 13230 */ GIR_Done,
5342 /* 13231 */ // Label 516: @13231
5343 /* 13231 */ GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(13265), // Rule ID 35 //
5344 /* 13236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5345 /* 13239 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5346 /* 13246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5347 /* 13250 */ // MIs[0] ptr
5348 /* 13250 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5349 /* 13254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5350 /* 13258 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i16>> => (ATOMIC_LOAD_UMIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5351 /* 13258 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I16),
5352 /* 13263 */ GIR_RootConstrainSelectedInstOperands,
5353 /* 13264 */ // GIR_Coverage, 35,
5354 /* 13264 */ GIR_Done,
5355 /* 13265 */ // Label 517: @13265
5356 /* 13265 */ GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(13299), // Rule ID 36 //
5357 /* 13270 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5358 /* 13273 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5359 /* 13280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5360 /* 13284 */ // MIs[0] ptr
5361 /* 13284 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5362 /* 13288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5363 /* 13292 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i32>> => (ATOMIC_LOAD_UMIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5364 /* 13292 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I32),
5365 /* 13297 */ GIR_RootConstrainSelectedInstOperands,
5366 /* 13298 */ // GIR_Coverage, 36,
5367 /* 13298 */ GIR_Done,
5368 /* 13299 */ // Label 518: @13299
5369 /* 13299 */ GIM_Reject,
5370 /* 13300 */ // Label 515: @13300
5371 /* 13300 */ GIM_Reject,
5372 /* 13301 */ // Label 513: @13301
5373 /* 13301 */ GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(13338), // Rule ID 194 //
5374 /* 13306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5375 /* 13309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5376 /* 13312 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5377 /* 13319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5378 /* 13323 */ // MIs[0] ptr
5379 /* 13323 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5380 /* 13327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5381 /* 13331 */ // (atomic_load_umin:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umin_i64>> => (ATOMIC_LOAD_UMIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5382 /* 13331 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I64),
5383 /* 13336 */ GIR_RootConstrainSelectedInstOperands,
5384 /* 13337 */ // GIR_Coverage, 194,
5385 /* 13337 */ GIR_Done,
5386 /* 13338 */ // Label 519: @13338
5387 /* 13338 */ GIM_Reject,
5388 /* 13339 */ // Label 514: @13339
5389 /* 13339 */ GIM_Reject,
5390 /* 13340 */ // Label 28: @13340
5391 /* 13340 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 522*/ GIMT_Encode4(18060),
5392 /* 13351 */ /*GILLT_s32*//*Label 520*/ GIMT_Encode4(13359),
5393 /* 13355 */ /*GILLT_s64*//*Label 521*/ GIMT_Encode4(18026),
5394 /* 13359 */ // Label 520: @13359
5395 /* 13359 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(13467), // Rule ID 2365 //
5396 /* 13364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5397 /* 13367 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5398 /* 13371 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5399 /* 13375 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5400 /* 13379 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5401 /* 13383 */ // MIs[1] Operand 1
5402 /* 13383 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5403 /* 13388 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5404 /* 13392 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5405 /* 13396 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5406 /* 13400 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5407 /* 13404 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5408 /* 13408 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5409 /* 13412 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5410 /* 13416 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5411 /* 13420 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5412 /* 13424 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5413 /* 13428 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5414 /* 13432 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5415 /* 13436 */ // MIs[4] Operand 1
5416 /* 13436 */ // No operand predicates
5417 /* 13436 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5418 /* 13441 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5419 /* 13445 */ // MIs[0] offset
5420 /* 13445 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5421 /* 13448 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5422 /* 13450 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5423 /* 13450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5424 /* 13453 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5425 /* 13457 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5426 /* 13460 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5427 /* 13462 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5428 /* 13465 */ GIR_RootConstrainSelectedInstOperands,
5429 /* 13466 */ // GIR_Coverage, 2365,
5430 /* 13466 */ GIR_EraseRootFromParent_Done,
5431 /* 13467 */ // Label 523: @13467
5432 /* 13467 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(13582), // Rule ID 2366 //
5433 /* 13472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5434 /* 13475 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5435 /* 13479 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5436 /* 13483 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5437 /* 13487 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5438 /* 13491 */ // MIs[1] Operand 1
5439 /* 13491 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5440 /* 13496 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5441 /* 13500 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5442 /* 13504 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5443 /* 13508 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5444 /* 13512 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5445 /* 13516 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5446 /* 13520 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5447 /* 13524 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5448 /* 13528 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5449 /* 13539 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5450 /* 13543 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5451 /* 13547 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5452 /* 13551 */ // MIs[4] Operand 1
5453 /* 13551 */ // No operand predicates
5454 /* 13551 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5455 /* 13556 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5456 /* 13560 */ // MIs[0] offset
5457 /* 13560 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5458 /* 13563 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5459 /* 13565 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5460 /* 13565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5461 /* 13568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5462 /* 13572 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5463 /* 13575 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5464 /* 13577 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5465 /* 13580 */ GIR_RootConstrainSelectedInstOperands,
5466 /* 13581 */ // GIR_Coverage, 2366,
5467 /* 13581 */ GIR_EraseRootFromParent_Done,
5468 /* 13582 */ // Label 524: @13582
5469 /* 13582 */ GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(13690), // Rule ID 2367 //
5470 /* 13587 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5471 /* 13590 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5472 /* 13594 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5473 /* 13598 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5474 /* 13602 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5475 /* 13606 */ // MIs[1] Operand 1
5476 /* 13606 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5477 /* 13611 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5478 /* 13615 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5479 /* 13619 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5480 /* 13623 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5481 /* 13627 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5482 /* 13631 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5483 /* 13635 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5484 /* 13639 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5485 /* 13643 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5486 /* 13647 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5487 /* 13651 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5488 /* 13655 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5489 /* 13659 */ // MIs[4] Operand 1
5490 /* 13659 */ // No operand predicates
5491 /* 13659 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5492 /* 13664 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5493 /* 13668 */ // MIs[0] offset
5494 /* 13668 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5495 /* 13671 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5496 /* 13673 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5497 /* 13673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5498 /* 13676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5499 /* 13680 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5500 /* 13683 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5501 /* 13685 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5502 /* 13688 */ GIR_RootConstrainSelectedInstOperands,
5503 /* 13689 */ // GIR_Coverage, 2367,
5504 /* 13689 */ GIR_EraseRootFromParent_Done,
5505 /* 13690 */ // Label 525: @13690
5506 /* 13690 */ GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(13805), // Rule ID 2368 //
5507 /* 13695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5508 /* 13698 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5509 /* 13702 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5510 /* 13706 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5511 /* 13710 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5512 /* 13714 */ // MIs[1] Operand 1
5513 /* 13714 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5514 /* 13719 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5515 /* 13723 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5516 /* 13727 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5517 /* 13731 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5518 /* 13735 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5519 /* 13739 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5520 /* 13743 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5521 /* 13747 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5522 /* 13751 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5523 /* 13762 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5524 /* 13766 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5525 /* 13770 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5526 /* 13774 */ // MIs[4] Operand 1
5527 /* 13774 */ // No operand predicates
5528 /* 13774 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5529 /* 13779 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5530 /* 13783 */ // MIs[0] offset
5531 /* 13783 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5532 /* 13786 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5533 /* 13788 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5534 /* 13788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5535 /* 13791 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5536 /* 13795 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5537 /* 13798 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5538 /* 13800 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5539 /* 13803 */ GIR_RootConstrainSelectedInstOperands,
5540 /* 13804 */ // GIR_Coverage, 2368,
5541 /* 13804 */ GIR_EraseRootFromParent_Done,
5542 /* 13805 */ // Label 526: @13805
5543 /* 13805 */ GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(13913), // Rule ID 270 //
5544 /* 13810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5545 /* 13813 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5546 /* 13817 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5547 /* 13821 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5548 /* 13825 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5549 /* 13829 */ // MIs[1] Operand 1
5550 /* 13829 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5551 /* 13834 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5552 /* 13838 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5553 /* 13842 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5554 /* 13846 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5555 /* 13850 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5556 /* 13855 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5557 /* 13859 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5558 /* 13863 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5559 /* 13867 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5560 /* 13871 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5561 /* 13875 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5562 /* 13879 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5563 /* 13883 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5564 /* 13887 */ // MIs[4] Operand 1
5565 /* 13887 */ // No operand predicates
5566 /* 13887 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5567 /* 13891 */ // MIs[0] offset
5568 /* 13891 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5569 /* 13894 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5570 /* 13896 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5571 /* 13896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5572 /* 13899 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5573 /* 13903 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5574 /* 13906 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5575 /* 13908 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5576 /* 13911 */ GIR_RootConstrainSelectedInstOperands,
5577 /* 13912 */ // GIR_Coverage, 270,
5578 /* 13912 */ GIR_EraseRootFromParent_Done,
5579 /* 13913 */ // Label 527: @13913
5580 /* 13913 */ GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(14028), // Rule ID 271 //
5581 /* 13918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5582 /* 13921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5583 /* 13925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5584 /* 13929 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5585 /* 13933 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5586 /* 13937 */ // MIs[1] Operand 1
5587 /* 13937 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5588 /* 13942 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5589 /* 13946 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5590 /* 13950 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5591 /* 13954 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5592 /* 13958 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5593 /* 13963 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5594 /* 13967 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5595 /* 13971 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5596 /* 13975 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5597 /* 13979 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5598 /* 13990 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5599 /* 13994 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5600 /* 13998 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5601 /* 14002 */ // MIs[4] Operand 1
5602 /* 14002 */ // No operand predicates
5603 /* 14002 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5604 /* 14006 */ // MIs[0] offset
5605 /* 14006 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5606 /* 14009 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5607 /* 14011 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5608 /* 14011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5609 /* 14014 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5610 /* 14018 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5611 /* 14021 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5612 /* 14023 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5613 /* 14026 */ GIR_RootConstrainSelectedInstOperands,
5614 /* 14027 */ // GIR_Coverage, 271,
5615 /* 14027 */ GIR_EraseRootFromParent_Done,
5616 /* 14028 */ // Label 528: @14028
5617 /* 14028 */ GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(14136), // Rule ID 272 //
5618 /* 14033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5619 /* 14036 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5620 /* 14040 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5621 /* 14044 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5622 /* 14048 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5623 /* 14052 */ // MIs[1] Operand 1
5624 /* 14052 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5625 /* 14057 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5626 /* 14061 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5627 /* 14065 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5628 /* 14069 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5629 /* 14073 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5630 /* 14078 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5631 /* 14082 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5632 /* 14086 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5633 /* 14090 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5634 /* 14094 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5635 /* 14098 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5636 /* 14102 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5637 /* 14106 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5638 /* 14110 */ // MIs[4] Operand 1
5639 /* 14110 */ // No operand predicates
5640 /* 14110 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5641 /* 14114 */ // MIs[0] offset
5642 /* 14114 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5643 /* 14117 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5644 /* 14119 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5645 /* 14119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5646 /* 14122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5647 /* 14126 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5648 /* 14129 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5649 /* 14131 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5650 /* 14134 */ GIR_RootConstrainSelectedInstOperands,
5651 /* 14135 */ // GIR_Coverage, 272,
5652 /* 14135 */ GIR_EraseRootFromParent_Done,
5653 /* 14136 */ // Label 529: @14136
5654 /* 14136 */ GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(14251), // Rule ID 273 //
5655 /* 14141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5656 /* 14144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5657 /* 14148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5658 /* 14152 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5659 /* 14156 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5660 /* 14160 */ // MIs[1] Operand 1
5661 /* 14160 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5662 /* 14165 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5663 /* 14169 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5664 /* 14173 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5665 /* 14177 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5666 /* 14181 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5667 /* 14186 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5668 /* 14190 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5669 /* 14194 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5670 /* 14198 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5671 /* 14202 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5672 /* 14213 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5673 /* 14217 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5674 /* 14221 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5675 /* 14225 */ // MIs[4] Operand 1
5676 /* 14225 */ // No operand predicates
5677 /* 14225 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5678 /* 14229 */ // MIs[0] offset
5679 /* 14229 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5680 /* 14232 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5681 /* 14234 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5682 /* 14234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5683 /* 14237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5684 /* 14241 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5685 /* 14244 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5686 /* 14246 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5687 /* 14249 */ GIR_RootConstrainSelectedInstOperands,
5688 /* 14250 */ // GIR_Coverage, 273,
5689 /* 14250 */ GIR_EraseRootFromParent_Done,
5690 /* 14251 */ // Label 530: @14251
5691 /* 14251 */ GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(14308), // Rule ID 94 //
5692 /* 14256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5693 /* 14259 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5694 /* 14263 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5695 /* 14267 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5696 /* 14271 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5697 /* 14275 */ // MIs[1] Operand 1
5698 /* 14275 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5699 /* 14280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5700 /* 14285 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5701 /* 14289 */ // MIs[0] offset
5702 /* 14289 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5703 /* 14292 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5704 /* 14294 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5705 /* 14294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
5706 /* 14297 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5707 /* 14301 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5708 /* 14303 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5709 /* 14306 */ GIR_RootConstrainSelectedInstOperands,
5710 /* 14307 */ // GIR_Coverage, 94,
5711 /* 14307 */ GIR_EraseRootFromParent_Done,
5712 /* 14308 */ // Label 531: @14308
5713 /* 14308 */ GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(14365), // Rule ID 95 //
5714 /* 14313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5715 /* 14316 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5716 /* 14320 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5717 /* 14324 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5718 /* 14328 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5719 /* 14332 */ // MIs[1] Operand 1
5720 /* 14332 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5721 /* 14337 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5722 /* 14342 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5723 /* 14346 */ // MIs[0] offset
5724 /* 14346 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5725 /* 14349 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5726 /* 14351 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5727 /* 14351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ),
5728 /* 14354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5729 /* 14358 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5730 /* 14360 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5731 /* 14363 */ GIR_RootConstrainSelectedInstOperands,
5732 /* 14364 */ // GIR_Coverage, 95,
5733 /* 14364 */ GIR_EraseRootFromParent_Done,
5734 /* 14365 */ // Label 532: @14365
5735 /* 14365 */ GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(14422), // Rule ID 96 //
5736 /* 14370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5737 /* 14373 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5738 /* 14377 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5739 /* 14381 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5740 /* 14385 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5741 /* 14389 */ // MIs[1] Operand 1
5742 /* 14389 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5743 /* 14394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5744 /* 14399 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5745 /* 14403 */ // MIs[0] offset
5746 /* 14403 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5747 /* 14406 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5748 /* 14408 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5749 /* 14408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
5750 /* 14411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5751 /* 14415 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5752 /* 14417 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5753 /* 14420 */ GIR_RootConstrainSelectedInstOperands,
5754 /* 14421 */ // GIR_Coverage, 96,
5755 /* 14421 */ GIR_EraseRootFromParent_Done,
5756 /* 14422 */ // Label 533: @14422
5757 /* 14422 */ GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(14479), // Rule ID 97 //
5758 /* 14427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5759 /* 14430 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5760 /* 14434 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5761 /* 14438 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5762 /* 14442 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5763 /* 14446 */ // MIs[1] Operand 1
5764 /* 14446 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5765 /* 14451 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5766 /* 14456 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5767 /* 14460 */ // MIs[0] offset
5768 /* 14460 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5769 /* 14463 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5770 /* 14465 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5771 /* 14465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ),
5772 /* 14468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5773 /* 14472 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5774 /* 14474 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5775 /* 14477 */ GIR_RootConstrainSelectedInstOperands,
5776 /* 14478 */ // GIR_Coverage, 97,
5777 /* 14478 */ GIR_EraseRootFromParent_Done,
5778 /* 14479 */ // Label 534: @14479
5779 /* 14479 */ GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(14536), // Rule ID 245 //
5780 /* 14484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5781 /* 14487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5782 /* 14491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5783 /* 14495 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5784 /* 14499 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5785 /* 14503 */ // MIs[1] Operand 1
5786 /* 14503 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5787 /* 14508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5788 /* 14513 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5789 /* 14517 */ // MIs[0] offset
5790 /* 14517 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5791 /* 14520 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5792 /* 14522 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5793 /* 14522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
5794 /* 14525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5795 /* 14529 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5796 /* 14531 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5797 /* 14534 */ GIR_RootConstrainSelectedInstOperands,
5798 /* 14535 */ // GIR_Coverage, 245,
5799 /* 14535 */ GIR_EraseRootFromParent_Done,
5800 /* 14536 */ // Label 535: @14536
5801 /* 14536 */ GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(14593), // Rule ID 246 //
5802 /* 14541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5803 /* 14544 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5804 /* 14548 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5805 /* 14552 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5806 /* 14556 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5807 /* 14560 */ // MIs[1] Operand 1
5808 /* 14560 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5809 /* 14565 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5810 /* 14570 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5811 /* 14574 */ // MIs[0] offset
5812 /* 14574 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5813 /* 14577 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5814 /* 14579 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5815 /* 14579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ64),
5816 /* 14582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5817 /* 14586 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5818 /* 14588 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5819 /* 14591 */ GIR_RootConstrainSelectedInstOperands,
5820 /* 14592 */ // GIR_Coverage, 246,
5821 /* 14592 */ GIR_EraseRootFromParent_Done,
5822 /* 14593 */ // Label 536: @14593
5823 /* 14593 */ GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(14650), // Rule ID 247 //
5824 /* 14598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5825 /* 14601 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5826 /* 14605 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5827 /* 14609 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5828 /* 14613 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5829 /* 14617 */ // MIs[1] Operand 1
5830 /* 14617 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5831 /* 14622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5832 /* 14627 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5833 /* 14631 */ // MIs[0] offset
5834 /* 14631 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5835 /* 14634 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5836 /* 14636 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5837 /* 14636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
5838 /* 14639 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5839 /* 14643 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5840 /* 14645 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5841 /* 14648 */ GIR_RootConstrainSelectedInstOperands,
5842 /* 14649 */ // GIR_Coverage, 247,
5843 /* 14649 */ GIR_EraseRootFromParent_Done,
5844 /* 14650 */ // Label 537: @14650
5845 /* 14650 */ GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(14707), // Rule ID 248 //
5846 /* 14655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5847 /* 14658 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5848 /* 14662 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5849 /* 14666 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5850 /* 14670 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5851 /* 14674 */ // MIs[1] Operand 1
5852 /* 14674 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5853 /* 14679 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5854 /* 14684 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5855 /* 14688 */ // MIs[0] offset
5856 /* 14688 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5857 /* 14691 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5858 /* 14693 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5859 /* 14693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ64),
5860 /* 14696 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5861 /* 14700 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5862 /* 14702 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5863 /* 14705 */ GIR_RootConstrainSelectedInstOperands,
5864 /* 14706 */ // GIR_Coverage, 248,
5865 /* 14706 */ GIR_EraseRootFromParent_Done,
5866 /* 14707 */ // Label 538: @14707
5867 /* 14707 */ GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(14764), // Rule ID 1109 //
5868 /* 14712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5869 /* 14715 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5870 /* 14719 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5871 /* 14723 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5872 /* 14727 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5873 /* 14731 */ // MIs[1] Operand 1
5874 /* 14731 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5875 /* 14736 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5876 /* 14741 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5877 /* 14745 */ // MIs[0] offset
5878 /* 14745 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5879 /* 14748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5880 /* 14750 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5881 /* 14750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
5882 /* 14753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5883 /* 14757 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5884 /* 14759 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5885 /* 14762 */ GIR_RootConstrainSelectedInstOperands,
5886 /* 14763 */ // GIR_Coverage, 1109,
5887 /* 14763 */ GIR_EraseRootFromParent_Done,
5888 /* 14764 */ // Label 539: @14764
5889 /* 14764 */ GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(14821), // Rule ID 1110 //
5890 /* 14769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5891 /* 14772 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5892 /* 14776 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5893 /* 14780 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5894 /* 14784 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5895 /* 14788 */ // MIs[1] Operand 1
5896 /* 14788 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5897 /* 14793 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5898 /* 14798 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5899 /* 14802 */ // MIs[0] offset
5900 /* 14802 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5901 /* 14805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5902 /* 14807 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5903 /* 14807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ_MM),
5904 /* 14810 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5905 /* 14814 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5906 /* 14816 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5907 /* 14819 */ GIR_RootConstrainSelectedInstOperands,
5908 /* 14820 */ // GIR_Coverage, 1110,
5909 /* 14820 */ GIR_EraseRootFromParent_Done,
5910 /* 14821 */ // Label 540: @14821
5911 /* 14821 */ GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(14878), // Rule ID 1111 //
5912 /* 14826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5913 /* 14829 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5914 /* 14833 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5915 /* 14837 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5916 /* 14841 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5917 /* 14845 */ // MIs[1] Operand 1
5918 /* 14845 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5919 /* 14850 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5920 /* 14855 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5921 /* 14859 */ // MIs[0] offset
5922 /* 14859 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5923 /* 14862 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5924 /* 14864 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5925 /* 14864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
5926 /* 14867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5927 /* 14871 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5928 /* 14873 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5929 /* 14876 */ GIR_RootConstrainSelectedInstOperands,
5930 /* 14877 */ // GIR_Coverage, 1111,
5931 /* 14877 */ GIR_EraseRootFromParent_Done,
5932 /* 14878 */ // Label 541: @14878
5933 /* 14878 */ GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(14935), // Rule ID 1112 //
5934 /* 14883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5935 /* 14886 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5936 /* 14890 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5937 /* 14894 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5938 /* 14898 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5939 /* 14902 */ // MIs[1] Operand 1
5940 /* 14902 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5941 /* 14907 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5942 /* 14912 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5943 /* 14916 */ // MIs[0] offset
5944 /* 14916 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5945 /* 14919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5946 /* 14921 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5947 /* 14921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ_MM),
5948 /* 14924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5949 /* 14928 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5950 /* 14930 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5951 /* 14933 */ GIR_RootConstrainSelectedInstOperands,
5952 /* 14934 */ // GIR_Coverage, 1112,
5953 /* 14934 */ GIR_EraseRootFromParent_Done,
5954 /* 14935 */ // Label 542: @14935
5955 /* 14935 */ GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(14998), // Rule ID 1402 //
5956 /* 14940 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5957 /* 14943 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5958 /* 14947 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5959 /* 14951 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5960 /* 14955 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5961 /* 14959 */ // MIs[1] Operand 1
5962 /* 14959 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5963 /* 14964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5964 /* 14969 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5965 /* 14973 */ // MIs[0] dst
5966 /* 14973 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5967 /* 14976 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5968 /* 14978 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5969 /* 14978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
5970 /* 14981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5971 /* 14985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5972 /* 14991 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5973 /* 14993 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5974 /* 14996 */ GIR_RootConstrainSelectedInstOperands,
5975 /* 14997 */ // GIR_Coverage, 1402,
5976 /* 14997 */ GIR_EraseRootFromParent_Done,
5977 /* 14998 */ // Label 543: @14998
5978 /* 14998 */ GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(15061), // Rule ID 1403 //
5979 /* 15003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5980 /* 15006 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5981 /* 15010 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5982 /* 15014 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5983 /* 15018 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5984 /* 15022 */ // MIs[1] Operand 1
5985 /* 15022 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5986 /* 15027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5987 /* 15032 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5988 /* 15036 */ // MIs[0] dst
5989 /* 15036 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5990 /* 15039 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5991 /* 15041 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5992 /* 15041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5993 /* 15044 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5994 /* 15048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5995 /* 15054 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5996 /* 15056 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5997 /* 15059 */ GIR_RootConstrainSelectedInstOperands,
5998 /* 15060 */ // GIR_Coverage, 1403,
5999 /* 15060 */ GIR_EraseRootFromParent_Done,
6000 /* 15061 */ // Label 544: @15061
6001 /* 15061 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(15124), // Rule ID 1548 //
6002 /* 15066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6003 /* 15069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6004 /* 15073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6005 /* 15077 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6006 /* 15081 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6007 /* 15085 */ // MIs[1] Operand 1
6008 /* 15085 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6009 /* 15090 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6010 /* 15095 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6011 /* 15099 */ // MIs[0] dst
6012 /* 15099 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6013 /* 15102 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6014 /* 15104 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
6015 /* 15104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6016 /* 15107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6017 /* 15111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6018 /* 15117 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6019 /* 15119 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6020 /* 15122 */ GIR_RootConstrainSelectedInstOperands,
6021 /* 15123 */ // GIR_Coverage, 1548,
6022 /* 15123 */ GIR_EraseRootFromParent_Done,
6023 /* 15124 */ // Label 545: @15124
6024 /* 15124 */ GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(15187), // Rule ID 1549 //
6025 /* 15129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6026 /* 15132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6027 /* 15136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6028 /* 15140 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6029 /* 15144 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6030 /* 15148 */ // MIs[1] Operand 1
6031 /* 15148 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6032 /* 15153 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6033 /* 15158 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6034 /* 15162 */ // MIs[0] dst
6035 /* 15162 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6036 /* 15165 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6037 /* 15167 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
6038 /* 15167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
6039 /* 15170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6040 /* 15174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6041 /* 15180 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6042 /* 15182 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6043 /* 15185 */ GIR_RootConstrainSelectedInstOperands,
6044 /* 15186 */ // GIR_Coverage, 1549,
6045 /* 15186 */ GIR_EraseRootFromParent_Done,
6046 /* 15187 */ // Label 546: @15187
6047 /* 15187 */ GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(15241), // Rule ID 1856 //
6048 /* 15192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6049 /* 15195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6050 /* 15199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6051 /* 15203 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6052 /* 15207 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6053 /* 15211 */ // MIs[1] Operand 1
6054 /* 15211 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6055 /* 15216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6056 /* 15221 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6057 /* 15225 */ // MIs[0] targ16
6058 /* 15225 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6059 /* 15228 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6060 /* 15230 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
6061 /* 15230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BeqzRxImm16),
6062 /* 15233 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6063 /* 15237 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
6064 /* 15239 */ GIR_RootConstrainSelectedInstOperands,
6065 /* 15240 */ // GIR_Coverage, 1856,
6066 /* 15240 */ GIR_EraseRootFromParent_Done,
6067 /* 15241 */ // Label 547: @15241
6068 /* 15241 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(15295), // Rule ID 1865 //
6069 /* 15246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6070 /* 15249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6071 /* 15253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6072 /* 15257 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6073 /* 15261 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6074 /* 15265 */ // MIs[1] Operand 1
6075 /* 15265 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6076 /* 15270 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6077 /* 15275 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6078 /* 15279 */ // MIs[0] targ16
6079 /* 15279 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6080 /* 15282 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6081 /* 15284 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
6082 /* 15284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
6083 /* 15287 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6084 /* 15291 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
6085 /* 15293 */ GIR_RootConstrainSelectedInstOperands,
6086 /* 15294 */ // GIR_Coverage, 1865,
6087 /* 15294 */ GIR_EraseRootFromParent_Done,
6088 /* 15295 */ // Label 548: @15295
6089 /* 15295 */ GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(15358), // Rule ID 2195 //
6090 /* 15300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6091 /* 15303 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6092 /* 15307 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6093 /* 15311 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6094 /* 15315 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6095 /* 15319 */ // MIs[1] Operand 1
6096 /* 15319 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6097 /* 15324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6098 /* 15329 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6099 /* 15333 */ // MIs[0] dst
6100 /* 15333 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6101 /* 15336 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6102 /* 15338 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6103 /* 15338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6104 /* 15341 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6105 /* 15345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6106 /* 15351 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6107 /* 15353 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6108 /* 15356 */ GIR_RootConstrainSelectedInstOperands,
6109 /* 15357 */ // GIR_Coverage, 2195,
6110 /* 15357 */ GIR_EraseRootFromParent_Done,
6111 /* 15358 */ // Label 549: @15358
6112 /* 15358 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(15421), // Rule ID 2196 //
6113 /* 15363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6114 /* 15366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6115 /* 15370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6116 /* 15374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6117 /* 15378 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6118 /* 15382 */ // MIs[1] Operand 1
6119 /* 15382 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6120 /* 15387 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6121 /* 15392 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6122 /* 15396 */ // MIs[0] dst
6123 /* 15396 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6124 /* 15399 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6125 /* 15401 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6126 /* 15401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6127 /* 15404 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6128 /* 15408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6129 /* 15414 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6130 /* 15416 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6131 /* 15419 */ GIR_RootConstrainSelectedInstOperands,
6132 /* 15420 */ // GIR_Coverage, 2196,
6133 /* 15420 */ GIR_EraseRootFromParent_Done,
6134 /* 15421 */ // Label 550: @15421
6135 /* 15421 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(15478), // Rule ID 2342 //
6136 /* 15426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6137 /* 15429 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6138 /* 15433 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6139 /* 15437 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6140 /* 15441 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6141 /* 15445 */ // MIs[1] Operand 1
6142 /* 15445 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6143 /* 15450 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6144 /* 15455 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6145 /* 15459 */ // MIs[0] dst
6146 /* 15459 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6147 /* 15462 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6148 /* 15464 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6149 /* 15464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
6150 /* 15467 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6151 /* 15471 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6152 /* 15473 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6153 /* 15476 */ GIR_RootConstrainSelectedInstOperands,
6154 /* 15477 */ // GIR_Coverage, 2342,
6155 /* 15477 */ GIR_EraseRootFromParent_Done,
6156 /* 15478 */ // Label 551: @15478
6157 /* 15478 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(15535), // Rule ID 2343 //
6158 /* 15483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6159 /* 15486 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6160 /* 15490 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6161 /* 15494 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6162 /* 15498 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6163 /* 15502 */ // MIs[1] Operand 1
6164 /* 15502 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6165 /* 15507 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6166 /* 15512 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6167 /* 15516 */ // MIs[0] dst
6168 /* 15516 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6169 /* 15519 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6170 /* 15521 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6171 /* 15521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6172 /* 15524 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6173 /* 15528 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6174 /* 15530 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6175 /* 15533 */ GIR_RootConstrainSelectedInstOperands,
6176 /* 15534 */ // GIR_Coverage, 2343,
6177 /* 15534 */ GIR_EraseRootFromParent_Done,
6178 /* 15535 */ // Label 552: @15535
6179 /* 15535 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(15587), // Rule ID 1413 //
6180 /* 15540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6181 /* 15543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6182 /* 15547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6183 /* 15551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6184 /* 15555 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6185 /* 15559 */ // MIs[1] Operand 1
6186 /* 15559 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6187 /* 15564 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6188 /* 15568 */ // MIs[0] dst
6189 /* 15568 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6190 /* 15571 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6191 /* 15573 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6192 /* 15573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
6193 /* 15576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6194 /* 15580 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6195 /* 15582 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6196 /* 15585 */ GIR_RootConstrainSelectedInstOperands,
6197 /* 15586 */ // GIR_Coverage, 1413,
6198 /* 15586 */ GIR_EraseRootFromParent_Done,
6199 /* 15587 */ // Label 553: @15587
6200 /* 15587 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(15639), // Rule ID 1414 //
6201 /* 15592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6202 /* 15595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6203 /* 15599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6204 /* 15603 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6205 /* 15607 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6206 /* 15611 */ // MIs[1] Operand 1
6207 /* 15611 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6208 /* 15616 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
6209 /* 15620 */ // MIs[0] dst
6210 /* 15620 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6211 /* 15623 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6212 /* 15625 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6213 /* 15625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
6214 /* 15628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6215 /* 15632 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6216 /* 15634 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6217 /* 15637 */ GIR_RootConstrainSelectedInstOperands,
6218 /* 15638 */ // GIR_Coverage, 1414,
6219 /* 15638 */ GIR_EraseRootFromParent_Done,
6220 /* 15639 */ // Label 554: @15639
6221 /* 15639 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(15691), // Rule ID 1559 //
6222 /* 15644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6223 /* 15647 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6224 /* 15651 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6225 /* 15655 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6226 /* 15659 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6227 /* 15663 */ // MIs[1] Operand 1
6228 /* 15663 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6229 /* 15668 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6230 /* 15672 */ // MIs[0] dst
6231 /* 15672 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6232 /* 15675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6233 /* 15677 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
6234 /* 15677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
6235 /* 15680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6236 /* 15684 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6237 /* 15686 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6238 /* 15689 */ GIR_RootConstrainSelectedInstOperands,
6239 /* 15690 */ // GIR_Coverage, 1559,
6240 /* 15690 */ GIR_EraseRootFromParent_Done,
6241 /* 15691 */ // Label 555: @15691
6242 /* 15691 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(15743), // Rule ID 1560 //
6243 /* 15696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6244 /* 15699 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6245 /* 15703 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6246 /* 15707 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6247 /* 15711 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6248 /* 15715 */ // MIs[1] Operand 1
6249 /* 15715 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6250 /* 15720 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
6251 /* 15724 */ // MIs[0] dst
6252 /* 15724 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6253 /* 15727 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6254 /* 15729 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
6255 /* 15729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
6256 /* 15732 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6257 /* 15736 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6258 /* 15738 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6259 /* 15741 */ GIR_RootConstrainSelectedInstOperands,
6260 /* 15742 */ // GIR_Coverage, 1560,
6261 /* 15742 */ GIR_EraseRootFromParent_Done,
6262 /* 15743 */ // Label 556: @15743
6263 /* 15743 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(15795), // Rule ID 2206 //
6264 /* 15748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6265 /* 15751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6266 /* 15755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6267 /* 15759 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6268 /* 15763 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6269 /* 15767 */ // MIs[1] Operand 1
6270 /* 15767 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6271 /* 15772 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6272 /* 15776 */ // MIs[0] dst
6273 /* 15776 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6274 /* 15779 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6275 /* 15781 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6276 /* 15781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
6277 /* 15784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6278 /* 15788 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6279 /* 15790 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6280 /* 15793 */ GIR_RootConstrainSelectedInstOperands,
6281 /* 15794 */ // GIR_Coverage, 2206,
6282 /* 15794 */ GIR_EraseRootFromParent_Done,
6283 /* 15795 */ // Label 557: @15795
6284 /* 15795 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(15847), // Rule ID 2207 //
6285 /* 15800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6286 /* 15803 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6287 /* 15807 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6288 /* 15811 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6289 /* 15815 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6290 /* 15819 */ // MIs[1] Operand 1
6291 /* 15819 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6292 /* 15824 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
6293 /* 15828 */ // MIs[0] dst
6294 /* 15828 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6295 /* 15831 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6296 /* 15833 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6297 /* 15833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
6298 /* 15836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6299 /* 15840 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6300 /* 15842 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6301 /* 15845 */ GIR_RootConstrainSelectedInstOperands,
6302 /* 15846 */ // GIR_Coverage, 2207,
6303 /* 15846 */ GIR_EraseRootFromParent_Done,
6304 /* 15847 */ // Label 558: @15847
6305 /* 15847 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(15909), // Rule ID 92 //
6306 /* 15852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6307 /* 15855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6308 /* 15859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6309 /* 15863 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6310 /* 15867 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6311 /* 15871 */ // MIs[1] Operand 1
6312 /* 15871 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6313 /* 15876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6314 /* 15881 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6315 /* 15886 */ // MIs[0] offset
6316 /* 15886 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6317 /* 15889 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6318 /* 15891 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6319 /* 15891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6320 /* 15894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6321 /* 15898 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6322 /* 15902 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6323 /* 15904 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6324 /* 15907 */ GIR_RootConstrainSelectedInstOperands,
6325 /* 15908 */ // GIR_Coverage, 92,
6326 /* 15908 */ GIR_EraseRootFromParent_Done,
6327 /* 15909 */ // Label 559: @15909
6328 /* 15909 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(15971), // Rule ID 93 //
6329 /* 15914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6330 /* 15917 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6331 /* 15921 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6332 /* 15925 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6333 /* 15929 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6334 /* 15933 */ // MIs[1] Operand 1
6335 /* 15933 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6336 /* 15938 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6337 /* 15943 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6338 /* 15948 */ // MIs[0] offset
6339 /* 15948 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6340 /* 15951 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6341 /* 15953 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6342 /* 15953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
6343 /* 15956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6344 /* 15960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6345 /* 15964 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6346 /* 15966 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6347 /* 15969 */ GIR_RootConstrainSelectedInstOperands,
6348 /* 15970 */ // GIR_Coverage, 93,
6349 /* 15970 */ GIR_EraseRootFromParent_Done,
6350 /* 15971 */ // Label 560: @15971
6351 /* 15971 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(16033), // Rule ID 243 //
6352 /* 15976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
6353 /* 15979 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6354 /* 15983 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6355 /* 15987 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6356 /* 15991 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6357 /* 15995 */ // MIs[1] Operand 1
6358 /* 15995 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6359 /* 16000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6360 /* 16005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6361 /* 16010 */ // MIs[0] offset
6362 /* 16010 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6363 /* 16013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6364 /* 16015 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6365 /* 16015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
6366 /* 16018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6367 /* 16022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6368 /* 16026 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6369 /* 16028 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6370 /* 16031 */ GIR_RootConstrainSelectedInstOperands,
6371 /* 16032 */ // GIR_Coverage, 243,
6372 /* 16032 */ GIR_EraseRootFromParent_Done,
6373 /* 16033 */ // Label 561: @16033
6374 /* 16033 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(16095), // Rule ID 244 //
6375 /* 16038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
6376 /* 16041 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6377 /* 16045 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6378 /* 16049 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6379 /* 16053 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6380 /* 16057 */ // MIs[1] Operand 1
6381 /* 16057 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6382 /* 16062 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6383 /* 16067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6384 /* 16072 */ // MIs[0] offset
6385 /* 16072 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6386 /* 16075 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6387 /* 16077 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6388 /* 16077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6389 /* 16080 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6390 /* 16084 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6391 /* 16088 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6392 /* 16090 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6393 /* 16093 */ GIR_RootConstrainSelectedInstOperands,
6394 /* 16094 */ // GIR_Coverage, 244,
6395 /* 16094 */ GIR_EraseRootFromParent_Done,
6396 /* 16095 */ // Label 562: @16095
6397 /* 16095 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(16157), // Rule ID 1107 //
6398 /* 16100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6399 /* 16103 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6400 /* 16107 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6401 /* 16111 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6402 /* 16115 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6403 /* 16119 */ // MIs[1] Operand 1
6404 /* 16119 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6405 /* 16124 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6406 /* 16129 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6407 /* 16134 */ // MIs[0] offset
6408 /* 16134 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6409 /* 16137 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6410 /* 16139 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6411 /* 16139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6412 /* 16142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6413 /* 16146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6414 /* 16150 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6415 /* 16152 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6416 /* 16155 */ GIR_RootConstrainSelectedInstOperands,
6417 /* 16156 */ // GIR_Coverage, 1107,
6418 /* 16156 */ GIR_EraseRootFromParent_Done,
6419 /* 16157 */ // Label 563: @16157
6420 /* 16157 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(16219), // Rule ID 1108 //
6421 /* 16162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6422 /* 16165 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6423 /* 16169 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6424 /* 16173 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6425 /* 16177 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6426 /* 16181 */ // MIs[1] Operand 1
6427 /* 16181 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6428 /* 16186 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6429 /* 16191 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6430 /* 16196 */ // MIs[0] offset
6431 /* 16196 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6432 /* 16199 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6433 /* 16201 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6434 /* 16201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6435 /* 16204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6436 /* 16208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6437 /* 16212 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6438 /* 16214 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6439 /* 16217 */ GIR_RootConstrainSelectedInstOperands,
6440 /* 16218 */ // GIR_Coverage, 1108,
6441 /* 16218 */ GIR_EraseRootFromParent_Done,
6442 /* 16219 */ // Label 564: @16219
6443 /* 16219 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(16304), // Rule ID 1404 //
6444 /* 16224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6445 /* 16227 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6446 /* 16231 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6447 /* 16235 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6448 /* 16239 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6449 /* 16243 */ // MIs[1] Operand 1
6450 /* 16243 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6451 /* 16248 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6452 /* 16253 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6453 /* 16258 */ // MIs[0] dst
6454 /* 16258 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6455 /* 16261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6456 /* 16263 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6457 /* 16263 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6458 /* 16266 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6459 /* 16270 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6460 /* 16275 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6461 /* 16279 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6462 /* 16283 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6463 /* 16285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6464 /* 16288 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6465 /* 16291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6466 /* 16297 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6467 /* 16299 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6468 /* 16302 */ GIR_RootConstrainSelectedInstOperands,
6469 /* 16303 */ // GIR_Coverage, 1404,
6470 /* 16303 */ GIR_EraseRootFromParent_Done,
6471 /* 16304 */ // Label 565: @16304
6472 /* 16304 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(16389), // Rule ID 1405 //
6473 /* 16309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6474 /* 16312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6475 /* 16316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6476 /* 16320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6477 /* 16324 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6478 /* 16328 */ // MIs[1] Operand 1
6479 /* 16328 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6480 /* 16333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6481 /* 16338 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6482 /* 16343 */ // MIs[0] dst
6483 /* 16343 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6484 /* 16346 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6485 /* 16348 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6486 /* 16348 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6487 /* 16351 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6488 /* 16355 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6489 /* 16360 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6490 /* 16364 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6491 /* 16368 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6492 /* 16370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6493 /* 16373 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6494 /* 16376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6495 /* 16382 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6496 /* 16384 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6497 /* 16387 */ GIR_RootConstrainSelectedInstOperands,
6498 /* 16388 */ // GIR_Coverage, 1405,
6499 /* 16388 */ GIR_EraseRootFromParent_Done,
6500 /* 16389 */ // Label 566: @16389
6501 /* 16389 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(16474), // Rule ID 1410 //
6502 /* 16394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6503 /* 16397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6504 /* 16401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6505 /* 16405 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6506 /* 16409 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6507 /* 16413 */ // MIs[1] Operand 1
6508 /* 16413 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6509 /* 16418 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6510 /* 16423 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6511 /* 16428 */ // MIs[0] dst
6512 /* 16428 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6513 /* 16431 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6514 /* 16433 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6515 /* 16433 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6516 /* 16436 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6517 /* 16440 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6518 /* 16445 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6519 /* 16449 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6520 /* 16453 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6521 /* 16455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6522 /* 16458 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6523 /* 16461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6524 /* 16467 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6525 /* 16469 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6526 /* 16472 */ GIR_RootConstrainSelectedInstOperands,
6527 /* 16473 */ // GIR_Coverage, 1410,
6528 /* 16473 */ GIR_EraseRootFromParent_Done,
6529 /* 16474 */ // Label 567: @16474
6530 /* 16474 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(16559), // Rule ID 1411 //
6531 /* 16479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6532 /* 16482 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6533 /* 16486 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6534 /* 16490 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6535 /* 16494 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6536 /* 16498 */ // MIs[1] Operand 1
6537 /* 16498 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6538 /* 16503 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6539 /* 16508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6540 /* 16513 */ // MIs[0] dst
6541 /* 16513 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6542 /* 16516 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6543 /* 16518 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6544 /* 16518 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6545 /* 16521 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6546 /* 16525 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6547 /* 16530 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6548 /* 16534 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6549 /* 16538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6550 /* 16540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6551 /* 16543 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6552 /* 16546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6553 /* 16552 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6554 /* 16554 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6555 /* 16557 */ GIR_RootConstrainSelectedInstOperands,
6556 /* 16558 */ // GIR_Coverage, 1411,
6557 /* 16558 */ GIR_EraseRootFromParent_Done,
6558 /* 16559 */ // Label 568: @16559
6559 /* 16559 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(16644), // Rule ID 1550 //
6560 /* 16564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6561 /* 16567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6562 /* 16571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6563 /* 16575 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6564 /* 16579 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6565 /* 16583 */ // MIs[1] Operand 1
6566 /* 16583 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6567 /* 16588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6568 /* 16593 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6569 /* 16598 */ // MIs[0] dst
6570 /* 16598 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6571 /* 16601 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6572 /* 16603 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6573 /* 16603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6574 /* 16606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6575 /* 16610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6576 /* 16615 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6577 /* 16619 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6578 /* 16623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6579 /* 16625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6580 /* 16628 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6581 /* 16631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6582 /* 16637 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6583 /* 16639 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6584 /* 16642 */ GIR_RootConstrainSelectedInstOperands,
6585 /* 16643 */ // GIR_Coverage, 1550,
6586 /* 16643 */ GIR_EraseRootFromParent_Done,
6587 /* 16644 */ // Label 569: @16644
6588 /* 16644 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(16729), // Rule ID 1551 //
6589 /* 16649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6590 /* 16652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6591 /* 16656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6592 /* 16660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6593 /* 16664 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6594 /* 16668 */ // MIs[1] Operand 1
6595 /* 16668 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6596 /* 16673 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6597 /* 16678 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6598 /* 16683 */ // MIs[0] dst
6599 /* 16683 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6600 /* 16686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6601 /* 16688 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6602 /* 16688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6603 /* 16691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
6604 /* 16695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6605 /* 16700 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6606 /* 16704 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6607 /* 16708 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6608 /* 16710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6609 /* 16713 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6610 /* 16716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6611 /* 16722 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6612 /* 16724 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6613 /* 16727 */ GIR_RootConstrainSelectedInstOperands,
6614 /* 16728 */ // GIR_Coverage, 1551,
6615 /* 16728 */ GIR_EraseRootFromParent_Done,
6616 /* 16729 */ // Label 570: @16729
6617 /* 16729 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(16814), // Rule ID 1556 //
6618 /* 16734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6619 /* 16737 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6620 /* 16741 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6621 /* 16745 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6622 /* 16749 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6623 /* 16753 */ // MIs[1] Operand 1
6624 /* 16753 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6625 /* 16758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6626 /* 16763 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6627 /* 16768 */ // MIs[0] dst
6628 /* 16768 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6629 /* 16771 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6630 /* 16773 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6631 /* 16773 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6632 /* 16776 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6633 /* 16780 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6634 /* 16785 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6635 /* 16789 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6636 /* 16793 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6637 /* 16795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6638 /* 16798 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6639 /* 16801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6640 /* 16807 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6641 /* 16809 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6642 /* 16812 */ GIR_RootConstrainSelectedInstOperands,
6643 /* 16813 */ // GIR_Coverage, 1556,
6644 /* 16813 */ GIR_EraseRootFromParent_Done,
6645 /* 16814 */ // Label 571: @16814
6646 /* 16814 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(16899), // Rule ID 1557 //
6647 /* 16819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6648 /* 16822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6649 /* 16826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6650 /* 16830 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6651 /* 16834 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6652 /* 16838 */ // MIs[1] Operand 1
6653 /* 16838 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6654 /* 16843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6655 /* 16848 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6656 /* 16853 */ // MIs[0] dst
6657 /* 16853 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6658 /* 16856 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6659 /* 16858 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6660 /* 16858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6661 /* 16861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
6662 /* 16865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6663 /* 16870 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6664 /* 16874 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6665 /* 16878 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6666 /* 16880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6667 /* 16883 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6668 /* 16886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6669 /* 16892 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6670 /* 16894 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6671 /* 16897 */ GIR_RootConstrainSelectedInstOperands,
6672 /* 16898 */ // GIR_Coverage, 1557,
6673 /* 16898 */ GIR_EraseRootFromParent_Done,
6674 /* 16899 */ // Label 572: @16899
6675 /* 16899 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(16958), // Rule ID 1854 //
6676 /* 16904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6677 /* 16907 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6678 /* 16911 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6679 /* 16915 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6680 /* 16919 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6681 /* 16923 */ // MIs[1] Operand 1
6682 /* 16923 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6683 /* 16928 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6684 /* 16933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6685 /* 16938 */ // MIs[0] imm16
6686 /* 16938 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6687 /* 16941 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6688 /* 16943 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6689 /* 16943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8CmpX16),
6690 /* 16946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6691 /* 16950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6692 /* 16954 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6693 /* 16956 */ GIR_RootConstrainSelectedInstOperands,
6694 /* 16957 */ // GIR_Coverage, 1854,
6695 /* 16957 */ GIR_EraseRootFromParent_Done,
6696 /* 16958 */ // Label 573: @16958
6697 /* 16958 */ GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(17017), // Rule ID 1857 //
6698 /* 16963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6699 /* 16966 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6700 /* 16970 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6701 /* 16974 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6702 /* 16978 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6703 /* 16982 */ // MIs[1] Operand 1
6704 /* 16982 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6705 /* 16987 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6706 /* 16992 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6707 /* 16997 */ // MIs[0] imm16
6708 /* 16997 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6709 /* 17000 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6710 /* 17002 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
6711 /* 17002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
6712 /* 17005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6713 /* 17009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6714 /* 17013 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6715 /* 17015 */ GIR_RootConstrainSelectedInstOperands,
6716 /* 17016 */ // GIR_Coverage, 1857,
6717 /* 17016 */ GIR_EraseRootFromParent_Done,
6718 /* 17017 */ // Label 574: @17017
6719 /* 17017 */ GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(17076), // Rule ID 1858 //
6720 /* 17022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6721 /* 17025 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6722 /* 17029 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6723 /* 17033 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6724 /* 17037 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6725 /* 17041 */ // MIs[1] Operand 1
6726 /* 17041 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6727 /* 17046 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6728 /* 17051 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6729 /* 17056 */ // MIs[0] imm16
6730 /* 17056 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6731 /* 17059 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6732 /* 17061 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6733 /* 17061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
6734 /* 17064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6735 /* 17068 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6736 /* 17072 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6737 /* 17074 */ GIR_RootConstrainSelectedInstOperands,
6738 /* 17075 */ // GIR_Coverage, 1858,
6739 /* 17075 */ GIR_EraseRootFromParent_Done,
6740 /* 17076 */ // Label 575: @17076
6741 /* 17076 */ GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(17135), // Rule ID 1860 //
6742 /* 17081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6743 /* 17084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6744 /* 17088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6745 /* 17092 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6746 /* 17096 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6747 /* 17100 */ // MIs[1] Operand 1
6748 /* 17100 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6749 /* 17105 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6750 /* 17110 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6751 /* 17115 */ // MIs[0] imm16
6752 /* 17115 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6753 /* 17118 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6754 /* 17120 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6755 /* 17120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
6756 /* 17123 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6757 /* 17127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6758 /* 17131 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6759 /* 17133 */ GIR_RootConstrainSelectedInstOperands,
6760 /* 17134 */ // GIR_Coverage, 1860,
6761 /* 17134 */ GIR_EraseRootFromParent_Done,
6762 /* 17135 */ // Label 576: @17135
6763 /* 17135 */ GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(17194), // Rule ID 1862 //
6764 /* 17140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6765 /* 17143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6766 /* 17147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6767 /* 17151 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6768 /* 17155 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6769 /* 17159 */ // MIs[1] Operand 1
6770 /* 17159 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6771 /* 17164 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6772 /* 17169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6773 /* 17174 */ // MIs[0] imm16
6774 /* 17174 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6775 /* 17177 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6776 /* 17179 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
6777 /* 17179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
6778 /* 17182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6779 /* 17186 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6780 /* 17190 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6781 /* 17192 */ GIR_RootConstrainSelectedInstOperands,
6782 /* 17193 */ // GIR_Coverage, 1862,
6783 /* 17193 */ GIR_EraseRootFromParent_Done,
6784 /* 17194 */ // Label 577: @17194
6785 /* 17194 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(17253), // Rule ID 1863 //
6786 /* 17199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6787 /* 17202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6788 /* 17206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6789 /* 17210 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6790 /* 17214 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6791 /* 17218 */ // MIs[1] Operand 1
6792 /* 17218 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6793 /* 17223 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6794 /* 17228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6795 /* 17233 */ // MIs[0] imm16
6796 /* 17233 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6797 /* 17236 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6798 /* 17238 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6799 /* 17238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8CmpX16),
6800 /* 17241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6801 /* 17245 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6802 /* 17249 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6803 /* 17251 */ GIR_RootConstrainSelectedInstOperands,
6804 /* 17252 */ // GIR_Coverage, 1863,
6805 /* 17252 */ GIR_EraseRootFromParent_Done,
6806 /* 17253 */ // Label 578: @17253
6807 /* 17253 */ GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(17338), // Rule ID 2197 //
6808 /* 17258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6809 /* 17261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6810 /* 17265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6811 /* 17269 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6812 /* 17273 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6813 /* 17277 */ // MIs[1] Operand 1
6814 /* 17277 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6815 /* 17282 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6816 /* 17287 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6817 /* 17292 */ // MIs[0] dst
6818 /* 17292 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6819 /* 17295 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6820 /* 17297 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6821 /* 17297 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6822 /* 17300 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
6823 /* 17304 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6824 /* 17309 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6825 /* 17313 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6826 /* 17317 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6827 /* 17319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6828 /* 17322 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6829 /* 17325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6830 /* 17331 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6831 /* 17333 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6832 /* 17336 */ GIR_RootConstrainSelectedInstOperands,
6833 /* 17337 */ // GIR_Coverage, 2197,
6834 /* 17337 */ GIR_EraseRootFromParent_Done,
6835 /* 17338 */ // Label 579: @17338
6836 /* 17338 */ GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(17423), // Rule ID 2198 //
6837 /* 17343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6838 /* 17346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6839 /* 17350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6840 /* 17354 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6841 /* 17358 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6842 /* 17362 */ // MIs[1] Operand 1
6843 /* 17362 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6844 /* 17367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6845 /* 17372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6846 /* 17377 */ // MIs[0] dst
6847 /* 17377 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6848 /* 17380 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6849 /* 17382 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6850 /* 17382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6851 /* 17385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
6852 /* 17389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6853 /* 17394 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6854 /* 17398 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6855 /* 17402 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6856 /* 17404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6857 /* 17407 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6858 /* 17410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6859 /* 17416 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6860 /* 17418 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6861 /* 17421 */ GIR_RootConstrainSelectedInstOperands,
6862 /* 17422 */ // GIR_Coverage, 2198,
6863 /* 17422 */ GIR_EraseRootFromParent_Done,
6864 /* 17423 */ // Label 580: @17423
6865 /* 17423 */ GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(17508), // Rule ID 2203 //
6866 /* 17428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6867 /* 17431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6868 /* 17435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6869 /* 17439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6870 /* 17443 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6871 /* 17447 */ // MIs[1] Operand 1
6872 /* 17447 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6873 /* 17452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6874 /* 17457 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6875 /* 17462 */ // MIs[0] dst
6876 /* 17462 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6877 /* 17465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6878 /* 17467 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6879 /* 17467 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6880 /* 17470 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
6881 /* 17474 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6882 /* 17479 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6883 /* 17483 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6884 /* 17487 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6885 /* 17489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6886 /* 17492 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6887 /* 17495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6888 /* 17501 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6889 /* 17503 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6890 /* 17506 */ GIR_RootConstrainSelectedInstOperands,
6891 /* 17507 */ // GIR_Coverage, 2203,
6892 /* 17507 */ GIR_EraseRootFromParent_Done,
6893 /* 17508 */ // Label 581: @17508
6894 /* 17508 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(17593), // Rule ID 2204 //
6895 /* 17513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6896 /* 17516 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6897 /* 17520 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6898 /* 17524 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6899 /* 17528 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6900 /* 17532 */ // MIs[1] Operand 1
6901 /* 17532 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6902 /* 17537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6903 /* 17542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6904 /* 17547 */ // MIs[0] dst
6905 /* 17547 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6906 /* 17550 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6907 /* 17552 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6908 /* 17552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6909 /* 17555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
6910 /* 17559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6911 /* 17564 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6912 /* 17568 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6913 /* 17572 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6914 /* 17574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6915 /* 17577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6916 /* 17580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6917 /* 17586 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6918 /* 17588 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6919 /* 17591 */ GIR_RootConstrainSelectedInstOperands,
6920 /* 17592 */ // GIR_Coverage, 2204,
6921 /* 17592 */ GIR_EraseRootFromParent_Done,
6922 /* 17593 */ // Label 582: @17593
6923 /* 17593 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(17672), // Rule ID 2344 //
6924 /* 17598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6925 /* 17601 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6926 /* 17605 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6927 /* 17609 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6928 /* 17613 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6929 /* 17617 */ // MIs[1] Operand 1
6930 /* 17617 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6931 /* 17622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6932 /* 17627 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6933 /* 17632 */ // MIs[0] dst
6934 /* 17632 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6935 /* 17635 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6936 /* 17637 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
6937 /* 17637 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6938 /* 17640 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
6939 /* 17644 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6940 /* 17649 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6941 /* 17653 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6942 /* 17657 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6943 /* 17659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6944 /* 17662 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6945 /* 17665 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6946 /* 17667 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6947 /* 17670 */ GIR_RootConstrainSelectedInstOperands,
6948 /* 17671 */ // GIR_Coverage, 2344,
6949 /* 17671 */ GIR_EraseRootFromParent_Done,
6950 /* 17672 */ // Label 583: @17672
6951 /* 17672 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(17751), // Rule ID 2345 //
6952 /* 17677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6953 /* 17680 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6954 /* 17684 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6955 /* 17688 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6956 /* 17692 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6957 /* 17696 */ // MIs[1] Operand 1
6958 /* 17696 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6959 /* 17701 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6960 /* 17706 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6961 /* 17711 */ // MIs[0] dst
6962 /* 17711 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6963 /* 17714 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6964 /* 17716 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
6965 /* 17716 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6966 /* 17719 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
6967 /* 17723 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6968 /* 17728 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6969 /* 17732 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6970 /* 17736 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6971 /* 17738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6972 /* 17741 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6973 /* 17744 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6974 /* 17746 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6975 /* 17749 */ GIR_RootConstrainSelectedInstOperands,
6976 /* 17750 */ // GIR_Coverage, 2345,
6977 /* 17750 */ GIR_EraseRootFromParent_Done,
6978 /* 17751 */ // Label 584: @17751
6979 /* 17751 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(17830), // Rule ID 2350 //
6980 /* 17756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6981 /* 17759 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6982 /* 17763 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6983 /* 17767 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6984 /* 17771 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6985 /* 17775 */ // MIs[1] Operand 1
6986 /* 17775 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6987 /* 17780 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6988 /* 17785 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6989 /* 17790 */ // MIs[0] dst
6990 /* 17790 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6991 /* 17793 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6992 /* 17795 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
6993 /* 17795 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6994 /* 17798 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
6995 /* 17802 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6996 /* 17807 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6997 /* 17811 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6998 /* 17815 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6999 /* 17817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7000 /* 17820 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7001 /* 17823 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7002 /* 17825 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7003 /* 17828 */ GIR_RootConstrainSelectedInstOperands,
7004 /* 17829 */ // GIR_Coverage, 2350,
7005 /* 17829 */ GIR_EraseRootFromParent_Done,
7006 /* 17830 */ // Label 585: @17830
7007 /* 17830 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(17909), // Rule ID 2351 //
7008 /* 17835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7009 /* 17838 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7010 /* 17842 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7011 /* 17846 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7012 /* 17850 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7013 /* 17854 */ // MIs[1] Operand 1
7014 /* 17854 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7015 /* 17859 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7016 /* 17864 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7017 /* 17869 */ // MIs[0] dst
7018 /* 17869 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7019 /* 17872 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7020 /* 17874 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7021 /* 17874 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7022 /* 17877 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7023 /* 17881 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
7024 /* 17886 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7025 /* 17890 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7026 /* 17894 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7027 /* 17896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7028 /* 17899 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7029 /* 17902 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7030 /* 17904 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7031 /* 17907 */ GIR_RootConstrainSelectedInstOperands,
7032 /* 17908 */ // GIR_Coverage, 2351,
7033 /* 17908 */ GIR_EraseRootFromParent_Done,
7034 /* 17909 */ // Label 586: @17909
7035 /* 17909 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(17942), // Rule ID 1412 //
7036 /* 17914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
7037 /* 17917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7038 /* 17921 */ // MIs[0] dst
7039 /* 17921 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7040 /* 17924 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7041 /* 17924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
7042 /* 17927 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7043 /* 17929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7044 /* 17935 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7045 /* 17937 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7046 /* 17940 */ GIR_RootConstrainSelectedInstOperands,
7047 /* 17941 */ // GIR_Coverage, 1412,
7048 /* 17941 */ GIR_EraseRootFromParent_Done,
7049 /* 17942 */ // Label 587: @17942
7050 /* 17942 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(17964), // Rule ID 1866 //
7051 /* 17947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7052 /* 17950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7053 /* 17954 */ // MIs[0] targ16
7054 /* 17954 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7055 /* 17957 */ // (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
7056 /* 17957 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
7057 /* 17962 */ GIR_RootConstrainSelectedInstOperands,
7058 /* 17963 */ // GIR_Coverage, 1866,
7059 /* 17963 */ GIR_Done,
7060 /* 17964 */ // Label 588: @17964
7061 /* 17964 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(17997), // Rule ID 2205 //
7062 /* 17969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7063 /* 17972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7064 /* 17976 */ // MIs[0] dst
7065 /* 17976 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7066 /* 17979 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7067 /* 17979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
7068 /* 17982 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7069 /* 17984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7070 /* 17990 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7071 /* 17992 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7072 /* 17995 */ GIR_RootConstrainSelectedInstOperands,
7073 /* 17996 */ // GIR_Coverage, 2205,
7074 /* 17996 */ GIR_EraseRootFromParent_Done,
7075 /* 17997 */ // Label 589: @17997
7076 /* 17997 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(18025), // Rule ID 2352 //
7077 /* 18002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7078 /* 18005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7079 /* 18009 */ // MIs[0] dst
7080 /* 18009 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7081 /* 18012 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
7082 /* 18012 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
7083 /* 18017 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
7084 /* 18023 */ GIR_RootConstrainSelectedInstOperands,
7085 /* 18024 */ // GIR_Coverage, 2352,
7086 /* 18024 */ GIR_Done,
7087 /* 18025 */ // Label 590: @18025
7088 /* 18025 */ GIM_Reject,
7089 /* 18026 */ // Label 521: @18026
7090 /* 18026 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(18059), // Rule ID 1558 //
7091 /* 18031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
7092 /* 18034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7093 /* 18038 */ // MIs[0] dst
7094 /* 18038 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7095 /* 18041 */ // (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$cond, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
7096 /* 18041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
7097 /* 18044 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7098 /* 18046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7099 /* 18052 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7100 /* 18054 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7101 /* 18057 */ GIR_RootConstrainSelectedInstOperands,
7102 /* 18058 */ // GIR_Coverage, 1558,
7103 /* 18058 */ GIR_EraseRootFromParent_Done,
7104 /* 18059 */ // Label 591: @18059
7105 /* 18059 */ GIM_Reject,
7106 /* 18060 */ // Label 522: @18060
7107 /* 18060 */ GIM_Reject,
7108 /* 18061 */ // Label 29: @18061
7109 /* 18061 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(20058),
7110 /* 18066 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
7111 /* 18069 */ GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(18116), // Rule ID 428 //
7112 /* 18074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7113 /* 18077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7114 /* 18082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7115 /* 18085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7116 /* 18088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7117 /* 18092 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7118 /* 18096 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7119 /* 18100 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7120 /* 18104 */ // MIs[1] Operand 1
7121 /* 18104 */ // No operand predicates
7122 /* 18104 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7123 /* 18106 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8133:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7124 /* 18106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB),
7125 /* 18109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7126 /* 18111 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7127 /* 18114 */ GIR_RootConstrainSelectedInstOperands,
7128 /* 18115 */ // GIR_Coverage, 428,
7129 /* 18115 */ GIR_EraseRootFromParent_Done,
7130 /* 18116 */ // Label 593: @18116
7131 /* 18116 */ GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(18163), // Rule ID 429 //
7132 /* 18121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7133 /* 18124 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7134 /* 18129 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7135 /* 18132 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7136 /* 18135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7137 /* 18139 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7138 /* 18143 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7139 /* 18147 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7140 /* 18151 */ // MIs[1] Operand 1
7141 /* 18151 */ // No operand predicates
7142 /* 18151 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7143 /* 18153 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8132:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7144 /* 18153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH),
7145 /* 18156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7146 /* 18158 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7147 /* 18161 */ GIR_RootConstrainSelectedInstOperands,
7148 /* 18162 */ // GIR_Coverage, 429,
7149 /* 18162 */ GIR_EraseRootFromParent_Done,
7150 /* 18163 */ // Label 594: @18163
7151 /* 18163 */ GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(18210), // Rule ID 1288 //
7152 /* 18168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7153 /* 18171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7154 /* 18176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7155 /* 18179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7156 /* 18182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7157 /* 18186 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7158 /* 18190 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7159 /* 18194 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7160 /* 18198 */ // MIs[1] Operand 1
7161 /* 18198 */ // No operand predicates
7162 /* 18198 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7163 /* 18200 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8132:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7164 /* 18200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH_MM),
7165 /* 18203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7166 /* 18205 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7167 /* 18208 */ GIR_RootConstrainSelectedInstOperands,
7168 /* 18209 */ // GIR_Coverage, 1288,
7169 /* 18209 */ GIR_EraseRootFromParent_Done,
7170 /* 18210 */ // Label 595: @18210
7171 /* 18210 */ GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(18257), // Rule ID 1289 //
7172 /* 18215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7173 /* 18218 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7174 /* 18223 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7175 /* 18226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7176 /* 18229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7177 /* 18233 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7178 /* 18237 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7179 /* 18241 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7180 /* 18245 */ // MIs[1] Operand 1
7181 /* 18245 */ // No operand predicates
7182 /* 18245 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7183 /* 18247 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8133:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7184 /* 18247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB_MM),
7185 /* 18250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7186 /* 18252 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7187 /* 18255 */ GIR_RootConstrainSelectedInstOperands,
7188 /* 18256 */ // GIR_Coverage, 1289,
7189 /* 18256 */ GIR_EraseRootFromParent_Done,
7190 /* 18257 */ // Label 596: @18257
7191 /* 18257 */ GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(18293), // Rule ID 362 //
7192 /* 18262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7193 /* 18265 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7194 /* 18270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7195 /* 18273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7196 /* 18276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7197 /* 18280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7198 /* 18284 */ // (intrinsic_wo_chain:{ *:[i32] } 8130:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
7199 /* 18284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB),
7200 /* 18287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7201 /* 18289 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7202 /* 18291 */ GIR_RootConstrainSelectedInstOperands,
7203 /* 18292 */ // GIR_Coverage, 362,
7204 /* 18292 */ GIR_EraseRootFromParent_Done,
7205 /* 18293 */ // Label 597: @18293
7206 /* 18293 */ GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(18329), // Rule ID 369 //
7207 /* 18298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7208 /* 18301 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7209 /* 18306 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7210 /* 18309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7211 /* 18312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7212 /* 18316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7213 /* 18320 */ // (intrinsic_wo_chain:{ *:[i32] } 8112:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7214 /* 18320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL),
7215 /* 18323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7216 /* 18325 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7217 /* 18327 */ GIR_RootConstrainSelectedInstOperands,
7218 /* 18328 */ // GIR_Coverage, 369,
7219 /* 18328 */ GIR_EraseRootFromParent_Done,
7220 /* 18329 */ // Label 598: @18329
7221 /* 18329 */ GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(18365), // Rule ID 370 //
7222 /* 18334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7223 /* 18337 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7224 /* 18342 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7225 /* 18345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7226 /* 18348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7227 /* 18352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7228 /* 18356 */ // (intrinsic_wo_chain:{ *:[i32] } 8113:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7229 /* 18356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR),
7230 /* 18359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7231 /* 18361 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7232 /* 18363 */ GIR_RootConstrainSelectedInstOperands,
7233 /* 18364 */ // GIR_Coverage, 370,
7234 /* 18364 */ GIR_EraseRootFromParent_Done,
7235 /* 18365 */ // Label 599: @18365
7236 /* 18365 */ GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(18401), // Rule ID 371 //
7237 /* 18370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7238 /* 18373 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7239 /* 18378 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7240 /* 18381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7241 /* 18384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7242 /* 18388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7243 /* 18392 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8114:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7244 /* 18392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
7245 /* 18395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7246 /* 18397 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7247 /* 18399 */ GIR_RootConstrainSelectedInstOperands,
7248 /* 18400 */ // GIR_Coverage, 371,
7249 /* 18400 */ GIR_EraseRootFromParent_Done,
7250 /* 18401 */ // Label 600: @18401
7251 /* 18401 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(18437), // Rule ID 372 //
7252 /* 18406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7253 /* 18409 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7254 /* 18414 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7255 /* 18417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7256 /* 18420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7257 /* 18424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7258 /* 18428 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8116:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7259 /* 18428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
7260 /* 18431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7261 /* 18433 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7262 /* 18435 */ GIR_RootConstrainSelectedInstOperands,
7263 /* 18436 */ // GIR_Coverage, 372,
7264 /* 18436 */ GIR_EraseRootFromParent_Done,
7265 /* 18437 */ // Label 601: @18437
7266 /* 18437 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(18473), // Rule ID 373 //
7267 /* 18442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7268 /* 18445 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7269 /* 18450 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7270 /* 18453 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7271 /* 18456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7272 /* 18460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7273 /* 18464 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8115:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7274 /* 18464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
7275 /* 18467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7276 /* 18469 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7277 /* 18471 */ GIR_RootConstrainSelectedInstOperands,
7278 /* 18472 */ // GIR_Coverage, 373,
7279 /* 18472 */ GIR_EraseRootFromParent_Done,
7280 /* 18473 */ // Label 602: @18473
7281 /* 18473 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(18509), // Rule ID 374 //
7282 /* 18478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7283 /* 18481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
7284 /* 18486 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7285 /* 18489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7286 /* 18492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7287 /* 18496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7288 /* 18500 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8117:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7289 /* 18500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
7290 /* 18503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7291 /* 18505 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7292 /* 18507 */ GIR_RootConstrainSelectedInstOperands,
7293 /* 18508 */ // GIR_Coverage, 374,
7294 /* 18508 */ GIR_EraseRootFromParent_Done,
7295 /* 18509 */ // Label 603: @18509
7296 /* 18509 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(18545), // Rule ID 375 //
7297 /* 18514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7298 /* 18517 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
7299 /* 18522 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7300 /* 18525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7301 /* 18528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7302 /* 18532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7303 /* 18536 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8118:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7304 /* 18536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL),
7305 /* 18539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7306 /* 18541 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7307 /* 18543 */ GIR_RootConstrainSelectedInstOperands,
7308 /* 18544 */ // GIR_Coverage, 375,
7309 /* 18544 */ GIR_EraseRootFromParent_Done,
7310 /* 18545 */ // Label 604: @18545
7311 /* 18545 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(18581), // Rule ID 376 //
7312 /* 18550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7313 /* 18553 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
7314 /* 18558 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7315 /* 18561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7316 /* 18564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7317 /* 18568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7318 /* 18572 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8120:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7319 /* 18572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR),
7320 /* 18575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7321 /* 18577 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7322 /* 18579 */ GIR_RootConstrainSelectedInstOperands,
7323 /* 18580 */ // GIR_Coverage, 376,
7324 /* 18580 */ GIR_EraseRootFromParent_Done,
7325 /* 18581 */ // Label 605: @18581
7326 /* 18581 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(18617), // Rule ID 377 //
7327 /* 18586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7328 /* 18589 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
7329 /* 18594 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7330 /* 18597 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7331 /* 18600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7332 /* 18604 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7333 /* 18608 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8119:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7334 /* 18608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
7335 /* 18611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7336 /* 18613 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7337 /* 18615 */ GIR_RootConstrainSelectedInstOperands,
7338 /* 18616 */ // GIR_Coverage, 377,
7339 /* 18616 */ GIR_EraseRootFromParent_Done,
7340 /* 18617 */ // Label 606: @18617
7341 /* 18617 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(18653), // Rule ID 378 //
7342 /* 18622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7343 /* 18625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
7344 /* 18630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7345 /* 18633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7346 /* 18636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7347 /* 18640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7348 /* 18644 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8121:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7349 /* 18644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
7350 /* 18647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7351 /* 18649 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7352 /* 18651 */ GIR_RootConstrainSelectedInstOperands,
7353 /* 18652 */ // GIR_Coverage, 378,
7354 /* 18652 */ GIR_EraseRootFromParent_Done,
7355 /* 18653 */ // Label 607: @18653
7356 /* 18653 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(18689), // Rule ID 426 //
7357 /* 18658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7358 /* 18661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
7359 /* 18666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7360 /* 18669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7361 /* 18672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7362 /* 18676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7363 /* 18680 */ // (intrinsic_wo_chain:{ *:[i32] } 7686:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
7364 /* 18680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV),
7365 /* 18683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7366 /* 18685 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7367 /* 18687 */ GIR_RootConstrainSelectedInstOperands,
7368 /* 18688 */ // GIR_Coverage, 426,
7369 /* 18688 */ GIR_EraseRootFromParent_Done,
7370 /* 18689 */ // Label 608: @18689
7371 /* 18689 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(18725), // Rule ID 430 //
7372 /* 18694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7373 /* 18697 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7374 /* 18702 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7375 /* 18705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7376 /* 18708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7377 /* 18712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7378 /* 18716 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8133:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
7379 /* 18716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB),
7380 /* 18719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7381 /* 18721 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7382 /* 18723 */ GIR_RootConstrainSelectedInstOperands,
7383 /* 18724 */ // GIR_Coverage, 430,
7384 /* 18724 */ GIR_EraseRootFromParent_Done,
7385 /* 18725 */ // Label 609: @18725
7386 /* 18725 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(18761), // Rule ID 431 //
7387 /* 18730 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7388 /* 18733 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7389 /* 18738 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7390 /* 18741 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7391 /* 18744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7392 /* 18748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7393 /* 18752 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8132:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
7394 /* 18752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH),
7395 /* 18755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7396 /* 18757 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7397 /* 18759 */ GIR_RootConstrainSelectedInstOperands,
7398 /* 18760 */ // GIR_Coverage, 431,
7399 /* 18760 */ GIR_EraseRootFromParent_Done,
7400 /* 18761 */ // Label 610: @18761
7401 /* 18761 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(18797), // Rule ID 680 //
7402 /* 18766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7403 /* 18769 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_w),
7404 /* 18774 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7405 /* 18777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7406 /* 18780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7407 /* 18784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7408 /* 18788 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7838:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7409 /* 18788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_W),
7410 /* 18791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7411 /* 18793 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7412 /* 18795 */ GIR_RootConstrainSelectedInstOperands,
7413 /* 18796 */ // GIR_Coverage, 680,
7414 /* 18796 */ GIR_EraseRootFromParent_Done,
7415 /* 18797 */ // Label 611: @18797
7416 /* 18797 */ GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(18833), // Rule ID 681 //
7417 /* 18802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7418 /* 18805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_d),
7419 /* 18810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7420 /* 18813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7421 /* 18816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7422 /* 18820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7423 /* 18824 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7837:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7424 /* 18824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_D),
7425 /* 18827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7426 /* 18829 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7427 /* 18831 */ GIR_RootConstrainSelectedInstOperands,
7428 /* 18832 */ // GIR_Coverage, 681,
7429 /* 18832 */ GIR_EraseRootFromParent_Done,
7430 /* 18833 */ // Label 612: @18833
7431 /* 18833 */ GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(18869), // Rule ID 704 //
7432 /* 18838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7433 /* 18841 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
7434 /* 18846 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7435 /* 18849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7436 /* 18852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7437 /* 18856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7438 /* 18860 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7864:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
7439 /* 18860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_W),
7440 /* 18863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7441 /* 18865 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7442 /* 18867 */ GIR_RootConstrainSelectedInstOperands,
7443 /* 18868 */ // GIR_Coverage, 704,
7444 /* 18868 */ GIR_EraseRootFromParent_Done,
7445 /* 18869 */ // Label 613: @18869
7446 /* 18869 */ GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(18905), // Rule ID 705 //
7447 /* 18874 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7448 /* 18877 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
7449 /* 18882 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7450 /* 18885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7451 /* 18888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7452 /* 18892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7453 /* 18896 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7863:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7454 /* 18896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_D),
7455 /* 18899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7456 /* 18901 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7457 /* 18903 */ GIR_RootConstrainSelectedInstOperands,
7458 /* 18904 */ // GIR_Coverage, 705,
7459 /* 18904 */ GIR_EraseRootFromParent_Done,
7460 /* 18905 */ // Label 614: @18905
7461 /* 18905 */ GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(18941), // Rule ID 706 //
7462 /* 18910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7463 /* 18913 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
7464 /* 18918 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7465 /* 18921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7466 /* 18924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7467 /* 18928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7468 /* 18932 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7866:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
7469 /* 18932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_W),
7470 /* 18935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7471 /* 18937 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7472 /* 18939 */ GIR_RootConstrainSelectedInstOperands,
7473 /* 18940 */ // GIR_Coverage, 706,
7474 /* 18940 */ GIR_EraseRootFromParent_Done,
7475 /* 18941 */ // Label 615: @18941
7476 /* 18941 */ GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(18977), // Rule ID 707 //
7477 /* 18946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7478 /* 18949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
7479 /* 18954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7480 /* 18957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7481 /* 18960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7482 /* 18964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7483 /* 18968 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7865:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7484 /* 18968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_D),
7485 /* 18971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7486 /* 18973 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7487 /* 18975 */ GIR_RootConstrainSelectedInstOperands,
7488 /* 18976 */ // GIR_Coverage, 707,
7489 /* 18976 */ GIR_EraseRootFromParent_Done,
7490 /* 18977 */ // Label 616: @18977
7491 /* 18977 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(19013), // Rule ID 712 //
7492 /* 18982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7493 /* 18985 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_w),
7494 /* 18990 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7495 /* 18993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7496 /* 18996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7497 /* 19000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7498 /* 19004 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7872:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7499 /* 19004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_W),
7500 /* 19007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7501 /* 19009 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7502 /* 19011 */ GIR_RootConstrainSelectedInstOperands,
7503 /* 19012 */ // GIR_Coverage, 712,
7504 /* 19012 */ GIR_EraseRootFromParent_Done,
7505 /* 19013 */ // Label 617: @19013
7506 /* 19013 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(19049), // Rule ID 713 //
7507 /* 19018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7508 /* 19021 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_d),
7509 /* 19026 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7510 /* 19029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7511 /* 19032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7512 /* 19036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7513 /* 19040 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7871:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
7514 /* 19040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_D),
7515 /* 19043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7516 /* 19045 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7517 /* 19047 */ GIR_RootConstrainSelectedInstOperands,
7518 /* 19048 */ // GIR_Coverage, 713,
7519 /* 19048 */ GIR_EraseRootFromParent_Done,
7520 /* 19049 */ // Label 618: @19049
7521 /* 19049 */ GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(19085), // Rule ID 714 //
7522 /* 19054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7523 /* 19057 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
7524 /* 19062 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7525 /* 19065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7526 /* 19068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7527 /* 19072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7528 /* 19076 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7874:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7529 /* 19076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_W),
7530 /* 19079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7531 /* 19081 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7532 /* 19083 */ GIR_RootConstrainSelectedInstOperands,
7533 /* 19084 */ // GIR_Coverage, 714,
7534 /* 19084 */ GIR_EraseRootFromParent_Done,
7535 /* 19085 */ // Label 619: @19085
7536 /* 19085 */ GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(19121), // Rule ID 715 //
7537 /* 19090 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7538 /* 19093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
7539 /* 19098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7540 /* 19101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7541 /* 19104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7542 /* 19108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7543 /* 19112 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7873:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
7544 /* 19112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_D),
7545 /* 19115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7546 /* 19117 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7547 /* 19119 */ GIR_RootConstrainSelectedInstOperands,
7548 /* 19120 */ // GIR_Coverage, 715,
7549 /* 19120 */ GIR_EraseRootFromParent_Done,
7550 /* 19121 */ // Label 620: @19121
7551 /* 19121 */ GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(19157), // Rule ID 740 //
7552 /* 19126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7553 /* 19129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_w),
7554 /* 19134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7555 /* 19137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7556 /* 19140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7557 /* 19144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7558 /* 19148 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7896:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7559 /* 19148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_W),
7560 /* 19151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7561 /* 19153 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7562 /* 19155 */ GIR_RootConstrainSelectedInstOperands,
7563 /* 19156 */ // GIR_Coverage, 740,
7564 /* 19156 */ GIR_EraseRootFromParent_Done,
7565 /* 19157 */ // Label 621: @19157
7566 /* 19157 */ GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(19193), // Rule ID 741 //
7567 /* 19162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7568 /* 19165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_d),
7569 /* 19170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7570 /* 19173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7571 /* 19176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7572 /* 19180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7573 /* 19184 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7895:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7574 /* 19184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_D),
7575 /* 19187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7576 /* 19189 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7577 /* 19191 */ GIR_RootConstrainSelectedInstOperands,
7578 /* 19192 */ // GIR_Coverage, 741,
7579 /* 19192 */ GIR_EraseRootFromParent_Done,
7580 /* 19193 */ // Label 622: @19193
7581 /* 19193 */ GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(19229), // Rule ID 742 //
7582 /* 19198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7583 /* 19201 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
7584 /* 19206 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7585 /* 19209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7586 /* 19212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7587 /* 19216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7588 /* 19220 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7900:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7589 /* 19220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_W),
7590 /* 19223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7591 /* 19225 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7592 /* 19227 */ GIR_RootConstrainSelectedInstOperands,
7593 /* 19228 */ // GIR_Coverage, 742,
7594 /* 19228 */ GIR_EraseRootFromParent_Done,
7595 /* 19229 */ // Label 623: @19229
7596 /* 19229 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(19265), // Rule ID 743 //
7597 /* 19234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7598 /* 19237 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
7599 /* 19242 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7600 /* 19245 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7601 /* 19248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7602 /* 19252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7603 /* 19256 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7899:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7604 /* 19256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_D),
7605 /* 19259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7606 /* 19261 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7607 /* 19263 */ GIR_RootConstrainSelectedInstOperands,
7608 /* 19264 */ // GIR_Coverage, 743,
7609 /* 19264 */ GIR_EraseRootFromParent_Done,
7610 /* 19265 */ // Label 624: @19265
7611 /* 19265 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(19301), // Rule ID 770 //
7612 /* 19270 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7613 /* 19273 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
7614 /* 19278 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7615 /* 19281 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7616 /* 19284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7617 /* 19288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7618 /* 19292 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7928:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7619 /* 19292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_W),
7620 /* 19295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7621 /* 19297 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7622 /* 19299 */ GIR_RootConstrainSelectedInstOperands,
7623 /* 19300 */ // GIR_Coverage, 770,
7624 /* 19300 */ GIR_EraseRootFromParent_Done,
7625 /* 19301 */ // Label 625: @19301
7626 /* 19301 */ GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(19337), // Rule ID 771 //
7627 /* 19306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7628 /* 19309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
7629 /* 19314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7630 /* 19317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7631 /* 19320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7632 /* 19324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7633 /* 19328 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7927:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7634 /* 19328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_D),
7635 /* 19331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7636 /* 19333 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7637 /* 19335 */ GIR_RootConstrainSelectedInstOperands,
7638 /* 19336 */ // GIR_Coverage, 771,
7639 /* 19336 */ GIR_EraseRootFromParent_Done,
7640 /* 19337 */ // Label 626: @19337
7641 /* 19337 */ GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(19373), // Rule ID 772 //
7642 /* 19342 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7643 /* 19345 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
7644 /* 19350 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7645 /* 19353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7646 /* 19356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7647 /* 19360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7648 /* 19364 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7930:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7649 /* 19364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_W),
7650 /* 19367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7651 /* 19369 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7652 /* 19371 */ GIR_RootConstrainSelectedInstOperands,
7653 /* 19372 */ // GIR_Coverage, 772,
7654 /* 19372 */ GIR_EraseRootFromParent_Done,
7655 /* 19373 */ // Label 627: @19373
7656 /* 19373 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(19409), // Rule ID 773 //
7657 /* 19378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7658 /* 19381 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
7659 /* 19386 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7660 /* 19389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7661 /* 19392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7662 /* 19396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7663 /* 19400 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7929:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7664 /* 19400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_D),
7665 /* 19403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7666 /* 19405 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7667 /* 19407 */ GIR_RootConstrainSelectedInstOperands,
7668 /* 19408 */ // GIR_Coverage, 773,
7669 /* 19408 */ GIR_EraseRootFromParent_Done,
7670 /* 19409 */ // Label 628: @19409
7671 /* 19409 */ GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(19445), // Rule ID 908 //
7672 /* 19414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7673 /* 19417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_b),
7674 /* 19422 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
7675 /* 19425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7676 /* 19428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7677 /* 19432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7678 /* 19436 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8085:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
7679 /* 19436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_B),
7680 /* 19439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7681 /* 19441 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7682 /* 19443 */ GIR_RootConstrainSelectedInstOperands,
7683 /* 19444 */ // GIR_Coverage, 908,
7684 /* 19444 */ GIR_EraseRootFromParent_Done,
7685 /* 19445 */ // Label 629: @19445
7686 /* 19445 */ GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(19481), // Rule ID 909 //
7687 /* 19450 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7688 /* 19453 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_h),
7689 /* 19458 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
7690 /* 19461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7691 /* 19464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7692 /* 19468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7693 /* 19472 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8087:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7694 /* 19472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_H),
7695 /* 19475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7696 /* 19477 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7697 /* 19479 */ GIR_RootConstrainSelectedInstOperands,
7698 /* 19480 */ // GIR_Coverage, 909,
7699 /* 19480 */ GIR_EraseRootFromParent_Done,
7700 /* 19481 */ // Label 630: @19481
7701 /* 19481 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(19517), // Rule ID 910 //
7702 /* 19486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7703 /* 19489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_w),
7704 /* 19494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7705 /* 19497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7706 /* 19500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7707 /* 19504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7708 /* 19508 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8088:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
7709 /* 19508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_W),
7710 /* 19511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7711 /* 19513 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7712 /* 19515 */ GIR_RootConstrainSelectedInstOperands,
7713 /* 19516 */ // GIR_Coverage, 910,
7714 /* 19516 */ GIR_EraseRootFromParent_Done,
7715 /* 19517 */ // Label 631: @19517
7716 /* 19517 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(19553), // Rule ID 911 //
7717 /* 19522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7718 /* 19525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_d),
7719 /* 19530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7720 /* 19533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7721 /* 19536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7722 /* 19540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7723 /* 19544 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8086:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
7724 /* 19544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_D),
7725 /* 19547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7726 /* 19549 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7727 /* 19551 */ GIR_RootConstrainSelectedInstOperands,
7728 /* 19552 */ // GIR_Coverage, 911,
7729 /* 19552 */ GIR_EraseRootFromParent_Done,
7730 /* 19553 */ // Label 632: @19553
7731 /* 19553 */ GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(19589), // Rule ID 1251 //
7732 /* 19558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7733 /* 19561 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7734 /* 19566 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7735 /* 19569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7736 /* 19572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7737 /* 19576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7738 /* 19580 */ // (intrinsic_wo_chain:{ *:[i32] } 8112:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
7739 /* 19580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
7740 /* 19583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7741 /* 19585 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7742 /* 19587 */ GIR_RootConstrainSelectedInstOperands,
7743 /* 19588 */ // GIR_Coverage, 1251,
7744 /* 19588 */ GIR_EraseRootFromParent_Done,
7745 /* 19589 */ // Label 633: @19589
7746 /* 19589 */ GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(19625), // Rule ID 1252 //
7747 /* 19594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7748 /* 19597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7749 /* 19602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7750 /* 19605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7751 /* 19608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7752 /* 19612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7753 /* 19616 */ // (intrinsic_wo_chain:{ *:[i32] } 8113:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
7754 /* 19616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
7755 /* 19619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7756 /* 19621 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7757 /* 19623 */ GIR_RootConstrainSelectedInstOperands,
7758 /* 19624 */ // GIR_Coverage, 1252,
7759 /* 19624 */ GIR_EraseRootFromParent_Done,
7760 /* 19625 */ // Label 634: @19625
7761 /* 19625 */ GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(19661), // Rule ID 1253 //
7762 /* 19630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7763 /* 19633 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7764 /* 19638 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7765 /* 19641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7766 /* 19644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7767 /* 19648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7768 /* 19652 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8114:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7769 /* 19652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
7770 /* 19655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7771 /* 19657 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7772 /* 19659 */ GIR_RootConstrainSelectedInstOperands,
7773 /* 19660 */ // GIR_Coverage, 1253,
7774 /* 19660 */ GIR_EraseRootFromParent_Done,
7775 /* 19661 */ // Label 635: @19661
7776 /* 19661 */ GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(19697), // Rule ID 1254 //
7777 /* 19666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7778 /* 19669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7779 /* 19674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7780 /* 19677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7781 /* 19680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7782 /* 19684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7783 /* 19688 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8115:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7784 /* 19688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
7785 /* 19691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7786 /* 19693 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7787 /* 19695 */ GIR_RootConstrainSelectedInstOperands,
7788 /* 19696 */ // GIR_Coverage, 1254,
7789 /* 19696 */ GIR_EraseRootFromParent_Done,
7790 /* 19697 */ // Label 636: @19697
7791 /* 19697 */ GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(19733), // Rule ID 1255 //
7792 /* 19702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7793 /* 19705 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7794 /* 19710 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7795 /* 19713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7796 /* 19716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7797 /* 19720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7798 /* 19724 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8116:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7799 /* 19724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
7800 /* 19727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7801 /* 19729 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7802 /* 19731 */ GIR_RootConstrainSelectedInstOperands,
7803 /* 19732 */ // GIR_Coverage, 1255,
7804 /* 19732 */ GIR_EraseRootFromParent_Done,
7805 /* 19733 */ // Label 637: @19733
7806 /* 19733 */ GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(19769), // Rule ID 1256 //
7807 /* 19738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7808 /* 19741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
7809 /* 19746 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7810 /* 19749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7811 /* 19752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7812 /* 19756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7813 /* 19760 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8117:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7814 /* 19760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
7815 /* 19763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7816 /* 19765 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7817 /* 19767 */ GIR_RootConstrainSelectedInstOperands,
7818 /* 19768 */ // GIR_Coverage, 1256,
7819 /* 19768 */ GIR_EraseRootFromParent_Done,
7820 /* 19769 */ // Label 638: @19769
7821 /* 19769 */ GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(19805), // Rule ID 1257 //
7822 /* 19774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7823 /* 19777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
7824 /* 19782 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7825 /* 19785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7826 /* 19788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7827 /* 19792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7828 /* 19796 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8118:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7829 /* 19796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
7830 /* 19799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7831 /* 19801 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7832 /* 19803 */ GIR_RootConstrainSelectedInstOperands,
7833 /* 19804 */ // GIR_Coverage, 1257,
7834 /* 19804 */ GIR_EraseRootFromParent_Done,
7835 /* 19805 */ // Label 639: @19805
7836 /* 19805 */ GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(19841), // Rule ID 1258 //
7837 /* 19810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7838 /* 19813 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
7839 /* 19818 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7840 /* 19821 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7841 /* 19824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7842 /* 19828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7843 /* 19832 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8119:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7844 /* 19832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
7845 /* 19835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7846 /* 19837 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7847 /* 19839 */ GIR_RootConstrainSelectedInstOperands,
7848 /* 19840 */ // GIR_Coverage, 1258,
7849 /* 19840 */ GIR_EraseRootFromParent_Done,
7850 /* 19841 */ // Label 640: @19841
7851 /* 19841 */ GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(19877), // Rule ID 1259 //
7852 /* 19846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7853 /* 19849 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
7854 /* 19854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7855 /* 19857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7856 /* 19860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7857 /* 19864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7858 /* 19868 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8120:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7859 /* 19868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
7860 /* 19871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7861 /* 19873 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7862 /* 19875 */ GIR_RootConstrainSelectedInstOperands,
7863 /* 19876 */ // GIR_Coverage, 1259,
7864 /* 19876 */ GIR_EraseRootFromParent_Done,
7865 /* 19877 */ // Label 641: @19877
7866 /* 19877 */ GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(19913), // Rule ID 1260 //
7867 /* 19882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7868 /* 19885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
7869 /* 19890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7870 /* 19893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7871 /* 19896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7872 /* 19900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7873 /* 19904 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8121:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7874 /* 19904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
7875 /* 19907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7876 /* 19909 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7877 /* 19911 */ GIR_RootConstrainSelectedInstOperands,
7878 /* 19912 */ // GIR_Coverage, 1260,
7879 /* 19912 */ GIR_EraseRootFromParent_Done,
7880 /* 19913 */ // Label 642: @19913
7881 /* 19913 */ GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(19949), // Rule ID 1286 //
7882 /* 19918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7883 /* 19921 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7884 /* 19926 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7885 /* 19929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7886 /* 19932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7887 /* 19936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7888 /* 19940 */ // (intrinsic_wo_chain:{ *:[i32] } 8130:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
7889 /* 19940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB_MM),
7890 /* 19943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7891 /* 19945 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7892 /* 19947 */ GIR_RootConstrainSelectedInstOperands,
7893 /* 19948 */ // GIR_Coverage, 1286,
7894 /* 19948 */ GIR_EraseRootFromParent_Done,
7895 /* 19949 */ // Label 643: @19949
7896 /* 19949 */ GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(19985), // Rule ID 1290 //
7897 /* 19954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7898 /* 19957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7899 /* 19962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7900 /* 19965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7901 /* 19968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7902 /* 19972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7903 /* 19976 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8132:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
7904 /* 19976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH_MM),
7905 /* 19979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7906 /* 19981 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7907 /* 19983 */ GIR_RootConstrainSelectedInstOperands,
7908 /* 19984 */ // GIR_Coverage, 1290,
7909 /* 19984 */ GIR_EraseRootFromParent_Done,
7910 /* 19985 */ // Label 644: @19985
7911 /* 19985 */ GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(20021), // Rule ID 1291 //
7912 /* 19990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7913 /* 19993 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7914 /* 19998 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7915 /* 20001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7916 /* 20004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7917 /* 20008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7918 /* 20012 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8133:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
7919 /* 20012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB_MM),
7920 /* 20015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7921 /* 20017 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7922 /* 20019 */ GIR_RootConstrainSelectedInstOperands,
7923 /* 20020 */ // GIR_Coverage, 1291,
7924 /* 20020 */ GIR_EraseRootFromParent_Done,
7925 /* 20021 */ // Label 645: @20021
7926 /* 20021 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(20057), // Rule ID 1301 //
7927 /* 20026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7928 /* 20029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
7929 /* 20034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7930 /* 20037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7931 /* 20040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7932 /* 20044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7933 /* 20048 */ // (intrinsic_wo_chain:{ *:[i32] } 7686:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
7934 /* 20048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV_MM),
7935 /* 20051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7936 /* 20053 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7937 /* 20055 */ GIR_RootConstrainSelectedInstOperands,
7938 /* 20056 */ // GIR_Coverage, 1301,
7939 /* 20056 */ GIR_EraseRootFromParent_Done,
7940 /* 20057 */ // Label 646: @20057
7941 /* 20057 */ GIM_Reject,
7942 /* 20058 */ // Label 592: @20058
7943 /* 20058 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(29811),
7944 /* 20063 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
7945 /* 20066 */ GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(20112), // Rule ID 938 //
7946 /* 20071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7947 /* 20074 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
7948 /* 20079 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
7949 /* 20082 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7950 /* 20085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7951 /* 20089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7952 /* 20093 */ // MIs[0] m
7953 /* 20093 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7954 /* 20096 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
7955 /* 20101 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8134:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
7956 /* 20101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_B),
7957 /* 20104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7958 /* 20106 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7959 /* 20108 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
7960 /* 20110 */ GIR_RootConstrainSelectedInstOperands,
7961 /* 20111 */ // GIR_Coverage, 938,
7962 /* 20111 */ GIR_EraseRootFromParent_Done,
7963 /* 20112 */ // Label 648: @20112
7964 /* 20112 */ GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(20158), // Rule ID 939 //
7965 /* 20117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7966 /* 20120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
7967 /* 20125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
7968 /* 20128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7969 /* 20131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7970 /* 20135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7971 /* 20139 */ // MIs[0] m
7972 /* 20139 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7973 /* 20142 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
7974 /* 20147 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8136:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
7975 /* 20147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_H),
7976 /* 20150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7977 /* 20152 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7978 /* 20154 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
7979 /* 20156 */ GIR_RootConstrainSelectedInstOperands,
7980 /* 20157 */ // GIR_Coverage, 939,
7981 /* 20157 */ GIR_EraseRootFromParent_Done,
7982 /* 20158 */ // Label 649: @20158
7983 /* 20158 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(20204), // Rule ID 940 //
7984 /* 20163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7985 /* 20166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
7986 /* 20171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7987 /* 20174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7988 /* 20177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7989 /* 20181 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7990 /* 20185 */ // MIs[0] m
7991 /* 20185 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7992 /* 20188 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
7993 /* 20193 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8137:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
7994 /* 20193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_W),
7995 /* 20196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7996 /* 20198 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7997 /* 20200 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
7998 /* 20202 */ GIR_RootConstrainSelectedInstOperands,
7999 /* 20203 */ // GIR_Coverage, 940,
8000 /* 20203 */ GIR_EraseRootFromParent_Done,
8001 /* 20204 */ // Label 650: @20204
8002 /* 20204 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(20250), // Rule ID 941 //
8003 /* 20209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8004 /* 20212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
8005 /* 20217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8006 /* 20220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8007 /* 20223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8008 /* 20227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8009 /* 20231 */ // MIs[0] m
8010 /* 20231 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8011 /* 20234 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8012 /* 20239 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8135:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8013 /* 20239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_D),
8014 /* 20242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8015 /* 20244 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8016 /* 20246 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8017 /* 20248 */ GIR_RootConstrainSelectedInstOperands,
8018 /* 20249 */ // GIR_Coverage, 941,
8019 /* 20249 */ GIR_EraseRootFromParent_Done,
8020 /* 20250 */ // Label 651: @20250
8021 /* 20250 */ GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(20296), // Rule ID 942 //
8022 /* 20255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8023 /* 20258 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
8024 /* 20263 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8025 /* 20266 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8026 /* 20269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8027 /* 20273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8028 /* 20277 */ // MIs[0] m
8029 /* 20277 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8030 /* 20280 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8031 /* 20285 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8138:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8032 /* 20285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_B),
8033 /* 20288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8034 /* 20290 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8035 /* 20292 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8036 /* 20294 */ GIR_RootConstrainSelectedInstOperands,
8037 /* 20295 */ // GIR_Coverage, 942,
8038 /* 20295 */ GIR_EraseRootFromParent_Done,
8039 /* 20296 */ // Label 652: @20296
8040 /* 20296 */ GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(20342), // Rule ID 943 //
8041 /* 20301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8042 /* 20304 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
8043 /* 20309 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8044 /* 20312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8045 /* 20315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8046 /* 20319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8047 /* 20323 */ // MIs[0] m
8048 /* 20323 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8049 /* 20326 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8050 /* 20331 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8140:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8051 /* 20331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_H),
8052 /* 20334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8053 /* 20336 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8054 /* 20338 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8055 /* 20340 */ GIR_RootConstrainSelectedInstOperands,
8056 /* 20341 */ // GIR_Coverage, 943,
8057 /* 20341 */ GIR_EraseRootFromParent_Done,
8058 /* 20342 */ // Label 653: @20342
8059 /* 20342 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(20388), // Rule ID 944 //
8060 /* 20347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8061 /* 20350 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
8062 /* 20355 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8063 /* 20358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8064 /* 20361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8065 /* 20365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8066 /* 20369 */ // MIs[0] m
8067 /* 20369 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8068 /* 20372 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8069 /* 20377 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8141:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8070 /* 20377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_W),
8071 /* 20380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8072 /* 20382 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8073 /* 20384 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8074 /* 20386 */ GIR_RootConstrainSelectedInstOperands,
8075 /* 20387 */ // GIR_Coverage, 944,
8076 /* 20387 */ GIR_EraseRootFromParent_Done,
8077 /* 20388 */ // Label 654: @20388
8078 /* 20388 */ GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(20434), // Rule ID 945 //
8079 /* 20393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8080 /* 20396 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
8081 /* 20401 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8082 /* 20404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8083 /* 20407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8084 /* 20411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8085 /* 20415 */ // MIs[0] m
8086 /* 20415 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8087 /* 20418 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8088 /* 20423 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8139:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8089 /* 20423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_D),
8090 /* 20426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8091 /* 20428 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8092 /* 20430 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8093 /* 20432 */ GIR_RootConstrainSelectedInstOperands,
8094 /* 20433 */ // GIR_Coverage, 945,
8095 /* 20433 */ GIR_EraseRootFromParent_Done,
8096 /* 20434 */ // Label 655: @20434
8097 /* 20434 */ GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(20480), // Rule ID 985 //
8098 /* 20439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8099 /* 20442 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_b),
8100 /* 20447 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8101 /* 20450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8102 /* 20453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8103 /* 20457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8104 /* 20461 */ // MIs[0] m
8105 /* 20461 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8106 /* 20464 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8107 /* 20469 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8193:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8108 /* 20469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_B),
8109 /* 20472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8110 /* 20474 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8111 /* 20476 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8112 /* 20478 */ GIR_RootConstrainSelectedInstOperands,
8113 /* 20479 */ // GIR_Coverage, 985,
8114 /* 20479 */ GIR_EraseRootFromParent_Done,
8115 /* 20480 */ // Label 656: @20480
8116 /* 20480 */ GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(20526), // Rule ID 986 //
8117 /* 20485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8118 /* 20488 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_h),
8119 /* 20493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8120 /* 20496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8121 /* 20499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8122 /* 20503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8123 /* 20507 */ // MIs[0] m
8124 /* 20507 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8125 /* 20510 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8126 /* 20515 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8195:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8127 /* 20515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_H),
8128 /* 20518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8129 /* 20520 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8130 /* 20522 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8131 /* 20524 */ GIR_RootConstrainSelectedInstOperands,
8132 /* 20525 */ // GIR_Coverage, 986,
8133 /* 20525 */ GIR_EraseRootFromParent_Done,
8134 /* 20526 */ // Label 657: @20526
8135 /* 20526 */ GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(20572), // Rule ID 987 //
8136 /* 20531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8137 /* 20534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_w),
8138 /* 20539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8139 /* 20542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8140 /* 20545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8141 /* 20549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8142 /* 20553 */ // MIs[0] m
8143 /* 20553 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8144 /* 20556 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8145 /* 20561 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8196:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8146 /* 20561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_W),
8147 /* 20564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8148 /* 20566 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8149 /* 20568 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8150 /* 20570 */ GIR_RootConstrainSelectedInstOperands,
8151 /* 20571 */ // GIR_Coverage, 987,
8152 /* 20571 */ GIR_EraseRootFromParent_Done,
8153 /* 20572 */ // Label 658: @20572
8154 /* 20572 */ GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(20618), // Rule ID 988 //
8155 /* 20577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8156 /* 20580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_d),
8157 /* 20585 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8158 /* 20588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8159 /* 20591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8160 /* 20595 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8161 /* 20599 */ // MIs[0] m
8162 /* 20599 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8163 /* 20602 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8164 /* 20607 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8194:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8165 /* 20607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_D),
8166 /* 20610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8167 /* 20612 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8168 /* 20614 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8169 /* 20616 */ GIR_RootConstrainSelectedInstOperands,
8170 /* 20617 */ // GIR_Coverage, 988,
8171 /* 20617 */ GIR_EraseRootFromParent_Done,
8172 /* 20618 */ // Label 659: @20618
8173 /* 20618 */ GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(20664), // Rule ID 1001 //
8174 /* 20623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8175 /* 20626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_b),
8176 /* 20631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8177 /* 20634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8178 /* 20637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8179 /* 20641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8180 /* 20645 */ // MIs[0] m
8181 /* 20645 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8182 /* 20648 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8183 /* 20653 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8209:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8184 /* 20653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_B),
8185 /* 20656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8186 /* 20658 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8187 /* 20660 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8188 /* 20662 */ GIR_RootConstrainSelectedInstOperands,
8189 /* 20663 */ // GIR_Coverage, 1001,
8190 /* 20663 */ GIR_EraseRootFromParent_Done,
8191 /* 20664 */ // Label 660: @20664
8192 /* 20664 */ GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(20710), // Rule ID 1002 //
8193 /* 20669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8194 /* 20672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_h),
8195 /* 20677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8196 /* 20680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8197 /* 20683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8198 /* 20687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8199 /* 20691 */ // MIs[0] m
8200 /* 20691 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8201 /* 20694 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8202 /* 20699 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8211:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8203 /* 20699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_H),
8204 /* 20702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8205 /* 20704 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8206 /* 20706 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8207 /* 20708 */ GIR_RootConstrainSelectedInstOperands,
8208 /* 20709 */ // GIR_Coverage, 1002,
8209 /* 20709 */ GIR_EraseRootFromParent_Done,
8210 /* 20710 */ // Label 661: @20710
8211 /* 20710 */ GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(20756), // Rule ID 1003 //
8212 /* 20715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8213 /* 20718 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_w),
8214 /* 20723 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8215 /* 20726 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8216 /* 20729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8217 /* 20733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8218 /* 20737 */ // MIs[0] m
8219 /* 20737 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8220 /* 20740 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8221 /* 20745 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8212:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8222 /* 20745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_W),
8223 /* 20748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8224 /* 20750 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8225 /* 20752 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8226 /* 20754 */ GIR_RootConstrainSelectedInstOperands,
8227 /* 20755 */ // GIR_Coverage, 1003,
8228 /* 20755 */ GIR_EraseRootFromParent_Done,
8229 /* 20756 */ // Label 662: @20756
8230 /* 20756 */ GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(20802), // Rule ID 1004 //
8231 /* 20761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8232 /* 20764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_d),
8233 /* 20769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8234 /* 20772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8235 /* 20775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8236 /* 20779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8237 /* 20783 */ // MIs[0] m
8238 /* 20783 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8239 /* 20786 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8240 /* 20791 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8210:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8241 /* 20791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_D),
8242 /* 20794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8243 /* 20796 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8244 /* 20798 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8245 /* 20800 */ GIR_RootConstrainSelectedInstOperands,
8246 /* 20801 */ // GIR_Coverage, 1004,
8247 /* 20801 */ GIR_EraseRootFromParent_Done,
8248 /* 20802 */ // Label 663: @20802
8249 /* 20802 */ GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(20858), // Rule ID 385 //
8250 /* 20807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8251 /* 20810 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8252 /* 20815 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8253 /* 20818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8254 /* 20821 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8255 /* 20824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8256 /* 20828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8257 /* 20832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8258 /* 20836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8259 /* 20840 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8260 /* 20844 */ // MIs[1] Operand 1
8261 /* 20844 */ // No operand predicates
8262 /* 20844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8263 /* 20846 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8152:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8264 /* 20846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH),
8265 /* 20849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8266 /* 20851 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8267 /* 20853 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8268 /* 20856 */ GIR_RootConstrainSelectedInstOperands,
8269 /* 20857 */ // GIR_Coverage, 385,
8270 /* 20857 */ GIR_EraseRootFromParent_Done,
8271 /* 20858 */ // Label 664: @20858
8272 /* 20858 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(20914), // Rule ID 389 //
8273 /* 20863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8274 /* 20866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8275 /* 20871 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8276 /* 20874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8277 /* 20877 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8278 /* 20880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8279 /* 20884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8280 /* 20888 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8281 /* 20892 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8282 /* 20896 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8283 /* 20900 */ // MIs[1] Operand 1
8284 /* 20900 */ // No operand predicates
8285 /* 20900 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8286 /* 20902 */ // (intrinsic_wo_chain:{ *:[i32] } 8154:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8287 /* 20902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W),
8288 /* 20905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8289 /* 20907 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8290 /* 20909 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8291 /* 20912 */ GIR_RootConstrainSelectedInstOperands,
8292 /* 20913 */ // GIR_Coverage, 389,
8293 /* 20913 */ GIR_EraseRootFromParent_Done,
8294 /* 20914 */ // Label 665: @20914
8295 /* 20914 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(20970), // Rule ID 480 //
8296 /* 20919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8297 /* 20922 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8298 /* 20927 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8299 /* 20930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8300 /* 20933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8301 /* 20936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8302 /* 20940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8303 /* 20944 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8304 /* 20948 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8305 /* 20952 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8306 /* 20956 */ // MIs[1] Operand 1
8307 /* 20956 */ // No operand predicates
8308 /* 20956 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8309 /* 20958 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8153:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8310 /* 20958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB),
8311 /* 20961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8312 /* 20963 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8313 /* 20965 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8314 /* 20968 */ GIR_RootConstrainSelectedInstOperands,
8315 /* 20969 */ // GIR_Coverage, 480,
8316 /* 20969 */ GIR_EraseRootFromParent_Done,
8317 /* 20970 */ // Label 666: @20970
8318 /* 20970 */ GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(21026), // Rule ID 1245 //
8319 /* 20975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8320 /* 20978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8321 /* 20983 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8322 /* 20986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8323 /* 20989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8324 /* 20992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8325 /* 20996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8326 /* 21000 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8327 /* 21004 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8328 /* 21008 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8329 /* 21012 */ // MIs[1] Operand 1
8330 /* 21012 */ // No operand predicates
8331 /* 21012 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8332 /* 21014 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8152:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
8333 /* 21014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH_MM),
8334 /* 21017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8335 /* 21019 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8336 /* 21021 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8337 /* 21024 */ GIR_RootConstrainSelectedInstOperands,
8338 /* 21025 */ // GIR_Coverage, 1245,
8339 /* 21025 */ GIR_EraseRootFromParent_Done,
8340 /* 21026 */ // Label 667: @21026
8341 /* 21026 */ GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(21082), // Rule ID 1249 //
8342 /* 21031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8343 /* 21034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8344 /* 21039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8345 /* 21042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8346 /* 21045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8347 /* 21048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8348 /* 21052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8349 /* 21056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8350 /* 21060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8351 /* 21064 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8352 /* 21068 */ // MIs[1] Operand 1
8353 /* 21068 */ // No operand predicates
8354 /* 21068 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8355 /* 21070 */ // (intrinsic_wo_chain:{ *:[i32] } 8154:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
8356 /* 21070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W_MM),
8357 /* 21073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8358 /* 21075 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8359 /* 21077 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8360 /* 21080 */ GIR_RootConstrainSelectedInstOperands,
8361 /* 21081 */ // GIR_Coverage, 1249,
8362 /* 21081 */ GIR_EraseRootFromParent_Done,
8363 /* 21082 */ // Label 668: @21082
8364 /* 21082 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(21138), // Rule ID 1324 //
8365 /* 21087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
8366 /* 21090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8367 /* 21095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8368 /* 21098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8369 /* 21101 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8370 /* 21104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8371 /* 21108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8372 /* 21112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8373 /* 21116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8374 /* 21120 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8375 /* 21124 */ // MIs[1] Operand 1
8376 /* 21124 */ // No operand predicates
8377 /* 21124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8378 /* 21126 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8153:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
8379 /* 21126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
8380 /* 21129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8381 /* 21131 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8382 /* 21133 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8383 /* 21136 */ GIR_RootConstrainSelectedInstOperands,
8384 /* 21137 */ // GIR_Coverage, 1324,
8385 /* 21137 */ GIR_EraseRootFromParent_Done,
8386 /* 21138 */ // Label 669: @21138
8387 /* 21138 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(21190), // Rule ID 1943 //
8388 /* 21143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8389 /* 21146 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
8390 /* 21151 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8391 /* 21154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8392 /* 21157 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8393 /* 21160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8394 /* 21164 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8395 /* 21168 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8396 /* 21172 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8397 /* 21176 */ // MIs[1] Operand 1
8398 /* 21176 */ // No operand predicates
8399 /* 21176 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8400 /* 21178 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8150:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
8401 /* 21178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_PH),
8402 /* 21181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8403 /* 21183 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8404 /* 21185 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8405 /* 21188 */ GIR_RootConstrainSelectedInstOperands,
8406 /* 21189 */ // GIR_Coverage, 1943,
8407 /* 21189 */ GIR_EraseRootFromParent_Done,
8408 /* 21190 */ // Label 670: @21190
8409 /* 21190 */ GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(21242), // Rule ID 1944 //
8410 /* 21195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8411 /* 21198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
8412 /* 21203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8413 /* 21206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8414 /* 21209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8415 /* 21212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8416 /* 21216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8417 /* 21220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8418 /* 21224 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8419 /* 21228 */ // MIs[1] Operand 1
8420 /* 21228 */ // No operand predicates
8421 /* 21228 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8422 /* 21230 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8155:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
8423 /* 21230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_PH),
8424 /* 21233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8425 /* 21235 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8426 /* 21237 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8427 /* 21240 */ GIR_RootConstrainSelectedInstOperands,
8428 /* 21241 */ // GIR_Coverage, 1944,
8429 /* 21241 */ GIR_EraseRootFromParent_Done,
8430 /* 21242 */ // Label 671: @21242
8431 /* 21242 */ GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(21294), // Rule ID 1949 //
8432 /* 21247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8433 /* 21250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
8434 /* 21255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8435 /* 21258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8436 /* 21261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8437 /* 21264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8438 /* 21268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8439 /* 21272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8440 /* 21276 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8441 /* 21280 */ // MIs[1] Operand 1
8442 /* 21280 */ // No operand predicates
8443 /* 21280 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8444 /* 21282 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8151:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
8445 /* 21282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_QB),
8446 /* 21285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8447 /* 21287 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8448 /* 21289 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8449 /* 21292 */ GIR_RootConstrainSelectedInstOperands,
8450 /* 21293 */ // GIR_Coverage, 1949,
8451 /* 21293 */ GIR_EraseRootFromParent_Done,
8452 /* 21294 */ // Label 672: @21294
8453 /* 21294 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(21346), // Rule ID 1950 //
8454 /* 21299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8455 /* 21302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
8456 /* 21307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8457 /* 21310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8458 /* 21313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8459 /* 21316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8460 /* 21320 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8461 /* 21324 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8462 /* 21328 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8463 /* 21332 */ // MIs[1] Operand 1
8464 /* 21332 */ // No operand predicates
8465 /* 21332 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8466 /* 21334 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8156:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
8467 /* 21334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_QB),
8468 /* 21337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8469 /* 21339 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8470 /* 21341 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8471 /* 21344 */ GIR_RootConstrainSelectedInstOperands,
8472 /* 21345 */ // GIR_Coverage, 1950,
8473 /* 21345 */ GIR_EraseRootFromParent_Done,
8474 /* 21346 */ // Label 673: @21346
8475 /* 21346 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(21394), // Rule ID 355 //
8476 /* 21351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8477 /* 21354 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
8478 /* 21359 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8479 /* 21362 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8480 /* 21365 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8481 /* 21368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8482 /* 21372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8483 /* 21376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8484 /* 21380 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7622:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8485 /* 21380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB),
8486 /* 21383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8487 /* 21385 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8488 /* 21387 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8489 /* 21389 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8490 /* 21392 */ GIR_RootConstrainSelectedInstOperands,
8491 /* 21393 */ // GIR_Coverage, 355,
8492 /* 21393 */ GIR_EraseRootFromParent_Done,
8493 /* 21394 */ // Label 674: @21394
8494 /* 21394 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(21442), // Rule ID 356 //
8495 /* 21399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8496 /* 21402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
8497 /* 21407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8498 /* 21410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8499 /* 21413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8500 /* 21416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8501 /* 21420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8502 /* 21424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8503 /* 21428 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8245:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8504 /* 21428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB),
8505 /* 21431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8506 /* 21433 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8507 /* 21435 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8508 /* 21437 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8509 /* 21440 */ GIR_RootConstrainSelectedInstOperands,
8510 /* 21441 */ // GIR_Coverage, 356,
8511 /* 21441 */ GIR_EraseRootFromParent_Done,
8512 /* 21442 */ // Label 675: @21442
8513 /* 21442 */ GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(21490), // Rule ID 357 //
8514 /* 21447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8515 /* 21450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
8516 /* 21455 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8517 /* 21458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8518 /* 21461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8519 /* 21464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8520 /* 21468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8521 /* 21472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8522 /* 21476 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7600:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8523 /* 21476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH),
8524 /* 21479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8525 /* 21481 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8526 /* 21483 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8527 /* 21485 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8528 /* 21488 */ GIR_RootConstrainSelectedInstOperands,
8529 /* 21489 */ // GIR_Coverage, 357,
8530 /* 21489 */ GIR_EraseRootFromParent_Done,
8531 /* 21490 */ // Label 676: @21490
8532 /* 21490 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(21538), // Rule ID 358 //
8533 /* 21495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8534 /* 21498 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
8535 /* 21503 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8536 /* 21506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8537 /* 21509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8538 /* 21512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8539 /* 21516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8540 /* 21520 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8541 /* 21524 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8220:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8542 /* 21524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH),
8543 /* 21527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8544 /* 21529 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8545 /* 21531 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8546 /* 21533 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8547 /* 21536 */ GIR_RootConstrainSelectedInstOperands,
8548 /* 21537 */ // GIR_Coverage, 358,
8549 /* 21537 */ GIR_EraseRootFromParent_Done,
8550 /* 21538 */ // Label 677: @21538
8551 /* 21538 */ GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(21583), // Rule ID 361 //
8552 /* 21543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8553 /* 21546 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
8554 /* 21551 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8555 /* 21554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8556 /* 21557 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8557 /* 21560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8558 /* 21564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8559 /* 21568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8560 /* 21572 */ // (intrinsic_wo_chain:{ *:[i32] } 8050:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8561 /* 21572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB),
8562 /* 21575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8563 /* 21577 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8564 /* 21579 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8565 /* 21581 */ GIR_RootConstrainSelectedInstOperands,
8566 /* 21582 */ // GIR_Coverage, 361,
8567 /* 21582 */ GIR_EraseRootFromParent_Done,
8568 /* 21583 */ // Label 678: @21583
8569 /* 21583 */ GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(21628), // Rule ID 365 //
8570 /* 21588 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8571 /* 21591 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
8572 /* 21596 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8573 /* 21599 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8574 /* 21602 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8575 /* 21605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8576 /* 21609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8577 /* 21613 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8578 /* 21617 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8126:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8579 /* 21617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH),
8580 /* 21620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8581 /* 21622 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8582 /* 21624 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8583 /* 21626 */ GIR_RootConstrainSelectedInstOperands,
8584 /* 21627 */ // GIR_Coverage, 365,
8585 /* 21627 */ GIR_EraseRootFromParent_Done,
8586 /* 21628 */ // Label 679: @21628
8587 /* 21628 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(21673), // Rule ID 366 //
8588 /* 21633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8589 /* 21636 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
8590 /* 21641 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8591 /* 21644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8592 /* 21647 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8593 /* 21650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8594 /* 21654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8595 /* 21658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8596 /* 21662 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8125:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8597 /* 21662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W),
8598 /* 21665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8599 /* 21667 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8600 /* 21669 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8601 /* 21671 */ GIR_RootConstrainSelectedInstOperands,
8602 /* 21672 */ // GIR_Coverage, 366,
8603 /* 21672 */ GIR_EraseRootFromParent_Done,
8604 /* 21673 */ // Label 680: @21673
8605 /* 21673 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(21718), // Rule ID 380 //
8606 /* 21678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8607 /* 21681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
8608 /* 21686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8609 /* 21689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8610 /* 21692 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8611 /* 21695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8612 /* 21699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8613 /* 21703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8614 /* 21707 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8156:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8615 /* 21707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB),
8616 /* 21710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8617 /* 21712 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8618 /* 21714 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8619 /* 21716 */ GIR_RootConstrainSelectedInstOperands,
8620 /* 21717 */ // GIR_Coverage, 380,
8621 /* 21717 */ GIR_EraseRootFromParent_Done,
8622 /* 21718 */ // Label 681: @21718
8623 /* 21718 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(21763), // Rule ID 384 //
8624 /* 21723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8625 /* 21726 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
8626 /* 21731 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8627 /* 21734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8628 /* 21737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8629 /* 21740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8630 /* 21744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8631 /* 21748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8632 /* 21752 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8150:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8633 /* 21752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH),
8634 /* 21755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8635 /* 21757 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8636 /* 21759 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8637 /* 21761 */ GIR_RootConstrainSelectedInstOperands,
8638 /* 21762 */ // GIR_Coverage, 384,
8639 /* 21762 */ GIR_EraseRootFromParent_Done,
8640 /* 21763 */ // Label 682: @21763
8641 /* 21763 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(21808), // Rule ID 386 //
8642 /* 21768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8643 /* 21771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8644 /* 21776 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8645 /* 21779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8646 /* 21782 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8647 /* 21785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8648 /* 21789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8649 /* 21793 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8650 /* 21797 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8152:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8651 /* 21797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH),
8652 /* 21800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8653 /* 21802 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8654 /* 21804 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8655 /* 21806 */ GIR_RootConstrainSelectedInstOperands,
8656 /* 21807 */ // GIR_Coverage, 386,
8657 /* 21807 */ GIR_EraseRootFromParent_Done,
8658 /* 21808 */ // Label 683: @21808
8659 /* 21808 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(21853), // Rule ID 390 //
8660 /* 21813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8661 /* 21816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8662 /* 21821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8663 /* 21824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8664 /* 21827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8665 /* 21830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8666 /* 21834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8667 /* 21838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8668 /* 21842 */ // (intrinsic_wo_chain:{ *:[i32] } 8154:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8669 /* 21842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W),
8670 /* 21845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8671 /* 21847 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8672 /* 21849 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8673 /* 21851 */ GIR_RootConstrainSelectedInstOperands,
8674 /* 21852 */ // GIR_Coverage, 390,
8675 /* 21852 */ GIR_EraseRootFromParent_Done,
8676 /* 21853 */ // Label 684: @21853
8677 /* 21853 */ GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(21898), // Rule ID 427 //
8678 /* 21858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8679 /* 21861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
8680 /* 21866 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8681 /* 21869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8682 /* 21872 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8683 /* 21875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8684 /* 21879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8685 /* 21883 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8686 /* 21887 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8097:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8687 /* 21887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH),
8688 /* 21890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8689 /* 21892 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8690 /* 21894 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8691 /* 21896 */ GIR_RootConstrainSelectedInstOperands,
8692 /* 21897 */ // GIR_Coverage, 427,
8693 /* 21897 */ GIR_EraseRootFromParent_Done,
8694 /* 21898 */ // Label 685: @21898
8695 /* 21898 */ GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(21943), // Rule ID 451 //
8696 /* 21903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8697 /* 21906 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
8698 /* 21911 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8699 /* 21914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8700 /* 21917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8701 /* 21920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8702 /* 21924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8703 /* 21928 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8704 /* 21932 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7623:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8705 /* 21932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB),
8706 /* 21935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8707 /* 21937 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8708 /* 21939 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8709 /* 21941 */ GIR_RootConstrainSelectedInstOperands,
8710 /* 21942 */ // GIR_Coverage, 451,
8711 /* 21942 */ GIR_EraseRootFromParent_Done,
8712 /* 21943 */ // Label 686: @21943
8713 /* 21943 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(21988), // Rule ID 452 //
8714 /* 21948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8715 /* 21951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
8716 /* 21956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8717 /* 21959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8718 /* 21962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8719 /* 21965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8720 /* 21969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8721 /* 21973 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8722 /* 21977 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7624:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8723 /* 21977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB),
8724 /* 21980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8725 /* 21982 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8726 /* 21984 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8727 /* 21986 */ GIR_RootConstrainSelectedInstOperands,
8728 /* 21987 */ // GIR_Coverage, 452,
8729 /* 21987 */ GIR_EraseRootFromParent_Done,
8730 /* 21988 */ // Label 687: @21988
8731 /* 21988 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(22033), // Rule ID 453 //
8732 /* 21993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8733 /* 21996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
8734 /* 22001 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8735 /* 22004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8736 /* 22007 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8737 /* 22010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8738 /* 22014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8739 /* 22018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8740 /* 22022 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8246:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8741 /* 22022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB),
8742 /* 22025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8743 /* 22027 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8744 /* 22029 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8745 /* 22031 */ GIR_RootConstrainSelectedInstOperands,
8746 /* 22032 */ // GIR_Coverage, 453,
8747 /* 22032 */ GIR_EraseRootFromParent_Done,
8748 /* 22033 */ // Label 688: @22033
8749 /* 22033 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(22078), // Rule ID 454 //
8750 /* 22038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8751 /* 22041 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
8752 /* 22046 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8753 /* 22049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8754 /* 22052 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8755 /* 22055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8756 /* 22059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8757 /* 22063 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8758 /* 22067 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8247:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8759 /* 22067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB),
8760 /* 22070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8761 /* 22072 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8762 /* 22074 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8763 /* 22076 */ GIR_RootConstrainSelectedInstOperands,
8764 /* 22077 */ // GIR_Coverage, 454,
8765 /* 22077 */ GIR_EraseRootFromParent_Done,
8766 /* 22078 */ // Label 689: @22078
8767 /* 22078 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(22123), // Rule ID 455 //
8768 /* 22083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8769 /* 22086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
8770 /* 22091 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8771 /* 22094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8772 /* 22097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8773 /* 22100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8774 /* 22104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8775 /* 22108 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8776 /* 22112 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7602:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8777 /* 22112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH),
8778 /* 22115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8779 /* 22117 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8780 /* 22119 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8781 /* 22121 */ GIR_RootConstrainSelectedInstOperands,
8782 /* 22122 */ // GIR_Coverage, 455,
8783 /* 22122 */ GIR_EraseRootFromParent_Done,
8784 /* 22123 */ // Label 690: @22123
8785 /* 22123 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(22168), // Rule ID 456 //
8786 /* 22128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8787 /* 22131 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
8788 /* 22136 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8789 /* 22139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8790 /* 22142 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8791 /* 22145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8792 /* 22149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8793 /* 22153 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8794 /* 22157 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7603:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8795 /* 22157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH),
8796 /* 22160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8797 /* 22162 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8798 /* 22164 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8799 /* 22166 */ GIR_RootConstrainSelectedInstOperands,
8800 /* 22167 */ // GIR_Coverage, 456,
8801 /* 22167 */ GIR_EraseRootFromParent_Done,
8802 /* 22168 */ // Label 691: @22168
8803 /* 22168 */ GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(22213), // Rule ID 457 //
8804 /* 22173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8805 /* 22176 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
8806 /* 22181 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8807 /* 22184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8808 /* 22187 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8809 /* 22190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8810 /* 22194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8811 /* 22198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8812 /* 22202 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8222:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8813 /* 22202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH),
8814 /* 22205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8815 /* 22207 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8816 /* 22209 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8817 /* 22211 */ GIR_RootConstrainSelectedInstOperands,
8818 /* 22212 */ // GIR_Coverage, 457,
8819 /* 22212 */ GIR_EraseRootFromParent_Done,
8820 /* 22213 */ // Label 692: @22213
8821 /* 22213 */ GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(22258), // Rule ID 458 //
8822 /* 22218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8823 /* 22221 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
8824 /* 22226 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8825 /* 22229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8826 /* 22232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8827 /* 22235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8828 /* 22239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8829 /* 22243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8830 /* 22247 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8223:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8831 /* 22247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH),
8832 /* 22250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8833 /* 22252 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8834 /* 22254 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8835 /* 22256 */ GIR_RootConstrainSelectedInstOperands,
8836 /* 22257 */ // GIR_Coverage, 458,
8837 /* 22257 */ GIR_EraseRootFromParent_Done,
8838 /* 22258 */ // Label 693: @22258
8839 /* 22258 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(22303), // Rule ID 459 //
8840 /* 22263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8841 /* 22266 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
8842 /* 22271 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8843 /* 22274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8844 /* 22277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8845 /* 22280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8846 /* 22284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8847 /* 22288 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8848 /* 22292 */ // (intrinsic_wo_chain:{ *:[i32] } 7605:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8849 /* 22292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W),
8850 /* 22295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8851 /* 22297 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8852 /* 22299 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8853 /* 22301 */ GIR_RootConstrainSelectedInstOperands,
8854 /* 22302 */ // GIR_Coverage, 459,
8855 /* 22302 */ GIR_EraseRootFromParent_Done,
8856 /* 22303 */ // Label 694: @22303
8857 /* 22303 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(22348), // Rule ID 460 //
8858 /* 22308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8859 /* 22311 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
8860 /* 22316 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8861 /* 22319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8862 /* 22322 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8863 /* 22325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8864 /* 22329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8865 /* 22333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8866 /* 22337 */ // (intrinsic_wo_chain:{ *:[i32] } 7604:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8867 /* 22337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W),
8868 /* 22340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8869 /* 22342 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8870 /* 22344 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8871 /* 22346 */ GIR_RootConstrainSelectedInstOperands,
8872 /* 22347 */ // GIR_Coverage, 460,
8873 /* 22347 */ GIR_EraseRootFromParent_Done,
8874 /* 22348 */ // Label 695: @22348
8875 /* 22348 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(22393), // Rule ID 461 //
8876 /* 22353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8877 /* 22356 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
8878 /* 22361 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8879 /* 22364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8880 /* 22367 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8881 /* 22370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8882 /* 22374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8883 /* 22378 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8884 /* 22382 */ // (intrinsic_wo_chain:{ *:[i32] } 8225:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8885 /* 22382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W),
8886 /* 22385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8887 /* 22387 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8888 /* 22389 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8889 /* 22391 */ GIR_RootConstrainSelectedInstOperands,
8890 /* 22392 */ // GIR_Coverage, 461,
8891 /* 22392 */ GIR_EraseRootFromParent_Done,
8892 /* 22393 */ // Label 696: @22393
8893 /* 22393 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(22438), // Rule ID 462 //
8894 /* 22398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8895 /* 22401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
8896 /* 22406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8897 /* 22409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8898 /* 22412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8899 /* 22415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8900 /* 22419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8901 /* 22423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8902 /* 22427 */ // (intrinsic_wo_chain:{ *:[i32] } 8224:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8903 /* 22427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W),
8904 /* 22430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8905 /* 22432 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8906 /* 22434 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8907 /* 22436 */ GIR_RootConstrainSelectedInstOperands,
8908 /* 22437 */ // GIR_Coverage, 462,
8909 /* 22437 */ GIR_EraseRootFromParent_Done,
8910 /* 22438 */ // Label 697: @22438
8911 /* 22438 */ GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(22483), // Rule ID 479 //
8912 /* 22443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8913 /* 22446 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
8914 /* 22451 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8915 /* 22454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8916 /* 22457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8917 /* 22460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8918 /* 22464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8919 /* 22468 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8920 /* 22472 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8151:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8921 /* 22472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB),
8922 /* 22475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8923 /* 22477 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8924 /* 22479 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8925 /* 22481 */ GIR_RootConstrainSelectedInstOperands,
8926 /* 22482 */ // GIR_Coverage, 479,
8927 /* 22482 */ GIR_EraseRootFromParent_Done,
8928 /* 22483 */ // Label 698: @22483
8929 /* 22483 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(22528), // Rule ID 481 //
8930 /* 22488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8931 /* 22491 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8932 /* 22496 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8933 /* 22499 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8934 /* 22502 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8935 /* 22505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8936 /* 22509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8937 /* 22513 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8938 /* 22517 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8153:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8939 /* 22517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB),
8940 /* 22520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8941 /* 22522 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8942 /* 22524 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8943 /* 22526 */ GIR_RootConstrainSelectedInstOperands,
8944 /* 22527 */ // GIR_Coverage, 481,
8945 /* 22527 */ GIR_EraseRootFromParent_Done,
8946 /* 22528 */ // Label 699: @22528
8947 /* 22528 */ GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(22573), // Rule ID 482 //
8948 /* 22533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8949 /* 22536 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
8950 /* 22541 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8951 /* 22544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8952 /* 22547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8953 /* 22550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8954 /* 22554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8955 /* 22558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8956 /* 22562 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8155:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8957 /* 22562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH),
8958 /* 22565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8959 /* 22567 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8960 /* 22569 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8961 /* 22571 */ GIR_RootConstrainSelectedInstOperands,
8962 /* 22572 */ // GIR_Coverage, 482,
8963 /* 22572 */ GIR_EraseRootFromParent_Done,
8964 /* 22573 */ // Label 700: @22573
8965 /* 22573 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(22618), // Rule ID 491 //
8966 /* 22578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8967 /* 22581 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_b),
8968 /* 22586 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8969 /* 22589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8970 /* 22592 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8971 /* 22595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8972 /* 22599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8973 /* 22603 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8974 /* 22607 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7595:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8975 /* 22607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_B),
8976 /* 22610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8977 /* 22612 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8978 /* 22614 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
8979 /* 22616 */ GIR_RootConstrainSelectedInstOperands,
8980 /* 22617 */ // GIR_Coverage, 491,
8981 /* 22617 */ GIR_EraseRootFromParent_Done,
8982 /* 22618 */ // Label 701: @22618
8983 /* 22618 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(22663), // Rule ID 492 //
8984 /* 22623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8985 /* 22626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_h),
8986 /* 22631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8987 /* 22634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8988 /* 22637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8989 /* 22640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8990 /* 22644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8991 /* 22648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8992 /* 22652 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7597:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8993 /* 22652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_H),
8994 /* 22655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8995 /* 22657 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8996 /* 22659 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
8997 /* 22661 */ GIR_RootConstrainSelectedInstOperands,
8998 /* 22662 */ // GIR_Coverage, 492,
8999 /* 22662 */ GIR_EraseRootFromParent_Done,
9000 /* 22663 */ // Label 702: @22663
9001 /* 22663 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(22708), // Rule ID 493 //
9002 /* 22668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9003 /* 22671 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_w),
9004 /* 22676 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9005 /* 22679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9006 /* 22682 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9007 /* 22685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9008 /* 22689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9009 /* 22693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9010 /* 22697 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7598:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9011 /* 22697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_W),
9012 /* 22700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9013 /* 22702 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9014 /* 22704 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9015 /* 22706 */ GIR_RootConstrainSelectedInstOperands,
9016 /* 22707 */ // GIR_Coverage, 493,
9017 /* 22707 */ GIR_EraseRootFromParent_Done,
9018 /* 22708 */ // Label 703: @22708
9019 /* 22708 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(22753), // Rule ID 494 //
9020 /* 22713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9021 /* 22716 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_d),
9022 /* 22721 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9023 /* 22724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9024 /* 22727 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9025 /* 22730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9026 /* 22734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9027 /* 22738 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9028 /* 22742 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7596:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9029 /* 22742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_D),
9030 /* 22745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9031 /* 22747 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9032 /* 22749 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9033 /* 22751 */ GIR_RootConstrainSelectedInstOperands,
9034 /* 22752 */ // GIR_Coverage, 494,
9035 /* 22752 */ GIR_EraseRootFromParent_Done,
9036 /* 22753 */ // Label 704: @22753
9037 /* 22753 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(22798), // Rule ID 495 //
9038 /* 22758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9039 /* 22761 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
9040 /* 22766 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9041 /* 22769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9042 /* 22772 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9043 /* 22775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9044 /* 22779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9045 /* 22783 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9046 /* 22787 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7606:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9047 /* 22787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_B),
9048 /* 22790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9049 /* 22792 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9050 /* 22794 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9051 /* 22796 */ GIR_RootConstrainSelectedInstOperands,
9052 /* 22797 */ // GIR_Coverage, 495,
9053 /* 22797 */ GIR_EraseRootFromParent_Done,
9054 /* 22798 */ // Label 705: @22798
9055 /* 22798 */ GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(22843), // Rule ID 496 //
9056 /* 22803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9057 /* 22806 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
9058 /* 22811 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9059 /* 22814 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9060 /* 22817 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9061 /* 22820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9062 /* 22824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9063 /* 22828 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9064 /* 22832 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7608:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9065 /* 22832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_H),
9066 /* 22835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9067 /* 22837 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9068 /* 22839 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9069 /* 22841 */ GIR_RootConstrainSelectedInstOperands,
9070 /* 22842 */ // GIR_Coverage, 496,
9071 /* 22842 */ GIR_EraseRootFromParent_Done,
9072 /* 22843 */ // Label 706: @22843
9073 /* 22843 */ GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(22888), // Rule ID 497 //
9074 /* 22848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9075 /* 22851 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
9076 /* 22856 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9077 /* 22859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9078 /* 22862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9079 /* 22865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9080 /* 22869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9081 /* 22873 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9082 /* 22877 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7609:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9083 /* 22877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_W),
9084 /* 22880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9085 /* 22882 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9086 /* 22884 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9087 /* 22886 */ GIR_RootConstrainSelectedInstOperands,
9088 /* 22887 */ // GIR_Coverage, 497,
9089 /* 22887 */ GIR_EraseRootFromParent_Done,
9090 /* 22888 */ // Label 707: @22888
9091 /* 22888 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(22933), // Rule ID 498 //
9092 /* 22893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9093 /* 22896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
9094 /* 22901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9095 /* 22904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9096 /* 22907 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9097 /* 22910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9098 /* 22914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9099 /* 22918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9100 /* 22922 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7607:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9101 /* 22922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_D),
9102 /* 22925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9103 /* 22927 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9104 /* 22929 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9105 /* 22931 */ GIR_RootConstrainSelectedInstOperands,
9106 /* 22932 */ // GIR_Coverage, 498,
9107 /* 22932 */ GIR_EraseRootFromParent_Done,
9108 /* 22933 */ // Label 708: @22933
9109 /* 22933 */ GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(22978), // Rule ID 499 //
9110 /* 22938 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9111 /* 22941 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
9112 /* 22946 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9113 /* 22949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9114 /* 22952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9115 /* 22955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9116 /* 22959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9117 /* 22963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9118 /* 22967 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7610:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9119 /* 22967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_B),
9120 /* 22970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9121 /* 22972 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9122 /* 22974 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9123 /* 22976 */ GIR_RootConstrainSelectedInstOperands,
9124 /* 22977 */ // GIR_Coverage, 499,
9125 /* 22977 */ GIR_EraseRootFromParent_Done,
9126 /* 22978 */ // Label 709: @22978
9127 /* 22978 */ GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(23023), // Rule ID 500 //
9128 /* 22983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9129 /* 22986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
9130 /* 22991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9131 /* 22994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9132 /* 22997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9133 /* 23000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9134 /* 23004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9135 /* 23008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9136 /* 23012 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7612:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9137 /* 23012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_H),
9138 /* 23015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9139 /* 23017 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9140 /* 23019 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9141 /* 23021 */ GIR_RootConstrainSelectedInstOperands,
9142 /* 23022 */ // GIR_Coverage, 500,
9143 /* 23022 */ GIR_EraseRootFromParent_Done,
9144 /* 23023 */ // Label 710: @23023
9145 /* 23023 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(23068), // Rule ID 501 //
9146 /* 23028 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9147 /* 23031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
9148 /* 23036 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9149 /* 23039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9150 /* 23042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9151 /* 23045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9152 /* 23049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9153 /* 23053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9154 /* 23057 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7613:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9155 /* 23057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_W),
9156 /* 23060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9157 /* 23062 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9158 /* 23064 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9159 /* 23066 */ GIR_RootConstrainSelectedInstOperands,
9160 /* 23067 */ // GIR_Coverage, 501,
9161 /* 23067 */ GIR_EraseRootFromParent_Done,
9162 /* 23068 */ // Label 711: @23068
9163 /* 23068 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(23113), // Rule ID 502 //
9164 /* 23073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9165 /* 23076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
9166 /* 23081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9167 /* 23084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9168 /* 23087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9169 /* 23090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9170 /* 23094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9171 /* 23098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9172 /* 23102 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7611:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9173 /* 23102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_D),
9174 /* 23105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9175 /* 23107 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9176 /* 23109 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9177 /* 23111 */ GIR_RootConstrainSelectedInstOperands,
9178 /* 23112 */ // GIR_Coverage, 502,
9179 /* 23112 */ GIR_EraseRootFromParent_Done,
9180 /* 23113 */ // Label 712: @23113
9181 /* 23113 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(23158), // Rule ID 503 //
9182 /* 23118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9183 /* 23121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
9184 /* 23126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9185 /* 23129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9186 /* 23132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9187 /* 23135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9188 /* 23139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9189 /* 23143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9190 /* 23147 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7614:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9191 /* 23147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_B),
9192 /* 23150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9193 /* 23152 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9194 /* 23154 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9195 /* 23156 */ GIR_RootConstrainSelectedInstOperands,
9196 /* 23157 */ // GIR_Coverage, 503,
9197 /* 23157 */ GIR_EraseRootFromParent_Done,
9198 /* 23158 */ // Label 713: @23158
9199 /* 23158 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(23203), // Rule ID 504 //
9200 /* 23163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9201 /* 23166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
9202 /* 23171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9203 /* 23174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9204 /* 23177 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9205 /* 23180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9206 /* 23184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9207 /* 23188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9208 /* 23192 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7616:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9209 /* 23192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_H),
9210 /* 23195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9211 /* 23197 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9212 /* 23199 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9213 /* 23201 */ GIR_RootConstrainSelectedInstOperands,
9214 /* 23202 */ // GIR_Coverage, 504,
9215 /* 23202 */ GIR_EraseRootFromParent_Done,
9216 /* 23203 */ // Label 714: @23203
9217 /* 23203 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(23248), // Rule ID 505 //
9218 /* 23208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9219 /* 23211 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
9220 /* 23216 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9221 /* 23219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9222 /* 23222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9223 /* 23225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9224 /* 23229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9225 /* 23233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9226 /* 23237 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7617:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9227 /* 23237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_W),
9228 /* 23240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9229 /* 23242 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9230 /* 23244 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9231 /* 23246 */ GIR_RootConstrainSelectedInstOperands,
9232 /* 23247 */ // GIR_Coverage, 505,
9233 /* 23247 */ GIR_EraseRootFromParent_Done,
9234 /* 23248 */ // Label 715: @23248
9235 /* 23248 */ GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(23293), // Rule ID 506 //
9236 /* 23253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9237 /* 23256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
9238 /* 23261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9239 /* 23264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9240 /* 23267 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9241 /* 23270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9242 /* 23274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9243 /* 23278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9244 /* 23282 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7615:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9245 /* 23282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_D),
9246 /* 23285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9247 /* 23287 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9248 /* 23289 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9249 /* 23291 */ GIR_RootConstrainSelectedInstOperands,
9250 /* 23292 */ // GIR_Coverage, 506,
9251 /* 23292 */ GIR_EraseRootFromParent_Done,
9252 /* 23293 */ // Label 716: @23293
9253 /* 23293 */ GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(23338), // Rule ID 520 //
9254 /* 23298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9255 /* 23301 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
9256 /* 23306 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9257 /* 23309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9258 /* 23312 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9259 /* 23315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9260 /* 23319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9261 /* 23323 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9262 /* 23327 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7637:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9263 /* 23327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_B),
9264 /* 23330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9265 /* 23332 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9266 /* 23334 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9267 /* 23336 */ GIR_RootConstrainSelectedInstOperands,
9268 /* 23337 */ // GIR_Coverage, 520,
9269 /* 23337 */ GIR_EraseRootFromParent_Done,
9270 /* 23338 */ // Label 717: @23338
9271 /* 23338 */ GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(23383), // Rule ID 521 //
9272 /* 23343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9273 /* 23346 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
9274 /* 23351 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9275 /* 23354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9276 /* 23357 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9277 /* 23360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9278 /* 23364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9279 /* 23368 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9280 /* 23372 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7639:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9281 /* 23372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_H),
9282 /* 23375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9283 /* 23377 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9284 /* 23379 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9285 /* 23381 */ GIR_RootConstrainSelectedInstOperands,
9286 /* 23382 */ // GIR_Coverage, 521,
9287 /* 23382 */ GIR_EraseRootFromParent_Done,
9288 /* 23383 */ // Label 718: @23383
9289 /* 23383 */ GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(23428), // Rule ID 522 //
9290 /* 23388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9291 /* 23391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
9292 /* 23396 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9293 /* 23399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9294 /* 23402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9295 /* 23405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9296 /* 23409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9297 /* 23413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9298 /* 23417 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7640:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9299 /* 23417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_W),
9300 /* 23420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9301 /* 23422 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9302 /* 23424 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9303 /* 23426 */ GIR_RootConstrainSelectedInstOperands,
9304 /* 23427 */ // GIR_Coverage, 522,
9305 /* 23427 */ GIR_EraseRootFromParent_Done,
9306 /* 23428 */ // Label 719: @23428
9307 /* 23428 */ GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(23473), // Rule ID 523 //
9308 /* 23433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9309 /* 23436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
9310 /* 23441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9311 /* 23444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9312 /* 23447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9313 /* 23450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9314 /* 23454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9315 /* 23458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9316 /* 23462 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7638:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9317 /* 23462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_D),
9318 /* 23465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9319 /* 23467 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9320 /* 23469 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9321 /* 23471 */ GIR_RootConstrainSelectedInstOperands,
9322 /* 23472 */ // GIR_Coverage, 523,
9323 /* 23472 */ GIR_EraseRootFromParent_Done,
9324 /* 23473 */ // Label 720: @23473
9325 /* 23473 */ GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(23518), // Rule ID 524 //
9326 /* 23478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9327 /* 23481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
9328 /* 23486 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9329 /* 23489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9330 /* 23492 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9331 /* 23495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9332 /* 23499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9333 /* 23503 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9334 /* 23507 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7641:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9335 /* 23507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_B),
9336 /* 23510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9337 /* 23512 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9338 /* 23514 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9339 /* 23516 */ GIR_RootConstrainSelectedInstOperands,
9340 /* 23517 */ // GIR_Coverage, 524,
9341 /* 23517 */ GIR_EraseRootFromParent_Done,
9342 /* 23518 */ // Label 721: @23518
9343 /* 23518 */ GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(23563), // Rule ID 525 //
9344 /* 23523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9345 /* 23526 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
9346 /* 23531 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9347 /* 23534 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9348 /* 23537 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9349 /* 23540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9350 /* 23544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9351 /* 23548 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9352 /* 23552 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7643:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9353 /* 23552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_H),
9354 /* 23555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9355 /* 23557 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9356 /* 23559 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9357 /* 23561 */ GIR_RootConstrainSelectedInstOperands,
9358 /* 23562 */ // GIR_Coverage, 525,
9359 /* 23562 */ GIR_EraseRootFromParent_Done,
9360 /* 23563 */ // Label 722: @23563
9361 /* 23563 */ GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(23608), // Rule ID 526 //
9362 /* 23568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9363 /* 23571 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
9364 /* 23576 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9365 /* 23579 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9366 /* 23582 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9367 /* 23585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9368 /* 23589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9369 /* 23593 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9370 /* 23597 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7644:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9371 /* 23597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_W),
9372 /* 23600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9373 /* 23602 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9374 /* 23604 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9375 /* 23606 */ GIR_RootConstrainSelectedInstOperands,
9376 /* 23607 */ // GIR_Coverage, 526,
9377 /* 23607 */ GIR_EraseRootFromParent_Done,
9378 /* 23608 */ // Label 723: @23608
9379 /* 23608 */ GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(23653), // Rule ID 527 //
9380 /* 23613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9381 /* 23616 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
9382 /* 23621 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9383 /* 23624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9384 /* 23627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9385 /* 23630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9386 /* 23634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9387 /* 23638 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9388 /* 23642 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7642:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9389 /* 23642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_D),
9390 /* 23645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9391 /* 23647 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9392 /* 23649 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9393 /* 23651 */ GIR_RootConstrainSelectedInstOperands,
9394 /* 23652 */ // GIR_Coverage, 527,
9395 /* 23652 */ GIR_EraseRootFromParent_Done,
9396 /* 23653 */ // Label 724: @23653
9397 /* 23653 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(23698), // Rule ID 528 //
9398 /* 23658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9399 /* 23661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
9400 /* 23666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9401 /* 23669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9402 /* 23672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9403 /* 23675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9404 /* 23679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9405 /* 23683 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9406 /* 23687 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7645:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9407 /* 23687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_B),
9408 /* 23690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9409 /* 23692 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9410 /* 23694 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9411 /* 23696 */ GIR_RootConstrainSelectedInstOperands,
9412 /* 23697 */ // GIR_Coverage, 528,
9413 /* 23697 */ GIR_EraseRootFromParent_Done,
9414 /* 23698 */ // Label 725: @23698
9415 /* 23698 */ GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(23743), // Rule ID 529 //
9416 /* 23703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9417 /* 23706 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
9418 /* 23711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9419 /* 23714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9420 /* 23717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9421 /* 23720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9422 /* 23724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9423 /* 23728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9424 /* 23732 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7647:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9425 /* 23732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_H),
9426 /* 23735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9427 /* 23737 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9428 /* 23739 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9429 /* 23741 */ GIR_RootConstrainSelectedInstOperands,
9430 /* 23742 */ // GIR_Coverage, 529,
9431 /* 23742 */ GIR_EraseRootFromParent_Done,
9432 /* 23743 */ // Label 726: @23743
9433 /* 23743 */ GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(23788), // Rule ID 530 //
9434 /* 23748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9435 /* 23751 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
9436 /* 23756 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9437 /* 23759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9438 /* 23762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9439 /* 23765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9440 /* 23769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9441 /* 23773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9442 /* 23777 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7648:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9443 /* 23777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_W),
9444 /* 23780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9445 /* 23782 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9446 /* 23784 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9447 /* 23786 */ GIR_RootConstrainSelectedInstOperands,
9448 /* 23787 */ // GIR_Coverage, 530,
9449 /* 23787 */ GIR_EraseRootFromParent_Done,
9450 /* 23788 */ // Label 727: @23788
9451 /* 23788 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(23833), // Rule ID 531 //
9452 /* 23793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9453 /* 23796 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
9454 /* 23801 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9455 /* 23804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9456 /* 23807 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9457 /* 23810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9458 /* 23814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9459 /* 23818 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9460 /* 23822 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7646:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9461 /* 23822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_D),
9462 /* 23825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9463 /* 23827 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9464 /* 23829 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9465 /* 23831 */ GIR_RootConstrainSelectedInstOperands,
9466 /* 23832 */ // GIR_Coverage, 531,
9467 /* 23832 */ GIR_EraseRootFromParent_Done,
9468 /* 23833 */ // Label 728: @23833
9469 /* 23833 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(23878), // Rule ID 532 //
9470 /* 23838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9471 /* 23841 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
9472 /* 23846 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9473 /* 23849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9474 /* 23852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9475 /* 23855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9476 /* 23859 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9477 /* 23863 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9478 /* 23867 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7649:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9479 /* 23867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_B),
9480 /* 23870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9481 /* 23872 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9482 /* 23874 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9483 /* 23876 */ GIR_RootConstrainSelectedInstOperands,
9484 /* 23877 */ // GIR_Coverage, 532,
9485 /* 23877 */ GIR_EraseRootFromParent_Done,
9486 /* 23878 */ // Label 729: @23878
9487 /* 23878 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(23923), // Rule ID 533 //
9488 /* 23883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9489 /* 23886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
9490 /* 23891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9491 /* 23894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9492 /* 23897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9493 /* 23900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9494 /* 23904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9495 /* 23908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9496 /* 23912 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7651:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9497 /* 23912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_H),
9498 /* 23915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9499 /* 23917 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9500 /* 23919 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9501 /* 23921 */ GIR_RootConstrainSelectedInstOperands,
9502 /* 23922 */ // GIR_Coverage, 533,
9503 /* 23922 */ GIR_EraseRootFromParent_Done,
9504 /* 23923 */ // Label 730: @23923
9505 /* 23923 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(23968), // Rule ID 534 //
9506 /* 23928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9507 /* 23931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
9508 /* 23936 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9509 /* 23939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9510 /* 23942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9511 /* 23945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9512 /* 23949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9513 /* 23953 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9514 /* 23957 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7652:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9515 /* 23957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_W),
9516 /* 23960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9517 /* 23962 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9518 /* 23964 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9519 /* 23966 */ GIR_RootConstrainSelectedInstOperands,
9520 /* 23967 */ // GIR_Coverage, 534,
9521 /* 23967 */ GIR_EraseRootFromParent_Done,
9522 /* 23968 */ // Label 731: @23968
9523 /* 23968 */ GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(24013), // Rule ID 535 //
9524 /* 23973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9525 /* 23976 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
9526 /* 23981 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9527 /* 23984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9528 /* 23987 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9529 /* 23990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9530 /* 23994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9531 /* 23998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9532 /* 24002 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7650:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9533 /* 24002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_D),
9534 /* 24005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9535 /* 24007 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9536 /* 24009 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9537 /* 24011 */ GIR_RootConstrainSelectedInstOperands,
9538 /* 24012 */ // GIR_Coverage, 535,
9539 /* 24012 */ GIR_EraseRootFromParent_Done,
9540 /* 24013 */ // Label 732: @24013
9541 /* 24013 */ GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(24058), // Rule ID 536 //
9542 /* 24018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9543 /* 24021 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
9544 /* 24026 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9545 /* 24029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9546 /* 24032 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9547 /* 24035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9548 /* 24039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9549 /* 24043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9550 /* 24047 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7653:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9551 /* 24047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_B),
9552 /* 24050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9553 /* 24052 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9554 /* 24054 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9555 /* 24056 */ GIR_RootConstrainSelectedInstOperands,
9556 /* 24057 */ // GIR_Coverage, 536,
9557 /* 24057 */ GIR_EraseRootFromParent_Done,
9558 /* 24058 */ // Label 733: @24058
9559 /* 24058 */ GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(24103), // Rule ID 537 //
9560 /* 24063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9561 /* 24066 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
9562 /* 24071 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9563 /* 24074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9564 /* 24077 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9565 /* 24080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9566 /* 24084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9567 /* 24088 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9568 /* 24092 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7655:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9569 /* 24092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_H),
9570 /* 24095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9571 /* 24097 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9572 /* 24099 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9573 /* 24101 */ GIR_RootConstrainSelectedInstOperands,
9574 /* 24102 */ // GIR_Coverage, 537,
9575 /* 24102 */ GIR_EraseRootFromParent_Done,
9576 /* 24103 */ // Label 734: @24103
9577 /* 24103 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(24148), // Rule ID 538 //
9578 /* 24108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9579 /* 24111 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
9580 /* 24116 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9581 /* 24119 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9582 /* 24122 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9583 /* 24125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9584 /* 24129 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9585 /* 24133 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9586 /* 24137 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7656:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9587 /* 24137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_W),
9588 /* 24140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9589 /* 24142 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9590 /* 24144 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9591 /* 24146 */ GIR_RootConstrainSelectedInstOperands,
9592 /* 24147 */ // GIR_Coverage, 538,
9593 /* 24147 */ GIR_EraseRootFromParent_Done,
9594 /* 24148 */ // Label 735: @24148
9595 /* 24148 */ GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(24193), // Rule ID 539 //
9596 /* 24153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9597 /* 24156 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
9598 /* 24161 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9599 /* 24164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9600 /* 24167 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9601 /* 24170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9602 /* 24174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9603 /* 24178 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9604 /* 24182 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7654:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9605 /* 24182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_D),
9606 /* 24185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9607 /* 24187 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9608 /* 24189 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9609 /* 24191 */ GIR_RootConstrainSelectedInstOperands,
9610 /* 24192 */ // GIR_Coverage, 539,
9611 /* 24192 */ GIR_EraseRootFromParent_Done,
9612 /* 24193 */ // Label 736: @24193
9613 /* 24193 */ GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(24238), // Rule ID 540 //
9614 /* 24198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9615 /* 24201 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
9616 /* 24206 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9617 /* 24209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9618 /* 24212 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9619 /* 24215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9620 /* 24219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9621 /* 24223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9622 /* 24227 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7657:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9623 /* 24227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_B),
9624 /* 24230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9625 /* 24232 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9626 /* 24234 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9627 /* 24236 */ GIR_RootConstrainSelectedInstOperands,
9628 /* 24237 */ // GIR_Coverage, 540,
9629 /* 24237 */ GIR_EraseRootFromParent_Done,
9630 /* 24238 */ // Label 737: @24238
9631 /* 24238 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(24283), // Rule ID 541 //
9632 /* 24243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9633 /* 24246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
9634 /* 24251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9635 /* 24254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9636 /* 24257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9637 /* 24260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9638 /* 24264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9639 /* 24268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9640 /* 24272 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7659:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9641 /* 24272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_H),
9642 /* 24275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9643 /* 24277 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9644 /* 24279 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9645 /* 24281 */ GIR_RootConstrainSelectedInstOperands,
9646 /* 24282 */ // GIR_Coverage, 541,
9647 /* 24282 */ GIR_EraseRootFromParent_Done,
9648 /* 24283 */ // Label 738: @24283
9649 /* 24283 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(24328), // Rule ID 542 //
9650 /* 24288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9651 /* 24291 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
9652 /* 24296 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9653 /* 24299 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9654 /* 24302 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9655 /* 24305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9656 /* 24309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9657 /* 24313 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9658 /* 24317 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7660:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9659 /* 24317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_W),
9660 /* 24320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9661 /* 24322 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9662 /* 24324 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9663 /* 24326 */ GIR_RootConstrainSelectedInstOperands,
9664 /* 24327 */ // GIR_Coverage, 542,
9665 /* 24327 */ GIR_EraseRootFromParent_Done,
9666 /* 24328 */ // Label 739: @24328
9667 /* 24328 */ GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(24373), // Rule ID 543 //
9668 /* 24333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9669 /* 24336 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
9670 /* 24341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9671 /* 24344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9672 /* 24347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9673 /* 24350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9674 /* 24354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9675 /* 24358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9676 /* 24362 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7658:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9677 /* 24362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_D),
9678 /* 24365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9679 /* 24367 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9680 /* 24369 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9681 /* 24371 */ GIR_RootConstrainSelectedInstOperands,
9682 /* 24372 */ // GIR_Coverage, 543,
9683 /* 24372 */ GIR_EraseRootFromParent_Done,
9684 /* 24373 */ // Label 740: @24373
9685 /* 24373 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(24418), // Rule ID 652 //
9686 /* 24378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9687 /* 24381 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
9688 /* 24386 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9689 /* 24389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9690 /* 24392 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9691 /* 24395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9692 /* 24399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9693 /* 24403 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9694 /* 24407 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7792:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9695 /* 24407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_H),
9696 /* 24410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9697 /* 24412 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9698 /* 24414 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9699 /* 24416 */ GIR_RootConstrainSelectedInstOperands,
9700 /* 24417 */ // GIR_Coverage, 652,
9701 /* 24417 */ GIR_EraseRootFromParent_Done,
9702 /* 24418 */ // Label 741: @24418
9703 /* 24418 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(24463), // Rule ID 653 //
9704 /* 24423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9705 /* 24426 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
9706 /* 24431 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9707 /* 24434 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9708 /* 24437 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9709 /* 24440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9710 /* 24444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9711 /* 24448 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9712 /* 24452 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7793:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9713 /* 24452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_W),
9714 /* 24455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9715 /* 24457 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9716 /* 24459 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9717 /* 24461 */ GIR_RootConstrainSelectedInstOperands,
9718 /* 24462 */ // GIR_Coverage, 653,
9719 /* 24462 */ GIR_EraseRootFromParent_Done,
9720 /* 24463 */ // Label 742: @24463
9721 /* 24463 */ GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(24508), // Rule ID 654 //
9722 /* 24468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9723 /* 24471 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
9724 /* 24476 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9725 /* 24479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9726 /* 24482 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9727 /* 24485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9728 /* 24489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9729 /* 24493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9730 /* 24497 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7791:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9731 /* 24497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_D),
9732 /* 24500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9733 /* 24502 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9734 /* 24504 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9735 /* 24506 */ GIR_RootConstrainSelectedInstOperands,
9736 /* 24507 */ // GIR_Coverage, 654,
9737 /* 24507 */ GIR_EraseRootFromParent_Done,
9738 /* 24508 */ // Label 743: @24508
9739 /* 24508 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(24553), // Rule ID 655 //
9740 /* 24513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9741 /* 24516 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
9742 /* 24521 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9743 /* 24524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9744 /* 24527 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9745 /* 24530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9746 /* 24534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9747 /* 24538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9748 /* 24542 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7795:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9749 /* 24542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_H),
9750 /* 24545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9751 /* 24547 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9752 /* 24549 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9753 /* 24551 */ GIR_RootConstrainSelectedInstOperands,
9754 /* 24552 */ // GIR_Coverage, 655,
9755 /* 24552 */ GIR_EraseRootFromParent_Done,
9756 /* 24553 */ // Label 744: @24553
9757 /* 24553 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(24598), // Rule ID 656 //
9758 /* 24558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9759 /* 24561 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
9760 /* 24566 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9761 /* 24569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9762 /* 24572 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9763 /* 24575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9764 /* 24579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9765 /* 24583 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9766 /* 24587 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7796:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9767 /* 24587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_W),
9768 /* 24590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9769 /* 24592 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9770 /* 24594 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9771 /* 24596 */ GIR_RootConstrainSelectedInstOperands,
9772 /* 24597 */ // GIR_Coverage, 656,
9773 /* 24597 */ GIR_EraseRootFromParent_Done,
9774 /* 24598 */ // Label 745: @24598
9775 /* 24598 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(24643), // Rule ID 657 //
9776 /* 24603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9777 /* 24606 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
9778 /* 24611 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9779 /* 24614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9780 /* 24617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9781 /* 24620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9782 /* 24624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9783 /* 24628 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9784 /* 24632 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7794:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9785 /* 24632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_D),
9786 /* 24635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9787 /* 24637 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9788 /* 24639 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9789 /* 24641 */ GIR_RootConstrainSelectedInstOperands,
9790 /* 24642 */ // GIR_Coverage, 657,
9791 /* 24642 */ GIR_EraseRootFromParent_Done,
9792 /* 24643 */ // Label 746: @24643
9793 /* 24643 */ GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(24688), // Rule ID 672 //
9794 /* 24648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9795 /* 24651 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
9796 /* 24656 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9797 /* 24659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9798 /* 24662 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9799 /* 24665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9800 /* 24669 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9801 /* 24673 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9802 /* 24677 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7834:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9803 /* 24677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_W),
9804 /* 24680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9805 /* 24682 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9806 /* 24684 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9807 /* 24686 */ GIR_RootConstrainSelectedInstOperands,
9808 /* 24687 */ // GIR_Coverage, 672,
9809 /* 24687 */ GIR_EraseRootFromParent_Done,
9810 /* 24688 */ // Label 747: @24688
9811 /* 24688 */ GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(24733), // Rule ID 673 //
9812 /* 24693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9813 /* 24696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
9814 /* 24701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9815 /* 24704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9816 /* 24707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9817 /* 24710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9818 /* 24714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9819 /* 24718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9820 /* 24722 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7833:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9821 /* 24722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_D),
9822 /* 24725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9823 /* 24727 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9824 /* 24729 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9825 /* 24731 */ GIR_RootConstrainSelectedInstOperands,
9826 /* 24732 */ // GIR_Coverage, 673,
9827 /* 24732 */ GIR_EraseRootFromParent_Done,
9828 /* 24733 */ // Label 748: @24733
9829 /* 24733 */ GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(24778), // Rule ID 698 //
9830 /* 24738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9831 /* 24741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
9832 /* 24746 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9833 /* 24749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9834 /* 24752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9835 /* 24755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9836 /* 24759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9837 /* 24763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9838 /* 24767 */ // (intrinsic_wo_chain:{ *:[v8f16] } 7859:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9839 /* 24767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_H),
9840 /* 24770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9841 /* 24772 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9842 /* 24774 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9843 /* 24776 */ GIR_RootConstrainSelectedInstOperands,
9844 /* 24777 */ // GIR_Coverage, 698,
9845 /* 24777 */ GIR_EraseRootFromParent_Done,
9846 /* 24778 */ // Label 749: @24778
9847 /* 24778 */ GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(24823), // Rule ID 699 //
9848 /* 24783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9849 /* 24786 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
9850 /* 24791 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9851 /* 24794 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9852 /* 24797 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9853 /* 24800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9854 /* 24804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9855 /* 24808 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9856 /* 24812 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7860:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9857 /* 24812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_W),
9858 /* 24815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9859 /* 24817 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9860 /* 24819 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9861 /* 24821 */ GIR_RootConstrainSelectedInstOperands,
9862 /* 24822 */ // GIR_Coverage, 699,
9863 /* 24822 */ GIR_EraseRootFromParent_Done,
9864 /* 24823 */ // Label 750: @24823
9865 /* 24823 */ GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(24868), // Rule ID 726 //
9866 /* 24828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9867 /* 24831 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_w),
9868 /* 24836 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9869 /* 24839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9870 /* 24842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9871 /* 24845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9872 /* 24849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9873 /* 24853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9874 /* 24857 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7886:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9875 /* 24857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_W),
9876 /* 24860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9877 /* 24862 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9878 /* 24864 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9879 /* 24866 */ GIR_RootConstrainSelectedInstOperands,
9880 /* 24867 */ // GIR_Coverage, 726,
9881 /* 24867 */ GIR_EraseRootFromParent_Done,
9882 /* 24868 */ // Label 751: @24868
9883 /* 24868 */ GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(24913), // Rule ID 727 //
9884 /* 24873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9885 /* 24876 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_d),
9886 /* 24881 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9887 /* 24884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9888 /* 24887 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9889 /* 24890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9890 /* 24894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9891 /* 24898 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9892 /* 24902 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7885:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9893 /* 24902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_D),
9894 /* 24905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9895 /* 24907 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9896 /* 24909 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9897 /* 24911 */ GIR_RootConstrainSelectedInstOperands,
9898 /* 24912 */ // GIR_Coverage, 727,
9899 /* 24912 */ GIR_EraseRootFromParent_Done,
9900 /* 24913 */ // Label 752: @24913
9901 /* 24913 */ GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(24958), // Rule ID 728 //
9902 /* 24918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9903 /* 24921 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
9904 /* 24926 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9905 /* 24929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9906 /* 24932 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9907 /* 24935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9908 /* 24939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9909 /* 24943 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9910 /* 24947 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7884:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9911 /* 24947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_W),
9912 /* 24950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9913 /* 24952 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9914 /* 24954 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9915 /* 24956 */ GIR_RootConstrainSelectedInstOperands,
9916 /* 24957 */ // GIR_Coverage, 728,
9917 /* 24957 */ GIR_EraseRootFromParent_Done,
9918 /* 24958 */ // Label 753: @24958
9919 /* 24958 */ GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(25003), // Rule ID 729 //
9920 /* 24963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9921 /* 24966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
9922 /* 24971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9923 /* 24974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9924 /* 24977 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9925 /* 24980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9926 /* 24984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9927 /* 24988 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9928 /* 24992 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7883:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9929 /* 24992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_D),
9930 /* 24995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9931 /* 24997 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9932 /* 24999 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9933 /* 25001 */ GIR_RootConstrainSelectedInstOperands,
9934 /* 25002 */ // GIR_Coverage, 729,
9935 /* 25002 */ GIR_EraseRootFromParent_Done,
9936 /* 25003 */ // Label 754: @25003
9937 /* 25003 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(25048), // Rule ID 730 //
9938 /* 25008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9939 /* 25011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_w),
9940 /* 25016 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9941 /* 25019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9942 /* 25022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9943 /* 25025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9944 /* 25029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9945 /* 25033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9946 /* 25037 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7890:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9947 /* 25037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_W),
9948 /* 25040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9949 /* 25042 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9950 /* 25044 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9951 /* 25046 */ GIR_RootConstrainSelectedInstOperands,
9952 /* 25047 */ // GIR_Coverage, 730,
9953 /* 25047 */ GIR_EraseRootFromParent_Done,
9954 /* 25048 */ // Label 755: @25048
9955 /* 25048 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(25093), // Rule ID 731 //
9956 /* 25053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9957 /* 25056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_d),
9958 /* 25061 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9959 /* 25064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9960 /* 25067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9961 /* 25070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9962 /* 25074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9963 /* 25078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9964 /* 25082 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7889:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9965 /* 25082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_D),
9966 /* 25085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9967 /* 25087 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9968 /* 25089 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9969 /* 25091 */ GIR_RootConstrainSelectedInstOperands,
9970 /* 25092 */ // GIR_Coverage, 731,
9971 /* 25092 */ GIR_EraseRootFromParent_Done,
9972 /* 25093 */ // Label 756: @25093
9973 /* 25093 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(25138), // Rule ID 732 //
9974 /* 25098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9975 /* 25101 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
9976 /* 25106 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9977 /* 25109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9978 /* 25112 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9979 /* 25115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9980 /* 25119 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9981 /* 25123 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9982 /* 25127 */ // (intrinsic_wo_chain:{ *:[v4f32] } 7888:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9983 /* 25127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_W),
9984 /* 25130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9985 /* 25132 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9986 /* 25134 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9987 /* 25136 */ GIR_RootConstrainSelectedInstOperands,
9988 /* 25137 */ // GIR_Coverage, 732,
9989 /* 25137 */ GIR_EraseRootFromParent_Done,
9990 /* 25138 */ // Label 757: @25138
9991 /* 25138 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(25183), // Rule ID 733 //
9992 /* 25143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9993 /* 25146 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
9994 /* 25151 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9995 /* 25154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9996 /* 25157 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9997 /* 25160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9998 /* 25164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9999 /* 25168 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10000 /* 25172 */ // (intrinsic_wo_chain:{ *:[v2f64] } 7887:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10001 /* 25172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_D),
10002 /* 25175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10003 /* 25177 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10004 /* 25179 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10005 /* 25181 */ GIR_RootConstrainSelectedInstOperands,
10006 /* 25182 */ // GIR_Coverage, 733,
10007 /* 25182 */ GIR_EraseRootFromParent_Done,
10008 /* 25183 */ // Label 758: @25183
10009 /* 25183 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(25228), // Rule ID 744 //
10010 /* 25188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10011 /* 25191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
10012 /* 25196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10013 /* 25199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10014 /* 25202 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10015 /* 25205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10016 /* 25209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10017 /* 25213 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10018 /* 25217 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7902:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10019 /* 25217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_W),
10020 /* 25220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10021 /* 25222 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10022 /* 25224 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10023 /* 25226 */ GIR_RootConstrainSelectedInstOperands,
10024 /* 25227 */ // GIR_Coverage, 744,
10025 /* 25227 */ GIR_EraseRootFromParent_Done,
10026 /* 25228 */ // Label 759: @25228
10027 /* 25228 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(25273), // Rule ID 745 //
10028 /* 25233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10029 /* 25236 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
10030 /* 25241 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10031 /* 25244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10032 /* 25247 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10033 /* 25250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10034 /* 25254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10035 /* 25258 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10036 /* 25262 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7901:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10037 /* 25262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_D),
10038 /* 25265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10039 /* 25267 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10040 /* 25269 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10041 /* 25271 */ GIR_RootConstrainSelectedInstOperands,
10042 /* 25272 */ // GIR_Coverage, 745,
10043 /* 25272 */ GIR_EraseRootFromParent_Done,
10044 /* 25273 */ // Label 760: @25273
10045 /* 25273 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(25318), // Rule ID 746 //
10046 /* 25278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10047 /* 25281 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_w),
10048 /* 25286 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10049 /* 25289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10050 /* 25292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10051 /* 25295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10052 /* 25299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10053 /* 25303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10054 /* 25307 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7904:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10055 /* 25307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_W),
10056 /* 25310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10057 /* 25312 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10058 /* 25314 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10059 /* 25316 */ GIR_RootConstrainSelectedInstOperands,
10060 /* 25317 */ // GIR_Coverage, 746,
10061 /* 25317 */ GIR_EraseRootFromParent_Done,
10062 /* 25318 */ // Label 761: @25318
10063 /* 25318 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(25363), // Rule ID 747 //
10064 /* 25323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10065 /* 25326 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_d),
10066 /* 25331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10067 /* 25334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10068 /* 25337 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10069 /* 25340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10070 /* 25344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10071 /* 25348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10072 /* 25352 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7903:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10073 /* 25352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_D),
10074 /* 25355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10075 /* 25357 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10076 /* 25359 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10077 /* 25361 */ GIR_RootConstrainSelectedInstOperands,
10078 /* 25362 */ // GIR_Coverage, 747,
10079 /* 25362 */ GIR_EraseRootFromParent_Done,
10080 /* 25363 */ // Label 762: @25363
10081 /* 25363 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(25408), // Rule ID 748 //
10082 /* 25368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10083 /* 25371 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_w),
10084 /* 25376 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10085 /* 25379 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10086 /* 25382 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10087 /* 25385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10088 /* 25389 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10089 /* 25393 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10090 /* 25397 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7906:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10091 /* 25397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_W),
10092 /* 25400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10093 /* 25402 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10094 /* 25404 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10095 /* 25406 */ GIR_RootConstrainSelectedInstOperands,
10096 /* 25407 */ // GIR_Coverage, 748,
10097 /* 25407 */ GIR_EraseRootFromParent_Done,
10098 /* 25408 */ // Label 763: @25408
10099 /* 25408 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(25453), // Rule ID 749 //
10100 /* 25413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10101 /* 25416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_d),
10102 /* 25421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10103 /* 25424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10104 /* 25427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10105 /* 25430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10106 /* 25434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10107 /* 25438 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10108 /* 25442 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7905:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10109 /* 25442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_D),
10110 /* 25445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10111 /* 25447 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10112 /* 25449 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10113 /* 25451 */ GIR_RootConstrainSelectedInstOperands,
10114 /* 25452 */ // GIR_Coverage, 749,
10115 /* 25452 */ GIR_EraseRootFromParent_Done,
10116 /* 25453 */ // Label 764: @25453
10117 /* 25453 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(25498), // Rule ID 750 //
10118 /* 25458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10119 /* 25461 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_w),
10120 /* 25466 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10121 /* 25469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10122 /* 25472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10123 /* 25475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10124 /* 25479 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10125 /* 25483 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10126 /* 25487 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7908:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10127 /* 25487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_W),
10128 /* 25490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10129 /* 25492 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10130 /* 25494 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10131 /* 25496 */ GIR_RootConstrainSelectedInstOperands,
10132 /* 25497 */ // GIR_Coverage, 750,
10133 /* 25497 */ GIR_EraseRootFromParent_Done,
10134 /* 25498 */ // Label 765: @25498
10135 /* 25498 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(25543), // Rule ID 751 //
10136 /* 25503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10137 /* 25506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_d),
10138 /* 25511 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10139 /* 25514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10140 /* 25517 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10141 /* 25520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10142 /* 25524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10143 /* 25528 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10144 /* 25532 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7907:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10145 /* 25532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_D),
10146 /* 25535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10147 /* 25537 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10148 /* 25539 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10149 /* 25541 */ GIR_RootConstrainSelectedInstOperands,
10150 /* 25542 */ // GIR_Coverage, 751,
10151 /* 25542 */ GIR_EraseRootFromParent_Done,
10152 /* 25543 */ // Label 766: @25543
10153 /* 25543 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(25588), // Rule ID 752 //
10154 /* 25548 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10155 /* 25551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_w),
10156 /* 25556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10157 /* 25559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10158 /* 25562 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10159 /* 25565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10160 /* 25569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10161 /* 25573 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10162 /* 25577 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7910:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10163 /* 25577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_W),
10164 /* 25580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10165 /* 25582 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10166 /* 25584 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10167 /* 25586 */ GIR_RootConstrainSelectedInstOperands,
10168 /* 25587 */ // GIR_Coverage, 752,
10169 /* 25587 */ GIR_EraseRootFromParent_Done,
10170 /* 25588 */ // Label 767: @25588
10171 /* 25588 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(25633), // Rule ID 753 //
10172 /* 25593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10173 /* 25596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_d),
10174 /* 25601 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10175 /* 25604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10176 /* 25607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10177 /* 25610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10178 /* 25614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10179 /* 25618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10180 /* 25622 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7909:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10181 /* 25622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_D),
10182 /* 25625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10183 /* 25627 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10184 /* 25629 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10185 /* 25631 */ GIR_RootConstrainSelectedInstOperands,
10186 /* 25632 */ // GIR_Coverage, 753,
10187 /* 25632 */ GIR_EraseRootFromParent_Done,
10188 /* 25633 */ // Label 768: @25633
10189 /* 25633 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(25678), // Rule ID 754 //
10190 /* 25638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10191 /* 25641 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_w),
10192 /* 25646 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10193 /* 25649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10194 /* 25652 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10195 /* 25655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10196 /* 25659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10197 /* 25663 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10198 /* 25667 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7912:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10199 /* 25667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_W),
10200 /* 25670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10201 /* 25672 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10202 /* 25674 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10203 /* 25676 */ GIR_RootConstrainSelectedInstOperands,
10204 /* 25677 */ // GIR_Coverage, 754,
10205 /* 25677 */ GIR_EraseRootFromParent_Done,
10206 /* 25678 */ // Label 769: @25678
10207 /* 25678 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(25723), // Rule ID 755 //
10208 /* 25683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10209 /* 25686 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_d),
10210 /* 25691 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10211 /* 25694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10212 /* 25697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10213 /* 25700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10214 /* 25704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10215 /* 25708 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10216 /* 25712 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7911:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10217 /* 25712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_D),
10218 /* 25715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10219 /* 25717 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10220 /* 25719 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10221 /* 25721 */ GIR_RootConstrainSelectedInstOperands,
10222 /* 25722 */ // GIR_Coverage, 755,
10223 /* 25722 */ GIR_EraseRootFromParent_Done,
10224 /* 25723 */ // Label 770: @25723
10225 /* 25723 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(25768), // Rule ID 760 //
10226 /* 25728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10227 /* 25731 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
10228 /* 25736 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10229 /* 25739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10230 /* 25742 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10231 /* 25745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10232 /* 25749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10233 /* 25753 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10234 /* 25757 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7918:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10235 /* 25757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_W),
10236 /* 25760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10237 /* 25762 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10238 /* 25764 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10239 /* 25766 */ GIR_RootConstrainSelectedInstOperands,
10240 /* 25767 */ // GIR_Coverage, 760,
10241 /* 25767 */ GIR_EraseRootFromParent_Done,
10242 /* 25768 */ // Label 771: @25768
10243 /* 25768 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(25813), // Rule ID 761 //
10244 /* 25773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10245 /* 25776 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
10246 /* 25781 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10247 /* 25784 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10248 /* 25787 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10249 /* 25790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10250 /* 25794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10251 /* 25798 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10252 /* 25802 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7917:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10253 /* 25802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_D),
10254 /* 25805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10255 /* 25807 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10256 /* 25809 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10257 /* 25811 */ GIR_RootConstrainSelectedInstOperands,
10258 /* 25812 */ // GIR_Coverage, 761,
10259 /* 25812 */ GIR_EraseRootFromParent_Done,
10260 /* 25813 */ // Label 772: @25813
10261 /* 25813 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(25858), // Rule ID 762 //
10262 /* 25818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10263 /* 25821 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_w),
10264 /* 25826 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10265 /* 25829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10266 /* 25832 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10267 /* 25835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10268 /* 25839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10269 /* 25843 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10270 /* 25847 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7920:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10271 /* 25847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_W),
10272 /* 25850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10273 /* 25852 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10274 /* 25854 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10275 /* 25856 */ GIR_RootConstrainSelectedInstOperands,
10276 /* 25857 */ // GIR_Coverage, 762,
10277 /* 25857 */ GIR_EraseRootFromParent_Done,
10278 /* 25858 */ // Label 773: @25858
10279 /* 25858 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(25903), // Rule ID 763 //
10280 /* 25863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10281 /* 25866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_d),
10282 /* 25871 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10283 /* 25874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10284 /* 25877 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10285 /* 25880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10286 /* 25884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10287 /* 25888 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10288 /* 25892 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7919:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10289 /* 25892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_D),
10290 /* 25895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10291 /* 25897 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10292 /* 25899 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10293 /* 25901 */ GIR_RootConstrainSelectedInstOperands,
10294 /* 25902 */ // GIR_Coverage, 763,
10295 /* 25902 */ GIR_EraseRootFromParent_Done,
10296 /* 25903 */ // Label 774: @25903
10297 /* 25903 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(25948), // Rule ID 764 //
10298 /* 25908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10299 /* 25911 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_w),
10300 /* 25916 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10301 /* 25919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10302 /* 25922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10303 /* 25925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10304 /* 25929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10305 /* 25933 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10306 /* 25937 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7922:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10307 /* 25937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_W),
10308 /* 25940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10309 /* 25942 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10310 /* 25944 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10311 /* 25946 */ GIR_RootConstrainSelectedInstOperands,
10312 /* 25947 */ // GIR_Coverage, 764,
10313 /* 25947 */ GIR_EraseRootFromParent_Done,
10314 /* 25948 */ // Label 775: @25948
10315 /* 25948 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(25993), // Rule ID 765 //
10316 /* 25953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10317 /* 25956 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_d),
10318 /* 25961 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10319 /* 25964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10320 /* 25967 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10321 /* 25970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10322 /* 25974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10323 /* 25978 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10324 /* 25982 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7921:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10325 /* 25982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_D),
10326 /* 25985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10327 /* 25987 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10328 /* 25989 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10329 /* 25991 */ GIR_RootConstrainSelectedInstOperands,
10330 /* 25992 */ // GIR_Coverage, 765,
10331 /* 25992 */ GIR_EraseRootFromParent_Done,
10332 /* 25993 */ // Label 776: @25993
10333 /* 25993 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(26038), // Rule ID 766 //
10334 /* 25998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10335 /* 26001 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_w),
10336 /* 26006 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10337 /* 26009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10338 /* 26012 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10339 /* 26015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10340 /* 26019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10341 /* 26023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10342 /* 26027 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7924:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10343 /* 26027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_W),
10344 /* 26030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10345 /* 26032 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10346 /* 26034 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10347 /* 26036 */ GIR_RootConstrainSelectedInstOperands,
10348 /* 26037 */ // GIR_Coverage, 766,
10349 /* 26037 */ GIR_EraseRootFromParent_Done,
10350 /* 26038 */ // Label 777: @26038
10351 /* 26038 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(26083), // Rule ID 767 //
10352 /* 26043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10353 /* 26046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_d),
10354 /* 26051 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10355 /* 26054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10356 /* 26057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10357 /* 26060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10358 /* 26064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10359 /* 26068 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10360 /* 26072 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7923:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10361 /* 26072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_D),
10362 /* 26075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10363 /* 26077 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10364 /* 26079 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10365 /* 26081 */ GIR_RootConstrainSelectedInstOperands,
10366 /* 26082 */ // GIR_Coverage, 767,
10367 /* 26082 */ GIR_EraseRootFromParent_Done,
10368 /* 26083 */ // Label 778: @26083
10369 /* 26083 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(26128), // Rule ID 768 //
10370 /* 26088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10371 /* 26091 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_w),
10372 /* 26096 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10373 /* 26099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10374 /* 26102 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10375 /* 26105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10376 /* 26109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10377 /* 26113 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10378 /* 26117 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7926:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10379 /* 26117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_W),
10380 /* 26120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10381 /* 26122 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10382 /* 26124 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10383 /* 26126 */ GIR_RootConstrainSelectedInstOperands,
10384 /* 26127 */ // GIR_Coverage, 768,
10385 /* 26127 */ GIR_EraseRootFromParent_Done,
10386 /* 26128 */ // Label 779: @26128
10387 /* 26128 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(26173), // Rule ID 769 //
10388 /* 26133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10389 /* 26136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_d),
10390 /* 26141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10391 /* 26144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10392 /* 26147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10393 /* 26150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10394 /* 26154 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10395 /* 26158 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10396 /* 26162 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7925:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10397 /* 26162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_D),
10398 /* 26165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10399 /* 26167 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10400 /* 26169 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10401 /* 26171 */ GIR_RootConstrainSelectedInstOperands,
10402 /* 26172 */ // GIR_Coverage, 769,
10403 /* 26172 */ GIR_EraseRootFromParent_Done,
10404 /* 26173 */ // Label 780: @26173
10405 /* 26173 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(26218), // Rule ID 774 //
10406 /* 26178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10407 /* 26181 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_h),
10408 /* 26186 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10409 /* 26189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10410 /* 26192 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10411 /* 26195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10412 /* 26199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10413 /* 26203 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10414 /* 26207 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7931:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10415 /* 26207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_H),
10416 /* 26210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10417 /* 26212 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10418 /* 26214 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10419 /* 26216 */ GIR_RootConstrainSelectedInstOperands,
10420 /* 26217 */ // GIR_Coverage, 774,
10421 /* 26217 */ GIR_EraseRootFromParent_Done,
10422 /* 26218 */ // Label 781: @26218
10423 /* 26218 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(26263), // Rule ID 775 //
10424 /* 26223 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10425 /* 26226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_w),
10426 /* 26231 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10427 /* 26234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10428 /* 26237 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10429 /* 26240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10430 /* 26244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10431 /* 26248 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10432 /* 26252 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7932:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10433 /* 26252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_W),
10434 /* 26255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10435 /* 26257 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10436 /* 26259 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10437 /* 26261 */ GIR_RootConstrainSelectedInstOperands,
10438 /* 26262 */ // GIR_Coverage, 775,
10439 /* 26262 */ GIR_EraseRootFromParent_Done,
10440 /* 26263 */ // Label 782: @26263
10441 /* 26263 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(26308), // Rule ID 780 //
10442 /* 26268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10443 /* 26271 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
10444 /* 26276 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10445 /* 26279 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10446 /* 26282 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10447 /* 26285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10448 /* 26289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10449 /* 26293 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10450 /* 26297 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7938:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10451 /* 26297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_H),
10452 /* 26300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10453 /* 26302 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10454 /* 26304 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10455 /* 26306 */ GIR_RootConstrainSelectedInstOperands,
10456 /* 26307 */ // GIR_Coverage, 780,
10457 /* 26307 */ GIR_EraseRootFromParent_Done,
10458 /* 26308 */ // Label 783: @26308
10459 /* 26308 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(26353), // Rule ID 781 //
10460 /* 26313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10461 /* 26316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
10462 /* 26321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10463 /* 26324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10464 /* 26327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10465 /* 26330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10466 /* 26334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10467 /* 26338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10468 /* 26342 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7939:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10469 /* 26342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_W),
10470 /* 26345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10471 /* 26347 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10472 /* 26349 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10473 /* 26351 */ GIR_RootConstrainSelectedInstOperands,
10474 /* 26352 */ // GIR_Coverage, 781,
10475 /* 26352 */ GIR_EraseRootFromParent_Done,
10476 /* 26353 */ // Label 784: @26353
10477 /* 26353 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(26398), // Rule ID 782 //
10478 /* 26358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10479 /* 26361 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
10480 /* 26366 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10481 /* 26369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10482 /* 26372 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10483 /* 26375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10484 /* 26379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10485 /* 26383 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10486 /* 26387 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7937:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10487 /* 26387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_D),
10488 /* 26390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10489 /* 26392 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10490 /* 26394 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10491 /* 26396 */ GIR_RootConstrainSelectedInstOperands,
10492 /* 26397 */ // GIR_Coverage, 782,
10493 /* 26397 */ GIR_EraseRootFromParent_Done,
10494 /* 26398 */ // Label 785: @26398
10495 /* 26398 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(26443), // Rule ID 783 //
10496 /* 26403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10497 /* 26406 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
10498 /* 26411 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10499 /* 26414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10500 /* 26417 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10501 /* 26420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10502 /* 26424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10503 /* 26428 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10504 /* 26432 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7941:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10505 /* 26432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_H),
10506 /* 26435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10507 /* 26437 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10508 /* 26439 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10509 /* 26441 */ GIR_RootConstrainSelectedInstOperands,
10510 /* 26442 */ // GIR_Coverage, 783,
10511 /* 26442 */ GIR_EraseRootFromParent_Done,
10512 /* 26443 */ // Label 786: @26443
10513 /* 26443 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(26488), // Rule ID 784 //
10514 /* 26448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10515 /* 26451 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
10516 /* 26456 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10517 /* 26459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10518 /* 26462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10519 /* 26465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10520 /* 26469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10521 /* 26473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10522 /* 26477 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7942:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10523 /* 26477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_W),
10524 /* 26480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10525 /* 26482 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10526 /* 26484 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10527 /* 26486 */ GIR_RootConstrainSelectedInstOperands,
10528 /* 26487 */ // GIR_Coverage, 784,
10529 /* 26487 */ GIR_EraseRootFromParent_Done,
10530 /* 26488 */ // Label 787: @26488
10531 /* 26488 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(26533), // Rule ID 785 //
10532 /* 26493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10533 /* 26496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
10534 /* 26501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10535 /* 26504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10536 /* 26507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10537 /* 26510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10538 /* 26514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10539 /* 26518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10540 /* 26522 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7940:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10541 /* 26522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_D),
10542 /* 26525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10543 /* 26527 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10544 /* 26529 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10545 /* 26531 */ GIR_RootConstrainSelectedInstOperands,
10546 /* 26532 */ // GIR_Coverage, 785,
10547 /* 26532 */ GIR_EraseRootFromParent_Done,
10548 /* 26533 */ // Label 788: @26533
10549 /* 26533 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(26578), // Rule ID 786 //
10550 /* 26538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10551 /* 26541 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
10552 /* 26546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10553 /* 26549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10554 /* 26552 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10555 /* 26555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10556 /* 26559 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10557 /* 26563 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10558 /* 26567 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7944:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10559 /* 26567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_H),
10560 /* 26570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10561 /* 26572 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10562 /* 26574 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10563 /* 26576 */ GIR_RootConstrainSelectedInstOperands,
10564 /* 26577 */ // GIR_Coverage, 786,
10565 /* 26577 */ GIR_EraseRootFromParent_Done,
10566 /* 26578 */ // Label 789: @26578
10567 /* 26578 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(26623), // Rule ID 787 //
10568 /* 26583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10569 /* 26586 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
10570 /* 26591 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10571 /* 26594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10572 /* 26597 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10573 /* 26600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10574 /* 26604 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10575 /* 26608 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10576 /* 26612 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7945:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10577 /* 26612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_W),
10578 /* 26615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10579 /* 26617 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10580 /* 26619 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10581 /* 26621 */ GIR_RootConstrainSelectedInstOperands,
10582 /* 26622 */ // GIR_Coverage, 787,
10583 /* 26622 */ GIR_EraseRootFromParent_Done,
10584 /* 26623 */ // Label 790: @26623
10585 /* 26623 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(26668), // Rule ID 788 //
10586 /* 26628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10587 /* 26631 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
10588 /* 26636 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10589 /* 26639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10590 /* 26642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10591 /* 26645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10592 /* 26649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10593 /* 26653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10594 /* 26657 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7943:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10595 /* 26657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_D),
10596 /* 26660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10597 /* 26662 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10598 /* 26664 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10599 /* 26666 */ GIR_RootConstrainSelectedInstOperands,
10600 /* 26667 */ // GIR_Coverage, 788,
10601 /* 26667 */ GIR_EraseRootFromParent_Done,
10602 /* 26668 */ // Label 791: @26668
10603 /* 26668 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(26713), // Rule ID 789 //
10604 /* 26673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10605 /* 26676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
10606 /* 26681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10607 /* 26684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10608 /* 26687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10609 /* 26690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10610 /* 26694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10611 /* 26698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10612 /* 26702 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7947:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10613 /* 26702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_H),
10614 /* 26705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10615 /* 26707 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10616 /* 26709 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10617 /* 26711 */ GIR_RootConstrainSelectedInstOperands,
10618 /* 26712 */ // GIR_Coverage, 789,
10619 /* 26712 */ GIR_EraseRootFromParent_Done,
10620 /* 26713 */ // Label 792: @26713
10621 /* 26713 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(26758), // Rule ID 790 //
10622 /* 26718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10623 /* 26721 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
10624 /* 26726 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10625 /* 26729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10626 /* 26732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10627 /* 26735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10628 /* 26739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10629 /* 26743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10630 /* 26747 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7948:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10631 /* 26747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_W),
10632 /* 26750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10633 /* 26752 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10634 /* 26754 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10635 /* 26756 */ GIR_RootConstrainSelectedInstOperands,
10636 /* 26757 */ // GIR_Coverage, 790,
10637 /* 26757 */ GIR_EraseRootFromParent_Done,
10638 /* 26758 */ // Label 793: @26758
10639 /* 26758 */ GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(26803), // Rule ID 791 //
10640 /* 26763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10641 /* 26766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
10642 /* 26771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10643 /* 26774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10644 /* 26777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10645 /* 26780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10646 /* 26784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10647 /* 26788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10648 /* 26792 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7946:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10649 /* 26792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_D),
10650 /* 26795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10651 /* 26797 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10652 /* 26799 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10653 /* 26801 */ GIR_RootConstrainSelectedInstOperands,
10654 /* 26802 */ // GIR_Coverage, 791,
10655 /* 26802 */ GIR_EraseRootFromParent_Done,
10656 /* 26803 */ // Label 794: @26803
10657 /* 26803 */ GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(26848), // Rule ID 844 //
10658 /* 26808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10659 /* 26811 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_b),
10660 /* 26816 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10661 /* 26819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10662 /* 26822 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10663 /* 26825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10664 /* 26829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10665 /* 26833 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10666 /* 26837 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8002:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10667 /* 26837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_B),
10668 /* 26840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10669 /* 26842 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10670 /* 26844 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10671 /* 26846 */ GIR_RootConstrainSelectedInstOperands,
10672 /* 26847 */ // GIR_Coverage, 844,
10673 /* 26847 */ GIR_EraseRootFromParent_Done,
10674 /* 26848 */ // Label 795: @26848
10675 /* 26848 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(26893), // Rule ID 845 //
10676 /* 26853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10677 /* 26856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_h),
10678 /* 26861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10679 /* 26864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10680 /* 26867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10681 /* 26870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10682 /* 26874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10683 /* 26878 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10684 /* 26882 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8004:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10685 /* 26882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_H),
10686 /* 26885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10687 /* 26887 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10688 /* 26889 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10689 /* 26891 */ GIR_RootConstrainSelectedInstOperands,
10690 /* 26892 */ // GIR_Coverage, 845,
10691 /* 26892 */ GIR_EraseRootFromParent_Done,
10692 /* 26893 */ // Label 796: @26893
10693 /* 26893 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(26938), // Rule ID 846 //
10694 /* 26898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10695 /* 26901 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_w),
10696 /* 26906 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10697 /* 26909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10698 /* 26912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10699 /* 26915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10700 /* 26919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10701 /* 26923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10702 /* 26927 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8005:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10703 /* 26927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_W),
10704 /* 26930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10705 /* 26932 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10706 /* 26934 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10707 /* 26936 */ GIR_RootConstrainSelectedInstOperands,
10708 /* 26937 */ // GIR_Coverage, 846,
10709 /* 26937 */ GIR_EraseRootFromParent_Done,
10710 /* 26938 */ // Label 797: @26938
10711 /* 26938 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(26983), // Rule ID 847 //
10712 /* 26943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10713 /* 26946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_d),
10714 /* 26951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10715 /* 26954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10716 /* 26957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10717 /* 26960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10718 /* 26964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10719 /* 26968 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10720 /* 26972 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8003:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10721 /* 26972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_D),
10722 /* 26975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10723 /* 26977 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10724 /* 26979 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10725 /* 26981 */ GIR_RootConstrainSelectedInstOperands,
10726 /* 26982 */ // GIR_Coverage, 847,
10727 /* 26982 */ GIR_EraseRootFromParent_Done,
10728 /* 26983 */ // Label 798: @26983
10729 /* 26983 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(27028), // Rule ID 864 //
10730 /* 26988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10731 /* 26991 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_b),
10732 /* 26996 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10733 /* 26999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10734 /* 27002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10735 /* 27005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10736 /* 27009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10737 /* 27013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10738 /* 27017 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8022:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10739 /* 27017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_B),
10740 /* 27020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10741 /* 27022 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10742 /* 27024 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10743 /* 27026 */ GIR_RootConstrainSelectedInstOperands,
10744 /* 27027 */ // GIR_Coverage, 864,
10745 /* 27027 */ GIR_EraseRootFromParent_Done,
10746 /* 27028 */ // Label 799: @27028
10747 /* 27028 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(27073), // Rule ID 865 //
10748 /* 27033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10749 /* 27036 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_h),
10750 /* 27041 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10751 /* 27044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10752 /* 27047 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10753 /* 27050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10754 /* 27054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10755 /* 27058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10756 /* 27062 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8024:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10757 /* 27062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_H),
10758 /* 27065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10759 /* 27067 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10760 /* 27069 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10761 /* 27071 */ GIR_RootConstrainSelectedInstOperands,
10762 /* 27072 */ // GIR_Coverage, 865,
10763 /* 27072 */ GIR_EraseRootFromParent_Done,
10764 /* 27073 */ // Label 800: @27073
10765 /* 27073 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(27118), // Rule ID 866 //
10766 /* 27078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10767 /* 27081 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_w),
10768 /* 27086 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10769 /* 27089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10770 /* 27092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10771 /* 27095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10772 /* 27099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10773 /* 27103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10774 /* 27107 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8025:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10775 /* 27107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_W),
10776 /* 27110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10777 /* 27112 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10778 /* 27114 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10779 /* 27116 */ GIR_RootConstrainSelectedInstOperands,
10780 /* 27117 */ // GIR_Coverage, 866,
10781 /* 27117 */ GIR_EraseRootFromParent_Done,
10782 /* 27118 */ // Label 801: @27118
10783 /* 27118 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(27163), // Rule ID 867 //
10784 /* 27123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10785 /* 27126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_d),
10786 /* 27131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10787 /* 27134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10788 /* 27137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10789 /* 27140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10790 /* 27144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10791 /* 27148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10792 /* 27152 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8023:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10793 /* 27152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_D),
10794 /* 27155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10795 /* 27157 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10796 /* 27159 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10797 /* 27161 */ GIR_RootConstrainSelectedInstOperands,
10798 /* 27162 */ // GIR_Coverage, 867,
10799 /* 27162 */ GIR_EraseRootFromParent_Done,
10800 /* 27163 */ // Label 802: @27163
10801 /* 27163 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(27208), // Rule ID 900 //
10802 /* 27168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10803 /* 27171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
10804 /* 27176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10805 /* 27179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10806 /* 27182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10807 /* 27185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10808 /* 27189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10809 /* 27193 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10810 /* 27197 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8064:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10811 /* 27197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_H),
10812 /* 27200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10813 /* 27202 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10814 /* 27204 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10815 /* 27206 */ GIR_RootConstrainSelectedInstOperands,
10816 /* 27207 */ // GIR_Coverage, 900,
10817 /* 27207 */ GIR_EraseRootFromParent_Done,
10818 /* 27208 */ // Label 803: @27208
10819 /* 27208 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(27253), // Rule ID 901 //
10820 /* 27213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10821 /* 27216 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
10822 /* 27221 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10823 /* 27224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10824 /* 27227 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10825 /* 27230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10826 /* 27234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10827 /* 27238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10828 /* 27242 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8065:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10829 /* 27242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_W),
10830 /* 27245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10831 /* 27247 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10832 /* 27249 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10833 /* 27251 */ GIR_RootConstrainSelectedInstOperands,
10834 /* 27252 */ // GIR_Coverage, 901,
10835 /* 27252 */ GIR_EraseRootFromParent_Done,
10836 /* 27253 */ // Label 804: @27253
10837 /* 27253 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(27298), // Rule ID 902 //
10838 /* 27258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10839 /* 27261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
10840 /* 27266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10841 /* 27269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10842 /* 27272 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10843 /* 27275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10844 /* 27279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10845 /* 27283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10846 /* 27287 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8075:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10847 /* 27287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_H),
10848 /* 27290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10849 /* 27292 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10850 /* 27294 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10851 /* 27296 */ GIR_RootConstrainSelectedInstOperands,
10852 /* 27297 */ // GIR_Coverage, 902,
10853 /* 27297 */ GIR_EraseRootFromParent_Done,
10854 /* 27298 */ // Label 805: @27298
10855 /* 27298 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(27343), // Rule ID 903 //
10856 /* 27303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10857 /* 27306 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
10858 /* 27311 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10859 /* 27314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10860 /* 27317 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10861 /* 27320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10862 /* 27324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10863 /* 27328 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10864 /* 27332 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8076:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10865 /* 27332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_W),
10866 /* 27335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10867 /* 27337 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10868 /* 27339 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10869 /* 27341 */ GIR_RootConstrainSelectedInstOperands,
10870 /* 27342 */ // GIR_Coverage, 903,
10871 /* 27342 */ GIR_EraseRootFromParent_Done,
10872 /* 27343 */ // Label 806: @27343
10873 /* 27343 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(27388), // Rule ID 981 //
10874 /* 27348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10875 /* 27351 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_b),
10876 /* 27356 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10877 /* 27359 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10878 /* 27362 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10879 /* 27365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10880 /* 27369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10881 /* 27373 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10882 /* 27377 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8189:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10883 /* 27377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_B),
10884 /* 27380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10885 /* 27382 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10886 /* 27384 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10887 /* 27386 */ GIR_RootConstrainSelectedInstOperands,
10888 /* 27387 */ // GIR_Coverage, 981,
10889 /* 27387 */ GIR_EraseRootFromParent_Done,
10890 /* 27388 */ // Label 807: @27388
10891 /* 27388 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(27433), // Rule ID 982 //
10892 /* 27393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10893 /* 27396 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_h),
10894 /* 27401 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10895 /* 27404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10896 /* 27407 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10897 /* 27410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10898 /* 27414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10899 /* 27418 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10900 /* 27422 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8191:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10901 /* 27422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_H),
10902 /* 27425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10903 /* 27427 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10904 /* 27429 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10905 /* 27431 */ GIR_RootConstrainSelectedInstOperands,
10906 /* 27432 */ // GIR_Coverage, 982,
10907 /* 27432 */ GIR_EraseRootFromParent_Done,
10908 /* 27433 */ // Label 808: @27433
10909 /* 27433 */ GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(27478), // Rule ID 983 //
10910 /* 27438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10911 /* 27441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_w),
10912 /* 27446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10913 /* 27449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10914 /* 27452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10915 /* 27455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10916 /* 27459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10917 /* 27463 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10918 /* 27467 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8192:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10919 /* 27467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_W),
10920 /* 27470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10921 /* 27472 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10922 /* 27474 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10923 /* 27476 */ GIR_RootConstrainSelectedInstOperands,
10924 /* 27477 */ // GIR_Coverage, 983,
10925 /* 27477 */ GIR_EraseRootFromParent_Done,
10926 /* 27478 */ // Label 809: @27478
10927 /* 27478 */ GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(27523), // Rule ID 984 //
10928 /* 27483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10929 /* 27486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_d),
10930 /* 27491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10931 /* 27494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10932 /* 27497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10933 /* 27500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10934 /* 27504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10935 /* 27508 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10936 /* 27512 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8190:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10937 /* 27512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_D),
10938 /* 27515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10939 /* 27517 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10940 /* 27519 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10941 /* 27521 */ GIR_RootConstrainSelectedInstOperands,
10942 /* 27522 */ // GIR_Coverage, 984,
10943 /* 27522 */ GIR_EraseRootFromParent_Done,
10944 /* 27523 */ // Label 810: @27523
10945 /* 27523 */ GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(27568), // Rule ID 997 //
10946 /* 27528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10947 /* 27531 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_b),
10948 /* 27536 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10949 /* 27539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10950 /* 27542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10951 /* 27545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10952 /* 27549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10953 /* 27553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10954 /* 27557 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8205:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10955 /* 27557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_B),
10956 /* 27560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10957 /* 27562 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10958 /* 27564 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10959 /* 27566 */ GIR_RootConstrainSelectedInstOperands,
10960 /* 27567 */ // GIR_Coverage, 997,
10961 /* 27567 */ GIR_EraseRootFromParent_Done,
10962 /* 27568 */ // Label 811: @27568
10963 /* 27568 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(27613), // Rule ID 998 //
10964 /* 27573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10965 /* 27576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_h),
10966 /* 27581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10967 /* 27584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10968 /* 27587 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10969 /* 27590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10970 /* 27594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10971 /* 27598 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10972 /* 27602 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8207:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10973 /* 27602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_H),
10974 /* 27605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10975 /* 27607 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10976 /* 27609 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10977 /* 27611 */ GIR_RootConstrainSelectedInstOperands,
10978 /* 27612 */ // GIR_Coverage, 998,
10979 /* 27612 */ GIR_EraseRootFromParent_Done,
10980 /* 27613 */ // Label 812: @27613
10981 /* 27613 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(27658), // Rule ID 999 //
10982 /* 27618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10983 /* 27621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_w),
10984 /* 27626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10985 /* 27629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10986 /* 27632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10987 /* 27635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10988 /* 27639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10989 /* 27643 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10990 /* 27647 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8208:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10991 /* 27647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_W),
10992 /* 27650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10993 /* 27652 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10994 /* 27654 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10995 /* 27656 */ GIR_RootConstrainSelectedInstOperands,
10996 /* 27657 */ // GIR_Coverage, 999,
10997 /* 27657 */ GIR_EraseRootFromParent_Done,
10998 /* 27658 */ // Label 813: @27658
10999 /* 27658 */ GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(27703), // Rule ID 1000 //
11000 /* 27663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11001 /* 27666 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_d),
11002 /* 27671 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11003 /* 27674 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11004 /* 27677 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11005 /* 27680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11006 /* 27684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11007 /* 27688 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11008 /* 27692 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8206:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11009 /* 27692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_D),
11010 /* 27695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11011 /* 27697 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11012 /* 27699 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11013 /* 27701 */ GIR_RootConstrainSelectedInstOperands,
11014 /* 27702 */ // GIR_Coverage, 1000,
11015 /* 27702 */ GIR_EraseRootFromParent_Done,
11016 /* 27703 */ // Label 814: @27703
11017 /* 27703 */ GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(27748), // Rule ID 1009 //
11018 /* 27708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11019 /* 27711 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
11020 /* 27716 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11021 /* 27719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11022 /* 27722 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11023 /* 27725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11024 /* 27729 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11025 /* 27733 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11026 /* 27737 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8226:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11027 /* 27737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_B),
11028 /* 27740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11029 /* 27742 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11030 /* 27744 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11031 /* 27746 */ GIR_RootConstrainSelectedInstOperands,
11032 /* 27747 */ // GIR_Coverage, 1009,
11033 /* 27747 */ GIR_EraseRootFromParent_Done,
11034 /* 27748 */ // Label 815: @27748
11035 /* 27748 */ GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(27793), // Rule ID 1010 //
11036 /* 27753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11037 /* 27756 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
11038 /* 27761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11039 /* 27764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11040 /* 27767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11041 /* 27770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11042 /* 27774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11043 /* 27778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11044 /* 27782 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8228:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11045 /* 27782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_H),
11046 /* 27785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11047 /* 27787 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11048 /* 27789 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11049 /* 27791 */ GIR_RootConstrainSelectedInstOperands,
11050 /* 27792 */ // GIR_Coverage, 1010,
11051 /* 27792 */ GIR_EraseRootFromParent_Done,
11052 /* 27793 */ // Label 816: @27793
11053 /* 27793 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(27838), // Rule ID 1011 //
11054 /* 27798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11055 /* 27801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
11056 /* 27806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11057 /* 27809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11058 /* 27812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11059 /* 27815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11060 /* 27819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11061 /* 27823 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11062 /* 27827 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8229:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11063 /* 27827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_W),
11064 /* 27830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11065 /* 27832 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11066 /* 27834 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11067 /* 27836 */ GIR_RootConstrainSelectedInstOperands,
11068 /* 27837 */ // GIR_Coverage, 1011,
11069 /* 27837 */ GIR_EraseRootFromParent_Done,
11070 /* 27838 */ // Label 817: @27838
11071 /* 27838 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(27883), // Rule ID 1012 //
11072 /* 27843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11073 /* 27846 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
11074 /* 27851 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11075 /* 27854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11076 /* 27857 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11077 /* 27860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11078 /* 27864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11079 /* 27868 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11080 /* 27872 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8227:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11081 /* 27872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_D),
11082 /* 27875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11083 /* 27877 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11084 /* 27879 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11085 /* 27881 */ GIR_RootConstrainSelectedInstOperands,
11086 /* 27882 */ // GIR_Coverage, 1012,
11087 /* 27882 */ GIR_EraseRootFromParent_Done,
11088 /* 27883 */ // Label 818: @27883
11089 /* 27883 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(27928), // Rule ID 1013 //
11090 /* 27888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11091 /* 27891 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
11092 /* 27896 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11093 /* 27899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11094 /* 27902 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11095 /* 27905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11096 /* 27909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11097 /* 27913 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11098 /* 27917 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8230:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11099 /* 27917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_B),
11100 /* 27920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11101 /* 27922 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11102 /* 27924 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11103 /* 27926 */ GIR_RootConstrainSelectedInstOperands,
11104 /* 27927 */ // GIR_Coverage, 1013,
11105 /* 27927 */ GIR_EraseRootFromParent_Done,
11106 /* 27928 */ // Label 819: @27928
11107 /* 27928 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(27973), // Rule ID 1014 //
11108 /* 27933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11109 /* 27936 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
11110 /* 27941 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11111 /* 27944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11112 /* 27947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11113 /* 27950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11114 /* 27954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11115 /* 27958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11116 /* 27962 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8232:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11117 /* 27962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_H),
11118 /* 27965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11119 /* 27967 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11120 /* 27969 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11121 /* 27971 */ GIR_RootConstrainSelectedInstOperands,
11122 /* 27972 */ // GIR_Coverage, 1014,
11123 /* 27972 */ GIR_EraseRootFromParent_Done,
11124 /* 27973 */ // Label 820: @27973
11125 /* 27973 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(28018), // Rule ID 1015 //
11126 /* 27978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11127 /* 27981 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
11128 /* 27986 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11129 /* 27989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11130 /* 27992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11131 /* 27995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11132 /* 27999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11133 /* 28003 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11134 /* 28007 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8233:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11135 /* 28007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_W),
11136 /* 28010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11137 /* 28012 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11138 /* 28014 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11139 /* 28016 */ GIR_RootConstrainSelectedInstOperands,
11140 /* 28017 */ // GIR_Coverage, 1015,
11141 /* 28017 */ GIR_EraseRootFromParent_Done,
11142 /* 28018 */ // Label 821: @28018
11143 /* 28018 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(28063), // Rule ID 1016 //
11144 /* 28023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11145 /* 28026 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
11146 /* 28031 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11147 /* 28034 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11148 /* 28037 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11149 /* 28040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11150 /* 28044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11151 /* 28048 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11152 /* 28052 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8231:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11153 /* 28052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_D),
11154 /* 28055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11155 /* 28057 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11156 /* 28059 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11157 /* 28061 */ GIR_RootConstrainSelectedInstOperands,
11158 /* 28062 */ // GIR_Coverage, 1016,
11159 /* 28062 */ GIR_EraseRootFromParent_Done,
11160 /* 28063 */ // Label 822: @28063
11161 /* 28063 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(28108), // Rule ID 1017 //
11162 /* 28068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11163 /* 28071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
11164 /* 28076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11165 /* 28079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11166 /* 28082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11167 /* 28085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11168 /* 28089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11169 /* 28093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11170 /* 28097 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8234:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11171 /* 28097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_B),
11172 /* 28100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11173 /* 28102 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11174 /* 28104 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11175 /* 28106 */ GIR_RootConstrainSelectedInstOperands,
11176 /* 28107 */ // GIR_Coverage, 1017,
11177 /* 28107 */ GIR_EraseRootFromParent_Done,
11178 /* 28108 */ // Label 823: @28108
11179 /* 28108 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(28153), // Rule ID 1018 //
11180 /* 28113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11181 /* 28116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
11182 /* 28121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11183 /* 28124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11184 /* 28127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11185 /* 28130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11186 /* 28134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11187 /* 28138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11188 /* 28142 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8236:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11189 /* 28142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_H),
11190 /* 28145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11191 /* 28147 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11192 /* 28149 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11193 /* 28151 */ GIR_RootConstrainSelectedInstOperands,
11194 /* 28152 */ // GIR_Coverage, 1018,
11195 /* 28152 */ GIR_EraseRootFromParent_Done,
11196 /* 28153 */ // Label 824: @28153
11197 /* 28153 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(28198), // Rule ID 1019 //
11198 /* 28158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11199 /* 28161 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
11200 /* 28166 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11201 /* 28169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11202 /* 28172 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11203 /* 28175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11204 /* 28179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11205 /* 28183 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11206 /* 28187 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8237:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11207 /* 28187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_W),
11208 /* 28190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11209 /* 28192 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11210 /* 28194 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11211 /* 28196 */ GIR_RootConstrainSelectedInstOperands,
11212 /* 28197 */ // GIR_Coverage, 1019,
11213 /* 28197 */ GIR_EraseRootFromParent_Done,
11214 /* 28198 */ // Label 825: @28198
11215 /* 28198 */ GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(28243), // Rule ID 1020 //
11216 /* 28203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11217 /* 28206 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
11218 /* 28211 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11219 /* 28214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11220 /* 28217 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11221 /* 28220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11222 /* 28224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11223 /* 28228 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11224 /* 28232 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8235:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11225 /* 28232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_D),
11226 /* 28235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11227 /* 28237 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11228 /* 28239 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11229 /* 28241 */ GIR_RootConstrainSelectedInstOperands,
11230 /* 28242 */ // GIR_Coverage, 1020,
11231 /* 28242 */ GIR_EraseRootFromParent_Done,
11232 /* 28243 */ // Label 826: @28243
11233 /* 28243 */ GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(28288), // Rule ID 1021 //
11234 /* 28248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11235 /* 28251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
11236 /* 28256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11237 /* 28259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11238 /* 28262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11239 /* 28265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11240 /* 28269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11241 /* 28273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11242 /* 28277 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8238:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11243 /* 28277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_B),
11244 /* 28280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11245 /* 28282 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11246 /* 28284 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11247 /* 28286 */ GIR_RootConstrainSelectedInstOperands,
11248 /* 28287 */ // GIR_Coverage, 1021,
11249 /* 28287 */ GIR_EraseRootFromParent_Done,
11250 /* 28288 */ // Label 827: @28288
11251 /* 28288 */ GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(28333), // Rule ID 1022 //
11252 /* 28293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11253 /* 28296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
11254 /* 28301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11255 /* 28304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11256 /* 28307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11257 /* 28310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11258 /* 28314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11259 /* 28318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11260 /* 28322 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8240:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11261 /* 28322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_H),
11262 /* 28325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11263 /* 28327 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11264 /* 28329 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11265 /* 28331 */ GIR_RootConstrainSelectedInstOperands,
11266 /* 28332 */ // GIR_Coverage, 1022,
11267 /* 28332 */ GIR_EraseRootFromParent_Done,
11268 /* 28333 */ // Label 828: @28333
11269 /* 28333 */ GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(28378), // Rule ID 1023 //
11270 /* 28338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11271 /* 28341 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
11272 /* 28346 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11273 /* 28349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11274 /* 28352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11275 /* 28355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11276 /* 28359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11277 /* 28363 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11278 /* 28367 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8241:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11279 /* 28367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_W),
11280 /* 28370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11281 /* 28372 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11282 /* 28374 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11283 /* 28376 */ GIR_RootConstrainSelectedInstOperands,
11284 /* 28377 */ // GIR_Coverage, 1023,
11285 /* 28377 */ GIR_EraseRootFromParent_Done,
11286 /* 28378 */ // Label 829: @28378
11287 /* 28378 */ GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(28423), // Rule ID 1024 //
11288 /* 28383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11289 /* 28386 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
11290 /* 28391 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11291 /* 28394 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11292 /* 28397 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11293 /* 28400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11294 /* 28404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11295 /* 28408 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11296 /* 28412 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8239:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11297 /* 28412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_D),
11298 /* 28415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11299 /* 28417 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11300 /* 28419 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11301 /* 28421 */ GIR_RootConstrainSelectedInstOperands,
11302 /* 28422 */ // GIR_Coverage, 1024,
11303 /* 28422 */ GIR_EraseRootFromParent_Done,
11304 /* 28423 */ // Label 830: @28423
11305 /* 28423 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(28471), // Rule ID 1223 //
11306 /* 28428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11307 /* 28431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
11308 /* 28436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11309 /* 28439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11310 /* 28442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11311 /* 28445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11312 /* 28449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11313 /* 28453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11314 /* 28457 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7600:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11315 /* 28457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
11316 /* 28460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11317 /* 28462 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11318 /* 28464 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11319 /* 28466 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11320 /* 28469 */ GIR_RootConstrainSelectedInstOperands,
11321 /* 28470 */ // GIR_Coverage, 1223,
11322 /* 28470 */ GIR_EraseRootFromParent_Done,
11323 /* 28471 */ // Label 831: @28471
11324 /* 28471 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(28519), // Rule ID 1225 //
11325 /* 28476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11326 /* 28479 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
11327 /* 28484 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11328 /* 28487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11329 /* 28490 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11330 /* 28493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11331 /* 28497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11332 /* 28501 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11333 /* 28505 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7622:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11334 /* 28505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB_MM),
11335 /* 28508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11336 /* 28510 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11337 /* 28512 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11338 /* 28514 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11339 /* 28517 */ GIR_RootConstrainSelectedInstOperands,
11340 /* 28518 */ // GIR_Coverage, 1225,
11341 /* 28518 */ GIR_EraseRootFromParent_Done,
11342 /* 28519 */ // Label 832: @28519
11343 /* 28519 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(28564), // Rule ID 1246 //
11344 /* 28524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11345 /* 28527 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
11346 /* 28532 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11347 /* 28535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11348 /* 28538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11349 /* 28541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11350 /* 28545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11351 /* 28549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11352 /* 28553 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8150:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11353 /* 28553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH_MM),
11354 /* 28556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11355 /* 28558 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11356 /* 28560 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11357 /* 28562 */ GIR_RootConstrainSelectedInstOperands,
11358 /* 28563 */ // GIR_Coverage, 1246,
11359 /* 28563 */ GIR_EraseRootFromParent_Done,
11360 /* 28564 */ // Label 833: @28564
11361 /* 28564 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(28609), // Rule ID 1247 //
11362 /* 28569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11363 /* 28572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
11364 /* 28577 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11365 /* 28580 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11366 /* 28583 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11367 /* 28586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11368 /* 28590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11369 /* 28594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11370 /* 28598 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8152:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11371 /* 28598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
11372 /* 28601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11373 /* 28603 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11374 /* 28605 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11375 /* 28607 */ GIR_RootConstrainSelectedInstOperands,
11376 /* 28608 */ // GIR_Coverage, 1247,
11377 /* 28608 */ GIR_EraseRootFromParent_Done,
11378 /* 28609 */ // Label 834: @28609
11379 /* 28609 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(28654), // Rule ID 1248 //
11380 /* 28614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11381 /* 28617 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
11382 /* 28622 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11383 /* 28625 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11384 /* 28628 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11385 /* 28631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11386 /* 28635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11387 /* 28639 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11388 /* 28643 */ // (intrinsic_wo_chain:{ *:[i32] } 8154:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11389 /* 28643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W_MM),
11390 /* 28646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11391 /* 28648 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11392 /* 28650 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11393 /* 28652 */ GIR_RootConstrainSelectedInstOperands,
11394 /* 28653 */ // GIR_Coverage, 1248,
11395 /* 28653 */ GIR_EraseRootFromParent_Done,
11396 /* 28654 */ // Label 835: @28654
11397 /* 28654 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(28699), // Rule ID 1250 //
11398 /* 28659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11399 /* 28662 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
11400 /* 28667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11401 /* 28670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11402 /* 28673 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11403 /* 28676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11404 /* 28680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11405 /* 28684 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11406 /* 28688 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8156:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11407 /* 28688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB_MM),
11408 /* 28691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11409 /* 28693 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11410 /* 28695 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11411 /* 28697 */ GIR_RootConstrainSelectedInstOperands,
11412 /* 28698 */ // GIR_Coverage, 1250,
11413 /* 28698 */ GIR_EraseRootFromParent_Done,
11414 /* 28699 */ // Label 836: @28699
11415 /* 28699 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(28747), // Rule ID 1261 //
11416 /* 28704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11417 /* 28707 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
11418 /* 28712 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11419 /* 28715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11420 /* 28718 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11421 /* 28721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11422 /* 28725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11423 /* 28729 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11424 /* 28733 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8220:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11425 /* 28733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
11426 /* 28736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11427 /* 28738 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11428 /* 28740 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11429 /* 28742 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11430 /* 28745 */ GIR_RootConstrainSelectedInstOperands,
11431 /* 28746 */ // GIR_Coverage, 1261,
11432 /* 28746 */ GIR_EraseRootFromParent_Done,
11433 /* 28747 */ // Label 837: @28747
11434 /* 28747 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(28795), // Rule ID 1263 //
11435 /* 28752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11436 /* 28755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
11437 /* 28760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11438 /* 28763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11439 /* 28766 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11440 /* 28769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11441 /* 28773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11442 /* 28777 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11443 /* 28781 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8245:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11444 /* 28781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB_MM),
11445 /* 28784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11446 /* 28786 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11447 /* 28788 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11448 /* 28790 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11449 /* 28793 */ GIR_RootConstrainSelectedInstOperands,
11450 /* 28794 */ // GIR_Coverage, 1263,
11451 /* 28794 */ GIR_EraseRootFromParent_Done,
11452 /* 28795 */ // Label 838: @28795
11453 /* 28795 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(28840), // Rule ID 1273 //
11454 /* 28800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11455 /* 28803 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
11456 /* 28808 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11457 /* 28811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11458 /* 28814 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11459 /* 28817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11460 /* 28821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11461 /* 28825 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11462 /* 28829 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8125:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11463 /* 28829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
11464 /* 28832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11465 /* 28834 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11466 /* 28836 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11467 /* 28838 */ GIR_RootConstrainSelectedInstOperands,
11468 /* 28839 */ // GIR_Coverage, 1273,
11469 /* 28839 */ GIR_EraseRootFromParent_Done,
11470 /* 28840 */ // Label 839: @28840
11471 /* 28840 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(28885), // Rule ID 1274 //
11472 /* 28845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11473 /* 28848 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
11474 /* 28853 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11475 /* 28856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11476 /* 28859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11477 /* 28862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11478 /* 28866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11479 /* 28870 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11480 /* 28874 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8126:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11481 /* 28874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
11482 /* 28877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11483 /* 28879 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11484 /* 28881 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11485 /* 28883 */ GIR_RootConstrainSelectedInstOperands,
11486 /* 28884 */ // GIR_Coverage, 1274,
11487 /* 28884 */ GIR_EraseRootFromParent_Done,
11488 /* 28885 */ // Label 840: @28885
11489 /* 28885 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(28930), // Rule ID 1293 //
11490 /* 28890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11491 /* 28893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
11492 /* 28898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11493 /* 28901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11494 /* 28904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11495 /* 28907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11496 /* 28911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11497 /* 28915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11498 /* 28919 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8097:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11499 /* 28919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH_MM),
11500 /* 28922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11501 /* 28924 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11502 /* 28926 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11503 /* 28928 */ GIR_RootConstrainSelectedInstOperands,
11504 /* 28929 */ // GIR_Coverage, 1293,
11505 /* 28929 */ GIR_EraseRootFromParent_Done,
11506 /* 28930 */ // Label 841: @28930
11507 /* 28930 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(28975), // Rule ID 1299 //
11508 /* 28935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
11509 /* 28938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
11510 /* 28943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11511 /* 28946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11512 /* 28949 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11513 /* 28952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11514 /* 28956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11515 /* 28960 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11516 /* 28964 */ // (intrinsic_wo_chain:{ *:[i32] } 8050:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11517 /* 28964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB_MM),
11518 /* 28967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11519 /* 28969 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11520 /* 28971 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11521 /* 28973 */ GIR_RootConstrainSelectedInstOperands,
11522 /* 28974 */ // GIR_Coverage, 1299,
11523 /* 28974 */ GIR_EraseRootFromParent_Done,
11524 /* 28975 */ // Label 842: @28975
11525 /* 28975 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(29020), // Rule ID 1312 //
11526 /* 28980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11527 /* 28983 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
11528 /* 28988 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11529 /* 28991 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11530 /* 28994 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11531 /* 28997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11532 /* 29001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11533 /* 29005 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11534 /* 29009 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7602:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11535 /* 29009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
11536 /* 29012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11537 /* 29014 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11538 /* 29016 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11539 /* 29018 */ GIR_RootConstrainSelectedInstOperands,
11540 /* 29019 */ // GIR_Coverage, 1312,
11541 /* 29019 */ GIR_EraseRootFromParent_Done,
11542 /* 29020 */ // Label 843: @29020
11543 /* 29020 */ GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(29065), // Rule ID 1313 //
11544 /* 29025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11545 /* 29028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
11546 /* 29033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11547 /* 29036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11548 /* 29039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11549 /* 29042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11550 /* 29046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11551 /* 29050 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11552 /* 29054 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7603:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11553 /* 29054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
11554 /* 29057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11555 /* 29059 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11556 /* 29061 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11557 /* 29063 */ GIR_RootConstrainSelectedInstOperands,
11558 /* 29064 */ // GIR_Coverage, 1313,
11559 /* 29064 */ GIR_EraseRootFromParent_Done,
11560 /* 29065 */ // Label 844: @29065
11561 /* 29065 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(29110), // Rule ID 1314 //
11562 /* 29070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11563 /* 29073 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
11564 /* 29078 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11565 /* 29081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11566 /* 29084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11567 /* 29087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11568 /* 29091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11569 /* 29095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11570 /* 29099 */ // (intrinsic_wo_chain:{ *:[i32] } 7605:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11571 /* 29099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W_MMR2),
11572 /* 29102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11573 /* 29104 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11574 /* 29106 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11575 /* 29108 */ GIR_RootConstrainSelectedInstOperands,
11576 /* 29109 */ // GIR_Coverage, 1314,
11577 /* 29109 */ GIR_EraseRootFromParent_Done,
11578 /* 29110 */ // Label 845: @29110
11579 /* 29110 */ GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(29155), // Rule ID 1315 //
11580 /* 29115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11581 /* 29118 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
11582 /* 29123 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11583 /* 29126 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11584 /* 29129 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11585 /* 29132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11586 /* 29136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11587 /* 29140 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11588 /* 29144 */ // (intrinsic_wo_chain:{ *:[i32] } 7604:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11589 /* 29144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
11590 /* 29147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11591 /* 29149 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11592 /* 29151 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11593 /* 29153 */ GIR_RootConstrainSelectedInstOperands,
11594 /* 29154 */ // GIR_Coverage, 1315,
11595 /* 29154 */ GIR_EraseRootFromParent_Done,
11596 /* 29155 */ // Label 846: @29155
11597 /* 29155 */ GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(29200), // Rule ID 1318 //
11598 /* 29160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11599 /* 29163 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
11600 /* 29168 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11601 /* 29171 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11602 /* 29174 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11603 /* 29177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11604 /* 29181 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11605 /* 29185 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11606 /* 29189 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7623:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11607 /* 29189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
11608 /* 29192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11609 /* 29194 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11610 /* 29196 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11611 /* 29198 */ GIR_RootConstrainSelectedInstOperands,
11612 /* 29199 */ // GIR_Coverage, 1318,
11613 /* 29199 */ GIR_EraseRootFromParent_Done,
11614 /* 29200 */ // Label 847: @29200
11615 /* 29200 */ GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(29245), // Rule ID 1319 //
11616 /* 29205 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11617 /* 29208 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
11618 /* 29213 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11619 /* 29216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11620 /* 29219 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11621 /* 29222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11622 /* 29226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11623 /* 29230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11624 /* 29234 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7624:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11625 /* 29234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
11626 /* 29237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11627 /* 29239 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11628 /* 29241 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11629 /* 29243 */ GIR_RootConstrainSelectedInstOperands,
11630 /* 29244 */ // GIR_Coverage, 1319,
11631 /* 29244 */ GIR_EraseRootFromParent_Done,
11632 /* 29245 */ // Label 848: @29245
11633 /* 29245 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(29290), // Rule ID 1325 //
11634 /* 29250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11635 /* 29253 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
11636 /* 29258 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11637 /* 29261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11638 /* 29264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11639 /* 29267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11640 /* 29271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11641 /* 29275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11642 /* 29279 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8151:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11643 /* 29279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
11644 /* 29282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11645 /* 29284 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11646 /* 29286 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11647 /* 29288 */ GIR_RootConstrainSelectedInstOperands,
11648 /* 29289 */ // GIR_Coverage, 1325,
11649 /* 29289 */ GIR_EraseRootFromParent_Done,
11650 /* 29290 */ // Label 849: @29290
11651 /* 29290 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(29335), // Rule ID 1326 //
11652 /* 29295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11653 /* 29298 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
11654 /* 29303 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11655 /* 29306 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11656 /* 29309 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11657 /* 29312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11658 /* 29316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11659 /* 29320 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11660 /* 29324 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8153:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11661 /* 29324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
11662 /* 29327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11663 /* 29329 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11664 /* 29331 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11665 /* 29333 */ GIR_RootConstrainSelectedInstOperands,
11666 /* 29334 */ // GIR_Coverage, 1326,
11667 /* 29334 */ GIR_EraseRootFromParent_Done,
11668 /* 29335 */ // Label 850: @29335
11669 /* 29335 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(29380), // Rule ID 1331 //
11670 /* 29340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11671 /* 29343 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
11672 /* 29348 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11673 /* 29351 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11674 /* 29354 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11675 /* 29357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11676 /* 29361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11677 /* 29365 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11678 /* 29369 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8155:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11679 /* 29369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
11680 /* 29372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11681 /* 29374 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11682 /* 29376 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11683 /* 29378 */ GIR_RootConstrainSelectedInstOperands,
11684 /* 29379 */ // GIR_Coverage, 1331,
11685 /* 29379 */ GIR_EraseRootFromParent_Done,
11686 /* 29380 */ // Label 851: @29380
11687 /* 29380 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(29425), // Rule ID 1332 //
11688 /* 29385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11689 /* 29388 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
11690 /* 29393 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11691 /* 29396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11692 /* 29399 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11693 /* 29402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11694 /* 29406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11695 /* 29410 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11696 /* 29414 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8222:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11697 /* 29414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
11698 /* 29417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11699 /* 29419 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11700 /* 29421 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11701 /* 29423 */ GIR_RootConstrainSelectedInstOperands,
11702 /* 29424 */ // GIR_Coverage, 1332,
11703 /* 29424 */ GIR_EraseRootFromParent_Done,
11704 /* 29425 */ // Label 852: @29425
11705 /* 29425 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(29470), // Rule ID 1333 //
11706 /* 29430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11707 /* 29433 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
11708 /* 29438 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11709 /* 29441 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11710 /* 29444 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11711 /* 29447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11712 /* 29451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11713 /* 29455 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11714 /* 29459 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8223:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11715 /* 29459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
11716 /* 29462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11717 /* 29464 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11718 /* 29466 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11719 /* 29468 */ GIR_RootConstrainSelectedInstOperands,
11720 /* 29469 */ // GIR_Coverage, 1333,
11721 /* 29469 */ GIR_EraseRootFromParent_Done,
11722 /* 29470 */ // Label 853: @29470
11723 /* 29470 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(29515), // Rule ID 1334 //
11724 /* 29475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11725 /* 29478 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
11726 /* 29483 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11727 /* 29486 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11728 /* 29489 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11729 /* 29492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11730 /* 29496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11731 /* 29500 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11732 /* 29504 */ // (intrinsic_wo_chain:{ *:[i32] } 8225:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11733 /* 29504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W_MMR2),
11734 /* 29507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11735 /* 29509 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11736 /* 29511 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11737 /* 29513 */ GIR_RootConstrainSelectedInstOperands,
11738 /* 29514 */ // GIR_Coverage, 1334,
11739 /* 29514 */ GIR_EraseRootFromParent_Done,
11740 /* 29515 */ // Label 854: @29515
11741 /* 29515 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(29560), // Rule ID 1335 //
11742 /* 29520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11743 /* 29523 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
11744 /* 29528 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11745 /* 29531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11746 /* 29534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11747 /* 29537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11748 /* 29541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11749 /* 29545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11750 /* 29549 */ // (intrinsic_wo_chain:{ *:[i32] } 8224:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11751 /* 29549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
11752 /* 29552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11753 /* 29554 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11754 /* 29556 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11755 /* 29558 */ GIR_RootConstrainSelectedInstOperands,
11756 /* 29559 */ // GIR_Coverage, 1335,
11757 /* 29559 */ GIR_EraseRootFromParent_Done,
11758 /* 29560 */ // Label 855: @29560
11759 /* 29560 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(29605), // Rule ID 1338 //
11760 /* 29565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11761 /* 29568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
11762 /* 29573 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11763 /* 29576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11764 /* 29579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11765 /* 29582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11766 /* 29586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11767 /* 29590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11768 /* 29594 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8246:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11769 /* 29594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
11770 /* 29597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11771 /* 29599 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11772 /* 29601 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11773 /* 29603 */ GIR_RootConstrainSelectedInstOperands,
11774 /* 29604 */ // GIR_Coverage, 1338,
11775 /* 29604 */ GIR_EraseRootFromParent_Done,
11776 /* 29605 */ // Label 856: @29605
11777 /* 29605 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(29650), // Rule ID 1339 //
11778 /* 29610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11779 /* 29613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
11780 /* 29618 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11781 /* 29621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11782 /* 29624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11783 /* 29627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11784 /* 29631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11785 /* 29635 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11786 /* 29639 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8247:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11787 /* 29639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
11788 /* 29642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11789 /* 29644 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11790 /* 29646 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11791 /* 29648 */ GIR_RootConstrainSelectedInstOperands,
11792 /* 29649 */ // GIR_Coverage, 1339,
11793 /* 29649 */ GIR_EraseRootFromParent_Done,
11794 /* 29650 */ // Label 857: @29650
11795 /* 29650 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(29690), // Rule ID 1925 //
11796 /* 29655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
11797 /* 29658 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_ph),
11798 /* 29663 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11799 /* 29666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11800 /* 29669 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11801 /* 29672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11802 /* 29676 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7599:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
11803 /* 29676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
11804 /* 29679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11805 /* 29681 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11806 /* 29683 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11807 /* 29685 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11808 /* 29688 */ GIR_RootConstrainSelectedInstOperands,
11809 /* 29689 */ // GIR_Coverage, 1925,
11810 /* 29689 */ GIR_EraseRootFromParent_Done,
11811 /* 29690 */ // Label 858: @29690
11812 /* 29690 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(29730), // Rule ID 1927 //
11813 /* 29695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
11814 /* 29698 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_ph),
11815 /* 29703 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11816 /* 29706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11817 /* 29709 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11818 /* 29712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11819 /* 29716 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8219:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
11820 /* 29716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
11821 /* 29719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11822 /* 29721 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11823 /* 29723 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11824 /* 29725 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11825 /* 29728 */ GIR_RootConstrainSelectedInstOperands,
11826 /* 29729 */ // GIR_Coverage, 1927,
11827 /* 29729 */ GIR_EraseRootFromParent_Done,
11828 /* 29730 */ // Label 859: @29730
11829 /* 29730 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(29770), // Rule ID 1931 //
11830 /* 29735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
11831 /* 29738 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_qb),
11832 /* 29743 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11833 /* 29746 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11834 /* 29749 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11835 /* 29752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11836 /* 29756 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7620:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
11837 /* 29756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
11838 /* 29759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11839 /* 29761 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11840 /* 29763 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11841 /* 29765 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11842 /* 29768 */ GIR_RootConstrainSelectedInstOperands,
11843 /* 29769 */ // GIR_Coverage, 1931,
11844 /* 29769 */ GIR_EraseRootFromParent_Done,
11845 /* 29770 */ // Label 860: @29770
11846 /* 29770 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(29810), // Rule ID 1933 //
11847 /* 29775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
11848 /* 29778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_qb),
11849 /* 29783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11850 /* 29786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11851 /* 29789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11852 /* 29792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11853 /* 29796 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8243:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
11854 /* 29796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
11855 /* 29799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11856 /* 29801 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11857 /* 29803 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11858 /* 29805 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11859 /* 29808 */ GIR_RootConstrainSelectedInstOperands,
11860 /* 29809 */ // GIR_Coverage, 1933,
11861 /* 29809 */ GIR_EraseRootFromParent_Done,
11862 /* 29810 */ // Label 861: @29810
11863 /* 29810 */ GIM_Reject,
11864 /* 29811 */ // Label 647: @29811
11865 /* 29811 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(32325),
11866 /* 29816 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
11867 /* 29819 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(29874), // Rule ID 477 //
11868 /* 29824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11869 /* 29827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
11870 /* 29832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11871 /* 29835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11872 /* 29838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11873 /* 29841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11874 /* 29845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11875 /* 29849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11876 /* 29853 */ // MIs[0] sa
11877 /* 29853 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11878 /* 29856 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11879 /* 29861 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8123:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11880 /* 29861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
11881 /* 29864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11882 /* 29866 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11883 /* 29868 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11884 /* 29870 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11885 /* 29872 */ GIR_RootConstrainSelectedInstOperands,
11886 /* 29873 */ // GIR_Coverage, 477,
11887 /* 29873 */ GIR_EraseRootFromParent_Done,
11888 /* 29874 */ // Label 863: @29874
11889 /* 29874 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(29929), // Rule ID 478 //
11890 /* 29879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11891 /* 29882 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
11892 /* 29887 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11893 /* 29890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11894 /* 29893 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11895 /* 29896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11896 /* 29900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11897 /* 29904 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11898 /* 29908 */ // MIs[0] sa
11899 /* 29908 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11900 /* 29911 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11901 /* 29916 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8124:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11902 /* 29916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
11903 /* 29919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11904 /* 29921 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11905 /* 29923 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11906 /* 29925 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11907 /* 29927 */ GIR_RootConstrainSelectedInstOperands,
11908 /* 29928 */ // GIR_Coverage, 478,
11909 /* 29928 */ GIR_EraseRootFromParent_Done,
11910 /* 29929 */ // Label 864: @29929
11911 /* 29929 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(29984), // Rule ID 483 //
11912 /* 29934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11913 /* 29937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
11914 /* 29942 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11915 /* 29945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11916 /* 29948 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11917 /* 29951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11918 /* 29955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11919 /* 29959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11920 /* 29963 */ // MIs[0] sa
11921 /* 29963 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11922 /* 29966 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11923 /* 29971 */ // (intrinsic_wo_chain:{ *:[i32] } 7636:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11924 /* 29971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND),
11925 /* 29974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11926 /* 29976 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11927 /* 29978 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11928 /* 29980 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11929 /* 29982 */ GIR_RootConstrainSelectedInstOperands,
11930 /* 29983 */ // GIR_Coverage, 483,
11931 /* 29983 */ GIR_EraseRootFromParent_Done,
11932 /* 29984 */ // Label 865: @29984
11933 /* 29984 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(30039), // Rule ID 484 //
11934 /* 29989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11935 /* 29992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
11936 /* 29997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11937 /* 30000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11938 /* 30003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11939 /* 30006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11940 /* 30010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11941 /* 30014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11942 /* 30018 */ // MIs[0] sa
11943 /* 30018 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11944 /* 30021 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
11945 /* 30026 */ // (intrinsic_wo_chain:{ *:[i32] } 7661:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11946 /* 30026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN),
11947 /* 30029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11948 /* 30031 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11949 /* 30033 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11950 /* 30035 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11951 /* 30037 */ GIR_RootConstrainSelectedInstOperands,
11952 /* 30038 */ // GIR_Coverage, 484,
11953 /* 30038 */ GIR_EraseRootFromParent_Done,
11954 /* 30039 */ // Label 866: @30039
11955 /* 30039 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(30094), // Rule ID 485 //
11956 /* 30044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11957 /* 30047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
11958 /* 30052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11959 /* 30055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11960 /* 30058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11961 /* 30061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11962 /* 30065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11963 /* 30069 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11964 /* 30073 */ // MIs[0] sa
11965 /* 30073 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11966 /* 30076 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11967 /* 30081 */ // (intrinsic_wo_chain:{ *:[i32] } 8129:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11968 /* 30081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND),
11969 /* 30084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11970 /* 30086 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11971 /* 30088 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11972 /* 30090 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11973 /* 30092 */ GIR_RootConstrainSelectedInstOperands,
11974 /* 30093 */ // GIR_Coverage, 485,
11975 /* 30093 */ GIR_EraseRootFromParent_Done,
11976 /* 30094 */ // Label 867: @30094
11977 /* 30094 */ GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(30149), // Rule ID 953 //
11978 /* 30099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11979 /* 30102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_b),
11980 /* 30107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11981 /* 30110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11982 /* 30113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11983 /* 30116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11984 /* 30120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11985 /* 30124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11986 /* 30128 */ // MIs[0] n
11987 /* 30128 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11988 /* 30131 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
11989 /* 30136 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8161:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
11990 /* 30136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_B),
11991 /* 30139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11992 /* 30141 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11993 /* 30143 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
11994 /* 30145 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
11995 /* 30147 */ GIR_RootConstrainSelectedInstOperands,
11996 /* 30148 */ // GIR_Coverage, 953,
11997 /* 30148 */ GIR_EraseRootFromParent_Done,
11998 /* 30149 */ // Label 868: @30149
11999 /* 30149 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(30204), // Rule ID 954 //
12000 /* 30154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12001 /* 30157 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_h),
12002 /* 30162 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12003 /* 30165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12004 /* 30168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12005 /* 30171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12006 /* 30175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12007 /* 30179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12008 /* 30183 */ // MIs[0] n
12009 /* 30183 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12010 /* 30186 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
12011 /* 30191 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8163:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
12012 /* 30191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_H),
12013 /* 30194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12014 /* 30196 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12015 /* 30198 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12016 /* 30200 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12017 /* 30202 */ GIR_RootConstrainSelectedInstOperands,
12018 /* 30203 */ // GIR_Coverage, 954,
12019 /* 30203 */ GIR_EraseRootFromParent_Done,
12020 /* 30204 */ // Label 869: @30204
12021 /* 30204 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(30259), // Rule ID 955 //
12022 /* 30209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12023 /* 30212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_w),
12024 /* 30217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12025 /* 30220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12026 /* 30223 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12027 /* 30226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12028 /* 30230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12029 /* 30234 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12030 /* 30238 */ // MIs[0] n
12031 /* 30238 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12032 /* 30241 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
12033 /* 30246 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8164:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
12034 /* 30246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_W),
12035 /* 30249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12036 /* 30251 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12037 /* 30253 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12038 /* 30255 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12039 /* 30257 */ GIR_RootConstrainSelectedInstOperands,
12040 /* 30258 */ // GIR_Coverage, 955,
12041 /* 30258 */ GIR_EraseRootFromParent_Done,
12042 /* 30259 */ // Label 870: @30259
12043 /* 30259 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(30314), // Rule ID 956 //
12044 /* 30264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12045 /* 30267 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_d),
12046 /* 30272 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12047 /* 30275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12048 /* 30278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12049 /* 30281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12050 /* 30285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12051 /* 30289 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12052 /* 30293 */ // MIs[0] n
12053 /* 30293 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12054 /* 30296 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
12055 /* 30301 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8162:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
12056 /* 30301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_D),
12057 /* 30304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12058 /* 30306 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12059 /* 30308 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12060 /* 30310 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12061 /* 30312 */ GIR_RootConstrainSelectedInstOperands,
12062 /* 30313 */ // GIR_Coverage, 956,
12063 /* 30313 */ GIR_EraseRootFromParent_Done,
12064 /* 30314 */ // Label 871: @30314
12065 /* 30314 */ GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(30369), // Rule ID 1349 //
12066 /* 30319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12067 /* 30322 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
12068 /* 30327 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12069 /* 30330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12070 /* 30333 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12071 /* 30336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12072 /* 30340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12073 /* 30344 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12074 /* 30348 */ // MIs[0] sa
12075 /* 30348 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12076 /* 30351 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12077 /* 30356 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8123:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12078 /* 30356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
12079 /* 30359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12080 /* 30361 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12081 /* 30363 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12082 /* 30365 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12083 /* 30367 */ GIR_RootConstrainSelectedInstOperands,
12084 /* 30368 */ // GIR_Coverage, 1349,
12085 /* 30368 */ GIR_EraseRootFromParent_Done,
12086 /* 30369 */ // Label 872: @30369
12087 /* 30369 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(30424), // Rule ID 1350 //
12088 /* 30374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12089 /* 30377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
12090 /* 30382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12091 /* 30385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12092 /* 30388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12093 /* 30391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12094 /* 30395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12095 /* 30399 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12096 /* 30403 */ // MIs[0] sa
12097 /* 30403 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12098 /* 30406 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12099 /* 30411 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8124:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12100 /* 30411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
12101 /* 30414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12102 /* 30416 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12103 /* 30418 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12104 /* 30420 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12105 /* 30422 */ GIR_RootConstrainSelectedInstOperands,
12106 /* 30423 */ // GIR_Coverage, 1350,
12107 /* 30423 */ GIR_EraseRootFromParent_Done,
12108 /* 30424 */ // Label 873: @30424
12109 /* 30424 */ GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(30479), // Rule ID 1351 //
12110 /* 30429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12111 /* 30432 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
12112 /* 30437 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12113 /* 30440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12114 /* 30443 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12115 /* 30446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12116 /* 30450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12117 /* 30454 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12118 /* 30458 */ // MIs[0] sa
12119 /* 30458 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12120 /* 30461 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12121 /* 30466 */ // (intrinsic_wo_chain:{ *:[i32] } 8129:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12122 /* 30466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND_MMR2),
12123 /* 30469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12124 /* 30471 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12125 /* 30473 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12126 /* 30475 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12127 /* 30477 */ GIR_RootConstrainSelectedInstOperands,
12128 /* 30478 */ // GIR_Coverage, 1351,
12129 /* 30478 */ GIR_EraseRootFromParent_Done,
12130 /* 30479 */ // Label 874: @30479
12131 /* 30479 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(30534), // Rule ID 1352 //
12132 /* 30484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12133 /* 30487 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
12134 /* 30492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12135 /* 30495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12136 /* 30498 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12137 /* 30501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12138 /* 30505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12139 /* 30509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12140 /* 30513 */ // MIs[0] sa
12141 /* 30513 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12142 /* 30516 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12143 /* 30521 */ // (intrinsic_wo_chain:{ *:[i32] } 7636:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12144 /* 30521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND_MMR2),
12145 /* 30524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12146 /* 30526 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12147 /* 30528 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12148 /* 30530 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12149 /* 30532 */ GIR_RootConstrainSelectedInstOperands,
12150 /* 30533 */ // GIR_Coverage, 1352,
12151 /* 30533 */ GIR_EraseRootFromParent_Done,
12152 /* 30534 */ // Label 875: @30534
12153 /* 30534 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(30596), // Rule ID 1327 //
12154 /* 30539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12155 /* 30542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
12156 /* 30547 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12157 /* 30550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12158 /* 30553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12159 /* 30556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12160 /* 30560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12161 /* 30564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12162 /* 30568 */ // MIs[0] bp
12163 /* 30568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
12164 /* 30572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12165 /* 30576 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
12166 /* 30580 */ // MIs[1] Operand 1
12167 /* 30580 */ // No operand predicates
12168 /* 30580 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
12169 /* 30582 */ // (intrinsic_wo_chain:{ *:[i32] } 7661:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
12170 /* 30582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN_MMR2),
12171 /* 30585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12172 /* 30587 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12173 /* 30589 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
12174 /* 30592 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12175 /* 30594 */ GIR_RootConstrainSelectedInstOperands,
12176 /* 30595 */ // GIR_Coverage, 1327,
12177 /* 30595 */ GIR_EraseRootFromParent_Done,
12178 /* 30596 */ // Label 876: @30596
12179 /* 30596 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(30650), // Rule ID 552 //
12180 /* 30601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12181 /* 30604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_b),
12182 /* 30609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12183 /* 30612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12184 /* 30615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12185 /* 30618 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12186 /* 30621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12187 /* 30625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12188 /* 30629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12189 /* 30633 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12190 /* 30637 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7670:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12191 /* 30637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_B),
12192 /* 30640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12193 /* 30642 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12194 /* 30644 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12195 /* 30646 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12196 /* 30648 */ GIR_RootConstrainSelectedInstOperands,
12197 /* 30649 */ // GIR_Coverage, 552,
12198 /* 30649 */ GIR_EraseRootFromParent_Done,
12199 /* 30650 */ // Label 877: @30650
12200 /* 30650 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(30704), // Rule ID 553 //
12201 /* 30655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12202 /* 30658 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_h),
12203 /* 30663 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12204 /* 30666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12205 /* 30669 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12206 /* 30672 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12207 /* 30675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12208 /* 30679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12209 /* 30683 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12210 /* 30687 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12211 /* 30691 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7672:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12212 /* 30691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_H),
12213 /* 30694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12214 /* 30696 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12215 /* 30698 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12216 /* 30700 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12217 /* 30702 */ GIR_RootConstrainSelectedInstOperands,
12218 /* 30703 */ // GIR_Coverage, 553,
12219 /* 30703 */ GIR_EraseRootFromParent_Done,
12220 /* 30704 */ // Label 878: @30704
12221 /* 30704 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(30758), // Rule ID 554 //
12222 /* 30709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12223 /* 30712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_w),
12224 /* 30717 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12225 /* 30720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12226 /* 30723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12227 /* 30726 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12228 /* 30729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12229 /* 30733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12230 /* 30737 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12231 /* 30741 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12232 /* 30745 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7673:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12233 /* 30745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_W),
12234 /* 30748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12235 /* 30750 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12236 /* 30752 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12237 /* 30754 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12238 /* 30756 */ GIR_RootConstrainSelectedInstOperands,
12239 /* 30757 */ // GIR_Coverage, 554,
12240 /* 30757 */ GIR_EraseRootFromParent_Done,
12241 /* 30758 */ // Label 879: @30758
12242 /* 30758 */ GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(30812), // Rule ID 555 //
12243 /* 30763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12244 /* 30766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_d),
12245 /* 30771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12246 /* 30774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12247 /* 30777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12248 /* 30780 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
12249 /* 30783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12250 /* 30787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12251 /* 30791 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12252 /* 30795 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12253 /* 30799 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7671:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12254 /* 30799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_D),
12255 /* 30802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12256 /* 30804 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12257 /* 30806 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12258 /* 30808 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12259 /* 30810 */ GIR_RootConstrainSelectedInstOperands,
12260 /* 30811 */ // GIR_Coverage, 555,
12261 /* 30811 */ GIR_EraseRootFromParent_Done,
12262 /* 30812 */ // Label 880: @30812
12263 /* 30812 */ GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(30866), // Rule ID 560 //
12264 /* 30817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12265 /* 30820 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_b),
12266 /* 30825 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12267 /* 30828 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12268 /* 30831 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12269 /* 30834 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12270 /* 30837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12271 /* 30841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12272 /* 30845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12273 /* 30849 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12274 /* 30853 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7678:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12275 /* 30853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_B),
12276 /* 30856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12277 /* 30858 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12278 /* 30860 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12279 /* 30862 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12280 /* 30864 */ GIR_RootConstrainSelectedInstOperands,
12281 /* 30865 */ // GIR_Coverage, 560,
12282 /* 30865 */ GIR_EraseRootFromParent_Done,
12283 /* 30866 */ // Label 881: @30866
12284 /* 30866 */ GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(30920), // Rule ID 561 //
12285 /* 30871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12286 /* 30874 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_h),
12287 /* 30879 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12288 /* 30882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12289 /* 30885 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12290 /* 30888 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12291 /* 30891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12292 /* 30895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12293 /* 30899 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12294 /* 30903 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12295 /* 30907 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7680:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12296 /* 30907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_H),
12297 /* 30910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12298 /* 30912 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12299 /* 30914 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12300 /* 30916 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12301 /* 30918 */ GIR_RootConstrainSelectedInstOperands,
12302 /* 30919 */ // GIR_Coverage, 561,
12303 /* 30919 */ GIR_EraseRootFromParent_Done,
12304 /* 30920 */ // Label 882: @30920
12305 /* 30920 */ GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(30974), // Rule ID 562 //
12306 /* 30925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12307 /* 30928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_w),
12308 /* 30933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12309 /* 30936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12310 /* 30939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12311 /* 30942 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12312 /* 30945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12313 /* 30949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12314 /* 30953 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12315 /* 30957 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12316 /* 30961 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7681:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12317 /* 30961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_W),
12318 /* 30964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12319 /* 30966 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12320 /* 30968 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12321 /* 30970 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12322 /* 30972 */ GIR_RootConstrainSelectedInstOperands,
12323 /* 30973 */ // GIR_Coverage, 562,
12324 /* 30973 */ GIR_EraseRootFromParent_Done,
12325 /* 30974 */ // Label 883: @30974
12326 /* 30974 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(31028), // Rule ID 563 //
12327 /* 30979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12328 /* 30982 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_d),
12329 /* 30987 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12330 /* 30990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12331 /* 30993 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12332 /* 30996 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
12333 /* 30999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12334 /* 31003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12335 /* 31007 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12336 /* 31011 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12337 /* 31015 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7679:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12338 /* 31015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_D),
12339 /* 31018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12340 /* 31020 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12341 /* 31022 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12342 /* 31024 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12343 /* 31026 */ GIR_RootConstrainSelectedInstOperands,
12344 /* 31027 */ // GIR_Coverage, 563,
12345 /* 31027 */ GIR_EraseRootFromParent_Done,
12346 /* 31028 */ // Label 884: @31028
12347 /* 31028 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(31082), // Rule ID 658 //
12348 /* 31033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12349 /* 31036 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
12350 /* 31041 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12351 /* 31044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12352 /* 31047 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12353 /* 31050 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12354 /* 31053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12355 /* 31057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12356 /* 31061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12357 /* 31065 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12358 /* 31069 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7799:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12359 /* 31069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_H),
12360 /* 31072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12361 /* 31074 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12362 /* 31076 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12363 /* 31078 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12364 /* 31080 */ GIR_RootConstrainSelectedInstOperands,
12365 /* 31081 */ // GIR_Coverage, 658,
12366 /* 31081 */ GIR_EraseRootFromParent_Done,
12367 /* 31082 */ // Label 885: @31082
12368 /* 31082 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(31136), // Rule ID 659 //
12369 /* 31087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12370 /* 31090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
12371 /* 31095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12372 /* 31098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12373 /* 31101 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12374 /* 31104 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12375 /* 31107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12376 /* 31111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12377 /* 31115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12378 /* 31119 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12379 /* 31123 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7800:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12380 /* 31123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_W),
12381 /* 31126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12382 /* 31128 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12383 /* 31130 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12384 /* 31132 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12385 /* 31134 */ GIR_RootConstrainSelectedInstOperands,
12386 /* 31135 */ // GIR_Coverage, 659,
12387 /* 31135 */ GIR_EraseRootFromParent_Done,
12388 /* 31136 */ // Label 886: @31136
12389 /* 31136 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(31190), // Rule ID 660 //
12390 /* 31141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12391 /* 31144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
12392 /* 31149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12393 /* 31152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12394 /* 31155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12395 /* 31158 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12396 /* 31161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12397 /* 31165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12398 /* 31169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12399 /* 31173 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12400 /* 31177 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7798:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12401 /* 31177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_D),
12402 /* 31180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12403 /* 31182 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12404 /* 31184 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12405 /* 31186 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12406 /* 31188 */ GIR_RootConstrainSelectedInstOperands,
12407 /* 31189 */ // GIR_Coverage, 660,
12408 /* 31189 */ GIR_EraseRootFromParent_Done,
12409 /* 31190 */ // Label 887: @31190
12410 /* 31190 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(31244), // Rule ID 661 //
12411 /* 31195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12412 /* 31198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
12413 /* 31203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12414 /* 31206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12415 /* 31209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12416 /* 31212 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12417 /* 31215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12418 /* 31219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12419 /* 31223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12420 /* 31227 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12421 /* 31231 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7802:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12422 /* 31231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_H),
12423 /* 31234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12424 /* 31236 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12425 /* 31238 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12426 /* 31240 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12427 /* 31242 */ GIR_RootConstrainSelectedInstOperands,
12428 /* 31243 */ // GIR_Coverage, 661,
12429 /* 31243 */ GIR_EraseRootFromParent_Done,
12430 /* 31244 */ // Label 888: @31244
12431 /* 31244 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(31298), // Rule ID 662 //
12432 /* 31249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12433 /* 31252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
12434 /* 31257 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12435 /* 31260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12436 /* 31263 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12437 /* 31266 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12438 /* 31269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12439 /* 31273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12440 /* 31277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12441 /* 31281 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12442 /* 31285 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7803:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12443 /* 31285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_W),
12444 /* 31288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12445 /* 31290 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12446 /* 31292 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12447 /* 31294 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12448 /* 31296 */ GIR_RootConstrainSelectedInstOperands,
12449 /* 31297 */ // GIR_Coverage, 662,
12450 /* 31297 */ GIR_EraseRootFromParent_Done,
12451 /* 31298 */ // Label 889: @31298
12452 /* 31298 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(31352), // Rule ID 663 //
12453 /* 31303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12454 /* 31306 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
12455 /* 31311 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12456 /* 31314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12457 /* 31317 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12458 /* 31320 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12459 /* 31323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12460 /* 31327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12461 /* 31331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12462 /* 31335 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12463 /* 31339 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7801:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12464 /* 31339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_D),
12465 /* 31342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12466 /* 31344 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12467 /* 31346 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12468 /* 31348 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12469 /* 31350 */ GIR_RootConstrainSelectedInstOperands,
12470 /* 31351 */ // GIR_Coverage, 663,
12471 /* 31351 */ GIR_EraseRootFromParent_Done,
12472 /* 31352 */ // Label 890: @31352
12473 /* 31352 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(31406), // Rule ID 664 //
12474 /* 31357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12475 /* 31360 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
12476 /* 31365 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12477 /* 31368 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12478 /* 31371 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12479 /* 31374 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12480 /* 31377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12481 /* 31381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12482 /* 31385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12483 /* 31389 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12484 /* 31393 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7819:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12485 /* 31393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_H),
12486 /* 31396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12487 /* 31398 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12488 /* 31400 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12489 /* 31402 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12490 /* 31404 */ GIR_RootConstrainSelectedInstOperands,
12491 /* 31405 */ // GIR_Coverage, 664,
12492 /* 31405 */ GIR_EraseRootFromParent_Done,
12493 /* 31406 */ // Label 891: @31406
12494 /* 31406 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(31460), // Rule ID 665 //
12495 /* 31411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12496 /* 31414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
12497 /* 31419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12498 /* 31422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12499 /* 31425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12500 /* 31428 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12501 /* 31431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12502 /* 31435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12503 /* 31439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12504 /* 31443 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12505 /* 31447 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7820:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12506 /* 31447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_W),
12507 /* 31450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12508 /* 31452 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12509 /* 31454 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12510 /* 31456 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12511 /* 31458 */ GIR_RootConstrainSelectedInstOperands,
12512 /* 31459 */ // GIR_Coverage, 665,
12513 /* 31459 */ GIR_EraseRootFromParent_Done,
12514 /* 31460 */ // Label 892: @31460
12515 /* 31460 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(31514), // Rule ID 666 //
12516 /* 31465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12517 /* 31468 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
12518 /* 31473 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12519 /* 31476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12520 /* 31479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12521 /* 31482 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12522 /* 31485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12523 /* 31489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12524 /* 31493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12525 /* 31497 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12526 /* 31501 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7818:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12527 /* 31501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_D),
12528 /* 31504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12529 /* 31506 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12530 /* 31508 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12531 /* 31510 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12532 /* 31512 */ GIR_RootConstrainSelectedInstOperands,
12533 /* 31513 */ // GIR_Coverage, 666,
12534 /* 31513 */ GIR_EraseRootFromParent_Done,
12535 /* 31514 */ // Label 893: @31514
12536 /* 31514 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(31568), // Rule ID 667 //
12537 /* 31519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12538 /* 31522 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
12539 /* 31527 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12540 /* 31530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12541 /* 31533 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12542 /* 31536 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12543 /* 31539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12544 /* 31543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12545 /* 31547 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12546 /* 31551 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12547 /* 31555 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7822:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12548 /* 31555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_H),
12549 /* 31558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12550 /* 31560 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12551 /* 31562 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12552 /* 31564 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12553 /* 31566 */ GIR_RootConstrainSelectedInstOperands,
12554 /* 31567 */ // GIR_Coverage, 667,
12555 /* 31567 */ GIR_EraseRootFromParent_Done,
12556 /* 31568 */ // Label 894: @31568
12557 /* 31568 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(31622), // Rule ID 668 //
12558 /* 31573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12559 /* 31576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
12560 /* 31581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12561 /* 31584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12562 /* 31587 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12563 /* 31590 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12564 /* 31593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12565 /* 31597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12566 /* 31601 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12567 /* 31605 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12568 /* 31609 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7823:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12569 /* 31609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_W),
12570 /* 31612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12571 /* 31614 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12572 /* 31616 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12573 /* 31618 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12574 /* 31620 */ GIR_RootConstrainSelectedInstOperands,
12575 /* 31621 */ // GIR_Coverage, 668,
12576 /* 31621 */ GIR_EraseRootFromParent_Done,
12577 /* 31622 */ // Label 895: @31622
12578 /* 31622 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(31676), // Rule ID 669 //
12579 /* 31627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12580 /* 31630 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
12581 /* 31635 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12582 /* 31638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12583 /* 31641 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12584 /* 31644 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12585 /* 31647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12586 /* 31651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12587 /* 31655 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12588 /* 31659 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12589 /* 31663 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7821:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12590 /* 31663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_D),
12591 /* 31666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12592 /* 31668 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12593 /* 31670 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12594 /* 31672 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12595 /* 31674 */ GIR_RootConstrainSelectedInstOperands,
12596 /* 31675 */ // GIR_Coverage, 669,
12597 /* 31675 */ GIR_EraseRootFromParent_Done,
12598 /* 31676 */ // Label 896: @31676
12599 /* 31676 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(31730), // Rule ID 836 //
12600 /* 31681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12601 /* 31684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
12602 /* 31689 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12603 /* 31692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12604 /* 31695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12605 /* 31698 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12606 /* 31701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12607 /* 31705 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12608 /* 31709 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12609 /* 31713 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12610 /* 31717 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7989:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12611 /* 31717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_H),
12612 /* 31720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12613 /* 31722 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12614 /* 31724 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12615 /* 31726 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12616 /* 31728 */ GIR_RootConstrainSelectedInstOperands,
12617 /* 31729 */ // GIR_Coverage, 836,
12618 /* 31729 */ GIR_EraseRootFromParent_Done,
12619 /* 31730 */ // Label 897: @31730
12620 /* 31730 */ GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(31784), // Rule ID 837 //
12621 /* 31735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12622 /* 31738 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
12623 /* 31743 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12624 /* 31746 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12625 /* 31749 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12626 /* 31752 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12627 /* 31755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12628 /* 31759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12629 /* 31763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12630 /* 31767 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12631 /* 31771 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7990:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12632 /* 31771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_W),
12633 /* 31774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12634 /* 31776 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12635 /* 31778 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12636 /* 31780 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12637 /* 31782 */ GIR_RootConstrainSelectedInstOperands,
12638 /* 31783 */ // GIR_Coverage, 837,
12639 /* 31783 */ GIR_EraseRootFromParent_Done,
12640 /* 31784 */ // Label 898: @31784
12641 /* 31784 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(31838), // Rule ID 838 //
12642 /* 31789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12643 /* 31792 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
12644 /* 31797 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12645 /* 31800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12646 /* 31803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12647 /* 31806 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12648 /* 31809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12649 /* 31813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12650 /* 31817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12651 /* 31821 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12652 /* 31825 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7991:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12653 /* 31825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_H),
12654 /* 31828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12655 /* 31830 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12656 /* 31832 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12657 /* 31834 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12658 /* 31836 */ GIR_RootConstrainSelectedInstOperands,
12659 /* 31837 */ // GIR_Coverage, 838,
12660 /* 31837 */ GIR_EraseRootFromParent_Done,
12661 /* 31838 */ // Label 899: @31838
12662 /* 31838 */ GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(31892), // Rule ID 839 //
12663 /* 31843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12664 /* 31846 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
12665 /* 31851 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12666 /* 31854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12667 /* 31857 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12668 /* 31860 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12669 /* 31863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12670 /* 31867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12671 /* 31871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12672 /* 31875 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12673 /* 31879 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7992:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12674 /* 31879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_W),
12675 /* 31882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12676 /* 31884 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12677 /* 31886 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12678 /* 31888 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12679 /* 31890 */ GIR_RootConstrainSelectedInstOperands,
12680 /* 31891 */ // GIR_Coverage, 839,
12681 /* 31891 */ GIR_EraseRootFromParent_Done,
12682 /* 31892 */ // Label 900: @31892
12683 /* 31892 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(31946), // Rule ID 892 //
12684 /* 31897 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12685 /* 31900 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
12686 /* 31905 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12687 /* 31908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12688 /* 31911 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12689 /* 31914 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12690 /* 31917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12691 /* 31921 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12692 /* 31925 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12693 /* 31929 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12694 /* 31933 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8053:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12695 /* 31933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_H),
12696 /* 31936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12697 /* 31938 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12698 /* 31940 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12699 /* 31942 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12700 /* 31944 */ GIR_RootConstrainSelectedInstOperands,
12701 /* 31945 */ // GIR_Coverage, 892,
12702 /* 31945 */ GIR_EraseRootFromParent_Done,
12703 /* 31946 */ // Label 901: @31946
12704 /* 31946 */ GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(32000), // Rule ID 893 //
12705 /* 31951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12706 /* 31954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
12707 /* 31959 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12708 /* 31962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12709 /* 31965 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12710 /* 31968 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12711 /* 31971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12712 /* 31975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12713 /* 31979 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12714 /* 31983 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12715 /* 31987 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8054:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12716 /* 31987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_W),
12717 /* 31990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12718 /* 31992 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12719 /* 31994 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12720 /* 31996 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12721 /* 31998 */ GIR_RootConstrainSelectedInstOperands,
12722 /* 31999 */ // GIR_Coverage, 893,
12723 /* 31999 */ GIR_EraseRootFromParent_Done,
12724 /* 32000 */ // Label 902: @32000
12725 /* 32000 */ GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(32054), // Rule ID 894 //
12726 /* 32005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12727 /* 32008 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
12728 /* 32013 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12729 /* 32016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12730 /* 32019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12731 /* 32022 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12732 /* 32025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12733 /* 32029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12734 /* 32033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12735 /* 32037 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12736 /* 32041 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8055:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12737 /* 32041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_H),
12738 /* 32044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12739 /* 32046 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12740 /* 32048 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12741 /* 32050 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12742 /* 32052 */ GIR_RootConstrainSelectedInstOperands,
12743 /* 32053 */ // GIR_Coverage, 894,
12744 /* 32053 */ GIR_EraseRootFromParent_Done,
12745 /* 32054 */ // Label 903: @32054
12746 /* 32054 */ GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(32108), // Rule ID 895 //
12747 /* 32059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12748 /* 32062 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
12749 /* 32067 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12750 /* 32070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12751 /* 32073 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12752 /* 32076 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12753 /* 32079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12754 /* 32083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12755 /* 32087 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12756 /* 32091 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12757 /* 32095 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8056:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12758 /* 32095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_W),
12759 /* 32098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12760 /* 32100 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12761 /* 32102 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12762 /* 32104 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12763 /* 32106 */ GIR_RootConstrainSelectedInstOperands,
12764 /* 32107 */ // GIR_Coverage, 895,
12765 /* 32107 */ GIR_EraseRootFromParent_Done,
12766 /* 32108 */ // Label 904: @32108
12767 /* 32108 */ GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(32162), // Rule ID 949 //
12768 /* 32113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12769 /* 32116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_b),
12770 /* 32121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12771 /* 32124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12772 /* 32127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12773 /* 32130 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12774 /* 32133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12775 /* 32137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12776 /* 32141 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12777 /* 32145 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12778 /* 32149 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8157:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12779 /* 32149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_B),
12780 /* 32152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12781 /* 32154 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12782 /* 32156 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12783 /* 32158 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12784 /* 32160 */ GIR_RootConstrainSelectedInstOperands,
12785 /* 32161 */ // GIR_Coverage, 949,
12786 /* 32161 */ GIR_EraseRootFromParent_Done,
12787 /* 32162 */ // Label 905: @32162
12788 /* 32162 */ GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(32216), // Rule ID 950 //
12789 /* 32167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12790 /* 32170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_h),
12791 /* 32175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12792 /* 32178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12793 /* 32181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12794 /* 32184 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12795 /* 32187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12796 /* 32191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12797 /* 32195 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12798 /* 32199 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12799 /* 32203 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8159:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12800 /* 32203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_H),
12801 /* 32206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12802 /* 32208 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12803 /* 32210 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12804 /* 32212 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12805 /* 32214 */ GIR_RootConstrainSelectedInstOperands,
12806 /* 32215 */ // GIR_Coverage, 950,
12807 /* 32215 */ GIR_EraseRootFromParent_Done,
12808 /* 32216 */ // Label 906: @32216
12809 /* 32216 */ GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(32270), // Rule ID 951 //
12810 /* 32221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12811 /* 32224 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_w),
12812 /* 32229 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12813 /* 32232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12814 /* 32235 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12815 /* 32238 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12816 /* 32241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12817 /* 32245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12818 /* 32249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12819 /* 32253 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12820 /* 32257 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8160:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12821 /* 32257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_W),
12822 /* 32260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12823 /* 32262 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12824 /* 32264 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12825 /* 32266 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12826 /* 32268 */ GIR_RootConstrainSelectedInstOperands,
12827 /* 32269 */ // GIR_Coverage, 951,
12828 /* 32269 */ GIR_EraseRootFromParent_Done,
12829 /* 32270 */ // Label 907: @32270
12830 /* 32270 */ GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(32324), // Rule ID 952 //
12831 /* 32275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12832 /* 32278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_d),
12833 /* 32283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12834 /* 32286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12835 /* 32289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12836 /* 32292 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12837 /* 32295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12838 /* 32299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12839 /* 32303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12840 /* 32307 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12841 /* 32311 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8158:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12842 /* 32311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_D),
12843 /* 32314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12844 /* 32316 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12845 /* 32318 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12846 /* 32320 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12847 /* 32322 */ GIR_RootConstrainSelectedInstOperands,
12848 /* 32323 */ // GIR_Coverage, 952,
12849 /* 32323 */ GIR_EraseRootFromParent_Done,
12850 /* 32324 */ // Label 908: @32324
12851 /* 32324 */ GIM_Reject,
12852 /* 32325 */ // Label 862: @32325
12853 /* 32325 */ GIM_Reject,
12854 /* 32326 */ // Label 30: @32326
12855 /* 32326 */ GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(32357), // Rule ID 354 //
12856 /* 32331 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
12857 /* 32334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bposge32),
12858 /* 32339 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12859 /* 32342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12860 /* 32346 */ // (intrinsic_w_chain:{ *:[i32] } 7704:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] })
12861 /* 32346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
12862 /* 32349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12863 /* 32351 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12864 /* 32355 */ GIR_RootConstrainSelectedInstOperands,
12865 /* 32356 */ // GIR_Coverage, 354,
12866 /* 32356 */ GIR_EraseRootFromParent_Done,
12867 /* 32357 */ // Label 909: @32357
12868 /* 32357 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(33294),
12869 /* 32362 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
12870 /* 32365 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(32406), // Rule ID 441 //
12871 /* 32370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12872 /* 32373 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
12873 /* 32378 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12874 /* 32381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12875 /* 32385 */ // MIs[0] mask
12876 /* 32385 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12877 /* 32388 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12878 /* 32393 */ // (intrinsic_w_chain:{ *:[i32] } 8131:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
12879 /* 32393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP),
12880 /* 32396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12881 /* 32398 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12882 /* 32400 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12883 /* 32404 */ GIR_RootConstrainSelectedInstOperands,
12884 /* 32405 */ // GIR_Coverage, 441,
12885 /* 32405 */ GIR_EraseRootFromParent_Done,
12886 /* 32406 */ // Label 911: @32406
12887 /* 32406 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(32442), // Rule ID 1287 //
12888 /* 32411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12889 /* 32414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
12890 /* 32419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12891 /* 32422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12892 /* 32426 */ // MIs[0] mask
12893 /* 32426 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12894 /* 32429 */ // (intrinsic_w_chain:{ *:[i32] } 8131:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
12895 /* 32429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP_MM),
12896 /* 32432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12897 /* 32434 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12898 /* 32436 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12899 /* 32440 */ GIR_RootConstrainSelectedInstOperands,
12900 /* 32441 */ // GIR_Coverage, 1287,
12901 /* 32441 */ GIR_EraseRootFromParent_Done,
12902 /* 32442 */ // Label 912: @32442
12903 /* 32442 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(32483), // Rule ID 442 //
12904 /* 32447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips),
12905 /* 32450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
12906 /* 32455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
12907 /* 32458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12908 /* 32462 */ // MIs[0] mask
12909 /* 32462 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12910 /* 32465 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12911 /* 32470 */ // (intrinsic_void 8260:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
12912 /* 32470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP),
12913 /* 32473 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12914 /* 32475 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12915 /* 32477 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12916 /* 32481 */ GIR_RootConstrainSelectedInstOperands,
12917 /* 32482 */ // GIR_Coverage, 442,
12918 /* 32482 */ GIR_EraseRootFromParent_Done,
12919 /* 32483 */ // Label 913: @32483
12920 /* 32483 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(32519), // Rule ID 1298 //
12921 /* 32488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12922 /* 32491 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
12923 /* 32496 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
12924 /* 32499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12925 /* 32503 */ // MIs[0] mask
12926 /* 32503 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12927 /* 32506 */ // (intrinsic_void 8260:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
12928 /* 32506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP_MM),
12929 /* 32509 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
12930 /* 32511 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12931 /* 32513 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12932 /* 32517 */ GIR_RootConstrainSelectedInstOperands,
12933 /* 32518 */ // GIR_Coverage, 1298,
12934 /* 32518 */ GIR_EraseRootFromParent_Done,
12935 /* 32519 */ // Label 914: @32519
12936 /* 32519 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(32562), // Rule ID 363 //
12937 /* 32524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12938 /* 32527 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12939 /* 32532 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12940 /* 32535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12941 /* 32538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12942 /* 32542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12943 /* 32546 */ // (intrinsic_w_chain:{ *:[v2i16] } 7592:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
12944 /* 32546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH),
12945 /* 32549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12946 /* 32551 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12947 /* 32553 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12948 /* 32556 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12949 /* 32560 */ GIR_RootConstrainSelectedInstOperands,
12950 /* 32561 */ // GIR_Coverage, 363,
12951 /* 32561 */ GIR_EraseRootFromParent_Done,
12952 /* 32562 */ // Label 915: @32562
12953 /* 32562 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(32605), // Rule ID 364 //
12954 /* 32567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12955 /* 32570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
12956 /* 32575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12957 /* 32578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12958 /* 32581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12959 /* 32585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12960 /* 32589 */ // (intrinsic_w_chain:{ *:[i32] } 7594:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
12961 /* 32589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W),
12962 /* 32592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12963 /* 32594 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12964 /* 32596 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12965 /* 32599 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12966 /* 32603 */ GIR_RootConstrainSelectedInstOperands,
12967 /* 32604 */ // GIR_Coverage, 364,
12968 /* 32604 */ GIR_EraseRootFromParent_Done,
12969 /* 32605 */ // Label 916: @32605
12970 /* 32605 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(32648), // Rule ID 450 //
12971 /* 32610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12972 /* 32613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
12973 /* 32618 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12974 /* 32621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12975 /* 32624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12976 /* 32628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12977 /* 32632 */ // (intrinsic_w_chain:{ *:[v4i8] } 7593:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
12978 /* 32632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB),
12979 /* 32635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12980 /* 32637 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12981 /* 32639 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12982 /* 32642 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12983 /* 32646 */ GIR_RootConstrainSelectedInstOperands,
12984 /* 32647 */ // GIR_Coverage, 450,
12985 /* 32647 */ GIR_EraseRootFromParent_Done,
12986 /* 32648 */ // Label 917: @32648
12987 /* 32648 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(32691), // Rule ID 1230 //
12988 /* 32653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12989 /* 32656 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12990 /* 32661 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12991 /* 32664 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12992 /* 32667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12993 /* 32671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12994 /* 32675 */ // (intrinsic_w_chain:{ *:[v2i16] } 7592:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
12995 /* 32675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
12996 /* 32678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12997 /* 32680 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12998 /* 32682 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12999 /* 32685 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13000 /* 32689 */ GIR_RootConstrainSelectedInstOperands,
13001 /* 32690 */ // GIR_Coverage, 1230,
13002 /* 32690 */ GIR_EraseRootFromParent_Done,
13003 /* 32691 */ // Label 918: @32691
13004 /* 32691 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(32734), // Rule ID 1231 //
13005 /* 32696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13006 /* 32699 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
13007 /* 32704 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13008 /* 32707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13009 /* 32710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13010 /* 32714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13011 /* 32718 */ // (intrinsic_w_chain:{ *:[i32] } 7594:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
13012 /* 32718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W_MM),
13013 /* 32721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13014 /* 32723 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13015 /* 32725 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13016 /* 32728 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13017 /* 32732 */ GIR_RootConstrainSelectedInstOperands,
13018 /* 32733 */ // GIR_Coverage, 1231,
13019 /* 32733 */ GIR_EraseRootFromParent_Done,
13020 /* 32734 */ // Label 919: @32734
13021 /* 32734 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(32777), // Rule ID 1311 //
13022 /* 32739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13023 /* 32742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
13024 /* 32747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13025 /* 32750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13026 /* 32753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13027 /* 32757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13028 /* 32761 */ // (intrinsic_w_chain:{ *:[v4i8] } 7593:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
13029 /* 32761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
13030 /* 32764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13031 /* 32766 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13032 /* 32768 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13033 /* 32771 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13034 /* 32775 */ GIR_RootConstrainSelectedInstOperands,
13035 /* 32776 */ // GIR_Coverage, 1311,
13036 /* 32776 */ GIR_EraseRootFromParent_Done,
13037 /* 32777 */ // Label 920: @32777
13038 /* 32777 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(32820), // Rule ID 417 //
13039 /* 32782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13040 /* 32785 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13041 /* 32790 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13042 /* 32793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13043 /* 32796 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13044 /* 32800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13045 /* 32804 */ // (intrinsic_void 7770:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13046 /* 32804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB),
13047 /* 32807 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13048 /* 32809 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13049 /* 32811 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13050 /* 32814 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13051 /* 32818 */ GIR_RootConstrainSelectedInstOperands,
13052 /* 32819 */ // GIR_Coverage, 417,
13053 /* 32819 */ GIR_EraseRootFromParent_Done,
13054 /* 32820 */ // Label 921: @32820
13055 /* 32820 */ GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(32863), // Rule ID 418 //
13056 /* 32825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13057 /* 32828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13058 /* 32833 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13059 /* 32836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13060 /* 32839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13061 /* 32843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13062 /* 32847 */ // (intrinsic_void 7772:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13063 /* 32847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB),
13064 /* 32850 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13065 /* 32852 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13066 /* 32854 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13067 /* 32857 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13068 /* 32861 */ GIR_RootConstrainSelectedInstOperands,
13069 /* 32862 */ // GIR_Coverage, 418,
13070 /* 32862 */ GIR_EraseRootFromParent_Done,
13071 /* 32863 */ // Label 922: @32863
13072 /* 32863 */ GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(32906), // Rule ID 419 //
13073 /* 32868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13074 /* 32871 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13075 /* 32876 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13076 /* 32879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13077 /* 32882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13078 /* 32886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13079 /* 32890 */ // (intrinsic_void 7771:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13080 /* 32890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB),
13081 /* 32893 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13082 /* 32895 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13083 /* 32897 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13084 /* 32900 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13085 /* 32904 */ GIR_RootConstrainSelectedInstOperands,
13086 /* 32905 */ // GIR_Coverage, 419,
13087 /* 32905 */ GIR_EraseRootFromParent_Done,
13088 /* 32906 */ // Label 923: @32906
13089 /* 32906 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(32949), // Rule ID 423 //
13090 /* 32911 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13091 /* 32914 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
13092 /* 32919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13093 /* 32922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13094 /* 32925 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13095 /* 32929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13096 /* 32933 */ // (intrinsic_void 7761:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13097 /* 32933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH),
13098 /* 32936 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13099 /* 32938 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13100 /* 32940 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13101 /* 32943 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13102 /* 32947 */ GIR_RootConstrainSelectedInstOperands,
13103 /* 32948 */ // GIR_Coverage, 423,
13104 /* 32948 */ GIR_EraseRootFromParent_Done,
13105 /* 32949 */ // Label 924: @32949
13106 /* 32949 */ GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(32992), // Rule ID 424 //
13107 /* 32954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13108 /* 32957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
13109 /* 32962 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13110 /* 32965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13111 /* 32968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13112 /* 32972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13113 /* 32976 */ // (intrinsic_void 7763:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13114 /* 32976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH),
13115 /* 32979 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13116 /* 32981 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13117 /* 32983 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13118 /* 32986 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13119 /* 32990 */ GIR_RootConstrainSelectedInstOperands,
13120 /* 32991 */ // GIR_Coverage, 424,
13121 /* 32991 */ GIR_EraseRootFromParent_Done,
13122 /* 32992 */ // Label 925: @32992
13123 /* 32992 */ GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(33035), // Rule ID 425 //
13124 /* 32997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13125 /* 33000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13126 /* 33005 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13127 /* 33008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13128 /* 33011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13129 /* 33015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13130 /* 33019 */ // (intrinsic_void 7762:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13131 /* 33019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH),
13132 /* 33022 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13133 /* 33024 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13134 /* 33026 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13135 /* 33029 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13136 /* 33033 */ GIR_RootConstrainSelectedInstOperands,
13137 /* 33034 */ // GIR_Coverage, 425,
13138 /* 33034 */ GIR_EraseRootFromParent_Done,
13139 /* 33035 */ // Label 926: @33035
13140 /* 33035 */ GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(33078), // Rule ID 1302 //
13141 /* 33040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13142 /* 33043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
13143 /* 33048 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13144 /* 33051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13145 /* 33054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13146 /* 33058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13147 /* 33062 */ // (intrinsic_void 7761:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13148 /* 33062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
13149 /* 33065 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13150 /* 33067 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13151 /* 33069 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13152 /* 33072 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13153 /* 33076 */ GIR_RootConstrainSelectedInstOperands,
13154 /* 33077 */ // GIR_Coverage, 1302,
13155 /* 33077 */ GIR_EraseRootFromParent_Done,
13156 /* 33078 */ // Label 927: @33078
13157 /* 33078 */ GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(33121), // Rule ID 1303 //
13158 /* 33083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13159 /* 33086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
13160 /* 33091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13161 /* 33094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13162 /* 33097 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13163 /* 33101 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13164 /* 33105 */ // (intrinsic_void 7763:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13165 /* 33105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH_MM),
13166 /* 33108 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13167 /* 33110 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13168 /* 33112 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13169 /* 33115 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13170 /* 33119 */ GIR_RootConstrainSelectedInstOperands,
13171 /* 33120 */ // GIR_Coverage, 1303,
13172 /* 33120 */ GIR_EraseRootFromParent_Done,
13173 /* 33121 */ // Label 928: @33121
13174 /* 33121 */ GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(33164), // Rule ID 1304 //
13175 /* 33126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13176 /* 33129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13177 /* 33134 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13178 /* 33137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13179 /* 33140 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13180 /* 33144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13181 /* 33148 */ // (intrinsic_void 7762:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13182 /* 33148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH_MM),
13183 /* 33151 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13184 /* 33153 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13185 /* 33155 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13186 /* 33158 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13187 /* 33162 */ GIR_RootConstrainSelectedInstOperands,
13188 /* 33163 */ // GIR_Coverage, 1304,
13189 /* 33163 */ GIR_EraseRootFromParent_Done,
13190 /* 33164 */ // Label 929: @33164
13191 /* 33164 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(33207), // Rule ID 1308 //
13192 /* 33169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13193 /* 33172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13194 /* 33177 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13195 /* 33180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13196 /* 33183 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13197 /* 33187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13198 /* 33191 */ // (intrinsic_void 7770:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13199 /* 33191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
13200 /* 33194 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13201 /* 33196 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13202 /* 33198 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13203 /* 33201 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13204 /* 33205 */ GIR_RootConstrainSelectedInstOperands,
13205 /* 33206 */ // GIR_Coverage, 1308,
13206 /* 33206 */ GIR_EraseRootFromParent_Done,
13207 /* 33207 */ // Label 930: @33207
13208 /* 33207 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(33250), // Rule ID 1309 //
13209 /* 33212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13210 /* 33215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13211 /* 33220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13212 /* 33223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13213 /* 33226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13214 /* 33230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13215 /* 33234 */ // (intrinsic_void 7772:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13216 /* 33234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
13217 /* 33237 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13218 /* 33239 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13219 /* 33241 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13220 /* 33244 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13221 /* 33248 */ GIR_RootConstrainSelectedInstOperands,
13222 /* 33249 */ // GIR_Coverage, 1309,
13223 /* 33249 */ GIR_EraseRootFromParent_Done,
13224 /* 33250 */ // Label 931: @33250
13225 /* 33250 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(33293), // Rule ID 1310 //
13226 /* 33255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13227 /* 33258 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13228 /* 33263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13229 /* 33266 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13230 /* 33269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13231 /* 33273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13232 /* 33277 */ // (intrinsic_void 7771:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13233 /* 33277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
13234 /* 33280 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13235 /* 33282 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13236 /* 33284 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13237 /* 33287 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13238 /* 33291 */ GIR_RootConstrainSelectedInstOperands,
13239 /* 33292 */ // GIR_Coverage, 1310,
13240 /* 33292 */ GIR_EraseRootFromParent_Done,
13241 /* 33293 */ // Label 932: @33293
13242 /* 33293 */ GIM_Reject,
13243 /* 33294 */ // Label 910: @33294
13244 /* 33294 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(37419),
13245 /* 33299 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
13246 /* 33302 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(33366), // Rule ID 382 //
13247 /* 33307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13248 /* 33310 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13249 /* 33315 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13250 /* 33318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13251 /* 33321 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13252 /* 33324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13253 /* 33328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13254 /* 33332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13255 /* 33336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13256 /* 33340 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13257 /* 33344 */ // MIs[1] Operand 1
13258 /* 33344 */ // No operand predicates
13259 /* 33344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13260 /* 33346 */ // (intrinsic_w_chain:{ *:[v2i16] } 8148:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
13261 /* 33346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH),
13262 /* 33349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13263 /* 33351 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13264 /* 33353 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
13265 /* 33356 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13266 /* 33359 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13267 /* 33364 */ GIR_RootConstrainSelectedInstOperands,
13268 /* 33365 */ // GIR_Coverage, 382,
13269 /* 33365 */ GIR_EraseRootFromParent_Done,
13270 /* 33366 */ // Label 934: @33366
13271 /* 33366 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(33430), // Rule ID 387 //
13272 /* 33371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13273 /* 33374 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13274 /* 33379 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13275 /* 33382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13276 /* 33385 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13277 /* 33388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13278 /* 33392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13279 /* 33396 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13280 /* 33400 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13281 /* 33404 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13282 /* 33408 */ // MIs[1] Operand 1
13283 /* 33408 */ // No operand predicates
13284 /* 33408 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13285 /* 33410 */ // (intrinsic_w_chain:{ *:[i32] } 8149:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
13286 /* 33410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W),
13287 /* 33413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13288 /* 33415 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13289 /* 33417 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
13290 /* 33420 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13291 /* 33423 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13292 /* 33428 */ GIR_RootConstrainSelectedInstOperands,
13293 /* 33429 */ // GIR_Coverage, 387,
13294 /* 33429 */ GIR_EraseRootFromParent_Done,
13295 /* 33430 */ // Label 935: @33430
13296 /* 33430 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(33494), // Rule ID 1239 //
13297 /* 33435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13298 /* 33438 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13299 /* 33443 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13300 /* 33446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13301 /* 33449 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13302 /* 33452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13303 /* 33456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13304 /* 33460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13305 /* 33464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13306 /* 33468 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13307 /* 33472 */ // MIs[1] Operand 1
13308 /* 33472 */ // No operand predicates
13309 /* 33472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13310 /* 33474 */ // (intrinsic_w_chain:{ *:[v2i16] } 8148:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
13311 /* 33474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH_MM),
13312 /* 33477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13313 /* 33479 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13314 /* 33481 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
13315 /* 33484 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13316 /* 33487 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13317 /* 33492 */ GIR_RootConstrainSelectedInstOperands,
13318 /* 33493 */ // GIR_Coverage, 1239,
13319 /* 33493 */ GIR_EraseRootFromParent_Done,
13320 /* 33494 */ // Label 936: @33494
13321 /* 33494 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(33558), // Rule ID 1244 //
13322 /* 33499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13323 /* 33502 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13324 /* 33507 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13325 /* 33510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13326 /* 33513 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13327 /* 33516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13328 /* 33520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13329 /* 33524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13330 /* 33528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13331 /* 33532 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13332 /* 33536 */ // MIs[1] Operand 1
13333 /* 33536 */ // No operand predicates
13334 /* 33536 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13335 /* 33538 */ // (intrinsic_w_chain:{ *:[i32] } 8149:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
13336 /* 33538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W_MM),
13337 /* 33541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13338 /* 33543 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13339 /* 33545 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
13340 /* 33548 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13341 /* 33551 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13342 /* 33556 */ GIR_RootConstrainSelectedInstOperands,
13343 /* 33557 */ // GIR_Coverage, 1244,
13344 /* 33557 */ GIR_EraseRootFromParent_Done,
13345 /* 33558 */ // Label 937: @33558
13346 /* 33558 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(33613), // Rule ID 1942 //
13347 /* 33563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13348 /* 33566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
13349 /* 33571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13350 /* 33574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13351 /* 33577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13352 /* 33580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13353 /* 33584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13354 /* 33588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13355 /* 33592 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13356 /* 33596 */ // MIs[1] Operand 1
13357 /* 33596 */ // No operand predicates
13358 /* 33596 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13359 /* 33598 */ // (intrinsic_w_chain:{ *:[v2i16] } 8146:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
13360 /* 33598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_PH),
13361 /* 33601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13362 /* 33603 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
13363 /* 33605 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13364 /* 33608 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13365 /* 33611 */ GIR_RootConstrainSelectedInstOperands,
13366 /* 33612 */ // GIR_Coverage, 1942,
13367 /* 33612 */ GIR_EraseRootFromParent_Done,
13368 /* 33613 */ // Label 938: @33613
13369 /* 33613 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(33668), // Rule ID 1948 //
13370 /* 33618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13371 /* 33621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
13372 /* 33626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13373 /* 33629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13374 /* 33632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13375 /* 33635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13376 /* 33639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13377 /* 33643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13378 /* 33647 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
13379 /* 33651 */ // MIs[1] Operand 1
13380 /* 33651 */ // No operand predicates
13381 /* 33651 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13382 /* 33653 */ // (intrinsic_w_chain:{ *:[v4i8] } 8147:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
13383 /* 33653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_QB),
13384 /* 33656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13385 /* 33658 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
13386 /* 33660 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13387 /* 33663 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13388 /* 33666 */ GIR_RootConstrainSelectedInstOperands,
13389 /* 33667 */ // GIR_Coverage, 1948,
13390 /* 33667 */ GIR_EraseRootFromParent_Done,
13391 /* 33668 */ // Label 939: @33668
13392 /* 33668 */ GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(33720), // Rule ID 359 //
13393 /* 33673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13394 /* 33676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
13395 /* 33681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13396 /* 33684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13397 /* 33687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13398 /* 33690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13399 /* 33694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13400 /* 33698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13401 /* 33702 */ // (intrinsic_w_chain:{ *:[i32] } 7601:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13402 /* 33702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W),
13403 /* 33705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13404 /* 33707 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13405 /* 33709 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13406 /* 33711 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13407 /* 33714 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13408 /* 33718 */ GIR_RootConstrainSelectedInstOperands,
13409 /* 33719 */ // GIR_Coverage, 359,
13410 /* 33719 */ GIR_EraseRootFromParent_Done,
13411 /* 33720 */ // Label 940: @33720
13412 /* 33720 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(33772), // Rule ID 360 //
13413 /* 33725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13414 /* 33728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
13415 /* 33733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13416 /* 33736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13417 /* 33739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13418 /* 33742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13419 /* 33746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13420 /* 33750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13421 /* 33754 */ // (intrinsic_w_chain:{ *:[i32] } 8221:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13422 /* 33754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W),
13423 /* 33757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13424 /* 33759 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13425 /* 33761 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13426 /* 33763 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13427 /* 33766 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13428 /* 33770 */ GIR_RootConstrainSelectedInstOperands,
13429 /* 33771 */ // GIR_Coverage, 360,
13430 /* 33771 */ GIR_EraseRootFromParent_Done,
13431 /* 33772 */ // Label 941: @33772
13432 /* 33772 */ GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(33824), // Rule ID 367 //
13433 /* 33777 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13434 /* 33780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
13435 /* 33785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13436 /* 33788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13437 /* 33791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13438 /* 33794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13439 /* 33798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13440 /* 33802 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13441 /* 33806 */ // (intrinsic_w_chain:{ *:[v2i16] } 8127:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13442 /* 33806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
13443 /* 33809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13444 /* 33811 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13445 /* 33813 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13446 /* 33815 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13447 /* 33818 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13448 /* 33822 */ GIR_RootConstrainSelectedInstOperands,
13449 /* 33823 */ // GIR_Coverage, 367,
13450 /* 33823 */ GIR_EraseRootFromParent_Done,
13451 /* 33824 */ // Label 942: @33824
13452 /* 33824 */ GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(33876), // Rule ID 368 //
13453 /* 33829 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13454 /* 33832 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
13455 /* 33837 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13456 /* 33840 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13457 /* 33843 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13458 /* 33846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13459 /* 33850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13460 /* 33854 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13461 /* 33858 */ // (intrinsic_w_chain:{ *:[v4i8] } 8128:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13462 /* 33858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
13463 /* 33861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13464 /* 33863 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13465 /* 33865 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13466 /* 33867 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13467 /* 33870 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13468 /* 33874 */ GIR_RootConstrainSelectedInstOperands,
13469 /* 33875 */ // GIR_Coverage, 368,
13470 /* 33875 */ GIR_EraseRootFromParent_Done,
13471 /* 33876 */ // Label 943: @33876
13472 /* 33876 */ GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(33928), // Rule ID 379 //
13473 /* 33881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13474 /* 33884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
13475 /* 33889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13476 /* 33892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13477 /* 33895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13478 /* 33898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13479 /* 33902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13480 /* 33906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13481 /* 33910 */ // (intrinsic_w_chain:{ *:[v4i8] } 8147:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13482 /* 33910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB),
13483 /* 33913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13484 /* 33915 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13485 /* 33917 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13486 /* 33919 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13487 /* 33922 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13488 /* 33926 */ GIR_RootConstrainSelectedInstOperands,
13489 /* 33927 */ // GIR_Coverage, 379,
13490 /* 33927 */ GIR_EraseRootFromParent_Done,
13491 /* 33928 */ // Label 944: @33928
13492 /* 33928 */ GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(33980), // Rule ID 381 //
13493 /* 33933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13494 /* 33936 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
13495 /* 33941 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13496 /* 33944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13497 /* 33947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13498 /* 33950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13499 /* 33954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13500 /* 33958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13501 /* 33962 */ // (intrinsic_w_chain:{ *:[v2i16] } 8146:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13502 /* 33962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH),
13503 /* 33965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13504 /* 33967 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13505 /* 33969 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13506 /* 33971 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13507 /* 33974 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13508 /* 33978 */ GIR_RootConstrainSelectedInstOperands,
13509 /* 33979 */ // GIR_Coverage, 381,
13510 /* 33979 */ GIR_EraseRootFromParent_Done,
13511 /* 33980 */ // Label 945: @33980
13512 /* 33980 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(34032), // Rule ID 383 //
13513 /* 33985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13514 /* 33988 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13515 /* 33993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13516 /* 33996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13517 /* 33999 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13518 /* 34002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13519 /* 34006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13520 /* 34010 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13521 /* 34014 */ // (intrinsic_w_chain:{ *:[v2i16] } 8148:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13522 /* 34014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH),
13523 /* 34017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13524 /* 34019 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13525 /* 34021 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13526 /* 34023 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13527 /* 34026 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13528 /* 34030 */ GIR_RootConstrainSelectedInstOperands,
13529 /* 34031 */ // GIR_Coverage, 383,
13530 /* 34031 */ GIR_EraseRootFromParent_Done,
13531 /* 34032 */ // Label 946: @34032
13532 /* 34032 */ GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(34084), // Rule ID 388 //
13533 /* 34037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13534 /* 34040 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13535 /* 34045 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13536 /* 34048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13537 /* 34051 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13538 /* 34054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13539 /* 34058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13540 /* 34062 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13541 /* 34066 */ // (intrinsic_w_chain:{ *:[i32] } 8149:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13542 /* 34066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W),
13543 /* 34069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13544 /* 34071 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13545 /* 34073 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13546 /* 34075 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13547 /* 34078 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13548 /* 34082 */ GIR_RootConstrainSelectedInstOperands,
13549 /* 34083 */ // GIR_Coverage, 388,
13550 /* 34083 */ GIR_EraseRootFromParent_Done,
13551 /* 34084 */ // Label 947: @34084
13552 /* 34084 */ GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(34136), // Rule ID 391 //
13553 /* 34089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13554 /* 34092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
13555 /* 34097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13556 /* 34100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13557 /* 34103 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13558 /* 34106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13559 /* 34110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13560 /* 34114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13561 /* 34118 */ // (intrinsic_w_chain:{ *:[v2i16] } 8069:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13562 /* 34118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
13563 /* 34121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13564 /* 34123 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13565 /* 34125 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13566 /* 34127 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13567 /* 34130 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13568 /* 34134 */ GIR_RootConstrainSelectedInstOperands,
13569 /* 34135 */ // GIR_Coverage, 391,
13570 /* 34135 */ GIR_EraseRootFromParent_Done,
13571 /* 34136 */ // Label 948: @34136
13572 /* 34136 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(34188), // Rule ID 392 //
13573 /* 34141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13574 /* 34144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
13575 /* 34149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13576 /* 34152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13577 /* 34155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13578 /* 34158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13579 /* 34162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13580 /* 34166 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13581 /* 34170 */ // (intrinsic_w_chain:{ *:[v2i16] } 8070:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13582 /* 34170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
13583 /* 34173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13584 /* 34175 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13585 /* 34177 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13586 /* 34179 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13587 /* 34182 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13588 /* 34186 */ GIR_RootConstrainSelectedInstOperands,
13589 /* 34187 */ // GIR_Coverage, 392,
13590 /* 34187 */ GIR_EraseRootFromParent_Done,
13591 /* 34188 */ // Label 949: @34188
13592 /* 34188 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(34240), // Rule ID 393 //
13593 /* 34193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13594 /* 34196 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
13595 /* 34201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13596 /* 34204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13597 /* 34207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13598 /* 34210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13599 /* 34214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13600 /* 34218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13601 /* 34222 */ // (intrinsic_w_chain:{ *:[i32] } 8067:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13602 /* 34222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
13603 /* 34225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13604 /* 34227 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13605 /* 34229 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13606 /* 34231 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13607 /* 34234 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13608 /* 34238 */ GIR_RootConstrainSelectedInstOperands,
13609 /* 34239 */ // GIR_Coverage, 393,
13610 /* 34239 */ GIR_EraseRootFromParent_Done,
13611 /* 34240 */ // Label 950: @34240
13612 /* 34240 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(34292), // Rule ID 394 //
13613 /* 34245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13614 /* 34248 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
13615 /* 34253 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13616 /* 34256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13617 /* 34259 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13618 /* 34262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13619 /* 34266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13620 /* 34270 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13621 /* 34274 */ // (intrinsic_w_chain:{ *:[i32] } 8068:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13622 /* 34274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
13623 /* 34277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13624 /* 34279 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13625 /* 34281 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13626 /* 34283 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13627 /* 34286 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13628 /* 34290 */ GIR_RootConstrainSelectedInstOperands,
13629 /* 34291 */ // GIR_Coverage, 394,
13630 /* 34291 */ GIR_EraseRootFromParent_Done,
13631 /* 34292 */ // Label 951: @34292
13632 /* 34292 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(34344), // Rule ID 395 //
13633 /* 34297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13634 /* 34300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
13635 /* 34305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13636 /* 34308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13637 /* 34311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13638 /* 34314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13639 /* 34318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13640 /* 34322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13641 /* 34326 */ // (intrinsic_w_chain:{ *:[v2i16] } 8071:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13642 /* 34326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH),
13643 /* 34329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13644 /* 34331 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13645 /* 34333 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13646 /* 34335 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13647 /* 34338 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13648 /* 34342 */ GIR_RootConstrainSelectedInstOperands,
13649 /* 34343 */ // GIR_Coverage, 395,
13650 /* 34343 */ GIR_EraseRootFromParent_Done,
13651 /* 34344 */ // Label 952: @34344
13652 /* 34344 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(34393), // Rule ID 420 //
13653 /* 34349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13654 /* 34352 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
13655 /* 34357 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13656 /* 34360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13657 /* 34363 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13658 /* 34366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13659 /* 34370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13660 /* 34374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13661 /* 34378 */ // (intrinsic_w_chain:{ *:[i32] } 7767:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13662 /* 34378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB),
13663 /* 34381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13664 /* 34383 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13665 /* 34385 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13666 /* 34387 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13667 /* 34391 */ GIR_RootConstrainSelectedInstOperands,
13668 /* 34392 */ // GIR_Coverage, 420,
13669 /* 34392 */ GIR_EraseRootFromParent_Done,
13670 /* 34393 */ // Label 953: @34393
13671 /* 34393 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(34442), // Rule ID 421 //
13672 /* 34398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13673 /* 34401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
13674 /* 34406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13675 /* 34409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13676 /* 34412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13677 /* 34415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13678 /* 34419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13679 /* 34423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13680 /* 34427 */ // (intrinsic_w_chain:{ *:[i32] } 7769:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13681 /* 34427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB),
13682 /* 34430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13683 /* 34432 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13684 /* 34434 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13685 /* 34436 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13686 /* 34440 */ GIR_RootConstrainSelectedInstOperands,
13687 /* 34441 */ // GIR_Coverage, 421,
13688 /* 34441 */ GIR_EraseRootFromParent_Done,
13689 /* 34442 */ // Label 954: @34442
13690 /* 34442 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(34491), // Rule ID 422 //
13691 /* 34447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13692 /* 34450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
13693 /* 34455 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13694 /* 34458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13695 /* 34461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13696 /* 34464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13697 /* 34468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13698 /* 34472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13699 /* 34476 */ // (intrinsic_w_chain:{ *:[i32] } 7768:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13700 /* 34476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB),
13701 /* 34479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13702 /* 34481 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13703 /* 34483 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13704 /* 34485 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13705 /* 34489 */ GIR_RootConstrainSelectedInstOperands,
13706 /* 34490 */ // GIR_Coverage, 422,
13707 /* 34490 */ GIR_EraseRootFromParent_Done,
13708 /* 34491 */ // Label 955: @34491
13709 /* 34491 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(34540), // Rule ID 432 //
13710 /* 34496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13711 /* 34499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
13712 /* 34504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13713 /* 34507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13714 /* 34510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13715 /* 34513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13716 /* 34517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13717 /* 34521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13718 /* 34525 */ // (intrinsic_w_chain:{ *:[v4i8] } 8111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13719 /* 34525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB),
13720 /* 34528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13721 /* 34530 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13722 /* 34532 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13723 /* 34534 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13724 /* 34538 */ GIR_RootConstrainSelectedInstOperands,
13725 /* 34539 */ // GIR_Coverage, 432,
13726 /* 34539 */ GIR_EraseRootFromParent_Done,
13727 /* 34540 */ // Label 956: @34540
13728 /* 34540 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(34589), // Rule ID 433 //
13729 /* 34545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13730 /* 34548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
13731 /* 34553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13732 /* 34556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13733 /* 34559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13734 /* 34562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13735 /* 34566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13736 /* 34570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13737 /* 34574 */ // (intrinsic_w_chain:{ *:[v2i16] } 8110:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13738 /* 34574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH),
13739 /* 34577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13740 /* 34579 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13741 /* 34581 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13742 /* 34583 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13743 /* 34587 */ GIR_RootConstrainSelectedInstOperands,
13744 /* 34588 */ // GIR_Coverage, 433,
13745 /* 34588 */ GIR_EraseRootFromParent_Done,
13746 /* 34589 */ // Label 957: @34589
13747 /* 34589 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(34638), // Rule ID 437 //
13748 /* 34594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13749 /* 34597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
13750 /* 34602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13751 /* 34605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13752 /* 34608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13753 /* 34611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13754 /* 34615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13755 /* 34619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13756 /* 34623 */ // (intrinsic_w_chain:{ *:[i32] } 7969:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
13757 /* 34623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV),
13758 /* 34626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13759 /* 34628 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
13760 /* 34630 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13761 /* 34632 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13762 /* 34636 */ GIR_RootConstrainSelectedInstOperands,
13763 /* 34637 */ // GIR_Coverage, 437,
13764 /* 34637 */ GIR_EraseRootFromParent_Done,
13765 /* 34638 */ // Label 958: @34638
13766 /* 34638 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(34690), // Rule ID 443 //
13767 /* 34643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13768 /* 34646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
13769 /* 34651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13770 /* 34654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13771 /* 34657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13772 /* 34660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13773 /* 34664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13774 /* 34668 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13775 /* 34672 */ // (intrinsic_w_chain:{ *:[v2i16] } 7619:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13776 /* 34672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH),
13777 /* 34675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13778 /* 34677 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13779 /* 34679 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13780 /* 34681 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13781 /* 34684 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13782 /* 34688 */ GIR_RootConstrainSelectedInstOperands,
13783 /* 34689 */ // GIR_Coverage, 443,
13784 /* 34689 */ GIR_EraseRootFromParent_Done,
13785 /* 34690 */ // Label 959: @34690
13786 /* 34690 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(34742), // Rule ID 444 //
13787 /* 34695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13788 /* 34698 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
13789 /* 34703 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13790 /* 34706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13791 /* 34709 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13792 /* 34712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13793 /* 34716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13794 /* 34720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13795 /* 34724 */ // (intrinsic_w_chain:{ *:[v2i16] } 7621:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13796 /* 34724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH),
13797 /* 34727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13798 /* 34729 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13799 /* 34731 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13800 /* 34733 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13801 /* 34736 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13802 /* 34740 */ GIR_RootConstrainSelectedInstOperands,
13803 /* 34741 */ // GIR_Coverage, 444,
13804 /* 34741 */ GIR_EraseRootFromParent_Done,
13805 /* 34742 */ // Label 960: @34742
13806 /* 34742 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(34794), // Rule ID 445 //
13807 /* 34747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13808 /* 34750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
13809 /* 34755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13810 /* 34758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13811 /* 34761 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13812 /* 34764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13813 /* 34768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13814 /* 34772 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13815 /* 34776 */ // (intrinsic_w_chain:{ *:[v2i16] } 8242:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13816 /* 34776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH),
13817 /* 34779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13818 /* 34781 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13819 /* 34783 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13820 /* 34785 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13821 /* 34788 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13822 /* 34792 */ GIR_RootConstrainSelectedInstOperands,
13823 /* 34793 */ // GIR_Coverage, 445,
13824 /* 34793 */ GIR_EraseRootFromParent_Done,
13825 /* 34794 */ // Label 961: @34794
13826 /* 34794 */ GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(34846), // Rule ID 446 //
13827 /* 34799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13828 /* 34802 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
13829 /* 34807 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13830 /* 34810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13831 /* 34813 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13832 /* 34816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13833 /* 34820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13834 /* 34824 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13835 /* 34828 */ // (intrinsic_w_chain:{ *:[v2i16] } 8244:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13836 /* 34828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH),
13837 /* 34831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13838 /* 34833 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13839 /* 34835 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13840 /* 34837 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13841 /* 34840 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13842 /* 34844 */ GIR_RootConstrainSelectedInstOperands,
13843 /* 34845 */ // GIR_Coverage, 446,
13844 /* 34845 */ GIR_EraseRootFromParent_Done,
13845 /* 34846 */ // Label 962: @34846
13846 /* 34846 */ GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(34898), // Rule ID 447 //
13847 /* 34851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13848 /* 34854 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
13849 /* 34859 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13850 /* 34862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13851 /* 34865 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13852 /* 34868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13853 /* 34872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13854 /* 34876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13855 /* 34880 */ // (intrinsic_w_chain:{ *:[i32] } 7764:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13856 /* 34880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
13857 /* 34883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13858 /* 34885 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13859 /* 34887 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13860 /* 34889 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13861 /* 34892 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13862 /* 34896 */ GIR_RootConstrainSelectedInstOperands,
13863 /* 34897 */ // GIR_Coverage, 447,
13864 /* 34897 */ GIR_EraseRootFromParent_Done,
13865 /* 34898 */ // Label 963: @34898
13866 /* 34898 */ GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(34950), // Rule ID 448 //
13867 /* 34903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13868 /* 34906 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
13869 /* 34911 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13870 /* 34914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13871 /* 34917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13872 /* 34920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13873 /* 34924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13874 /* 34928 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13875 /* 34932 */ // (intrinsic_w_chain:{ *:[i32] } 7766:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13876 /* 34932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB),
13877 /* 34935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13878 /* 34937 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13879 /* 34939 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13880 /* 34941 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13881 /* 34944 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13882 /* 34948 */ GIR_RootConstrainSelectedInstOperands,
13883 /* 34949 */ // GIR_Coverage, 448,
13884 /* 34949 */ GIR_EraseRootFromParent_Done,
13885 /* 34950 */ // Label 964: @34950
13886 /* 34950 */ GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(35002), // Rule ID 449 //
13887 /* 34955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13888 /* 34958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
13889 /* 34963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13890 /* 34966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13891 /* 34969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13892 /* 34972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13893 /* 34976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13894 /* 34980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13895 /* 34984 */ // (intrinsic_w_chain:{ *:[i32] } 7765:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13896 /* 34984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB),
13897 /* 34987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13898 /* 34989 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13899 /* 34991 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13900 /* 34993 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13901 /* 34996 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13902 /* 35000 */ GIR_RootConstrainSelectedInstOperands,
13903 /* 35001 */ // GIR_Coverage, 449,
13904 /* 35001 */ GIR_EraseRootFromParent_Done,
13905 /* 35002 */ // Label 965: @35002
13906 /* 35002 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(35054), // Rule ID 463 //
13907 /* 35007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13908 /* 35010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
13909 /* 35015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13910 /* 35018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13911 /* 35021 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13912 /* 35024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13913 /* 35028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13914 /* 35032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13915 /* 35036 */ // (intrinsic_w_chain:{ *:[v2i16] } 8066:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13916 /* 35036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH),
13917 /* 35039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13918 /* 35041 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13919 /* 35043 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13920 /* 35045 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13921 /* 35048 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13922 /* 35052 */ GIR_RootConstrainSelectedInstOperands,
13923 /* 35053 */ // GIR_Coverage, 463,
13924 /* 35053 */ GIR_EraseRootFromParent_Done,
13925 /* 35054 */ // Label 966: @35054
13926 /* 35054 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(35106), // Rule ID 464 //
13927 /* 35059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13928 /* 35062 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
13929 /* 35067 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13930 /* 35070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13931 /* 35073 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13932 /* 35076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13933 /* 35080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13934 /* 35084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13935 /* 35088 */ // (intrinsic_w_chain:{ *:[i32] } 8074:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13936 /* 35088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W),
13937 /* 35091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13938 /* 35093 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13939 /* 35095 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13940 /* 35097 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13941 /* 35100 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13942 /* 35104 */ GIR_RootConstrainSelectedInstOperands,
13943 /* 35105 */ // GIR_Coverage, 464,
13944 /* 35105 */ GIR_EraseRootFromParent_Done,
13945 /* 35106 */ // Label 967: @35106
13946 /* 35106 */ GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(35158), // Rule ID 465 //
13947 /* 35111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13948 /* 35114 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
13949 /* 35119 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13950 /* 35122 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13951 /* 35125 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13952 /* 35128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13953 /* 35132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13954 /* 35136 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13955 /* 35140 */ // (intrinsic_w_chain:{ *:[i32] } 8072:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13956 /* 35140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W),
13957 /* 35143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13958 /* 35145 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13959 /* 35147 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13960 /* 35149 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13961 /* 35152 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13962 /* 35156 */ GIR_RootConstrainSelectedInstOperands,
13963 /* 35157 */ // GIR_Coverage, 465,
13964 /* 35157 */ GIR_EraseRootFromParent_Done,
13965 /* 35158 */ // Label 968: @35158
13966 /* 35158 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(35210), // Rule ID 466 //
13967 /* 35163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13968 /* 35166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
13969 /* 35171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13970 /* 35174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13971 /* 35177 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13972 /* 35180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13973 /* 35184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13974 /* 35188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13975 /* 35192 */ // (intrinsic_w_chain:{ *:[v2i16] } 8073:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13976 /* 35192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH),
13977 /* 35195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13978 /* 35197 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13979 /* 35199 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13980 /* 35201 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13981 /* 35204 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13982 /* 35208 */ GIR_RootConstrainSelectedInstOperands,
13983 /* 35209 */ // GIR_Coverage, 466,
13984 /* 35209 */ GIR_EraseRootFromParent_Done,
13985 /* 35210 */ // Label 969: @35210
13986 /* 35210 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(35259), // Rule ID 476 //
13987 /* 35215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13988 /* 35218 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
13989 /* 35223 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13990 /* 35226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13991 /* 35229 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13992 /* 35232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13993 /* 35236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13994 /* 35240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13995 /* 35244 */ // (intrinsic_w_chain:{ *:[v4i8] } 8122:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13996 /* 35244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH),
13997 /* 35247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13998 /* 35249 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13999 /* 35251 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14000 /* 35253 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14001 /* 35257 */ GIR_RootConstrainSelectedInstOperands,
14002 /* 35258 */ // GIR_Coverage, 476,
14003 /* 35258 */ GIR_EraseRootFromParent_Done,
14004 /* 35259 */ // Label 970: @35259
14005 /* 35259 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(35311), // Rule ID 1224 //
14006 /* 35264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14007 /* 35267 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
14008 /* 35272 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14009 /* 35275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14010 /* 35278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14011 /* 35281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14012 /* 35285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14013 /* 35289 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14014 /* 35293 */ // (intrinsic_w_chain:{ *:[i32] } 7601:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14015 /* 35293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W_MM),
14016 /* 35296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14017 /* 35298 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14018 /* 35300 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14019 /* 35302 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14020 /* 35305 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14021 /* 35309 */ GIR_RootConstrainSelectedInstOperands,
14022 /* 35310 */ // GIR_Coverage, 1224,
14023 /* 35310 */ GIR_EraseRootFromParent_Done,
14024 /* 35311 */ // Label 971: @35311
14025 /* 35311 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(35360), // Rule ID 1232 //
14026 /* 35316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14027 /* 35319 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
14028 /* 35324 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14029 /* 35327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14030 /* 35330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14031 /* 35333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14032 /* 35337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14033 /* 35341 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14034 /* 35345 */ // (intrinsic_w_chain:{ *:[i32] } 7969:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
14035 /* 35345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV_MM),
14036 /* 35348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14037 /* 35350 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
14038 /* 35352 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14039 /* 35354 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14040 /* 35358 */ GIR_RootConstrainSelectedInstOperands,
14041 /* 35359 */ // GIR_Coverage, 1232,
14042 /* 35359 */ GIR_EraseRootFromParent_Done,
14043 /* 35360 */ // Label 972: @35360
14044 /* 35360 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(35412), // Rule ID 1240 //
14045 /* 35365 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14046 /* 35368 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
14047 /* 35373 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14048 /* 35376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14049 /* 35379 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14050 /* 35382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14051 /* 35386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14052 /* 35390 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14053 /* 35394 */ // (intrinsic_w_chain:{ *:[v2i16] } 8146:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14054 /* 35394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH_MM),
14055 /* 35397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14056 /* 35399 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14057 /* 35401 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14058 /* 35403 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14059 /* 35406 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14060 /* 35410 */ GIR_RootConstrainSelectedInstOperands,
14061 /* 35411 */ // GIR_Coverage, 1240,
14062 /* 35411 */ GIR_EraseRootFromParent_Done,
14063 /* 35412 */ // Label 973: @35412
14064 /* 35412 */ GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(35464), // Rule ID 1241 //
14065 /* 35417 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14066 /* 35420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
14067 /* 35425 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14068 /* 35428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14069 /* 35431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14070 /* 35434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14071 /* 35438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14072 /* 35442 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14073 /* 35446 */ // (intrinsic_w_chain:{ *:[v2i16] } 8148:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14074 /* 35446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
14075 /* 35449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14076 /* 35451 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14077 /* 35453 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14078 /* 35455 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14079 /* 35458 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14080 /* 35462 */ GIR_RootConstrainSelectedInstOperands,
14081 /* 35463 */ // GIR_Coverage, 1241,
14082 /* 35463 */ GIR_EraseRootFromParent_Done,
14083 /* 35464 */ // Label 974: @35464
14084 /* 35464 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(35516), // Rule ID 1242 //
14085 /* 35469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14086 /* 35472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
14087 /* 35477 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14088 /* 35480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14089 /* 35483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14090 /* 35486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14091 /* 35490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14092 /* 35494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14093 /* 35498 */ // (intrinsic_w_chain:{ *:[v4i8] } 8147:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14094 /* 35498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB_MM),
14095 /* 35501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14096 /* 35503 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14097 /* 35505 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14098 /* 35507 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14099 /* 35510 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14100 /* 35514 */ GIR_RootConstrainSelectedInstOperands,
14101 /* 35515 */ // GIR_Coverage, 1242,
14102 /* 35515 */ GIR_EraseRootFromParent_Done,
14103 /* 35516 */ // Label 975: @35516
14104 /* 35516 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(35568), // Rule ID 1243 //
14105 /* 35521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14106 /* 35524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
14107 /* 35529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14108 /* 35532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14109 /* 35535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14110 /* 35538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14111 /* 35542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14112 /* 35546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14113 /* 35550 */ // (intrinsic_w_chain:{ *:[i32] } 8149:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14114 /* 35550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W_MM),
14115 /* 35553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14116 /* 35555 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14117 /* 35557 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14118 /* 35559 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14119 /* 35562 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14120 /* 35566 */ GIR_RootConstrainSelectedInstOperands,
14121 /* 35567 */ // GIR_Coverage, 1243,
14122 /* 35567 */ GIR_EraseRootFromParent_Done,
14123 /* 35568 */ // Label 976: @35568
14124 /* 35568 */ GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(35620), // Rule ID 1262 //
14125 /* 35573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14126 /* 35576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
14127 /* 35581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14128 /* 35584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14129 /* 35587 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14130 /* 35590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14131 /* 35594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14132 /* 35598 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14133 /* 35602 */ // (intrinsic_w_chain:{ *:[i32] } 8221:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14134 /* 35602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W_MM),
14135 /* 35605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14136 /* 35607 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14137 /* 35609 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14138 /* 35611 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14139 /* 35614 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14140 /* 35618 */ GIR_RootConstrainSelectedInstOperands,
14141 /* 35619 */ // GIR_Coverage, 1262,
14142 /* 35619 */ GIR_EraseRootFromParent_Done,
14143 /* 35620 */ // Label 977: @35620
14144 /* 35620 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(35672), // Rule ID 1268 //
14145 /* 35625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14146 /* 35628 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
14147 /* 35633 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14148 /* 35636 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14149 /* 35639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14150 /* 35642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14151 /* 35646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14152 /* 35650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14153 /* 35654 */ // (intrinsic_w_chain:{ *:[i32] } 8067:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14154 /* 35654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
14155 /* 35657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14156 /* 35659 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14157 /* 35661 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14158 /* 35663 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14159 /* 35666 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14160 /* 35670 */ GIR_RootConstrainSelectedInstOperands,
14161 /* 35671 */ // GIR_Coverage, 1268,
14162 /* 35671 */ GIR_EraseRootFromParent_Done,
14163 /* 35672 */ // Label 978: @35672
14164 /* 35672 */ GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(35724), // Rule ID 1269 //
14165 /* 35677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14166 /* 35680 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
14167 /* 35685 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14168 /* 35688 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14169 /* 35691 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14170 /* 35694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14171 /* 35698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14172 /* 35702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14173 /* 35706 */ // (intrinsic_w_chain:{ *:[i32] } 8068:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14174 /* 35706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
14175 /* 35709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14176 /* 35711 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14177 /* 35713 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14178 /* 35715 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14179 /* 35718 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14180 /* 35722 */ GIR_RootConstrainSelectedInstOperands,
14181 /* 35723 */ // GIR_Coverage, 1269,
14182 /* 35723 */ GIR_EraseRootFromParent_Done,
14183 /* 35724 */ // Label 979: @35724
14184 /* 35724 */ GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(35776), // Rule ID 1270 //
14185 /* 35729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14186 /* 35732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
14187 /* 35737 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14188 /* 35740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14189 /* 35743 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14190 /* 35746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14191 /* 35750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14192 /* 35754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14193 /* 35758 */ // (intrinsic_w_chain:{ *:[v2i16] } 8069:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14194 /* 35758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
14195 /* 35761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14196 /* 35763 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14197 /* 35765 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14198 /* 35767 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14199 /* 35770 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14200 /* 35774 */ GIR_RootConstrainSelectedInstOperands,
14201 /* 35775 */ // GIR_Coverage, 1270,
14202 /* 35775 */ GIR_EraseRootFromParent_Done,
14203 /* 35776 */ // Label 980: @35776
14204 /* 35776 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(35828), // Rule ID 1271 //
14205 /* 35781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14206 /* 35784 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
14207 /* 35789 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14208 /* 35792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14209 /* 35795 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14210 /* 35798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14211 /* 35802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14212 /* 35806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14213 /* 35810 */ // (intrinsic_w_chain:{ *:[v2i16] } 8070:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14214 /* 35810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
14215 /* 35813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14216 /* 35815 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14217 /* 35817 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14218 /* 35819 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14219 /* 35822 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14220 /* 35826 */ GIR_RootConstrainSelectedInstOperands,
14221 /* 35827 */ // GIR_Coverage, 1271,
14222 /* 35827 */ GIR_EraseRootFromParent_Done,
14223 /* 35828 */ // Label 981: @35828
14224 /* 35828 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(35880), // Rule ID 1272 //
14225 /* 35833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14226 /* 35836 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
14227 /* 35841 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14228 /* 35844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14229 /* 35847 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14230 /* 35850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14231 /* 35854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14232 /* 35858 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14233 /* 35862 */ // (intrinsic_w_chain:{ *:[v2i16] } 8071:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14234 /* 35862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
14235 /* 35865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14236 /* 35867 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14237 /* 35869 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14238 /* 35871 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14239 /* 35874 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14240 /* 35878 */ GIR_RootConstrainSelectedInstOperands,
14241 /* 35879 */ // GIR_Coverage, 1272,
14242 /* 35879 */ GIR_EraseRootFromParent_Done,
14243 /* 35880 */ // Label 982: @35880
14244 /* 35880 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(35932), // Rule ID 1275 //
14245 /* 35885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14246 /* 35888 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
14247 /* 35893 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14248 /* 35896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14249 /* 35899 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14250 /* 35902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14251 /* 35906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14252 /* 35910 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14253 /* 35914 */ // (intrinsic_w_chain:{ *:[v4i8] } 8128:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14254 /* 35914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
14255 /* 35917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14256 /* 35919 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14257 /* 35921 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14258 /* 35923 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14259 /* 35926 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14260 /* 35930 */ GIR_RootConstrainSelectedInstOperands,
14261 /* 35931 */ // GIR_Coverage, 1275,
14262 /* 35931 */ GIR_EraseRootFromParent_Done,
14263 /* 35932 */ // Label 983: @35932
14264 /* 35932 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(35984), // Rule ID 1276 //
14265 /* 35937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14266 /* 35940 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
14267 /* 35945 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14268 /* 35948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14269 /* 35951 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14270 /* 35954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14271 /* 35958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14272 /* 35962 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14273 /* 35966 */ // (intrinsic_w_chain:{ *:[v2i16] } 8127:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14274 /* 35966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
14275 /* 35969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14276 /* 35971 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14277 /* 35973 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14278 /* 35975 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14279 /* 35978 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14280 /* 35982 */ GIR_RootConstrainSelectedInstOperands,
14281 /* 35983 */ // GIR_Coverage, 1276,
14282 /* 35983 */ GIR_EraseRootFromParent_Done,
14283 /* 35984 */ // Label 984: @35984
14284 /* 35984 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(36033), // Rule ID 1294 //
14285 /* 35989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14286 /* 35992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
14287 /* 35997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14288 /* 36000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14289 /* 36003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14290 /* 36006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14291 /* 36010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14292 /* 36014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14293 /* 36018 */ // (intrinsic_w_chain:{ *:[v2i16] } 8110:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14294 /* 36018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH_MM),
14295 /* 36021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14296 /* 36023 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14297 /* 36025 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14298 /* 36027 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14299 /* 36031 */ GIR_RootConstrainSelectedInstOperands,
14300 /* 36032 */ // GIR_Coverage, 1294,
14301 /* 36032 */ GIR_EraseRootFromParent_Done,
14302 /* 36033 */ // Label 985: @36033
14303 /* 36033 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(36082), // Rule ID 1295 //
14304 /* 36038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14305 /* 36041 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
14306 /* 36046 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14307 /* 36049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14308 /* 36052 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14309 /* 36055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14310 /* 36059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14311 /* 36063 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14312 /* 36067 */ // (intrinsic_w_chain:{ *:[v4i8] } 8111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14313 /* 36067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB_MM),
14314 /* 36070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14315 /* 36072 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14316 /* 36074 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14317 /* 36076 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14318 /* 36080 */ GIR_RootConstrainSelectedInstOperands,
14319 /* 36081 */ // GIR_Coverage, 1295,
14320 /* 36081 */ GIR_EraseRootFromParent_Done,
14321 /* 36082 */ // Label 986: @36082
14322 /* 36082 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(36131), // Rule ID 1305 //
14323 /* 36087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14324 /* 36090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
14325 /* 36095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14326 /* 36098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14327 /* 36101 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14328 /* 36104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14329 /* 36108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14330 /* 36112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14331 /* 36116 */ // (intrinsic_w_chain:{ *:[i32] } 7767:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14332 /* 36116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
14333 /* 36119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14334 /* 36121 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14335 /* 36123 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14336 /* 36125 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14337 /* 36129 */ GIR_RootConstrainSelectedInstOperands,
14338 /* 36130 */ // GIR_Coverage, 1305,
14339 /* 36130 */ GIR_EraseRootFromParent_Done,
14340 /* 36131 */ // Label 987: @36131
14341 /* 36131 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(36180), // Rule ID 1306 //
14342 /* 36136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14343 /* 36139 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
14344 /* 36144 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14345 /* 36147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14346 /* 36150 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14347 /* 36153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14348 /* 36157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14349 /* 36161 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14350 /* 36165 */ // (intrinsic_w_chain:{ *:[i32] } 7769:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14351 /* 36165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
14352 /* 36168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14353 /* 36170 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14354 /* 36172 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14355 /* 36174 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14356 /* 36178 */ GIR_RootConstrainSelectedInstOperands,
14357 /* 36179 */ // GIR_Coverage, 1306,
14358 /* 36179 */ GIR_EraseRootFromParent_Done,
14359 /* 36180 */ // Label 988: @36180
14360 /* 36180 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(36229), // Rule ID 1307 //
14361 /* 36185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14362 /* 36188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
14363 /* 36193 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14364 /* 36196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14365 /* 36199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14366 /* 36202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14367 /* 36206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14368 /* 36210 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14369 /* 36214 */ // (intrinsic_w_chain:{ *:[i32] } 7768:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14370 /* 36214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
14371 /* 36217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14372 /* 36219 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14373 /* 36221 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14374 /* 36223 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14375 /* 36227 */ GIR_RootConstrainSelectedInstOperands,
14376 /* 36228 */ // GIR_Coverage, 1307,
14377 /* 36228 */ GIR_EraseRootFromParent_Done,
14378 /* 36229 */ // Label 989: @36229
14379 /* 36229 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(36281), // Rule ID 1316 //
14380 /* 36234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14381 /* 36237 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
14382 /* 36242 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14383 /* 36245 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14384 /* 36248 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14385 /* 36251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14386 /* 36255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14387 /* 36259 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14388 /* 36263 */ // (intrinsic_w_chain:{ *:[v2i16] } 7619:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14389 /* 36263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH_MMR2),
14390 /* 36266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14391 /* 36268 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14392 /* 36270 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14393 /* 36272 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14394 /* 36275 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14395 /* 36279 */ GIR_RootConstrainSelectedInstOperands,
14396 /* 36280 */ // GIR_Coverage, 1316,
14397 /* 36280 */ GIR_EraseRootFromParent_Done,
14398 /* 36281 */ // Label 990: @36281
14399 /* 36281 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(36333), // Rule ID 1317 //
14400 /* 36286 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14401 /* 36289 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
14402 /* 36294 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14403 /* 36297 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14404 /* 36300 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14405 /* 36303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14406 /* 36307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14407 /* 36311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14408 /* 36315 */ // (intrinsic_w_chain:{ *:[v2i16] } 7621:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14409 /* 36315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
14410 /* 36318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14411 /* 36320 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14412 /* 36322 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14413 /* 36324 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14414 /* 36327 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14415 /* 36331 */ GIR_RootConstrainSelectedInstOperands,
14416 /* 36332 */ // GIR_Coverage, 1317,
14417 /* 36332 */ GIR_EraseRootFromParent_Done,
14418 /* 36333 */ // Label 991: @36333
14419 /* 36333 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(36385), // Rule ID 1328 //
14420 /* 36338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14421 /* 36341 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
14422 /* 36346 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14423 /* 36349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14424 /* 36352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14425 /* 36355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14426 /* 36359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14427 /* 36363 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14428 /* 36367 */ // (intrinsic_w_chain:{ *:[i32] } 7764:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14429 /* 36367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
14430 /* 36370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14431 /* 36372 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14432 /* 36374 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14433 /* 36376 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14434 /* 36379 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14435 /* 36383 */ GIR_RootConstrainSelectedInstOperands,
14436 /* 36384 */ // GIR_Coverage, 1328,
14437 /* 36384 */ GIR_EraseRootFromParent_Done,
14438 /* 36385 */ // Label 992: @36385
14439 /* 36385 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(36437), // Rule ID 1329 //
14440 /* 36390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14441 /* 36393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
14442 /* 36398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14443 /* 36401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14444 /* 36404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14445 /* 36407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14446 /* 36411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14447 /* 36415 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14448 /* 36419 */ // (intrinsic_w_chain:{ *:[i32] } 7766:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14449 /* 36419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
14450 /* 36422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14451 /* 36424 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14452 /* 36426 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14453 /* 36428 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14454 /* 36431 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14455 /* 36435 */ GIR_RootConstrainSelectedInstOperands,
14456 /* 36436 */ // GIR_Coverage, 1329,
14457 /* 36436 */ GIR_EraseRootFromParent_Done,
14458 /* 36437 */ // Label 993: @36437
14459 /* 36437 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(36489), // Rule ID 1330 //
14460 /* 36442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14461 /* 36445 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
14462 /* 36450 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14463 /* 36453 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14464 /* 36456 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14465 /* 36459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14466 /* 36463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14467 /* 36467 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14468 /* 36471 */ // (intrinsic_w_chain:{ *:[i32] } 7765:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14469 /* 36471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
14470 /* 36474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14471 /* 36476 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14472 /* 36478 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14473 /* 36480 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14474 /* 36483 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14475 /* 36487 */ GIR_RootConstrainSelectedInstOperands,
14476 /* 36488 */ // GIR_Coverage, 1330,
14477 /* 36488 */ GIR_EraseRootFromParent_Done,
14478 /* 36489 */ // Label 994: @36489
14479 /* 36489 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(36541), // Rule ID 1336 //
14480 /* 36494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14481 /* 36497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
14482 /* 36502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14483 /* 36505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14484 /* 36508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14485 /* 36511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14486 /* 36515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14487 /* 36519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14488 /* 36523 */ // (intrinsic_w_chain:{ *:[v2i16] } 8242:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14489 /* 36523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH_MMR2),
14490 /* 36526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14491 /* 36528 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14492 /* 36530 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14493 /* 36532 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14494 /* 36535 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14495 /* 36539 */ GIR_RootConstrainSelectedInstOperands,
14496 /* 36540 */ // GIR_Coverage, 1336,
14497 /* 36540 */ GIR_EraseRootFromParent_Done,
14498 /* 36541 */ // Label 995: @36541
14499 /* 36541 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(36593), // Rule ID 1337 //
14500 /* 36546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14501 /* 36549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
14502 /* 36554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14503 /* 36557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14504 /* 36560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14505 /* 36563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14506 /* 36567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14507 /* 36571 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14508 /* 36575 */ // (intrinsic_w_chain:{ *:[v2i16] } 8244:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14509 /* 36575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH_MMR2),
14510 /* 36578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14511 /* 36580 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14512 /* 36582 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14513 /* 36584 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14514 /* 36587 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14515 /* 36591 */ GIR_RootConstrainSelectedInstOperands,
14516 /* 36592 */ // GIR_Coverage, 1337,
14517 /* 36592 */ GIR_EraseRootFromParent_Done,
14518 /* 36593 */ // Label 996: @36593
14519 /* 36593 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(36645), // Rule ID 1344 //
14520 /* 36598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14521 /* 36601 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
14522 /* 36606 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14523 /* 36609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14524 /* 36612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14525 /* 36615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14526 /* 36619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14527 /* 36623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14528 /* 36627 */ // (intrinsic_w_chain:{ *:[v2i16] } 8066:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14529 /* 36627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH_MMR2),
14530 /* 36630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14531 /* 36632 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14532 /* 36634 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14533 /* 36636 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14534 /* 36639 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14535 /* 36643 */ GIR_RootConstrainSelectedInstOperands,
14536 /* 36644 */ // GIR_Coverage, 1344,
14537 /* 36644 */ GIR_EraseRootFromParent_Done,
14538 /* 36645 */ // Label 997: @36645
14539 /* 36645 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(36697), // Rule ID 1345 //
14540 /* 36650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14541 /* 36653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
14542 /* 36658 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14543 /* 36661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14544 /* 36664 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14545 /* 36667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14546 /* 36671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14547 /* 36675 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14548 /* 36679 */ // (intrinsic_w_chain:{ *:[i32] } 8072:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14549 /* 36679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W_MMR2),
14550 /* 36682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14551 /* 36684 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14552 /* 36686 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14553 /* 36688 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14554 /* 36691 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14555 /* 36695 */ GIR_RootConstrainSelectedInstOperands,
14556 /* 36696 */ // GIR_Coverage, 1345,
14557 /* 36696 */ GIR_EraseRootFromParent_Done,
14558 /* 36697 */ // Label 998: @36697
14559 /* 36697 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(36749), // Rule ID 1346 //
14560 /* 36702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14561 /* 36705 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
14562 /* 36710 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14563 /* 36713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14564 /* 36716 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14565 /* 36719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14566 /* 36723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14567 /* 36727 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14568 /* 36731 */ // (intrinsic_w_chain:{ *:[v2i16] } 8073:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14569 /* 36731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH_MMR2),
14570 /* 36734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14571 /* 36736 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14572 /* 36738 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14573 /* 36740 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14574 /* 36743 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14575 /* 36747 */ GIR_RootConstrainSelectedInstOperands,
14576 /* 36748 */ // GIR_Coverage, 1346,
14577 /* 36748 */ GIR_EraseRootFromParent_Done,
14578 /* 36749 */ // Label 999: @36749
14579 /* 36749 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(36801), // Rule ID 1347 //
14580 /* 36754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14581 /* 36757 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
14582 /* 36762 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14583 /* 36765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14584 /* 36768 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14585 /* 36771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14586 /* 36775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14587 /* 36779 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14588 /* 36783 */ // (intrinsic_w_chain:{ *:[i32] } 8074:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14589 /* 36783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W_MMR2),
14590 /* 36786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14591 /* 36788 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14592 /* 36790 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14593 /* 36792 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14594 /* 36795 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14595 /* 36799 */ GIR_RootConstrainSelectedInstOperands,
14596 /* 36800 */ // GIR_Coverage, 1347,
14597 /* 36800 */ GIR_EraseRootFromParent_Done,
14598 /* 36801 */ // Label 1000: @36801
14599 /* 36801 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(36850), // Rule ID 1348 //
14600 /* 36806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
14601 /* 36809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
14602 /* 36814 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14603 /* 36817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14604 /* 36820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14605 /* 36823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14606 /* 36827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14607 /* 36831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14608 /* 36835 */ // (intrinsic_w_chain:{ *:[v4i8] } 8122:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14609 /* 36835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH_MMR2),
14610 /* 36838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14611 /* 36840 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14612 /* 36842 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14613 /* 36844 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14614 /* 36848 */ GIR_RootConstrainSelectedInstOperands,
14615 /* 36849 */ // GIR_Coverage, 1348,
14616 /* 36849 */ GIR_EraseRootFromParent_Done,
14617 /* 36850 */ // Label 1001: @36850
14618 /* 36850 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(36894), // Rule ID 1929 //
14619 /* 36855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14620 /* 36858 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_ph),
14621 /* 36863 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14622 /* 36866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14623 /* 36869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14624 /* 36872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14625 /* 36876 */ // (intrinsic_w_chain:{ *:[v2i16] } 8063:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
14626 /* 36876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
14627 /* 36879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14628 /* 36881 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14629 /* 36883 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14630 /* 36885 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14631 /* 36888 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14632 /* 36892 */ GIR_RootConstrainSelectedInstOperands,
14633 /* 36893 */ // GIR_Coverage, 1929,
14634 /* 36893 */ GIR_EraseRootFromParent_Done,
14635 /* 36894 */ // Label 1002: @36894
14636 /* 36894 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(36938), // Rule ID 1935 //
14637 /* 36899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14638 /* 36902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addsc),
14639 /* 36907 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14640 /* 36910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14641 /* 36913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14642 /* 36916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14643 /* 36920 */ // (intrinsic_w_chain:{ *:[i32] } 7618:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
14644 /* 36920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDSC),
14645 /* 36923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14646 /* 36925 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14647 /* 36927 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14648 /* 36929 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCarry*/0,
14649 /* 36932 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14650 /* 36936 */ GIR_RootConstrainSelectedInstOperands,
14651 /* 36937 */ // GIR_Coverage, 1935,
14652 /* 36937 */ GIR_EraseRootFromParent_Done,
14653 /* 36938 */ // Label 1003: @36938
14654 /* 36938 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(36982), // Rule ID 1937 //
14655 /* 36943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14656 /* 36946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addwc),
14657 /* 36951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14658 /* 36954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14659 /* 36957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14660 /* 36960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14661 /* 36964 */ // (intrinsic_w_chain:{ *:[i32] } 7633:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
14662 /* 36964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDWC),
14663 /* 36967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14664 /* 36969 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14665 /* 36971 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14666 /* 36973 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14667 /* 36976 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14668 /* 36980 */ GIR_RootConstrainSelectedInstOperands,
14669 /* 36981 */ // GIR_Coverage, 1937,
14670 /* 36981 */ GIR_EraseRootFromParent_Done,
14671 /* 36982 */ // Label 1004: @36982
14672 /* 36982 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(37028), // Rule ID 487 //
14673 /* 36987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
14674 /* 36990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_d),
14675 /* 36995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
14676 /* 36998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14677 /* 37001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14678 /* 37005 */ // MIs[0] ptr
14679 /* 37005 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14680 /* 37009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14681 /* 37013 */ // (intrinsic_w_chain:{ *:[v2i64] } 7983:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_D:{ *:[v2i64] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14682 /* 37013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_D),
14683 /* 37016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14684 /* 37018 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14685 /* 37020 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14686 /* 37022 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14687 /* 37026 */ GIR_RootConstrainSelectedInstOperands,
14688 /* 37027 */ // GIR_Coverage, 487,
14689 /* 37027 */ GIR_EraseRootFromParent_Done,
14690 /* 37028 */ // Label 1005: @37028
14691 /* 37028 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(37074), // Rule ID 488 //
14692 /* 37033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
14693 /* 37036 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_w),
14694 /* 37041 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
14695 /* 37044 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14696 /* 37047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14697 /* 37051 */ // MIs[0] ptr
14698 /* 37051 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14699 /* 37055 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14700 /* 37059 */ // (intrinsic_w_chain:{ *:[v4i32] } 7984:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_W:{ *:[v4i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14701 /* 37059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_W),
14702 /* 37062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14703 /* 37064 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14704 /* 37066 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14705 /* 37068 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14706 /* 37072 */ GIR_RootConstrainSelectedInstOperands,
14707 /* 37073 */ // GIR_Coverage, 488,
14708 /* 37073 */ GIR_EraseRootFromParent_Done,
14709 /* 37074 */ // Label 1006: @37074
14710 /* 37074 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(37116), // Rule ID 434 //
14711 /* 37079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14712 /* 37082 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
14713 /* 37087 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14714 /* 37090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14715 /* 37093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14716 /* 37097 */ // MIs[0] base
14717 /* 37097 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14718 /* 37101 */ // (intrinsic_w_chain:{ *:[i32] } 7987:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14719 /* 37101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
14720 /* 37104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14721 /* 37106 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14722 /* 37108 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14723 /* 37110 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14724 /* 37114 */ GIR_RootConstrainSelectedInstOperands,
14725 /* 37115 */ // GIR_Coverage, 434,
14726 /* 37115 */ GIR_EraseRootFromParent_Done,
14727 /* 37116 */ // Label 1007: @37116
14728 /* 37116 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(37158), // Rule ID 435 //
14729 /* 37121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14730 /* 37124 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
14731 /* 37129 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14732 /* 37132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14733 /* 37135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14734 /* 37139 */ // MIs[0] base
14735 /* 37139 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14736 /* 37143 */ // (intrinsic_w_chain:{ *:[i32] } 7985:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14737 /* 37143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
14738 /* 37146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14739 /* 37148 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14740 /* 37150 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14741 /* 37152 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14742 /* 37156 */ GIR_RootConstrainSelectedInstOperands,
14743 /* 37157 */ // GIR_Coverage, 435,
14744 /* 37157 */ GIR_EraseRootFromParent_Done,
14745 /* 37158 */ // Label 1008: @37158
14746 /* 37158 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(37200), // Rule ID 436 //
14747 /* 37163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14748 /* 37166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
14749 /* 37171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14750 /* 37174 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14751 /* 37177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14752 /* 37181 */ // MIs[0] base
14753 /* 37181 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14754 /* 37185 */ // (intrinsic_w_chain:{ *:[i32] } 7974:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14755 /* 37185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
14756 /* 37188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14757 /* 37190 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14758 /* 37192 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14759 /* 37194 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14760 /* 37198 */ GIR_RootConstrainSelectedInstOperands,
14761 /* 37199 */ // GIR_Coverage, 436,
14762 /* 37199 */ GIR_EraseRootFromParent_Done,
14763 /* 37200 */ // Label 1009: @37200
14764 /* 37200 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(37242), // Rule ID 1277 //
14765 /* 37205 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14766 /* 37208 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
14767 /* 37213 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14768 /* 37216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14769 /* 37219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14770 /* 37223 */ // MIs[0] base
14771 /* 37223 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14772 /* 37227 */ // (intrinsic_w_chain:{ *:[i32] } 7974:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14773 /* 37227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX_MM),
14774 /* 37230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14775 /* 37232 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14776 /* 37234 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14777 /* 37236 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14778 /* 37240 */ GIR_RootConstrainSelectedInstOperands,
14779 /* 37241 */ // GIR_Coverage, 1277,
14780 /* 37241 */ GIR_EraseRootFromParent_Done,
14781 /* 37242 */ // Label 1010: @37242
14782 /* 37242 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(37284), // Rule ID 1278 //
14783 /* 37247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14784 /* 37250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
14785 /* 37255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14786 /* 37258 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14787 /* 37261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14788 /* 37265 */ // MIs[0] base
14789 /* 37265 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14790 /* 37269 */ // (intrinsic_w_chain:{ *:[i32] } 7985:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14791 /* 37269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX_MM),
14792 /* 37272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14793 /* 37274 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14794 /* 37276 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14795 /* 37278 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14796 /* 37282 */ GIR_RootConstrainSelectedInstOperands,
14797 /* 37283 */ // GIR_Coverage, 1278,
14798 /* 37283 */ GIR_EraseRootFromParent_Done,
14799 /* 37284 */ // Label 1011: @37284
14800 /* 37284 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(37326), // Rule ID 1279 //
14801 /* 37289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14802 /* 37292 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
14803 /* 37297 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14804 /* 37300 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14805 /* 37303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14806 /* 37307 */ // MIs[0] base
14807 /* 37307 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14808 /* 37311 */ // (intrinsic_w_chain:{ *:[i32] } 7987:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14809 /* 37311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX_MM),
14810 /* 37314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14811 /* 37316 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14812 /* 37318 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14813 /* 37320 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14814 /* 37324 */ GIR_RootConstrainSelectedInstOperands,
14815 /* 37325 */ // GIR_Coverage, 1279,
14816 /* 37325 */ GIR_EraseRootFromParent_Done,
14817 /* 37326 */ // Label 1012: @37326
14818 /* 37326 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(37372), // Rule ID 489 //
14819 /* 37331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
14820 /* 37334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_d),
14821 /* 37339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14822 /* 37342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14823 /* 37345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14824 /* 37349 */ // MIs[0] ptr
14825 /* 37349 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14826 /* 37353 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14827 /* 37357 */ // (intrinsic_void 8217:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_D MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14828 /* 37357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_D),
14829 /* 37360 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
14830 /* 37362 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14831 /* 37364 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14832 /* 37366 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14833 /* 37370 */ GIR_RootConstrainSelectedInstOperands,
14834 /* 37371 */ // GIR_Coverage, 489,
14835 /* 37371 */ GIR_EraseRootFromParent_Done,
14836 /* 37372 */ // Label 1013: @37372
14837 /* 37372 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(37418), // Rule ID 490 //
14838 /* 37377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
14839 /* 37380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_w),
14840 /* 37385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14841 /* 37388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14842 /* 37391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14843 /* 37395 */ // MIs[0] ptr
14844 /* 37395 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14845 /* 37399 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14846 /* 37403 */ // (intrinsic_void 8218:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_W MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14847 /* 37403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_W),
14848 /* 37406 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
14849 /* 37408 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14850 /* 37410 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14851 /* 37412 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14852 /* 37416 */ GIR_RootConstrainSelectedInstOperands,
14853 /* 37417 */ // GIR_Coverage, 490,
14854 /* 37417 */ GIR_EraseRootFromParent_Done,
14855 /* 37418 */ // Label 1014: @37418
14856 /* 37418 */ GIM_Reject,
14857 /* 37419 */ // Label 933: @37419
14858 /* 37419 */ GIM_Reject,
14859 /* 37420 */ // Label 31: @37420
14860 /* 37420 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(37485), // Rule ID 1582 //
14861 /* 37425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
14862 /* 37428 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
14863 /* 37431 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14864 /* 37434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14865 /* 37438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14866 /* 37442 */ // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
14867 /* 37442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14868 /* 37445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14869 /* 37449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14870 /* 37454 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14871 /* 37456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14872 /* 37459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14873 /* 37461 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14874 /* 37464 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14875 /* 37466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14876 /* 37469 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14877 /* 37474 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14878 /* 37479 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14879 /* 37484 */ // GIR_Coverage, 1582,
14880 /* 37484 */ GIR_EraseRootFromParent_Done,
14881 /* 37485 */ // Label 1015: @37485
14882 /* 37485 */ GIM_Reject,
14883 /* 37486 */ // Label 32: @37486
14884 /* 37486 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(37549), // Rule ID 1575 //
14885 /* 37491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
14886 /* 37494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14887 /* 37497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14888 /* 37500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14889 /* 37504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14890 /* 37508 */ // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
14891 /* 37508 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14892 /* 37511 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14893 /* 37515 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14894 /* 37520 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
14895 /* 37526 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
14896 /* 37531 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14897 /* 37536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
14898 /* 37539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14899 /* 37541 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14900 /* 37544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14901 /* 37547 */ GIR_RootConstrainSelectedInstOperands,
14902 /* 37548 */ // GIR_Coverage, 1575,
14903 /* 37548 */ GIR_EraseRootFromParent_Done,
14904 /* 37549 */ // Label 1016: @37549
14905 /* 37549 */ GIM_Reject,
14906 /* 37550 */ // Label 33: @37550
14907 /* 37550 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(37610),
14908 /* 37555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14909 /* 37558 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(37584), // Rule ID 2162 //
14910 /* 37563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
14911 /* 37566 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immLi16),
14912 /* 37570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
14913 /* 37574 */ // MIs[0] Operand 1
14914 /* 37574 */ // No operand predicates
14915 /* 37574 */ // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
14916 /* 37574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LI16_MM),
14917 /* 37577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14918 /* 37579 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
14919 /* 37582 */ GIR_RootConstrainSelectedInstOperands,
14920 /* 37583 */ // GIR_Coverage, 2162,
14921 /* 37583 */ GIR_EraseRootFromParent_Done,
14922 /* 37584 */ // Label 1018: @37584
14923 /* 37584 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(37609), // Rule ID 1853 //
14924 /* 37589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
14925 /* 37592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14926 /* 37596 */ // MIs[0] Operand 1
14927 /* 37596 */ // No operand predicates
14928 /* 37596 */ // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
14929 /* 37596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LwConstant32),
14930 /* 37599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
14931 /* 37601 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
14932 /* 37604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1),
14933 /* 37607 */ GIR_RootConstrainSelectedInstOperands,
14934 /* 37608 */ // GIR_Coverage, 1853,
14935 /* 37608 */ GIR_EraseRootFromParent_Done,
14936 /* 37609 */ // Label 1019: @37609
14937 /* 37609 */ GIM_Reject,
14938 /* 37610 */ // Label 1017: @37610
14939 /* 37610 */ GIM_Reject,
14940 /* 37611 */ // Label 34: @37611
14941 /* 37611 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(39074),
14942 /* 37616 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
14943 /* 37619 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14944 /* 37622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14945 /* 37626 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(37731), // Rule ID 1631 //
14946 /* 37631 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14947 /* 37635 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
14948 /* 37639 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14949 /* 37643 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14950 /* 37647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14951 /* 37652 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14952 /* 37656 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14953 /* 37660 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14954 /* 37664 */ // MIs[2] Operand 1
14955 /* 37664 */ // No operand predicates
14956 /* 37664 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14957 /* 37666 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14958 /* 37666 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14959 /* 37669 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRA),
14960 /* 37673 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14961 /* 37678 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14962 /* 37682 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14963 /* 37685 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14964 /* 37687 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14965 /* 37690 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14966 /* 37694 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14967 /* 37699 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14968 /* 37701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14969 /* 37704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14970 /* 37706 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14971 /* 37709 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14972 /* 37712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14973 /* 37715 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14974 /* 37720 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14975 /* 37725 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14976 /* 37730 */ // GIR_Coverage, 1631,
14977 /* 37730 */ GIR_EraseRootFromParent_Done,
14978 /* 37731 */ // Label 1021: @37731
14979 /* 37731 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(37836), // Rule ID 1627 //
14980 /* 37736 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14981 /* 37740 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
14982 /* 37744 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14983 /* 37748 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14984 /* 37752 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14985 /* 37757 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14986 /* 37761 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14987 /* 37765 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14988 /* 37769 */ // MIs[2] Operand 1
14989 /* 37769 */ // No operand predicates
14990 /* 37769 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14991 /* 37771 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14992 /* 37771 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14993 /* 37774 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRL),
14994 /* 37778 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14995 /* 37783 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14996 /* 37787 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14997 /* 37790 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14998 /* 37792 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14999 /* 37795 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15000 /* 37799 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15001 /* 37804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15002 /* 37806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15003 /* 37809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15004 /* 37811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15005 /* 37814 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15006 /* 37817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15007 /* 37820 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15008 /* 37825 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15009 /* 37830 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15010 /* 37835 */ // GIR_Coverage, 1627,
15011 /* 37835 */ GIR_EraseRootFromParent_Done,
15012 /* 37836 */ // Label 1022: @37836
15013 /* 37836 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(37941), // Rule ID 1623 //
15014 /* 37841 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15015 /* 37845 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
15016 /* 37849 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15017 /* 37853 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15018 /* 37857 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15019 /* 37862 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15020 /* 37866 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15021 /* 37870 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15022 /* 37874 */ // MIs[2] Operand 1
15023 /* 37874 */ // No operand predicates
15024 /* 37874 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15025 /* 37876 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
15026 /* 37876 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15027 /* 37879 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL),
15028 /* 37883 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15029 /* 37888 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15030 /* 37892 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
15031 /* 37895 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15032 /* 37897 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15033 /* 37900 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15034 /* 37904 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15035 /* 37909 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15036 /* 37911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15037 /* 37914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15038 /* 37916 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15039 /* 37919 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15040 /* 37922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15041 /* 37925 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15042 /* 37930 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15043 /* 37935 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15044 /* 37940 */ // GIR_Coverage, 1623,
15045 /* 37940 */ GIR_EraseRootFromParent_Done,
15046 /* 37941 */ // Label 1023: @37941
15047 /* 37941 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(38040), // Rule ID 1613 //
15048 /* 37946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15049 /* 37950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
15050 /* 37954 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15051 /* 37958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15052 /* 37962 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15053 /* 37967 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15054 /* 37972 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15055 /* 37974 */ // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15056 /* 37974 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15057 /* 37977 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::ADDu),
15058 /* 37981 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15059 /* 37986 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15060 /* 37990 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15061 /* 37994 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15062 /* 37996 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15063 /* 37999 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15064 /* 38003 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15065 /* 38008 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15066 /* 38010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15067 /* 38013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15068 /* 38015 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15069 /* 38018 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15070 /* 38021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15071 /* 38024 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15072 /* 38029 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15073 /* 38034 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15074 /* 38039 */ // GIR_Coverage, 1613,
15075 /* 38039 */ GIR_EraseRootFromParent_Done,
15076 /* 38040 */ // Label 1024: @38040
15077 /* 38040 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(38139), // Rule ID 1633 //
15078 /* 38045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15079 /* 38049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
15080 /* 38053 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15081 /* 38057 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15082 /* 38061 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15083 /* 38066 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15084 /* 38071 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15085 /* 38073 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15086 /* 38073 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15087 /* 38076 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRAV),
15088 /* 38080 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15089 /* 38085 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15090 /* 38089 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15091 /* 38093 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15092 /* 38095 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15093 /* 38098 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15094 /* 38102 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15095 /* 38107 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15096 /* 38109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15097 /* 38112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15098 /* 38114 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15099 /* 38117 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15100 /* 38120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15101 /* 38123 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15102 /* 38128 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15103 /* 38133 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15104 /* 38138 */ // GIR_Coverage, 1633,
15105 /* 38138 */ GIR_EraseRootFromParent_Done,
15106 /* 38139 */ // Label 1025: @38139
15107 /* 38139 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(38238), // Rule ID 1629 //
15108 /* 38144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15109 /* 38148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
15110 /* 38152 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15111 /* 38156 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15112 /* 38160 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15113 /* 38165 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15114 /* 38170 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15115 /* 38172 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15116 /* 38172 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15117 /* 38175 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRLV),
15118 /* 38179 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15119 /* 38184 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15120 /* 38188 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15121 /* 38192 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15122 /* 38194 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15123 /* 38197 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15124 /* 38201 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15125 /* 38206 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15126 /* 38208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15127 /* 38211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15128 /* 38213 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15129 /* 38216 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15130 /* 38219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15131 /* 38222 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15132 /* 38227 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15133 /* 38232 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15134 /* 38237 */ // GIR_Coverage, 1629,
15135 /* 38237 */ GIR_EraseRootFromParent_Done,
15136 /* 38238 */ // Label 1026: @38238
15137 /* 38238 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(38346), // Rule ID 1617 //
15138 /* 38243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6),
15139 /* 38246 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15140 /* 38250 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
15141 /* 38254 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15142 /* 38258 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15143 /* 38262 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15144 /* 38267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15145 /* 38272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15146 /* 38274 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15147 /* 38274 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15148 /* 38277 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL),
15149 /* 38281 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15150 /* 38286 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15151 /* 38290 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15152 /* 38294 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::HI0*/0,
15153 /* 38297 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::LO0*/1,
15154 /* 38300 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15155 /* 38302 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15156 /* 38305 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15157 /* 38309 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15158 /* 38314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15159 /* 38316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15160 /* 38319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15161 /* 38321 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15162 /* 38324 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15163 /* 38327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15164 /* 38330 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15165 /* 38335 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15166 /* 38340 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15167 /* 38345 */ // GIR_Coverage, 1617,
15168 /* 38345 */ GIR_EraseRootFromParent_Done,
15169 /* 38346 */ // Label 1027: @38346
15170 /* 38346 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(38448), // Rule ID 1820 //
15171 /* 38351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15172 /* 38354 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15173 /* 38358 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
15174 /* 38362 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15175 /* 38366 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15176 /* 38370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15177 /* 38375 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15178 /* 38380 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15179 /* 38382 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15180 /* 38382 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15181 /* 38385 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
15182 /* 38389 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15183 /* 38394 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15184 /* 38398 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15185 /* 38402 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15186 /* 38404 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15187 /* 38407 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15188 /* 38411 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15189 /* 38416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15190 /* 38418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15191 /* 38421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15192 /* 38423 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15193 /* 38426 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15194 /* 38429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15195 /* 38432 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15196 /* 38437 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15197 /* 38442 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15198 /* 38447 */ // GIR_Coverage, 1820,
15199 /* 38447 */ GIR_EraseRootFromParent_Done,
15200 /* 38448 */ // Label 1028: @38448
15201 /* 38448 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(38550), // Rule ID 1821 //
15202 /* 38453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15203 /* 38456 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15204 /* 38460 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SDIV),
15205 /* 38464 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15206 /* 38468 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15207 /* 38472 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15208 /* 38477 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15209 /* 38482 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15210 /* 38484 */ // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15211 /* 38484 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15212 /* 38487 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIV),
15213 /* 38491 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15214 /* 38496 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15215 /* 38500 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15216 /* 38504 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15217 /* 38506 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15218 /* 38509 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15219 /* 38513 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15220 /* 38518 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15221 /* 38520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15222 /* 38523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15223 /* 38525 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15224 /* 38528 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15225 /* 38531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15226 /* 38534 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15227 /* 38539 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15228 /* 38544 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15229 /* 38549 */ // GIR_Coverage, 1821,
15230 /* 38549 */ GIR_EraseRootFromParent_Done,
15231 /* 38550 */ // Label 1029: @38550
15232 /* 38550 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(38649), // Rule ID 1625 //
15233 /* 38555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15234 /* 38559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
15235 /* 38563 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15236 /* 38567 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15237 /* 38571 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15238 /* 38576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15239 /* 38581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15240 /* 38583 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15241 /* 38583 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15242 /* 38586 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLLV),
15243 /* 38590 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15244 /* 38595 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15245 /* 38599 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15246 /* 38603 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15247 /* 38605 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15248 /* 38608 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15249 /* 38612 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15250 /* 38617 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15251 /* 38619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15252 /* 38622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15253 /* 38624 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15254 /* 38627 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15255 /* 38630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15256 /* 38633 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15257 /* 38638 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15258 /* 38643 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15259 /* 38648 */ // GIR_Coverage, 1625,
15260 /* 38648 */ GIR_EraseRootFromParent_Done,
15261 /* 38649 */ // Label 1030: @38649
15262 /* 38649 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(38751), // Rule ID 1823 //
15263 /* 38654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15264 /* 38657 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15265 /* 38661 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SREM),
15266 /* 38665 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15267 /* 38669 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15268 /* 38673 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15269 /* 38678 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15270 /* 38683 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15271 /* 38685 */ // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15272 /* 38685 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15273 /* 38688 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MOD),
15274 /* 38692 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15275 /* 38697 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15276 /* 38701 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15277 /* 38705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15278 /* 38707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15279 /* 38710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15280 /* 38714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15281 /* 38719 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15282 /* 38721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15283 /* 38724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15284 /* 38726 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15285 /* 38729 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15286 /* 38732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15287 /* 38735 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15288 /* 38740 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15289 /* 38745 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15290 /* 38750 */ // GIR_Coverage, 1823,
15291 /* 38750 */ GIR_EraseRootFromParent_Done,
15292 /* 38751 */ // Label 1031: @38751
15293 /* 38751 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(38850), // Rule ID 1615 //
15294 /* 38756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15295 /* 38760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
15296 /* 38764 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15297 /* 38768 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15298 /* 38772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15299 /* 38777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15300 /* 38782 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15301 /* 38784 */ // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15302 /* 38784 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15303 /* 38787 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SUBu),
15304 /* 38791 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15305 /* 38796 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15306 /* 38800 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15307 /* 38804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15308 /* 38806 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15309 /* 38809 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15310 /* 38813 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15311 /* 38818 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15312 /* 38820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15313 /* 38823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15314 /* 38825 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15315 /* 38828 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15316 /* 38831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15317 /* 38834 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15318 /* 38839 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15319 /* 38844 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15320 /* 38849 */ // GIR_Coverage, 1615,
15321 /* 38849 */ GIR_EraseRootFromParent_Done,
15322 /* 38850 */ // Label 1032: @38850
15323 /* 38850 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(38952), // Rule ID 1822 //
15324 /* 38855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15325 /* 38858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15326 /* 38862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UDIV),
15327 /* 38866 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15328 /* 38870 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15329 /* 38874 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15330 /* 38879 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15331 /* 38884 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15332 /* 38886 */ // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15333 /* 38886 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15334 /* 38889 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIVU),
15335 /* 38893 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15336 /* 38898 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15337 /* 38902 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15338 /* 38906 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15339 /* 38908 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15340 /* 38911 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15341 /* 38915 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15342 /* 38920 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15343 /* 38922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15344 /* 38925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15345 /* 38927 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15346 /* 38930 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15347 /* 38933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15348 /* 38936 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15349 /* 38941 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15350 /* 38946 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15351 /* 38951 */ // GIR_Coverage, 1822,
15352 /* 38951 */ GIR_EraseRootFromParent_Done,
15353 /* 38952 */ // Label 1033: @38952
15354 /* 38952 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(39054), // Rule ID 1824 //
15355 /* 38957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15356 /* 38960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15357 /* 38964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UREM),
15358 /* 38968 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15359 /* 38972 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15360 /* 38976 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15361 /* 38981 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15362 /* 38986 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15363 /* 38988 */ // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15364 /* 38988 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15365 /* 38991 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MODU),
15366 /* 38995 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15367 /* 39000 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15368 /* 39004 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15369 /* 39008 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15370 /* 39010 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15371 /* 39013 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15372 /* 39017 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15373 /* 39022 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15374 /* 39024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15375 /* 39027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15376 /* 39029 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15377 /* 39032 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15378 /* 39035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15379 /* 39038 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15380 /* 39043 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15381 /* 39048 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15382 /* 39053 */ // GIR_Coverage, 1824,
15383 /* 39053 */ GIR_EraseRootFromParent_Done,
15384 /* 39054 */ // Label 1034: @39054
15385 /* 39054 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(39073), // Rule ID 1585 //
15386 /* 39059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15387 /* 39062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15388 /* 39066 */ // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
15389 /* 39066 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
15390 /* 39071 */ GIR_RootConstrainSelectedInstOperands,
15391 /* 39072 */ // GIR_Coverage, 1585,
15392 /* 39072 */ GIR_Done,
15393 /* 39073 */ // Label 1035: @39073
15394 /* 39073 */ GIM_Reject,
15395 /* 39074 */ // Label 1020: @39074
15396 /* 39074 */ GIM_Reject,
15397 /* 39075 */ // Label 35: @39075
15398 /* 39075 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1038*/ GIMT_Encode4(39422),
15399 /* 39086 */ /*GILLT_s32*//*Label 1036*/ GIMT_Encode4(39094),
15400 /* 39090 */ /*GILLT_s64*//*Label 1037*/ GIMT_Encode4(39320),
15401 /* 39094 */ // Label 1036: @39094
15402 /* 39094 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(39319),
15403 /* 39099 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15404 /* 39102 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(39138), // Rule ID 106 //
15405 /* 39107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
15406 /* 39110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15407 /* 39114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15408 /* 39118 */ // MIs[0] Operand 2
15409 /* 39118 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15410 /* 39129 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15411 /* 39129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB),
15412 /* 39132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15413 /* 39134 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15414 /* 39136 */ GIR_RootConstrainSelectedInstOperands,
15415 /* 39137 */ // GIR_Coverage, 106,
15416 /* 39137 */ GIR_EraseRootFromParent_Done,
15417 /* 39138 */ // Label 1040: @39138
15418 /* 39138 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(39174), // Rule ID 107 //
15419 /* 39143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
15420 /* 39146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15421 /* 39150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15422 /* 39154 */ // MIs[0] Operand 2
15423 /* 39154 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15424 /* 39165 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15425 /* 39165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH),
15426 /* 39168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15427 /* 39170 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15428 /* 39172 */ GIR_RootConstrainSelectedInstOperands,
15429 /* 39173 */ // GIR_Coverage, 107,
15430 /* 39173 */ GIR_EraseRootFromParent_Done,
15431 /* 39174 */ // Label 1041: @39174
15432 /* 39174 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(39210), // Rule ID 1101 //
15433 /* 39179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15434 /* 39182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15435 /* 39186 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15436 /* 39190 */ // MIs[0] Operand 2
15437 /* 39190 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15438 /* 39201 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15439 /* 39201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB_MM),
15440 /* 39204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15441 /* 39206 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15442 /* 39208 */ GIR_RootConstrainSelectedInstOperands,
15443 /* 39209 */ // GIR_Coverage, 1101,
15444 /* 39209 */ GIR_EraseRootFromParent_Done,
15445 /* 39210 */ // Label 1042: @39210
15446 /* 39210 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(39246), // Rule ID 1102 //
15447 /* 39215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15448 /* 39218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15449 /* 39222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15450 /* 39226 */ // MIs[0] Operand 2
15451 /* 39226 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15452 /* 39237 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15453 /* 39237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH_MM),
15454 /* 39240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15455 /* 39242 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15456 /* 39244 */ GIR_RootConstrainSelectedInstOperands,
15457 /* 39245 */ // GIR_Coverage, 1102,
15458 /* 39245 */ GIR_EraseRootFromParent_Done,
15459 /* 39246 */ // Label 1043: @39246
15460 /* 39246 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(39282), // Rule ID 1911 //
15461 /* 39251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15462 /* 39254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15463 /* 39258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15464 /* 39262 */ // MIs[0] Operand 2
15465 /* 39262 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15466 /* 39273 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i8:{ *:[Other] }) => (SebRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
15467 /* 39273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SebRx16),
15468 /* 39276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15469 /* 39278 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
15470 /* 39280 */ GIR_RootConstrainSelectedInstOperands,
15471 /* 39281 */ // GIR_Coverage, 1911,
15472 /* 39281 */ GIR_EraseRootFromParent_Done,
15473 /* 39282 */ // Label 1044: @39282
15474 /* 39282 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(39318), // Rule ID 1912 //
15475 /* 39287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15476 /* 39290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15477 /* 39294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15478 /* 39298 */ // MIs[0] Operand 2
15479 /* 39298 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15480 /* 39309 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i16:{ *:[Other] }) => (SehRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
15481 /* 39309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SehRx16),
15482 /* 39312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15483 /* 39314 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
15484 /* 39316 */ GIR_RootConstrainSelectedInstOperands,
15485 /* 39317 */ // GIR_Coverage, 1912,
15486 /* 39317 */ GIR_EraseRootFromParent_Done,
15487 /* 39318 */ // Label 1045: @39318
15488 /* 39318 */ GIM_Reject,
15489 /* 39319 */ // Label 1039: @39319
15490 /* 39319 */ GIM_Reject,
15491 /* 39320 */ // Label 1037: @39320
15492 /* 39320 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(39421),
15493 /* 39325 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15494 /* 39328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15495 /* 39332 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15496 /* 39336 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(39364), // Rule ID 261 //
15497 /* 39341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit),
15498 /* 39344 */ // MIs[0] Operand 2
15499 /* 39344 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15500 /* 39355 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i8:{ *:[Other] }) => (SEB64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
15501 /* 39355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB64),
15502 /* 39358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15503 /* 39360 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15504 /* 39362 */ GIR_RootConstrainSelectedInstOperands,
15505 /* 39363 */ // GIR_Coverage, 261,
15506 /* 39363 */ GIR_EraseRootFromParent_Done,
15507 /* 39364 */ // Label 1047: @39364
15508 /* 39364 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(39392), // Rule ID 262 //
15509 /* 39369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit),
15510 /* 39372 */ // MIs[0] Operand 2
15511 /* 39372 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15512 /* 39383 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i16:{ *:[Other] }) => (SEH64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
15513 /* 39383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH64),
15514 /* 39386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15515 /* 39388 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15516 /* 39390 */ GIR_RootConstrainSelectedInstOperands,
15517 /* 39391 */ // GIR_Coverage, 262,
15518 /* 39391 */ GIR_EraseRootFromParent_Done,
15519 /* 39392 */ // Label 1048: @39392
15520 /* 39392 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(39420), // Rule ID 1588 //
15521 /* 39397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15522 /* 39400 */ // MIs[0] Operand 2
15523 /* 39400 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
15524 /* 39411 */ // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] }) => (SLL64_64:{ *:[i64] } GPR64:{ *:[i64] }:$src)
15525 /* 39411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL64_64),
15526 /* 39414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15527 /* 39416 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15528 /* 39418 */ GIR_RootConstrainSelectedInstOperands,
15529 /* 39419 */ // GIR_Coverage, 1588,
15530 /* 39419 */ GIR_EraseRootFromParent_Done,
15531 /* 39420 */ // Label 1049: @39420
15532 /* 39420 */ GIM_Reject,
15533 /* 39421 */ // Label 1046: @39421
15534 /* 39421 */ GIM_Reject,
15535 /* 39422 */ // Label 1038: @39422
15536 /* 39422 */ GIM_Reject,
15537 /* 39423 */ // Label 36: @39423
15538 /* 39423 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(39623),
15539 /* 39428 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15540 /* 39431 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15541 /* 39434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15542 /* 39438 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(39494), // Rule ID 280 //
15543 /* 39443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
15544 /* 39446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15545 /* 39450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15546 /* 39454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15547 /* 39458 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15548 /* 39462 */ // MIs[1] Operand 1
15549 /* 39462 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
15550 /* 39467 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15551 /* 39472 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15552 /* 39477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15553 /* 39479 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) => (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15554 /* 39479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEQ),
15555 /* 39482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15556 /* 39484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
15557 /* 39488 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
15558 /* 39492 */ GIR_RootConstrainSelectedInstOperands,
15559 /* 39493 */ // GIR_Coverage, 280,
15560 /* 39493 */ GIR_EraseRootFromParent_Done,
15561 /* 39494 */ // Label 1051: @39494
15562 /* 39494 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(39550), // Rule ID 282 //
15563 /* 39499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
15564 /* 39502 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15565 /* 39506 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15566 /* 39510 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15567 /* 39514 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15568 /* 39518 */ // MIs[1] Operand 1
15569 /* 39518 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
15570 /* 39523 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15571 /* 39528 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15572 /* 39533 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15573 /* 39535 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) => (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15574 /* 39535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SNE),
15575 /* 39538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15576 /* 39540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
15577 /* 39544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
15578 /* 39548 */ GIR_RootConstrainSelectedInstOperands,
15579 /* 39549 */ // GIR_Coverage, 282,
15580 /* 39549 */ GIR_EraseRootFromParent_Done,
15581 /* 39550 */ // Label 1052: @39550
15582 /* 39550 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(39622),
15583 /* 39555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15584 /* 39559 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(39598), // Rule ID 1583 //
15585 /* 39564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15586 /* 39567 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
15587 /* 39567 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15588 /* 39570 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSLL64_32),
15589 /* 39574 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15590 /* 39579 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
15591 /* 39583 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15592 /* 39585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
15593 /* 39588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15594 /* 39590 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15595 /* 39593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
15596 /* 39596 */ GIR_RootConstrainSelectedInstOperands,
15597 /* 39597 */ // GIR_Coverage, 1583,
15598 /* 39597 */ GIR_EraseRootFromParent_Done,
15599 /* 39598 */ // Label 1054: @39598
15600 /* 39598 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(39621), // Rule ID 1586 //
15601 /* 39603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips),
15602 /* 39606 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
15603 /* 39606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DEXT64_32),
15604 /* 39609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
15605 /* 39611 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15606 /* 39613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15607 /* 39616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
15608 /* 39619 */ GIR_RootConstrainSelectedInstOperands,
15609 /* 39620 */ // GIR_Coverage, 1586,
15610 /* 39620 */ GIR_EraseRootFromParent_Done,
15611 /* 39621 */ // Label 1055: @39621
15612 /* 39621 */ GIM_Reject,
15613 /* 39622 */ // Label 1053: @39622
15614 /* 39622 */ GIM_Reject,
15615 /* 39623 */ // Label 1050: @39623
15616 /* 39623 */ GIM_Reject,
15617 /* 39624 */ // Label 37: @39624
15618 /* 39624 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1062*/ GIMT_Encode4(41420),
15619 /* 39635 */ /*GILLT_s32*//*Label 1056*/ GIMT_Encode4(39667),
15620 /* 39639 */ /*GILLT_s64*//*Label 1057*/ GIMT_Encode4(39929), GIMT_Encode4(0),
15621 /* 39647 */ /*GILLT_v2s64*//*Label 1058*/ GIMT_Encode4(40070), GIMT_Encode4(0),
15622 /* 39655 */ /*GILLT_v4s32*//*Label 1059*/ GIMT_Encode4(40104),
15623 /* 39659 */ /*GILLT_v8s16*//*Label 1060*/ GIMT_Encode4(40372),
15624 /* 39663 */ /*GILLT_v16s8*//*Label 1061*/ GIMT_Encode4(40768),
15625 /* 39667 */ // Label 1056: @39667
15626 /* 39667 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(39928),
15627 /* 39672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15628 /* 39675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15629 /* 39678 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(39720), // Rule ID 55 //
15630 /* 39683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
15631 /* 39686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15632 /* 39690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15633 /* 39694 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15634 /* 39698 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15635 /* 39702 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15636 /* 39706 */ // MIs[1] Operand 1
15637 /* 39706 */ // No operand predicates
15638 /* 39706 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15639 /* 39708 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
15640 /* 39708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
15641 /* 39711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15642 /* 39713 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15643 /* 39715 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15644 /* 39718 */ GIR_RootConstrainSelectedInstOperands,
15645 /* 39719 */ // GIR_Coverage, 55,
15646 /* 39719 */ GIR_EraseRootFromParent_Done,
15647 /* 39720 */ // Label 1064: @39720
15648 /* 39720 */ GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(39762), // Rule ID 1835 //
15649 /* 39725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15650 /* 39728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15651 /* 39732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15652 /* 39736 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15653 /* 39740 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15654 /* 39744 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15655 /* 39748 */ // MIs[1] Operand 1
15656 /* 39748 */ // No operand predicates
15657 /* 39748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15658 /* 39750 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15659 /* 39750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SllX16),
15660 /* 39753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15661 /* 39755 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
15662 /* 39757 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15663 /* 39760 */ GIR_RootConstrainSelectedInstOperands,
15664 /* 39761 */ // GIR_Coverage, 1835,
15665 /* 39761 */ GIR_EraseRootFromParent_Done,
15666 /* 39762 */ // Label 1065: @39762
15667 /* 39762 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(39804), // Rule ID 2174 //
15668 /* 39767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15669 /* 39770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15670 /* 39774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15671 /* 39778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15672 /* 39782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15673 /* 39786 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
15674 /* 39790 */ // MIs[1] Operand 1
15675 /* 39790 */ // No operand predicates
15676 /* 39790 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15677 /* 39792 */ // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
15678 /* 39792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL16_MM),
15679 /* 39795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15680 /* 39797 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15681 /* 39799 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15682 /* 39802 */ GIR_RootConstrainSelectedInstOperands,
15683 /* 39803 */ // GIR_Coverage, 2174,
15684 /* 39803 */ GIR_EraseRootFromParent_Done,
15685 /* 39804 */ // Label 1066: @39804
15686 /* 39804 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(39846), // Rule ID 2175 //
15687 /* 39809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15688 /* 39812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15689 /* 39816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15690 /* 39820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15691 /* 39824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15692 /* 39828 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15693 /* 39832 */ // MIs[1] Operand 1
15694 /* 39832 */ // No operand predicates
15695 /* 39832 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15696 /* 39834 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15697 /* 39834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_MM),
15698 /* 39837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15699 /* 39839 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15700 /* 39841 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15701 /* 39844 */ GIR_RootConstrainSelectedInstOperands,
15702 /* 39845 */ // GIR_Coverage, 2175,
15703 /* 39845 */ GIR_EraseRootFromParent_Done,
15704 /* 39846 */ // Label 1067: @39846
15705 /* 39846 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(39873), // Rule ID 61 //
15706 /* 39851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
15707 /* 39854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15708 /* 39858 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15709 /* 39862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15710 /* 39866 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15711 /* 39866 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV),
15712 /* 39871 */ GIR_RootConstrainSelectedInstOperands,
15713 /* 39872 */ // GIR_Coverage, 61,
15714 /* 39872 */ GIR_Done,
15715 /* 39873 */ // Label 1068: @39873
15716 /* 39873 */ GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(39900), // Rule ID 1838 //
15717 /* 39878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15718 /* 39881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15719 /* 39885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15720 /* 39889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15721 /* 39893 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
15722 /* 39893 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SllvRxRy16),
15723 /* 39898 */ GIR_RootConstrainSelectedInstOperands,
15724 /* 39899 */ // GIR_Coverage, 1838,
15725 /* 39899 */ GIR_Done,
15726 /* 39900 */ // Label 1069: @39900
15727 /* 39900 */ GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(39927), // Rule ID 2176 //
15728 /* 39905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15729 /* 39908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15730 /* 39912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15731 /* 39916 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15732 /* 39920 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
15733 /* 39920 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV_MM),
15734 /* 39925 */ GIR_RootConstrainSelectedInstOperands,
15735 /* 39926 */ // GIR_Coverage, 2176,
15736 /* 39926 */ GIR_Done,
15737 /* 39927 */ // Label 1070: @39927
15738 /* 39927 */ GIM_Reject,
15739 /* 39928 */ // Label 1063: @39928
15740 /* 39928 */ GIM_Reject,
15741 /* 39929 */ // Label 1057: @39929
15742 /* 39929 */ GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(40069),
15743 /* 39934 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15744 /* 39937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15745 /* 39940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15746 /* 39944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15747 /* 39948 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(39982), // Rule ID 210 //
15748 /* 39953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
15749 /* 39956 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15750 /* 39960 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15751 /* 39964 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
15752 /* 39968 */ // MIs[1] Operand 1
15753 /* 39968 */ // No operand predicates
15754 /* 39968 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15755 /* 39970 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
15756 /* 39970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLL),
15757 /* 39973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15758 /* 39975 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15759 /* 39977 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15760 /* 39980 */ GIR_RootConstrainSelectedInstOperands,
15761 /* 39981 */ // GIR_Coverage, 210,
15762 /* 39981 */ GIR_EraseRootFromParent_Done,
15763 /* 39982 */ // Label 1072: @39982
15764 /* 39982 */ GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(40049), // Rule ID 1576 //
15765 /* 39987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15766 /* 39990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15767 /* 39994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
15768 /* 39998 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15769 /* 40002 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15770 /* 40007 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15771 /* 40009 */ // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
15772 /* 40009 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15773 /* 40012 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15774 /* 40016 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15775 /* 40021 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
15776 /* 40027 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
15777 /* 40032 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15778 /* 40037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
15779 /* 40040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15780 /* 40042 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15781 /* 40044 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15782 /* 40047 */ GIR_RootConstrainSelectedInstOperands,
15783 /* 40048 */ // GIR_Coverage, 1576,
15784 /* 40048 */ GIR_EraseRootFromParent_Done,
15785 /* 40049 */ // Label 1073: @40049
15786 /* 40049 */ GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(40068), // Rule ID 216 //
15787 /* 40054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
15788 /* 40057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15789 /* 40061 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15790 /* 40061 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
15791 /* 40066 */ GIR_RootConstrainSelectedInstOperands,
15792 /* 40067 */ // GIR_Coverage, 216,
15793 /* 40067 */ GIR_Done,
15794 /* 40068 */ // Label 1074: @40068
15795 /* 40068 */ GIM_Reject,
15796 /* 40069 */ // Label 1071: @40069
15797 /* 40069 */ GIM_Reject,
15798 /* 40070 */ // Label 1058: @40070
15799 /* 40070 */ GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(40103), // Rule ID 960 //
15800 /* 40075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
15801 /* 40078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
15802 /* 40081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15803 /* 40084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15804 /* 40088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15805 /* 40092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15806 /* 40096 */ // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
15807 /* 40096 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_D),
15808 /* 40101 */ GIR_RootConstrainSelectedInstOperands,
15809 /* 40102 */ // GIR_Coverage, 960,
15810 /* 40102 */ GIR_Done,
15811 /* 40103 */ // Label 1075: @40103
15812 /* 40103 */ GIM_Reject,
15813 /* 40104 */ // Label 1059: @40104
15814 /* 40104 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(40371),
15815 /* 40109 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
15816 /* 40112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15817 /* 40115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15818 /* 40119 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(40233), // Rule ID 2466 //
15819 /* 40124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15820 /* 40127 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15821 /* 40131 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15822 /* 40135 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15823 /* 40139 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15824 /* 40143 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15825 /* 40147 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15826 /* 40151 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
15827 /* 40154 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15828 /* 40158 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15829 /* 40162 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15830 /* 40166 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15831 /* 40170 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15832 /* 40174 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15833 /* 40178 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15834 /* 40182 */ // MIs[3] Operand 1
15835 /* 40182 */ // No operand predicates
15836 /* 40182 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15837 /* 40186 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15838 /* 40190 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15839 /* 40194 */ // MIs[4] Operand 1
15840 /* 40194 */ // No operand predicates
15841 /* 40194 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15842 /* 40198 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15843 /* 40202 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15844 /* 40206 */ // MIs[5] Operand 1
15845 /* 40206 */ // No operand predicates
15846 /* 40206 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15847 /* 40210 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15848 /* 40214 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15849 /* 40218 */ // MIs[6] Operand 1
15850 /* 40218 */ // No operand predicates
15851 /* 40218 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
15852 /* 40220 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15853 /* 40220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
15854 /* 40223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15855 /* 40225 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15856 /* 40227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15857 /* 40231 */ GIR_RootConstrainSelectedInstOperands,
15858 /* 40232 */ // GIR_Coverage, 2466,
15859 /* 40232 */ GIR_EraseRootFromParent_Done,
15860 /* 40233 */ // Label 1077: @40233
15861 /* 40233 */ GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(40347), // Rule ID 2075 //
15862 /* 40238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15863 /* 40241 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15864 /* 40245 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15865 /* 40249 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15866 /* 40253 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15867 /* 40257 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15868 /* 40261 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15869 /* 40265 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
15870 /* 40268 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15871 /* 40272 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15872 /* 40276 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15873 /* 40280 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15874 /* 40284 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15875 /* 40288 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15876 /* 40292 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15877 /* 40296 */ // MIs[3] Operand 1
15878 /* 40296 */ // No operand predicates
15879 /* 40296 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15880 /* 40300 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15881 /* 40304 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15882 /* 40308 */ // MIs[4] Operand 1
15883 /* 40308 */ // No operand predicates
15884 /* 40308 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15885 /* 40312 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15886 /* 40316 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15887 /* 40320 */ // MIs[5] Operand 1
15888 /* 40320 */ // No operand predicates
15889 /* 40320 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15890 /* 40324 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15891 /* 40328 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15892 /* 40332 */ // MIs[6] Operand 1
15893 /* 40332 */ // No operand predicates
15894 /* 40332 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
15895 /* 40334 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15896 /* 40334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
15897 /* 40337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15898 /* 40339 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15899 /* 40341 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15900 /* 40345 */ GIR_RootConstrainSelectedInstOperands,
15901 /* 40346 */ // GIR_Coverage, 2075,
15902 /* 40346 */ GIR_EraseRootFromParent_Done,
15903 /* 40347 */ // Label 1078: @40347
15904 /* 40347 */ GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(40370), // Rule ID 959 //
15905 /* 40352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
15906 /* 40355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15907 /* 40359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15908 /* 40363 */ // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
15909 /* 40363 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
15910 /* 40368 */ GIR_RootConstrainSelectedInstOperands,
15911 /* 40369 */ // GIR_Coverage, 959,
15912 /* 40369 */ GIR_Done,
15913 /* 40370 */ // Label 1079: @40370
15914 /* 40370 */ GIM_Reject,
15915 /* 40371 */ // Label 1076: @40371
15916 /* 40371 */ GIM_Reject,
15917 /* 40372 */ // Label 1060: @40372
15918 /* 40372 */ GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(40767),
15919 /* 40377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
15920 /* 40380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15921 /* 40383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
15922 /* 40387 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(40565), // Rule ID 2465 //
15923 /* 40392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15924 /* 40395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15925 /* 40399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15926 /* 40403 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15927 /* 40407 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15928 /* 40411 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15929 /* 40415 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15930 /* 40419 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15931 /* 40422 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15932 /* 40426 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15933 /* 40430 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15934 /* 40434 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15935 /* 40438 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15936 /* 40442 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15937 /* 40446 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15938 /* 40450 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15939 /* 40454 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15940 /* 40458 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15941 /* 40462 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15942 /* 40466 */ // MIs[3] Operand 1
15943 /* 40466 */ // No operand predicates
15944 /* 40466 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15945 /* 40470 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15946 /* 40474 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15947 /* 40478 */ // MIs[4] Operand 1
15948 /* 40478 */ // No operand predicates
15949 /* 40478 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15950 /* 40482 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15951 /* 40486 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15952 /* 40490 */ // MIs[5] Operand 1
15953 /* 40490 */ // No operand predicates
15954 /* 40490 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15955 /* 40494 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15956 /* 40498 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15957 /* 40502 */ // MIs[6] Operand 1
15958 /* 40502 */ // No operand predicates
15959 /* 40502 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15960 /* 40506 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15961 /* 40510 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15962 /* 40514 */ // MIs[7] Operand 1
15963 /* 40514 */ // No operand predicates
15964 /* 40514 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15965 /* 40518 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15966 /* 40522 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15967 /* 40526 */ // MIs[8] Operand 1
15968 /* 40526 */ // No operand predicates
15969 /* 40526 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15970 /* 40530 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15971 /* 40534 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15972 /* 40538 */ // MIs[9] Operand 1
15973 /* 40538 */ // No operand predicates
15974 /* 40538 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15975 /* 40542 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15976 /* 40546 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15977 /* 40550 */ // MIs[10] Operand 1
15978 /* 40550 */ // No operand predicates
15979 /* 40550 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
15980 /* 40552 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15981 /* 40552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
15982 /* 40555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15983 /* 40557 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15984 /* 40559 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15985 /* 40563 */ GIR_RootConstrainSelectedInstOperands,
15986 /* 40564 */ // GIR_Coverage, 2465,
15987 /* 40564 */ GIR_EraseRootFromParent_Done,
15988 /* 40565 */ // Label 1081: @40565
15989 /* 40565 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(40743), // Rule ID 2074 //
15990 /* 40570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15991 /* 40573 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15992 /* 40577 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15993 /* 40581 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15994 /* 40585 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15995 /* 40589 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15996 /* 40593 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15997 /* 40597 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15998 /* 40600 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15999 /* 40604 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16000 /* 40608 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16001 /* 40612 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16002 /* 40616 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16003 /* 40620 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16004 /* 40624 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16005 /* 40628 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16006 /* 40632 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16007 /* 40636 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16008 /* 40640 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16009 /* 40644 */ // MIs[3] Operand 1
16010 /* 40644 */ // No operand predicates
16011 /* 40644 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16012 /* 40648 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16013 /* 40652 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16014 /* 40656 */ // MIs[4] Operand 1
16015 /* 40656 */ // No operand predicates
16016 /* 40656 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16017 /* 40660 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16018 /* 40664 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16019 /* 40668 */ // MIs[5] Operand 1
16020 /* 40668 */ // No operand predicates
16021 /* 40668 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16022 /* 40672 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16023 /* 40676 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16024 /* 40680 */ // MIs[6] Operand 1
16025 /* 40680 */ // No operand predicates
16026 /* 40680 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16027 /* 40684 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16028 /* 40688 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16029 /* 40692 */ // MIs[7] Operand 1
16030 /* 40692 */ // No operand predicates
16031 /* 40692 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16032 /* 40696 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16033 /* 40700 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16034 /* 40704 */ // MIs[8] Operand 1
16035 /* 40704 */ // No operand predicates
16036 /* 40704 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16037 /* 40708 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16038 /* 40712 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16039 /* 40716 */ // MIs[9] Operand 1
16040 /* 40716 */ // No operand predicates
16041 /* 40716 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16042 /* 40720 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16043 /* 40724 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16044 /* 40728 */ // MIs[10] Operand 1
16045 /* 40728 */ // No operand predicates
16046 /* 40728 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16047 /* 40730 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16048 /* 40730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16049 /* 40733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16050 /* 40735 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16051 /* 40737 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16052 /* 40741 */ GIR_RootConstrainSelectedInstOperands,
16053 /* 40742 */ // GIR_Coverage, 2074,
16054 /* 40742 */ GIR_EraseRootFromParent_Done,
16055 /* 40743 */ // Label 1082: @40743
16056 /* 40743 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(40766), // Rule ID 958 //
16057 /* 40748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16058 /* 40751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16059 /* 40755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16060 /* 40759 */ // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
16061 /* 40759 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16062 /* 40764 */ GIR_RootConstrainSelectedInstOperands,
16063 /* 40765 */ // GIR_Coverage, 958,
16064 /* 40765 */ GIR_Done,
16065 /* 40766 */ // Label 1083: @40766
16066 /* 40766 */ GIM_Reject,
16067 /* 40767 */ // Label 1080: @40767
16068 /* 40767 */ GIM_Reject,
16069 /* 40768 */ // Label 1061: @40768
16070 /* 40768 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(41419),
16071 /* 40773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16072 /* 40776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16073 /* 40779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16074 /* 40783 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(41089), // Rule ID 2464 //
16075 /* 40788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16076 /* 40791 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16077 /* 40795 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16078 /* 40799 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16079 /* 40803 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16080 /* 40807 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16081 /* 40811 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16082 /* 40815 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16083 /* 40818 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16084 /* 40822 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16085 /* 40826 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16086 /* 40830 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16087 /* 40834 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16088 /* 40838 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16089 /* 40842 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16090 /* 40846 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16091 /* 40850 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16092 /* 40854 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16093 /* 40858 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16094 /* 40862 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16095 /* 40866 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16096 /* 40870 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16097 /* 40874 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16098 /* 40878 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16099 /* 40882 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16100 /* 40886 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16101 /* 40890 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16102 /* 40894 */ // MIs[3] Operand 1
16103 /* 40894 */ // No operand predicates
16104 /* 40894 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16105 /* 40898 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16106 /* 40902 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16107 /* 40906 */ // MIs[4] Operand 1
16108 /* 40906 */ // No operand predicates
16109 /* 40906 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16110 /* 40910 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16111 /* 40914 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16112 /* 40918 */ // MIs[5] Operand 1
16113 /* 40918 */ // No operand predicates
16114 /* 40918 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16115 /* 40922 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16116 /* 40926 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16117 /* 40930 */ // MIs[6] Operand 1
16118 /* 40930 */ // No operand predicates
16119 /* 40930 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16120 /* 40934 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16121 /* 40938 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16122 /* 40942 */ // MIs[7] Operand 1
16123 /* 40942 */ // No operand predicates
16124 /* 40942 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16125 /* 40946 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16126 /* 40950 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16127 /* 40954 */ // MIs[8] Operand 1
16128 /* 40954 */ // No operand predicates
16129 /* 40954 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16130 /* 40958 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16131 /* 40962 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16132 /* 40966 */ // MIs[9] Operand 1
16133 /* 40966 */ // No operand predicates
16134 /* 40966 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16135 /* 40970 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16136 /* 40974 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16137 /* 40978 */ // MIs[10] Operand 1
16138 /* 40978 */ // No operand predicates
16139 /* 40978 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16140 /* 40982 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16141 /* 40986 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16142 /* 40990 */ // MIs[11] Operand 1
16143 /* 40990 */ // No operand predicates
16144 /* 40990 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16145 /* 40994 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16146 /* 40998 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16147 /* 41002 */ // MIs[12] Operand 1
16148 /* 41002 */ // No operand predicates
16149 /* 41002 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16150 /* 41006 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16151 /* 41010 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16152 /* 41014 */ // MIs[13] Operand 1
16153 /* 41014 */ // No operand predicates
16154 /* 41014 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16155 /* 41018 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16156 /* 41022 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16157 /* 41026 */ // MIs[14] Operand 1
16158 /* 41026 */ // No operand predicates
16159 /* 41026 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16160 /* 41030 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16161 /* 41034 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16162 /* 41038 */ // MIs[15] Operand 1
16163 /* 41038 */ // No operand predicates
16164 /* 41038 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16165 /* 41042 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16166 /* 41046 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16167 /* 41050 */ // MIs[16] Operand 1
16168 /* 41050 */ // No operand predicates
16169 /* 41050 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16170 /* 41054 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16171 /* 41058 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16172 /* 41062 */ // MIs[17] Operand 1
16173 /* 41062 */ // No operand predicates
16174 /* 41062 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16175 /* 41066 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16176 /* 41070 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16177 /* 41074 */ // MIs[18] Operand 1
16178 /* 41074 */ // No operand predicates
16179 /* 41074 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16180 /* 41076 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16181 /* 41076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
16182 /* 41079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16183 /* 41081 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16184 /* 41083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16185 /* 41087 */ GIR_RootConstrainSelectedInstOperands,
16186 /* 41088 */ // GIR_Coverage, 2464,
16187 /* 41088 */ GIR_EraseRootFromParent_Done,
16188 /* 41089 */ // Label 1085: @41089
16189 /* 41089 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(41395), // Rule ID 2073 //
16190 /* 41094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16191 /* 41097 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16192 /* 41101 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16193 /* 41105 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16194 /* 41109 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16195 /* 41113 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16196 /* 41117 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16197 /* 41121 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16198 /* 41124 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16199 /* 41128 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16200 /* 41132 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16201 /* 41136 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16202 /* 41140 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16203 /* 41144 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16204 /* 41148 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16205 /* 41152 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16206 /* 41156 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16207 /* 41160 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16208 /* 41164 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16209 /* 41168 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16210 /* 41172 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16211 /* 41176 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16212 /* 41180 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16213 /* 41184 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16214 /* 41188 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16215 /* 41192 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16216 /* 41196 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16217 /* 41200 */ // MIs[3] Operand 1
16218 /* 41200 */ // No operand predicates
16219 /* 41200 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16220 /* 41204 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16221 /* 41208 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16222 /* 41212 */ // MIs[4] Operand 1
16223 /* 41212 */ // No operand predicates
16224 /* 41212 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16225 /* 41216 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16226 /* 41220 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16227 /* 41224 */ // MIs[5] Operand 1
16228 /* 41224 */ // No operand predicates
16229 /* 41224 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16230 /* 41228 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16231 /* 41232 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16232 /* 41236 */ // MIs[6] Operand 1
16233 /* 41236 */ // No operand predicates
16234 /* 41236 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16235 /* 41240 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16236 /* 41244 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16237 /* 41248 */ // MIs[7] Operand 1
16238 /* 41248 */ // No operand predicates
16239 /* 41248 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16240 /* 41252 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16241 /* 41256 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16242 /* 41260 */ // MIs[8] Operand 1
16243 /* 41260 */ // No operand predicates
16244 /* 41260 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16245 /* 41264 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16246 /* 41268 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16247 /* 41272 */ // MIs[9] Operand 1
16248 /* 41272 */ // No operand predicates
16249 /* 41272 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16250 /* 41276 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16251 /* 41280 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16252 /* 41284 */ // MIs[10] Operand 1
16253 /* 41284 */ // No operand predicates
16254 /* 41284 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16255 /* 41288 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16256 /* 41292 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16257 /* 41296 */ // MIs[11] Operand 1
16258 /* 41296 */ // No operand predicates
16259 /* 41296 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16260 /* 41300 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16261 /* 41304 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16262 /* 41308 */ // MIs[12] Operand 1
16263 /* 41308 */ // No operand predicates
16264 /* 41308 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16265 /* 41312 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16266 /* 41316 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16267 /* 41320 */ // MIs[13] Operand 1
16268 /* 41320 */ // No operand predicates
16269 /* 41320 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16270 /* 41324 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16271 /* 41328 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16272 /* 41332 */ // MIs[14] Operand 1
16273 /* 41332 */ // No operand predicates
16274 /* 41332 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16275 /* 41336 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16276 /* 41340 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16277 /* 41344 */ // MIs[15] Operand 1
16278 /* 41344 */ // No operand predicates
16279 /* 41344 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16280 /* 41348 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16281 /* 41352 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16282 /* 41356 */ // MIs[16] Operand 1
16283 /* 41356 */ // No operand predicates
16284 /* 41356 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16285 /* 41360 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16286 /* 41364 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16287 /* 41368 */ // MIs[17] Operand 1
16288 /* 41368 */ // No operand predicates
16289 /* 41368 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16290 /* 41372 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16291 /* 41376 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16292 /* 41380 */ // MIs[18] Operand 1
16293 /* 41380 */ // No operand predicates
16294 /* 41380 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16295 /* 41382 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16296 /* 41382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
16297 /* 41385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16298 /* 41387 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16299 /* 41389 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16300 /* 41393 */ GIR_RootConstrainSelectedInstOperands,
16301 /* 41394 */ // GIR_Coverage, 2073,
16302 /* 41394 */ GIR_EraseRootFromParent_Done,
16303 /* 41395 */ // Label 1086: @41395
16304 /* 41395 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(41418), // Rule ID 957 //
16305 /* 41400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16306 /* 41403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16307 /* 41407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16308 /* 41411 */ // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
16309 /* 41411 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
16310 /* 41416 */ GIR_RootConstrainSelectedInstOperands,
16311 /* 41417 */ // GIR_Coverage, 957,
16312 /* 41417 */ GIR_Done,
16313 /* 41418 */ // Label 1087: @41418
16314 /* 41418 */ GIM_Reject,
16315 /* 41419 */ // Label 1084: @41419
16316 /* 41419 */ GIM_Reject,
16317 /* 41420 */ // Label 1062: @41420
16318 /* 41420 */ GIM_Reject,
16319 /* 41421 */ // Label 38: @41421
16320 /* 41421 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1094*/ GIMT_Encode4(43217),
16321 /* 41432 */ /*GILLT_s32*//*Label 1088*/ GIMT_Encode4(41464),
16322 /* 41436 */ /*GILLT_s64*//*Label 1089*/ GIMT_Encode4(41726), GIMT_Encode4(0),
16323 /* 41444 */ /*GILLT_v2s64*//*Label 1090*/ GIMT_Encode4(41867), GIMT_Encode4(0),
16324 /* 41452 */ /*GILLT_v4s32*//*Label 1091*/ GIMT_Encode4(41901),
16325 /* 41456 */ /*GILLT_v8s16*//*Label 1092*/ GIMT_Encode4(42169),
16326 /* 41460 */ /*GILLT_v16s8*//*Label 1093*/ GIMT_Encode4(42565),
16327 /* 41464 */ // Label 1088: @41464
16328 /* 41464 */ GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(41725),
16329 /* 41469 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16330 /* 41472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16331 /* 41475 */ GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(41517), // Rule ID 57 //
16332 /* 41480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16333 /* 41483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16334 /* 41487 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16335 /* 41491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16336 /* 41495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16337 /* 41499 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16338 /* 41503 */ // MIs[1] Operand 1
16339 /* 41503 */ // No operand predicates
16340 /* 41503 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16341 /* 41505 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16342 /* 41505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL),
16343 /* 41508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16344 /* 41510 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16345 /* 41512 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16346 /* 41515 */ GIR_RootConstrainSelectedInstOperands,
16347 /* 41516 */ // GIR_Coverage, 57,
16348 /* 41516 */ GIR_EraseRootFromParent_Done,
16349 /* 41517 */ // Label 1096: @41517
16350 /* 41517 */ GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(41559), // Rule ID 1836 //
16351 /* 41522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16352 /* 41525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16353 /* 41529 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16354 /* 41533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16355 /* 41537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16356 /* 41541 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16357 /* 41545 */ // MIs[1] Operand 1
16358 /* 41545 */ // No operand predicates
16359 /* 41545 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16360 /* 41547 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16361 /* 41547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SrlX16),
16362 /* 41550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16363 /* 41552 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
16364 /* 41554 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16365 /* 41557 */ GIR_RootConstrainSelectedInstOperands,
16366 /* 41558 */ // GIR_Coverage, 1836,
16367 /* 41558 */ GIR_EraseRootFromParent_Done,
16368 /* 41559 */ // Label 1097: @41559
16369 /* 41559 */ GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(41601), // Rule ID 2177 //
16370 /* 41564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16371 /* 41567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16372 /* 41571 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16373 /* 41575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16374 /* 41579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16375 /* 41583 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
16376 /* 41587 */ // MIs[1] Operand 1
16377 /* 41587 */ // No operand predicates
16378 /* 41587 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16379 /* 41589 */ // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
16380 /* 41589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL16_MM),
16381 /* 41592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16382 /* 41594 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16383 /* 41596 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16384 /* 41599 */ GIR_RootConstrainSelectedInstOperands,
16385 /* 41600 */ // GIR_Coverage, 2177,
16386 /* 41600 */ GIR_EraseRootFromParent_Done,
16387 /* 41601 */ // Label 1098: @41601
16388 /* 41601 */ GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(41643), // Rule ID 2178 //
16389 /* 41606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16390 /* 41609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16391 /* 41613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16392 /* 41617 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16393 /* 41621 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16394 /* 41625 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16395 /* 41629 */ // MIs[1] Operand 1
16396 /* 41629 */ // No operand predicates
16397 /* 41629 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16398 /* 41631 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16399 /* 41631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_MM),
16400 /* 41634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16401 /* 41636 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16402 /* 41638 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16403 /* 41641 */ GIR_RootConstrainSelectedInstOperands,
16404 /* 41642 */ // GIR_Coverage, 2178,
16405 /* 41642 */ GIR_EraseRootFromParent_Done,
16406 /* 41643 */ // Label 1099: @41643
16407 /* 41643 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(41670), // Rule ID 63 //
16408 /* 41648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16409 /* 41651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16410 /* 41655 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16411 /* 41659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16412 /* 41663 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16413 /* 41663 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV),
16414 /* 41668 */ GIR_RootConstrainSelectedInstOperands,
16415 /* 41669 */ // GIR_Coverage, 63,
16416 /* 41669 */ GIR_Done,
16417 /* 41670 */ // Label 1100: @41670
16418 /* 41670 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(41697), // Rule ID 1840 //
16419 /* 41675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16420 /* 41678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16421 /* 41682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16422 /* 41686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16423 /* 41690 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
16424 /* 41690 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SrlvRxRy16),
16425 /* 41695 */ GIR_RootConstrainSelectedInstOperands,
16426 /* 41696 */ // GIR_Coverage, 1840,
16427 /* 41696 */ GIR_Done,
16428 /* 41697 */ // Label 1101: @41697
16429 /* 41697 */ GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(41724), // Rule ID 2179 //
16430 /* 41702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16431 /* 41705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16432 /* 41709 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16433 /* 41713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16434 /* 41717 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
16435 /* 41717 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV_MM),
16436 /* 41722 */ GIR_RootConstrainSelectedInstOperands,
16437 /* 41723 */ // GIR_Coverage, 2179,
16438 /* 41723 */ GIR_Done,
16439 /* 41724 */ // Label 1102: @41724
16440 /* 41724 */ GIM_Reject,
16441 /* 41725 */ // Label 1095: @41725
16442 /* 41725 */ GIM_Reject,
16443 /* 41726 */ // Label 1089: @41726
16444 /* 41726 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(41866),
16445 /* 41731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16446 /* 41734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16447 /* 41737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16448 /* 41741 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16449 /* 41745 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(41779), // Rule ID 212 //
16450 /* 41750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
16451 /* 41753 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16452 /* 41757 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16453 /* 41761 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16454 /* 41765 */ // MIs[1] Operand 1
16455 /* 41765 */ // No operand predicates
16456 /* 41765 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16457 /* 41767 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
16458 /* 41767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
16459 /* 41770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16460 /* 41772 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16461 /* 41774 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16462 /* 41777 */ GIR_RootConstrainSelectedInstOperands,
16463 /* 41778 */ // GIR_Coverage, 212,
16464 /* 41778 */ GIR_EraseRootFromParent_Done,
16465 /* 41779 */ // Label 1104: @41779
16466 /* 41779 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(41846), // Rule ID 1577 //
16467 /* 41784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16468 /* 41787 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16469 /* 41791 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16470 /* 41795 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16471 /* 41799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16472 /* 41804 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16473 /* 41806 */ // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
16474 /* 41806 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16475 /* 41809 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16476 /* 41813 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16477 /* 41818 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
16478 /* 41824 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
16479 /* 41829 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16480 /* 41834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
16481 /* 41837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16482 /* 41839 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16483 /* 41841 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16484 /* 41844 */ GIR_RootConstrainSelectedInstOperands,
16485 /* 41845 */ // GIR_Coverage, 1577,
16486 /* 41845 */ GIR_EraseRootFromParent_Done,
16487 /* 41846 */ // Label 1105: @41846
16488 /* 41846 */ GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(41865), // Rule ID 220 //
16489 /* 41851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
16490 /* 41854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16491 /* 41858 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16492 /* 41858 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
16493 /* 41863 */ GIR_RootConstrainSelectedInstOperands,
16494 /* 41864 */ // GIR_Coverage, 220,
16495 /* 41864 */ GIR_Done,
16496 /* 41865 */ // Label 1106: @41865
16497 /* 41865 */ GIM_Reject,
16498 /* 41866 */ // Label 1103: @41866
16499 /* 41866 */ GIM_Reject,
16500 /* 41867 */ // Label 1090: @41867
16501 /* 41867 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(41900), // Rule ID 992 //
16502 /* 41872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16503 /* 41875 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
16504 /* 41878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
16505 /* 41881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16506 /* 41885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16507 /* 41889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16508 /* 41893 */ // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
16509 /* 41893 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_D),
16510 /* 41898 */ GIR_RootConstrainSelectedInstOperands,
16511 /* 41899 */ // GIR_Coverage, 992,
16512 /* 41899 */ GIR_Done,
16513 /* 41900 */ // Label 1107: @41900
16514 /* 41900 */ GIM_Reject,
16515 /* 41901 */ // Label 1091: @41901
16516 /* 41901 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(42168),
16517 /* 41906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
16518 /* 41909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16519 /* 41912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16520 /* 41916 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(42030), // Rule ID 2482 //
16521 /* 41921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16522 /* 41924 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16523 /* 41928 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16524 /* 41932 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16525 /* 41936 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16526 /* 41940 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16527 /* 41944 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16528 /* 41948 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16529 /* 41951 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16530 /* 41955 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16531 /* 41959 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16532 /* 41963 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16533 /* 41967 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16534 /* 41971 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16535 /* 41975 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16536 /* 41979 */ // MIs[3] Operand 1
16537 /* 41979 */ // No operand predicates
16538 /* 41979 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16539 /* 41983 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16540 /* 41987 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16541 /* 41991 */ // MIs[4] Operand 1
16542 /* 41991 */ // No operand predicates
16543 /* 41991 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16544 /* 41995 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16545 /* 41999 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16546 /* 42003 */ // MIs[5] Operand 1
16547 /* 42003 */ // No operand predicates
16548 /* 42003 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16549 /* 42007 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16550 /* 42011 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16551 /* 42015 */ // MIs[6] Operand 1
16552 /* 42015 */ // No operand predicates
16553 /* 42015 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16554 /* 42017 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16555 /* 42017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16556 /* 42020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16557 /* 42022 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16558 /* 42024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16559 /* 42028 */ GIR_RootConstrainSelectedInstOperands,
16560 /* 42029 */ // GIR_Coverage, 2482,
16561 /* 42029 */ GIR_EraseRootFromParent_Done,
16562 /* 42030 */ // Label 1109: @42030
16563 /* 42030 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(42144), // Rule ID 2083 //
16564 /* 42035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16565 /* 42038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16566 /* 42042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16567 /* 42046 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16568 /* 42050 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16569 /* 42054 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16570 /* 42058 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16571 /* 42062 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16572 /* 42065 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16573 /* 42069 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16574 /* 42073 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16575 /* 42077 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16576 /* 42081 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16577 /* 42085 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16578 /* 42089 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16579 /* 42093 */ // MIs[3] Operand 1
16580 /* 42093 */ // No operand predicates
16581 /* 42093 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16582 /* 42097 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16583 /* 42101 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16584 /* 42105 */ // MIs[4] Operand 1
16585 /* 42105 */ // No operand predicates
16586 /* 42105 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16587 /* 42109 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16588 /* 42113 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16589 /* 42117 */ // MIs[5] Operand 1
16590 /* 42117 */ // No operand predicates
16591 /* 42117 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16592 /* 42121 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16593 /* 42125 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16594 /* 42129 */ // MIs[6] Operand 1
16595 /* 42129 */ // No operand predicates
16596 /* 42129 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16597 /* 42131 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16598 /* 42131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16599 /* 42134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16600 /* 42136 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16601 /* 42138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16602 /* 42142 */ GIR_RootConstrainSelectedInstOperands,
16603 /* 42143 */ // GIR_Coverage, 2083,
16604 /* 42143 */ GIR_EraseRootFromParent_Done,
16605 /* 42144 */ // Label 1110: @42144
16606 /* 42144 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(42167), // Rule ID 991 //
16607 /* 42149 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16608 /* 42152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16609 /* 42156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16610 /* 42160 */ // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
16611 /* 42160 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16612 /* 42165 */ GIR_RootConstrainSelectedInstOperands,
16613 /* 42166 */ // GIR_Coverage, 991,
16614 /* 42166 */ GIR_Done,
16615 /* 42167 */ // Label 1111: @42167
16616 /* 42167 */ GIM_Reject,
16617 /* 42168 */ // Label 1108: @42168
16618 /* 42168 */ GIM_Reject,
16619 /* 42169 */ // Label 1092: @42169
16620 /* 42169 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(42564),
16621 /* 42174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
16622 /* 42177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16623 /* 42180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16624 /* 42184 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(42362), // Rule ID 2481 //
16625 /* 42189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16626 /* 42192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16627 /* 42196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16628 /* 42200 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16629 /* 42204 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16630 /* 42208 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16631 /* 42212 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16632 /* 42216 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16633 /* 42219 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16634 /* 42223 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16635 /* 42227 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16636 /* 42231 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16637 /* 42235 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16638 /* 42239 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16639 /* 42243 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16640 /* 42247 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16641 /* 42251 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16642 /* 42255 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16643 /* 42259 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16644 /* 42263 */ // MIs[3] Operand 1
16645 /* 42263 */ // No operand predicates
16646 /* 42263 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16647 /* 42267 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16648 /* 42271 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16649 /* 42275 */ // MIs[4] Operand 1
16650 /* 42275 */ // No operand predicates
16651 /* 42275 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16652 /* 42279 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16653 /* 42283 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16654 /* 42287 */ // MIs[5] Operand 1
16655 /* 42287 */ // No operand predicates
16656 /* 42287 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16657 /* 42291 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16658 /* 42295 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16659 /* 42299 */ // MIs[6] Operand 1
16660 /* 42299 */ // No operand predicates
16661 /* 42299 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16662 /* 42303 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16663 /* 42307 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16664 /* 42311 */ // MIs[7] Operand 1
16665 /* 42311 */ // No operand predicates
16666 /* 42311 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16667 /* 42315 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16668 /* 42319 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16669 /* 42323 */ // MIs[8] Operand 1
16670 /* 42323 */ // No operand predicates
16671 /* 42323 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16672 /* 42327 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16673 /* 42331 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16674 /* 42335 */ // MIs[9] Operand 1
16675 /* 42335 */ // No operand predicates
16676 /* 42335 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16677 /* 42339 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16678 /* 42343 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16679 /* 42347 */ // MIs[10] Operand 1
16680 /* 42347 */ // No operand predicates
16681 /* 42347 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16682 /* 42349 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16683 /* 42349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16684 /* 42352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16685 /* 42354 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16686 /* 42356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16687 /* 42360 */ GIR_RootConstrainSelectedInstOperands,
16688 /* 42361 */ // GIR_Coverage, 2481,
16689 /* 42361 */ GIR_EraseRootFromParent_Done,
16690 /* 42362 */ // Label 1113: @42362
16691 /* 42362 */ GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(42540), // Rule ID 2082 //
16692 /* 42367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16693 /* 42370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16694 /* 42374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16695 /* 42378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16696 /* 42382 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16697 /* 42386 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16698 /* 42390 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16699 /* 42394 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16700 /* 42397 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16701 /* 42401 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16702 /* 42405 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16703 /* 42409 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16704 /* 42413 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16705 /* 42417 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16706 /* 42421 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16707 /* 42425 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16708 /* 42429 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16709 /* 42433 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16710 /* 42437 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16711 /* 42441 */ // MIs[3] Operand 1
16712 /* 42441 */ // No operand predicates
16713 /* 42441 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16714 /* 42445 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16715 /* 42449 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16716 /* 42453 */ // MIs[4] Operand 1
16717 /* 42453 */ // No operand predicates
16718 /* 42453 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16719 /* 42457 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16720 /* 42461 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16721 /* 42465 */ // MIs[5] Operand 1
16722 /* 42465 */ // No operand predicates
16723 /* 42465 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16724 /* 42469 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16725 /* 42473 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16726 /* 42477 */ // MIs[6] Operand 1
16727 /* 42477 */ // No operand predicates
16728 /* 42477 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16729 /* 42481 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16730 /* 42485 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16731 /* 42489 */ // MIs[7] Operand 1
16732 /* 42489 */ // No operand predicates
16733 /* 42489 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16734 /* 42493 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16735 /* 42497 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16736 /* 42501 */ // MIs[8] Operand 1
16737 /* 42501 */ // No operand predicates
16738 /* 42501 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16739 /* 42505 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16740 /* 42509 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16741 /* 42513 */ // MIs[9] Operand 1
16742 /* 42513 */ // No operand predicates
16743 /* 42513 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16744 /* 42517 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16745 /* 42521 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16746 /* 42525 */ // MIs[10] Operand 1
16747 /* 42525 */ // No operand predicates
16748 /* 42525 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16749 /* 42527 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16750 /* 42527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16751 /* 42530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16752 /* 42532 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16753 /* 42534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16754 /* 42538 */ GIR_RootConstrainSelectedInstOperands,
16755 /* 42539 */ // GIR_Coverage, 2082,
16756 /* 42539 */ GIR_EraseRootFromParent_Done,
16757 /* 42540 */ // Label 1114: @42540
16758 /* 42540 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(42563), // Rule ID 990 //
16759 /* 42545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16760 /* 42548 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16761 /* 42552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16762 /* 42556 */ // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
16763 /* 42556 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16764 /* 42561 */ GIR_RootConstrainSelectedInstOperands,
16765 /* 42562 */ // GIR_Coverage, 990,
16766 /* 42562 */ GIR_Done,
16767 /* 42563 */ // Label 1115: @42563
16768 /* 42563 */ GIM_Reject,
16769 /* 42564 */ // Label 1112: @42564
16770 /* 42564 */ GIM_Reject,
16771 /* 42565 */ // Label 1093: @42565
16772 /* 42565 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(43216),
16773 /* 42570 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16774 /* 42573 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16775 /* 42576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16776 /* 42580 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(42886), // Rule ID 2480 //
16777 /* 42585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16778 /* 42588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16779 /* 42592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16780 /* 42596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16781 /* 42600 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16782 /* 42604 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16783 /* 42608 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16784 /* 42612 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16785 /* 42615 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16786 /* 42619 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16787 /* 42623 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16788 /* 42627 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16789 /* 42631 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16790 /* 42635 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16791 /* 42639 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16792 /* 42643 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16793 /* 42647 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16794 /* 42651 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16795 /* 42655 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16796 /* 42659 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16797 /* 42663 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16798 /* 42667 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16799 /* 42671 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16800 /* 42675 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16801 /* 42679 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16802 /* 42683 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16803 /* 42687 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16804 /* 42691 */ // MIs[3] Operand 1
16805 /* 42691 */ // No operand predicates
16806 /* 42691 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16807 /* 42695 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16808 /* 42699 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16809 /* 42703 */ // MIs[4] Operand 1
16810 /* 42703 */ // No operand predicates
16811 /* 42703 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16812 /* 42707 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16813 /* 42711 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16814 /* 42715 */ // MIs[5] Operand 1
16815 /* 42715 */ // No operand predicates
16816 /* 42715 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16817 /* 42719 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16818 /* 42723 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16819 /* 42727 */ // MIs[6] Operand 1
16820 /* 42727 */ // No operand predicates
16821 /* 42727 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16822 /* 42731 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16823 /* 42735 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16824 /* 42739 */ // MIs[7] Operand 1
16825 /* 42739 */ // No operand predicates
16826 /* 42739 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16827 /* 42743 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16828 /* 42747 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16829 /* 42751 */ // MIs[8] Operand 1
16830 /* 42751 */ // No operand predicates
16831 /* 42751 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16832 /* 42755 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16833 /* 42759 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16834 /* 42763 */ // MIs[9] Operand 1
16835 /* 42763 */ // No operand predicates
16836 /* 42763 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16837 /* 42767 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16838 /* 42771 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16839 /* 42775 */ // MIs[10] Operand 1
16840 /* 42775 */ // No operand predicates
16841 /* 42775 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16842 /* 42779 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16843 /* 42783 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16844 /* 42787 */ // MIs[11] Operand 1
16845 /* 42787 */ // No operand predicates
16846 /* 42787 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16847 /* 42791 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16848 /* 42795 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16849 /* 42799 */ // MIs[12] Operand 1
16850 /* 42799 */ // No operand predicates
16851 /* 42799 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16852 /* 42803 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16853 /* 42807 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16854 /* 42811 */ // MIs[13] Operand 1
16855 /* 42811 */ // No operand predicates
16856 /* 42811 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16857 /* 42815 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16858 /* 42819 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16859 /* 42823 */ // MIs[14] Operand 1
16860 /* 42823 */ // No operand predicates
16861 /* 42823 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16862 /* 42827 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16863 /* 42831 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16864 /* 42835 */ // MIs[15] Operand 1
16865 /* 42835 */ // No operand predicates
16866 /* 42835 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16867 /* 42839 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16868 /* 42843 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16869 /* 42847 */ // MIs[16] Operand 1
16870 /* 42847 */ // No operand predicates
16871 /* 42847 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16872 /* 42851 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16873 /* 42855 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16874 /* 42859 */ // MIs[17] Operand 1
16875 /* 42859 */ // No operand predicates
16876 /* 42859 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16877 /* 42863 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16878 /* 42867 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16879 /* 42871 */ // MIs[18] Operand 1
16880 /* 42871 */ // No operand predicates
16881 /* 42871 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16882 /* 42873 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16883 /* 42873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
16884 /* 42876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16885 /* 42878 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16886 /* 42880 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16887 /* 42884 */ GIR_RootConstrainSelectedInstOperands,
16888 /* 42885 */ // GIR_Coverage, 2480,
16889 /* 42885 */ GIR_EraseRootFromParent_Done,
16890 /* 42886 */ // Label 1117: @42886
16891 /* 42886 */ GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(43192), // Rule ID 2081 //
16892 /* 42891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16893 /* 42894 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16894 /* 42898 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16895 /* 42902 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16896 /* 42906 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16897 /* 42910 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16898 /* 42914 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16899 /* 42918 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16900 /* 42921 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16901 /* 42925 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16902 /* 42929 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16903 /* 42933 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16904 /* 42937 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16905 /* 42941 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16906 /* 42945 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16907 /* 42949 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16908 /* 42953 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16909 /* 42957 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16910 /* 42961 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16911 /* 42965 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16912 /* 42969 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16913 /* 42973 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16914 /* 42977 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16915 /* 42981 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16916 /* 42985 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16917 /* 42989 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16918 /* 42993 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16919 /* 42997 */ // MIs[3] Operand 1
16920 /* 42997 */ // No operand predicates
16921 /* 42997 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16922 /* 43001 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16923 /* 43005 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16924 /* 43009 */ // MIs[4] Operand 1
16925 /* 43009 */ // No operand predicates
16926 /* 43009 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16927 /* 43013 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16928 /* 43017 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16929 /* 43021 */ // MIs[5] Operand 1
16930 /* 43021 */ // No operand predicates
16931 /* 43021 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16932 /* 43025 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16933 /* 43029 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16934 /* 43033 */ // MIs[6] Operand 1
16935 /* 43033 */ // No operand predicates
16936 /* 43033 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16937 /* 43037 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16938 /* 43041 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16939 /* 43045 */ // MIs[7] Operand 1
16940 /* 43045 */ // No operand predicates
16941 /* 43045 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16942 /* 43049 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16943 /* 43053 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16944 /* 43057 */ // MIs[8] Operand 1
16945 /* 43057 */ // No operand predicates
16946 /* 43057 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16947 /* 43061 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16948 /* 43065 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16949 /* 43069 */ // MIs[9] Operand 1
16950 /* 43069 */ // No operand predicates
16951 /* 43069 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16952 /* 43073 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16953 /* 43077 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16954 /* 43081 */ // MIs[10] Operand 1
16955 /* 43081 */ // No operand predicates
16956 /* 43081 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16957 /* 43085 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16958 /* 43089 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16959 /* 43093 */ // MIs[11] Operand 1
16960 /* 43093 */ // No operand predicates
16961 /* 43093 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16962 /* 43097 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16963 /* 43101 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16964 /* 43105 */ // MIs[12] Operand 1
16965 /* 43105 */ // No operand predicates
16966 /* 43105 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16967 /* 43109 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16968 /* 43113 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16969 /* 43117 */ // MIs[13] Operand 1
16970 /* 43117 */ // No operand predicates
16971 /* 43117 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16972 /* 43121 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16973 /* 43125 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16974 /* 43129 */ // MIs[14] Operand 1
16975 /* 43129 */ // No operand predicates
16976 /* 43129 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16977 /* 43133 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16978 /* 43137 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16979 /* 43141 */ // MIs[15] Operand 1
16980 /* 43141 */ // No operand predicates
16981 /* 43141 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16982 /* 43145 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16983 /* 43149 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16984 /* 43153 */ // MIs[16] Operand 1
16985 /* 43153 */ // No operand predicates
16986 /* 43153 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16987 /* 43157 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16988 /* 43161 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16989 /* 43165 */ // MIs[17] Operand 1
16990 /* 43165 */ // No operand predicates
16991 /* 43165 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16992 /* 43169 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16993 /* 43173 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16994 /* 43177 */ // MIs[18] Operand 1
16995 /* 43177 */ // No operand predicates
16996 /* 43177 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16997 /* 43179 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16998 /* 43179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
16999 /* 43182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17000 /* 43184 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17001 /* 43186 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17002 /* 43190 */ GIR_RootConstrainSelectedInstOperands,
17003 /* 43191 */ // GIR_Coverage, 2081,
17004 /* 43191 */ GIR_EraseRootFromParent_Done,
17005 /* 43192 */ // Label 1118: @43192
17006 /* 43192 */ GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(43215), // Rule ID 989 //
17007 /* 43197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17008 /* 43200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17009 /* 43204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17010 /* 43208 */ // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
17011 /* 43208 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
17012 /* 43213 */ GIR_RootConstrainSelectedInstOperands,
17013 /* 43214 */ // GIR_Coverage, 989,
17014 /* 43214 */ GIR_Done,
17015 /* 43215 */ // Label 1119: @43215
17016 /* 43215 */ GIM_Reject,
17017 /* 43216 */ // Label 1116: @43216
17018 /* 43216 */ GIM_Reject,
17019 /* 43217 */ // Label 1094: @43217
17020 /* 43217 */ GIM_Reject,
17021 /* 43218 */ // Label 39: @43218
17022 /* 43218 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1126*/ GIMT_Encode4(44972),
17023 /* 43229 */ /*GILLT_s32*//*Label 1120*/ GIMT_Encode4(43261),
17024 /* 43233 */ /*GILLT_s64*//*Label 1121*/ GIMT_Encode4(43481), GIMT_Encode4(0),
17025 /* 43241 */ /*GILLT_v2s64*//*Label 1122*/ GIMT_Encode4(43622), GIMT_Encode4(0),
17026 /* 43249 */ /*GILLT_v4s32*//*Label 1123*/ GIMT_Encode4(43656),
17027 /* 43253 */ /*GILLT_v8s16*//*Label 1124*/ GIMT_Encode4(43924),
17028 /* 43257 */ /*GILLT_v16s8*//*Label 1125*/ GIMT_Encode4(44320),
17029 /* 43261 */ // Label 1120: @43261
17030 /* 43261 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(43480),
17031 /* 43266 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
17032 /* 43269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17033 /* 43272 */ GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(43314), // Rule ID 59 //
17034 /* 43277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17035 /* 43280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17036 /* 43284 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17037 /* 43288 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17038 /* 43292 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17039 /* 43296 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17040 /* 43300 */ // MIs[1] Operand 1
17041 /* 43300 */ // No operand predicates
17042 /* 43300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17043 /* 43302 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17044 /* 43302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA),
17045 /* 43305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17046 /* 43307 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17047 /* 43309 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17048 /* 43312 */ GIR_RootConstrainSelectedInstOperands,
17049 /* 43313 */ // GIR_Coverage, 59,
17050 /* 43313 */ GIR_EraseRootFromParent_Done,
17051 /* 43314 */ // Label 1128: @43314
17052 /* 43314 */ GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(43356), // Rule ID 1837 //
17053 /* 43319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17054 /* 43322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17055 /* 43326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17056 /* 43330 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17057 /* 43334 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17058 /* 43338 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17059 /* 43342 */ // MIs[1] Operand 1
17060 /* 43342 */ // No operand predicates
17061 /* 43342 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17062 /* 43344 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17063 /* 43344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SraX16),
17064 /* 43347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
17065 /* 43349 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17066 /* 43351 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17067 /* 43354 */ GIR_RootConstrainSelectedInstOperands,
17068 /* 43355 */ // GIR_Coverage, 1837,
17069 /* 43355 */ GIR_EraseRootFromParent_Done,
17070 /* 43356 */ // Label 1129: @43356
17071 /* 43356 */ GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(43398), // Rule ID 2180 //
17072 /* 43361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17073 /* 43364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17074 /* 43368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17075 /* 43372 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17076 /* 43376 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17077 /* 43380 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17078 /* 43384 */ // MIs[1] Operand 1
17079 /* 43384 */ // No operand predicates
17080 /* 43384 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17081 /* 43386 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17082 /* 43386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_MM),
17083 /* 43389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17084 /* 43391 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
17085 /* 43393 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17086 /* 43396 */ GIR_RootConstrainSelectedInstOperands,
17087 /* 43397 */ // GIR_Coverage, 2180,
17088 /* 43397 */ GIR_EraseRootFromParent_Done,
17089 /* 43398 */ // Label 1130: @43398
17090 /* 43398 */ GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(43425), // Rule ID 65 //
17091 /* 43403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17092 /* 43406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17093 /* 43410 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17094 /* 43414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17095 /* 43418 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17096 /* 43418 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV),
17097 /* 43423 */ GIR_RootConstrainSelectedInstOperands,
17098 /* 43424 */ // GIR_Coverage, 65,
17099 /* 43424 */ GIR_Done,
17100 /* 43425 */ // Label 1131: @43425
17101 /* 43425 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(43452), // Rule ID 1839 //
17102 /* 43430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17103 /* 43433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17104 /* 43437 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17105 /* 43441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17106 /* 43445 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
17107 /* 43445 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SravRxRy16),
17108 /* 43450 */ GIR_RootConstrainSelectedInstOperands,
17109 /* 43451 */ // GIR_Coverage, 1839,
17110 /* 43451 */ GIR_Done,
17111 /* 43452 */ // Label 1132: @43452
17112 /* 43452 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(43479), // Rule ID 2181 //
17113 /* 43457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17114 /* 43460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17115 /* 43464 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17116 /* 43468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17117 /* 43472 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
17118 /* 43472 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV_MM),
17119 /* 43477 */ GIR_RootConstrainSelectedInstOperands,
17120 /* 43478 */ // GIR_Coverage, 2181,
17121 /* 43478 */ GIR_Done,
17122 /* 43479 */ // Label 1133: @43479
17123 /* 43479 */ GIM_Reject,
17124 /* 43480 */ // Label 1127: @43480
17125 /* 43480 */ GIM_Reject,
17126 /* 43481 */ // Label 1121: @43481
17127 /* 43481 */ GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(43621),
17128 /* 43486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17129 /* 43489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17130 /* 43492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17131 /* 43496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17132 /* 43500 */ GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(43534), // Rule ID 214 //
17133 /* 43505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17134 /* 43508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17135 /* 43512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17136 /* 43516 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17137 /* 43520 */ // MIs[1] Operand 1
17138 /* 43520 */ // No operand predicates
17139 /* 43520 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17140 /* 43522 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
17141 /* 43522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRA),
17142 /* 43525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17143 /* 43527 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17144 /* 43529 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17145 /* 43532 */ GIR_RootConstrainSelectedInstOperands,
17146 /* 43533 */ // GIR_Coverage, 214,
17147 /* 43533 */ GIR_EraseRootFromParent_Done,
17148 /* 43534 */ // Label 1135: @43534
17149 /* 43534 */ GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(43601), // Rule ID 1578 //
17150 /* 43539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
17151 /* 43542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17152 /* 43546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
17153 /* 43550 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17154 /* 43554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17155 /* 43559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17156 /* 43561 */ // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
17157 /* 43561 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17158 /* 43564 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17159 /* 43568 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17160 /* 43573 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17161 /* 43579 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17162 /* 43584 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17163 /* 43589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
17164 /* 43592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17165 /* 43594 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17166 /* 43596 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17167 /* 43599 */ GIR_RootConstrainSelectedInstOperands,
17168 /* 43600 */ // GIR_Coverage, 1578,
17169 /* 43600 */ GIR_EraseRootFromParent_Done,
17170 /* 43601 */ // Label 1136: @43601
17171 /* 43601 */ GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(43620), // Rule ID 218 //
17172 /* 43606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17173 /* 43609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17174 /* 43613 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17175 /* 43613 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
17176 /* 43618 */ GIR_RootConstrainSelectedInstOperands,
17177 /* 43619 */ // GIR_Coverage, 218,
17178 /* 43619 */ GIR_Done,
17179 /* 43620 */ // Label 1137: @43620
17180 /* 43620 */ GIM_Reject,
17181 /* 43621 */ // Label 1134: @43621
17182 /* 43621 */ GIM_Reject,
17183 /* 43622 */ // Label 1122: @43622
17184 /* 43622 */ GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(43655), // Rule ID 976 //
17185 /* 43627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17186 /* 43630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
17187 /* 43633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
17188 /* 43636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17189 /* 43640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17190 /* 43644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17191 /* 43648 */ // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
17192 /* 43648 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_D),
17193 /* 43653 */ GIR_RootConstrainSelectedInstOperands,
17194 /* 43654 */ // GIR_Coverage, 976,
17195 /* 43654 */ GIR_Done,
17196 /* 43655 */ // Label 1138: @43655
17197 /* 43655 */ GIM_Reject,
17198 /* 43656 */ // Label 1123: @43656
17199 /* 43656 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(43923),
17200 /* 43661 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
17201 /* 43664 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17202 /* 43667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17203 /* 43671 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(43785), // Rule ID 2486 //
17204 /* 43676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17205 /* 43679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17206 /* 43683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17207 /* 43687 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17208 /* 43691 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17209 /* 43695 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17210 /* 43699 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17211 /* 43703 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17212 /* 43706 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17213 /* 43710 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17214 /* 43714 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17215 /* 43718 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17216 /* 43722 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17217 /* 43726 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17218 /* 43730 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17219 /* 43734 */ // MIs[3] Operand 1
17220 /* 43734 */ // No operand predicates
17221 /* 43734 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17222 /* 43738 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17223 /* 43742 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17224 /* 43746 */ // MIs[4] Operand 1
17225 /* 43746 */ // No operand predicates
17226 /* 43746 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17227 /* 43750 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17228 /* 43754 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17229 /* 43758 */ // MIs[5] Operand 1
17230 /* 43758 */ // No operand predicates
17231 /* 43758 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17232 /* 43762 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17233 /* 43766 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17234 /* 43770 */ // MIs[6] Operand 1
17235 /* 43770 */ // No operand predicates
17236 /* 43770 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17237 /* 43772 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17238 /* 43772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17239 /* 43775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17240 /* 43777 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17241 /* 43779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17242 /* 43783 */ GIR_RootConstrainSelectedInstOperands,
17243 /* 43784 */ // GIR_Coverage, 2486,
17244 /* 43784 */ GIR_EraseRootFromParent_Done,
17245 /* 43785 */ // Label 1140: @43785
17246 /* 43785 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(43899), // Rule ID 2087 //
17247 /* 43790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17248 /* 43793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17249 /* 43797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17250 /* 43801 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17251 /* 43805 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17252 /* 43809 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17253 /* 43813 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17254 /* 43817 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17255 /* 43820 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17256 /* 43824 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17257 /* 43828 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17258 /* 43832 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17259 /* 43836 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17260 /* 43840 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17261 /* 43844 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17262 /* 43848 */ // MIs[3] Operand 1
17263 /* 43848 */ // No operand predicates
17264 /* 43848 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17265 /* 43852 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17266 /* 43856 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17267 /* 43860 */ // MIs[4] Operand 1
17268 /* 43860 */ // No operand predicates
17269 /* 43860 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17270 /* 43864 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17271 /* 43868 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17272 /* 43872 */ // MIs[5] Operand 1
17273 /* 43872 */ // No operand predicates
17274 /* 43872 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17275 /* 43876 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17276 /* 43880 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17277 /* 43884 */ // MIs[6] Operand 1
17278 /* 43884 */ // No operand predicates
17279 /* 43884 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17280 /* 43886 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17281 /* 43886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17282 /* 43889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17283 /* 43891 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17284 /* 43893 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17285 /* 43897 */ GIR_RootConstrainSelectedInstOperands,
17286 /* 43898 */ // GIR_Coverage, 2087,
17287 /* 43898 */ GIR_EraseRootFromParent_Done,
17288 /* 43899 */ // Label 1141: @43899
17289 /* 43899 */ GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(43922), // Rule ID 975 //
17290 /* 43904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17291 /* 43907 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17292 /* 43911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17293 /* 43915 */ // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
17294 /* 43915 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17295 /* 43920 */ GIR_RootConstrainSelectedInstOperands,
17296 /* 43921 */ // GIR_Coverage, 975,
17297 /* 43921 */ GIR_Done,
17298 /* 43922 */ // Label 1142: @43922
17299 /* 43922 */ GIM_Reject,
17300 /* 43923 */ // Label 1139: @43923
17301 /* 43923 */ GIM_Reject,
17302 /* 43924 */ // Label 1124: @43924
17303 /* 43924 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(44319),
17304 /* 43929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
17305 /* 43932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17306 /* 43935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17307 /* 43939 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(44117), // Rule ID 2485 //
17308 /* 43944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17309 /* 43947 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17310 /* 43951 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17311 /* 43955 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17312 /* 43959 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17313 /* 43963 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17314 /* 43967 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17315 /* 43971 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17316 /* 43974 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17317 /* 43978 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17318 /* 43982 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17319 /* 43986 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17320 /* 43990 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17321 /* 43994 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17322 /* 43998 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17323 /* 44002 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17324 /* 44006 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17325 /* 44010 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17326 /* 44014 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17327 /* 44018 */ // MIs[3] Operand 1
17328 /* 44018 */ // No operand predicates
17329 /* 44018 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17330 /* 44022 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17331 /* 44026 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17332 /* 44030 */ // MIs[4] Operand 1
17333 /* 44030 */ // No operand predicates
17334 /* 44030 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17335 /* 44034 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17336 /* 44038 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17337 /* 44042 */ // MIs[5] Operand 1
17338 /* 44042 */ // No operand predicates
17339 /* 44042 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17340 /* 44046 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17341 /* 44050 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17342 /* 44054 */ // MIs[6] Operand 1
17343 /* 44054 */ // No operand predicates
17344 /* 44054 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17345 /* 44058 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17346 /* 44062 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17347 /* 44066 */ // MIs[7] Operand 1
17348 /* 44066 */ // No operand predicates
17349 /* 44066 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17350 /* 44070 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17351 /* 44074 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17352 /* 44078 */ // MIs[8] Operand 1
17353 /* 44078 */ // No operand predicates
17354 /* 44078 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17355 /* 44082 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17356 /* 44086 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17357 /* 44090 */ // MIs[9] Operand 1
17358 /* 44090 */ // No operand predicates
17359 /* 44090 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17360 /* 44094 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17361 /* 44098 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17362 /* 44102 */ // MIs[10] Operand 1
17363 /* 44102 */ // No operand predicates
17364 /* 44102 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17365 /* 44104 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17366 /* 44104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17367 /* 44107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17368 /* 44109 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17369 /* 44111 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17370 /* 44115 */ GIR_RootConstrainSelectedInstOperands,
17371 /* 44116 */ // GIR_Coverage, 2485,
17372 /* 44116 */ GIR_EraseRootFromParent_Done,
17373 /* 44117 */ // Label 1144: @44117
17374 /* 44117 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(44295), // Rule ID 2086 //
17375 /* 44122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17376 /* 44125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17377 /* 44129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17378 /* 44133 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17379 /* 44137 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17380 /* 44141 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17381 /* 44145 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17382 /* 44149 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17383 /* 44152 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17384 /* 44156 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17385 /* 44160 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17386 /* 44164 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17387 /* 44168 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17388 /* 44172 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17389 /* 44176 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17390 /* 44180 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17391 /* 44184 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17392 /* 44188 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17393 /* 44192 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17394 /* 44196 */ // MIs[3] Operand 1
17395 /* 44196 */ // No operand predicates
17396 /* 44196 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17397 /* 44200 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17398 /* 44204 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17399 /* 44208 */ // MIs[4] Operand 1
17400 /* 44208 */ // No operand predicates
17401 /* 44208 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17402 /* 44212 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17403 /* 44216 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17404 /* 44220 */ // MIs[5] Operand 1
17405 /* 44220 */ // No operand predicates
17406 /* 44220 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17407 /* 44224 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17408 /* 44228 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17409 /* 44232 */ // MIs[6] Operand 1
17410 /* 44232 */ // No operand predicates
17411 /* 44232 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17412 /* 44236 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17413 /* 44240 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17414 /* 44244 */ // MIs[7] Operand 1
17415 /* 44244 */ // No operand predicates
17416 /* 44244 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17417 /* 44248 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17418 /* 44252 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17419 /* 44256 */ // MIs[8] Operand 1
17420 /* 44256 */ // No operand predicates
17421 /* 44256 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17422 /* 44260 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17423 /* 44264 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17424 /* 44268 */ // MIs[9] Operand 1
17425 /* 44268 */ // No operand predicates
17426 /* 44268 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17427 /* 44272 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17428 /* 44276 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17429 /* 44280 */ // MIs[10] Operand 1
17430 /* 44280 */ // No operand predicates
17431 /* 44280 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17432 /* 44282 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17433 /* 44282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17434 /* 44285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17435 /* 44287 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17436 /* 44289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17437 /* 44293 */ GIR_RootConstrainSelectedInstOperands,
17438 /* 44294 */ // GIR_Coverage, 2086,
17439 /* 44294 */ GIR_EraseRootFromParent_Done,
17440 /* 44295 */ // Label 1145: @44295
17441 /* 44295 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(44318), // Rule ID 974 //
17442 /* 44300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17443 /* 44303 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17444 /* 44307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17445 /* 44311 */ // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
17446 /* 44311 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17447 /* 44316 */ GIR_RootConstrainSelectedInstOperands,
17448 /* 44317 */ // GIR_Coverage, 974,
17449 /* 44317 */ GIR_Done,
17450 /* 44318 */ // Label 1146: @44318
17451 /* 44318 */ GIM_Reject,
17452 /* 44319 */ // Label 1143: @44319
17453 /* 44319 */ GIM_Reject,
17454 /* 44320 */ // Label 1125: @44320
17455 /* 44320 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(44971),
17456 /* 44325 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
17457 /* 44328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
17458 /* 44331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17459 /* 44335 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(44641), // Rule ID 2484 //
17460 /* 44340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17461 /* 44343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17462 /* 44347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17463 /* 44351 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17464 /* 44355 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17465 /* 44359 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17466 /* 44363 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17467 /* 44367 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17468 /* 44370 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17469 /* 44374 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17470 /* 44378 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17471 /* 44382 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17472 /* 44386 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17473 /* 44390 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17474 /* 44394 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17475 /* 44398 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17476 /* 44402 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17477 /* 44406 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17478 /* 44410 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17479 /* 44414 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17480 /* 44418 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17481 /* 44422 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17482 /* 44426 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17483 /* 44430 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17484 /* 44434 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17485 /* 44438 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17486 /* 44442 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17487 /* 44446 */ // MIs[3] Operand 1
17488 /* 44446 */ // No operand predicates
17489 /* 44446 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17490 /* 44450 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17491 /* 44454 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17492 /* 44458 */ // MIs[4] Operand 1
17493 /* 44458 */ // No operand predicates
17494 /* 44458 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17495 /* 44462 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17496 /* 44466 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17497 /* 44470 */ // MIs[5] Operand 1
17498 /* 44470 */ // No operand predicates
17499 /* 44470 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17500 /* 44474 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17501 /* 44478 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17502 /* 44482 */ // MIs[6] Operand 1
17503 /* 44482 */ // No operand predicates
17504 /* 44482 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17505 /* 44486 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17506 /* 44490 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17507 /* 44494 */ // MIs[7] Operand 1
17508 /* 44494 */ // No operand predicates
17509 /* 44494 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17510 /* 44498 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17511 /* 44502 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17512 /* 44506 */ // MIs[8] Operand 1
17513 /* 44506 */ // No operand predicates
17514 /* 44506 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17515 /* 44510 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17516 /* 44514 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17517 /* 44518 */ // MIs[9] Operand 1
17518 /* 44518 */ // No operand predicates
17519 /* 44518 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17520 /* 44522 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17521 /* 44526 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17522 /* 44530 */ // MIs[10] Operand 1
17523 /* 44530 */ // No operand predicates
17524 /* 44530 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17525 /* 44534 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17526 /* 44538 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17527 /* 44542 */ // MIs[11] Operand 1
17528 /* 44542 */ // No operand predicates
17529 /* 44542 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17530 /* 44546 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17531 /* 44550 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17532 /* 44554 */ // MIs[12] Operand 1
17533 /* 44554 */ // No operand predicates
17534 /* 44554 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17535 /* 44558 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17536 /* 44562 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17537 /* 44566 */ // MIs[13] Operand 1
17538 /* 44566 */ // No operand predicates
17539 /* 44566 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17540 /* 44570 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17541 /* 44574 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17542 /* 44578 */ // MIs[14] Operand 1
17543 /* 44578 */ // No operand predicates
17544 /* 44578 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17545 /* 44582 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17546 /* 44586 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17547 /* 44590 */ // MIs[15] Operand 1
17548 /* 44590 */ // No operand predicates
17549 /* 44590 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17550 /* 44594 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17551 /* 44598 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17552 /* 44602 */ // MIs[16] Operand 1
17553 /* 44602 */ // No operand predicates
17554 /* 44602 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17555 /* 44606 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17556 /* 44610 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17557 /* 44614 */ // MIs[17] Operand 1
17558 /* 44614 */ // No operand predicates
17559 /* 44614 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17560 /* 44618 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17561 /* 44622 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17562 /* 44626 */ // MIs[18] Operand 1
17563 /* 44626 */ // No operand predicates
17564 /* 44626 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17565 /* 44628 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17566 /* 44628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
17567 /* 44631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17568 /* 44633 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17569 /* 44635 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17570 /* 44639 */ GIR_RootConstrainSelectedInstOperands,
17571 /* 44640 */ // GIR_Coverage, 2484,
17572 /* 44640 */ GIR_EraseRootFromParent_Done,
17573 /* 44641 */ // Label 1148: @44641
17574 /* 44641 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(44947), // Rule ID 2085 //
17575 /* 44646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17576 /* 44649 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17577 /* 44653 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17578 /* 44657 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17579 /* 44661 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17580 /* 44665 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17581 /* 44669 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17582 /* 44673 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17583 /* 44676 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17584 /* 44680 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17585 /* 44684 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17586 /* 44688 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17587 /* 44692 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17588 /* 44696 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17589 /* 44700 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17590 /* 44704 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17591 /* 44708 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17592 /* 44712 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17593 /* 44716 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17594 /* 44720 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17595 /* 44724 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17596 /* 44728 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17597 /* 44732 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17598 /* 44736 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17599 /* 44740 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17600 /* 44744 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17601 /* 44748 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17602 /* 44752 */ // MIs[3] Operand 1
17603 /* 44752 */ // No operand predicates
17604 /* 44752 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17605 /* 44756 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17606 /* 44760 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17607 /* 44764 */ // MIs[4] Operand 1
17608 /* 44764 */ // No operand predicates
17609 /* 44764 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17610 /* 44768 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17611 /* 44772 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17612 /* 44776 */ // MIs[5] Operand 1
17613 /* 44776 */ // No operand predicates
17614 /* 44776 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17615 /* 44780 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17616 /* 44784 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17617 /* 44788 */ // MIs[6] Operand 1
17618 /* 44788 */ // No operand predicates
17619 /* 44788 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17620 /* 44792 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17621 /* 44796 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17622 /* 44800 */ // MIs[7] Operand 1
17623 /* 44800 */ // No operand predicates
17624 /* 44800 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17625 /* 44804 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17626 /* 44808 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17627 /* 44812 */ // MIs[8] Operand 1
17628 /* 44812 */ // No operand predicates
17629 /* 44812 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17630 /* 44816 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17631 /* 44820 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17632 /* 44824 */ // MIs[9] Operand 1
17633 /* 44824 */ // No operand predicates
17634 /* 44824 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17635 /* 44828 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17636 /* 44832 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17637 /* 44836 */ // MIs[10] Operand 1
17638 /* 44836 */ // No operand predicates
17639 /* 44836 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17640 /* 44840 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17641 /* 44844 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17642 /* 44848 */ // MIs[11] Operand 1
17643 /* 44848 */ // No operand predicates
17644 /* 44848 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17645 /* 44852 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17646 /* 44856 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17647 /* 44860 */ // MIs[12] Operand 1
17648 /* 44860 */ // No operand predicates
17649 /* 44860 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17650 /* 44864 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17651 /* 44868 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17652 /* 44872 */ // MIs[13] Operand 1
17653 /* 44872 */ // No operand predicates
17654 /* 44872 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17655 /* 44876 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17656 /* 44880 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17657 /* 44884 */ // MIs[14] Operand 1
17658 /* 44884 */ // No operand predicates
17659 /* 44884 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17660 /* 44888 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17661 /* 44892 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17662 /* 44896 */ // MIs[15] Operand 1
17663 /* 44896 */ // No operand predicates
17664 /* 44896 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17665 /* 44900 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17666 /* 44904 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17667 /* 44908 */ // MIs[16] Operand 1
17668 /* 44908 */ // No operand predicates
17669 /* 44908 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17670 /* 44912 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17671 /* 44916 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17672 /* 44920 */ // MIs[17] Operand 1
17673 /* 44920 */ // No operand predicates
17674 /* 44920 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17675 /* 44924 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17676 /* 44928 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17677 /* 44932 */ // MIs[18] Operand 1
17678 /* 44932 */ // No operand predicates
17679 /* 44932 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17680 /* 44934 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17681 /* 44934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
17682 /* 44937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17683 /* 44939 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17684 /* 44941 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17685 /* 44945 */ GIR_RootConstrainSelectedInstOperands,
17686 /* 44946 */ // GIR_Coverage, 2085,
17687 /* 44946 */ GIR_EraseRootFromParent_Done,
17688 /* 44947 */ // Label 1149: @44947
17689 /* 44947 */ GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(44970), // Rule ID 973 //
17690 /* 44952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17691 /* 44955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17692 /* 44959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17693 /* 44963 */ // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
17694 /* 44963 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
17695 /* 44968 */ GIR_RootConstrainSelectedInstOperands,
17696 /* 44969 */ // GIR_Coverage, 973,
17697 /* 44969 */ GIR_Done,
17698 /* 44970 */ // Label 1150: @44970
17699 /* 44970 */ GIM_Reject,
17700 /* 44971 */ // Label 1147: @44971
17701 /* 44971 */ GIM_Reject,
17702 /* 44972 */ // Label 1126: @44972
17703 /* 44972 */ GIM_Reject,
17704 /* 44973 */ // Label 40: @44973
17705 /* 44973 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1153*/ GIMT_Encode4(45260),
17706 /* 44984 */ /*GILLT_s32*//*Label 1151*/ GIMT_Encode4(44992),
17707 /* 44988 */ /*GILLT_s64*//*Label 1152*/ GIMT_Encode4(45119),
17708 /* 44992 */ // Label 1151: @44992
17709 /* 44992 */ GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(45118),
17710 /* 44997 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
17711 /* 45000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17712 /* 45003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17713 /* 45007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17714 /* 45011 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(45045), // Rule ID 67 //
17715 /* 45016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
17716 /* 45019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17717 /* 45023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17718 /* 45027 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17719 /* 45031 */ // MIs[1] Operand 1
17720 /* 45031 */ // No operand predicates
17721 /* 45031 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17722 /* 45033 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17723 /* 45033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
17724 /* 45036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17725 /* 45038 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17726 /* 45040 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17727 /* 45043 */ GIR_RootConstrainSelectedInstOperands,
17728 /* 45044 */ // GIR_Coverage, 67,
17729 /* 45044 */ GIR_EraseRootFromParent_Done,
17730 /* 45045 */ // Label 1155: @45045
17731 /* 45045 */ GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(45079), // Rule ID 1081 //
17732 /* 45050 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17733 /* 45053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17734 /* 45057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17735 /* 45061 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17736 /* 45065 */ // MIs[1] Operand 1
17737 /* 45065 */ // No operand predicates
17738 /* 45065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17739 /* 45067 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17740 /* 45067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
17741 /* 45070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17742 /* 45072 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17743 /* 45074 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17744 /* 45077 */ GIR_RootConstrainSelectedInstOperands,
17745 /* 45078 */ // GIR_Coverage, 1081,
17746 /* 45078 */ GIR_EraseRootFromParent_Done,
17747 /* 45079 */ // Label 1156: @45079
17748 /* 45079 */ GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(45098), // Rule ID 68 //
17749 /* 45084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
17750 /* 45087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17751 /* 45091 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17752 /* 45091 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV),
17753 /* 45096 */ GIR_RootConstrainSelectedInstOperands,
17754 /* 45097 */ // GIR_Coverage, 68,
17755 /* 45097 */ GIR_Done,
17756 /* 45098 */ // Label 1157: @45098
17757 /* 45098 */ GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(45117), // Rule ID 1082 //
17758 /* 45103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17759 /* 45106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17760 /* 45110 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17761 /* 45110 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV_MM),
17762 /* 45115 */ GIR_RootConstrainSelectedInstOperands,
17763 /* 45116 */ // GIR_Coverage, 1082,
17764 /* 45116 */ GIR_Done,
17765 /* 45117 */ // Label 1158: @45117
17766 /* 45117 */ GIM_Reject,
17767 /* 45118 */ // Label 1154: @45118
17768 /* 45118 */ GIM_Reject,
17769 /* 45119 */ // Label 1152: @45119
17770 /* 45119 */ GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(45259),
17771 /* 45124 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17772 /* 45127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17773 /* 45130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17774 /* 45134 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17775 /* 45138 */ GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(45172), // Rule ID 222 //
17776 /* 45143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
17777 /* 45146 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17778 /* 45150 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17779 /* 45154 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17780 /* 45158 */ // MIs[1] Operand 1
17781 /* 45158 */ // No operand predicates
17782 /* 45158 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17783 /* 45160 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
17784 /* 45160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTR),
17785 /* 45163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17786 /* 45165 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17787 /* 45167 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17788 /* 45170 */ GIR_RootConstrainSelectedInstOperands,
17789 /* 45171 */ // GIR_Coverage, 222,
17790 /* 45171 */ GIR_EraseRootFromParent_Done,
17791 /* 45172 */ // Label 1160: @45172
17792 /* 45172 */ GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(45239), // Rule ID 1579 //
17793 /* 45177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
17794 /* 45180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17795 /* 45184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
17796 /* 45188 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17797 /* 45192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17798 /* 45197 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17799 /* 45199 */ // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
17800 /* 45199 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17801 /* 45202 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17802 /* 45206 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17803 /* 45211 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17804 /* 45217 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17805 /* 45222 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17806 /* 45227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
17807 /* 45230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17808 /* 45232 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17809 /* 45234 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17810 /* 45237 */ GIR_RootConstrainSelectedInstOperands,
17811 /* 45238 */ // GIR_Coverage, 1579,
17812 /* 45238 */ GIR_EraseRootFromParent_Done,
17813 /* 45239 */ // Label 1161: @45239
17814 /* 45239 */ GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(45258), // Rule ID 223 //
17815 /* 45244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
17816 /* 45247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17817 /* 45251 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17818 /* 45251 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
17819 /* 45256 */ GIR_RootConstrainSelectedInstOperands,
17820 /* 45257 */ // GIR_Coverage, 223,
17821 /* 45257 */ GIR_Done,
17822 /* 45258 */ // Label 1162: @45258
17823 /* 45258 */ GIM_Reject,
17824 /* 45259 */ // Label 1159: @45259
17825 /* 45259 */ GIM_Reject,
17826 /* 45260 */ // Label 1153: @45260
17827 /* 45260 */ GIM_Reject,
17828 /* 45261 */ // Label 41: @45261
17829 /* 45261 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(47791),
17830 /* 45266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17831 /* 45269 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1166*/ GIMT_Encode4(45454),
17832 /* 45280 */ /*GILLT_s32*//*Label 1164*/ GIMT_Encode4(45288),
17833 /* 45284 */ /*GILLT_s64*//*Label 1165*/ GIMT_Encode4(45371),
17834 /* 45288 */ // Label 1164: @45288
17835 /* 45288 */ GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(45370),
17836 /* 45293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17837 /* 45296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17838 /* 45300 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(45333), // Rule ID 1415 //
17839 /* 45305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17840 /* 45308 */ // MIs[0] Operand 1
17841 /* 45308 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17842 /* 45313 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17843 /* 45317 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17844 /* 45321 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17845 /* 45321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
17846 /* 45324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17847 /* 45326 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17848 /* 45328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17849 /* 45331 */ GIR_RootConstrainSelectedInstOperands,
17850 /* 45332 */ // GIR_Coverage, 1415,
17851 /* 45332 */ GIR_EraseRootFromParent_Done,
17852 /* 45333 */ // Label 1168: @45333
17853 /* 45333 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(45369), // Rule ID 1416 //
17854 /* 45338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17855 /* 45341 */ // MIs[0] Operand 1
17856 /* 45341 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17857 /* 45346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17858 /* 45350 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17859 /* 45354 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
17860 /* 45354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17861 /* 45357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17862 /* 45359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17863 /* 45365 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17864 /* 45367 */ GIR_RootConstrainSelectedInstOperands,
17865 /* 45368 */ // GIR_Coverage, 1416,
17866 /* 45368 */ GIR_EraseRootFromParent_Done,
17867 /* 45369 */ // Label 1169: @45369
17868 /* 45369 */ GIM_Reject,
17869 /* 45370 */ // Label 1167: @45370
17870 /* 45370 */ GIM_Reject,
17871 /* 45371 */ // Label 1165: @45371
17872 /* 45371 */ GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(45453),
17873 /* 45376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
17874 /* 45379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17875 /* 45383 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(45416), // Rule ID 1561 //
17876 /* 45388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17877 /* 45391 */ // MIs[0] Operand 1
17878 /* 45391 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17879 /* 45396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17880 /* 45400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17881 /* 45404 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
17882 /* 45404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
17883 /* 45407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17884 /* 45409 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17885 /* 45411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17886 /* 45414 */ GIR_RootConstrainSelectedInstOperands,
17887 /* 45415 */ // GIR_Coverage, 1561,
17888 /* 45415 */ GIR_EraseRootFromParent_Done,
17889 /* 45416 */ // Label 1171: @45416
17890 /* 45416 */ GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(45452), // Rule ID 1562 //
17891 /* 45421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17892 /* 45424 */ // MIs[0] Operand 1
17893 /* 45424 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17894 /* 45429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17895 /* 45433 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17896 /* 45437 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
17897 /* 45437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
17898 /* 45440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17899 /* 45442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17900 /* 45448 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17901 /* 45450 */ GIR_RootConstrainSelectedInstOperands,
17902 /* 45451 */ // GIR_Coverage, 1562,
17903 /* 45451 */ GIR_EraseRootFromParent_Done,
17904 /* 45452 */ // Label 1172: @45452
17905 /* 45452 */ GIM_Reject,
17906 /* 45453 */ // Label 1170: @45453
17907 /* 45453 */ GIM_Reject,
17908 /* 45454 */ // Label 1166: @45454
17909 /* 45454 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1175*/ GIMT_Encode4(45837),
17910 /* 45465 */ /*GILLT_s32*//*Label 1173*/ GIMT_Encode4(45473),
17911 /* 45469 */ /*GILLT_s64*//*Label 1174*/ GIMT_Encode4(45759),
17912 /* 45473 */ // Label 1173: @45473
17913 /* 45473 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(45758),
17914 /* 45478 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17915 /* 45481 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(45518), // Rule ID 1887 //
17916 /* 45486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17917 /* 45489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17918 /* 45493 */ // MIs[0] Operand 1
17919 /* 45493 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17920 /* 45498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17921 /* 45502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17922 /* 45506 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17923 /* 45506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
17924 /* 45509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17925 /* 45511 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17926 /* 45513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17927 /* 45516 */ GIR_RootConstrainSelectedInstOperands,
17928 /* 45517 */ // GIR_Coverage, 1887,
17929 /* 45517 */ GIR_EraseRootFromParent_Done,
17930 /* 45518 */ // Label 1177: @45518
17931 /* 45518 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(45608), // Rule ID 1889 //
17932 /* 45523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17933 /* 45526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17934 /* 45530 */ // MIs[0] Operand 1
17935 /* 45530 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17936 /* 45535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17937 /* 45539 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-32769),
17938 /* 45550 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
17939 /* 45550 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17940 /* 45553 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17941 /* 45557 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17942 /* 45562 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17943 /* 45565 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17944 /* 45567 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17945 /* 45570 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltiCCRxImmX16),
17946 /* 45574 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17947 /* 45579 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17948 /* 45583 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-32768),
17949 /* 45593 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17950 /* 45595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17951 /* 45598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17952 /* 45600 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17953 /* 45603 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17954 /* 45606 */ GIR_RootConstrainSelectedInstOperands,
17955 /* 45607 */ // GIR_Coverage, 1889,
17956 /* 45607 */ GIR_EraseRootFromParent_Done,
17957 /* 45608 */ // Label 1178: @45608
17958 /* 45608 */ GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(45645), // Rule ID 2208 //
17959 /* 45613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17960 /* 45616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17961 /* 45620 */ // MIs[0] Operand 1
17962 /* 45620 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17963 /* 45625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17964 /* 45629 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17965 /* 45633 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17966 /* 45633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
17967 /* 45636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17968 /* 45638 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17969 /* 45640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17970 /* 45643 */ GIR_RootConstrainSelectedInstOperands,
17971 /* 45644 */ // GIR_Coverage, 2208,
17972 /* 45644 */ GIR_EraseRootFromParent_Done,
17973 /* 45645 */ // Label 1179: @45645
17974 /* 45645 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(45685), // Rule ID 2209 //
17975 /* 45650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17976 /* 45653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17977 /* 45657 */ // MIs[0] Operand 1
17978 /* 45657 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17979 /* 45662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17980 /* 45666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17981 /* 45670 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
17982 /* 45670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17983 /* 45673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17984 /* 45675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17985 /* 45681 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17986 /* 45683 */ GIR_RootConstrainSelectedInstOperands,
17987 /* 45684 */ // GIR_Coverage, 2209,
17988 /* 45684 */ GIR_EraseRootFromParent_Done,
17989 /* 45685 */ // Label 1180: @45685
17990 /* 45685 */ GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(45721), // Rule ID 49 //
17991 /* 45690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17992 /* 45693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17993 /* 45697 */ // MIs[0] Operand 1
17994 /* 45697 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17995 /* 45702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17996 /* 45706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17997 /* 45710 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17998 /* 45710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
17999 /* 45713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18000 /* 45715 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18001 /* 45717 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18002 /* 45719 */ GIR_RootConstrainSelectedInstOperands,
18003 /* 45720 */ // GIR_Coverage, 49,
18004 /* 45720 */ GIR_EraseRootFromParent_Done,
18005 /* 45721 */ // Label 1181: @45721
18006 /* 45721 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(45757), // Rule ID 50 //
18007 /* 45726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18008 /* 45729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18009 /* 45733 */ // MIs[0] Operand 1
18010 /* 45733 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18011 /* 45738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18012 /* 45742 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18013 /* 45746 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18014 /* 45746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18015 /* 45749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18016 /* 45751 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18017 /* 45753 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18018 /* 45755 */ GIR_RootConstrainSelectedInstOperands,
18019 /* 45756 */ // GIR_Coverage, 50,
18020 /* 45756 */ GIR_EraseRootFromParent_Done,
18021 /* 45757 */ // Label 1182: @45757
18022 /* 45757 */ GIM_Reject,
18023 /* 45758 */ // Label 1176: @45758
18024 /* 45758 */ GIM_Reject,
18025 /* 45759 */ // Label 1174: @45759
18026 /* 45759 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(45836),
18027 /* 45764 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18028 /* 45767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18029 /* 45771 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(45803), // Rule ID 204 //
18030 /* 45776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
18031 /* 45779 */ // MIs[0] Operand 1
18032 /* 45779 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18033 /* 45784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18034 /* 45788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18035 /* 45792 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18036 /* 45792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18037 /* 45795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18038 /* 45797 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18039 /* 45799 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18040 /* 45801 */ GIR_RootConstrainSelectedInstOperands,
18041 /* 45802 */ // GIR_Coverage, 204,
18042 /* 45802 */ GIR_EraseRootFromParent_Done,
18043 /* 45803 */ // Label 1184: @45803
18044 /* 45803 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(45835), // Rule ID 205 //
18045 /* 45808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
18046 /* 45811 */ // MIs[0] Operand 1
18047 /* 45811 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18048 /* 45816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18049 /* 45820 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18050 /* 45824 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18051 /* 45824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18052 /* 45827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18053 /* 45829 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18054 /* 45831 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18055 /* 45833 */ GIR_RootConstrainSelectedInstOperands,
18056 /* 45834 */ // GIR_Coverage, 205,
18057 /* 45834 */ GIR_EraseRootFromParent_Done,
18058 /* 45835 */ // Label 1185: @45835
18059 /* 45835 */ GIM_Reject,
18060 /* 45836 */ // Label 1183: @45836
18061 /* 45836 */ GIM_Reject,
18062 /* 45837 */ // Label 1175: @45837
18063 /* 45837 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1188*/ GIMT_Encode4(46754),
18064 /* 45848 */ /*GILLT_s32*//*Label 1186*/ GIMT_Encode4(45856),
18065 /* 45852 */ /*GILLT_s64*//*Label 1187*/ GIMT_Encode4(46337),
18066 /* 45856 */ // Label 1186: @45856
18067 /* 45856 */ GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(46336),
18068 /* 45861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18069 /* 45864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18070 /* 45868 */ GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(45900), // Rule ID 1075 //
18071 /* 45873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18072 /* 45876 */ // MIs[0] Operand 1
18073 /* 45876 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18074 /* 45881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18075 /* 45885 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18076 /* 45889 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18077 /* 45889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18078 /* 45892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18079 /* 45894 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18080 /* 45896 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18081 /* 45898 */ GIR_RootConstrainSelectedInstOperands,
18082 /* 45899 */ // GIR_Coverage, 1075,
18083 /* 45899 */ GIR_EraseRootFromParent_Done,
18084 /* 45900 */ // Label 1190: @45900
18085 /* 45900 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(45932), // Rule ID 1076 //
18086 /* 45905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18087 /* 45908 */ // MIs[0] Operand 1
18088 /* 45908 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18089 /* 45913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18090 /* 45917 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18091 /* 45921 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18092 /* 45921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18093 /* 45924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18094 /* 45926 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18095 /* 45928 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18096 /* 45930 */ GIR_RootConstrainSelectedInstOperands,
18097 /* 45931 */ // GIR_Coverage, 1076,
18098 /* 45931 */ GIR_EraseRootFromParent_Done,
18099 /* 45932 */ // Label 1191: @45932
18100 /* 45932 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(45988), // Rule ID 1417 //
18101 /* 45937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18102 /* 45940 */ // MIs[0] Operand 1
18103 /* 45940 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18104 /* 45945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18105 /* 45949 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18106 /* 45953 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18107 /* 45953 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18108 /* 45956 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
18109 /* 45960 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18110 /* 45965 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18111 /* 45969 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18112 /* 45973 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18113 /* 45975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
18114 /* 45978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18115 /* 45980 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18116 /* 45983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18117 /* 45986 */ GIR_RootConstrainSelectedInstOperands,
18118 /* 45987 */ // GIR_Coverage, 1417,
18119 /* 45987 */ GIR_EraseRootFromParent_Done,
18120 /* 45988 */ // Label 1192: @45988
18121 /* 45988 */ GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(46047), // Rule ID 1418 //
18122 /* 45993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18123 /* 45996 */ // MIs[0] Operand 1
18124 /* 45996 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18125 /* 46001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18126 /* 46005 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18127 /* 46009 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
18128 /* 46009 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18129 /* 46012 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
18130 /* 46016 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18131 /* 46021 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18132 /* 46025 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18133 /* 46029 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18134 /* 46031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18135 /* 46034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18136 /* 46036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18137 /* 46042 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18138 /* 46045 */ GIR_RootConstrainSelectedInstOperands,
18139 /* 46046 */ // GIR_Coverage, 1418,
18140 /* 46046 */ GIR_EraseRootFromParent_Done,
18141 /* 46047 */ // Label 1193: @46047
18142 /* 46047 */ GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(46103), // Rule ID 1419 //
18143 /* 46052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18144 /* 46055 */ // MIs[0] Operand 1
18145 /* 46055 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18146 /* 46060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18147 /* 46064 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18148 /* 46068 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18149 /* 46068 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18150 /* 46071 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
18151 /* 46075 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18152 /* 46080 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18153 /* 46084 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18154 /* 46088 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18155 /* 46090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18156 /* 46093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18157 /* 46095 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18158 /* 46098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18159 /* 46101 */ GIR_RootConstrainSelectedInstOperands,
18160 /* 46102 */ // GIR_Coverage, 1419,
18161 /* 46102 */ GIR_EraseRootFromParent_Done,
18162 /* 46103 */ // Label 1194: @46103
18163 /* 46103 */ GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(46159), // Rule ID 1420 //
18164 /* 46108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18165 /* 46111 */ // MIs[0] Operand 1
18166 /* 46111 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18167 /* 46116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18168 /* 46120 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18169 /* 46124 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18170 /* 46124 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18171 /* 46127 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18172 /* 46131 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18173 /* 46136 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18174 /* 46140 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18175 /* 46144 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18176 /* 46146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18177 /* 46149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18178 /* 46151 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18179 /* 46154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18180 /* 46157 */ GIR_RootConstrainSelectedInstOperands,
18181 /* 46158 */ // GIR_Coverage, 1420,
18182 /* 46158 */ GIR_EraseRootFromParent_Done,
18183 /* 46159 */ // Label 1195: @46159
18184 /* 46159 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(46191), // Rule ID 1421 //
18185 /* 46164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18186 /* 46167 */ // MIs[0] Operand 1
18187 /* 46167 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18188 /* 46172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18189 /* 46176 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18190 /* 46180 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18191 /* 46180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
18192 /* 46183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18193 /* 46185 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18194 /* 46187 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18195 /* 46189 */ GIR_RootConstrainSelectedInstOperands,
18196 /* 46190 */ // GIR_Coverage, 1421,
18197 /* 46190 */ GIR_EraseRootFromParent_Done,
18198 /* 46191 */ // Label 1196: @46191
18199 /* 46191 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(46223), // Rule ID 1422 //
18200 /* 46196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18201 /* 46199 */ // MIs[0] Operand 1
18202 /* 46199 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18203 /* 46204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18204 /* 46208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18205 /* 46212 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18206 /* 46212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18207 /* 46215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18208 /* 46217 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18209 /* 46219 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18210 /* 46221 */ GIR_RootConstrainSelectedInstOperands,
18211 /* 46222 */ // GIR_Coverage, 1422,
18212 /* 46222 */ GIR_EraseRootFromParent_Done,
18213 /* 46223 */ // Label 1197: @46223
18214 /* 46223 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(46279), // Rule ID 1423 //
18215 /* 46228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18216 /* 46231 */ // MIs[0] Operand 1
18217 /* 46231 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18218 /* 46236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18219 /* 46240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18220 /* 46244 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18221 /* 46244 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18222 /* 46247 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
18223 /* 46251 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18224 /* 46256 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18225 /* 46260 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18226 /* 46264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18227 /* 46266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18228 /* 46269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18229 /* 46271 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18230 /* 46274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18231 /* 46277 */ GIR_RootConstrainSelectedInstOperands,
18232 /* 46278 */ // GIR_Coverage, 1423,
18233 /* 46278 */ GIR_EraseRootFromParent_Done,
18234 /* 46279 */ // Label 1198: @46279
18235 /* 46279 */ GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(46335), // Rule ID 1424 //
18236 /* 46284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18237 /* 46287 */ // MIs[0] Operand 1
18238 /* 46287 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18239 /* 46292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18240 /* 46296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18241 /* 46300 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18242 /* 46300 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18243 /* 46303 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18244 /* 46307 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18245 /* 46312 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18246 /* 46316 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18247 /* 46320 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18248 /* 46322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18249 /* 46325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18250 /* 46327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18251 /* 46330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18252 /* 46333 */ GIR_RootConstrainSelectedInstOperands,
18253 /* 46334 */ // GIR_Coverage, 1424,
18254 /* 46334 */ GIR_EraseRootFromParent_Done,
18255 /* 46335 */ // Label 1199: @46335
18256 /* 46335 */ GIM_Reject,
18257 /* 46336 */ // Label 1189: @46336
18258 /* 46336 */ GIM_Reject,
18259 /* 46337 */ // Label 1187: @46337
18260 /* 46337 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(46753),
18261 /* 46342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18262 /* 46345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18263 /* 46349 */ GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(46405), // Rule ID 1563 //
18264 /* 46354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18265 /* 46357 */ // MIs[0] Operand 1
18266 /* 46357 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18267 /* 46362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18268 /* 46366 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18269 /* 46370 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
18270 /* 46370 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18271 /* 46373 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
18272 /* 46377 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18273 /* 46382 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18274 /* 46386 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18275 /* 46390 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18276 /* 46392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18277 /* 46395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18278 /* 46397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18279 /* 46400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18280 /* 46403 */ GIR_RootConstrainSelectedInstOperands,
18281 /* 46404 */ // GIR_Coverage, 1563,
18282 /* 46404 */ GIR_EraseRootFromParent_Done,
18283 /* 46405 */ // Label 1201: @46405
18284 /* 46405 */ GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(46464), // Rule ID 1564 //
18285 /* 46410 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18286 /* 46413 */ // MIs[0] Operand 1
18287 /* 46413 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18288 /* 46418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18289 /* 46422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18290 /* 46426 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
18291 /* 46426 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18292 /* 46429 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
18293 /* 46433 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18294 /* 46438 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18295 /* 46442 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18296 /* 46446 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18297 /* 46448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18298 /* 46451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18299 /* 46453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18300 /* 46459 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18301 /* 46462 */ GIR_RootConstrainSelectedInstOperands,
18302 /* 46463 */ // GIR_Coverage, 1564,
18303 /* 46463 */ GIR_EraseRootFromParent_Done,
18304 /* 46464 */ // Label 1202: @46464
18305 /* 46464 */ GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(46520), // Rule ID 1565 //
18306 /* 46469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18307 /* 46472 */ // MIs[0] Operand 1
18308 /* 46472 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18309 /* 46477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18310 /* 46481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18311 /* 46485 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
18312 /* 46485 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18313 /* 46488 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18314 /* 46492 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18315 /* 46497 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18316 /* 46501 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18317 /* 46505 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18318 /* 46507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18319 /* 46510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18320 /* 46512 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18321 /* 46515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18322 /* 46518 */ GIR_RootConstrainSelectedInstOperands,
18323 /* 46519 */ // GIR_Coverage, 1565,
18324 /* 46519 */ GIR_EraseRootFromParent_Done,
18325 /* 46520 */ // Label 1203: @46520
18326 /* 46520 */ GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(46576), // Rule ID 1566 //
18327 /* 46525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18328 /* 46528 */ // MIs[0] Operand 1
18329 /* 46528 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18330 /* 46533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18331 /* 46537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18332 /* 46541 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
18333 /* 46541 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18334 /* 46544 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18335 /* 46548 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18336 /* 46553 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18337 /* 46557 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18338 /* 46561 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18339 /* 46563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18340 /* 46566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18341 /* 46568 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18342 /* 46571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18343 /* 46574 */ GIR_RootConstrainSelectedInstOperands,
18344 /* 46575 */ // GIR_Coverage, 1566,
18345 /* 46575 */ GIR_EraseRootFromParent_Done,
18346 /* 46576 */ // Label 1204: @46576
18347 /* 46576 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(46608), // Rule ID 1567 //
18348 /* 46581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18349 /* 46584 */ // MIs[0] Operand 1
18350 /* 46584 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18351 /* 46589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18352 /* 46593 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18353 /* 46597 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
18354 /* 46597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18355 /* 46600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18356 /* 46602 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18357 /* 46604 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18358 /* 46606 */ GIR_RootConstrainSelectedInstOperands,
18359 /* 46607 */ // GIR_Coverage, 1567,
18360 /* 46607 */ GIR_EraseRootFromParent_Done,
18361 /* 46608 */ // Label 1205: @46608
18362 /* 46608 */ GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(46640), // Rule ID 1568 //
18363 /* 46613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18364 /* 46616 */ // MIs[0] Operand 1
18365 /* 46616 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18366 /* 46621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18367 /* 46625 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18368 /* 46629 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
18369 /* 46629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18370 /* 46632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18371 /* 46634 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18372 /* 46636 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18373 /* 46638 */ GIR_RootConstrainSelectedInstOperands,
18374 /* 46639 */ // GIR_Coverage, 1568,
18375 /* 46639 */ GIR_EraseRootFromParent_Done,
18376 /* 46640 */ // Label 1206: @46640
18377 /* 46640 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(46696), // Rule ID 1569 //
18378 /* 46645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18379 /* 46648 */ // MIs[0] Operand 1
18380 /* 46648 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18381 /* 46653 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18382 /* 46657 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18383 /* 46661 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
18384 /* 46661 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18385 /* 46664 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18386 /* 46668 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18387 /* 46673 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18388 /* 46677 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18389 /* 46681 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18390 /* 46683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18391 /* 46686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18392 /* 46688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18393 /* 46691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18394 /* 46694 */ GIR_RootConstrainSelectedInstOperands,
18395 /* 46695 */ // GIR_Coverage, 1569,
18396 /* 46695 */ GIR_EraseRootFromParent_Done,
18397 /* 46696 */ // Label 1207: @46696
18398 /* 46696 */ GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(46752), // Rule ID 1570 //
18399 /* 46701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18400 /* 46704 */ // MIs[0] Operand 1
18401 /* 46704 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18402 /* 46709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18403 /* 46713 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18404 /* 46717 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
18405 /* 46717 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18406 /* 46720 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18407 /* 46724 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18408 /* 46729 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18409 /* 46733 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18410 /* 46737 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18411 /* 46739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18412 /* 46742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18413 /* 46744 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18414 /* 46747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18415 /* 46750 */ GIR_RootConstrainSelectedInstOperands,
18416 /* 46751 */ // GIR_Coverage, 1570,
18417 /* 46751 */ GIR_EraseRootFromParent_Done,
18418 /* 46752 */ // Label 1208: @46752
18419 /* 46752 */ GIM_Reject,
18420 /* 46753 */ // Label 1200: @46753
18421 /* 46753 */ GIM_Reject,
18422 /* 46754 */ // Label 1188: @46754
18423 /* 46754 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(47790),
18424 /* 46759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18425 /* 46762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18426 /* 46765 */ GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(46825), // Rule ID 1886 //
18427 /* 46770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18428 /* 46773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18429 /* 46777 */ // MIs[0] Operand 1
18430 /* 46777 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18431 /* 46782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18432 /* 46786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18433 /* 46790 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18434 /* 46790 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18435 /* 46793 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18436 /* 46797 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18437 /* 46802 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18438 /* 46806 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18439 /* 46810 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18440 /* 46812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
18441 /* 46815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18442 /* 46817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18443 /* 46820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18444 /* 46823 */ GIR_RootConstrainSelectedInstOperands,
18445 /* 46824 */ // GIR_Coverage, 1886,
18446 /* 46824 */ GIR_EraseRootFromParent_Done,
18447 /* 46825 */ // Label 1210: @46825
18448 /* 46825 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(46902), // Rule ID 1888 //
18449 /* 46830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18450 /* 46833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18451 /* 46837 */ // MIs[0] Operand 1
18452 /* 46837 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18453 /* 46842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18454 /* 46846 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18455 /* 46850 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18456 /* 46850 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18457 /* 46853 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18458 /* 46857 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18459 /* 46862 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18460 /* 46865 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18461 /* 46867 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18462 /* 46870 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
18463 /* 46874 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18464 /* 46879 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18465 /* 46883 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18466 /* 46887 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18467 /* 46889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18468 /* 46892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18469 /* 46894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18470 /* 46897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18471 /* 46900 */ GIR_RootConstrainSelectedInstOperands,
18472 /* 46901 */ // GIR_Coverage, 1888,
18473 /* 46901 */ GIR_EraseRootFromParent_Done,
18474 /* 46902 */ // Label 1211: @46902
18475 /* 46902 */ GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(46938), // Rule ID 1890 //
18476 /* 46907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18477 /* 46910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18478 /* 46914 */ // MIs[0] Operand 1
18479 /* 46914 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18480 /* 46919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18481 /* 46923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18482 /* 46927 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
18483 /* 46927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
18484 /* 46930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18485 /* 46932 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18486 /* 46934 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18487 /* 46936 */ GIR_RootConstrainSelectedInstOperands,
18488 /* 46937 */ // GIR_Coverage, 1890,
18489 /* 46937 */ GIR_EraseRootFromParent_Done,
18490 /* 46938 */ // Label 1212: @46938
18491 /* 46938 */ GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(47015), // Rule ID 1891 //
18492 /* 46943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18493 /* 46946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18494 /* 46950 */ // MIs[0] Operand 1
18495 /* 46950 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18496 /* 46955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18497 /* 46959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18498 /* 46963 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
18499 /* 46963 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18500 /* 46966 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImm16),
18501 /* 46970 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18502 /* 46975 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18503 /* 46978 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18504 /* 46980 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18505 /* 46983 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
18506 /* 46987 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18507 /* 46992 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18508 /* 46996 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18509 /* 47000 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18510 /* 47002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18511 /* 47005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18512 /* 47007 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18513 /* 47010 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18514 /* 47013 */ GIR_RootConstrainSelectedInstOperands,
18515 /* 47014 */ // GIR_Coverage, 1891,
18516 /* 47014 */ GIR_EraseRootFromParent_Done,
18517 /* 47015 */ // Label 1213: @47015
18518 /* 47015 */ GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(47051), // Rule ID 1892 //
18519 /* 47020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18520 /* 47023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18521 /* 47027 */ // MIs[0] Operand 1
18522 /* 47027 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18523 /* 47032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18524 /* 47036 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18525 /* 47040 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
18526 /* 47040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
18527 /* 47043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18528 /* 47045 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
18529 /* 47047 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
18530 /* 47049 */ GIR_RootConstrainSelectedInstOperands,
18531 /* 47050 */ // GIR_Coverage, 1892,
18532 /* 47050 */ GIR_EraseRootFromParent_Done,
18533 /* 47051 */ // Label 1214: @47051
18534 /* 47051 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(47128), // Rule ID 1894 //
18535 /* 47056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18536 /* 47059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18537 /* 47063 */ // MIs[0] Operand 1
18538 /* 47063 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18539 /* 47068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18540 /* 47072 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18541 /* 47076 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
18542 /* 47076 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18543 /* 47079 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18544 /* 47083 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18545 /* 47088 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18546 /* 47092 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18547 /* 47096 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18548 /* 47098 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18549 /* 47101 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18550 /* 47105 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18551 /* 47110 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
18552 /* 47113 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18553 /* 47115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18554 /* 47118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18555 /* 47120 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18556 /* 47123 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18557 /* 47126 */ GIR_RootConstrainSelectedInstOperands,
18558 /* 47127 */ // GIR_Coverage, 1894,
18559 /* 47127 */ GIR_EraseRootFromParent_Done,
18560 /* 47128 */ // Label 1215: @47128
18561 /* 47128 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(47205), // Rule ID 1895 //
18562 /* 47133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18563 /* 47136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18564 /* 47140 */ // MIs[0] Operand 1
18565 /* 47140 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18566 /* 47145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18567 /* 47149 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18568 /* 47153 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18569 /* 47153 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18570 /* 47156 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18571 /* 47160 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18572 /* 47165 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18573 /* 47168 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18574 /* 47170 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18575 /* 47173 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18576 /* 47177 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18577 /* 47182 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18578 /* 47186 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18579 /* 47190 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18580 /* 47192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18581 /* 47195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18582 /* 47197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18583 /* 47200 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18584 /* 47203 */ GIR_RootConstrainSelectedInstOperands,
18585 /* 47204 */ // GIR_Coverage, 1895,
18586 /* 47204 */ GIR_EraseRootFromParent_Done,
18587 /* 47205 */ // Label 1216: @47205
18588 /* 47205 */ GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(47241), // Rule ID 1896 //
18589 /* 47210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18590 /* 47213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18591 /* 47217 */ // MIs[0] Operand 1
18592 /* 47217 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18593 /* 47222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18594 /* 47226 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18595 /* 47230 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
18596 /* 47230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18597 /* 47233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18598 /* 47235 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18599 /* 47237 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18600 /* 47239 */ GIR_RootConstrainSelectedInstOperands,
18601 /* 47240 */ // GIR_Coverage, 1896,
18602 /* 47240 */ GIR_EraseRootFromParent_Done,
18603 /* 47241 */ // Label 1217: @47241
18604 /* 47241 */ GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(47318), // Rule ID 1897 //
18605 /* 47246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18606 /* 47249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18607 /* 47253 */ // MIs[0] Operand 1
18608 /* 47253 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18609 /* 47258 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18610 /* 47262 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18611 /* 47266 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18612 /* 47266 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18613 /* 47269 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18614 /* 47273 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18615 /* 47278 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18616 /* 47281 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18617 /* 47283 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18618 /* 47286 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18619 /* 47290 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18620 /* 47295 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18621 /* 47299 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18622 /* 47303 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18623 /* 47305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18624 /* 47308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18625 /* 47310 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18626 /* 47313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18627 /* 47316 */ GIR_RootConstrainSelectedInstOperands,
18628 /* 47317 */ // GIR_Coverage, 1897,
18629 /* 47317 */ GIR_EraseRootFromParent_Done,
18630 /* 47318 */ // Label 1218: @47318
18631 /* 47318 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(47354), // Rule ID 1898 //
18632 /* 47323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18633 /* 47326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18634 /* 47330 */ // MIs[0] Operand 1
18635 /* 47330 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18636 /* 47335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18637 /* 47339 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18638 /* 47343 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
18639 /* 47343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18640 /* 47346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18641 /* 47348 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
18642 /* 47350 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
18643 /* 47352 */ GIR_RootConstrainSelectedInstOperands,
18644 /* 47353 */ // GIR_Coverage, 1898,
18645 /* 47353 */ GIR_EraseRootFromParent_Done,
18646 /* 47354 */ // Label 1219: @47354
18647 /* 47354 */ GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(47414), // Rule ID 2210 //
18648 /* 47359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18649 /* 47362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18650 /* 47366 */ // MIs[0] Operand 1
18651 /* 47366 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18652 /* 47371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18653 /* 47375 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18654 /* 47379 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18655 /* 47379 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18656 /* 47382 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
18657 /* 47386 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18658 /* 47391 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18659 /* 47395 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18660 /* 47399 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18661 /* 47401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
18662 /* 47404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18663 /* 47406 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18664 /* 47409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18665 /* 47412 */ GIR_RootConstrainSelectedInstOperands,
18666 /* 47413 */ // GIR_Coverage, 2210,
18667 /* 47413 */ GIR_EraseRootFromParent_Done,
18668 /* 47414 */ // Label 1220: @47414
18669 /* 47414 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(47477), // Rule ID 2211 //
18670 /* 47419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18671 /* 47422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18672 /* 47426 */ // MIs[0] Operand 1
18673 /* 47426 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18674 /* 47431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18675 /* 47435 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18676 /* 47439 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
18677 /* 47439 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18678 /* 47442 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
18679 /* 47446 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18680 /* 47451 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18681 /* 47455 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18682 /* 47459 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18683 /* 47461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18684 /* 47464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18685 /* 47466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18686 /* 47472 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18687 /* 47475 */ GIR_RootConstrainSelectedInstOperands,
18688 /* 47476 */ // GIR_Coverage, 2211,
18689 /* 47476 */ GIR_EraseRootFromParent_Done,
18690 /* 47477 */ // Label 1221: @47477
18691 /* 47477 */ GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(47537), // Rule ID 2212 //
18692 /* 47482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18693 /* 47485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18694 /* 47489 */ // MIs[0] Operand 1
18695 /* 47489 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18696 /* 47494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18697 /* 47498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18698 /* 47502 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18699 /* 47502 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18700 /* 47505 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18701 /* 47509 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18702 /* 47514 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18703 /* 47518 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18704 /* 47522 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18705 /* 47524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18706 /* 47527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18707 /* 47529 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18708 /* 47532 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18709 /* 47535 */ GIR_RootConstrainSelectedInstOperands,
18710 /* 47536 */ // GIR_Coverage, 2212,
18711 /* 47536 */ GIR_EraseRootFromParent_Done,
18712 /* 47537 */ // Label 1222: @47537
18713 /* 47537 */ GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(47597), // Rule ID 2213 //
18714 /* 47542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18715 /* 47545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18716 /* 47549 */ // MIs[0] Operand 1
18717 /* 47549 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18718 /* 47554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18719 /* 47558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18720 /* 47562 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18721 /* 47562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18722 /* 47565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18723 /* 47569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18724 /* 47574 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18725 /* 47578 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18726 /* 47582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18727 /* 47584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18728 /* 47587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18729 /* 47589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18730 /* 47592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18731 /* 47595 */ GIR_RootConstrainSelectedInstOperands,
18732 /* 47596 */ // GIR_Coverage, 2213,
18733 /* 47596 */ GIR_EraseRootFromParent_Done,
18734 /* 47597 */ // Label 1223: @47597
18735 /* 47597 */ GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(47633), // Rule ID 2214 //
18736 /* 47602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18737 /* 47605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18738 /* 47609 */ // MIs[0] Operand 1
18739 /* 47609 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18740 /* 47614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18741 /* 47618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18742 /* 47622 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18743 /* 47622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18744 /* 47625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18745 /* 47627 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18746 /* 47629 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18747 /* 47631 */ GIR_RootConstrainSelectedInstOperands,
18748 /* 47632 */ // GIR_Coverage, 2214,
18749 /* 47632 */ GIR_EraseRootFromParent_Done,
18750 /* 47633 */ // Label 1224: @47633
18751 /* 47633 */ GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(47669), // Rule ID 2215 //
18752 /* 47638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18753 /* 47641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18754 /* 47645 */ // MIs[0] Operand 1
18755 /* 47645 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18756 /* 47650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18757 /* 47654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18758 /* 47658 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18759 /* 47658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18760 /* 47661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18761 /* 47663 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18762 /* 47665 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18763 /* 47667 */ GIR_RootConstrainSelectedInstOperands,
18764 /* 47668 */ // GIR_Coverage, 2215,
18765 /* 47668 */ GIR_EraseRootFromParent_Done,
18766 /* 47669 */ // Label 1225: @47669
18767 /* 47669 */ GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(47729), // Rule ID 2216 //
18768 /* 47674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18769 /* 47677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18770 /* 47681 */ // MIs[0] Operand 1
18771 /* 47681 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18772 /* 47686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18773 /* 47690 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18774 /* 47694 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18775 /* 47694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18776 /* 47697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18777 /* 47701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18778 /* 47706 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18779 /* 47710 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18780 /* 47714 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18781 /* 47716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18782 /* 47719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18783 /* 47721 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18784 /* 47724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18785 /* 47727 */ GIR_RootConstrainSelectedInstOperands,
18786 /* 47728 */ // GIR_Coverage, 2216,
18787 /* 47728 */ GIR_EraseRootFromParent_Done,
18788 /* 47729 */ // Label 1226: @47729
18789 /* 47729 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(47789), // Rule ID 2217 //
18790 /* 47734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18791 /* 47737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18792 /* 47741 */ // MIs[0] Operand 1
18793 /* 47741 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18794 /* 47746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18795 /* 47750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18796 /* 47754 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18797 /* 47754 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18798 /* 47757 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18799 /* 47761 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18800 /* 47766 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18801 /* 47770 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18802 /* 47774 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18803 /* 47776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18804 /* 47779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18805 /* 47781 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18806 /* 47784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18807 /* 47787 */ GIR_RootConstrainSelectedInstOperands,
18808 /* 47788 */ // GIR_Coverage, 2217,
18809 /* 47788 */ GIR_EraseRootFromParent_Done,
18810 /* 47789 */ // Label 1227: @47789
18811 /* 47789 */ GIM_Reject,
18812 /* 47790 */ // Label 1209: @47790
18813 /* 47790 */ GIM_Reject,
18814 /* 47791 */ // Label 1163: @47791
18815 /* 47791 */ GIM_Reject,
18816 /* 47792 */ // Label 42: @47792
18817 /* 47792 */ GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(49497),
18818 /* 47797 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18819 /* 47800 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1231*/ GIMT_Encode4(48295),
18820 /* 47811 */ /*GILLT_s32*//*Label 1229*/ GIMT_Encode4(47819),
18821 /* 47815 */ /*GILLT_s64*//*Label 1230*/ GIMT_Encode4(48057),
18822 /* 47819 */ // Label 1229: @47819
18823 /* 47819 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(48056),
18824 /* 47824 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18825 /* 47827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
18826 /* 47831 */ GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(47863), // Rule ID 312 //
18827 /* 47836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18828 /* 47839 */ // MIs[0] Operand 1
18829 /* 47839 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18830 /* 47844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18831 /* 47848 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18832 /* 47852 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18833 /* 47852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
18834 /* 47855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18835 /* 47857 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18836 /* 47859 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18837 /* 47861 */ GIR_RootConstrainSelectedInstOperands,
18838 /* 47862 */ // GIR_Coverage, 312,
18839 /* 47862 */ GIR_EraseRootFromParent_Done,
18840 /* 47863 */ // Label 1233: @47863
18841 /* 47863 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(47895), // Rule ID 313 //
18842 /* 47868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18843 /* 47871 */ // MIs[0] Operand 1
18844 /* 47871 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18845 /* 47876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18846 /* 47880 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18847 /* 47884 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18848 /* 47884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
18849 /* 47887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18850 /* 47889 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18851 /* 47891 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18852 /* 47893 */ GIR_RootConstrainSelectedInstOperands,
18853 /* 47894 */ // GIR_Coverage, 313,
18854 /* 47894 */ GIR_EraseRootFromParent_Done,
18855 /* 47895 */ // Label 1234: @47895
18856 /* 47895 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(47927), // Rule ID 314 //
18857 /* 47900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18858 /* 47903 */ // MIs[0] Operand 1
18859 /* 47903 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18860 /* 47908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18861 /* 47912 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18862 /* 47916 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18863 /* 47916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
18864 /* 47919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18865 /* 47921 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18866 /* 47923 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18867 /* 47925 */ GIR_RootConstrainSelectedInstOperands,
18868 /* 47926 */ // GIR_Coverage, 314,
18869 /* 47926 */ GIR_EraseRootFromParent_Done,
18870 /* 47927 */ // Label 1235: @47927
18871 /* 47927 */ GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(47959), // Rule ID 315 //
18872 /* 47932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18873 /* 47935 */ // MIs[0] Operand 1
18874 /* 47935 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18875 /* 47940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18876 /* 47944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18877 /* 47948 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18878 /* 47948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S),
18879 /* 47951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18880 /* 47953 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18881 /* 47955 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18882 /* 47957 */ GIR_RootConstrainSelectedInstOperands,
18883 /* 47958 */ // GIR_Coverage, 315,
18884 /* 47958 */ GIR_EraseRootFromParent_Done,
18885 /* 47959 */ // Label 1236: @47959
18886 /* 47959 */ GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(47991), // Rule ID 316 //
18887 /* 47964 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18888 /* 47967 */ // MIs[0] Operand 1
18889 /* 47967 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18890 /* 47972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18891 /* 47976 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18892 /* 47980 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18893 /* 47980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S),
18894 /* 47983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18895 /* 47985 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18896 /* 47987 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18897 /* 47989 */ GIR_RootConstrainSelectedInstOperands,
18898 /* 47990 */ // GIR_Coverage, 316,
18899 /* 47990 */ GIR_EraseRootFromParent_Done,
18900 /* 47991 */ // Label 1237: @47991
18901 /* 47991 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(48023), // Rule ID 317 //
18902 /* 47996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18903 /* 47999 */ // MIs[0] Operand 1
18904 /* 47999 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18905 /* 48004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18906 /* 48008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18907 /* 48012 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18908 /* 48012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S),
18909 /* 48015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18910 /* 48017 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18911 /* 48019 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18912 /* 48021 */ GIR_RootConstrainSelectedInstOperands,
18913 /* 48022 */ // GIR_Coverage, 317,
18914 /* 48022 */ GIR_EraseRootFromParent_Done,
18915 /* 48023 */ // Label 1238: @48023
18916 /* 48023 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(48055), // Rule ID 318 //
18917 /* 48028 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18918 /* 48031 */ // MIs[0] Operand 1
18919 /* 48031 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18920 /* 48036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18921 /* 48040 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18922 /* 48044 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18923 /* 48044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S),
18924 /* 48047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18925 /* 48049 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18926 /* 48051 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18927 /* 48053 */ GIR_RootConstrainSelectedInstOperands,
18928 /* 48054 */ // GIR_Coverage, 318,
18929 /* 48054 */ GIR_EraseRootFromParent_Done,
18930 /* 48055 */ // Label 1239: @48055
18931 /* 48055 */ GIM_Reject,
18932 /* 48056 */ // Label 1232: @48056
18933 /* 48056 */ GIM_Reject,
18934 /* 48057 */ // Label 1230: @48057
18935 /* 48057 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(48294),
18936 /* 48062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18937 /* 48065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
18938 /* 48069 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(48101), // Rule ID 319 //
18939 /* 48074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18940 /* 48077 */ // MIs[0] Operand 1
18941 /* 48077 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18942 /* 48082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18943 /* 48086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18944 /* 48090 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18945 /* 48090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
18946 /* 48093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18947 /* 48095 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18948 /* 48097 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18949 /* 48099 */ GIR_RootConstrainSelectedInstOperands,
18950 /* 48100 */ // GIR_Coverage, 319,
18951 /* 48100 */ GIR_EraseRootFromParent_Done,
18952 /* 48101 */ // Label 1241: @48101
18953 /* 48101 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(48133), // Rule ID 320 //
18954 /* 48106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18955 /* 48109 */ // MIs[0] Operand 1
18956 /* 48109 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18957 /* 48114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18958 /* 48118 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18959 /* 48122 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18960 /* 48122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
18961 /* 48125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18962 /* 48127 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18963 /* 48129 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18964 /* 48131 */ GIR_RootConstrainSelectedInstOperands,
18965 /* 48132 */ // GIR_Coverage, 320,
18966 /* 48132 */ GIR_EraseRootFromParent_Done,
18967 /* 48133 */ // Label 1242: @48133
18968 /* 48133 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(48165), // Rule ID 321 //
18969 /* 48138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18970 /* 48141 */ // MIs[0] Operand 1
18971 /* 48141 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18972 /* 48146 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18973 /* 48150 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18974 /* 48154 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18975 /* 48154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
18976 /* 48157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18977 /* 48159 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18978 /* 48161 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18979 /* 48163 */ GIR_RootConstrainSelectedInstOperands,
18980 /* 48164 */ // GIR_Coverage, 321,
18981 /* 48164 */ GIR_EraseRootFromParent_Done,
18982 /* 48165 */ // Label 1243: @48165
18983 /* 48165 */ GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(48197), // Rule ID 322 //
18984 /* 48170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
18985 /* 48173 */ // MIs[0] Operand 1
18986 /* 48173 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18987 /* 48178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18988 /* 48182 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18989 /* 48186 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18990 /* 48186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D),
18991 /* 48189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18992 /* 48191 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18993 /* 48193 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18994 /* 48195 */ GIR_RootConstrainSelectedInstOperands,
18995 /* 48196 */ // GIR_Coverage, 322,
18996 /* 48196 */ GIR_EraseRootFromParent_Done,
18997 /* 48197 */ // Label 1244: @48197
18998 /* 48197 */ GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(48229), // Rule ID 323 //
18999 /* 48202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19000 /* 48205 */ // MIs[0] Operand 1
19001 /* 48205 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19002 /* 48210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19003 /* 48214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19004 /* 48218 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19005 /* 48218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D),
19006 /* 48221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19007 /* 48223 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19008 /* 48225 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19009 /* 48227 */ GIR_RootConstrainSelectedInstOperands,
19010 /* 48228 */ // GIR_Coverage, 323,
19011 /* 48228 */ GIR_EraseRootFromParent_Done,
19012 /* 48229 */ // Label 1245: @48229
19013 /* 48229 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(48261), // Rule ID 324 //
19014 /* 48234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19015 /* 48237 */ // MIs[0] Operand 1
19016 /* 48237 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19017 /* 48242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19018 /* 48246 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19019 /* 48250 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19020 /* 48250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D),
19021 /* 48253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19022 /* 48255 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19023 /* 48257 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19024 /* 48259 */ GIR_RootConstrainSelectedInstOperands,
19025 /* 48260 */ // GIR_Coverage, 324,
19026 /* 48260 */ GIR_EraseRootFromParent_Done,
19027 /* 48261 */ // Label 1246: @48261
19028 /* 48261 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(48293), // Rule ID 325 //
19029 /* 48266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19030 /* 48269 */ // MIs[0] Operand 1
19031 /* 48269 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19032 /* 48274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19033 /* 48278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19034 /* 48282 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19035 /* 48282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D),
19036 /* 48285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19037 /* 48287 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19038 /* 48289 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19039 /* 48291 */ GIR_RootConstrainSelectedInstOperands,
19040 /* 48292 */ // GIR_Coverage, 325,
19041 /* 48292 */ GIR_EraseRootFromParent_Done,
19042 /* 48293 */ // Label 1247: @48293
19043 /* 48293 */ GIM_Reject,
19044 /* 48294 */ // Label 1240: @48294
19045 /* 48294 */ GIM_Reject,
19046 /* 48295 */ // Label 1231: @48295
19047 /* 48295 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1250*/ GIMT_Encode4(48790),
19048 /* 48306 */ /*GILLT_s32*//*Label 1248*/ GIMT_Encode4(48314),
19049 /* 48310 */ /*GILLT_s64*//*Label 1249*/ GIMT_Encode4(48552),
19050 /* 48314 */ // Label 1248: @48314
19051 /* 48314 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(48551),
19052 /* 48319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19053 /* 48322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
19054 /* 48326 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(48358), // Rule ID 1193 //
19055 /* 48331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19056 /* 48334 */ // MIs[0] Operand 1
19057 /* 48334 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19058 /* 48339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19059 /* 48343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19060 /* 48347 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19061 /* 48347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
19062 /* 48350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19063 /* 48352 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19064 /* 48354 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19065 /* 48356 */ GIR_RootConstrainSelectedInstOperands,
19066 /* 48357 */ // GIR_Coverage, 1193,
19067 /* 48357 */ GIR_EraseRootFromParent_Done,
19068 /* 48358 */ // Label 1252: @48358
19069 /* 48358 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(48390), // Rule ID 1194 //
19070 /* 48363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19071 /* 48366 */ // MIs[0] Operand 1
19072 /* 48366 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19073 /* 48371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19074 /* 48375 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19075 /* 48379 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19076 /* 48379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
19077 /* 48382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19078 /* 48384 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19079 /* 48386 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19080 /* 48388 */ GIR_RootConstrainSelectedInstOperands,
19081 /* 48389 */ // GIR_Coverage, 1194,
19082 /* 48389 */ GIR_EraseRootFromParent_Done,
19083 /* 48390 */ // Label 1253: @48390
19084 /* 48390 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(48422), // Rule ID 1195 //
19085 /* 48395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19086 /* 48398 */ // MIs[0] Operand 1
19087 /* 48398 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19088 /* 48403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19089 /* 48407 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19090 /* 48411 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19091 /* 48411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
19092 /* 48414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19093 /* 48416 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19094 /* 48418 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19095 /* 48420 */ GIR_RootConstrainSelectedInstOperands,
19096 /* 48421 */ // GIR_Coverage, 1195,
19097 /* 48421 */ GIR_EraseRootFromParent_Done,
19098 /* 48422 */ // Label 1254: @48422
19099 /* 48422 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(48454), // Rule ID 1196 //
19100 /* 48427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19101 /* 48430 */ // MIs[0] Operand 1
19102 /* 48430 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19103 /* 48435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19104 /* 48439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19105 /* 48443 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19106 /* 48443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S_MMR6),
19107 /* 48446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19108 /* 48448 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19109 /* 48450 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19110 /* 48452 */ GIR_RootConstrainSelectedInstOperands,
19111 /* 48453 */ // GIR_Coverage, 1196,
19112 /* 48453 */ GIR_EraseRootFromParent_Done,
19113 /* 48454 */ // Label 1255: @48454
19114 /* 48454 */ GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(48486), // Rule ID 1197 //
19115 /* 48459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19116 /* 48462 */ // MIs[0] Operand 1
19117 /* 48462 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19118 /* 48467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19119 /* 48471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19120 /* 48475 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19121 /* 48475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S_MMR6),
19122 /* 48478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19123 /* 48480 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19124 /* 48482 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19125 /* 48484 */ GIR_RootConstrainSelectedInstOperands,
19126 /* 48485 */ // GIR_Coverage, 1197,
19127 /* 48485 */ GIR_EraseRootFromParent_Done,
19128 /* 48486 */ // Label 1256: @48486
19129 /* 48486 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(48518), // Rule ID 1198 //
19130 /* 48491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19131 /* 48494 */ // MIs[0] Operand 1
19132 /* 48494 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19133 /* 48499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19134 /* 48503 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19135 /* 48507 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19136 /* 48507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S_MMR6),
19137 /* 48510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19138 /* 48512 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19139 /* 48514 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19140 /* 48516 */ GIR_RootConstrainSelectedInstOperands,
19141 /* 48517 */ // GIR_Coverage, 1198,
19142 /* 48517 */ GIR_EraseRootFromParent_Done,
19143 /* 48518 */ // Label 1257: @48518
19144 /* 48518 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(48550), // Rule ID 1199 //
19145 /* 48523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19146 /* 48526 */ // MIs[0] Operand 1
19147 /* 48526 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19148 /* 48531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19149 /* 48535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19150 /* 48539 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19151 /* 48539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S_MMR6),
19152 /* 48542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19153 /* 48544 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19154 /* 48546 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19155 /* 48548 */ GIR_RootConstrainSelectedInstOperands,
19156 /* 48549 */ // GIR_Coverage, 1199,
19157 /* 48549 */ GIR_EraseRootFromParent_Done,
19158 /* 48550 */ // Label 1258: @48550
19159 /* 48550 */ GIM_Reject,
19160 /* 48551 */ // Label 1251: @48551
19161 /* 48551 */ GIM_Reject,
19162 /* 48552 */ // Label 1249: @48552
19163 /* 48552 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(48789),
19164 /* 48557 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19165 /* 48560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
19166 /* 48564 */ GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(48596), // Rule ID 1200 //
19167 /* 48569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19168 /* 48572 */ // MIs[0] Operand 1
19169 /* 48572 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19170 /* 48577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19171 /* 48581 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19172 /* 48585 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19173 /* 48585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
19174 /* 48588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19175 /* 48590 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19176 /* 48592 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19177 /* 48594 */ GIR_RootConstrainSelectedInstOperands,
19178 /* 48595 */ // GIR_Coverage, 1200,
19179 /* 48595 */ GIR_EraseRootFromParent_Done,
19180 /* 48596 */ // Label 1260: @48596
19181 /* 48596 */ GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(48628), // Rule ID 1201 //
19182 /* 48601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19183 /* 48604 */ // MIs[0] Operand 1
19184 /* 48604 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19185 /* 48609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19186 /* 48613 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19187 /* 48617 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19188 /* 48617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
19189 /* 48620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19190 /* 48622 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19191 /* 48624 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19192 /* 48626 */ GIR_RootConstrainSelectedInstOperands,
19193 /* 48627 */ // GIR_Coverage, 1201,
19194 /* 48627 */ GIR_EraseRootFromParent_Done,
19195 /* 48628 */ // Label 1261: @48628
19196 /* 48628 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(48660), // Rule ID 1202 //
19197 /* 48633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19198 /* 48636 */ // MIs[0] Operand 1
19199 /* 48636 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19200 /* 48641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19201 /* 48645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19202 /* 48649 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19203 /* 48649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
19204 /* 48652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19205 /* 48654 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19206 /* 48656 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19207 /* 48658 */ GIR_RootConstrainSelectedInstOperands,
19208 /* 48659 */ // GIR_Coverage, 1202,
19209 /* 48659 */ GIR_EraseRootFromParent_Done,
19210 /* 48660 */ // Label 1262: @48660
19211 /* 48660 */ GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(48692), // Rule ID 1203 //
19212 /* 48665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19213 /* 48668 */ // MIs[0] Operand 1
19214 /* 48668 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19215 /* 48673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19216 /* 48677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19217 /* 48681 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19218 /* 48681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D_MMR6),
19219 /* 48684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19220 /* 48686 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19221 /* 48688 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19222 /* 48690 */ GIR_RootConstrainSelectedInstOperands,
19223 /* 48691 */ // GIR_Coverage, 1203,
19224 /* 48691 */ GIR_EraseRootFromParent_Done,
19225 /* 48692 */ // Label 1263: @48692
19226 /* 48692 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(48724), // Rule ID 1204 //
19227 /* 48697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19228 /* 48700 */ // MIs[0] Operand 1
19229 /* 48700 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19230 /* 48705 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19231 /* 48709 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19232 /* 48713 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19233 /* 48713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D_MMR6),
19234 /* 48716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19235 /* 48718 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19236 /* 48720 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19237 /* 48722 */ GIR_RootConstrainSelectedInstOperands,
19238 /* 48723 */ // GIR_Coverage, 1204,
19239 /* 48723 */ GIR_EraseRootFromParent_Done,
19240 /* 48724 */ // Label 1264: @48724
19241 /* 48724 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(48756), // Rule ID 1205 //
19242 /* 48729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19243 /* 48732 */ // MIs[0] Operand 1
19244 /* 48732 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19245 /* 48737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19246 /* 48741 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19247 /* 48745 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19248 /* 48745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D_MMR6),
19249 /* 48748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19250 /* 48750 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19251 /* 48752 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19252 /* 48754 */ GIR_RootConstrainSelectedInstOperands,
19253 /* 48755 */ // GIR_Coverage, 1205,
19254 /* 48755 */ GIR_EraseRootFromParent_Done,
19255 /* 48756 */ // Label 1265: @48756
19256 /* 48756 */ GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(48788), // Rule ID 1206 //
19257 /* 48761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19258 /* 48764 */ // MIs[0] Operand 1
19259 /* 48764 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19260 /* 48769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19261 /* 48773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19262 /* 48777 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19263 /* 48777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D_MMR6),
19264 /* 48780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19265 /* 48782 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19266 /* 48784 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19267 /* 48786 */ GIR_RootConstrainSelectedInstOperands,
19268 /* 48787 */ // GIR_Coverage, 1206,
19269 /* 48787 */ GIR_EraseRootFromParent_Done,
19270 /* 48788 */ // Label 1266: @48788
19271 /* 48788 */ GIM_Reject,
19272 /* 48789 */ // Label 1259: @48789
19273 /* 48789 */ GIM_Reject,
19274 /* 48790 */ // Label 1250: @48790
19275 /* 48790 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1269*/ GIMT_Encode4(49143),
19276 /* 48801 */ /*GILLT_s32*//*Label 1267*/ GIMT_Encode4(48809),
19277 /* 48805 */ /*GILLT_s64*//*Label 1268*/ GIMT_Encode4(48976),
19278 /* 48809 */ // Label 1267: @48809
19279 /* 48809 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(48975),
19280 /* 48814 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19281 /* 48817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19282 /* 48821 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(48872), // Rule ID 1755 //
19283 /* 48826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
19284 /* 48829 */ // MIs[0] Operand 1
19285 /* 48829 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
19286 /* 48834 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UEQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
19287 /* 48834 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19288 /* 48837 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
19289 /* 48841 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19290 /* 48846 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19291 /* 48850 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19292 /* 48854 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19293 /* 48856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
19294 /* 48859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19295 /* 48861 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19296 /* 48864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19297 /* 48870 */ GIR_RootConstrainSelectedInstOperands,
19298 /* 48871 */ // GIR_Coverage, 1755,
19299 /* 48871 */ GIR_EraseRootFromParent_Done,
19300 /* 48872 */ // Label 1271: @48872
19301 /* 48872 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(48923), // Rule ID 1756 //
19302 /* 48877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
19303 /* 48880 */ // MIs[0] Operand 1
19304 /* 48880 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
19305 /* 48885 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UN_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
19306 /* 48885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19307 /* 48888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
19308 /* 48892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19309 /* 48897 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19310 /* 48901 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19311 /* 48905 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19312 /* 48907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
19313 /* 48910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19314 /* 48912 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19315 /* 48915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19316 /* 48921 */ GIR_RootConstrainSelectedInstOperands,
19317 /* 48922 */ // GIR_Coverage, 1756,
19318 /* 48922 */ GIR_EraseRootFromParent_Done,
19319 /* 48923 */ // Label 1272: @48923
19320 /* 48923 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(48974), // Rule ID 1757 //
19321 /* 48928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
19322 /* 48931 */ // MIs[0] Operand 1
19323 /* 48931 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
19324 /* 48936 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
19325 /* 48936 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19326 /* 48939 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
19327 /* 48943 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19328 /* 48948 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19329 /* 48952 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19330 /* 48956 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19331 /* 48958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
19332 /* 48961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19333 /* 48963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19334 /* 48966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19335 /* 48972 */ GIR_RootConstrainSelectedInstOperands,
19336 /* 48973 */ // GIR_Coverage, 1757,
19337 /* 48973 */ GIR_EraseRootFromParent_Done,
19338 /* 48974 */ // Label 1273: @48974
19339 /* 48974 */ GIM_Reject,
19340 /* 48975 */ // Label 1270: @48975
19341 /* 48975 */ GIM_Reject,
19342 /* 48976 */ // Label 1268: @48976
19343 /* 48976 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(49142),
19344 /* 48981 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19345 /* 48984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19346 /* 48988 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(49039), // Rule ID 1764 //
19347 /* 48993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
19348 /* 48996 */ // MIs[0] Operand 1
19349 /* 48996 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
19350 /* 49001 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UEQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
19351 /* 49001 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19352 /* 49004 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
19353 /* 49008 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19354 /* 49013 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19355 /* 49017 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19356 /* 49021 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19357 /* 49023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
19358 /* 49026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19359 /* 49028 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19360 /* 49031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19361 /* 49037 */ GIR_RootConstrainSelectedInstOperands,
19362 /* 49038 */ // GIR_Coverage, 1764,
19363 /* 49038 */ GIR_EraseRootFromParent_Done,
19364 /* 49039 */ // Label 1275: @49039
19365 /* 49039 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(49090), // Rule ID 1765 //
19366 /* 49044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
19367 /* 49047 */ // MIs[0] Operand 1
19368 /* 49047 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
19369 /* 49052 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UN_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
19370 /* 49052 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19371 /* 49055 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
19372 /* 49059 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19373 /* 49064 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19374 /* 49068 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19375 /* 49072 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19376 /* 49074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
19377 /* 49077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19378 /* 49079 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19379 /* 49082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19380 /* 49088 */ GIR_RootConstrainSelectedInstOperands,
19381 /* 49089 */ // GIR_Coverage, 1765,
19382 /* 49089 */ GIR_EraseRootFromParent_Done,
19383 /* 49090 */ // Label 1276: @49090
19384 /* 49090 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(49141), // Rule ID 1766 //
19385 /* 49095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
19386 /* 49098 */ // MIs[0] Operand 1
19387 /* 49098 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
19388 /* 49103 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
19389 /* 49103 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19390 /* 49106 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
19391 /* 49110 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19392 /* 49115 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19393 /* 49119 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19394 /* 49123 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19395 /* 49125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
19396 /* 49128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19397 /* 49130 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19398 /* 49133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19399 /* 49139 */ GIR_RootConstrainSelectedInstOperands,
19400 /* 49140 */ // GIR_Coverage, 1766,
19401 /* 49140 */ GIR_EraseRootFromParent_Done,
19402 /* 49141 */ // Label 1277: @49141
19403 /* 49141 */ GIM_Reject,
19404 /* 49142 */ // Label 1274: @49142
19405 /* 49142 */ GIM_Reject,
19406 /* 49143 */ // Label 1269: @49143
19407 /* 49143 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1280*/ GIMT_Encode4(49496),
19408 /* 49154 */ /*GILLT_s32*//*Label 1278*/ GIMT_Encode4(49162),
19409 /* 49158 */ /*GILLT_s64*//*Label 1279*/ GIMT_Encode4(49329),
19410 /* 49162 */ // Label 1278: @49162
19411 /* 49162 */ GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(49328),
19412 /* 49167 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19413 /* 49170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19414 /* 49174 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(49225), // Rule ID 2309 //
19415 /* 49179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
19416 /* 49182 */ // MIs[0] Operand 1
19417 /* 49182 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
19418 /* 49187 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UEQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
19419 /* 49187 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19420 /* 49190 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
19421 /* 49194 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19422 /* 49199 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19423 /* 49203 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19424 /* 49207 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19425 /* 49209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
19426 /* 49212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19427 /* 49214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19428 /* 49217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19429 /* 49223 */ GIR_RootConstrainSelectedInstOperands,
19430 /* 49224 */ // GIR_Coverage, 2309,
19431 /* 49224 */ GIR_EraseRootFromParent_Done,
19432 /* 49225 */ // Label 1282: @49225
19433 /* 49225 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(49276), // Rule ID 2310 //
19434 /* 49230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
19435 /* 49233 */ // MIs[0] Operand 1
19436 /* 49233 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
19437 /* 49238 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UN_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
19438 /* 49238 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19439 /* 49241 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
19440 /* 49245 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19441 /* 49250 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19442 /* 49254 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19443 /* 49258 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19444 /* 49260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
19445 /* 49263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19446 /* 49265 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19447 /* 49268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19448 /* 49274 */ GIR_RootConstrainSelectedInstOperands,
19449 /* 49275 */ // GIR_Coverage, 2310,
19450 /* 49275 */ GIR_EraseRootFromParent_Done,
19451 /* 49276 */ // Label 1283: @49276
19452 /* 49276 */ GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(49327), // Rule ID 2311 //
19453 /* 49281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
19454 /* 49284 */ // MIs[0] Operand 1
19455 /* 49284 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
19456 /* 49289 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
19457 /* 49289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19458 /* 49292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
19459 /* 49296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19460 /* 49301 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19461 /* 49305 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19462 /* 49309 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19463 /* 49311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
19464 /* 49314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19465 /* 49316 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19466 /* 49319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19467 /* 49325 */ GIR_RootConstrainSelectedInstOperands,
19468 /* 49326 */ // GIR_Coverage, 2311,
19469 /* 49326 */ GIR_EraseRootFromParent_Done,
19470 /* 49327 */ // Label 1284: @49327
19471 /* 49327 */ GIM_Reject,
19472 /* 49328 */ // Label 1281: @49328
19473 /* 49328 */ GIM_Reject,
19474 /* 49329 */ // Label 1279: @49329
19475 /* 49329 */ GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(49495),
19476 /* 49334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19477 /* 49337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19478 /* 49341 */ GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(49392), // Rule ID 2318 //
19479 /* 49346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
19480 /* 49349 */ // MIs[0] Operand 1
19481 /* 49349 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
19482 /* 49354 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UEQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
19483 /* 49354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19484 /* 49357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
19485 /* 49361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19486 /* 49366 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19487 /* 49370 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19488 /* 49374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19489 /* 49376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
19490 /* 49379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19491 /* 49381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19492 /* 49384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19493 /* 49390 */ GIR_RootConstrainSelectedInstOperands,
19494 /* 49391 */ // GIR_Coverage, 2318,
19495 /* 49391 */ GIR_EraseRootFromParent_Done,
19496 /* 49392 */ // Label 1286: @49392
19497 /* 49392 */ GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(49443), // Rule ID 2319 //
19498 /* 49397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
19499 /* 49400 */ // MIs[0] Operand 1
19500 /* 49400 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
19501 /* 49405 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UN_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
19502 /* 49405 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19503 /* 49408 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
19504 /* 49412 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19505 /* 49417 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19506 /* 49421 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19507 /* 49425 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19508 /* 49427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
19509 /* 49430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19510 /* 49432 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19511 /* 49435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19512 /* 49441 */ GIR_RootConstrainSelectedInstOperands,
19513 /* 49442 */ // GIR_Coverage, 2319,
19514 /* 49442 */ GIR_EraseRootFromParent_Done,
19515 /* 49443 */ // Label 1287: @49443
19516 /* 49443 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(49494), // Rule ID 2320 //
19517 /* 49448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
19518 /* 49451 */ // MIs[0] Operand 1
19519 /* 49451 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
19520 /* 49456 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
19521 /* 49456 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19522 /* 49459 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
19523 /* 49463 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19524 /* 49468 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19525 /* 49472 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19526 /* 49476 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19527 /* 49478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
19528 /* 49481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19529 /* 49483 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19530 /* 49486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19531 /* 49492 */ GIR_RootConstrainSelectedInstOperands,
19532 /* 49493 */ // GIR_Coverage, 2320,
19533 /* 49493 */ GIR_EraseRootFromParent_Done,
19534 /* 49494 */ // Label 1288: @49494
19535 /* 49494 */ GIM_Reject,
19536 /* 49495 */ // Label 1285: @49495
19537 /* 49495 */ GIM_Reject,
19538 /* 49496 */ // Label 1280: @49496
19539 /* 49496 */ GIM_Reject,
19540 /* 49497 */ // Label 1228: @49497
19541 /* 49497 */ GIM_Reject,
19542 /* 49498 */ // Label 43: @49498
19543 /* 49498 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1295*/ GIMT_Encode4(61535),
19544 /* 49509 */ /*GILLT_s32*//*Label 1289*/ GIMT_Encode4(49541),
19545 /* 49513 */ /*GILLT_s64*//*Label 1290*/ GIMT_Encode4(56218), GIMT_Encode4(0),
19546 /* 49521 */ /*GILLT_v2s64*//*Label 1291*/ GIMT_Encode4(61245), GIMT_Encode4(0),
19547 /* 49529 */ /*GILLT_v4s32*//*Label 1292*/ GIMT_Encode4(61319),
19548 /* 49533 */ /*GILLT_v8s16*//*Label 1293*/ GIMT_Encode4(61393),
19549 /* 49537 */ /*GILLT_v16s8*//*Label 1294*/ GIMT_Encode4(61440),
19550 /* 49541 */ // Label 1289: @49541
19551 /* 49541 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(49617), // Rule ID 1643 //
19552 /* 49546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19553 /* 49549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19554 /* 49552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19555 /* 49555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19556 /* 49558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19557 /* 49562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19558 /* 49566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19559 /* 49570 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19560 /* 49574 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19561 /* 49578 */ // MIs[1] Operand 1
19562 /* 49578 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19563 /* 49583 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19564 /* 49588 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19565 /* 49592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19566 /* 49596 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19567 /* 49600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19568 /* 49602 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19569 /* 49602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19570 /* 49605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19571 /* 49607 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19572 /* 49609 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19573 /* 49613 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19574 /* 49615 */ GIR_RootConstrainSelectedInstOperands,
19575 /* 49616 */ // GIR_Coverage, 1643,
19576 /* 49616 */ GIR_EraseRootFromParent_Done,
19577 /* 49617 */ // Label 1296: @49617
19578 /* 49617 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(49693), // Rule ID 1647 //
19579 /* 49622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19580 /* 49625 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19581 /* 49628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19582 /* 49631 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19583 /* 49634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19584 /* 49638 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19585 /* 49642 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19586 /* 49646 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19587 /* 49650 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19588 /* 49654 */ // MIs[1] Operand 1
19589 /* 49654 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19590 /* 49659 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19591 /* 49664 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19592 /* 49668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19593 /* 49672 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19594 /* 49676 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19595 /* 49678 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19596 /* 49678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
19597 /* 49681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19598 /* 49683 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19599 /* 49685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19600 /* 49689 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19601 /* 49691 */ GIR_RootConstrainSelectedInstOperands,
19602 /* 49692 */ // GIR_Coverage, 1647,
19603 /* 49692 */ GIR_EraseRootFromParent_Done,
19604 /* 49693 */ // Label 1297: @49693
19605 /* 49693 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(49769), // Rule ID 1675 //
19606 /* 49698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19607 /* 49701 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19608 /* 49704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19609 /* 49707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19610 /* 49710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19611 /* 49714 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19612 /* 49718 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19613 /* 49722 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19614 /* 49726 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19615 /* 49730 */ // MIs[1] Operand 1
19616 /* 49730 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19617 /* 49735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19618 /* 49740 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19619 /* 49744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19620 /* 49748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19621 /* 49752 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19622 /* 49754 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
19623 /* 49754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
19624 /* 49757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19625 /* 49759 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19626 /* 49761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19627 /* 49765 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19628 /* 49767 */ GIR_RootConstrainSelectedInstOperands,
19629 /* 49768 */ // GIR_Coverage, 1675,
19630 /* 49768 */ GIR_EraseRootFromParent_Done,
19631 /* 49769 */ // Label 1298: @49769
19632 /* 49769 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(49845), // Rule ID 1686 //
19633 /* 49774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19634 /* 49777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19635 /* 49780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19636 /* 49783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19637 /* 49786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19638 /* 49790 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19639 /* 49794 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19640 /* 49798 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19641 /* 49802 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19642 /* 49806 */ // MIs[1] Operand 1
19643 /* 49806 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19644 /* 49811 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19645 /* 49816 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19646 /* 49820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19647 /* 49824 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19648 /* 49828 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19649 /* 49830 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
19650 /* 49830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
19651 /* 49833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19652 /* 49835 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19653 /* 49837 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19654 /* 49841 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19655 /* 49843 */ GIR_RootConstrainSelectedInstOperands,
19656 /* 49844 */ // GIR_Coverage, 1686,
19657 /* 49844 */ GIR_EraseRootFromParent_Done,
19658 /* 49845 */ // Label 1299: @49845
19659 /* 49845 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(49921), // Rule ID 1699 //
19660 /* 49850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19661 /* 49853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19662 /* 49856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19663 /* 49859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19664 /* 49862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19665 /* 49866 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19666 /* 49870 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19667 /* 49874 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19668 /* 49878 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19669 /* 49882 */ // MIs[1] Operand 1
19670 /* 49882 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19671 /* 49887 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19672 /* 49892 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19673 /* 49896 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19674 /* 49900 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19675 /* 49904 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19676 /* 49906 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19677 /* 49906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19678 /* 49909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19679 /* 49911 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19680 /* 49913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19681 /* 49917 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19682 /* 49919 */ GIR_RootConstrainSelectedInstOperands,
19683 /* 49920 */ // GIR_Coverage, 1699,
19684 /* 49920 */ GIR_EraseRootFromParent_Done,
19685 /* 49921 */ // Label 1300: @49921
19686 /* 49921 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(49997), // Rule ID 1702 //
19687 /* 49926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19688 /* 49929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19689 /* 49932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19690 /* 49935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19691 /* 49938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19692 /* 49942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19693 /* 49946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19694 /* 49950 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19695 /* 49954 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19696 /* 49958 */ // MIs[1] Operand 1
19697 /* 49958 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19698 /* 49963 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19699 /* 49968 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19700 /* 49972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19701 /* 49976 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19702 /* 49980 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19703 /* 49982 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19704 /* 49982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
19705 /* 49985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19706 /* 49987 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19707 /* 49989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19708 /* 49993 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19709 /* 49995 */ GIR_RootConstrainSelectedInstOperands,
19710 /* 49996 */ // GIR_Coverage, 1702,
19711 /* 49996 */ GIR_EraseRootFromParent_Done,
19712 /* 49997 */ // Label 1301: @49997
19713 /* 49997 */ GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(50073), // Rule ID 1712 //
19714 /* 50002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19715 /* 50005 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19716 /* 50008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19717 /* 50011 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19718 /* 50014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19719 /* 50018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19720 /* 50022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19721 /* 50026 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19722 /* 50030 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19723 /* 50034 */ // MIs[1] Operand 1
19724 /* 50034 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19725 /* 50039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19726 /* 50044 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19727 /* 50048 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19728 /* 50052 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19729 /* 50056 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19730 /* 50058 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
19731 /* 50058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
19732 /* 50061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19733 /* 50063 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19734 /* 50065 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19735 /* 50069 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19736 /* 50071 */ GIR_RootConstrainSelectedInstOperands,
19737 /* 50072 */ // GIR_Coverage, 1712,
19738 /* 50072 */ GIR_EraseRootFromParent_Done,
19739 /* 50073 */ // Label 1302: @50073
19740 /* 50073 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(50149), // Rule ID 1715 //
19741 /* 50078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19742 /* 50081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19743 /* 50084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19744 /* 50087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19745 /* 50090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19746 /* 50094 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19747 /* 50098 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19748 /* 50102 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19749 /* 50106 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19750 /* 50110 */ // MIs[1] Operand 1
19751 /* 50110 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19752 /* 50115 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19753 /* 50120 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19754 /* 50124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19755 /* 50128 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19756 /* 50132 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19757 /* 50134 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
19758 /* 50134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
19759 /* 50137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19760 /* 50139 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19761 /* 50141 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19762 /* 50145 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19763 /* 50147 */ GIR_RootConstrainSelectedInstOperands,
19764 /* 50148 */ // GIR_Coverage, 1715,
19765 /* 50148 */ GIR_EraseRootFromParent_Done,
19766 /* 50149 */ // Label 1303: @50149
19767 /* 50149 */ GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(50225), // Rule ID 1880 //
19768 /* 50154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19769 /* 50157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19770 /* 50160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19771 /* 50163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19772 /* 50166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19773 /* 50170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19774 /* 50174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19775 /* 50178 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19776 /* 50182 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19777 /* 50186 */ // MIs[1] Operand 1
19778 /* 50186 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19779 /* 50191 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19780 /* 50196 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19781 /* 50200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19782 /* 50204 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19783 /* 50208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19784 /* 50210 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
19785 /* 50210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBeqZ),
19786 /* 50213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19787 /* 50215 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19788 /* 50217 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19789 /* 50219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19790 /* 50223 */ GIR_RootConstrainSelectedInstOperands,
19791 /* 50224 */ // GIR_Coverage, 1880,
19792 /* 50224 */ GIR_EraseRootFromParent_Done,
19793 /* 50225 */ // Label 1304: @50225
19794 /* 50225 */ GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(50301), // Rule ID 1883 //
19795 /* 50230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19796 /* 50233 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19797 /* 50236 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19798 /* 50239 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19799 /* 50242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19800 /* 50246 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19801 /* 50250 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19802 /* 50254 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19803 /* 50258 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19804 /* 50262 */ // MIs[1] Operand 1
19805 /* 50262 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19806 /* 50267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19807 /* 50272 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19808 /* 50276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19809 /* 50280 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19810 /* 50284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19811 /* 50286 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
19812 /* 50286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
19813 /* 50289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19814 /* 50291 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19815 /* 50293 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19816 /* 50295 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19817 /* 50299 */ GIR_RootConstrainSelectedInstOperands,
19818 /* 50300 */ // GIR_Coverage, 1883,
19819 /* 50300 */ GIR_EraseRootFromParent_Done,
19820 /* 50301 */ // Label 1305: @50301
19821 /* 50301 */ GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(50377), // Rule ID 2229 //
19822 /* 50306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19823 /* 50309 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19824 /* 50312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19825 /* 50315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19826 /* 50318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19827 /* 50322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19828 /* 50326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19829 /* 50330 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19830 /* 50334 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19831 /* 50338 */ // MIs[1] Operand 1
19832 /* 50338 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19833 /* 50343 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19834 /* 50348 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19835 /* 50352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19836 /* 50356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19837 /* 50360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19838 /* 50362 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19839 /* 50362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19840 /* 50365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19841 /* 50367 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19842 /* 50369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19843 /* 50373 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19844 /* 50375 */ GIR_RootConstrainSelectedInstOperands,
19845 /* 50376 */ // GIR_Coverage, 2229,
19846 /* 50376 */ GIR_EraseRootFromParent_Done,
19847 /* 50377 */ // Label 1306: @50377
19848 /* 50377 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(50453), // Rule ID 2233 //
19849 /* 50382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
19850 /* 50385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19851 /* 50388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19852 /* 50391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19853 /* 50394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19854 /* 50398 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19855 /* 50402 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19856 /* 50406 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19857 /* 50410 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19858 /* 50414 */ // MIs[1] Operand 1
19859 /* 50414 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19860 /* 50419 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19861 /* 50424 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19862 /* 50428 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19863 /* 50432 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19864 /* 50436 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19865 /* 50438 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19866 /* 50438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
19867 /* 50441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19868 /* 50443 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19869 /* 50445 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19870 /* 50449 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19871 /* 50451 */ GIR_RootConstrainSelectedInstOperands,
19872 /* 50452 */ // GIR_Coverage, 2233,
19873 /* 50452 */ GIR_EraseRootFromParent_Done,
19874 /* 50453 */ // Label 1307: @50453
19875 /* 50453 */ GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(50529), // Rule ID 2243 //
19876 /* 50458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19877 /* 50461 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19878 /* 50464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19879 /* 50467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19880 /* 50470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19881 /* 50474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19882 /* 50478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19883 /* 50482 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19884 /* 50486 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19885 /* 50490 */ // MIs[1] Operand 1
19886 /* 50490 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19887 /* 50495 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19888 /* 50500 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19889 /* 50504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19890 /* 50508 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19891 /* 50512 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19892 /* 50514 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19893 /* 50514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19894 /* 50517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19895 /* 50519 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19896 /* 50521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19897 /* 50525 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19898 /* 50527 */ GIR_RootConstrainSelectedInstOperands,
19899 /* 50528 */ // GIR_Coverage, 2243,
19900 /* 50528 */ GIR_EraseRootFromParent_Done,
19901 /* 50529 */ // Label 1308: @50529
19902 /* 50529 */ GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(50605), // Rule ID 2247 //
19903 /* 50534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19904 /* 50537 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19905 /* 50540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19906 /* 50543 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19907 /* 50546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19908 /* 50550 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19909 /* 50554 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19910 /* 50558 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19911 /* 50562 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19912 /* 50566 */ // MIs[1] Operand 1
19913 /* 50566 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19914 /* 50571 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19915 /* 50576 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19916 /* 50580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19917 /* 50584 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19918 /* 50588 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19919 /* 50590 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19920 /* 50590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
19921 /* 50593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19922 /* 50595 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19923 /* 50597 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19924 /* 50601 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19925 /* 50603 */ GIR_RootConstrainSelectedInstOperands,
19926 /* 50604 */ // GIR_Coverage, 2247,
19927 /* 50604 */ GIR_EraseRootFromParent_Done,
19928 /* 50605 */ // Label 1309: @50605
19929 /* 50605 */ GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(50681), // Rule ID 2277 //
19930 /* 50610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19931 /* 50613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19932 /* 50616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19933 /* 50619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19934 /* 50622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19935 /* 50626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19936 /* 50630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19937 /* 50634 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19938 /* 50638 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19939 /* 50642 */ // MIs[1] Operand 1
19940 /* 50642 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19941 /* 50647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19942 /* 50652 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19943 /* 50656 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19944 /* 50660 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19945 /* 50664 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19946 /* 50666 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19947 /* 50666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
19948 /* 50669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19949 /* 50671 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19950 /* 50673 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19951 /* 50677 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19952 /* 50679 */ GIR_RootConstrainSelectedInstOperands,
19953 /* 50680 */ // GIR_Coverage, 2277,
19954 /* 50680 */ GIR_EraseRootFromParent_Done,
19955 /* 50681 */ // Label 1310: @50681
19956 /* 50681 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(50757), // Rule ID 2280 //
19957 /* 50686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19958 /* 50689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19959 /* 50692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19960 /* 50695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19961 /* 50698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19962 /* 50702 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19963 /* 50706 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19964 /* 50710 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19965 /* 50714 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19966 /* 50718 */ // MIs[1] Operand 1
19967 /* 50718 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19968 /* 50723 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19969 /* 50728 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19970 /* 50732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19971 /* 50736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19972 /* 50740 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19973 /* 50742 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19974 /* 50742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
19975 /* 50745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19976 /* 50747 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19977 /* 50749 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19978 /* 50753 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19979 /* 50755 */ GIR_RootConstrainSelectedInstOperands,
19980 /* 50756 */ // GIR_Coverage, 2280,
19981 /* 50756 */ GIR_EraseRootFromParent_Done,
19982 /* 50757 */ // Label 1311: @50757
19983 /* 50757 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(50855), // Rule ID 1634 //
19984 /* 50762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19985 /* 50765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19986 /* 50768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19987 /* 50771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19988 /* 50774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19989 /* 50778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19990 /* 50782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19991 /* 50786 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19992 /* 50790 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19993 /* 50794 */ // MIs[1] Operand 1
19994 /* 50794 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19995 /* 50799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19996 /* 50804 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19997 /* 50809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19998 /* 50813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19999 /* 50817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20000 /* 50819 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20001 /* 50819 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20002 /* 50822 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20003 /* 50826 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20004 /* 50831 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20005 /* 50835 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20006 /* 50839 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20007 /* 50841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20008 /* 50844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20009 /* 50846 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20010 /* 50848 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20011 /* 50851 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20012 /* 50853 */ GIR_RootConstrainSelectedInstOperands,
20013 /* 50854 */ // GIR_Coverage, 1634,
20014 /* 50854 */ GIR_EraseRootFromParent_Done,
20015 /* 50855 */ // Label 1312: @50855
20016 /* 50855 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(50953), // Rule ID 1635 //
20017 /* 50860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20018 /* 50863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20019 /* 50866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20020 /* 50869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20021 /* 50872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20022 /* 50876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20023 /* 50880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20024 /* 50884 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20025 /* 50888 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20026 /* 50892 */ // MIs[1] Operand 1
20027 /* 50892 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20028 /* 50897 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20029 /* 50902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20030 /* 50907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20031 /* 50911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20032 /* 50915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20033 /* 50917 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20034 /* 50917 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20035 /* 50920 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20036 /* 50924 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20037 /* 50929 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20038 /* 50933 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20039 /* 50937 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20040 /* 50939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20041 /* 50942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20042 /* 50944 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20043 /* 50946 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20044 /* 50949 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20045 /* 50951 */ GIR_RootConstrainSelectedInstOperands,
20046 /* 50952 */ // GIR_Coverage, 1635,
20047 /* 50952 */ GIR_EraseRootFromParent_Done,
20048 /* 50953 */ // Label 1313: @50953
20049 /* 50953 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(51051), // Rule ID 1638 //
20050 /* 50958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20051 /* 50961 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20052 /* 50964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20053 /* 50967 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20054 /* 50970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20055 /* 50974 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20056 /* 50978 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20057 /* 50982 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20058 /* 50986 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20059 /* 50990 */ // MIs[1] Operand 1
20060 /* 50990 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20061 /* 50995 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20062 /* 51000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20063 /* 51005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20064 /* 51009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20065 /* 51013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20066 /* 51015 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20067 /* 51015 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20068 /* 51018 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20069 /* 51022 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20070 /* 51027 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20071 /* 51031 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20072 /* 51035 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20073 /* 51037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20074 /* 51040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20075 /* 51042 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20076 /* 51044 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20077 /* 51047 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20078 /* 51049 */ GIR_RootConstrainSelectedInstOperands,
20079 /* 51050 */ // GIR_Coverage, 1638,
20080 /* 51050 */ GIR_EraseRootFromParent_Done,
20081 /* 51051 */ // Label 1314: @51051
20082 /* 51051 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(51149), // Rule ID 1639 //
20083 /* 51056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20084 /* 51059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20085 /* 51062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20086 /* 51065 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20087 /* 51068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20088 /* 51072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20089 /* 51076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20090 /* 51080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20091 /* 51084 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20092 /* 51088 */ // MIs[1] Operand 1
20093 /* 51088 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20094 /* 51093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20095 /* 51098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20096 /* 51103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20097 /* 51107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20098 /* 51111 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20099 /* 51113 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20100 /* 51113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20101 /* 51116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20102 /* 51120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20103 /* 51125 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20104 /* 51129 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20105 /* 51133 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20106 /* 51135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20107 /* 51138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20108 /* 51140 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20109 /* 51142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20110 /* 51145 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20111 /* 51147 */ GIR_RootConstrainSelectedInstOperands,
20112 /* 51148 */ // GIR_Coverage, 1639,
20113 /* 51148 */ GIR_EraseRootFromParent_Done,
20114 /* 51149 */ // Label 1315: @51149
20115 /* 51149 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(51247), // Rule ID 1642 //
20116 /* 51154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20117 /* 51157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20118 /* 51160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20119 /* 51163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20120 /* 51166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20121 /* 51170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20122 /* 51174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20123 /* 51178 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20124 /* 51182 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20125 /* 51186 */ // MIs[1] Operand 1
20126 /* 51186 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20127 /* 51191 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20128 /* 51196 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20129 /* 51201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20130 /* 51205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20131 /* 51209 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20132 /* 51211 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20133 /* 51211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20134 /* 51214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20135 /* 51218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20136 /* 51223 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20137 /* 51227 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20138 /* 51231 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20139 /* 51233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20140 /* 51236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20141 /* 51238 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20142 /* 51240 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20143 /* 51243 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20144 /* 51245 */ GIR_RootConstrainSelectedInstOperands,
20145 /* 51246 */ // GIR_Coverage, 1642,
20146 /* 51246 */ GIR_EraseRootFromParent_Done,
20147 /* 51247 */ // Label 1316: @51247
20148 /* 51247 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(51345), // Rule ID 1645 //
20149 /* 51252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20150 /* 51255 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20151 /* 51258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20152 /* 51261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20153 /* 51264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20154 /* 51268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20155 /* 51272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20156 /* 51276 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20157 /* 51280 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20158 /* 51284 */ // MIs[1] Operand 1
20159 /* 51284 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20160 /* 51289 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20161 /* 51294 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20162 /* 51299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20163 /* 51303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20164 /* 51307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20165 /* 51309 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20166 /* 51309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20167 /* 51312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20168 /* 51316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20169 /* 51321 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20170 /* 51325 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20171 /* 51329 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20172 /* 51331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
20173 /* 51334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20174 /* 51336 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20175 /* 51338 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20176 /* 51341 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20177 /* 51343 */ GIR_RootConstrainSelectedInstOperands,
20178 /* 51344 */ // GIR_Coverage, 1645,
20179 /* 51344 */ GIR_EraseRootFromParent_Done,
20180 /* 51345 */ // Label 1317: @51345
20181 /* 51345 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(51443), // Rule ID 1656 //
20182 /* 51350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20183 /* 51353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20184 /* 51356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20185 /* 51359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20186 /* 51362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20187 /* 51366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20188 /* 51370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20189 /* 51374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20190 /* 51378 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20191 /* 51382 */ // MIs[1] Operand 1
20192 /* 51382 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20193 /* 51387 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20194 /* 51392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20195 /* 51397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20196 /* 51401 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20197 /* 51405 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20198 /* 51407 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20199 /* 51407 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20200 /* 51410 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20201 /* 51414 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20202 /* 51419 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20203 /* 51423 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20204 /* 51427 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20205 /* 51429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20206 /* 51432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20207 /* 51434 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20208 /* 51436 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20209 /* 51439 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20210 /* 51441 */ GIR_RootConstrainSelectedInstOperands,
20211 /* 51442 */ // GIR_Coverage, 1656,
20212 /* 51442 */ GIR_EraseRootFromParent_Done,
20213 /* 51443 */ // Label 1318: @51443
20214 /* 51443 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(51541), // Rule ID 1657 //
20215 /* 51448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20216 /* 51451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20217 /* 51454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20218 /* 51457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20219 /* 51460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20220 /* 51464 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20221 /* 51468 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20222 /* 51472 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20223 /* 51476 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20224 /* 51480 */ // MIs[1] Operand 1
20225 /* 51480 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20226 /* 51485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20227 /* 51490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20228 /* 51495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20229 /* 51499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20230 /* 51503 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20231 /* 51505 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20232 /* 51505 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20233 /* 51508 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20234 /* 51512 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20235 /* 51517 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20236 /* 51521 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20237 /* 51525 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20238 /* 51527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20239 /* 51530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20240 /* 51532 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20241 /* 51534 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20242 /* 51537 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20243 /* 51539 */ GIR_RootConstrainSelectedInstOperands,
20244 /* 51540 */ // GIR_Coverage, 1657,
20245 /* 51540 */ GIR_EraseRootFromParent_Done,
20246 /* 51541 */ // Label 1319: @51541
20247 /* 51541 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(51639), // Rule ID 1660 //
20248 /* 51546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20249 /* 51549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20250 /* 51552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20251 /* 51555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20252 /* 51558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20253 /* 51562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20254 /* 51566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20255 /* 51570 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20256 /* 51574 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20257 /* 51578 */ // MIs[1] Operand 1
20258 /* 51578 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20259 /* 51583 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20260 /* 51588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20261 /* 51593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20262 /* 51597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20263 /* 51601 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20264 /* 51603 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
20265 /* 51603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20266 /* 51606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20267 /* 51610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20268 /* 51615 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20269 /* 51619 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20270 /* 51623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20271 /* 51625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20272 /* 51628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20273 /* 51630 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20274 /* 51632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20275 /* 51635 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20276 /* 51637 */ GIR_RootConstrainSelectedInstOperands,
20277 /* 51638 */ // GIR_Coverage, 1660,
20278 /* 51638 */ GIR_EraseRootFromParent_Done,
20279 /* 51639 */ // Label 1320: @51639
20280 /* 51639 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(51737), // Rule ID 1661 //
20281 /* 51644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20282 /* 51647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20283 /* 51650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20284 /* 51653 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20285 /* 51656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20286 /* 51660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20287 /* 51664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20288 /* 51668 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20289 /* 51672 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20290 /* 51676 */ // MIs[1] Operand 1
20291 /* 51676 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20292 /* 51681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20293 /* 51686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20294 /* 51691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20295 /* 51695 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20296 /* 51699 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20297 /* 51701 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
20298 /* 51701 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20299 /* 51704 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20300 /* 51708 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20301 /* 51713 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20302 /* 51717 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20303 /* 51721 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20304 /* 51723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20305 /* 51726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20306 /* 51728 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20307 /* 51730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20308 /* 51733 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20309 /* 51735 */ GIR_RootConstrainSelectedInstOperands,
20310 /* 51736 */ // GIR_Coverage, 1661,
20311 /* 51736 */ GIR_EraseRootFromParent_Done,
20312 /* 51737 */ // Label 1321: @51737
20313 /* 51737 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(51835), // Rule ID 1674 //
20314 /* 51742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20315 /* 51745 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20316 /* 51748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20317 /* 51751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20318 /* 51754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20319 /* 51758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20320 /* 51762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20321 /* 51766 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20322 /* 51770 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20323 /* 51774 */ // MIs[1] Operand 1
20324 /* 51774 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20325 /* 51779 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20326 /* 51784 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20327 /* 51789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20328 /* 51793 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20329 /* 51797 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20330 /* 51799 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20331 /* 51799 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20332 /* 51802 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20333 /* 51806 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20334 /* 51811 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20335 /* 51815 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20336 /* 51819 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20337 /* 51821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
20338 /* 51824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20339 /* 51826 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20340 /* 51828 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20341 /* 51831 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20342 /* 51833 */ GIR_RootConstrainSelectedInstOperands,
20343 /* 51834 */ // GIR_Coverage, 1674,
20344 /* 51834 */ GIR_EraseRootFromParent_Done,
20345 /* 51835 */ // Label 1322: @51835
20346 /* 51835 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(51933), // Rule ID 1684 //
20347 /* 51840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20348 /* 51843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20349 /* 51846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20350 /* 51849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20351 /* 51852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20352 /* 51856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20353 /* 51860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20354 /* 51864 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20355 /* 51868 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20356 /* 51872 */ // MIs[1] Operand 1
20357 /* 51872 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20358 /* 51877 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20359 /* 51882 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20360 /* 51887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20361 /* 51891 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20362 /* 51895 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20363 /* 51897 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20364 /* 51897 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20365 /* 51900 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20366 /* 51904 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20367 /* 51909 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20368 /* 51913 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20369 /* 51917 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20370 /* 51919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
20371 /* 51922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20372 /* 51924 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20373 /* 51926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20374 /* 51929 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20375 /* 51931 */ GIR_RootConstrainSelectedInstOperands,
20376 /* 51932 */ // GIR_Coverage, 1684,
20377 /* 51932 */ GIR_EraseRootFromParent_Done,
20378 /* 51933 */ // Label 1323: @51933
20379 /* 51933 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(52031), // Rule ID 1690 //
20380 /* 51938 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20381 /* 51941 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20382 /* 51944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20383 /* 51947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20384 /* 51950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20385 /* 51954 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20386 /* 51958 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20387 /* 51962 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20388 /* 51966 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20389 /* 51970 */ // MIs[1] Operand 1
20390 /* 51970 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20391 /* 51975 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20392 /* 51980 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20393 /* 51985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20394 /* 51989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20395 /* 51993 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20396 /* 51995 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20397 /* 51995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20398 /* 51998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20399 /* 52002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20400 /* 52007 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20401 /* 52011 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20402 /* 52015 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20403 /* 52017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20404 /* 52020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20405 /* 52022 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20406 /* 52024 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20407 /* 52027 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20408 /* 52029 */ GIR_RootConstrainSelectedInstOperands,
20409 /* 52030 */ // GIR_Coverage, 1690,
20410 /* 52030 */ GIR_EraseRootFromParent_Done,
20411 /* 52031 */ // Label 1324: @52031
20412 /* 52031 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(52129), // Rule ID 1691 //
20413 /* 52036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20414 /* 52039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20415 /* 52042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20416 /* 52045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20417 /* 52048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20418 /* 52052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20419 /* 52056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20420 /* 52060 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20421 /* 52064 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20422 /* 52068 */ // MIs[1] Operand 1
20423 /* 52068 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20424 /* 52073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20425 /* 52078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20426 /* 52083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20427 /* 52087 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20428 /* 52091 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20429 /* 52093 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20430 /* 52093 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20431 /* 52096 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20432 /* 52100 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20433 /* 52105 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20434 /* 52109 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20435 /* 52113 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20436 /* 52115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20437 /* 52118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20438 /* 52120 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20439 /* 52122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20440 /* 52125 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20441 /* 52127 */ GIR_RootConstrainSelectedInstOperands,
20442 /* 52128 */ // GIR_Coverage, 1691,
20443 /* 52128 */ GIR_EraseRootFromParent_Done,
20444 /* 52129 */ // Label 1325: @52129
20445 /* 52129 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(52227), // Rule ID 1694 //
20446 /* 52134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20447 /* 52137 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20448 /* 52140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20449 /* 52143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20450 /* 52146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20451 /* 52150 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20452 /* 52154 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20453 /* 52158 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20454 /* 52162 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20455 /* 52166 */ // MIs[1] Operand 1
20456 /* 52166 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20457 /* 52171 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20458 /* 52176 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20459 /* 52181 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20460 /* 52185 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20461 /* 52189 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20462 /* 52191 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20463 /* 52191 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20464 /* 52194 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20465 /* 52198 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20466 /* 52203 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20467 /* 52207 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20468 /* 52211 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20469 /* 52213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20470 /* 52216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20471 /* 52218 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20472 /* 52220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20473 /* 52223 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20474 /* 52225 */ GIR_RootConstrainSelectedInstOperands,
20475 /* 52226 */ // GIR_Coverage, 1694,
20476 /* 52226 */ GIR_EraseRootFromParent_Done,
20477 /* 52227 */ // Label 1326: @52227
20478 /* 52227 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(52325), // Rule ID 1695 //
20479 /* 52232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20480 /* 52235 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20481 /* 52238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20482 /* 52241 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20483 /* 52244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20484 /* 52248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20485 /* 52252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20486 /* 52256 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20487 /* 52260 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20488 /* 52264 */ // MIs[1] Operand 1
20489 /* 52264 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20490 /* 52269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20491 /* 52274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20492 /* 52279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20493 /* 52283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20494 /* 52287 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20495 /* 52289 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20496 /* 52289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20497 /* 52292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20498 /* 52296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20499 /* 52301 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20500 /* 52305 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20501 /* 52309 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20502 /* 52311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20503 /* 52314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20504 /* 52316 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20505 /* 52318 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20506 /* 52321 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20507 /* 52323 */ GIR_RootConstrainSelectedInstOperands,
20508 /* 52324 */ // GIR_Coverage, 1695,
20509 /* 52324 */ GIR_EraseRootFromParent_Done,
20510 /* 52325 */ // Label 1327: @52325
20511 /* 52325 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(52423), // Rule ID 1698 //
20512 /* 52330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20513 /* 52333 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20514 /* 52336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20515 /* 52339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20516 /* 52342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20517 /* 52346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20518 /* 52350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20519 /* 52354 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20520 /* 52358 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20521 /* 52362 */ // MIs[1] Operand 1
20522 /* 52362 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20523 /* 52367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20524 /* 52372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20525 /* 52377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20526 /* 52381 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20527 /* 52385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20528 /* 52387 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20529 /* 52387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20530 /* 52390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20531 /* 52394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20532 /* 52399 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20533 /* 52403 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20534 /* 52407 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20535 /* 52409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20536 /* 52412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20537 /* 52414 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20538 /* 52416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20539 /* 52419 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20540 /* 52421 */ GIR_RootConstrainSelectedInstOperands,
20541 /* 52422 */ // GIR_Coverage, 1698,
20542 /* 52422 */ GIR_EraseRootFromParent_Done,
20543 /* 52423 */ // Label 1328: @52423
20544 /* 52423 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(52521), // Rule ID 1700 //
20545 /* 52428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20546 /* 52431 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20547 /* 52434 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20548 /* 52437 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20549 /* 52440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20550 /* 52444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20551 /* 52448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20552 /* 52452 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20553 /* 52456 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20554 /* 52460 */ // MIs[1] Operand 1
20555 /* 52460 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20556 /* 52465 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20557 /* 52470 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20558 /* 52475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20559 /* 52479 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20560 /* 52483 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20561 /* 52485 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20562 /* 52485 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20563 /* 52488 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20564 /* 52492 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20565 /* 52497 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20566 /* 52501 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20567 /* 52505 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20568 /* 52507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
20569 /* 52510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20570 /* 52512 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20571 /* 52514 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20572 /* 52517 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20573 /* 52519 */ GIR_RootConstrainSelectedInstOperands,
20574 /* 52520 */ // GIR_Coverage, 1700,
20575 /* 52520 */ GIR_EraseRootFromParent_Done,
20576 /* 52521 */ // Label 1329: @52521
20577 /* 52521 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(52619), // Rule ID 1703 //
20578 /* 52526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20579 /* 52529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20580 /* 52532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20581 /* 52535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20582 /* 52538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20583 /* 52542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20584 /* 52546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20585 /* 52550 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20586 /* 52554 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20587 /* 52558 */ // MIs[1] Operand 1
20588 /* 52558 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20589 /* 52563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20590 /* 52568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20591 /* 52573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20592 /* 52577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20593 /* 52581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20594 /* 52583 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
20595 /* 52583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20596 /* 52586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20597 /* 52590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20598 /* 52595 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20599 /* 52599 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20600 /* 52603 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20601 /* 52605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20602 /* 52608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20603 /* 52610 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20604 /* 52612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20605 /* 52615 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20606 /* 52617 */ GIR_RootConstrainSelectedInstOperands,
20607 /* 52618 */ // GIR_Coverage, 1703,
20608 /* 52618 */ GIR_EraseRootFromParent_Done,
20609 /* 52619 */ // Label 1330: @52619
20610 /* 52619 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(52717), // Rule ID 1704 //
20611 /* 52624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20612 /* 52627 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20613 /* 52630 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20614 /* 52633 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20615 /* 52636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20616 /* 52640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20617 /* 52644 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20618 /* 52648 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20619 /* 52652 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20620 /* 52656 */ // MIs[1] Operand 1
20621 /* 52656 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20622 /* 52661 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20623 /* 52666 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20624 /* 52671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20625 /* 52675 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20626 /* 52679 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20627 /* 52681 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
20628 /* 52681 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20629 /* 52684 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20630 /* 52688 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20631 /* 52693 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20632 /* 52697 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20633 /* 52701 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20634 /* 52703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20635 /* 52706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20636 /* 52708 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20637 /* 52710 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20638 /* 52713 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20639 /* 52715 */ GIR_RootConstrainSelectedInstOperands,
20640 /* 52716 */ // GIR_Coverage, 1704,
20641 /* 52716 */ GIR_EraseRootFromParent_Done,
20642 /* 52717 */ // Label 1331: @52717
20643 /* 52717 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(52815), // Rule ID 1707 //
20644 /* 52722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20645 /* 52725 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20646 /* 52728 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20647 /* 52731 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20648 /* 52734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20649 /* 52738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20650 /* 52742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20651 /* 52746 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20652 /* 52750 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20653 /* 52754 */ // MIs[1] Operand 1
20654 /* 52754 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20655 /* 52759 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20656 /* 52764 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20657 /* 52769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20658 /* 52773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20659 /* 52777 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20660 /* 52779 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
20661 /* 52779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20662 /* 52782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20663 /* 52786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20664 /* 52791 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20665 /* 52795 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20666 /* 52799 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20667 /* 52801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20668 /* 52804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20669 /* 52806 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20670 /* 52808 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20671 /* 52811 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20672 /* 52813 */ GIR_RootConstrainSelectedInstOperands,
20673 /* 52814 */ // GIR_Coverage, 1707,
20674 /* 52814 */ GIR_EraseRootFromParent_Done,
20675 /* 52815 */ // Label 1332: @52815
20676 /* 52815 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(52913), // Rule ID 1708 //
20677 /* 52820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20678 /* 52823 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20679 /* 52826 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20680 /* 52829 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20681 /* 52832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20682 /* 52836 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20683 /* 52840 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20684 /* 52844 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20685 /* 52848 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20686 /* 52852 */ // MIs[1] Operand 1
20687 /* 52852 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20688 /* 52857 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20689 /* 52862 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20690 /* 52867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20691 /* 52871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20692 /* 52875 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20693 /* 52877 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
20694 /* 52877 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20695 /* 52880 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20696 /* 52884 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20697 /* 52889 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20698 /* 52893 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20699 /* 52897 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20700 /* 52899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20701 /* 52902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20702 /* 52904 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20703 /* 52906 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20704 /* 52909 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20705 /* 52911 */ GIR_RootConstrainSelectedInstOperands,
20706 /* 52912 */ // GIR_Coverage, 1708,
20707 /* 52912 */ GIR_EraseRootFromParent_Done,
20708 /* 52913 */ // Label 1333: @52913
20709 /* 52913 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(53011), // Rule ID 1711 //
20710 /* 52918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20711 /* 52921 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20712 /* 52924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20713 /* 52927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20714 /* 52930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20715 /* 52934 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20716 /* 52938 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20717 /* 52942 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20718 /* 52946 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20719 /* 52950 */ // MIs[1] Operand 1
20720 /* 52950 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20721 /* 52955 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20722 /* 52960 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20723 /* 52965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20724 /* 52969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20725 /* 52973 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20726 /* 52975 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
20727 /* 52975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20728 /* 52978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20729 /* 52982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20730 /* 52987 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20731 /* 52991 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20732 /* 52995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20733 /* 52997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
20734 /* 53000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20735 /* 53002 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20736 /* 53004 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20737 /* 53007 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20738 /* 53009 */ GIR_RootConstrainSelectedInstOperands,
20739 /* 53010 */ // GIR_Coverage, 1711,
20740 /* 53010 */ GIR_EraseRootFromParent_Done,
20741 /* 53011 */ // Label 1334: @53011
20742 /* 53011 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(53109), // Rule ID 1713 //
20743 /* 53016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20744 /* 53019 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20745 /* 53022 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20746 /* 53025 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20747 /* 53028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20748 /* 53032 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20749 /* 53036 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20750 /* 53040 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20751 /* 53044 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20752 /* 53048 */ // MIs[1] Operand 1
20753 /* 53048 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20754 /* 53053 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20755 /* 53058 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20756 /* 53063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20757 /* 53067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20758 /* 53071 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20759 /* 53073 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
20760 /* 53073 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20761 /* 53076 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20762 /* 53080 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20763 /* 53085 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20764 /* 53089 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20765 /* 53093 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20766 /* 53095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
20767 /* 53098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20768 /* 53100 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20769 /* 53102 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20770 /* 53105 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20771 /* 53107 */ GIR_RootConstrainSelectedInstOperands,
20772 /* 53108 */ // GIR_Coverage, 1713,
20773 /* 53108 */ GIR_EraseRootFromParent_Done,
20774 /* 53109 */ // Label 1335: @53109
20775 /* 53109 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(53190), // Rule ID 1872 //
20776 /* 53114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20777 /* 53117 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20778 /* 53120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20779 /* 53123 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20780 /* 53126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20781 /* 53130 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20782 /* 53134 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20783 /* 53138 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20784 /* 53142 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20785 /* 53146 */ // MIs[1] Operand 1
20786 /* 53146 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20787 /* 53151 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20788 /* 53156 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20789 /* 53161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20790 /* 53165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20791 /* 53169 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20792 /* 53171 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
20793 /* 53171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
20794 /* 53174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20795 /* 53176 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20796 /* 53178 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20797 /* 53180 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20798 /* 53184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20799 /* 53188 */ GIR_RootConstrainSelectedInstOperands,
20800 /* 53189 */ // GIR_Coverage, 1872,
20801 /* 53189 */ GIR_EraseRootFromParent_Done,
20802 /* 53190 */ // Label 1336: @53190
20803 /* 53190 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(53271), // Rule ID 1873 //
20804 /* 53195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20805 /* 53198 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20806 /* 53201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20807 /* 53204 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20808 /* 53207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20809 /* 53211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20810 /* 53215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20811 /* 53219 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20812 /* 53223 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20813 /* 53227 */ // MIs[1] Operand 1
20814 /* 53227 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
20815 /* 53232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20816 /* 53237 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20817 /* 53242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20818 /* 53246 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20819 /* 53250 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20820 /* 53252 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20821 /* 53252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSlt),
20822 /* 53255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20823 /* 53257 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20824 /* 53259 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20825 /* 53261 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20826 /* 53265 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20827 /* 53269 */ GIR_RootConstrainSelectedInstOperands,
20828 /* 53270 */ // GIR_Coverage, 1873,
20829 /* 53270 */ GIR_EraseRootFromParent_Done,
20830 /* 53271 */ // Label 1337: @53271
20831 /* 53271 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(53352), // Rule ID 1874 //
20832 /* 53276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20833 /* 53279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20834 /* 53282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20835 /* 53285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20836 /* 53288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20837 /* 53292 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20838 /* 53296 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20839 /* 53300 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20840 /* 53304 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20841 /* 53308 */ // MIs[1] Operand 1
20842 /* 53308 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20843 /* 53313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20844 /* 53318 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20845 /* 53323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20846 /* 53327 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20847 /* 53331 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20848 /* 53333 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
20849 /* 53333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
20850 /* 53336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20851 /* 53338 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20852 /* 53340 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20853 /* 53342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20854 /* 53346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20855 /* 53350 */ GIR_RootConstrainSelectedInstOperands,
20856 /* 53351 */ // GIR_Coverage, 1874,
20857 /* 53351 */ GIR_EraseRootFromParent_Done,
20858 /* 53352 */ // Label 1338: @53352
20859 /* 53352 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(53433), // Rule ID 1875 //
20860 /* 53357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20861 /* 53360 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20862 /* 53363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20863 /* 53366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20864 /* 53369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20865 /* 53373 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20866 /* 53377 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20867 /* 53381 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20868 /* 53385 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20869 /* 53389 */ // MIs[1] Operand 1
20870 /* 53389 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
20871 /* 53394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20872 /* 53399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20873 /* 53404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20874 /* 53408 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20875 /* 53412 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20876 /* 53414 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20877 /* 53414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSltu),
20878 /* 53417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20879 /* 53419 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20880 /* 53421 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20881 /* 53423 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20882 /* 53427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20883 /* 53431 */ GIR_RootConstrainSelectedInstOperands,
20884 /* 53432 */ // GIR_Coverage, 1875,
20885 /* 53432 */ GIR_EraseRootFromParent_Done,
20886 /* 53433 */ // Label 1339: @53433
20887 /* 53433 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(53514), // Rule ID 1877 //
20888 /* 53438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20889 /* 53441 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20890 /* 53444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20891 /* 53447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20892 /* 53450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20893 /* 53454 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20894 /* 53458 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20895 /* 53462 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20896 /* 53466 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20897 /* 53470 */ // MIs[1] Operand 1
20898 /* 53470 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20899 /* 53475 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20900 /* 53480 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20901 /* 53485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20902 /* 53489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20903 /* 53493 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20904 /* 53495 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20905 /* 53495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
20906 /* 53498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20907 /* 53500 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20908 /* 53502 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20909 /* 53504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20910 /* 53508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20911 /* 53512 */ GIR_RootConstrainSelectedInstOperands,
20912 /* 53513 */ // GIR_Coverage, 1877,
20913 /* 53513 */ GIR_EraseRootFromParent_Done,
20914 /* 53514 */ // Label 1340: @53514
20915 /* 53514 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(53595), // Rule ID 1878 //
20916 /* 53519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20917 /* 53522 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20918 /* 53525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20919 /* 53528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20920 /* 53531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20921 /* 53535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20922 /* 53539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20923 /* 53543 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20924 /* 53547 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20925 /* 53551 */ // MIs[1] Operand 1
20926 /* 53551 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20927 /* 53556 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20928 /* 53561 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20929 /* 53566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20930 /* 53570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20931 /* 53574 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20932 /* 53576 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20933 /* 53576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
20934 /* 53579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20935 /* 53581 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20936 /* 53583 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20937 /* 53585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20938 /* 53589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20939 /* 53593 */ GIR_RootConstrainSelectedInstOperands,
20940 /* 53594 */ // GIR_Coverage, 1878,
20941 /* 53594 */ GIR_EraseRootFromParent_Done,
20942 /* 53595 */ // Label 1341: @53595
20943 /* 53595 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(53676), // Rule ID 1879 //
20944 /* 53600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20945 /* 53603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20946 /* 53606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20947 /* 53609 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20948 /* 53612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20949 /* 53616 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20950 /* 53620 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20951 /* 53624 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20952 /* 53628 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20953 /* 53632 */ // MIs[1] Operand 1
20954 /* 53632 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20955 /* 53637 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20956 /* 53642 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20957 /* 53647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20958 /* 53651 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20959 /* 53655 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20960 /* 53657 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20961 /* 53657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZCmp),
20962 /* 53660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20963 /* 53662 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20964 /* 53664 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20965 /* 53666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20966 /* 53670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20967 /* 53674 */ GIR_RootConstrainSelectedInstOperands,
20968 /* 53675 */ // GIR_Coverage, 1879,
20969 /* 53675 */ GIR_EraseRootFromParent_Done,
20970 /* 53676 */ // Label 1342: @53676
20971 /* 53676 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(53757), // Rule ID 1882 //
20972 /* 53681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20973 /* 53684 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20974 /* 53687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20975 /* 53690 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20976 /* 53693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20977 /* 53697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20978 /* 53701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20979 /* 53705 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20980 /* 53709 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20981 /* 53713 */ // MIs[1] Operand 1
20982 /* 53713 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20983 /* 53718 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20984 /* 53723 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20985 /* 53728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20986 /* 53732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20987 /* 53736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20988 /* 53738 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20989 /* 53738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZCmp),
20990 /* 53741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20991 /* 53743 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20992 /* 53745 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20993 /* 53747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20994 /* 53751 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20995 /* 53755 */ GIR_RootConstrainSelectedInstOperands,
20996 /* 53756 */ // GIR_Coverage, 1882,
20997 /* 53756 */ GIR_EraseRootFromParent_Done,
20998 /* 53757 */ // Label 1343: @53757
20999 /* 53757 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(53855), // Rule ID 2220 //
21000 /* 53762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21001 /* 53765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21002 /* 53768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21003 /* 53771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21004 /* 53774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21005 /* 53778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21006 /* 53782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21007 /* 53786 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21008 /* 53790 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21009 /* 53794 */ // MIs[1] Operand 1
21010 /* 53794 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21011 /* 53799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21012 /* 53804 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21013 /* 53809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21014 /* 53813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21015 /* 53817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21016 /* 53819 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21017 /* 53819 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21018 /* 53822 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21019 /* 53826 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21020 /* 53831 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21021 /* 53835 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21022 /* 53839 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21023 /* 53841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21024 /* 53844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21025 /* 53846 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21026 /* 53848 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21027 /* 53851 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21028 /* 53853 */ GIR_RootConstrainSelectedInstOperands,
21029 /* 53854 */ // GIR_Coverage, 2220,
21030 /* 53854 */ GIR_EraseRootFromParent_Done,
21031 /* 53855 */ // Label 1344: @53855
21032 /* 53855 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(53953), // Rule ID 2221 //
21033 /* 53860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21034 /* 53863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21035 /* 53866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21036 /* 53869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21037 /* 53872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21038 /* 53876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21039 /* 53880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21040 /* 53884 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21041 /* 53888 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21042 /* 53892 */ // MIs[1] Operand 1
21043 /* 53892 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21044 /* 53897 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21045 /* 53902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21046 /* 53907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21047 /* 53911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21048 /* 53915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21049 /* 53917 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21050 /* 53917 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21051 /* 53920 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21052 /* 53924 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21053 /* 53929 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21054 /* 53933 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21055 /* 53937 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21056 /* 53939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21057 /* 53942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21058 /* 53944 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21059 /* 53946 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21060 /* 53949 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21061 /* 53951 */ GIR_RootConstrainSelectedInstOperands,
21062 /* 53952 */ // GIR_Coverage, 2221,
21063 /* 53952 */ GIR_EraseRootFromParent_Done,
21064 /* 53953 */ // Label 1345: @53953
21065 /* 53953 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(54051), // Rule ID 2224 //
21066 /* 53958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21067 /* 53961 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21068 /* 53964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21069 /* 53967 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21070 /* 53970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21071 /* 53974 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21072 /* 53978 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21073 /* 53982 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21074 /* 53986 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21075 /* 53990 */ // MIs[1] Operand 1
21076 /* 53990 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21077 /* 53995 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21078 /* 54000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21079 /* 54005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21080 /* 54009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21081 /* 54013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21082 /* 54015 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21083 /* 54015 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21084 /* 54018 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21085 /* 54022 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21086 /* 54027 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21087 /* 54031 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21088 /* 54035 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21089 /* 54037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21090 /* 54040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21091 /* 54042 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21092 /* 54044 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21093 /* 54047 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21094 /* 54049 */ GIR_RootConstrainSelectedInstOperands,
21095 /* 54050 */ // GIR_Coverage, 2224,
21096 /* 54050 */ GIR_EraseRootFromParent_Done,
21097 /* 54051 */ // Label 1346: @54051
21098 /* 54051 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(54149), // Rule ID 2225 //
21099 /* 54056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21100 /* 54059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21101 /* 54062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21102 /* 54065 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21103 /* 54068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21104 /* 54072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21105 /* 54076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21106 /* 54080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21107 /* 54084 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21108 /* 54088 */ // MIs[1] Operand 1
21109 /* 54088 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21110 /* 54093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21111 /* 54098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21112 /* 54103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21113 /* 54107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21114 /* 54111 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21115 /* 54113 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21116 /* 54113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21117 /* 54116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21118 /* 54120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21119 /* 54125 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21120 /* 54129 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21121 /* 54133 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21122 /* 54135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21123 /* 54138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21124 /* 54140 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21125 /* 54142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21126 /* 54145 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21127 /* 54147 */ GIR_RootConstrainSelectedInstOperands,
21128 /* 54148 */ // GIR_Coverage, 2225,
21129 /* 54148 */ GIR_EraseRootFromParent_Done,
21130 /* 54149 */ // Label 1347: @54149
21131 /* 54149 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(54247), // Rule ID 2228 //
21132 /* 54154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21133 /* 54157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21134 /* 54160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21135 /* 54163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21136 /* 54166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21137 /* 54170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21138 /* 54174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21139 /* 54178 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21140 /* 54182 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21141 /* 54186 */ // MIs[1] Operand 1
21142 /* 54186 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21143 /* 54191 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21144 /* 54196 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21145 /* 54201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21146 /* 54205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21147 /* 54209 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21148 /* 54211 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21149 /* 54211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21150 /* 54214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21151 /* 54218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21152 /* 54223 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21153 /* 54227 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21154 /* 54231 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21155 /* 54233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21156 /* 54236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21157 /* 54238 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21158 /* 54240 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21159 /* 54243 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21160 /* 54245 */ GIR_RootConstrainSelectedInstOperands,
21161 /* 54246 */ // GIR_Coverage, 2228,
21162 /* 54246 */ GIR_EraseRootFromParent_Done,
21163 /* 54247 */ // Label 1348: @54247
21164 /* 54247 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(54345), // Rule ID 2231 //
21165 /* 54252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
21166 /* 54255 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21167 /* 54258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21168 /* 54261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21169 /* 54264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21170 /* 54268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21171 /* 54272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21172 /* 54276 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21173 /* 54280 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21174 /* 54284 */ // MIs[1] Operand 1
21175 /* 54284 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21176 /* 54289 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21177 /* 54294 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21178 /* 54299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21179 /* 54303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21180 /* 54307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21181 /* 54309 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21182 /* 54309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21183 /* 54312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21184 /* 54316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21185 /* 54321 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21186 /* 54325 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21187 /* 54329 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21188 /* 54331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
21189 /* 54334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21190 /* 54336 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21191 /* 54338 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21192 /* 54341 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21193 /* 54343 */ GIR_RootConstrainSelectedInstOperands,
21194 /* 54344 */ // GIR_Coverage, 2231,
21195 /* 54344 */ GIR_EraseRootFromParent_Done,
21196 /* 54345 */ // Label 1349: @54345
21197 /* 54345 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(54443), // Rule ID 2234 //
21198 /* 54350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21199 /* 54353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21200 /* 54356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21201 /* 54359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21202 /* 54362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21203 /* 54366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21204 /* 54370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21205 /* 54374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21206 /* 54378 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21207 /* 54382 */ // MIs[1] Operand 1
21208 /* 54382 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21209 /* 54387 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21210 /* 54392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21211 /* 54397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21212 /* 54401 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21213 /* 54405 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21214 /* 54407 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21215 /* 54407 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21216 /* 54410 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21217 /* 54414 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21218 /* 54419 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21219 /* 54423 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21220 /* 54427 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21221 /* 54429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21222 /* 54432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21223 /* 54434 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21224 /* 54436 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21225 /* 54439 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21226 /* 54441 */ GIR_RootConstrainSelectedInstOperands,
21227 /* 54442 */ // GIR_Coverage, 2234,
21228 /* 54442 */ GIR_EraseRootFromParent_Done,
21229 /* 54443 */ // Label 1350: @54443
21230 /* 54443 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(54541), // Rule ID 2235 //
21231 /* 54448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21232 /* 54451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21233 /* 54454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21234 /* 54457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21235 /* 54460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21236 /* 54464 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21237 /* 54468 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21238 /* 54472 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21239 /* 54476 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21240 /* 54480 */ // MIs[1] Operand 1
21241 /* 54480 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21242 /* 54485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21243 /* 54490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21244 /* 54495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21245 /* 54499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21246 /* 54503 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21247 /* 54505 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21248 /* 54505 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21249 /* 54508 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21250 /* 54512 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21251 /* 54517 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21252 /* 54521 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21253 /* 54525 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21254 /* 54527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21255 /* 54530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21256 /* 54532 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21257 /* 54534 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21258 /* 54537 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21259 /* 54539 */ GIR_RootConstrainSelectedInstOperands,
21260 /* 54540 */ // GIR_Coverage, 2235,
21261 /* 54540 */ GIR_EraseRootFromParent_Done,
21262 /* 54541 */ // Label 1351: @54541
21263 /* 54541 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(54639), // Rule ID 2238 //
21264 /* 54546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21265 /* 54549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21266 /* 54552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21267 /* 54555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21268 /* 54558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21269 /* 54562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21270 /* 54566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21271 /* 54570 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21272 /* 54574 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21273 /* 54578 */ // MIs[1] Operand 1
21274 /* 54578 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21275 /* 54583 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21276 /* 54588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21277 /* 54593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21278 /* 54597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21279 /* 54601 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21280 /* 54603 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21281 /* 54603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21282 /* 54606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21283 /* 54610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21284 /* 54615 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21285 /* 54619 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21286 /* 54623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21287 /* 54625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21288 /* 54628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21289 /* 54630 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21290 /* 54632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21291 /* 54635 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21292 /* 54637 */ GIR_RootConstrainSelectedInstOperands,
21293 /* 54638 */ // GIR_Coverage, 2238,
21294 /* 54638 */ GIR_EraseRootFromParent_Done,
21295 /* 54639 */ // Label 1352: @54639
21296 /* 54639 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(54737), // Rule ID 2239 //
21297 /* 54644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21298 /* 54647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21299 /* 54650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21300 /* 54653 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21301 /* 54656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21302 /* 54660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21303 /* 54664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21304 /* 54668 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21305 /* 54672 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21306 /* 54676 */ // MIs[1] Operand 1
21307 /* 54676 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21308 /* 54681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21309 /* 54686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21310 /* 54691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21311 /* 54695 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21312 /* 54699 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21313 /* 54701 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21314 /* 54701 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21315 /* 54704 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21316 /* 54708 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21317 /* 54713 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21318 /* 54717 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21319 /* 54721 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21320 /* 54723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21321 /* 54726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21322 /* 54728 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21323 /* 54730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21324 /* 54733 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21325 /* 54735 */ GIR_RootConstrainSelectedInstOperands,
21326 /* 54736 */ // GIR_Coverage, 2239,
21327 /* 54736 */ GIR_EraseRootFromParent_Done,
21328 /* 54737 */ // Label 1353: @54737
21329 /* 54737 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(54835), // Rule ID 2242 //
21330 /* 54742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21331 /* 54745 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21332 /* 54748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21333 /* 54751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21334 /* 54754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21335 /* 54758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21336 /* 54762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21337 /* 54766 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21338 /* 54770 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21339 /* 54774 */ // MIs[1] Operand 1
21340 /* 54774 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21341 /* 54779 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21342 /* 54784 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21343 /* 54789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21344 /* 54793 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21345 /* 54797 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21346 /* 54799 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21347 /* 54799 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21348 /* 54802 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21349 /* 54806 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21350 /* 54811 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21351 /* 54815 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21352 /* 54819 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21353 /* 54821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21354 /* 54824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21355 /* 54826 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21356 /* 54828 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21357 /* 54831 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21358 /* 54833 */ GIR_RootConstrainSelectedInstOperands,
21359 /* 54834 */ // GIR_Coverage, 2242,
21360 /* 54834 */ GIR_EraseRootFromParent_Done,
21361 /* 54835 */ // Label 1354: @54835
21362 /* 54835 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(54933), // Rule ID 2245 //
21363 /* 54840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21364 /* 54843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21365 /* 54846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21366 /* 54849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21367 /* 54852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21368 /* 54856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21369 /* 54860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21370 /* 54864 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21371 /* 54868 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21372 /* 54872 */ // MIs[1] Operand 1
21373 /* 54872 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21374 /* 54877 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21375 /* 54882 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21376 /* 54887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21377 /* 54891 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21378 /* 54895 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21379 /* 54897 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21380 /* 54897 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21381 /* 54900 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21382 /* 54904 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21383 /* 54909 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21384 /* 54913 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21385 /* 54917 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21386 /* 54919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
21387 /* 54922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21388 /* 54924 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21389 /* 54926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21390 /* 54929 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21391 /* 54931 */ GIR_RootConstrainSelectedInstOperands,
21392 /* 54932 */ // GIR_Coverage, 2245,
21393 /* 54932 */ GIR_EraseRootFromParent_Done,
21394 /* 54933 */ // Label 1355: @54933
21395 /* 54933 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(55031), // Rule ID 2268 //
21396 /* 54938 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21397 /* 54941 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21398 /* 54944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21399 /* 54947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21400 /* 54950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21401 /* 54954 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21402 /* 54958 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21403 /* 54962 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21404 /* 54966 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21405 /* 54970 */ // MIs[1] Operand 1
21406 /* 54970 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21407 /* 54975 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21408 /* 54980 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21409 /* 54985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21410 /* 54989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21411 /* 54993 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21412 /* 54995 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21413 /* 54995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21414 /* 54998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21415 /* 55002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21416 /* 55007 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21417 /* 55011 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21418 /* 55015 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21419 /* 55017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21420 /* 55020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21421 /* 55022 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21422 /* 55024 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21423 /* 55027 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21424 /* 55029 */ GIR_RootConstrainSelectedInstOperands,
21425 /* 55030 */ // GIR_Coverage, 2268,
21426 /* 55030 */ GIR_EraseRootFromParent_Done,
21427 /* 55031 */ // Label 1356: @55031
21428 /* 55031 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(55129), // Rule ID 2269 //
21429 /* 55036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21430 /* 55039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21431 /* 55042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21432 /* 55045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21433 /* 55048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21434 /* 55052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21435 /* 55056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21436 /* 55060 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21437 /* 55064 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21438 /* 55068 */ // MIs[1] Operand 1
21439 /* 55068 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21440 /* 55073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21441 /* 55078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21442 /* 55083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21443 /* 55087 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21444 /* 55091 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21445 /* 55093 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21446 /* 55093 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21447 /* 55096 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21448 /* 55100 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21449 /* 55105 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21450 /* 55109 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21451 /* 55113 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21452 /* 55115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21453 /* 55118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21454 /* 55120 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21455 /* 55122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21456 /* 55125 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21457 /* 55127 */ GIR_RootConstrainSelectedInstOperands,
21458 /* 55128 */ // GIR_Coverage, 2269,
21459 /* 55128 */ GIR_EraseRootFromParent_Done,
21460 /* 55129 */ // Label 1357: @55129
21461 /* 55129 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(55227), // Rule ID 2272 //
21462 /* 55134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21463 /* 55137 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21464 /* 55140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21465 /* 55143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21466 /* 55146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21467 /* 55150 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21468 /* 55154 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21469 /* 55158 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21470 /* 55162 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21471 /* 55166 */ // MIs[1] Operand 1
21472 /* 55166 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21473 /* 55171 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21474 /* 55176 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21475 /* 55181 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21476 /* 55185 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21477 /* 55189 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21478 /* 55191 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
21479 /* 55191 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21480 /* 55194 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21481 /* 55198 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21482 /* 55203 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21483 /* 55207 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21484 /* 55211 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21485 /* 55213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21486 /* 55216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21487 /* 55218 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21488 /* 55220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21489 /* 55223 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21490 /* 55225 */ GIR_RootConstrainSelectedInstOperands,
21491 /* 55226 */ // GIR_Coverage, 2272,
21492 /* 55226 */ GIR_EraseRootFromParent_Done,
21493 /* 55227 */ // Label 1358: @55227
21494 /* 55227 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(55325), // Rule ID 2273 //
21495 /* 55232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21496 /* 55235 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21497 /* 55238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21498 /* 55241 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21499 /* 55244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21500 /* 55248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21501 /* 55252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21502 /* 55256 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21503 /* 55260 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21504 /* 55264 */ // MIs[1] Operand 1
21505 /* 55264 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21506 /* 55269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21507 /* 55274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21508 /* 55279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21509 /* 55283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21510 /* 55287 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21511 /* 55289 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
21512 /* 55289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21513 /* 55292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21514 /* 55296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21515 /* 55301 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21516 /* 55305 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21517 /* 55309 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21518 /* 55311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21519 /* 55314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21520 /* 55316 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21521 /* 55318 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21522 /* 55321 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21523 /* 55323 */ GIR_RootConstrainSelectedInstOperands,
21524 /* 55324 */ // GIR_Coverage, 2273,
21525 /* 55324 */ GIR_EraseRootFromParent_Done,
21526 /* 55325 */ // Label 1359: @55325
21527 /* 55325 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(55423), // Rule ID 2276 //
21528 /* 55330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21529 /* 55333 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21530 /* 55336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21531 /* 55339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21532 /* 55342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21533 /* 55346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21534 /* 55350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21535 /* 55354 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21536 /* 55358 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21537 /* 55362 */ // MIs[1] Operand 1
21538 /* 55362 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21539 /* 55367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21540 /* 55372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21541 /* 55377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21542 /* 55381 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21543 /* 55385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21544 /* 55387 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21545 /* 55387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21546 /* 55390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21547 /* 55394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21548 /* 55399 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21549 /* 55403 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21550 /* 55407 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21551 /* 55409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21552 /* 55412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21553 /* 55414 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21554 /* 55416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21555 /* 55419 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21556 /* 55421 */ GIR_RootConstrainSelectedInstOperands,
21557 /* 55422 */ // GIR_Coverage, 2276,
21558 /* 55422 */ GIR_EraseRootFromParent_Done,
21559 /* 55423 */ // Label 1360: @55423
21560 /* 55423 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(55521), // Rule ID 2278 //
21561 /* 55428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21562 /* 55431 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21563 /* 55434 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21564 /* 55437 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21565 /* 55440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21566 /* 55444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21567 /* 55448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21568 /* 55452 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21569 /* 55456 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21570 /* 55460 */ // MIs[1] Operand 1
21571 /* 55460 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21572 /* 55465 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21573 /* 55470 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21574 /* 55475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21575 /* 55479 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21576 /* 55483 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21577 /* 55485 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21578 /* 55485 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21579 /* 55488 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21580 /* 55492 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21581 /* 55497 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21582 /* 55501 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21583 /* 55505 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21584 /* 55507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
21585 /* 55510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21586 /* 55512 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21587 /* 55514 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21588 /* 55517 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21589 /* 55519 */ GIR_RootConstrainSelectedInstOperands,
21590 /* 55520 */ // GIR_Coverage, 2278,
21591 /* 55520 */ GIR_EraseRootFromParent_Done,
21592 /* 55521 */ // Label 1361: @55521
21593 /* 55521 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(55561), // Rule ID 295 //
21594 /* 55526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
21595 /* 55529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21596 /* 55532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21597 /* 55535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21598 /* 55538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21599 /* 55542 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21600 /* 55546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21601 /* 55550 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21602 /* 55554 */ // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
21603 /* 55554 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I),
21604 /* 55559 */ GIR_RootConstrainSelectedInstOperands,
21605 /* 55560 */ // GIR_Coverage, 295,
21606 /* 55560 */ GIR_Done,
21607 /* 55561 */ // Label 1362: @55561
21608 /* 55561 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(55601), // Rule ID 297 //
21609 /* 55566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
21610 /* 55569 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21611 /* 55572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21612 /* 55575 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21613 /* 55578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21614 /* 55582 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21615 /* 55586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21616 /* 55590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21617 /* 55594 */ // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
21618 /* 55594 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_S),
21619 /* 55599 */ GIR_RootConstrainSelectedInstOperands,
21620 /* 55600 */ // GIR_Coverage, 297,
21621 /* 55600 */ GIR_Done,
21622 /* 55601 */ // Label 1363: @55601
21623 /* 55601 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(55647), // Rule ID 334 //
21624 /* 55606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
21625 /* 55609 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21626 /* 55612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21627 /* 55615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21628 /* 55618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21629 /* 55622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
21630 /* 55626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21631 /* 55630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21632 /* 55634 */ // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21633 /* 55634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S),
21634 /* 55637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21635 /* 55639 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
21636 /* 55641 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
21637 /* 55643 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
21638 /* 55645 */ GIR_RootConstrainSelectedInstOperands,
21639 /* 55646 */ // GIR_Coverage, 334,
21640 /* 55646 */ GIR_EraseRootFromParent_Done,
21641 /* 55647 */ // Label 1364: @55647
21642 /* 55647 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(55693), // Rule ID 1213 //
21643 /* 55652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
21644 /* 55655 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21645 /* 55658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21646 /* 55661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21647 /* 55664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21648 /* 55668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
21649 /* 55672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21650 /* 55676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21651 /* 55680 */ // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
21652 /* 55680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S_MMR6),
21653 /* 55683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21654 /* 55685 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
21655 /* 55687 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
21656 /* 55689 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
21657 /* 55691 */ GIR_RootConstrainSelectedInstOperands,
21658 /* 55692 */ // GIR_Coverage, 1213,
21659 /* 55692 */ GIR_EraseRootFromParent_Done,
21660 /* 55693 */ // Label 1365: @55693
21661 /* 55693 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(55739), // Rule ID 1646 //
21662 /* 55698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
21663 /* 55701 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21664 /* 55704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21665 /* 55707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21666 /* 55710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21667 /* 55714 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21668 /* 55718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21669 /* 55722 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21670 /* 55726 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
21671 /* 55726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
21672 /* 55729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21673 /* 55731 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21674 /* 55733 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
21675 /* 55735 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21676 /* 55737 */ GIR_RootConstrainSelectedInstOperands,
21677 /* 55738 */ // GIR_Coverage, 1646,
21678 /* 55738 */ GIR_EraseRootFromParent_Done,
21679 /* 55739 */ // Label 1366: @55739
21680 /* 55739 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(55785), // Rule ID 1685 //
21681 /* 55744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21682 /* 55747 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21683 /* 55750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21684 /* 55753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21685 /* 55756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21686 /* 55760 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21687 /* 55764 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21688 /* 55768 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21689 /* 55772 */ // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
21690 /* 55772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
21691 /* 55775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21692 /* 55777 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21693 /* 55779 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
21694 /* 55781 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21695 /* 55783 */ GIR_RootConstrainSelectedInstOperands,
21696 /* 55784 */ // GIR_Coverage, 1685,
21697 /* 55784 */ GIR_EraseRootFromParent_Done,
21698 /* 55785 */ // Label 1367: @55785
21699 /* 55785 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(55831), // Rule ID 1701 //
21700 /* 55790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
21701 /* 55793 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21702 /* 55796 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21703 /* 55799 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21704 /* 55802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21705 /* 55806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21706 /* 55810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21707 /* 55814 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21708 /* 55818 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
21709 /* 55818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
21710 /* 55821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21711 /* 55823 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21712 /* 55825 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
21713 /* 55827 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21714 /* 55829 */ GIR_RootConstrainSelectedInstOperands,
21715 /* 55830 */ // GIR_Coverage, 1701,
21716 /* 55830 */ GIR_EraseRootFromParent_Done,
21717 /* 55831 */ // Label 1368: @55831
21718 /* 55831 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(55877), // Rule ID 1714 //
21719 /* 55836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21720 /* 55839 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21721 /* 55842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21722 /* 55845 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21723 /* 55848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21724 /* 55852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21725 /* 55856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21726 /* 55860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21727 /* 55864 */ // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
21728 /* 55864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
21729 /* 55867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21730 /* 55869 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21731 /* 55871 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
21732 /* 55873 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21733 /* 55875 */ GIR_RootConstrainSelectedInstOperands,
21734 /* 55876 */ // GIR_Coverage, 1714,
21735 /* 55876 */ GIR_EraseRootFromParent_Done,
21736 /* 55877 */ // Label 1369: @55877
21737 /* 55877 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(55923), // Rule ID 1884 //
21738 /* 55882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21739 /* 55885 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21740 /* 55888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21741 /* 55891 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21742 /* 55894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21743 /* 55898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21744 /* 55902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21745 /* 55906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21746 /* 55910 */ // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
21747 /* 55910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
21748 /* 55913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21749 /* 55915 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21750 /* 55917 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21751 /* 55919 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
21752 /* 55921 */ GIR_RootConstrainSelectedInstOperands,
21753 /* 55922 */ // GIR_Coverage, 1884,
21754 /* 55922 */ GIR_EraseRootFromParent_Done,
21755 /* 55923 */ // Label 1370: @55923
21756 /* 55923 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(55969), // Rule ID 2232 //
21757 /* 55928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
21758 /* 55931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21759 /* 55934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21760 /* 55937 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21761 /* 55940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21762 /* 55944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21763 /* 55948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21764 /* 55952 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21765 /* 55956 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
21766 /* 55956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
21767 /* 55959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21768 /* 55961 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21769 /* 55963 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
21770 /* 55965 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21771 /* 55967 */ GIR_RootConstrainSelectedInstOperands,
21772 /* 55968 */ // GIR_Coverage, 2232,
21773 /* 55968 */ GIR_EraseRootFromParent_Done,
21774 /* 55969 */ // Label 1371: @55969
21775 /* 55969 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(56015), // Rule ID 2246 //
21776 /* 55974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21777 /* 55977 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21778 /* 55980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21779 /* 55983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21780 /* 55986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21781 /* 55990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21782 /* 55994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21783 /* 55998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21784 /* 56002 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
21785 /* 56002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
21786 /* 56005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21787 /* 56007 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21788 /* 56009 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
21789 /* 56011 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21790 /* 56013 */ GIR_RootConstrainSelectedInstOperands,
21791 /* 56014 */ // GIR_Coverage, 2246,
21792 /* 56014 */ GIR_EraseRootFromParent_Done,
21793 /* 56015 */ // Label 1372: @56015
21794 /* 56015 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(56061), // Rule ID 2279 //
21795 /* 56020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21796 /* 56023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21797 /* 56026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21798 /* 56029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21799 /* 56032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21800 /* 56036 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21801 /* 56040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21802 /* 56044 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21803 /* 56048 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
21804 /* 56048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
21805 /* 56051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21806 /* 56053 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21807 /* 56055 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
21808 /* 56057 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21809 /* 56059 */ GIR_RootConstrainSelectedInstOperands,
21810 /* 56060 */ // GIR_Coverage, 2279,
21811 /* 56060 */ GIR_EraseRootFromParent_Done,
21812 /* 56061 */ // Label 1373: @56061
21813 /* 56061 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(56139), // Rule ID 1783 //
21814 /* 56066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
21815 /* 56069 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21816 /* 56072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21817 /* 56075 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21818 /* 56078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21819 /* 56082 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
21820 /* 56082 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
21821 /* 56085 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ),
21822 /* 56089 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21823 /* 56094 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
21824 /* 56098 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
21825 /* 56102 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21826 /* 56104 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21827 /* 56107 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ),
21828 /* 56111 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21829 /* 56116 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
21830 /* 56120 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
21831 /* 56124 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21832 /* 56126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR),
21833 /* 56129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21834 /* 56131 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21835 /* 56134 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
21836 /* 56137 */ GIR_RootConstrainSelectedInstOperands,
21837 /* 56138 */ // GIR_Coverage, 1783,
21838 /* 56138 */ GIR_EraseRootFromParent_Done,
21839 /* 56139 */ // Label 1374: @56139
21840 /* 56139 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(56217), // Rule ID 2296 //
21841 /* 56144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
21842 /* 56147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21843 /* 56150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21844 /* 56153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21845 /* 56156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21846 /* 56160 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
21847 /* 56160 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
21848 /* 56163 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ_MMR6),
21849 /* 56167 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21850 /* 56172 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
21851 /* 56176 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
21852 /* 56180 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21853 /* 56182 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21854 /* 56185 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ_MMR6),
21855 /* 56189 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21856 /* 56194 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
21857 /* 56198 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
21858 /* 56202 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21859 /* 56204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
21860 /* 56207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21861 /* 56209 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21862 /* 56212 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
21863 /* 56215 */ GIR_RootConstrainSelectedInstOperands,
21864 /* 56216 */ // GIR_Coverage, 2296,
21865 /* 56216 */ GIR_EraseRootFromParent_Done,
21866 /* 56217 */ // Label 1375: @56217
21867 /* 56217 */ GIM_Reject,
21868 /* 56218 */ // Label 1290: @56218
21869 /* 56218 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(56294), // Rule ID 1673 //
21870 /* 56223 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21871 /* 56226 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21872 /* 56229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21873 /* 56232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21874 /* 56235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21875 /* 56239 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21876 /* 56243 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21877 /* 56247 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21878 /* 56251 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21879 /* 56255 */ // MIs[1] Operand 1
21880 /* 56255 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21881 /* 56260 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21882 /* 56265 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21883 /* 56269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21884 /* 56273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21885 /* 56277 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21886 /* 56279 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
21887 /* 56279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21888 /* 56282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21889 /* 56284 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21890 /* 56286 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21891 /* 56290 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21892 /* 56292 */ GIR_RootConstrainSelectedInstOperands,
21893 /* 56293 */ // GIR_Coverage, 1673,
21894 /* 56293 */ GIR_EraseRootFromParent_Done,
21895 /* 56294 */ // Label 1376: @56294
21896 /* 56294 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(56370), // Rule ID 1677 //
21897 /* 56299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21898 /* 56302 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21899 /* 56305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21900 /* 56308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21901 /* 56311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21902 /* 56315 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21903 /* 56319 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21904 /* 56323 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21905 /* 56327 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21906 /* 56331 */ // MIs[1] Operand 1
21907 /* 56331 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21908 /* 56336 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21909 /* 56341 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21910 /* 56345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21911 /* 56349 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21912 /* 56353 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21913 /* 56355 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
21914 /* 56355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
21915 /* 56358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21916 /* 56360 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21917 /* 56362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21918 /* 56366 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21919 /* 56368 */ GIR_RootConstrainSelectedInstOperands,
21920 /* 56369 */ // GIR_Coverage, 1677,
21921 /* 56369 */ GIR_EraseRootFromParent_Done,
21922 /* 56370 */ // Label 1377: @56370
21923 /* 56370 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(56446), // Rule ID 1683 //
21924 /* 56375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21925 /* 56378 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21926 /* 56381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21927 /* 56384 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21928 /* 56387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21929 /* 56391 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21930 /* 56395 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21931 /* 56399 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21932 /* 56403 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21933 /* 56407 */ // MIs[1] Operand 1
21934 /* 56407 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21935 /* 56412 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21936 /* 56417 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21937 /* 56421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21938 /* 56425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21939 /* 56429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21940 /* 56431 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
21941 /* 56431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
21942 /* 56434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21943 /* 56436 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21944 /* 56438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21945 /* 56442 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21946 /* 56444 */ GIR_RootConstrainSelectedInstOperands,
21947 /* 56445 */ // GIR_Coverage, 1683,
21948 /* 56445 */ GIR_EraseRootFromParent_Done,
21949 /* 56446 */ // Label 1378: @56446
21950 /* 56446 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(56522), // Rule ID 1689 //
21951 /* 56451 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21952 /* 56454 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21953 /* 56457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21954 /* 56460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21955 /* 56463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21956 /* 56467 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21957 /* 56471 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21958 /* 56475 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21959 /* 56479 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21960 /* 56483 */ // MIs[1] Operand 1
21961 /* 56483 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21962 /* 56488 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21963 /* 56493 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21964 /* 56497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21965 /* 56501 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21966 /* 56505 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21967 /* 56507 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
21968 /* 56507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
21969 /* 56510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21970 /* 56512 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21971 /* 56514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21972 /* 56518 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21973 /* 56520 */ GIR_RootConstrainSelectedInstOperands,
21974 /* 56521 */ // GIR_Coverage, 1689,
21975 /* 56521 */ GIR_EraseRootFromParent_Done,
21976 /* 56522 */ // Label 1379: @56522
21977 /* 56522 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(56598), // Rule ID 1725 //
21978 /* 56527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21979 /* 56530 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21980 /* 56533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21981 /* 56536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21982 /* 56539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21983 /* 56543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21984 /* 56547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21985 /* 56551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21986 /* 56555 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21987 /* 56559 */ // MIs[1] Operand 1
21988 /* 56559 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21989 /* 56564 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21990 /* 56569 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21991 /* 56573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21992 /* 56577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21993 /* 56581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21994 /* 56583 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
21995 /* 56583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21996 /* 56586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21997 /* 56588 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21998 /* 56590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21999 /* 56594 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22000 /* 56596 */ GIR_RootConstrainSelectedInstOperands,
22001 /* 56597 */ // GIR_Coverage, 1725,
22002 /* 56597 */ GIR_EraseRootFromParent_Done,
22003 /* 56598 */ // Label 1380: @56598
22004 /* 56598 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(56674), // Rule ID 1728 //
22005 /* 56603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22006 /* 56606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22007 /* 56609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22008 /* 56612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22009 /* 56615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22010 /* 56619 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22011 /* 56623 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22012 /* 56627 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22013 /* 56631 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22014 /* 56635 */ // MIs[1] Operand 1
22015 /* 56635 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22016 /* 56640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22017 /* 56645 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22018 /* 56649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22019 /* 56653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22020 /* 56657 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22021 /* 56659 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22022 /* 56659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
22023 /* 56662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22024 /* 56664 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22025 /* 56666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22026 /* 56670 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22027 /* 56672 */ GIR_RootConstrainSelectedInstOperands,
22028 /* 56673 */ // GIR_Coverage, 1728,
22029 /* 56673 */ GIR_EraseRootFromParent_Done,
22030 /* 56674 */ // Label 1381: @56674
22031 /* 56674 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(56750), // Rule ID 1746 //
22032 /* 56679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22033 /* 56682 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22034 /* 56685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22035 /* 56688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22036 /* 56691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22037 /* 56695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22038 /* 56699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22039 /* 56703 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22040 /* 56707 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22041 /* 56711 */ // MIs[1] Operand 1
22042 /* 56711 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22043 /* 56716 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22044 /* 56721 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22045 /* 56725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22046 /* 56729 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22047 /* 56733 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22048 /* 56735 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
22049 /* 56735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22050 /* 56738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22051 /* 56740 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22052 /* 56742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22053 /* 56746 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22054 /* 56748 */ GIR_RootConstrainSelectedInstOperands,
22055 /* 56749 */ // GIR_Coverage, 1746,
22056 /* 56749 */ GIR_EraseRootFromParent_Done,
22057 /* 56750 */ // Label 1382: @56750
22058 /* 56750 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(56826), // Rule ID 1748 //
22059 /* 56755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22060 /* 56758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22061 /* 56761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22062 /* 56764 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22063 /* 56767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22064 /* 56771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22065 /* 56775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22066 /* 56779 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22067 /* 56783 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22068 /* 56787 */ // MIs[1] Operand 1
22069 /* 56787 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22070 /* 56792 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22071 /* 56797 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22072 /* 56801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22073 /* 56805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22074 /* 56809 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22075 /* 56811 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
22076 /* 56811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
22077 /* 56814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22078 /* 56816 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22079 /* 56818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22080 /* 56822 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22081 /* 56824 */ GIR_RootConstrainSelectedInstOperands,
22082 /* 56825 */ // GIR_Coverage, 1748,
22083 /* 56825 */ GIR_EraseRootFromParent_Done,
22084 /* 56826 */ // Label 1383: @56826
22085 /* 56826 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(56902), // Rule ID 1751 //
22086 /* 56831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22087 /* 56834 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22088 /* 56837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22089 /* 56840 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22090 /* 56843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22091 /* 56847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22092 /* 56851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22093 /* 56855 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22094 /* 56859 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22095 /* 56863 */ // MIs[1] Operand 1
22096 /* 56863 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22097 /* 56868 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22098 /* 56873 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22099 /* 56877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22100 /* 56881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22101 /* 56885 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22102 /* 56887 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
22103 /* 56887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
22104 /* 56890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22105 /* 56892 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22106 /* 56894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22107 /* 56898 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22108 /* 56900 */ GIR_RootConstrainSelectedInstOperands,
22109 /* 56901 */ // GIR_Coverage, 1751,
22110 /* 56901 */ GIR_EraseRootFromParent_Done,
22111 /* 56902 */ // Label 1384: @56902
22112 /* 56902 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(56978), // Rule ID 1754 //
22113 /* 56907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22114 /* 56910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22115 /* 56913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22116 /* 56916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22117 /* 56919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22118 /* 56923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22119 /* 56927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22120 /* 56931 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22121 /* 56935 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22122 /* 56939 */ // MIs[1] Operand 1
22123 /* 56939 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22124 /* 56944 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22125 /* 56949 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22126 /* 56953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22127 /* 56957 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22128 /* 56961 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22129 /* 56963 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
22130 /* 56963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
22131 /* 56966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22132 /* 56968 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22133 /* 56970 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22134 /* 56974 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22135 /* 56976 */ GIR_RootConstrainSelectedInstOperands,
22136 /* 56977 */ // GIR_Coverage, 1754,
22137 /* 56977 */ GIR_EraseRootFromParent_Done,
22138 /* 56978 */ // Label 1385: @56978
22139 /* 56978 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(57054), // Rule ID 2290 //
22140 /* 56983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22141 /* 56986 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22142 /* 56989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22143 /* 56992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22144 /* 56995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22145 /* 56999 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22146 /* 57003 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22147 /* 57007 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22148 /* 57011 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22149 /* 57015 */ // MIs[1] Operand 1
22150 /* 57015 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22151 /* 57020 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22152 /* 57025 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22153 /* 57029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22154 /* 57033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22155 /* 57037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22156 /* 57039 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22157 /* 57039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22158 /* 57042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22159 /* 57044 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22160 /* 57046 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22161 /* 57050 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22162 /* 57052 */ GIR_RootConstrainSelectedInstOperands,
22163 /* 57053 */ // GIR_Coverage, 2290,
22164 /* 57053 */ GIR_EraseRootFromParent_Done,
22165 /* 57054 */ // Label 1386: @57054
22166 /* 57054 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(57130), // Rule ID 2293 //
22167 /* 57059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22168 /* 57062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22169 /* 57065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22170 /* 57068 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22171 /* 57071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22172 /* 57075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22173 /* 57079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22174 /* 57083 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22175 /* 57087 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22176 /* 57091 */ // MIs[1] Operand 1
22177 /* 57091 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22178 /* 57096 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22179 /* 57101 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22180 /* 57105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22181 /* 57109 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22182 /* 57113 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22183 /* 57115 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22184 /* 57115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22185 /* 57118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22186 /* 57120 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22187 /* 57122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22188 /* 57126 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22189 /* 57128 */ GIR_RootConstrainSelectedInstOperands,
22190 /* 57129 */ // GIR_Coverage, 2293,
22191 /* 57129 */ GIR_EraseRootFromParent_Done,
22192 /* 57130 */ // Label 1387: @57130
22193 /* 57130 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(57228), // Rule ID 1648 //
22194 /* 57135 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22195 /* 57138 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22196 /* 57141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22197 /* 57144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22198 /* 57147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22199 /* 57151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22200 /* 57155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22201 /* 57159 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22202 /* 57163 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22203 /* 57167 */ // MIs[1] Operand 1
22204 /* 57167 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22205 /* 57172 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22206 /* 57177 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22207 /* 57182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22208 /* 57186 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22209 /* 57190 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22210 /* 57192 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22211 /* 57192 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22212 /* 57195 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22213 /* 57199 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22214 /* 57204 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22215 /* 57208 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22216 /* 57212 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22217 /* 57214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22218 /* 57217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22219 /* 57219 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22220 /* 57221 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22221 /* 57224 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22222 /* 57226 */ GIR_RootConstrainSelectedInstOperands,
22223 /* 57227 */ // GIR_Coverage, 1648,
22224 /* 57227 */ GIR_EraseRootFromParent_Done,
22225 /* 57228 */ // Label 1388: @57228
22226 /* 57228 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(57326), // Rule ID 1649 //
22227 /* 57233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22228 /* 57236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22229 /* 57239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22230 /* 57242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22231 /* 57245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22232 /* 57249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22233 /* 57253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22234 /* 57257 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22235 /* 57261 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22236 /* 57265 */ // MIs[1] Operand 1
22237 /* 57265 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22238 /* 57270 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22239 /* 57275 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22240 /* 57280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22241 /* 57284 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22242 /* 57288 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22243 /* 57290 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22244 /* 57290 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22245 /* 57293 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22246 /* 57297 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22247 /* 57302 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22248 /* 57306 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22249 /* 57310 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22250 /* 57312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22251 /* 57315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22252 /* 57317 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22253 /* 57319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22254 /* 57322 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22255 /* 57324 */ GIR_RootConstrainSelectedInstOperands,
22256 /* 57325 */ // GIR_Coverage, 1649,
22257 /* 57325 */ GIR_EraseRootFromParent_Done,
22258 /* 57326 */ // Label 1389: @57326
22259 /* 57326 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(57424), // Rule ID 1652 //
22260 /* 57331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22261 /* 57334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22262 /* 57337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22263 /* 57340 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22264 /* 57343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22265 /* 57347 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22266 /* 57351 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22267 /* 57355 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22268 /* 57359 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22269 /* 57363 */ // MIs[1] Operand 1
22270 /* 57363 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22271 /* 57368 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22272 /* 57373 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22273 /* 57378 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22274 /* 57382 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22275 /* 57386 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22276 /* 57388 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
22277 /* 57388 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22278 /* 57391 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22279 /* 57395 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22280 /* 57400 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22281 /* 57404 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22282 /* 57408 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22283 /* 57410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22284 /* 57413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22285 /* 57415 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22286 /* 57417 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22287 /* 57420 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22288 /* 57422 */ GIR_RootConstrainSelectedInstOperands,
22289 /* 57423 */ // GIR_Coverage, 1652,
22290 /* 57423 */ GIR_EraseRootFromParent_Done,
22291 /* 57424 */ // Label 1390: @57424
22292 /* 57424 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(57522), // Rule ID 1653 //
22293 /* 57429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22294 /* 57432 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22295 /* 57435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22296 /* 57438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22297 /* 57441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22298 /* 57445 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22299 /* 57449 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22300 /* 57453 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22301 /* 57457 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22302 /* 57461 */ // MIs[1] Operand 1
22303 /* 57461 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22304 /* 57466 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22305 /* 57471 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22306 /* 57476 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22307 /* 57480 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22308 /* 57484 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22309 /* 57486 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
22310 /* 57486 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22311 /* 57489 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22312 /* 57493 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22313 /* 57498 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22314 /* 57502 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22315 /* 57506 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22316 /* 57508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22317 /* 57511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22318 /* 57513 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22319 /* 57515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22320 /* 57518 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22321 /* 57520 */ GIR_RootConstrainSelectedInstOperands,
22322 /* 57521 */ // GIR_Coverage, 1653,
22323 /* 57521 */ GIR_EraseRootFromParent_Done,
22324 /* 57522 */ // Label 1391: @57522
22325 /* 57522 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(57620), // Rule ID 1664 //
22326 /* 57527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22327 /* 57530 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22328 /* 57533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22329 /* 57536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22330 /* 57539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22331 /* 57543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22332 /* 57547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22333 /* 57551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22334 /* 57555 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22335 /* 57559 */ // MIs[1] Operand 1
22336 /* 57559 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22337 /* 57564 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22338 /* 57569 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22339 /* 57574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22340 /* 57578 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22341 /* 57582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22342 /* 57584 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22343 /* 57584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22344 /* 57587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
22345 /* 57591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22346 /* 57596 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22347 /* 57600 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22348 /* 57604 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22349 /* 57606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22350 /* 57609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22351 /* 57611 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22352 /* 57613 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22353 /* 57616 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22354 /* 57618 */ GIR_RootConstrainSelectedInstOperands,
22355 /* 57619 */ // GIR_Coverage, 1664,
22356 /* 57619 */ GIR_EraseRootFromParent_Done,
22357 /* 57620 */ // Label 1392: @57620
22358 /* 57620 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(57718), // Rule ID 1665 //
22359 /* 57625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22360 /* 57628 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22361 /* 57631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22362 /* 57634 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22363 /* 57637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22364 /* 57641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22365 /* 57645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22366 /* 57649 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22367 /* 57653 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22368 /* 57657 */ // MIs[1] Operand 1
22369 /* 57657 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22370 /* 57662 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22371 /* 57667 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22372 /* 57672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22373 /* 57676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22374 /* 57680 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22375 /* 57682 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22376 /* 57682 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22377 /* 57685 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
22378 /* 57689 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22379 /* 57694 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22380 /* 57698 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22381 /* 57702 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22382 /* 57704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22383 /* 57707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22384 /* 57709 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22385 /* 57711 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22386 /* 57714 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22387 /* 57716 */ GIR_RootConstrainSelectedInstOperands,
22388 /* 57717 */ // GIR_Coverage, 1665,
22389 /* 57717 */ GIR_EraseRootFromParent_Done,
22390 /* 57718 */ // Label 1393: @57718
22391 /* 57718 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(57816), // Rule ID 1668 //
22392 /* 57723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22393 /* 57726 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22394 /* 57729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22395 /* 57732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22396 /* 57735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22397 /* 57739 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22398 /* 57743 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22399 /* 57747 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22400 /* 57751 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22401 /* 57755 */ // MIs[1] Operand 1
22402 /* 57755 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22403 /* 57760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22404 /* 57765 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22405 /* 57770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22406 /* 57774 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22407 /* 57778 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22408 /* 57780 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
22409 /* 57780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22410 /* 57783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
22411 /* 57787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22412 /* 57792 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22413 /* 57796 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22414 /* 57800 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22415 /* 57802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22416 /* 57805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22417 /* 57807 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22418 /* 57809 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22419 /* 57812 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22420 /* 57814 */ GIR_RootConstrainSelectedInstOperands,
22421 /* 57815 */ // GIR_Coverage, 1668,
22422 /* 57815 */ GIR_EraseRootFromParent_Done,
22423 /* 57816 */ // Label 1394: @57816
22424 /* 57816 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(57914), // Rule ID 1669 //
22425 /* 57821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22426 /* 57824 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22427 /* 57827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22428 /* 57830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22429 /* 57833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22430 /* 57837 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22431 /* 57841 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22432 /* 57845 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22433 /* 57849 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22434 /* 57853 */ // MIs[1] Operand 1
22435 /* 57853 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22436 /* 57858 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22437 /* 57863 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22438 /* 57868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22439 /* 57872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22440 /* 57876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22441 /* 57878 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
22442 /* 57878 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22443 /* 57881 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
22444 /* 57885 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22445 /* 57890 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22446 /* 57894 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22447 /* 57898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22448 /* 57900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22449 /* 57903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22450 /* 57905 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22451 /* 57907 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22452 /* 57910 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22453 /* 57912 */ GIR_RootConstrainSelectedInstOperands,
22454 /* 57913 */ // GIR_Coverage, 1669,
22455 /* 57913 */ GIR_EraseRootFromParent_Done,
22456 /* 57914 */ // Label 1395: @57914
22457 /* 57914 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(58012), // Rule ID 1672 //
22458 /* 57919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22459 /* 57922 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22460 /* 57925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22461 /* 57928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22462 /* 57931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22463 /* 57935 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22464 /* 57939 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22465 /* 57943 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22466 /* 57947 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22467 /* 57951 */ // MIs[1] Operand 1
22468 /* 57951 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22469 /* 57956 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22470 /* 57961 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22471 /* 57966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22472 /* 57970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22473 /* 57974 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22474 /* 57976 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22475 /* 57976 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22476 /* 57979 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
22477 /* 57983 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22478 /* 57988 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22479 /* 57992 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22480 /* 57996 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22481 /* 57998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22482 /* 58001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22483 /* 58003 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22484 /* 58005 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22485 /* 58008 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22486 /* 58010 */ GIR_RootConstrainSelectedInstOperands,
22487 /* 58011 */ // GIR_Coverage, 1672,
22488 /* 58011 */ GIR_EraseRootFromParent_Done,
22489 /* 58012 */ // Label 1396: @58012
22490 /* 58012 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(58110), // Rule ID 1676 //
22491 /* 58017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22492 /* 58020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22493 /* 58023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22494 /* 58026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22495 /* 58029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22496 /* 58033 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22497 /* 58037 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22498 /* 58041 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22499 /* 58045 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22500 /* 58049 */ // MIs[1] Operand 1
22501 /* 58049 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22502 /* 58054 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22503 /* 58059 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22504 /* 58064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22505 /* 58068 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22506 /* 58072 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22507 /* 58074 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22508 /* 58074 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22509 /* 58077 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
22510 /* 58081 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22511 /* 58086 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22512 /* 58090 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22513 /* 58094 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22514 /* 58096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
22515 /* 58099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22516 /* 58101 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22517 /* 58103 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22518 /* 58106 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22519 /* 58108 */ GIR_RootConstrainSelectedInstOperands,
22520 /* 58109 */ // GIR_Coverage, 1676,
22521 /* 58109 */ GIR_EraseRootFromParent_Done,
22522 /* 58110 */ // Label 1397: @58110
22523 /* 58110 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(58208), // Rule ID 1681 //
22524 /* 58115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22525 /* 58118 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22526 /* 58121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22527 /* 58124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22528 /* 58127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22529 /* 58131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22530 /* 58135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22531 /* 58139 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22532 /* 58143 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22533 /* 58147 */ // MIs[1] Operand 1
22534 /* 58147 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22535 /* 58152 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22536 /* 58157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22537 /* 58162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22538 /* 58166 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22539 /* 58170 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22540 /* 58172 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22541 /* 58172 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22542 /* 58175 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
22543 /* 58179 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22544 /* 58184 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22545 /* 58188 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22546 /* 58192 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22547 /* 58194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
22548 /* 58197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22549 /* 58199 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22550 /* 58201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22551 /* 58204 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22552 /* 58206 */ GIR_RootConstrainSelectedInstOperands,
22553 /* 58207 */ // GIR_Coverage, 1681,
22554 /* 58207 */ GIR_EraseRootFromParent_Done,
22555 /* 58208 */ // Label 1398: @58208
22556 /* 58208 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(58306), // Rule ID 1687 //
22557 /* 58213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22558 /* 58216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22559 /* 58219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22560 /* 58222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22561 /* 58225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22562 /* 58229 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22563 /* 58233 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22564 /* 58237 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22565 /* 58241 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22566 /* 58245 */ // MIs[1] Operand 1
22567 /* 58245 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22568 /* 58250 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22569 /* 58255 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22570 /* 58260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22571 /* 58264 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22572 /* 58268 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22573 /* 58270 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22574 /* 58270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22575 /* 58273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
22576 /* 58277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22577 /* 58282 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22578 /* 58286 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22579 /* 58290 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22580 /* 58292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
22581 /* 58295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22582 /* 58297 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22583 /* 58299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22584 /* 58302 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22585 /* 58304 */ GIR_RootConstrainSelectedInstOperands,
22586 /* 58305 */ // GIR_Coverage, 1687,
22587 /* 58305 */ GIR_EraseRootFromParent_Done,
22588 /* 58306 */ // Label 1399: @58306
22589 /* 58306 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(58404), // Rule ID 1716 //
22590 /* 58311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22591 /* 58314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22592 /* 58317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22593 /* 58320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22594 /* 58323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22595 /* 58327 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22596 /* 58331 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22597 /* 58335 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22598 /* 58339 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22599 /* 58343 */ // MIs[1] Operand 1
22600 /* 58343 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22601 /* 58348 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22602 /* 58353 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22603 /* 58358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22604 /* 58362 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22605 /* 58366 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22606 /* 58368 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22607 /* 58368 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22608 /* 58371 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22609 /* 58375 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22610 /* 58380 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22611 /* 58384 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22612 /* 58388 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22613 /* 58390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
22614 /* 58393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22615 /* 58395 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22616 /* 58397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22617 /* 58400 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22618 /* 58402 */ GIR_RootConstrainSelectedInstOperands,
22619 /* 58403 */ // GIR_Coverage, 1716,
22620 /* 58403 */ GIR_EraseRootFromParent_Done,
22621 /* 58404 */ // Label 1400: @58404
22622 /* 58404 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(58502), // Rule ID 1717 //
22623 /* 58409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22624 /* 58412 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22625 /* 58415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22626 /* 58418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22627 /* 58421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22628 /* 58425 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22629 /* 58429 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22630 /* 58433 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22631 /* 58437 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22632 /* 58441 */ // MIs[1] Operand 1
22633 /* 58441 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22634 /* 58446 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22635 /* 58451 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22636 /* 58456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22637 /* 58460 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22638 /* 58464 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22639 /* 58466 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22640 /* 58466 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22641 /* 58469 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22642 /* 58473 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22643 /* 58478 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22644 /* 58482 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22645 /* 58486 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22646 /* 58488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
22647 /* 58491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22648 /* 58493 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22649 /* 58495 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22650 /* 58498 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22651 /* 58500 */ GIR_RootConstrainSelectedInstOperands,
22652 /* 58501 */ // GIR_Coverage, 1717,
22653 /* 58501 */ GIR_EraseRootFromParent_Done,
22654 /* 58502 */ // Label 1401: @58502
22655 /* 58502 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(58600), // Rule ID 1720 //
22656 /* 58507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22657 /* 58510 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22658 /* 58513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22659 /* 58516 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22660 /* 58519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22661 /* 58523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22662 /* 58527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22663 /* 58531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22664 /* 58535 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22665 /* 58539 */ // MIs[1] Operand 1
22666 /* 58539 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22667 /* 58544 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22668 /* 58549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22669 /* 58554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22670 /* 58558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22671 /* 58562 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22672 /* 58564 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
22673 /* 58564 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22674 /* 58567 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22675 /* 58571 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22676 /* 58576 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22677 /* 58580 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22678 /* 58584 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22679 /* 58586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
22680 /* 58589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22681 /* 58591 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22682 /* 58593 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22683 /* 58596 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22684 /* 58598 */ GIR_RootConstrainSelectedInstOperands,
22685 /* 58599 */ // GIR_Coverage, 1720,
22686 /* 58599 */ GIR_EraseRootFromParent_Done,
22687 /* 58600 */ // Label 1402: @58600
22688 /* 58600 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(58698), // Rule ID 1721 //
22689 /* 58605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22690 /* 58608 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22691 /* 58611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22692 /* 58614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22693 /* 58617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22694 /* 58621 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22695 /* 58625 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22696 /* 58629 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22697 /* 58633 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22698 /* 58637 */ // MIs[1] Operand 1
22699 /* 58637 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22700 /* 58642 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22701 /* 58647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22702 /* 58652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22703 /* 58656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22704 /* 58660 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22705 /* 58662 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
22706 /* 58662 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22707 /* 58665 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22708 /* 58669 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22709 /* 58674 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22710 /* 58678 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22711 /* 58682 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22712 /* 58684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
22713 /* 58687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22714 /* 58689 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22715 /* 58691 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22716 /* 58694 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22717 /* 58696 */ GIR_RootConstrainSelectedInstOperands,
22718 /* 58697 */ // GIR_Coverage, 1721,
22719 /* 58697 */ GIR_EraseRootFromParent_Done,
22720 /* 58698 */ // Label 1403: @58698
22721 /* 58698 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(58796), // Rule ID 1724 //
22722 /* 58703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22723 /* 58706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22724 /* 58709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22725 /* 58712 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22726 /* 58715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22727 /* 58719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22728 /* 58723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22729 /* 58727 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22730 /* 58731 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22731 /* 58735 */ // MIs[1] Operand 1
22732 /* 58735 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22733 /* 58740 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22734 /* 58745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22735 /* 58750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22736 /* 58754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22737 /* 58758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22738 /* 58760 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22739 /* 58760 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22740 /* 58763 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
22741 /* 58767 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22742 /* 58772 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22743 /* 58776 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22744 /* 58780 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22745 /* 58782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
22746 /* 58785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22747 /* 58787 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22748 /* 58789 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22749 /* 58792 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22750 /* 58794 */ GIR_RootConstrainSelectedInstOperands,
22751 /* 58795 */ // GIR_Coverage, 1724,
22752 /* 58795 */ GIR_EraseRootFromParent_Done,
22753 /* 58796 */ // Label 1404: @58796
22754 /* 58796 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(58894), // Rule ID 1726 //
22755 /* 58801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22756 /* 58804 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22757 /* 58807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22758 /* 58810 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22759 /* 58813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22760 /* 58817 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22761 /* 58821 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22762 /* 58825 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22763 /* 58829 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22764 /* 58833 */ // MIs[1] Operand 1
22765 /* 58833 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22766 /* 58838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22767 /* 58843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22768 /* 58848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22769 /* 58852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22770 /* 58856 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22771 /* 58858 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22772 /* 58858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22773 /* 58861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
22774 /* 58865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22775 /* 58870 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22776 /* 58874 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22777 /* 58878 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22778 /* 58880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
22779 /* 58883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22780 /* 58885 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22781 /* 58887 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22782 /* 58890 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22783 /* 58892 */ GIR_RootConstrainSelectedInstOperands,
22784 /* 58893 */ // GIR_Coverage, 1726,
22785 /* 58893 */ GIR_EraseRootFromParent_Done,
22786 /* 58894 */ // Label 1405: @58894
22787 /* 58894 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(58992), // Rule ID 1729 //
22788 /* 58899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22789 /* 58902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22790 /* 58905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22791 /* 58908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22792 /* 58911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22793 /* 58915 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22794 /* 58919 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22795 /* 58923 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22796 /* 58927 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22797 /* 58931 */ // MIs[1] Operand 1
22798 /* 58931 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22799 /* 58936 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22800 /* 58941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22801 /* 58946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22802 /* 58950 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22803 /* 58954 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22804 /* 58956 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
22805 /* 58956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22806 /* 58959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22807 /* 58963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22808 /* 58968 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22809 /* 58972 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22810 /* 58976 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22811 /* 58978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22812 /* 58981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22813 /* 58983 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22814 /* 58985 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22815 /* 58988 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22816 /* 58990 */ GIR_RootConstrainSelectedInstOperands,
22817 /* 58991 */ // GIR_Coverage, 1729,
22818 /* 58991 */ GIR_EraseRootFromParent_Done,
22819 /* 58992 */ // Label 1406: @58992
22820 /* 58992 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(59090), // Rule ID 1730 //
22821 /* 58997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22822 /* 59000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22823 /* 59003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22824 /* 59006 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22825 /* 59009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22826 /* 59013 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22827 /* 59017 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22828 /* 59021 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22829 /* 59025 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22830 /* 59029 */ // MIs[1] Operand 1
22831 /* 59029 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22832 /* 59034 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22833 /* 59039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22834 /* 59044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22835 /* 59048 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22836 /* 59052 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22837 /* 59054 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
22838 /* 59054 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22839 /* 59057 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22840 /* 59061 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22841 /* 59066 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22842 /* 59070 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22843 /* 59074 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22844 /* 59076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22845 /* 59079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22846 /* 59081 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22847 /* 59083 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22848 /* 59086 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22849 /* 59088 */ GIR_RootConstrainSelectedInstOperands,
22850 /* 59089 */ // GIR_Coverage, 1730,
22851 /* 59089 */ GIR_EraseRootFromParent_Done,
22852 /* 59090 */ // Label 1407: @59090
22853 /* 59090 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(59188), // Rule ID 1733 //
22854 /* 59095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22855 /* 59098 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22856 /* 59101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22857 /* 59104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22858 /* 59107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22859 /* 59111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22860 /* 59115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22861 /* 59119 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22862 /* 59123 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22863 /* 59127 */ // MIs[1] Operand 1
22864 /* 59127 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22865 /* 59132 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22866 /* 59137 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22867 /* 59142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22868 /* 59146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22869 /* 59150 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22870 /* 59152 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
22871 /* 59152 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22872 /* 59155 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22873 /* 59159 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22874 /* 59164 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22875 /* 59168 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22876 /* 59172 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22877 /* 59174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22878 /* 59177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22879 /* 59179 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22880 /* 59181 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22881 /* 59184 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22882 /* 59186 */ GIR_RootConstrainSelectedInstOperands,
22883 /* 59187 */ // GIR_Coverage, 1733,
22884 /* 59187 */ GIR_EraseRootFromParent_Done,
22885 /* 59188 */ // Label 1408: @59188
22886 /* 59188 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(59286), // Rule ID 1734 //
22887 /* 59193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22888 /* 59196 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22889 /* 59199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22890 /* 59202 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22891 /* 59205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22892 /* 59209 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22893 /* 59213 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22894 /* 59217 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22895 /* 59221 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22896 /* 59225 */ // MIs[1] Operand 1
22897 /* 59225 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22898 /* 59230 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22899 /* 59235 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22900 /* 59240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22901 /* 59244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22902 /* 59248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22903 /* 59250 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
22904 /* 59250 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22905 /* 59253 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22906 /* 59257 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22907 /* 59262 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22908 /* 59266 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22909 /* 59270 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22910 /* 59272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22911 /* 59275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22912 /* 59277 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22913 /* 59279 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22914 /* 59282 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22915 /* 59284 */ GIR_RootConstrainSelectedInstOperands,
22916 /* 59285 */ // GIR_Coverage, 1734,
22917 /* 59285 */ GIR_EraseRootFromParent_Done,
22918 /* 59286 */ // Label 1409: @59286
22919 /* 59286 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(59384), // Rule ID 1737 //
22920 /* 59291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22921 /* 59294 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22922 /* 59297 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22923 /* 59300 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22924 /* 59303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22925 /* 59307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22926 /* 59311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22927 /* 59315 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22928 /* 59319 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22929 /* 59323 */ // MIs[1] Operand 1
22930 /* 59323 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22931 /* 59328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22932 /* 59333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22933 /* 59338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22934 /* 59342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22935 /* 59346 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22936 /* 59348 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
22937 /* 59348 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22938 /* 59351 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
22939 /* 59355 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22940 /* 59360 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22941 /* 59364 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22942 /* 59368 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22943 /* 59370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22944 /* 59373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22945 /* 59375 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22946 /* 59377 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22947 /* 59380 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22948 /* 59382 */ GIR_RootConstrainSelectedInstOperands,
22949 /* 59383 */ // GIR_Coverage, 1737,
22950 /* 59383 */ GIR_EraseRootFromParent_Done,
22951 /* 59384 */ // Label 1410: @59384
22952 /* 59384 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(59482), // Rule ID 1738 //
22953 /* 59389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22954 /* 59392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22955 /* 59395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22956 /* 59398 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22957 /* 59401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22958 /* 59405 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22959 /* 59409 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22960 /* 59413 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22961 /* 59417 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22962 /* 59421 */ // MIs[1] Operand 1
22963 /* 59421 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22964 /* 59426 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22965 /* 59431 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22966 /* 59436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22967 /* 59440 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22968 /* 59444 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22969 /* 59446 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
22970 /* 59446 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22971 /* 59449 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
22972 /* 59453 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22973 /* 59458 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22974 /* 59462 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22975 /* 59466 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22976 /* 59468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22977 /* 59471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22978 /* 59473 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22979 /* 59475 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22980 /* 59478 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22981 /* 59480 */ GIR_RootConstrainSelectedInstOperands,
22982 /* 59481 */ // GIR_Coverage, 1738,
22983 /* 59481 */ GIR_EraseRootFromParent_Done,
22984 /* 59482 */ // Label 1411: @59482
22985 /* 59482 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(59580), // Rule ID 1741 //
22986 /* 59487 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22987 /* 59490 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22988 /* 59493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22989 /* 59496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22990 /* 59499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22991 /* 59503 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22992 /* 59507 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22993 /* 59511 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22994 /* 59515 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22995 /* 59519 */ // MIs[1] Operand 1
22996 /* 59519 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22997 /* 59524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22998 /* 59529 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22999 /* 59534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23000 /* 59538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23001 /* 59542 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23002 /* 59544 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
23003 /* 59544 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23004 /* 59547 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
23005 /* 59551 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23006 /* 59556 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23007 /* 59560 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23008 /* 59564 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23009 /* 59566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23010 /* 59569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23011 /* 59571 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23012 /* 59573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23013 /* 59576 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23014 /* 59578 */ GIR_RootConstrainSelectedInstOperands,
23015 /* 59579 */ // GIR_Coverage, 1741,
23016 /* 59579 */ GIR_EraseRootFromParent_Done,
23017 /* 59580 */ // Label 1412: @59580
23018 /* 59580 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(59678), // Rule ID 1742 //
23019 /* 59585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23020 /* 59588 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23021 /* 59591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23022 /* 59594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23023 /* 59597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23024 /* 59601 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23025 /* 59605 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23026 /* 59609 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23027 /* 59613 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23028 /* 59617 */ // MIs[1] Operand 1
23029 /* 59617 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23030 /* 59622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23031 /* 59627 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23032 /* 59632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23033 /* 59636 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23034 /* 59640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23035 /* 59642 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
23036 /* 59642 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23037 /* 59645 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
23038 /* 59649 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23039 /* 59654 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23040 /* 59658 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23041 /* 59662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23042 /* 59664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23043 /* 59667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23044 /* 59669 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23045 /* 59671 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23046 /* 59674 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23047 /* 59676 */ GIR_RootConstrainSelectedInstOperands,
23048 /* 59677 */ // GIR_Coverage, 1742,
23049 /* 59677 */ GIR_EraseRootFromParent_Done,
23050 /* 59678 */ // Label 1413: @59678
23051 /* 59678 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(59776), // Rule ID 1745 //
23052 /* 59683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23053 /* 59686 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23054 /* 59689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23055 /* 59692 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23056 /* 59695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23057 /* 59699 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23058 /* 59703 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23059 /* 59707 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23060 /* 59711 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23061 /* 59715 */ // MIs[1] Operand 1
23062 /* 59715 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23063 /* 59720 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23064 /* 59725 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23065 /* 59730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23066 /* 59734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23067 /* 59738 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23068 /* 59740 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23069 /* 59740 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23070 /* 59743 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23071 /* 59747 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23072 /* 59752 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23073 /* 59756 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23074 /* 59760 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23075 /* 59762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23076 /* 59765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23077 /* 59767 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23078 /* 59769 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23079 /* 59772 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23080 /* 59774 */ GIR_RootConstrainSelectedInstOperands,
23081 /* 59775 */ // GIR_Coverage, 1745,
23082 /* 59775 */ GIR_EraseRootFromParent_Done,
23083 /* 59776 */ // Label 1414: @59776
23084 /* 59776 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(59874), // Rule ID 1747 //
23085 /* 59781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23086 /* 59784 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23087 /* 59787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23088 /* 59790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23089 /* 59793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23090 /* 59797 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23091 /* 59801 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23092 /* 59805 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23093 /* 59809 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23094 /* 59813 */ // MIs[1] Operand 1
23095 /* 59813 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23096 /* 59818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23097 /* 59823 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23098 /* 59828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23099 /* 59832 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23100 /* 59836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23101 /* 59838 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23102 /* 59838 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23103 /* 59841 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
23104 /* 59845 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23105 /* 59850 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23106 /* 59854 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23107 /* 59858 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23108 /* 59860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
23109 /* 59863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23110 /* 59865 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23111 /* 59867 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23112 /* 59870 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23113 /* 59872 */ GIR_RootConstrainSelectedInstOperands,
23114 /* 59873 */ // GIR_Coverage, 1747,
23115 /* 59873 */ GIR_EraseRootFromParent_Done,
23116 /* 59874 */ // Label 1415: @59874
23117 /* 59874 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(59972), // Rule ID 1749 //
23118 /* 59879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23119 /* 59882 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23120 /* 59885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23121 /* 59888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23122 /* 59891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23123 /* 59895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23124 /* 59899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23125 /* 59903 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23126 /* 59907 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23127 /* 59911 */ // MIs[1] Operand 1
23128 /* 59911 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23129 /* 59916 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23130 /* 59921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23131 /* 59926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23132 /* 59930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23133 /* 59934 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23134 /* 59936 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23135 /* 59936 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23136 /* 59939 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23137 /* 59943 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23138 /* 59948 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23139 /* 59952 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23140 /* 59956 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23141 /* 59958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
23142 /* 59961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23143 /* 59963 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23144 /* 59965 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23145 /* 59968 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23146 /* 59970 */ GIR_RootConstrainSelectedInstOperands,
23147 /* 59971 */ // GIR_Coverage, 1749,
23148 /* 59971 */ GIR_EraseRootFromParent_Done,
23149 /* 59972 */ // Label 1416: @59972
23150 /* 59972 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(60070), // Rule ID 1752 //
23151 /* 59977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23152 /* 59980 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23153 /* 59983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23154 /* 59986 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23155 /* 59989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23156 /* 59993 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23157 /* 59997 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23158 /* 60001 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23159 /* 60005 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23160 /* 60009 */ // MIs[1] Operand 1
23161 /* 60009 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23162 /* 60014 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23163 /* 60019 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23164 /* 60024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23165 /* 60028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23166 /* 60032 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23167 /* 60034 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23168 /* 60034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23169 /* 60037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
23170 /* 60041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23171 /* 60046 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23172 /* 60050 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23173 /* 60054 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23174 /* 60056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
23175 /* 60059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23176 /* 60061 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23177 /* 60063 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23178 /* 60066 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23179 /* 60068 */ GIR_RootConstrainSelectedInstOperands,
23180 /* 60069 */ // GIR_Coverage, 1752,
23181 /* 60069 */ GIR_EraseRootFromParent_Done,
23182 /* 60070 */ // Label 1417: @60070
23183 /* 60070 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(60168), // Rule ID 2281 //
23184 /* 60075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23185 /* 60078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23186 /* 60081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23187 /* 60084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23188 /* 60087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23189 /* 60091 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23190 /* 60095 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23191 /* 60099 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23192 /* 60103 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23193 /* 60107 */ // MIs[1] Operand 1
23194 /* 60107 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23195 /* 60112 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23196 /* 60117 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23197 /* 60122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23198 /* 60126 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23199 /* 60130 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23200 /* 60132 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23201 /* 60132 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23202 /* 60135 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
23203 /* 60139 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23204 /* 60144 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23205 /* 60148 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23206 /* 60152 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23207 /* 60154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23208 /* 60157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23209 /* 60159 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23210 /* 60161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23211 /* 60164 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23212 /* 60166 */ GIR_RootConstrainSelectedInstOperands,
23213 /* 60167 */ // GIR_Coverage, 2281,
23214 /* 60167 */ GIR_EraseRootFromParent_Done,
23215 /* 60168 */ // Label 1418: @60168
23216 /* 60168 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(60266), // Rule ID 2282 //
23217 /* 60173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23218 /* 60176 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23219 /* 60179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23220 /* 60182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23221 /* 60185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23222 /* 60189 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23223 /* 60193 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23224 /* 60197 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23225 /* 60201 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23226 /* 60205 */ // MIs[1] Operand 1
23227 /* 60205 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23228 /* 60210 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23229 /* 60215 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23230 /* 60220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23231 /* 60224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23232 /* 60228 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23233 /* 60230 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23234 /* 60230 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23235 /* 60233 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
23236 /* 60237 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23237 /* 60242 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23238 /* 60246 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23239 /* 60250 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23240 /* 60252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23241 /* 60255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23242 /* 60257 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23243 /* 60259 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23244 /* 60262 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23245 /* 60264 */ GIR_RootConstrainSelectedInstOperands,
23246 /* 60265 */ // GIR_Coverage, 2282,
23247 /* 60265 */ GIR_EraseRootFromParent_Done,
23248 /* 60266 */ // Label 1419: @60266
23249 /* 60266 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(60364), // Rule ID 2285 //
23250 /* 60271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23251 /* 60274 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23252 /* 60277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23253 /* 60280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23254 /* 60283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23255 /* 60287 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23256 /* 60291 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23257 /* 60295 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23258 /* 60299 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23259 /* 60303 */ // MIs[1] Operand 1
23260 /* 60303 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23261 /* 60308 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23262 /* 60313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23263 /* 60318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23264 /* 60322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23265 /* 60326 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23266 /* 60328 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23267 /* 60328 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23268 /* 60331 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
23269 /* 60335 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23270 /* 60340 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23271 /* 60344 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23272 /* 60348 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23273 /* 60350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23274 /* 60353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23275 /* 60355 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23276 /* 60357 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23277 /* 60360 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23278 /* 60362 */ GIR_RootConstrainSelectedInstOperands,
23279 /* 60363 */ // GIR_Coverage, 2285,
23280 /* 60363 */ GIR_EraseRootFromParent_Done,
23281 /* 60364 */ // Label 1420: @60364
23282 /* 60364 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(60462), // Rule ID 2286 //
23283 /* 60369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23284 /* 60372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23285 /* 60375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23286 /* 60378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23287 /* 60381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23288 /* 60385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23289 /* 60389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23290 /* 60393 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23291 /* 60397 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23292 /* 60401 */ // MIs[1] Operand 1
23293 /* 60401 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23294 /* 60406 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23295 /* 60411 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23296 /* 60416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23297 /* 60420 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23298 /* 60424 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23299 /* 60426 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23300 /* 60426 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23301 /* 60429 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
23302 /* 60433 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23303 /* 60438 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23304 /* 60442 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23305 /* 60446 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23306 /* 60448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23307 /* 60451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23308 /* 60453 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23309 /* 60455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23310 /* 60458 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23311 /* 60460 */ GIR_RootConstrainSelectedInstOperands,
23312 /* 60461 */ // GIR_Coverage, 2286,
23313 /* 60461 */ GIR_EraseRootFromParent_Done,
23314 /* 60462 */ // Label 1421: @60462
23315 /* 60462 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(60560), // Rule ID 2289 //
23316 /* 60467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23317 /* 60470 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23318 /* 60473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23319 /* 60476 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23320 /* 60479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23321 /* 60483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23322 /* 60487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23323 /* 60491 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23324 /* 60495 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23325 /* 60499 */ // MIs[1] Operand 1
23326 /* 60499 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23327 /* 60504 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23328 /* 60509 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23329 /* 60514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23330 /* 60518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23331 /* 60522 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23332 /* 60524 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23333 /* 60524 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23334 /* 60527 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
23335 /* 60531 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23336 /* 60536 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23337 /* 60540 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23338 /* 60544 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23339 /* 60546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23340 /* 60549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23341 /* 60551 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23342 /* 60553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23343 /* 60556 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23344 /* 60558 */ GIR_RootConstrainSelectedInstOperands,
23345 /* 60559 */ // GIR_Coverage, 2289,
23346 /* 60559 */ GIR_EraseRootFromParent_Done,
23347 /* 60560 */ // Label 1422: @60560
23348 /* 60560 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(60658), // Rule ID 2291 //
23349 /* 60565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23350 /* 60568 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23351 /* 60571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23352 /* 60574 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23353 /* 60577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23354 /* 60581 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23355 /* 60585 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23356 /* 60589 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23357 /* 60593 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23358 /* 60597 */ // MIs[1] Operand 1
23359 /* 60597 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23360 /* 60602 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23361 /* 60607 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23362 /* 60612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23363 /* 60616 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23364 /* 60620 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23365 /* 60622 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23366 /* 60622 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23367 /* 60625 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
23368 /* 60629 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23369 /* 60634 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23370 /* 60638 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23371 /* 60642 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23372 /* 60644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
23373 /* 60647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23374 /* 60649 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23375 /* 60651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23376 /* 60654 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23377 /* 60656 */ GIR_RootConstrainSelectedInstOperands,
23378 /* 60657 */ // GIR_Coverage, 2291,
23379 /* 60657 */ GIR_EraseRootFromParent_Done,
23380 /* 60658 */ // Label 1423: @60658
23381 /* 60658 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(60698), // Rule ID 296 //
23382 /* 60663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
23383 /* 60666 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23384 /* 60669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23385 /* 60672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23386 /* 60675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23387 /* 60679 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23388 /* 60683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23389 /* 60687 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23390 /* 60691 */ // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
23391 /* 60691 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I64),
23392 /* 60696 */ GIR_RootConstrainSelectedInstOperands,
23393 /* 60697 */ // GIR_Coverage, 296,
23394 /* 60697 */ GIR_Done,
23395 /* 60698 */ // Label 1424: @60698
23396 /* 60698 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(60738), // Rule ID 298 //
23397 /* 60703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotMips4_32),
23398 /* 60706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23399 /* 60709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23400 /* 60712 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23401 /* 60715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23402 /* 60719 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23403 /* 60723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23404 /* 60727 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23405 /* 60731 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
23406 /* 60731 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D32),
23407 /* 60736 */ GIR_RootConstrainSelectedInstOperands,
23408 /* 60737 */ // GIR_Coverage, 298,
23409 /* 60737 */ GIR_Done,
23410 /* 60738 */ // Label 1425: @60738
23411 /* 60738 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(60778), // Rule ID 299 //
23412 /* 60743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotMips4_32),
23413 /* 60746 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23414 /* 60749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23415 /* 60752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23416 /* 60755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23417 /* 60759 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23418 /* 60763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23419 /* 60767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23420 /* 60771 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
23421 /* 60771 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D64),
23422 /* 60776 */ GIR_RootConstrainSelectedInstOperands,
23423 /* 60777 */ // GIR_Coverage, 299,
23424 /* 60777 */ GIR_Done,
23425 /* 60778 */ // Label 1426: @60778
23426 /* 60778 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(60824), // Rule ID 1682 //
23427 /* 60783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23428 /* 60786 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23429 /* 60789 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23430 /* 60792 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23431 /* 60795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23432 /* 60799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23433 /* 60803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23434 /* 60807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23435 /* 60811 */ // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
23436 /* 60811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
23437 /* 60814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23438 /* 60816 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23439 /* 60818 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23440 /* 60820 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23441 /* 60822 */ GIR_RootConstrainSelectedInstOperands,
23442 /* 60823 */ // GIR_Coverage, 1682,
23443 /* 60823 */ GIR_EraseRootFromParent_Done,
23444 /* 60824 */ // Label 1427: @60824
23445 /* 60824 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(60870), // Rule ID 1688 //
23446 /* 60829 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23447 /* 60832 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23448 /* 60835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23449 /* 60838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23450 /* 60841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23451 /* 60845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23452 /* 60849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23453 /* 60853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23454 /* 60857 */ // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
23455 /* 60857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
23456 /* 60860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23457 /* 60862 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23458 /* 60864 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23459 /* 60866 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23460 /* 60868 */ GIR_RootConstrainSelectedInstOperands,
23461 /* 60869 */ // GIR_Coverage, 1688,
23462 /* 60869 */ GIR_EraseRootFromParent_Done,
23463 /* 60870 */ // Label 1428: @60870
23464 /* 60870 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(60916), // Rule ID 1727 //
23465 /* 60875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23466 /* 60878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23467 /* 60881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23468 /* 60884 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23469 /* 60887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23470 /* 60891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23471 /* 60895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23472 /* 60899 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23473 /* 60903 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
23474 /* 60903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
23475 /* 60906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23476 /* 60908 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23477 /* 60910 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23478 /* 60912 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23479 /* 60914 */ GIR_RootConstrainSelectedInstOperands,
23480 /* 60915 */ // GIR_Coverage, 1727,
23481 /* 60915 */ GIR_EraseRootFromParent_Done,
23482 /* 60916 */ // Label 1429: @60916
23483 /* 60916 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(60962), // Rule ID 1750 //
23484 /* 60921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23485 /* 60924 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23486 /* 60927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23487 /* 60930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23488 /* 60933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23489 /* 60937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23490 /* 60941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23491 /* 60945 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23492 /* 60949 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
23493 /* 60949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
23494 /* 60952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23495 /* 60954 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23496 /* 60956 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23497 /* 60958 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23498 /* 60960 */ GIR_RootConstrainSelectedInstOperands,
23499 /* 60961 */ // GIR_Coverage, 1750,
23500 /* 60961 */ GIR_EraseRootFromParent_Done,
23501 /* 60962 */ // Label 1430: @60962
23502 /* 60962 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(61008), // Rule ID 1753 //
23503 /* 60967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23504 /* 60970 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23505 /* 60973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23506 /* 60976 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23507 /* 60979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23508 /* 60983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23509 /* 60987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23510 /* 60991 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23511 /* 60995 */ // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
23512 /* 60995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
23513 /* 60998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23514 /* 61000 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23515 /* 61002 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23516 /* 61004 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23517 /* 61006 */ GIR_RootConstrainSelectedInstOperands,
23518 /* 61007 */ // GIR_Coverage, 1753,
23519 /* 61007 */ GIR_EraseRootFromParent_Done,
23520 /* 61008 */ // Label 1431: @61008
23521 /* 61008 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(61054), // Rule ID 2292 //
23522 /* 61013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23523 /* 61016 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23524 /* 61019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23525 /* 61022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23526 /* 61025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23527 /* 61029 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23528 /* 61033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23529 /* 61037 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23530 /* 61041 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
23531 /* 61041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
23532 /* 61044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23533 /* 61046 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23534 /* 61048 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23535 /* 61050 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23536 /* 61052 */ GIR_RootConstrainSelectedInstOperands,
23537 /* 61053 */ // GIR_Coverage, 2292,
23538 /* 61053 */ GIR_EraseRootFromParent_Done,
23539 /* 61054 */ // Label 1432: @61054
23540 /* 61054 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(61132), // Rule ID 1798 //
23541 /* 61059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
23542 /* 61062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23543 /* 61065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23544 /* 61068 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23545 /* 61071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23546 /* 61075 */ // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
23547 /* 61075 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
23548 /* 61078 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
23549 /* 61082 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23550 /* 61087 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
23551 /* 61091 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
23552 /* 61095 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23553 /* 61097 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23554 /* 61100 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
23555 /* 61104 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23556 /* 61109 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
23557 /* 61113 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
23558 /* 61117 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23559 /* 61119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
23560 /* 61122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23561 /* 61124 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23562 /* 61127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
23563 /* 61130 */ GIR_RootConstrainSelectedInstOperands,
23564 /* 61131 */ // GIR_Coverage, 1798,
23565 /* 61131 */ GIR_EraseRootFromParent_Done,
23566 /* 61132 */ // Label 1433: @61132
23567 /* 61132 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(61244), // Rule ID 1809 //
23568 /* 61137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
23569 /* 61140 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23570 /* 61143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23571 /* 61146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23572 /* 61149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23573 /* 61153 */ // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
23574 /* 61153 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
23575 /* 61156 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
23576 /* 61160 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23577 /* 61165 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
23578 /* 61169 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
23579 /* 61171 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
23580 /* 61174 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
23581 /* 61178 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23582 /* 61183 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
23583 /* 61187 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
23584 /* 61190 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
23585 /* 61192 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
23586 /* 61195 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
23587 /* 61199 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23588 /* 61204 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
23589 /* 61208 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23590 /* 61210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23591 /* 61213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
23592 /* 61217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23593 /* 61222 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
23594 /* 61226 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23595 /* 61229 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23596 /* 61231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
23597 /* 61234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23598 /* 61236 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23599 /* 61239 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
23600 /* 61242 */ GIR_RootConstrainSelectedInstOperands,
23601 /* 61243 */ // GIR_Coverage, 1809,
23602 /* 61243 */ GIR_EraseRootFromParent_Done,
23603 /* 61244 */ // Label 1434: @61244
23604 /* 61244 */ GIM_Reject,
23605 /* 61245 */ // Label 1291: @61245
23606 /* 61245 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(61318),
23607 /* 61250 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23608 /* 61253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23609 /* 61256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23610 /* 61259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23611 /* 61263 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23612 /* 61267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23613 /* 61271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23614 /* 61275 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(61296), // Rule ID 583 //
23615 /* 61280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23616 /* 61283 */ // (vselect:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$wt, MSA128DOpnd:{ *:[v2i64] }:$ws) => (BSEL_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
23617 /* 61283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_D_PSEUDO),
23618 /* 61286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23619 /* 61288 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
23620 /* 61290 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
23621 /* 61292 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
23622 /* 61294 */ GIR_RootConstrainSelectedInstOperands,
23623 /* 61295 */ // GIR_Coverage, 583,
23624 /* 61295 */ GIR_EraseRootFromParent_Done,
23625 /* 61296 */ // Label 1436: @61296
23626 /* 61296 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(61317), // Rule ID 585 //
23627 /* 61301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23628 /* 61304 */ // (vselect:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$wt, MSA128DOpnd:{ *:[v2f64] }:$ws) => (BSEL_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23629 /* 61304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FD_PSEUDO),
23630 /* 61307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23631 /* 61309 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
23632 /* 61311 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
23633 /* 61313 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
23634 /* 61315 */ GIR_RootConstrainSelectedInstOperands,
23635 /* 61316 */ // GIR_Coverage, 585,
23636 /* 61316 */ GIR_EraseRootFromParent_Done,
23637 /* 61317 */ // Label 1437: @61317
23638 /* 61317 */ GIM_Reject,
23639 /* 61318 */ // Label 1435: @61318
23640 /* 61318 */ GIM_Reject,
23641 /* 61319 */ // Label 1292: @61319
23642 /* 61319 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(61392),
23643 /* 61324 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23644 /* 61327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23645 /* 61330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23646 /* 61333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23647 /* 61337 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23648 /* 61341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23649 /* 61345 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23650 /* 61349 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(61370), // Rule ID 582 //
23651 /* 61354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23652 /* 61357 */ // (vselect:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$wt, MSA128WOpnd:{ *:[v4i32] }:$ws) => (BSEL_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
23653 /* 61357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_W_PSEUDO),
23654 /* 61360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23655 /* 61362 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
23656 /* 61364 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
23657 /* 61366 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
23658 /* 61368 */ GIR_RootConstrainSelectedInstOperands,
23659 /* 61369 */ // GIR_Coverage, 582,
23660 /* 61369 */ GIR_EraseRootFromParent_Done,
23661 /* 61370 */ // Label 1439: @61370
23662 /* 61370 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(61391), // Rule ID 584 //
23663 /* 61375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23664 /* 61378 */ // (vselect:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$wt, MSA128WOpnd:{ *:[v4f32] }:$ws) => (BSEL_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23665 /* 61378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FW_PSEUDO),
23666 /* 61381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23667 /* 61383 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
23668 /* 61385 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
23669 /* 61387 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
23670 /* 61389 */ GIR_RootConstrainSelectedInstOperands,
23671 /* 61390 */ // GIR_Coverage, 584,
23672 /* 61390 */ GIR_EraseRootFromParent_Done,
23673 /* 61391 */ // Label 1440: @61391
23674 /* 61391 */ GIM_Reject,
23675 /* 61392 */ // Label 1438: @61392
23676 /* 61392 */ GIM_Reject,
23677 /* 61393 */ // Label 1293: @61393
23678 /* 61393 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(61439), // Rule ID 581 //
23679 /* 61398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23680 /* 61401 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23681 /* 61404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23682 /* 61407 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23683 /* 61410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
23684 /* 61414 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
23685 /* 61418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
23686 /* 61422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
23687 /* 61426 */ // (vselect:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$wt, MSA128HOpnd:{ *:[v8i16] }:$ws) => (BSEL_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
23688 /* 61426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_H_PSEUDO),
23689 /* 61429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23690 /* 61431 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
23691 /* 61433 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
23692 /* 61435 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
23693 /* 61437 */ GIR_RootConstrainSelectedInstOperands,
23694 /* 61438 */ // GIR_Coverage, 581,
23695 /* 61438 */ GIR_EraseRootFromParent_Done,
23696 /* 61439 */ // Label 1441: @61439
23697 /* 61439 */ GIM_Reject,
23698 /* 61440 */ // Label 1294: @61440
23699 /* 61440 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(61534),
23700 /* 61445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
23701 /* 61448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23702 /* 61451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23703 /* 61454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
23704 /* 61458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
23705 /* 61462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
23706 /* 61466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
23707 /* 61470 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(61491), // Rule ID 568 //
23708 /* 61475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23709 /* 61478 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (BMNZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23710 /* 61478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMNZ_V),
23711 /* 61481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23712 /* 61483 */ GIR_RootToRootCopy, /*OpIdx*/3, // wd_in
23713 /* 61485 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
23714 /* 61487 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
23715 /* 61489 */ GIR_RootConstrainSelectedInstOperands,
23716 /* 61490 */ // GIR_Coverage, 568,
23717 /* 61490 */ GIR_EraseRootFromParent_Done,
23718 /* 61491 */ // Label 1443: @61491
23719 /* 61491 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(61512), // Rule ID 570 //
23720 /* 61496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23721 /* 61499 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BMZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23722 /* 61499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMZ_V),
23723 /* 61502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23724 /* 61504 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
23725 /* 61506 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
23726 /* 61508 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
23727 /* 61510 */ GIR_RootConstrainSelectedInstOperands,
23728 /* 61511 */ // GIR_Coverage, 570,
23729 /* 61511 */ GIR_EraseRootFromParent_Done,
23730 /* 61512 */ // Label 1444: @61512
23731 /* 61512 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(61533), // Rule ID 580 //
23732 /* 61517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23733 /* 61520 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
23734 /* 61520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_V),
23735 /* 61523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23736 /* 61525 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
23737 /* 61527 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
23738 /* 61529 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
23739 /* 61531 */ GIR_RootConstrainSelectedInstOperands,
23740 /* 61532 */ // GIR_Coverage, 580,
23741 /* 61532 */ GIR_EraseRootFromParent_Done,
23742 /* 61533 */ // Label 1445: @61533
23743 /* 61533 */ GIM_Reject,
23744 /* 61534 */ // Label 1442: @61534
23745 /* 61534 */ GIM_Reject,
23746 /* 61535 */ // Label 1295: @61535
23747 /* 61535 */ GIM_Reject,
23748 /* 61536 */ // Label 44: @61536
23749 /* 61536 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1448*/ GIMT_Encode4(61644),
23750 /* 61547 */ /*GILLT_s32*//*Label 1446*/ GIMT_Encode4(61555),
23751 /* 61551 */ /*GILLT_s64*//*Label 1447*/ GIMT_Encode4(61610),
23752 /* 61555 */ // Label 1446: @61555
23753 /* 61555 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(61609),
23754 /* 61560 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23755 /* 61563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23756 /* 61566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23757 /* 61570 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23758 /* 61574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23759 /* 61578 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(61593), // Rule ID 331 //
23760 /* 61583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
23761 /* 61586 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
23762 /* 61586 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU),
23763 /* 61591 */ GIR_RootConstrainSelectedInstOperands,
23764 /* 61592 */ // GIR_Coverage, 331,
23765 /* 61592 */ GIR_Done,
23766 /* 61593 */ // Label 1450: @61593
23767 /* 61593 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(61608), // Rule ID 1181 //
23768 /* 61598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
23769 /* 61601 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
23770 /* 61601 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU_MMR6),
23771 /* 61606 */ GIR_RootConstrainSelectedInstOperands,
23772 /* 61607 */ // GIR_Coverage, 1181,
23773 /* 61607 */ GIR_Done,
23774 /* 61608 */ // Label 1451: @61608
23775 /* 61608 */ GIM_Reject,
23776 /* 61609 */ // Label 1449: @61609
23777 /* 61609 */ GIM_Reject,
23778 /* 61610 */ // Label 1447: @61610
23779 /* 61610 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(61643), // Rule ID 346 //
23780 /* 61615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
23781 /* 61618 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23782 /* 61621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23783 /* 61624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23784 /* 61628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23785 /* 61632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23786 /* 61636 */ // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
23787 /* 61636 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUHU),
23788 /* 61641 */ GIR_RootConstrainSelectedInstOperands,
23789 /* 61642 */ // GIR_Coverage, 346,
23790 /* 61642 */ GIR_Done,
23791 /* 61643 */ // Label 1452: @61643
23792 /* 61643 */ GIM_Reject,
23793 /* 61644 */ // Label 1448: @61644
23794 /* 61644 */ GIM_Reject,
23795 /* 61645 */ // Label 45: @61645
23796 /* 61645 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1455*/ GIMT_Encode4(61753),
23797 /* 61656 */ /*GILLT_s32*//*Label 1453*/ GIMT_Encode4(61664),
23798 /* 61660 */ /*GILLT_s64*//*Label 1454*/ GIMT_Encode4(61719),
23799 /* 61664 */ // Label 1453: @61664
23800 /* 61664 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(61718),
23801 /* 61669 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23802 /* 61672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23803 /* 61675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23804 /* 61679 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23805 /* 61683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23806 /* 61687 */ GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(61702), // Rule ID 330 //
23807 /* 61692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
23808 /* 61695 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
23809 /* 61695 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH),
23810 /* 61700 */ GIR_RootConstrainSelectedInstOperands,
23811 /* 61701 */ // GIR_Coverage, 330,
23812 /* 61701 */ GIR_Done,
23813 /* 61702 */ // Label 1457: @61702
23814 /* 61702 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(61717), // Rule ID 1180 //
23815 /* 61707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
23816 /* 61710 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
23817 /* 61710 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH_MMR6),
23818 /* 61715 */ GIR_RootConstrainSelectedInstOperands,
23819 /* 61716 */ // GIR_Coverage, 1180,
23820 /* 61716 */ GIR_Done,
23821 /* 61717 */ // Label 1458: @61717
23822 /* 61717 */ GIM_Reject,
23823 /* 61718 */ // Label 1456: @61718
23824 /* 61718 */ GIM_Reject,
23825 /* 61719 */ // Label 1454: @61719
23826 /* 61719 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(61752), // Rule ID 345 //
23827 /* 61724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
23828 /* 61727 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23829 /* 61730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23830 /* 61733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23831 /* 61737 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23832 /* 61741 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23833 /* 61745 */ // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
23834 /* 61745 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUH),
23835 /* 61750 */ GIR_RootConstrainSelectedInstOperands,
23836 /* 61751 */ // GIR_Coverage, 345,
23837 /* 61751 */ GIR_Done,
23838 /* 61752 */ // Label 1459: @61752
23839 /* 61752 */ GIM_Reject,
23840 /* 61753 */ // Label 1455: @61753
23841 /* 61753 */ GIM_Reject,
23842 /* 61754 */ // Label 46: @61754
23843 /* 61754 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1464*/ GIMT_Encode4(62666),
23844 /* 61765 */ /*GILLT_s32*//*Label 1460*/ GIMT_Encode4(61789),
23845 /* 61769 */ /*GILLT_s64*//*Label 1461*/ GIMT_Encode4(61993), GIMT_Encode4(0),
23846 /* 61777 */ /*GILLT_v2s64*//*Label 1462*/ GIMT_Encode4(62358), GIMT_Encode4(0),
23847 /* 61785 */ /*GILLT_v4s32*//*Label 1463*/ GIMT_Encode4(62512),
23848 /* 61789 */ // Label 1460: @61789
23849 /* 61789 */ GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(61992),
23850 /* 61794 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23851 /* 61797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23852 /* 61800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23853 /* 61804 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(61861), // Rule ID 163 //
23854 /* 61809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23855 /* 61812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23856 /* 61816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23857 /* 61820 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23858 /* 61824 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23859 /* 61828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23860 /* 61833 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23861 /* 61838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23862 /* 61842 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23863 /* 61844 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23864 /* 61844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
23865 /* 61847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23866 /* 61849 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23867 /* 61851 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23868 /* 61855 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23869 /* 61859 */ GIR_RootConstrainSelectedInstOperands,
23870 /* 61860 */ // GIR_Coverage, 163,
23871 /* 61860 */ GIR_EraseRootFromParent_Done,
23872 /* 61861 */ // Label 1466: @61861
23873 /* 61861 */ GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(61918), // Rule ID 2356 //
23874 /* 61866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23875 /* 61869 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23876 /* 61873 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23877 /* 61877 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23878 /* 61881 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23879 /* 61885 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23880 /* 61889 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23881 /* 61894 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23882 /* 61899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23883 /* 61901 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23884 /* 61901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
23885 /* 61904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23886 /* 61906 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
23887 /* 61908 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23888 /* 61912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23889 /* 61916 */ GIR_RootConstrainSelectedInstOperands,
23890 /* 61917 */ // GIR_Coverage, 2356,
23891 /* 61917 */ GIR_EraseRootFromParent_Done,
23892 /* 61918 */ // Label 1467: @61918
23893 /* 61918 */ GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(61941), // Rule ID 151 //
23894 /* 61923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
23895 /* 61926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23896 /* 61930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23897 /* 61934 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23898 /* 61934 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
23899 /* 61939 */ GIR_RootConstrainSelectedInstOperands,
23900 /* 61940 */ // GIR_Coverage, 151,
23901 /* 61940 */ GIR_Done,
23902 /* 61941 */ // Label 1468: @61941
23903 /* 61941 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(61964), // Rule ID 1130 //
23904 /* 61946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
23905 /* 61949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23906 /* 61953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23907 /* 61957 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23908 /* 61957 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MM),
23909 /* 61962 */ GIR_RootConstrainSelectedInstOperands,
23910 /* 61963 */ // GIR_Coverage, 1130,
23911 /* 61963 */ GIR_Done,
23912 /* 61964 */ // Label 1469: @61964
23913 /* 61964 */ GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(61991), // Rule ID 1188 //
23914 /* 61969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
23915 /* 61972 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23916 /* 61976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23917 /* 61980 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23918 /* 61980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MMR6),
23919 /* 61983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23920 /* 61985 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23921 /* 61987 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
23922 /* 61989 */ GIR_RootConstrainSelectedInstOperands,
23923 /* 61990 */ // GIR_Coverage, 1188,
23924 /* 61990 */ GIR_EraseRootFromParent_Done,
23925 /* 61991 */ // Label 1470: @61991
23926 /* 61991 */ GIM_Reject,
23927 /* 61992 */ // Label 1465: @61992
23928 /* 61992 */ GIM_Reject,
23929 /* 61993 */ // Label 1461: @61993
23930 /* 61993 */ GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(62357),
23931 /* 61998 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23932 /* 62001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23933 /* 62004 */ GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(62065), // Rule ID 165 //
23934 /* 62009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23935 /* 62012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23936 /* 62016 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23937 /* 62020 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23938 /* 62024 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23939 /* 62028 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23940 /* 62032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23941 /* 62037 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23942 /* 62042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23943 /* 62046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23944 /* 62048 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23945 /* 62048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
23946 /* 62051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23947 /* 62053 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23948 /* 62055 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23949 /* 62059 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23950 /* 62063 */ GIR_RootConstrainSelectedInstOperands,
23951 /* 62064 */ // GIR_Coverage, 165,
23952 /* 62064 */ GIR_EraseRootFromParent_Done,
23953 /* 62065 */ // Label 1472: @62065
23954 /* 62065 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(62126), // Rule ID 167 //
23955 /* 62070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23956 /* 62073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23957 /* 62077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23958 /* 62081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23959 /* 62085 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23960 /* 62089 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23961 /* 62093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23962 /* 62098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23963 /* 62103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23964 /* 62107 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23965 /* 62109 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23966 /* 62109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
23967 /* 62112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23968 /* 62114 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23969 /* 62116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23970 /* 62120 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23971 /* 62124 */ GIR_RootConstrainSelectedInstOperands,
23972 /* 62125 */ // GIR_Coverage, 167,
23973 /* 62125 */ GIR_EraseRootFromParent_Done,
23974 /* 62126 */ // Label 1473: @62126
23975 /* 62126 */ GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(62187), // Rule ID 2357 //
23976 /* 62131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23977 /* 62134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23978 /* 62138 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23979 /* 62142 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23980 /* 62146 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23981 /* 62150 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23982 /* 62154 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23983 /* 62158 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23984 /* 62163 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23985 /* 62168 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23986 /* 62170 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23987 /* 62170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
23988 /* 62173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23989 /* 62175 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
23990 /* 62177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23991 /* 62181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23992 /* 62185 */ GIR_RootConstrainSelectedInstOperands,
23993 /* 62186 */ // GIR_Coverage, 2357,
23994 /* 62186 */ GIR_EraseRootFromParent_Done,
23995 /* 62187 */ // Label 1474: @62187
23996 /* 62187 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(62248), // Rule ID 2358 //
23997 /* 62192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23998 /* 62195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23999 /* 62199 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24000 /* 62203 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24001 /* 62207 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24002 /* 62211 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24003 /* 62215 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24004 /* 62219 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24005 /* 62224 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24006 /* 62229 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24007 /* 62231 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24008 /* 62231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24009 /* 62234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24010 /* 62236 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24011 /* 62238 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24012 /* 62242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24013 /* 62246 */ GIR_RootConstrainSelectedInstOperands,
24014 /* 62247 */ // GIR_Coverage, 2358,
24015 /* 62247 */ GIR_EraseRootFromParent_Done,
24016 /* 62248 */ // Label 1475: @62248
24017 /* 62248 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(62275), // Rule ID 152 //
24018 /* 62253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24019 /* 62256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24020 /* 62260 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24021 /* 62264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24022 /* 62268 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24023 /* 62268 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
24024 /* 62273 */ GIR_RootConstrainSelectedInstOperands,
24025 /* 62274 */ // GIR_Coverage, 152,
24026 /* 62274 */ GIR_Done,
24027 /* 62275 */ // Label 1476: @62275
24028 /* 62275 */ GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(62302), // Rule ID 153 //
24029 /* 62280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
24030 /* 62283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24031 /* 62287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24032 /* 62291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24033 /* 62295 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24034 /* 62295 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
24035 /* 62300 */ GIR_RootConstrainSelectedInstOperands,
24036 /* 62301 */ // GIR_Coverage, 153,
24037 /* 62301 */ GIR_Done,
24038 /* 62302 */ // Label 1477: @62302
24039 /* 62302 */ GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(62329), // Rule ID 1134 //
24040 /* 62307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
24041 /* 62310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24042 /* 62314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24043 /* 62318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24044 /* 62322 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24045 /* 62322 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32_MM),
24046 /* 62327 */ GIR_RootConstrainSelectedInstOperands,
24047 /* 62328 */ // GIR_Coverage, 1134,
24048 /* 62328 */ GIR_Done,
24049 /* 62329 */ // Label 1478: @62329
24050 /* 62329 */ GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(62356), // Rule ID 1135 //
24051 /* 62334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
24052 /* 62337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24053 /* 62341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24054 /* 62345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24055 /* 62349 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24056 /* 62349 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64_MM),
24057 /* 62354 */ GIR_RootConstrainSelectedInstOperands,
24058 /* 62355 */ // GIR_Coverage, 1135,
24059 /* 62355 */ GIR_Done,
24060 /* 62356 */ // Label 1479: @62356
24061 /* 62356 */ GIM_Reject,
24062 /* 62357 */ // Label 1471: @62357
24063 /* 62357 */ GIM_Reject,
24064 /* 62358 */ // Label 1462: @62358
24065 /* 62358 */ GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(62511),
24066 /* 62363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24067 /* 62366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24068 /* 62369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24069 /* 62373 */ GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(62430), // Rule ID 2463 //
24070 /* 62378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24071 /* 62381 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24072 /* 62385 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24073 /* 62389 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24074 /* 62393 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
24075 /* 62397 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24076 /* 62402 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24077 /* 62407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24078 /* 62411 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24079 /* 62413 */ // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24080 /* 62413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
24081 /* 62416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24082 /* 62418 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
24083 /* 62420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24084 /* 62424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24085 /* 62428 */ GIR_RootConstrainSelectedInstOperands,
24086 /* 62429 */ // GIR_Coverage, 2463,
24087 /* 62429 */ GIR_EraseRootFromParent_Done,
24088 /* 62430 */ // Label 1481: @62430
24089 /* 62430 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(62487), // Rule ID 1993 //
24090 /* 62435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24091 /* 62438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24092 /* 62442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24093 /* 62446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24094 /* 62450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24095 /* 62454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
24096 /* 62458 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24097 /* 62463 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24098 /* 62468 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24099 /* 62470 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24100 /* 62470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
24101 /* 62473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24102 /* 62475 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
24103 /* 62477 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24104 /* 62481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24105 /* 62485 */ GIR_RootConstrainSelectedInstOperands,
24106 /* 62486 */ // GIR_Coverage, 1993,
24107 /* 62486 */ GIR_EraseRootFromParent_Done,
24108 /* 62487 */ // Label 1482: @62487
24109 /* 62487 */ GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(62510), // Rule ID 671 //
24110 /* 62492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24111 /* 62495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24112 /* 62499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24113 /* 62503 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24114 /* 62503 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D),
24115 /* 62508 */ GIR_RootConstrainSelectedInstOperands,
24116 /* 62509 */ // GIR_Coverage, 671,
24117 /* 62509 */ GIR_Done,
24118 /* 62510 */ // Label 1483: @62510
24119 /* 62510 */ GIM_Reject,
24120 /* 62511 */ // Label 1480: @62511
24121 /* 62511 */ GIM_Reject,
24122 /* 62512 */ // Label 1463: @62512
24123 /* 62512 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(62665),
24124 /* 62517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24125 /* 62520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24126 /* 62523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24127 /* 62527 */ GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(62584), // Rule ID 2462 //
24128 /* 62532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24129 /* 62535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24130 /* 62539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24131 /* 62543 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24132 /* 62547 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
24133 /* 62551 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24134 /* 62556 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24135 /* 62561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24136 /* 62565 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24137 /* 62567 */ // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24138 /* 62567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
24139 /* 62570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24140 /* 62572 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
24141 /* 62574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24142 /* 62578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24143 /* 62582 */ GIR_RootConstrainSelectedInstOperands,
24144 /* 62583 */ // GIR_Coverage, 2462,
24145 /* 62583 */ GIR_EraseRootFromParent_Done,
24146 /* 62584 */ // Label 1485: @62584
24147 /* 62584 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(62641), // Rule ID 1992 //
24148 /* 62589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24149 /* 62592 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24150 /* 62596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24151 /* 62600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24152 /* 62604 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24153 /* 62608 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
24154 /* 62612 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24155 /* 62617 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24156 /* 62622 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24157 /* 62624 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24158 /* 62624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
24159 /* 62627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24160 /* 62629 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
24161 /* 62631 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24162 /* 62635 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24163 /* 62639 */ GIR_RootConstrainSelectedInstOperands,
24164 /* 62640 */ // GIR_Coverage, 1992,
24165 /* 62640 */ GIR_EraseRootFromParent_Done,
24166 /* 62641 */ // Label 1486: @62641
24167 /* 62641 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(62664), // Rule ID 670 //
24168 /* 62646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24169 /* 62649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24170 /* 62653 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24171 /* 62657 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24172 /* 62657 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_W),
24173 /* 62662 */ GIR_RootConstrainSelectedInstOperands,
24174 /* 62663 */ // GIR_Coverage, 670,
24175 /* 62663 */ GIR_Done,
24176 /* 62664 */ // Label 1487: @62664
24177 /* 62664 */ GIM_Reject,
24178 /* 62665 */ // Label 1484: @62665
24179 /* 62665 */ GIM_Reject,
24180 /* 62666 */ // Label 1464: @62666
24181 /* 62666 */ GIM_Reject,
24182 /* 62667 */ // Label 47: @62667
24183 /* 62667 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1492*/ GIMT_Encode4(63278),
24184 /* 62678 */ /*GILLT_s32*//*Label 1488*/ GIMT_Encode4(62702),
24185 /* 62682 */ /*GILLT_s64*//*Label 1489*/ GIMT_Encode4(62849), GIMT_Encode4(0),
24186 /* 62690 */ /*GILLT_v2s64*//*Label 1490*/ GIMT_Encode4(63092), GIMT_Encode4(0),
24187 /* 62698 */ /*GILLT_v4s32*//*Label 1491*/ GIMT_Encode4(63185),
24188 /* 62702 */ // Label 1488: @62702
24189 /* 62702 */ GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(62848),
24190 /* 62707 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24191 /* 62710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24192 /* 62713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24193 /* 62717 */ GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(62774), // Rule ID 164 //
24194 /* 62722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24195 /* 62725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24196 /* 62729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24197 /* 62733 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24198 /* 62737 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24199 /* 62741 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24200 /* 62746 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24201 /* 62751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24202 /* 62755 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24203 /* 62757 */ // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24204 /* 62757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
24205 /* 62760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24206 /* 62762 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24207 /* 62764 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24208 /* 62768 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24209 /* 62772 */ GIR_RootConstrainSelectedInstOperands,
24210 /* 62773 */ // GIR_Coverage, 164,
24211 /* 62773 */ GIR_EraseRootFromParent_Done,
24212 /* 62774 */ // Label 1494: @62774
24213 /* 62774 */ GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(62797), // Rule ID 160 //
24214 /* 62779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
24215 /* 62782 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24216 /* 62786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24217 /* 62790 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24218 /* 62790 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
24219 /* 62795 */ GIR_RootConstrainSelectedInstOperands,
24220 /* 62796 */ // GIR_Coverage, 160,
24221 /* 62796 */ GIR_Done,
24222 /* 62797 */ // Label 1495: @62797
24223 /* 62797 */ GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(62820), // Rule ID 1133 //
24224 /* 62802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
24225 /* 62805 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24226 /* 62809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24227 /* 62813 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24228 /* 62813 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MM),
24229 /* 62818 */ GIR_RootConstrainSelectedInstOperands,
24230 /* 62819 */ // GIR_Coverage, 1133,
24231 /* 62819 */ GIR_Done,
24232 /* 62820 */ // Label 1496: @62820
24233 /* 62820 */ GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(62847), // Rule ID 1189 //
24234 /* 62825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
24235 /* 62828 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24236 /* 62832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24237 /* 62836 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
24238 /* 62836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MMR6),
24239 /* 62839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24240 /* 62841 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
24241 /* 62843 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
24242 /* 62845 */ GIR_RootConstrainSelectedInstOperands,
24243 /* 62846 */ // GIR_Coverage, 1189,
24244 /* 62846 */ GIR_EraseRootFromParent_Done,
24245 /* 62847 */ // Label 1497: @62847
24246 /* 62847 */ GIM_Reject,
24247 /* 62848 */ // Label 1493: @62848
24248 /* 62848 */ GIM_Reject,
24249 /* 62849 */ // Label 1489: @62849
24250 /* 62849 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(63091),
24251 /* 62854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24252 /* 62857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24253 /* 62860 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(62921), // Rule ID 166 //
24254 /* 62865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24255 /* 62868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24256 /* 62872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24257 /* 62876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24258 /* 62880 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24259 /* 62884 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24260 /* 62888 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24261 /* 62893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24262 /* 62898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24263 /* 62902 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24264 /* 62904 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24265 /* 62904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
24266 /* 62907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24267 /* 62909 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24268 /* 62911 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24269 /* 62915 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24270 /* 62919 */ GIR_RootConstrainSelectedInstOperands,
24271 /* 62920 */ // GIR_Coverage, 166,
24272 /* 62920 */ GIR_EraseRootFromParent_Done,
24273 /* 62921 */ // Label 1499: @62921
24274 /* 62921 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(62982), // Rule ID 168 //
24275 /* 62926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24276 /* 62929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24277 /* 62933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24278 /* 62937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24279 /* 62941 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24280 /* 62945 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24281 /* 62949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24282 /* 62954 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24283 /* 62959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24284 /* 62963 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24285 /* 62965 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24286 /* 62965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
24287 /* 62968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24288 /* 62970 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24289 /* 62972 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24290 /* 62976 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24291 /* 62980 */ GIR_RootConstrainSelectedInstOperands,
24292 /* 62981 */ // GIR_Coverage, 168,
24293 /* 62981 */ GIR_EraseRootFromParent_Done,
24294 /* 62982 */ // Label 1500: @62982
24295 /* 62982 */ GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(63009), // Rule ID 161 //
24296 /* 62987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24297 /* 62990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24298 /* 62994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24299 /* 62998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24300 /* 63002 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24301 /* 63002 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
24302 /* 63007 */ GIR_RootConstrainSelectedInstOperands,
24303 /* 63008 */ // GIR_Coverage, 161,
24304 /* 63008 */ GIR_Done,
24305 /* 63009 */ // Label 1501: @63009
24306 /* 63009 */ GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(63036), // Rule ID 162 //
24307 /* 63014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
24308 /* 63017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24309 /* 63021 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24310 /* 63025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24311 /* 63029 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24312 /* 63029 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
24313 /* 63034 */ GIR_RootConstrainSelectedInstOperands,
24314 /* 63035 */ // GIR_Coverage, 162,
24315 /* 63035 */ GIR_Done,
24316 /* 63036 */ // Label 1502: @63036
24317 /* 63036 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(63063), // Rule ID 1140 //
24318 /* 63041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
24319 /* 63044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24320 /* 63048 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24321 /* 63052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24322 /* 63056 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24323 /* 63056 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32_MM),
24324 /* 63061 */ GIR_RootConstrainSelectedInstOperands,
24325 /* 63062 */ // GIR_Coverage, 1140,
24326 /* 63062 */ GIR_Done,
24327 /* 63063 */ // Label 1503: @63063
24328 /* 63063 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(63090), // Rule ID 1141 //
24329 /* 63068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
24330 /* 63071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24331 /* 63075 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24332 /* 63079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24333 /* 63083 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24334 /* 63083 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64_MM),
24335 /* 63088 */ GIR_RootConstrainSelectedInstOperands,
24336 /* 63089 */ // GIR_Coverage, 1141,
24337 /* 63089 */ GIR_Done,
24338 /* 63090 */ // Label 1504: @63090
24339 /* 63090 */ GIM_Reject,
24340 /* 63091 */ // Label 1498: @63091
24341 /* 63091 */ GIM_Reject,
24342 /* 63092 */ // Label 1490: @63092
24343 /* 63092 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(63184),
24344 /* 63097 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24345 /* 63100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24346 /* 63103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24347 /* 63107 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24348 /* 63111 */ GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(63164), // Rule ID 1991 //
24349 /* 63116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24350 /* 63119 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24351 /* 63123 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24352 /* 63127 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24353 /* 63131 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
24354 /* 63135 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24355 /* 63140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24356 /* 63145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24357 /* 63147 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24358 /* 63147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_D),
24359 /* 63150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24360 /* 63152 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
24361 /* 63154 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24362 /* 63158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24363 /* 63162 */ GIR_RootConstrainSelectedInstOperands,
24364 /* 63163 */ // GIR_Coverage, 1991,
24365 /* 63163 */ GIR_EraseRootFromParent_Done,
24366 /* 63164 */ // Label 1506: @63164
24367 /* 63164 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(63183), // Rule ID 759 //
24368 /* 63169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24369 /* 63172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24370 /* 63176 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24371 /* 63176 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D),
24372 /* 63181 */ GIR_RootConstrainSelectedInstOperands,
24373 /* 63182 */ // GIR_Coverage, 759,
24374 /* 63182 */ GIR_Done,
24375 /* 63183 */ // Label 1507: @63183
24376 /* 63183 */ GIM_Reject,
24377 /* 63184 */ // Label 1505: @63184
24378 /* 63184 */ GIM_Reject,
24379 /* 63185 */ // Label 1491: @63185
24380 /* 63185 */ GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(63277),
24381 /* 63190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24382 /* 63193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24383 /* 63196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24384 /* 63200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24385 /* 63204 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(63257), // Rule ID 1990 //
24386 /* 63209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24387 /* 63212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24388 /* 63216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24389 /* 63220 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24390 /* 63224 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
24391 /* 63228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24392 /* 63233 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24393 /* 63238 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24394 /* 63240 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24395 /* 63240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_W),
24396 /* 63243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24397 /* 63245 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
24398 /* 63247 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24399 /* 63251 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24400 /* 63255 */ GIR_RootConstrainSelectedInstOperands,
24401 /* 63256 */ // GIR_Coverage, 1990,
24402 /* 63256 */ GIR_EraseRootFromParent_Done,
24403 /* 63257 */ // Label 1509: @63257
24404 /* 63257 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(63276), // Rule ID 758 //
24405 /* 63262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24406 /* 63265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24407 /* 63269 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24408 /* 63269 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_W),
24409 /* 63274 */ GIR_RootConstrainSelectedInstOperands,
24410 /* 63275 */ // GIR_Coverage, 758,
24411 /* 63275 */ GIR_Done,
24412 /* 63276 */ // Label 1510: @63276
24413 /* 63276 */ GIM_Reject,
24414 /* 63277 */ // Label 1508: @63277
24415 /* 63277 */ GIM_Reject,
24416 /* 63278 */ // Label 1492: @63278
24417 /* 63278 */ GIM_Reject,
24418 /* 63279 */ // Label 48: @63279
24419 /* 63279 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1515*/ GIMT_Encode4(63765),
24420 /* 63290 */ /*GILLT_s32*//*Label 1511*/ GIMT_Encode4(63314),
24421 /* 63294 */ /*GILLT_s64*//*Label 1512*/ GIMT_Encode4(63388), GIMT_Encode4(0),
24422 /* 63302 */ /*GILLT_v2s64*//*Label 1513*/ GIMT_Encode4(63509), GIMT_Encode4(0),
24423 /* 63310 */ /*GILLT_v4s32*//*Label 1514*/ GIMT_Encode4(63637),
24424 /* 63314 */ // Label 1511: @63314
24425 /* 63314 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(63387),
24426 /* 63319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24427 /* 63322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24428 /* 63325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24429 /* 63329 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24430 /* 63333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24431 /* 63337 */ GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(63352), // Rule ID 157 //
24432 /* 63342 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
24433 /* 63345 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24434 /* 63345 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
24435 /* 63350 */ GIR_RootConstrainSelectedInstOperands,
24436 /* 63351 */ // GIR_Coverage, 157,
24437 /* 63351 */ GIR_Done,
24438 /* 63352 */ // Label 1517: @63352
24439 /* 63352 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(63367), // Rule ID 1132 //
24440 /* 63357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
24441 /* 63360 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24442 /* 63360 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MM),
24443 /* 63365 */ GIR_RootConstrainSelectedInstOperands,
24444 /* 63366 */ // GIR_Coverage, 1132,
24445 /* 63366 */ GIR_Done,
24446 /* 63367 */ // Label 1518: @63367
24447 /* 63367 */ GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(63386), // Rule ID 1190 //
24448 /* 63372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
24449 /* 63375 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
24450 /* 63375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MMR6),
24451 /* 63378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24452 /* 63380 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
24453 /* 63382 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
24454 /* 63384 */ GIR_RootConstrainSelectedInstOperands,
24455 /* 63385 */ // GIR_Coverage, 1190,
24456 /* 63385 */ GIR_EraseRootFromParent_Done,
24457 /* 63386 */ // Label 1519: @63386
24458 /* 63386 */ GIM_Reject,
24459 /* 63387 */ // Label 1516: @63387
24460 /* 63387 */ GIM_Reject,
24461 /* 63388 */ // Label 1512: @63388
24462 /* 63388 */ GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(63508),
24463 /* 63393 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24464 /* 63396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24465 /* 63399 */ GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(63426), // Rule ID 158 //
24466 /* 63404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24467 /* 63407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24468 /* 63411 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24469 /* 63415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24470 /* 63419 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24471 /* 63419 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
24472 /* 63424 */ GIR_RootConstrainSelectedInstOperands,
24473 /* 63425 */ // GIR_Coverage, 158,
24474 /* 63425 */ GIR_Done,
24475 /* 63426 */ // Label 1521: @63426
24476 /* 63426 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(63453), // Rule ID 159 //
24477 /* 63431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
24478 /* 63434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24479 /* 63438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24480 /* 63442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24481 /* 63446 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24482 /* 63446 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
24483 /* 63451 */ GIR_RootConstrainSelectedInstOperands,
24484 /* 63452 */ // GIR_Coverage, 159,
24485 /* 63452 */ GIR_Done,
24486 /* 63453 */ // Label 1522: @63453
24487 /* 63453 */ GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(63480), // Rule ID 1138 //
24488 /* 63458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
24489 /* 63461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24490 /* 63465 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24491 /* 63469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24492 /* 63473 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24493 /* 63473 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32_MM),
24494 /* 63478 */ GIR_RootConstrainSelectedInstOperands,
24495 /* 63479 */ // GIR_Coverage, 1138,
24496 /* 63479 */ GIR_Done,
24497 /* 63480 */ // Label 1523: @63480
24498 /* 63480 */ GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(63507), // Rule ID 1139 //
24499 /* 63485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
24500 /* 63488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24501 /* 63492 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24502 /* 63496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24503 /* 63500 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24504 /* 63500 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64_MM),
24505 /* 63505 */ GIR_RootConstrainSelectedInstOperands,
24506 /* 63506 */ // GIR_Coverage, 1139,
24507 /* 63506 */ GIR_Done,
24508 /* 63507 */ // Label 1524: @63507
24509 /* 63507 */ GIM_Reject,
24510 /* 63508 */ // Label 1520: @63508
24511 /* 63508 */ GIM_Reject,
24512 /* 63509 */ // Label 1513: @63509
24513 /* 63509 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(63636),
24514 /* 63514 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24515 /* 63517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24516 /* 63520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24517 /* 63524 */ GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(63568), // Rule ID 2399 //
24518 /* 63529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24519 /* 63532 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24520 /* 63536 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
24521 /* 63540 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24522 /* 63544 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24523 /* 63549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24524 /* 63553 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24525 /* 63555 */ // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24526 /* 63555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
24527 /* 63558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24528 /* 63560 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
24529 /* 63562 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
24530 /* 63566 */ GIR_RootConstrainSelectedInstOperands,
24531 /* 63567 */ // GIR_Coverage, 2399,
24532 /* 63567 */ GIR_EraseRootFromParent_Done,
24533 /* 63568 */ // Label 1526: @63568
24534 /* 63568 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(63612), // Rule ID 701 //
24535 /* 63573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24536 /* 63576 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24537 /* 63580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24538 /* 63584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
24539 /* 63588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24540 /* 63592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24541 /* 63597 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24542 /* 63599 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24543 /* 63599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
24544 /* 63602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24545 /* 63604 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
24546 /* 63606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
24547 /* 63610 */ GIR_RootConstrainSelectedInstOperands,
24548 /* 63611 */ // GIR_Coverage, 701,
24549 /* 63611 */ GIR_EraseRootFromParent_Done,
24550 /* 63612 */ // Label 1527: @63612
24551 /* 63612 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(63635), // Rule ID 737 //
24552 /* 63617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24553 /* 63620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24554 /* 63624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24555 /* 63628 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24556 /* 63628 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D),
24557 /* 63633 */ GIR_RootConstrainSelectedInstOperands,
24558 /* 63634 */ // GIR_Coverage, 737,
24559 /* 63634 */ GIR_Done,
24560 /* 63635 */ // Label 1528: @63635
24561 /* 63635 */ GIM_Reject,
24562 /* 63636 */ // Label 1525: @63636
24563 /* 63636 */ GIM_Reject,
24564 /* 63637 */ // Label 1514: @63637
24565 /* 63637 */ GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(63764),
24566 /* 63642 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24567 /* 63645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24568 /* 63648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24569 /* 63652 */ GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(63696), // Rule ID 2398 //
24570 /* 63657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24571 /* 63660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24572 /* 63664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
24573 /* 63668 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24574 /* 63672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24575 /* 63677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24576 /* 63681 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24577 /* 63683 */ // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24578 /* 63683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
24579 /* 63686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24580 /* 63688 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
24581 /* 63690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
24582 /* 63694 */ GIR_RootConstrainSelectedInstOperands,
24583 /* 63695 */ // GIR_Coverage, 2398,
24584 /* 63695 */ GIR_EraseRootFromParent_Done,
24585 /* 63696 */ // Label 1530: @63696
24586 /* 63696 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(63740), // Rule ID 700 //
24587 /* 63701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24588 /* 63704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24589 /* 63708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24590 /* 63712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
24591 /* 63716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24592 /* 63720 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24593 /* 63725 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24594 /* 63727 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24595 /* 63727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
24596 /* 63730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24597 /* 63732 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
24598 /* 63734 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
24599 /* 63738 */ GIR_RootConstrainSelectedInstOperands,
24600 /* 63739 */ // GIR_Coverage, 700,
24601 /* 63739 */ GIR_EraseRootFromParent_Done,
24602 /* 63740 */ // Label 1531: @63740
24603 /* 63740 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(63763), // Rule ID 736 //
24604 /* 63745 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24605 /* 63748 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24606 /* 63752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24607 /* 63756 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24608 /* 63756 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_W),
24609 /* 63761 */ GIR_RootConstrainSelectedInstOperands,
24610 /* 63762 */ // GIR_Coverage, 736,
24611 /* 63762 */ GIR_Done,
24612 /* 63763 */ // Label 1532: @63763
24613 /* 63763 */ GIM_Reject,
24614 /* 63764 */ // Label 1529: @63764
24615 /* 63764 */ GIM_Reject,
24616 /* 63765 */ // Label 1515: @63765
24617 /* 63765 */ GIM_Reject,
24618 /* 63766 */ // Label 49: @63766
24619 /* 63766 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1535*/ GIMT_Encode4(63871),
24620 /* 63777 */ /*GILLT_v2s64*//*Label 1533*/ GIMT_Encode4(63789), GIMT_Encode4(0),
24621 /* 63785 */ /*GILLT_v4s32*//*Label 1534*/ GIMT_Encode4(63830),
24622 /* 63789 */ // Label 1533: @63789
24623 /* 63789 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(63829), // Rule ID 725 //
24624 /* 63794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24625 /* 63797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24626 /* 63800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24627 /* 63803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24628 /* 63806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24629 /* 63810 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24630 /* 63814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24631 /* 63818 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24632 /* 63822 */ // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24633 /* 63822 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
24634 /* 63827 */ GIR_RootConstrainSelectedInstOperands,
24635 /* 63828 */ // GIR_Coverage, 725,
24636 /* 63828 */ GIR_Done,
24637 /* 63829 */ // Label 1536: @63829
24638 /* 63829 */ GIM_Reject,
24639 /* 63830 */ // Label 1534: @63830
24640 /* 63830 */ GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(63870), // Rule ID 724 //
24641 /* 63835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24642 /* 63838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24643 /* 63841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24644 /* 63844 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24645 /* 63847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24646 /* 63851 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24647 /* 63855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24648 /* 63859 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24649 /* 63863 */ // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24650 /* 63863 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
24651 /* 63868 */ GIR_RootConstrainSelectedInstOperands,
24652 /* 63869 */ // GIR_Coverage, 724,
24653 /* 63869 */ GIR_Done,
24654 /* 63870 */ // Label 1537: @63870
24655 /* 63870 */ GIM_Reject,
24656 /* 63871 */ // Label 1535: @63871
24657 /* 63871 */ GIM_Reject,
24658 /* 63872 */ // Label 50: @63872
24659 /* 63872 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1542*/ GIMT_Encode4(64170),
24660 /* 63883 */ /*GILLT_s32*//*Label 1538*/ GIMT_Encode4(63907),
24661 /* 63887 */ /*GILLT_s64*//*Label 1539*/ GIMT_Encode4(63981), GIMT_Encode4(0),
24662 /* 63895 */ /*GILLT_v2s64*//*Label 1540*/ GIMT_Encode4(64102), GIMT_Encode4(0),
24663 /* 63903 */ /*GILLT_v4s32*//*Label 1541*/ GIMT_Encode4(64136),
24664 /* 63907 */ // Label 1538: @63907
24665 /* 63907 */ GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(63980),
24666 /* 63912 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24667 /* 63915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24668 /* 63918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24669 /* 63922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24670 /* 63926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24671 /* 63930 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(63945), // Rule ID 154 //
24672 /* 63935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
24673 /* 63938 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24674 /* 63938 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
24675 /* 63943 */ GIR_RootConstrainSelectedInstOperands,
24676 /* 63944 */ // GIR_Coverage, 154,
24677 /* 63944 */ GIR_Done,
24678 /* 63945 */ // Label 1544: @63945
24679 /* 63945 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(63960), // Rule ID 1131 //
24680 /* 63950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
24681 /* 63953 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24682 /* 63953 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MM),
24683 /* 63958 */ GIR_RootConstrainSelectedInstOperands,
24684 /* 63959 */ // GIR_Coverage, 1131,
24685 /* 63959 */ GIR_Done,
24686 /* 63960 */ // Label 1545: @63960
24687 /* 63960 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(63979), // Rule ID 1191 //
24688 /* 63965 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
24689 /* 63968 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
24690 /* 63968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MMR6),
24691 /* 63971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24692 /* 63973 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
24693 /* 63975 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
24694 /* 63977 */ GIR_RootConstrainSelectedInstOperands,
24695 /* 63978 */ // GIR_Coverage, 1191,
24696 /* 63978 */ GIR_EraseRootFromParent_Done,
24697 /* 63979 */ // Label 1546: @63979
24698 /* 63979 */ GIM_Reject,
24699 /* 63980 */ // Label 1543: @63980
24700 /* 63980 */ GIM_Reject,
24701 /* 63981 */ // Label 1539: @63981
24702 /* 63981 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(64101),
24703 /* 63986 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24704 /* 63989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24705 /* 63992 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(64019), // Rule ID 155 //
24706 /* 63997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24707 /* 64000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24708 /* 64004 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24709 /* 64008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24710 /* 64012 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24711 /* 64012 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
24712 /* 64017 */ GIR_RootConstrainSelectedInstOperands,
24713 /* 64018 */ // GIR_Coverage, 155,
24714 /* 64018 */ GIR_Done,
24715 /* 64019 */ // Label 1548: @64019
24716 /* 64019 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(64046), // Rule ID 156 //
24717 /* 64024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
24718 /* 64027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24719 /* 64031 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24720 /* 64035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24721 /* 64039 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24722 /* 64039 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
24723 /* 64044 */ GIR_RootConstrainSelectedInstOperands,
24724 /* 64045 */ // GIR_Coverage, 156,
24725 /* 64045 */ GIR_Done,
24726 /* 64046 */ // Label 1549: @64046
24727 /* 64046 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(64073), // Rule ID 1136 //
24728 /* 64051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
24729 /* 64054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24730 /* 64058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24731 /* 64062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24732 /* 64066 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24733 /* 64066 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32_MM),
24734 /* 64071 */ GIR_RootConstrainSelectedInstOperands,
24735 /* 64072 */ // GIR_Coverage, 1136,
24736 /* 64072 */ GIR_Done,
24737 /* 64073 */ // Label 1550: @64073
24738 /* 64073 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(64100), // Rule ID 1137 //
24739 /* 64078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
24740 /* 64081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24741 /* 64085 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24742 /* 64089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24743 /* 64093 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24744 /* 64093 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64_MM),
24745 /* 64098 */ GIR_RootConstrainSelectedInstOperands,
24746 /* 64099 */ // GIR_Coverage, 1137,
24747 /* 64099 */ GIR_Done,
24748 /* 64100 */ // Label 1551: @64100
24749 /* 64100 */ GIM_Reject,
24750 /* 64101 */ // Label 1547: @64101
24751 /* 64101 */ GIM_Reject,
24752 /* 64102 */ // Label 1540: @64102
24753 /* 64102 */ GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(64135), // Rule ID 697 //
24754 /* 64107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24755 /* 64110 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24756 /* 64113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24757 /* 64116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24758 /* 64120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24759 /* 64124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24760 /* 64128 */ // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24761 /* 64128 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D),
24762 /* 64133 */ GIR_RootConstrainSelectedInstOperands,
24763 /* 64134 */ // GIR_Coverage, 697,
24764 /* 64134 */ GIR_Done,
24765 /* 64135 */ // Label 1552: @64135
24766 /* 64135 */ GIM_Reject,
24767 /* 64136 */ // Label 1541: @64136
24768 /* 64136 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(64169), // Rule ID 696 //
24769 /* 64141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24770 /* 64144 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24771 /* 64147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24772 /* 64150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24773 /* 64154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24774 /* 64158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24775 /* 64162 */ // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24776 /* 64162 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_W),
24777 /* 64167 */ GIR_RootConstrainSelectedInstOperands,
24778 /* 64168 */ // GIR_Coverage, 696,
24779 /* 64168 */ GIR_Done,
24780 /* 64169 */ // Label 1553: @64169
24781 /* 64169 */ GIM_Reject,
24782 /* 64170 */ // Label 1542: @64170
24783 /* 64170 */ GIM_Reject,
24784 /* 64171 */ // Label 51: @64171
24785 /* 64171 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1556*/ GIMT_Encode4(64248),
24786 /* 64182 */ /*GILLT_v2s64*//*Label 1554*/ GIMT_Encode4(64194), GIMT_Encode4(0),
24787 /* 64190 */ /*GILLT_v4s32*//*Label 1555*/ GIMT_Encode4(64221),
24788 /* 64194 */ // Label 1554: @64194
24789 /* 64194 */ GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(64220), // Rule ID 703 //
24790 /* 64199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24791 /* 64202 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24792 /* 64205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24793 /* 64209 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24794 /* 64213 */ // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
24795 /* 64213 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D_1_PSEUDO),
24796 /* 64218 */ GIR_RootConstrainSelectedInstOperands,
24797 /* 64219 */ // GIR_Coverage, 703,
24798 /* 64219 */ GIR_Done,
24799 /* 64220 */ // Label 1557: @64220
24800 /* 64220 */ GIM_Reject,
24801 /* 64221 */ // Label 1555: @64221
24802 /* 64221 */ GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(64247), // Rule ID 702 //
24803 /* 64226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24804 /* 64229 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24805 /* 64232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24806 /* 64236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24807 /* 64240 */ // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
24808 /* 64240 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W_1_PSEUDO),
24809 /* 64245 */ GIR_RootConstrainSelectedInstOperands,
24810 /* 64246 */ // GIR_Coverage, 702,
24811 /* 64246 */ GIR_Done,
24812 /* 64247 */ // Label 1558: @64247
24813 /* 64247 */ GIM_Reject,
24814 /* 64248 */ // Label 1556: @64248
24815 /* 64248 */ GIM_Reject,
24816 /* 64249 */ // Label 52: @64249
24817 /* 64249 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1561*/ GIMT_Encode4(64326),
24818 /* 64260 */ /*GILLT_v2s64*//*Label 1559*/ GIMT_Encode4(64272), GIMT_Encode4(0),
24819 /* 64268 */ /*GILLT_v4s32*//*Label 1560*/ GIMT_Encode4(64299),
24820 /* 64272 */ // Label 1559: @64272
24821 /* 64272 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(64298), // Rule ID 723 //
24822 /* 64277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24823 /* 64280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24824 /* 64283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24825 /* 64287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24826 /* 64291 */ // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24827 /* 64291 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_D),
24828 /* 64296 */ GIR_RootConstrainSelectedInstOperands,
24829 /* 64297 */ // GIR_Coverage, 723,
24830 /* 64297 */ GIR_Done,
24831 /* 64298 */ // Label 1562: @64298
24832 /* 64298 */ GIM_Reject,
24833 /* 64299 */ // Label 1560: @64299
24834 /* 64299 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(64325), // Rule ID 722 //
24835 /* 64304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24836 /* 64307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24837 /* 64310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24838 /* 64314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24839 /* 64318 */ // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24840 /* 64318 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_W),
24841 /* 64323 */ GIR_RootConstrainSelectedInstOperands,
24842 /* 64324 */ // GIR_Coverage, 722,
24843 /* 64324 */ GIR_Done,
24844 /* 64325 */ // Label 1563: @64325
24845 /* 64325 */ GIM_Reject,
24846 /* 64326 */ // Label 1561: @64326
24847 /* 64326 */ GIM_Reject,
24848 /* 64327 */ // Label 53: @64327
24849 /* 64327 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1566*/ GIMT_Encode4(65695),
24850 /* 64338 */ /*GILLT_s32*//*Label 1564*/ GIMT_Encode4(64346),
24851 /* 64342 */ /*GILLT_s64*//*Label 1565*/ GIMT_Encode4(64873),
24852 /* 64346 */ // Label 1564: @64346
24853 /* 64346 */ GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(64872),
24854 /* 64351 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24855 /* 64354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24856 /* 64358 */ GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(64434), // Rule ID 1460 //
24857 /* 64363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
24858 /* 64366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24859 /* 64370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
24860 /* 64374 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24861 /* 64378 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24862 /* 64382 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
24863 /* 64386 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24864 /* 64390 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
24865 /* 64394 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
24866 /* 64398 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24867 /* 64403 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24868 /* 64408 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24869 /* 64413 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
24870 /* 64415 */ // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24871 /* 64415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
24872 /* 64418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24873 /* 64420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
24874 /* 64424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24875 /* 64428 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24876 /* 64432 */ GIR_RootConstrainSelectedInstOperands,
24877 /* 64433 */ // GIR_Coverage, 1460,
24878 /* 64433 */ GIR_EraseRootFromParent_Done,
24879 /* 64434 */ // Label 1568: @64434
24880 /* 64434 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(64510), // Rule ID 2248 //
24881 /* 64439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
24882 /* 64442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24883 /* 64446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
24884 /* 64450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24885 /* 64454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24886 /* 64458 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
24887 /* 64462 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24888 /* 64466 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
24889 /* 64470 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
24890 /* 64474 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24891 /* 64479 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24892 /* 64484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24893 /* 64489 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
24894 /* 64491 */ // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24895 /* 64491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
24896 /* 64494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24897 /* 64496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
24898 /* 64500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24899 /* 64504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24900 /* 64508 */ GIR_RootConstrainSelectedInstOperands,
24901 /* 64509 */ // GIR_Coverage, 2248,
24902 /* 64509 */ GIR_EraseRootFromParent_Done,
24903 /* 64510 */ // Label 1569: @64510
24904 /* 64510 */ GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(64586), // Rule ID 2434 //
24905 /* 64515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
24906 /* 64518 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24907 /* 64522 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
24908 /* 64526 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24909 /* 64530 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24910 /* 64534 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24911 /* 64539 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
24912 /* 64543 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24913 /* 64547 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
24914 /* 64551 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
24915 /* 64555 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24916 /* 64560 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24917 /* 64565 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
24918 /* 64567 */ // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24919 /* 64567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
24920 /* 64570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24921 /* 64572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
24922 /* 64576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24923 /* 64580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24924 /* 64584 */ GIR_RootConstrainSelectedInstOperands,
24925 /* 64585 */ // GIR_Coverage, 2434,
24926 /* 64585 */ GIR_EraseRootFromParent_Done,
24927 /* 64586 */ // Label 1570: @64586
24928 /* 64586 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(64662), // Rule ID 2520 //
24929 /* 64591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
24930 /* 64594 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24931 /* 64598 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
24932 /* 64602 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24933 /* 64606 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24934 /* 64610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24935 /* 64615 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
24936 /* 64619 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24937 /* 64623 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
24938 /* 64627 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
24939 /* 64631 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24940 /* 64636 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24941 /* 64641 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
24942 /* 64643 */ // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24943 /* 64643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
24944 /* 64646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24945 /* 64648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
24946 /* 64652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24947 /* 64656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24948 /* 64660 */ GIR_RootConstrainSelectedInstOperands,
24949 /* 64661 */ // GIR_Coverage, 2520,
24950 /* 64661 */ GIR_EraseRootFromParent_Done,
24951 /* 64662 */ // Label 1571: @64662
24952 /* 64662 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(64738), // Rule ID 1461 //
24953 /* 64667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
24954 /* 64670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24955 /* 64674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
24956 /* 64678 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24957 /* 64682 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24958 /* 64686 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
24959 /* 64690 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24960 /* 64694 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
24961 /* 64698 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
24962 /* 64702 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24963 /* 64707 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24964 /* 64712 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24965 /* 64717 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
24966 /* 64719 */ // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24967 /* 64719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S),
24968 /* 64722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24969 /* 64724 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
24970 /* 64728 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24971 /* 64732 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24972 /* 64736 */ GIR_RootConstrainSelectedInstOperands,
24973 /* 64737 */ // GIR_Coverage, 1461,
24974 /* 64737 */ GIR_EraseRootFromParent_Done,
24975 /* 64738 */ // Label 1572: @64738
24976 /* 64738 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(64814), // Rule ID 2249 //
24977 /* 64743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
24978 /* 64746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24979 /* 64750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
24980 /* 64754 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24981 /* 64758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24982 /* 64762 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
24983 /* 64766 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24984 /* 64770 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
24985 /* 64774 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
24986 /* 64778 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24987 /* 64783 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24988 /* 64788 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24989 /* 64793 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
24990 /* 64795 */ // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24991 /* 64795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S_MM),
24992 /* 64798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24993 /* 64800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
24994 /* 64804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24995 /* 64808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24996 /* 64812 */ GIR_RootConstrainSelectedInstOperands,
24997 /* 64813 */ // GIR_Coverage, 2249,
24998 /* 64813 */ GIR_EraseRootFromParent_Done,
24999 /* 64814 */ // Label 1573: @64814
25000 /* 64814 */ GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(64833), // Rule ID 129 //
25001 /* 64819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat),
25002 /* 64822 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25003 /* 64826 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25004 /* 64826 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S),
25005 /* 64831 */ GIR_RootConstrainSelectedInstOperands,
25006 /* 64832 */ // GIR_Coverage, 129,
25007 /* 64832 */ GIR_Done,
25008 /* 64833 */ // Label 1574: @64833
25009 /* 64833 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(64852), // Rule ID 1153 //
25010 /* 64838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
25011 /* 64841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25012 /* 64845 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25013 /* 64845 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MM),
25014 /* 64850 */ GIR_RootConstrainSelectedInstOperands,
25015 /* 64851 */ // GIR_Coverage, 1153,
25016 /* 64851 */ GIR_Done,
25017 /* 64852 */ // Label 1575: @64852
25018 /* 64852 */ GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(64871), // Rule ID 1192 //
25019 /* 64857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
25020 /* 64860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25021 /* 64864 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25022 /* 64864 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MMR6),
25023 /* 64869 */ GIR_RootConstrainSelectedInstOperands,
25024 /* 64870 */ // GIR_Coverage, 1192,
25025 /* 64870 */ GIR_Done,
25026 /* 64871 */ // Label 1576: @64871
25027 /* 64871 */ GIM_Reject,
25028 /* 64872 */ // Label 1567: @64872
25029 /* 64872 */ GIM_Reject,
25030 /* 64873 */ // Label 1565: @64873
25031 /* 64873 */ GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(65694),
25032 /* 64878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25033 /* 64881 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(64961), // Rule ID 1462 //
25034 /* 64886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
25035 /* 64889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25036 /* 64893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25037 /* 64897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
25038 /* 64901 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25039 /* 64905 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25040 /* 64909 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
25041 /* 64913 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25042 /* 64917 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25043 /* 64921 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25044 /* 64925 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25045 /* 64930 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25046 /* 64935 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25047 /* 64940 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25048 /* 64942 */ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25049 /* 64942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
25050 /* 64945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25051 /* 64947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
25052 /* 64951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25053 /* 64955 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25054 /* 64959 */ GIR_RootConstrainSelectedInstOperands,
25055 /* 64960 */ // GIR_Coverage, 1462,
25056 /* 64960 */ GIR_EraseRootFromParent_Done,
25057 /* 64961 */ // Label 1578: @64961
25058 /* 64961 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(65041), // Rule ID 1464 //
25059 /* 64966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
25060 /* 64969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25061 /* 64973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25062 /* 64977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
25063 /* 64981 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25064 /* 64985 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25065 /* 64989 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
25066 /* 64993 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25067 /* 64997 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25068 /* 65001 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25069 /* 65005 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25070 /* 65010 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25071 /* 65015 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25072 /* 65020 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25073 /* 65022 */ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25074 /* 65022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
25075 /* 65025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25076 /* 65027 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
25077 /* 65031 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25078 /* 65035 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25079 /* 65039 */ GIR_RootConstrainSelectedInstOperands,
25080 /* 65040 */ // GIR_Coverage, 1464,
25081 /* 65040 */ GIR_EraseRootFromParent_Done,
25082 /* 65041 */ // Label 1579: @65041
25083 /* 65041 */ GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(65121), // Rule ID 2250 //
25084 /* 65046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
25085 /* 65049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25086 /* 65053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25087 /* 65057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
25088 /* 65061 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25089 /* 65065 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25090 /* 65069 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
25091 /* 65073 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25092 /* 65077 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25093 /* 65081 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25094 /* 65085 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25095 /* 65090 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25096 /* 65095 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25097 /* 65100 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25098 /* 65102 */ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25099 /* 65102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
25100 /* 65105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25101 /* 65107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
25102 /* 65111 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25103 /* 65115 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25104 /* 65119 */ GIR_RootConstrainSelectedInstOperands,
25105 /* 65120 */ // GIR_Coverage, 2250,
25106 /* 65120 */ GIR_EraseRootFromParent_Done,
25107 /* 65121 */ // Label 1580: @65121
25108 /* 65121 */ GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(65201), // Rule ID 2435 //
25109 /* 65126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
25110 /* 65129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25111 /* 65133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25112 /* 65137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
25113 /* 65141 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25114 /* 65145 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25115 /* 65149 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25116 /* 65154 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
25117 /* 65158 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25118 /* 65162 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25119 /* 65166 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25120 /* 65170 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25121 /* 65175 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25122 /* 65180 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25123 /* 65182 */ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25124 /* 65182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
25125 /* 65185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25126 /* 65187 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
25127 /* 65191 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25128 /* 65195 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25129 /* 65199 */ GIR_RootConstrainSelectedInstOperands,
25130 /* 65200 */ // GIR_Coverage, 2435,
25131 /* 65200 */ GIR_EraseRootFromParent_Done,
25132 /* 65201 */ // Label 1581: @65201
25133 /* 65201 */ GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(65281), // Rule ID 2436 //
25134 /* 65206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
25135 /* 65209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25136 /* 65213 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25137 /* 65217 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
25138 /* 65221 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25139 /* 65225 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25140 /* 65229 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25141 /* 65234 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
25142 /* 65238 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25143 /* 65242 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25144 /* 65246 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25145 /* 65250 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25146 /* 65255 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25147 /* 65260 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25148 /* 65262 */ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25149 /* 65262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
25150 /* 65265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25151 /* 65267 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
25152 /* 65271 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25153 /* 65275 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25154 /* 65279 */ GIR_RootConstrainSelectedInstOperands,
25155 /* 65280 */ // GIR_Coverage, 2436,
25156 /* 65280 */ GIR_EraseRootFromParent_Done,
25157 /* 65281 */ // Label 1582: @65281
25158 /* 65281 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(65361), // Rule ID 2521 //
25159 /* 65286 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
25160 /* 65289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25161 /* 65293 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25162 /* 65297 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
25163 /* 65301 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25164 /* 65305 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25165 /* 65309 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25166 /* 65314 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
25167 /* 65318 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25168 /* 65322 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25169 /* 65326 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25170 /* 65330 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25171 /* 65335 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25172 /* 65340 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25173 /* 65342 */ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25174 /* 65342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
25175 /* 65345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25176 /* 65347 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
25177 /* 65351 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25178 /* 65355 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25179 /* 65359 */ GIR_RootConstrainSelectedInstOperands,
25180 /* 65360 */ // GIR_Coverage, 2521,
25181 /* 65360 */ GIR_EraseRootFromParent_Done,
25182 /* 65361 */ // Label 1583: @65361
25183 /* 65361 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(65441), // Rule ID 1463 //
25184 /* 65366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
25185 /* 65369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25186 /* 65373 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25187 /* 65377 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
25188 /* 65381 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25189 /* 65385 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25190 /* 65389 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
25191 /* 65393 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25192 /* 65397 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25193 /* 65401 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25194 /* 65405 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25195 /* 65410 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25196 /* 65415 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25197 /* 65420 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25198 /* 65422 */ // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25199 /* 65422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32),
25200 /* 65425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25201 /* 65427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
25202 /* 65431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25203 /* 65435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25204 /* 65439 */ GIR_RootConstrainSelectedInstOperands,
25205 /* 65440 */ // GIR_Coverage, 1463,
25206 /* 65440 */ GIR_EraseRootFromParent_Done,
25207 /* 65441 */ // Label 1584: @65441
25208 /* 65441 */ GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(65521), // Rule ID 1465 //
25209 /* 65446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
25210 /* 65449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25211 /* 65453 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25212 /* 65457 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
25213 /* 65461 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25214 /* 65465 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25215 /* 65469 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
25216 /* 65473 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25217 /* 65477 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25218 /* 65481 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25219 /* 65485 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25220 /* 65490 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25221 /* 65495 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25222 /* 65500 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25223 /* 65502 */ // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25224 /* 65502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D64),
25225 /* 65505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25226 /* 65507 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
25227 /* 65511 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25228 /* 65515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25229 /* 65519 */ GIR_RootConstrainSelectedInstOperands,
25230 /* 65520 */ // GIR_Coverage, 1465,
25231 /* 65520 */ GIR_EraseRootFromParent_Done,
25232 /* 65521 */ // Label 1585: @65521
25233 /* 65521 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(65601), // Rule ID 2251 //
25234 /* 65526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
25235 /* 65529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25236 /* 65533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25237 /* 65537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
25238 /* 65541 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25239 /* 65545 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25240 /* 65549 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
25241 /* 65553 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
25242 /* 65557 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
25243 /* 65561 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
25244 /* 65565 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25245 /* 65570 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25246 /* 65575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25247 /* 65580 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
25248 /* 65582 */ // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25249 /* 65582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32_MM),
25250 /* 65585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25251 /* 65587 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
25252 /* 65591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
25253 /* 65595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
25254 /* 65599 */ GIR_RootConstrainSelectedInstOperands,
25255 /* 65600 */ // GIR_Coverage, 2251,
25256 /* 65600 */ GIR_EraseRootFromParent_Done,
25257 /* 65601 */ // Label 1586: @65601
25258 /* 65601 */ GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(65624), // Rule ID 130 //
25259 /* 65606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
25260 /* 65609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25261 /* 65613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25262 /* 65617 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25263 /* 65617 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32),
25264 /* 65622 */ GIR_RootConstrainSelectedInstOperands,
25265 /* 65623 */ // GIR_Coverage, 130,
25266 /* 65623 */ GIR_Done,
25267 /* 65624 */ // Label 1587: @65624
25268 /* 65624 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(65647), // Rule ID 131 //
25269 /* 65629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
25270 /* 65632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25271 /* 65636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25272 /* 65640 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25273 /* 65640 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64),
25274 /* 65645 */ GIR_RootConstrainSelectedInstOperands,
25275 /* 65646 */ // GIR_Coverage, 131,
25276 /* 65646 */ GIR_Done,
25277 /* 65647 */ // Label 1588: @65647
25278 /* 65647 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(65670), // Rule ID 1154 //
25279 /* 65652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
25280 /* 65655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25281 /* 65659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25282 /* 65663 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25283 /* 65663 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32_MM),
25284 /* 65668 */ GIR_RootConstrainSelectedInstOperands,
25285 /* 65669 */ // GIR_Coverage, 1154,
25286 /* 65669 */ GIR_Done,
25287 /* 65670 */ // Label 1589: @65670
25288 /* 65670 */ GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(65693), // Rule ID 1155 //
25289 /* 65675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
25290 /* 65678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25291 /* 65682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25292 /* 65686 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25293 /* 65686 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64_MM),
25294 /* 65691 */ GIR_RootConstrainSelectedInstOperands,
25295 /* 65692 */ // GIR_Coverage, 1155,
25296 /* 65692 */ GIR_Done,
25297 /* 65693 */ // Label 1590: @65693
25298 /* 65693 */ GIM_Reject,
25299 /* 65694 */ // Label 1577: @65694
25300 /* 65694 */ GIM_Reject,
25301 /* 65695 */ // Label 1566: @65695
25302 /* 65695 */ GIM_Reject,
25303 /* 65696 */ // Label 54: @65696
25304 /* 65696 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1593*/ GIMT_Encode4(65873),
25305 /* 65707 */ /*GILLT_s32*//*Label 1591*/ GIMT_Encode4(65715),
25306 /* 65711 */ /*GILLT_s64*//*Label 1592*/ GIMT_Encode4(65742),
25307 /* 65715 */ // Label 1591: @65715
25308 /* 65715 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(65741), // Rule ID 1056 //
25309 /* 65720 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25310 /* 65723 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
25311 /* 65726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25312 /* 65730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25313 /* 65734 */ // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
25314 /* 65734 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_W_PSEUDO),
25315 /* 65739 */ GIR_RootConstrainSelectedInstOperands,
25316 /* 65740 */ // GIR_Coverage, 1056,
25317 /* 65740 */ GIR_Done,
25318 /* 65741 */ // Label 1594: @65741
25319 /* 65741 */ GIM_Reject,
25320 /* 65742 */ // Label 1592: @65742
25321 /* 65742 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(65768), // Rule ID 1058 //
25322 /* 65747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25323 /* 65750 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
25324 /* 65753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25325 /* 65757 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25326 /* 65761 */ // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
25327 /* 65761 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_D_PSEUDO),
25328 /* 65766 */ GIR_RootConstrainSelectedInstOperands,
25329 /* 65767 */ // GIR_Coverage, 1058,
25330 /* 65767 */ GIR_Done,
25331 /* 65768 */ // Label 1595: @65768
25332 /* 65768 */ GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(65794), // Rule ID 1449 //
25333 /* 65773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips),
25334 /* 65776 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25335 /* 65779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25336 /* 65783 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25337 /* 65787 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25338 /* 65787 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S),
25339 /* 65792 */ GIR_RootConstrainSelectedInstOperands,
25340 /* 65793 */ // GIR_Coverage, 1449,
25341 /* 65793 */ GIR_Done,
25342 /* 65794 */ // Label 1596: @65794
25343 /* 65794 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(65820), // Rule ID 1459 //
25344 /* 65799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips),
25345 /* 65802 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25346 /* 65805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25347 /* 65809 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25348 /* 65813 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25349 /* 65813 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S),
25350 /* 65818 */ GIR_RootConstrainSelectedInstOperands,
25351 /* 65819 */ // GIR_Coverage, 1459,
25352 /* 65819 */ GIR_Done,
25353 /* 65820 */ // Label 1597: @65820
25354 /* 65820 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(65846), // Rule ID 2262 //
25355 /* 65825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit),
25356 /* 65828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25357 /* 65831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25358 /* 65835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25359 /* 65839 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25360 /* 65839 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S_MM),
25361 /* 65844 */ GIR_RootConstrainSelectedInstOperands,
25362 /* 65845 */ // GIR_Coverage, 2262,
25363 /* 65845 */ GIR_Done,
25364 /* 65846 */ // Label 1598: @65846
25365 /* 65846 */ GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(65872), // Rule ID 2264 //
25366 /* 65851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit),
25367 /* 65854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25368 /* 65857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25369 /* 65861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25370 /* 65865 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25371 /* 65865 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S_MM),
25372 /* 65870 */ GIR_RootConstrainSelectedInstOperands,
25373 /* 65871 */ // GIR_Coverage, 2264,
25374 /* 65871 */ GIR_Done,
25375 /* 65872 */ // Label 1599: @65872
25376 /* 65872 */ GIM_Reject,
25377 /* 65873 */ // Label 1593: @65873
25378 /* 65873 */ GIM_Reject,
25379 /* 65874 */ // Label 55: @65874
25380 /* 65874 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1602*/ GIMT_Encode4(66036),
25381 /* 65885 */ /*GILLT_s16*//*Label 1600*/ GIMT_Encode4(65893),
25382 /* 65889 */ /*GILLT_s32*//*Label 1601*/ GIMT_Encode4(65946),
25383 /* 65893 */ // Label 1600: @65893
25384 /* 65893 */ GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(65919), // Rule ID 1057 //
25385 /* 65898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25386 /* 65901 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25387 /* 65904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25388 /* 65908 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25389 /* 65912 */ // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
25390 /* 65912 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_W_PSEUDO),
25391 /* 65917 */ GIR_RootConstrainSelectedInstOperands,
25392 /* 65918 */ // GIR_Coverage, 1057,
25393 /* 65918 */ GIR_Done,
25394 /* 65919 */ // Label 1603: @65919
25395 /* 65919 */ GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(65945), // Rule ID 1059 //
25396 /* 65924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25397 /* 65927 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25398 /* 65930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25399 /* 65934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25400 /* 65938 */ // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
25401 /* 65938 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_D_PSEUDO),
25402 /* 65943 */ GIR_RootConstrainSelectedInstOperands,
25403 /* 65944 */ // GIR_Coverage, 1059,
25404 /* 65944 */ GIR_Done,
25405 /* 65945 */ // Label 1604: @65945
25406 /* 65945 */ GIM_Reject,
25407 /* 65946 */ // Label 1601: @65946
25408 /* 65946 */ GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(66035),
25409 /* 65951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25410 /* 65954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25411 /* 65958 */ GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(65977), // Rule ID 1448 //
25412 /* 65963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips),
25413 /* 65966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25414 /* 65970 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
25415 /* 65970 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32),
25416 /* 65975 */ GIR_RootConstrainSelectedInstOperands,
25417 /* 65976 */ // GIR_Coverage, 1448,
25418 /* 65976 */ GIR_Done,
25419 /* 65977 */ // Label 1606: @65977
25420 /* 65977 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(65996), // Rule ID 1458 //
25421 /* 65982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips),
25422 /* 65985 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25423 /* 65989 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
25424 /* 65989 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64),
25425 /* 65994 */ GIR_RootConstrainSelectedInstOperands,
25426 /* 65995 */ // GIR_Coverage, 1458,
25427 /* 65995 */ GIR_Done,
25428 /* 65996 */ // Label 1607: @65996
25429 /* 65996 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(66015), // Rule ID 2261 //
25430 /* 66001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit),
25431 /* 66004 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25432 /* 66008 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
25433 /* 66008 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64_MM),
25434 /* 66013 */ GIR_RootConstrainSelectedInstOperands,
25435 /* 66014 */ // GIR_Coverage, 2261,
25436 /* 66014 */ GIR_Done,
25437 /* 66015 */ // Label 1608: @66015
25438 /* 66015 */ GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(66034), // Rule ID 2263 //
25439 /* 66020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit),
25440 /* 66023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25441 /* 66027 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
25442 /* 66027 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32_MM),
25443 /* 66032 */ GIR_RootConstrainSelectedInstOperands,
25444 /* 66033 */ // GIR_Coverage, 2263,
25445 /* 66033 */ GIR_Done,
25446 /* 66034 */ // Label 1609: @66034
25447 /* 66034 */ GIM_Reject,
25448 /* 66035 */ // Label 1605: @66035
25449 /* 66035 */ GIM_Reject,
25450 /* 66036 */ // Label 1602: @66036
25451 /* 66036 */ GIM_Reject,
25452 /* 66037 */ // Label 56: @66037
25453 /* 66037 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1612*/ GIMT_Encode4(66114),
25454 /* 66048 */ /*GILLT_v2s64*//*Label 1610*/ GIMT_Encode4(66060), GIMT_Encode4(0),
25455 /* 66056 */ /*GILLT_v4s32*//*Label 1611*/ GIMT_Encode4(66087),
25456 /* 66060 */ // Label 1610: @66060
25457 /* 66060 */ GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(66086), // Rule ID 777 //
25458 /* 66065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25459 /* 66068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25460 /* 66071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25461 /* 66075 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25462 /* 66079 */ // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25463 /* 66079 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_D),
25464 /* 66084 */ GIR_RootConstrainSelectedInstOperands,
25465 /* 66085 */ // GIR_Coverage, 777,
25466 /* 66085 */ GIR_Done,
25467 /* 66086 */ // Label 1613: @66086
25468 /* 66086 */ GIM_Reject,
25469 /* 66087 */ // Label 1611: @66087
25470 /* 66087 */ GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(66113), // Rule ID 776 //
25471 /* 66092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25472 /* 66095 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25473 /* 66098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25474 /* 66102 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25475 /* 66106 */ // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25476 /* 66106 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_W),
25477 /* 66111 */ GIR_RootConstrainSelectedInstOperands,
25478 /* 66112 */ // GIR_Coverage, 776,
25479 /* 66112 */ GIR_Done,
25480 /* 66113 */ // Label 1614: @66113
25481 /* 66113 */ GIM_Reject,
25482 /* 66114 */ // Label 1612: @66114
25483 /* 66114 */ GIM_Reject,
25484 /* 66115 */ // Label 57: @66115
25485 /* 66115 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1617*/ GIMT_Encode4(66192),
25486 /* 66126 */ /*GILLT_v2s64*//*Label 1615*/ GIMT_Encode4(66138), GIMT_Encode4(0),
25487 /* 66134 */ /*GILLT_v4s32*//*Label 1616*/ GIMT_Encode4(66165),
25488 /* 66138 */ // Label 1615: @66138
25489 /* 66138 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(66164), // Rule ID 779 //
25490 /* 66143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25491 /* 66146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25492 /* 66149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25493 /* 66153 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25494 /* 66157 */ // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25495 /* 66157 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_D),
25496 /* 66162 */ GIR_RootConstrainSelectedInstOperands,
25497 /* 66163 */ // GIR_Coverage, 779,
25498 /* 66163 */ GIR_Done,
25499 /* 66164 */ // Label 1618: @66164
25500 /* 66164 */ GIM_Reject,
25501 /* 66165 */ // Label 1616: @66165
25502 /* 66165 */ GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(66191), // Rule ID 778 //
25503 /* 66170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25504 /* 66173 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25505 /* 66176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25506 /* 66180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25507 /* 66184 */ // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25508 /* 66184 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_W),
25509 /* 66189 */ GIR_RootConstrainSelectedInstOperands,
25510 /* 66190 */ // GIR_Coverage, 778,
25511 /* 66190 */ GIR_Done,
25512 /* 66191 */ // Label 1619: @66191
25513 /* 66191 */ GIM_Reject,
25514 /* 66192 */ // Label 1617: @66192
25515 /* 66192 */ GIM_Reject,
25516 /* 66193 */ // Label 58: @66193
25517 /* 66193 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1624*/ GIMT_Encode4(66445),
25518 /* 66204 */ /*GILLT_s32*//*Label 1620*/ GIMT_Encode4(66228),
25519 /* 66208 */ /*GILLT_s64*//*Label 1621*/ GIMT_Encode4(66312), GIMT_Encode4(0),
25520 /* 66216 */ /*GILLT_v2s64*//*Label 1622*/ GIMT_Encode4(66391), GIMT_Encode4(0),
25521 /* 66224 */ /*GILLT_v4s32*//*Label 1623*/ GIMT_Encode4(66418),
25522 /* 66228 */ // Label 1620: @66228
25523 /* 66228 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(66251), // Rule ID 1443 //
25524 /* 66233 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25525 /* 66236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25526 /* 66240 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25527 /* 66244 */ // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
25528 /* 66244 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_W),
25529 /* 66249 */ GIR_RootConstrainSelectedInstOperands,
25530 /* 66250 */ // GIR_Coverage, 1443,
25531 /* 66250 */ GIR_Done,
25532 /* 66251 */ // Label 1625: @66251
25533 /* 66251 */ GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(66311), // Rule ID 1453 //
25534 /* 66256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
25535 /* 66259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25536 /* 66262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25537 /* 66266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25538 /* 66270 */ // (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
25539 /* 66270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
25540 /* 66273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_L),
25541 /* 66277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25542 /* 66282 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
25543 /* 66286 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25544 /* 66288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25545 /* 66291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
25546 /* 66293 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
25547 /* 66300 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
25548 /* 66305 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
25549 /* 66310 */ // GIR_Coverage, 1453,
25550 /* 66310 */ GIR_EraseRootFromParent_Done,
25551 /* 66311 */ // Label 1626: @66311
25552 /* 66311 */ GIM_Reject,
25553 /* 66312 */ // Label 1621: @66312
25554 /* 66312 */ GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(66338), // Rule ID 1446 //
25555 /* 66317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotFP64bit),
25556 /* 66320 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25557 /* 66323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25558 /* 66327 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25559 /* 66331 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
25560 /* 66331 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D32_W),
25561 /* 66336 */ GIR_RootConstrainSelectedInstOperands,
25562 /* 66337 */ // GIR_Coverage, 1446,
25563 /* 66337 */ GIR_Done,
25564 /* 66338 */ // Label 1627: @66338
25565 /* 66338 */ GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(66364), // Rule ID 1452 //
25566 /* 66343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
25567 /* 66346 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25568 /* 66349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25569 /* 66353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25570 /* 66357 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
25571 /* 66357 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_W),
25572 /* 66362 */ GIR_RootConstrainSelectedInstOperands,
25573 /* 66363 */ // GIR_Coverage, 1452,
25574 /* 66363 */ GIR_Done,
25575 /* 66364 */ // Label 1628: @66364
25576 /* 66364 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(66390), // Rule ID 1454 //
25577 /* 66369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
25578 /* 66372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25579 /* 66375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25580 /* 66379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25581 /* 66383 */ // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
25582 /* 66383 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_L),
25583 /* 66388 */ GIR_RootConstrainSelectedInstOperands,
25584 /* 66389 */ // GIR_Coverage, 1454,
25585 /* 66389 */ GIR_Done,
25586 /* 66390 */ // Label 1629: @66390
25587 /* 66390 */ GIM_Reject,
25588 /* 66391 */ // Label 1622: @66391
25589 /* 66391 */ GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(66417), // Rule ID 709 //
25590 /* 66396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25591 /* 66399 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25592 /* 66402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25593 /* 66406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25594 /* 66410 */ // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25595 /* 66410 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_D),
25596 /* 66415 */ GIR_RootConstrainSelectedInstOperands,
25597 /* 66416 */ // GIR_Coverage, 709,
25598 /* 66416 */ GIR_Done,
25599 /* 66417 */ // Label 1630: @66417
25600 /* 66417 */ GIM_Reject,
25601 /* 66418 */ // Label 1623: @66418
25602 /* 66418 */ GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(66444), // Rule ID 708 //
25603 /* 66423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25604 /* 66426 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25605 /* 66429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25606 /* 66433 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25607 /* 66437 */ // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25608 /* 66437 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_W),
25609 /* 66442 */ GIR_RootConstrainSelectedInstOperands,
25610 /* 66443 */ // GIR_Coverage, 708,
25611 /* 66443 */ GIR_Done,
25612 /* 66444 */ // Label 1631: @66444
25613 /* 66444 */ GIM_Reject,
25614 /* 66445 */ // Label 1624: @66445
25615 /* 66445 */ GIM_Reject,
25616 /* 66446 */ // Label 59: @66446
25617 /* 66446 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1634*/ GIMT_Encode4(66523),
25618 /* 66457 */ /*GILLT_v2s64*//*Label 1632*/ GIMT_Encode4(66469), GIMT_Encode4(0),
25619 /* 66465 */ /*GILLT_v4s32*//*Label 1633*/ GIMT_Encode4(66496),
25620 /* 66469 */ // Label 1632: @66469
25621 /* 66469 */ GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(66495), // Rule ID 711 //
25622 /* 66474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25623 /* 66477 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25624 /* 66480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25625 /* 66484 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25626 /* 66488 */ // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25627 /* 66488 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_D),
25628 /* 66493 */ GIR_RootConstrainSelectedInstOperands,
25629 /* 66494 */ // GIR_Coverage, 711,
25630 /* 66494 */ GIR_Done,
25631 /* 66495 */ // Label 1635: @66495
25632 /* 66495 */ GIM_Reject,
25633 /* 66496 */ // Label 1633: @66496
25634 /* 66496 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(66522), // Rule ID 710 //
25635 /* 66501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25636 /* 66504 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25637 /* 66507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25638 /* 66511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25639 /* 66515 */ // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25640 /* 66515 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_W),
25641 /* 66520 */ GIR_RootConstrainSelectedInstOperands,
25642 /* 66521 */ // GIR_Coverage, 710,
25643 /* 66521 */ GIR_Done,
25644 /* 66522 */ // Label 1636: @66522
25645 /* 66522 */ GIM_Reject,
25646 /* 66523 */ // Label 1634: @66523
25647 /* 66523 */ GIM_Reject,
25648 /* 66524 */ // Label 60: @66524
25649 /* 66524 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1641*/ GIMT_Encode4(66763),
25650 /* 66535 */ /*GILLT_s32*//*Label 1637*/ GIMT_Encode4(66559),
25651 /* 66539 */ /*GILLT_s64*//*Label 1638*/ GIMT_Encode4(66607), GIMT_Encode4(0),
25652 /* 66547 */ /*GILLT_v2s64*//*Label 1639*/ GIMT_Encode4(66709), GIMT_Encode4(0),
25653 /* 66555 */ /*GILLT_v4s32*//*Label 1640*/ GIMT_Encode4(66736),
25654 /* 66559 */ // Label 1637: @66559
25655 /* 66559 */ GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(66606),
25656 /* 66564 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25657 /* 66567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25658 /* 66571 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25659 /* 66575 */ GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(66590), // Rule ID 126 //
25660 /* 66580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs),
25661 /* 66583 */ // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25662 /* 66583 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S),
25663 /* 66588 */ GIR_RootConstrainSelectedInstOperands,
25664 /* 66589 */ // GIR_Coverage, 126,
25665 /* 66589 */ GIR_Done,
25666 /* 66590 */ // Label 1643: @66590
25667 /* 66590 */ GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(66605), // Rule ID 1152 //
25668 /* 66595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_UseAbs),
25669 /* 66598 */ // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25670 /* 66598 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S_MM),
25671 /* 66603 */ GIR_RootConstrainSelectedInstOperands,
25672 /* 66604 */ // GIR_Coverage, 1152,
25673 /* 66604 */ GIR_Done,
25674 /* 66605 */ // Label 1644: @66605
25675 /* 66605 */ GIM_Reject,
25676 /* 66606 */ // Label 1642: @66606
25677 /* 66606 */ GIM_Reject,
25678 /* 66607 */ // Label 1638: @66607
25679 /* 66607 */ GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(66708),
25680 /* 66612 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25681 /* 66615 */ GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(66638), // Rule ID 127 //
25682 /* 66620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs),
25683 /* 66623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25684 /* 66627 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25685 /* 66631 */ // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25686 /* 66631 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32),
25687 /* 66636 */ GIR_RootConstrainSelectedInstOperands,
25688 /* 66637 */ // GIR_Coverage, 127,
25689 /* 66637 */ GIR_Done,
25690 /* 66638 */ // Label 1646: @66638
25691 /* 66638 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(66661), // Rule ID 128 //
25692 /* 66643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs),
25693 /* 66646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25694 /* 66650 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25695 /* 66654 */ // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25696 /* 66654 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64),
25697 /* 66659 */ GIR_RootConstrainSelectedInstOperands,
25698 /* 66660 */ // GIR_Coverage, 128,
25699 /* 66660 */ GIR_Done,
25700 /* 66661 */ // Label 1647: @66661
25701 /* 66661 */ GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(66684), // Rule ID 1150 //
25702 /* 66666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
25703 /* 66669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25704 /* 66673 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25705 /* 66677 */ // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25706 /* 66677 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32_MM),
25707 /* 66682 */ GIR_RootConstrainSelectedInstOperands,
25708 /* 66683 */ // GIR_Coverage, 1150,
25709 /* 66683 */ GIR_Done,
25710 /* 66684 */ // Label 1648: @66684
25711 /* 66684 */ GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(66707), // Rule ID 1151 //
25712 /* 66689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
25713 /* 66692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25714 /* 66696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25715 /* 66700 */ // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25716 /* 66700 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64_MM),
25717 /* 66705 */ GIR_RootConstrainSelectedInstOperands,
25718 /* 66706 */ // GIR_Coverage, 1151,
25719 /* 66706 */ GIR_Done,
25720 /* 66707 */ // Label 1649: @66707
25721 /* 66707 */ GIM_Reject,
25722 /* 66708 */ // Label 1645: @66708
25723 /* 66708 */ GIM_Reject,
25724 /* 66709 */ // Label 1639: @66709
25725 /* 66709 */ GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(66735), // Rule ID 1043 //
25726 /* 66714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25727 /* 66717 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25728 /* 66720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25729 /* 66724 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25730 /* 66728 */ // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25731 /* 66728 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D),
25732 /* 66733 */ GIR_RootConstrainSelectedInstOperands,
25733 /* 66734 */ // GIR_Coverage, 1043,
25734 /* 66734 */ GIR_Done,
25735 /* 66735 */ // Label 1650: @66735
25736 /* 66735 */ GIM_Reject,
25737 /* 66736 */ // Label 1640: @66736
25738 /* 66736 */ GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(66762), // Rule ID 1042 //
25739 /* 66741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25740 /* 66744 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25741 /* 66747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25742 /* 66751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25743 /* 66755 */ // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25744 /* 66755 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_W),
25745 /* 66760 */ GIR_RootConstrainSelectedInstOperands,
25746 /* 66761 */ // GIR_Coverage, 1042,
25747 /* 66761 */ GIR_Done,
25748 /* 66762 */ // Label 1651: @66762
25749 /* 66762 */ GIM_Reject,
25750 /* 66763 */ // Label 1641: @66763
25751 /* 66763 */ GIM_Reject,
25752 /* 66764 */ // Label 61: @66764
25753 /* 66764 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1654*/ GIMT_Encode4(66837),
25754 /* 66775 */ /*GILLT_s32*//*Label 1652*/ GIMT_Encode4(66783),
25755 /* 66779 */ /*GILLT_s64*//*Label 1653*/ GIMT_Encode4(66810),
25756 /* 66783 */ // Label 1652: @66783
25757 /* 66783 */ GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(66809), // Rule ID 1794 //
25758 /* 66788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25759 /* 66791 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25760 /* 66794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25761 /* 66798 */ // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$src) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$src)
25762 /* 66798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
25763 /* 66801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25764 /* 66803 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
25765 /* 66805 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
25766 /* 66807 */ GIR_RootConstrainSelectedInstOperands,
25767 /* 66808 */ // GIR_Coverage, 1794,
25768 /* 66808 */ GIR_EraseRootFromParent_Done,
25769 /* 66809 */ // Label 1655: @66809
25770 /* 66809 */ GIM_Reject,
25771 /* 66810 */ // Label 1653: @66810
25772 /* 66810 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(66836), // Rule ID 1795 //
25773 /* 66815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25774 /* 66818 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25775 /* 66821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25776 /* 66825 */ // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$src) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$src, f64:{ *:[f64] }:$src)
25777 /* 66825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
25778 /* 66828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25779 /* 66830 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
25780 /* 66832 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
25781 /* 66834 */ GIR_RootConstrainSelectedInstOperands,
25782 /* 66835 */ // GIR_Coverage, 1795,
25783 /* 66835 */ GIR_EraseRootFromParent_Done,
25784 /* 66836 */ // Label 1656: @66836
25785 /* 66836 */ GIM_Reject,
25786 /* 66837 */ // Label 1654: @66837
25787 /* 66837 */ GIM_Reject,
25788 /* 66838 */ // Label 62: @66838
25789 /* 66838 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1659*/ GIMT_Encode4(66909),
25790 /* 66849 */ /*GILLT_s32*//*Label 1657*/ GIMT_Encode4(66857),
25791 /* 66853 */ /*GILLT_s64*//*Label 1658*/ GIMT_Encode4(66883),
25792 /* 66857 */ // Label 1657: @66857
25793 /* 66857 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(66882), // Rule ID 1791 //
25794 /* 66862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25795 /* 66865 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25796 /* 66868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25797 /* 66871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25798 /* 66875 */ // (fminnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
25799 /* 66875 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
25800 /* 66880 */ GIR_RootConstrainSelectedInstOperands,
25801 /* 66881 */ // GIR_Coverage, 1791,
25802 /* 66881 */ GIR_Done,
25803 /* 66882 */ // Label 1660: @66882
25804 /* 66882 */ GIM_Reject,
25805 /* 66883 */ // Label 1658: @66883
25806 /* 66883 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(66908), // Rule ID 1793 //
25807 /* 66888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25808 /* 66891 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25809 /* 66894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25810 /* 66897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25811 /* 66901 */ // (fminnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
25812 /* 66901 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
25813 /* 66906 */ GIR_RootConstrainSelectedInstOperands,
25814 /* 66907 */ // GIR_Coverage, 1793,
25815 /* 66907 */ GIR_Done,
25816 /* 66908 */ // Label 1661: @66908
25817 /* 66908 */ GIM_Reject,
25818 /* 66909 */ // Label 1659: @66909
25819 /* 66909 */ GIM_Reject,
25820 /* 66910 */ // Label 63: @66910
25821 /* 66910 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1664*/ GIMT_Encode4(66981),
25822 /* 66921 */ /*GILLT_s32*//*Label 1662*/ GIMT_Encode4(66929),
25823 /* 66925 */ /*GILLT_s64*//*Label 1663*/ GIMT_Encode4(66955),
25824 /* 66929 */ // Label 1662: @66929
25825 /* 66929 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(66954), // Rule ID 1787 //
25826 /* 66934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25827 /* 66937 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25828 /* 66940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25829 /* 66943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25830 /* 66947 */ // (fmaxnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
25831 /* 66947 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
25832 /* 66952 */ GIR_RootConstrainSelectedInstOperands,
25833 /* 66953 */ // GIR_Coverage, 1787,
25834 /* 66953 */ GIR_Done,
25835 /* 66954 */ // Label 1665: @66954
25836 /* 66954 */ GIM_Reject,
25837 /* 66955 */ // Label 1663: @66955
25838 /* 66955 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(66980), // Rule ID 1789 //
25839 /* 66960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25840 /* 66963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25841 /* 66966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25842 /* 66969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25843 /* 66973 */ // (fmaxnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
25844 /* 66973 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
25845 /* 66978 */ GIR_RootConstrainSelectedInstOperands,
25846 /* 66979 */ // GIR_Coverage, 1789,
25847 /* 66979 */ GIR_Done,
25848 /* 66980 */ // Label 1666: @66980
25849 /* 66980 */ GIM_Reject,
25850 /* 66981 */ // Label 1664: @66981
25851 /* 66981 */ GIM_Reject,
25852 /* 66982 */ // Label 64: @66982
25853 /* 66982 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1669*/ GIMT_Encode4(67053),
25854 /* 66993 */ /*GILLT_s32*//*Label 1667*/ GIMT_Encode4(67001),
25855 /* 66997 */ /*GILLT_s64*//*Label 1668*/ GIMT_Encode4(67027),
25856 /* 67001 */ // Label 1667: @67001
25857 /* 67001 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(67026), // Rule ID 1790 //
25858 /* 67006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25859 /* 67009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25860 /* 67012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25861 /* 67015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25862 /* 67019 */ // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
25863 /* 67019 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
25864 /* 67024 */ GIR_RootConstrainSelectedInstOperands,
25865 /* 67025 */ // GIR_Coverage, 1790,
25866 /* 67025 */ GIR_Done,
25867 /* 67026 */ // Label 1670: @67026
25868 /* 67026 */ GIM_Reject,
25869 /* 67027 */ // Label 1668: @67027
25870 /* 67027 */ GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(67052), // Rule ID 1792 //
25871 /* 67032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25872 /* 67035 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25873 /* 67038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25874 /* 67041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25875 /* 67045 */ // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
25876 /* 67045 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
25877 /* 67050 */ GIR_RootConstrainSelectedInstOperands,
25878 /* 67051 */ // GIR_Coverage, 1792,
25879 /* 67051 */ GIR_Done,
25880 /* 67052 */ // Label 1671: @67052
25881 /* 67052 */ GIM_Reject,
25882 /* 67053 */ // Label 1669: @67053
25883 /* 67053 */ GIM_Reject,
25884 /* 67054 */ // Label 65: @67054
25885 /* 67054 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1674*/ GIMT_Encode4(67125),
25886 /* 67065 */ /*GILLT_s32*//*Label 1672*/ GIMT_Encode4(67073),
25887 /* 67069 */ /*GILLT_s64*//*Label 1673*/ GIMT_Encode4(67099),
25888 /* 67073 */ // Label 1672: @67073
25889 /* 67073 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(67098), // Rule ID 1786 //
25890 /* 67078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25891 /* 67081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25892 /* 67084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25893 /* 67087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25894 /* 67091 */ // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
25895 /* 67091 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
25896 /* 67096 */ GIR_RootConstrainSelectedInstOperands,
25897 /* 67097 */ // GIR_Coverage, 1786,
25898 /* 67097 */ GIR_Done,
25899 /* 67098 */ // Label 1675: @67098
25900 /* 67098 */ GIM_Reject,
25901 /* 67099 */ // Label 1673: @67099
25902 /* 67099 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(67124), // Rule ID 1788 //
25903 /* 67104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
25904 /* 67107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25905 /* 67110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25906 /* 67113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25907 /* 67117 */ // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
25908 /* 67117 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
25909 /* 67122 */ GIR_RootConstrainSelectedInstOperands,
25910 /* 67123 */ // GIR_Coverage, 1788,
25911 /* 67123 */ GIR_Done,
25912 /* 67124 */ // Label 1676: @67124
25913 /* 67124 */ GIM_Reject,
25914 /* 67125 */ // Label 1674: @67125
25915 /* 67125 */ GIM_Reject,
25916 /* 67126 */ // Label 66: @67126
25917 /* 67126 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1681*/ GIMT_Encode4(67293),
25918 /* 67137 */ /*GILLT_v2s64*//*Label 1677*/ GIMT_Encode4(67157), GIMT_Encode4(0),
25919 /* 67145 */ /*GILLT_v4s32*//*Label 1678*/ GIMT_Encode4(67191),
25920 /* 67149 */ /*GILLT_v8s16*//*Label 1679*/ GIMT_Encode4(67225),
25921 /* 67153 */ /*GILLT_v16s8*//*Label 1680*/ GIMT_Encode4(67259),
25922 /* 67157 */ // Label 1677: @67157
25923 /* 67157 */ GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(67190), // Rule ID 871 //
25924 /* 67162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25925 /* 67165 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25926 /* 67168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25927 /* 67171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25928 /* 67175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25929 /* 67179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25930 /* 67183 */ // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
25931 /* 67183 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_D),
25932 /* 67188 */ GIR_RootConstrainSelectedInstOperands,
25933 /* 67189 */ // GIR_Coverage, 871,
25934 /* 67189 */ GIR_Done,
25935 /* 67190 */ // Label 1682: @67190
25936 /* 67190 */ GIM_Reject,
25937 /* 67191 */ // Label 1678: @67191
25938 /* 67191 */ GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(67224), // Rule ID 870 //
25939 /* 67196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25940 /* 67199 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25941 /* 67202 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25942 /* 67205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25943 /* 67209 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25944 /* 67213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25945 /* 67217 */ // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
25946 /* 67217 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_W),
25947 /* 67222 */ GIR_RootConstrainSelectedInstOperands,
25948 /* 67223 */ // GIR_Coverage, 870,
25949 /* 67223 */ GIR_Done,
25950 /* 67224 */ // Label 1683: @67224
25951 /* 67224 */ GIM_Reject,
25952 /* 67225 */ // Label 1679: @67225
25953 /* 67225 */ GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(67258), // Rule ID 869 //
25954 /* 67230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25955 /* 67233 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25956 /* 67236 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25957 /* 67239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25958 /* 67243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25959 /* 67247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25960 /* 67251 */ // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
25961 /* 67251 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_H),
25962 /* 67256 */ GIR_RootConstrainSelectedInstOperands,
25963 /* 67257 */ // GIR_Coverage, 869,
25964 /* 67257 */ GIR_Done,
25965 /* 67258 */ // Label 1684: @67258
25966 /* 67258 */ GIM_Reject,
25967 /* 67259 */ // Label 1680: @67259
25968 /* 67259 */ GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(67292), // Rule ID 868 //
25969 /* 67264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25970 /* 67267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25971 /* 67270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25972 /* 67273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25973 /* 67277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25974 /* 67281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25975 /* 67285 */ // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
25976 /* 67285 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_B),
25977 /* 67290 */ GIR_RootConstrainSelectedInstOperands,
25978 /* 67291 */ // GIR_Coverage, 868,
25979 /* 67291 */ GIR_Done,
25980 /* 67292 */ // Label 1685: @67292
25981 /* 67292 */ GIM_Reject,
25982 /* 67293 */ // Label 1681: @67293
25983 /* 67293 */ GIM_Reject,
25984 /* 67294 */ // Label 67: @67294
25985 /* 67294 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1690*/ GIMT_Encode4(67461),
25986 /* 67305 */ /*GILLT_v2s64*//*Label 1686*/ GIMT_Encode4(67325), GIMT_Encode4(0),
25987 /* 67313 */ /*GILLT_v4s32*//*Label 1687*/ GIMT_Encode4(67359),
25988 /* 67317 */ /*GILLT_v8s16*//*Label 1688*/ GIMT_Encode4(67393),
25989 /* 67321 */ /*GILLT_v16s8*//*Label 1689*/ GIMT_Encode4(67427),
25990 /* 67325 */ // Label 1686: @67325
25991 /* 67325 */ GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(67358), // Rule ID 851 //
25992 /* 67330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25993 /* 67333 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25994 /* 67336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25995 /* 67339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25996 /* 67343 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25997 /* 67347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25998 /* 67351 */ // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
25999 /* 67351 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_D),
26000 /* 67356 */ GIR_RootConstrainSelectedInstOperands,
26001 /* 67357 */ // GIR_Coverage, 851,
26002 /* 67357 */ GIR_Done,
26003 /* 67358 */ // Label 1691: @67358
26004 /* 67358 */ GIM_Reject,
26005 /* 67359 */ // Label 1687: @67359
26006 /* 67359 */ GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(67392), // Rule ID 850 //
26007 /* 67364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26008 /* 67367 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26009 /* 67370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26010 /* 67373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26011 /* 67377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26012 /* 67381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26013 /* 67385 */ // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26014 /* 67385 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_W),
26015 /* 67390 */ GIR_RootConstrainSelectedInstOperands,
26016 /* 67391 */ // GIR_Coverage, 850,
26017 /* 67391 */ GIR_Done,
26018 /* 67392 */ // Label 1692: @67392
26019 /* 67392 */ GIM_Reject,
26020 /* 67393 */ // Label 1688: @67393
26021 /* 67393 */ GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(67426), // Rule ID 849 //
26022 /* 67398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26023 /* 67401 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26024 /* 67404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26025 /* 67407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26026 /* 67411 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26027 /* 67415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26028 /* 67419 */ // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26029 /* 67419 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_H),
26030 /* 67424 */ GIR_RootConstrainSelectedInstOperands,
26031 /* 67425 */ // GIR_Coverage, 849,
26032 /* 67425 */ GIR_Done,
26033 /* 67426 */ // Label 1693: @67426
26034 /* 67426 */ GIM_Reject,
26035 /* 67427 */ // Label 1689: @67427
26036 /* 67427 */ GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(67460), // Rule ID 848 //
26037 /* 67432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26038 /* 67435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26039 /* 67438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26040 /* 67441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26041 /* 67445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26042 /* 67449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26043 /* 67453 */ // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26044 /* 67453 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_B),
26045 /* 67458 */ GIR_RootConstrainSelectedInstOperands,
26046 /* 67459 */ // GIR_Coverage, 848,
26047 /* 67459 */ GIR_Done,
26048 /* 67460 */ // Label 1694: @67460
26049 /* 67460 */ GIM_Reject,
26050 /* 67461 */ // Label 1690: @67461
26051 /* 67461 */ GIM_Reject,
26052 /* 67462 */ // Label 68: @67462
26053 /* 67462 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1699*/ GIMT_Encode4(67629),
26054 /* 67473 */ /*GILLT_v2s64*//*Label 1695*/ GIMT_Encode4(67493), GIMT_Encode4(0),
26055 /* 67481 */ /*GILLT_v4s32*//*Label 1696*/ GIMT_Encode4(67527),
26056 /* 67485 */ /*GILLT_v8s16*//*Label 1697*/ GIMT_Encode4(67561),
26057 /* 67489 */ /*GILLT_v16s8*//*Label 1698*/ GIMT_Encode4(67595),
26058 /* 67493 */ // Label 1695: @67493
26059 /* 67493 */ GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(67526), // Rule ID 875 //
26060 /* 67498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26061 /* 67501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26062 /* 67504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26063 /* 67507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26064 /* 67511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26065 /* 67515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26066 /* 67519 */ // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26067 /* 67519 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_D),
26068 /* 67524 */ GIR_RootConstrainSelectedInstOperands,
26069 /* 67525 */ // GIR_Coverage, 875,
26070 /* 67525 */ GIR_Done,
26071 /* 67526 */ // Label 1700: @67526
26072 /* 67526 */ GIM_Reject,
26073 /* 67527 */ // Label 1696: @67527
26074 /* 67527 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(67560), // Rule ID 874 //
26075 /* 67532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26076 /* 67535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26077 /* 67538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26078 /* 67541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26079 /* 67545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26080 /* 67549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26081 /* 67553 */ // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26082 /* 67553 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_W),
26083 /* 67558 */ GIR_RootConstrainSelectedInstOperands,
26084 /* 67559 */ // GIR_Coverage, 874,
26085 /* 67559 */ GIR_Done,
26086 /* 67560 */ // Label 1701: @67560
26087 /* 67560 */ GIM_Reject,
26088 /* 67561 */ // Label 1697: @67561
26089 /* 67561 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(67594), // Rule ID 873 //
26090 /* 67566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26091 /* 67569 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26092 /* 67572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26093 /* 67575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26094 /* 67579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26095 /* 67583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26096 /* 67587 */ // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26097 /* 67587 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_H),
26098 /* 67592 */ GIR_RootConstrainSelectedInstOperands,
26099 /* 67593 */ // GIR_Coverage, 873,
26100 /* 67593 */ GIR_Done,
26101 /* 67594 */ // Label 1702: @67594
26102 /* 67594 */ GIM_Reject,
26103 /* 67595 */ // Label 1698: @67595
26104 /* 67595 */ GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(67628), // Rule ID 872 //
26105 /* 67600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26106 /* 67603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26107 /* 67606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26108 /* 67609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26109 /* 67613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26110 /* 67617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26111 /* 67621 */ // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26112 /* 67621 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_B),
26113 /* 67626 */ GIR_RootConstrainSelectedInstOperands,
26114 /* 67627 */ // GIR_Coverage, 872,
26115 /* 67627 */ GIR_Done,
26116 /* 67628 */ // Label 1703: @67628
26117 /* 67628 */ GIM_Reject,
26118 /* 67629 */ // Label 1699: @67629
26119 /* 67629 */ GIM_Reject,
26120 /* 67630 */ // Label 69: @67630
26121 /* 67630 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1708*/ GIMT_Encode4(67797),
26122 /* 67641 */ /*GILLT_v2s64*//*Label 1704*/ GIMT_Encode4(67661), GIMT_Encode4(0),
26123 /* 67649 */ /*GILLT_v4s32*//*Label 1705*/ GIMT_Encode4(67695),
26124 /* 67653 */ /*GILLT_v8s16*//*Label 1706*/ GIMT_Encode4(67729),
26125 /* 67657 */ /*GILLT_v16s8*//*Label 1707*/ GIMT_Encode4(67763),
26126 /* 67661 */ // Label 1704: @67661
26127 /* 67661 */ GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(67694), // Rule ID 855 //
26128 /* 67666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26129 /* 67669 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26130 /* 67672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26131 /* 67675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26132 /* 67679 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26133 /* 67683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26134 /* 67687 */ // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26135 /* 67687 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_D),
26136 /* 67692 */ GIR_RootConstrainSelectedInstOperands,
26137 /* 67693 */ // GIR_Coverage, 855,
26138 /* 67693 */ GIR_Done,
26139 /* 67694 */ // Label 1709: @67694
26140 /* 67694 */ GIM_Reject,
26141 /* 67695 */ // Label 1705: @67695
26142 /* 67695 */ GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(67728), // Rule ID 854 //
26143 /* 67700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26144 /* 67703 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26145 /* 67706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26146 /* 67709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26147 /* 67713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26148 /* 67717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26149 /* 67721 */ // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26150 /* 67721 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_W),
26151 /* 67726 */ GIR_RootConstrainSelectedInstOperands,
26152 /* 67727 */ // GIR_Coverage, 854,
26153 /* 67727 */ GIR_Done,
26154 /* 67728 */ // Label 1710: @67728
26155 /* 67728 */ GIM_Reject,
26156 /* 67729 */ // Label 1706: @67729
26157 /* 67729 */ GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(67762), // Rule ID 853 //
26158 /* 67734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26159 /* 67737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26160 /* 67740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26161 /* 67743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26162 /* 67747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26163 /* 67751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26164 /* 67755 */ // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26165 /* 67755 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_H),
26166 /* 67760 */ GIR_RootConstrainSelectedInstOperands,
26167 /* 67761 */ // GIR_Coverage, 853,
26168 /* 67761 */ GIR_Done,
26169 /* 67762 */ // Label 1711: @67762
26170 /* 67762 */ GIM_Reject,
26171 /* 67763 */ // Label 1707: @67763
26172 /* 67763 */ GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(67796), // Rule ID 852 //
26173 /* 67768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26174 /* 67771 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26175 /* 67774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26176 /* 67777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26177 /* 67781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26178 /* 67785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26179 /* 67789 */ // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26180 /* 67789 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_B),
26181 /* 67794 */ GIR_RootConstrainSelectedInstOperands,
26182 /* 67795 */ // GIR_Coverage, 852,
26183 /* 67795 */ GIR_Done,
26184 /* 67796 */ // Label 1712: @67796
26185 /* 67796 */ GIM_Reject,
26186 /* 67797 */ // Label 1708: @67797
26187 /* 67797 */ GIM_Reject,
26188 /* 67798 */ // Label 70: @67798
26189 /* 67798 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(67921),
26190 /* 67803 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
26191 /* 67806 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(67827), // Rule ID 91 //
26192 /* 67811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC),
26193 /* 67814 */ // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target)
26194 /* 67814 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J),
26195 /* 67819 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
26196 /* 67825 */ GIR_RootConstrainSelectedInstOperands,
26197 /* 67826 */ // GIR_Coverage, 91,
26198 /* 67826 */ GIR_Done,
26199 /* 67827 */ // Label 1714: @67827
26200 /* 67827 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(67848), // Rule ID 98 //
26201 /* 67832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
26202 /* 67835 */ // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset)
26203 /* 67835 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B),
26204 /* 67840 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
26205 /* 67846 */ GIR_RootConstrainSelectedInstOperands,
26206 /* 67847 */ // GIR_Coverage, 98,
26207 /* 67847 */ GIR_Done,
26208 /* 67848 */ // Label 1715: @67848
26209 /* 67848 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(67869), // Rule ID 1104 //
26210 /* 67853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocNotPIC),
26211 /* 67856 */ // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target)
26212 /* 67856 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J_MM),
26213 /* 67861 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
26214 /* 67867 */ GIR_RootConstrainSelectedInstOperands,
26215 /* 67868 */ // GIR_Coverage, 1104,
26216 /* 67868 */ GIR_Done,
26217 /* 67869 */ // Label 1716: @67869
26218 /* 67869 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(67890), // Rule ID 1113 //
26219 /* 67874 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocPIC),
26220 /* 67877 */ // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset)
26221 /* 67877 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B_MM),
26222 /* 67882 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
26223 /* 67888 */ GIR_RootConstrainSelectedInstOperands,
26224 /* 67889 */ // GIR_Coverage, 1113,
26225 /* 67889 */ GIR_Done,
26226 /* 67890 */ // Label 1717: @67890
26227 /* 67890 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(67905), // Rule ID 1171 //
26228 /* 67895 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
26229 /* 67898 */ // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset)
26230 /* 67898 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BC_MMR6),
26231 /* 67903 */ GIR_RootConstrainSelectedInstOperands,
26232 /* 67904 */ // GIR_Coverage, 1171,
26233 /* 67904 */ GIR_Done,
26234 /* 67905 */ // Label 1718: @67905
26235 /* 67905 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(67920), // Rule ID 1867 //
26236 /* 67910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
26237 /* 67913 */ // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16)
26238 /* 67913 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Bimm16),
26239 /* 67918 */ GIR_RootConstrainSelectedInstOperands,
26240 /* 67919 */ // GIR_Coverage, 1867,
26241 /* 67919 */ GIR_Done,
26242 /* 67920 */ // Label 1719: @67920
26243 /* 67920 */ GIM_Reject,
26244 /* 67921 */ // Label 1713: @67921
26245 /* 67921 */ GIM_Reject,
26246 /* 67922 */ // Label 71: @67922
26247 /* 67922 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1724*/ GIMT_Encode4(68485),
26248 /* 67933 */ /*GILLT_v2s64*//*Label 1720*/ GIMT_Encode4(67953), GIMT_Encode4(0),
26249 /* 67941 */ /*GILLT_v4s32*//*Label 1721*/ GIMT_Encode4(68126),
26250 /* 67945 */ /*GILLT_v8s16*//*Label 1722*/ GIMT_Encode4(68299),
26251 /* 67949 */ /*GILLT_v16s8*//*Label 1723*/ GIMT_Encode4(68392),
26252 /* 67953 */ // Label 1720: @67953
26253 /* 67953 */ GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(68125),
26254 /* 67958 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26255 /* 67961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26256 /* 67964 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(68004), // Rule ID 821 //
26257 /* 67969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26258 /* 67972 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26259 /* 67975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26260 /* 67979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26261 /* 67983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26262 /* 67987 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26263 /* 67991 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_D_VIDX_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
26264 /* 67991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX_PSEUDO),
26265 /* 67994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26266 /* 67996 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26267 /* 67998 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26268 /* 68000 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26269 /* 68002 */ GIR_RootConstrainSelectedInstOperands,
26270 /* 68003 */ // GIR_Coverage, 821,
26271 /* 68003 */ GIR_EraseRootFromParent_Done,
26272 /* 68004 */ // Label 1726: @68004
26273 /* 68004 */ GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(68044), // Rule ID 823 //
26274 /* 68009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26275 /* 68012 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26276 /* 68015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26277 /* 68019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26278 /* 68023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26279 /* 68027 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26280 /* 68031 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FD_VIDX_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
26281 /* 68031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX_PSEUDO),
26282 /* 68034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26283 /* 68036 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26284 /* 68038 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26285 /* 68040 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26286 /* 68042 */ GIR_RootConstrainSelectedInstOperands,
26287 /* 68043 */ // GIR_Coverage, 823,
26288 /* 68043 */ GIR_EraseRootFromParent_Done,
26289 /* 68044 */ // Label 1727: @68044
26290 /* 68044 */ GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(68084), // Rule ID 827 //
26291 /* 68049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26292 /* 68052 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26293 /* 68055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26294 /* 68059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26295 /* 68063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26296 /* 68067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26297 /* 68071 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_D_VIDX64_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
26298 /* 68071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX64_PSEUDO),
26299 /* 68074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26300 /* 68076 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26301 /* 68078 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26302 /* 68080 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26303 /* 68082 */ GIR_RootConstrainSelectedInstOperands,
26304 /* 68083 */ // GIR_Coverage, 827,
26305 /* 68083 */ GIR_EraseRootFromParent_Done,
26306 /* 68084 */ // Label 1728: @68084
26307 /* 68084 */ GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(68124), // Rule ID 829 //
26308 /* 68089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26309 /* 68092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26310 /* 68095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26311 /* 68099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26312 /* 68103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26313 /* 68107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26314 /* 68111 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FD_VIDX64_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
26315 /* 68111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX64_PSEUDO),
26316 /* 68114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26317 /* 68116 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26318 /* 68118 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26319 /* 68120 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26320 /* 68122 */ GIR_RootConstrainSelectedInstOperands,
26321 /* 68123 */ // GIR_Coverage, 829,
26322 /* 68123 */ GIR_EraseRootFromParent_Done,
26323 /* 68124 */ // Label 1729: @68124
26324 /* 68124 */ GIM_Reject,
26325 /* 68125 */ // Label 1725: @68125
26326 /* 68125 */ GIM_Reject,
26327 /* 68126 */ // Label 1721: @68126
26328 /* 68126 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(68298),
26329 /* 68131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26330 /* 68134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26331 /* 68137 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(68177), // Rule ID 820 //
26332 /* 68142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26333 /* 68145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26334 /* 68148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26335 /* 68152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26336 /* 68156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26337 /* 68160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26338 /* 68164 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_W_VIDX_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26339 /* 68164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX_PSEUDO),
26340 /* 68167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26341 /* 68169 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26342 /* 68171 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26343 /* 68173 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26344 /* 68175 */ GIR_RootConstrainSelectedInstOperands,
26345 /* 68176 */ // GIR_Coverage, 820,
26346 /* 68176 */ GIR_EraseRootFromParent_Done,
26347 /* 68177 */ // Label 1731: @68177
26348 /* 68177 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(68217), // Rule ID 822 //
26349 /* 68182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26350 /* 68185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26351 /* 68188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26352 /* 68192 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26353 /* 68196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26354 /* 68200 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26355 /* 68204 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FW_VIDX_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
26356 /* 68204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX_PSEUDO),
26357 /* 68207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26358 /* 68209 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26359 /* 68211 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26360 /* 68213 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26361 /* 68215 */ GIR_RootConstrainSelectedInstOperands,
26362 /* 68216 */ // GIR_Coverage, 822,
26363 /* 68216 */ GIR_EraseRootFromParent_Done,
26364 /* 68217 */ // Label 1732: @68217
26365 /* 68217 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(68257), // Rule ID 826 //
26366 /* 68222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26367 /* 68225 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26368 /* 68228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26369 /* 68232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26370 /* 68236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26371 /* 68240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26372 /* 68244 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_W_VIDX64_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26373 /* 68244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX64_PSEUDO),
26374 /* 68247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26375 /* 68249 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26376 /* 68251 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26377 /* 68253 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26378 /* 68255 */ GIR_RootConstrainSelectedInstOperands,
26379 /* 68256 */ // GIR_Coverage, 826,
26380 /* 68256 */ GIR_EraseRootFromParent_Done,
26381 /* 68257 */ // Label 1733: @68257
26382 /* 68257 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(68297), // Rule ID 828 //
26383 /* 68262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26384 /* 68265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26385 /* 68268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26386 /* 68272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26387 /* 68276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26388 /* 68280 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26389 /* 68284 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FW_VIDX64_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
26390 /* 68284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX64_PSEUDO),
26391 /* 68287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26392 /* 68289 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26393 /* 68291 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26394 /* 68293 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26395 /* 68295 */ GIR_RootConstrainSelectedInstOperands,
26396 /* 68296 */ // GIR_Coverage, 828,
26397 /* 68296 */ GIR_EraseRootFromParent_Done,
26398 /* 68297 */ // Label 1734: @68297
26399 /* 68297 */ GIM_Reject,
26400 /* 68298 */ // Label 1730: @68298
26401 /* 68298 */ GIM_Reject,
26402 /* 68299 */ // Label 1722: @68299
26403 /* 68299 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(68391),
26404 /* 68304 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26405 /* 68307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26406 /* 68310 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(68350), // Rule ID 819 //
26407 /* 68315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26408 /* 68318 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26409 /* 68321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26410 /* 68325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26411 /* 68329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26412 /* 68333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26413 /* 68337 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_H_VIDX_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26414 /* 68337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX_PSEUDO),
26415 /* 68340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26416 /* 68342 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26417 /* 68344 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26418 /* 68346 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26419 /* 68348 */ GIR_RootConstrainSelectedInstOperands,
26420 /* 68349 */ // GIR_Coverage, 819,
26421 /* 68349 */ GIR_EraseRootFromParent_Done,
26422 /* 68350 */ // Label 1736: @68350
26423 /* 68350 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(68390), // Rule ID 825 //
26424 /* 68355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26425 /* 68358 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26426 /* 68361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26427 /* 68365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26428 /* 68369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26429 /* 68373 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26430 /* 68377 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_H_VIDX64_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26431 /* 68377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX64_PSEUDO),
26432 /* 68380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26433 /* 68382 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26434 /* 68384 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26435 /* 68386 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26436 /* 68388 */ GIR_RootConstrainSelectedInstOperands,
26437 /* 68389 */ // GIR_Coverage, 825,
26438 /* 68389 */ GIR_EraseRootFromParent_Done,
26439 /* 68390 */ // Label 1737: @68390
26440 /* 68390 */ GIM_Reject,
26441 /* 68391 */ // Label 1735: @68391
26442 /* 68391 */ GIM_Reject,
26443 /* 68392 */ // Label 1723: @68392
26444 /* 68392 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(68484),
26445 /* 68397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26446 /* 68400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26447 /* 68403 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(68443), // Rule ID 818 //
26448 /* 68408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26449 /* 68411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26450 /* 68414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26451 /* 68418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26452 /* 68422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26453 /* 68426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26454 /* 68430 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_B_VIDX_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26455 /* 68430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX_PSEUDO),
26456 /* 68433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26457 /* 68435 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26458 /* 68437 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26459 /* 68439 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26460 /* 68441 */ GIR_RootConstrainSelectedInstOperands,
26461 /* 68442 */ // GIR_Coverage, 818,
26462 /* 68442 */ GIR_EraseRootFromParent_Done,
26463 /* 68443 */ // Label 1739: @68443
26464 /* 68443 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(68483), // Rule ID 824 //
26465 /* 68448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26466 /* 68451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26467 /* 68454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26468 /* 68458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26469 /* 68462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26470 /* 68466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26471 /* 68470 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_B_VIDX64_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26472 /* 68470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX64_PSEUDO),
26473 /* 68473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26474 /* 68475 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26475 /* 68477 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26476 /* 68479 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26477 /* 68481 */ GIR_RootConstrainSelectedInstOperands,
26478 /* 68482 */ // GIR_Coverage, 824,
26479 /* 68482 */ GIR_EraseRootFromParent_Done,
26480 /* 68483 */ // Label 1740: @68483
26481 /* 68483 */ GIM_Reject,
26482 /* 68484 */ // Label 1738: @68484
26483 /* 68484 */ GIM_Reject,
26484 /* 68485 */ // Label 1724: @68485
26485 /* 68485 */ GIM_Reject,
26486 /* 68486 */ // Label 72: @68486
26487 /* 68486 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(68537), // Rule ID 1994 //
26488 /* 68491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
26489 /* 68494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26490 /* 68497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26491 /* 68500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26492 /* 68503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26493 /* 68507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26494 /* 68511 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26495 /* 68515 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26496 /* 68519 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
26497 /* 68523 */ // MIs[1] Operand 1
26498 /* 68523 */ // No operand predicates
26499 /* 68523 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26500 /* 68525 */ // (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx) => (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
26501 /* 68525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::COPY_S_W),
26502 /* 68528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26503 /* 68530 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
26504 /* 68532 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
26505 /* 68535 */ GIR_RootConstrainSelectedInstOperands,
26506 /* 68536 */ // GIR_Coverage, 1994,
26507 /* 68536 */ GIR_EraseRootFromParent_Done,
26508 /* 68537 */ // Label 1741: @68537
26509 /* 68537 */ GIM_Reject,
26510 /* 68538 */ // Label 73: @68538
26511 /* 68538 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1748*/ GIMT_Encode4(69042),
26512 /* 68549 */ /*GILLT_s32*//*Label 1742*/ GIMT_Encode4(68581),
26513 /* 68553 */ /*GILLT_s64*//*Label 1743*/ GIMT_Encode4(68790), GIMT_Encode4(0),
26514 /* 68561 */ /*GILLT_v2s64*//*Label 1744*/ GIMT_Encode4(68934), GIMT_Encode4(0),
26515 /* 68569 */ /*GILLT_v4s32*//*Label 1745*/ GIMT_Encode4(68961),
26516 /* 68573 */ /*GILLT_v8s16*//*Label 1746*/ GIMT_Encode4(68988),
26517 /* 68577 */ /*GILLT_v16s8*//*Label 1747*/ GIMT_Encode4(69015),
26518 /* 68581 */ // Label 1742: @68581
26519 /* 68581 */ GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(68789),
26520 /* 68586 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26521 /* 68589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26522 /* 68593 */ GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(68639), // Rule ID 109 //
26523 /* 68598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
26524 /* 68601 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26525 /* 68605 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26526 /* 68609 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26527 /* 68613 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26528 /* 68617 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26529 /* 68622 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
26530 /* 68626 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26531 /* 68628 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26532 /* 68628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO),
26533 /* 68631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26534 /* 68633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26535 /* 68637 */ GIR_RootConstrainSelectedInstOperands,
26536 /* 68638 */ // GIR_Coverage, 109,
26537 /* 68638 */ GIR_EraseRootFromParent_Done,
26538 /* 68639 */ // Label 1750: @68639
26539 /* 68639 */ GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(68685), // Rule ID 310 //
26540 /* 68644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
26541 /* 68647 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26542 /* 68651 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26543 /* 68655 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26544 /* 68659 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26545 /* 68663 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26546 /* 68668 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
26547 /* 68672 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26548 /* 68674 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26549 /* 68674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_R6),
26550 /* 68677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26551 /* 68679 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26552 /* 68683 */ GIR_RootConstrainSelectedInstOperands,
26553 /* 68684 */ // GIR_Coverage, 310,
26554 /* 68684 */ GIR_EraseRootFromParent_Done,
26555 /* 68685 */ // Label 1751: @68685
26556 /* 68685 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(68731), // Rule ID 1100 //
26557 /* 68690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
26558 /* 68693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26559 /* 68697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26560 /* 68701 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26561 /* 68705 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26562 /* 68709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26563 /* 68714 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
26564 /* 68718 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26565 /* 68720 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26566 /* 68720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_MM),
26567 /* 68723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26568 /* 68725 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26569 /* 68729 */ GIR_RootConstrainSelectedInstOperands,
26570 /* 68730 */ // GIR_Coverage, 1100,
26571 /* 68730 */ GIR_EraseRootFromParent_Done,
26572 /* 68731 */ // Label 1752: @68731
26573 /* 68731 */ GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(68750), // Rule ID 108 //
26574 /* 68736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
26575 /* 68739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26576 /* 68743 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26577 /* 68743 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ),
26578 /* 68748 */ GIR_RootConstrainSelectedInstOperands,
26579 /* 68749 */ // GIR_Coverage, 108,
26580 /* 68749 */ GIR_Done,
26581 /* 68750 */ // Label 1753: @68750
26582 /* 68750 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(68769), // Rule ID 311 //
26583 /* 68755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
26584 /* 68758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26585 /* 68762 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26586 /* 68762 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_R6),
26587 /* 68767 */ GIR_RootConstrainSelectedInstOperands,
26588 /* 68768 */ // GIR_Coverage, 311,
26589 /* 68768 */ GIR_Done,
26590 /* 68769 */ // Label 1754: @68769
26591 /* 68769 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(68788), // Rule ID 1099 //
26592 /* 68774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
26593 /* 68777 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26594 /* 68781 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26595 /* 68781 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_MM),
26596 /* 68786 */ GIR_RootConstrainSelectedInstOperands,
26597 /* 68787 */ // GIR_Coverage, 1099,
26598 /* 68787 */ GIR_Done,
26599 /* 68788 */ // Label 1755: @68788
26600 /* 68788 */ GIM_Reject,
26601 /* 68789 */ // Label 1749: @68789
26602 /* 68789 */ GIM_Reject,
26603 /* 68790 */ // Label 1743: @68790
26604 /* 68790 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(68933),
26605 /* 68795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26606 /* 68798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26607 /* 68802 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(68848), // Rule ID 264 //
26608 /* 68807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
26609 /* 68810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26610 /* 68814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26611 /* 68818 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
26612 /* 68822 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
26613 /* 68826 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26614 /* 68831 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
26615 /* 68835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26616 /* 68837 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26617 /* 68837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO),
26618 /* 68840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26619 /* 68842 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26620 /* 68846 */ GIR_RootConstrainSelectedInstOperands,
26621 /* 68847 */ // GIR_Coverage, 264,
26622 /* 68847 */ GIR_EraseRootFromParent_Done,
26623 /* 68848 */ // Label 1757: @68848
26624 /* 68848 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(68894), // Rule ID 339 //
26625 /* 68853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
26626 /* 68856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26627 /* 68860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26628 /* 68864 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
26629 /* 68868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
26630 /* 68872 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26631 /* 68877 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
26632 /* 68881 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26633 /* 68883 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26634 /* 68883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO_R6),
26635 /* 68886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26636 /* 68888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26637 /* 68892 */ GIR_RootConstrainSelectedInstOperands,
26638 /* 68893 */ // GIR_Coverage, 339,
26639 /* 68893 */ GIR_EraseRootFromParent_Done,
26640 /* 68894 */ // Label 1758: @68894
26641 /* 68894 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(68913), // Rule ID 263 //
26642 /* 68899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
26643 /* 68902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26644 /* 68906 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26645 /* 68906 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ),
26646 /* 68911 */ GIR_RootConstrainSelectedInstOperands,
26647 /* 68912 */ // GIR_Coverage, 263,
26648 /* 68912 */ GIR_Done,
26649 /* 68913 */ // Label 1759: @68913
26650 /* 68913 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(68932), // Rule ID 340 //
26651 /* 68918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
26652 /* 68921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26653 /* 68925 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26654 /* 68925 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ_R6),
26655 /* 68930 */ GIR_RootConstrainSelectedInstOperands,
26656 /* 68931 */ // GIR_Coverage, 340,
26657 /* 68931 */ GIR_Done,
26658 /* 68932 */ // Label 1760: @68932
26659 /* 68932 */ GIM_Reject,
26660 /* 68933 */ // Label 1756: @68933
26661 /* 68933 */ GIM_Reject,
26662 /* 68934 */ // Label 1744: @68934
26663 /* 68934 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(68960), // Rule ID 915 //
26664 /* 68939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26665 /* 68942 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26666 /* 68945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26667 /* 68949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26668 /* 68953 */ // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
26669 /* 68953 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_D),
26670 /* 68958 */ GIR_RootConstrainSelectedInstOperands,
26671 /* 68959 */ // GIR_Coverage, 915,
26672 /* 68959 */ GIR_Done,
26673 /* 68960 */ // Label 1761: @68960
26674 /* 68960 */ GIM_Reject,
26675 /* 68961 */ // Label 1745: @68961
26676 /* 68961 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(68987), // Rule ID 914 //
26677 /* 68966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26678 /* 68969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26679 /* 68972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26680 /* 68976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26681 /* 68980 */ // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
26682 /* 68980 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_W),
26683 /* 68985 */ GIR_RootConstrainSelectedInstOperands,
26684 /* 68986 */ // GIR_Coverage, 914,
26685 /* 68986 */ GIR_Done,
26686 /* 68987 */ // Label 1762: @68987
26687 /* 68987 */ GIM_Reject,
26688 /* 68988 */ // Label 1746: @68988
26689 /* 68988 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(69014), // Rule ID 913 //
26690 /* 68993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26691 /* 68996 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26692 /* 68999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26693 /* 69003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26694 /* 69007 */ // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
26695 /* 69007 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_H),
26696 /* 69012 */ GIR_RootConstrainSelectedInstOperands,
26697 /* 69013 */ // GIR_Coverage, 913,
26698 /* 69013 */ GIR_Done,
26699 /* 69014 */ // Label 1763: @69014
26700 /* 69014 */ GIM_Reject,
26701 /* 69015 */ // Label 1747: @69015
26702 /* 69015 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(69041), // Rule ID 912 //
26703 /* 69020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26704 /* 69023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26705 /* 69026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26706 /* 69030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26707 /* 69034 */ // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
26708 /* 69034 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_B),
26709 /* 69039 */ GIR_RootConstrainSelectedInstOperands,
26710 /* 69040 */ // GIR_Coverage, 912,
26711 /* 69040 */ GIR_Done,
26712 /* 69041 */ // Label 1764: @69041
26713 /* 69041 */ GIM_Reject,
26714 /* 69042 */ // Label 1748: @69042
26715 /* 69042 */ GIM_Reject,
26716 /* 69043 */ // Label 74: @69043
26717 /* 69043 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1771*/ GIMT_Encode4(69248),
26718 /* 69054 */ /*GILLT_s32*//*Label 1765*/ GIMT_Encode4(69086),
26719 /* 69058 */ /*GILLT_s64*//*Label 1766*/ GIMT_Encode4(69113), GIMT_Encode4(0),
26720 /* 69066 */ /*GILLT_v2s64*//*Label 1767*/ GIMT_Encode4(69140), GIMT_Encode4(0),
26721 /* 69074 */ /*GILLT_v4s32*//*Label 1768*/ GIMT_Encode4(69167),
26722 /* 69078 */ /*GILLT_v8s16*//*Label 1769*/ GIMT_Encode4(69194),
26723 /* 69082 */ /*GILLT_v16s8*//*Label 1770*/ GIMT_Encode4(69221),
26724 /* 69086 */ // Label 1765: @69086
26725 /* 69086 */ GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(69112), // Rule ID 278 //
26726 /* 69091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
26727 /* 69094 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26728 /* 69097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26729 /* 69101 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26730 /* 69105 */ // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26731 /* 69105 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::POP),
26732 /* 69110 */ GIR_RootConstrainSelectedInstOperands,
26733 /* 69111 */ // GIR_Coverage, 278,
26734 /* 69111 */ GIR_Done,
26735 /* 69112 */ // Label 1772: @69112
26736 /* 69112 */ GIM_Reject,
26737 /* 69113 */ // Label 1766: @69113
26738 /* 69113 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(69139), // Rule ID 279 //
26739 /* 69118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
26740 /* 69121 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26741 /* 69124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26742 /* 69128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26743 /* 69132 */ // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26744 /* 69132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DPOP),
26745 /* 69137 */ GIR_RootConstrainSelectedInstOperands,
26746 /* 69138 */ // GIR_Coverage, 279,
26747 /* 69138 */ GIR_Done,
26748 /* 69139 */ // Label 1773: @69139
26749 /* 69139 */ GIM_Reject,
26750 /* 69140 */ // Label 1767: @69140
26751 /* 69140 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(69166), // Rule ID 937 //
26752 /* 69145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26753 /* 69148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26754 /* 69151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26755 /* 69155 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26756 /* 69159 */ // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
26757 /* 69159 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_D),
26758 /* 69164 */ GIR_RootConstrainSelectedInstOperands,
26759 /* 69165 */ // GIR_Coverage, 937,
26760 /* 69165 */ GIR_Done,
26761 /* 69166 */ // Label 1774: @69166
26762 /* 69166 */ GIM_Reject,
26763 /* 69167 */ // Label 1768: @69167
26764 /* 69167 */ GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(69193), // Rule ID 936 //
26765 /* 69172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26766 /* 69175 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26767 /* 69178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26768 /* 69182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26769 /* 69186 */ // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
26770 /* 69186 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_W),
26771 /* 69191 */ GIR_RootConstrainSelectedInstOperands,
26772 /* 69192 */ // GIR_Coverage, 936,
26773 /* 69192 */ GIR_Done,
26774 /* 69193 */ // Label 1775: @69193
26775 /* 69193 */ GIM_Reject,
26776 /* 69194 */ // Label 1769: @69194
26777 /* 69194 */ GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(69220), // Rule ID 935 //
26778 /* 69199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26779 /* 69202 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26780 /* 69205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26781 /* 69209 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26782 /* 69213 */ // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
26783 /* 69213 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_H),
26784 /* 69218 */ GIR_RootConstrainSelectedInstOperands,
26785 /* 69219 */ // GIR_Coverage, 935,
26786 /* 69219 */ GIR_Done,
26787 /* 69220 */ // Label 1776: @69220
26788 /* 69220 */ GIM_Reject,
26789 /* 69221 */ // Label 1770: @69221
26790 /* 69221 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(69247), // Rule ID 934 //
26791 /* 69226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26792 /* 69229 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26793 /* 69232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26794 /* 69236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26795 /* 69240 */ // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
26796 /* 69240 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_B),
26797 /* 69245 */ GIR_RootConstrainSelectedInstOperands,
26798 /* 69246 */ // GIR_Coverage, 934,
26799 /* 69246 */ GIR_Done,
26800 /* 69247 */ // Label 1777: @69247
26801 /* 69247 */ GIM_Reject,
26802 /* 69248 */ // Label 1771: @69248
26803 /* 69248 */ GIM_Reject,
26804 /* 69249 */ // Label 75: @69249
26805 /* 69249 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1780*/ GIMT_Encode4(69412),
26806 /* 69260 */ /*GILLT_s32*//*Label 1778*/ GIMT_Encode4(69268),
26807 /* 69264 */ /*GILLT_s64*//*Label 1779*/ GIMT_Encode4(69364),
26808 /* 69268 */ // Label 1778: @69268
26809 /* 69268 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(69363),
26810 /* 69273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26811 /* 69276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26812 /* 69280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26813 /* 69284 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(69323), // Rule ID 1427 //
26814 /* 69289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
26815 /* 69292 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
26816 /* 69292 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
26817 /* 69295 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH),
26818 /* 69299 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26819 /* 69304 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
26820 /* 69308 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26821 /* 69310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
26822 /* 69313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26823 /* 69315 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26824 /* 69318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
26825 /* 69321 */ GIR_RootConstrainSelectedInstOperands,
26826 /* 69322 */ // GIR_Coverage, 1427,
26827 /* 69322 */ GIR_EraseRootFromParent_Done,
26828 /* 69323 */ // Label 1782: @69323
26829 /* 69323 */ GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(69362), // Rule ID 2191 //
26830 /* 69328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
26831 /* 69331 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
26832 /* 69331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
26833 /* 69334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH_MM),
26834 /* 69338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26835 /* 69343 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
26836 /* 69347 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26837 /* 69349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
26838 /* 69352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26839 /* 69354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26840 /* 69357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
26841 /* 69360 */ GIR_RootConstrainSelectedInstOperands,
26842 /* 69361 */ // GIR_Coverage, 2191,
26843 /* 69361 */ GIR_EraseRootFromParent_Done,
26844 /* 69362 */ // Label 1783: @69362
26845 /* 69362 */ GIM_Reject,
26846 /* 69363 */ // Label 1781: @69363
26847 /* 69363 */ GIM_Reject,
26848 /* 69364 */ // Label 1779: @69364
26849 /* 69364 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(69411), // Rule ID 1589 //
26850 /* 69369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc),
26851 /* 69372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26852 /* 69375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26853 /* 69379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26854 /* 69383 */ // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
26855 /* 69383 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
26856 /* 69386 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSBH),
26857 /* 69390 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26858 /* 69395 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
26859 /* 69399 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26860 /* 69401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSHD),
26861 /* 69404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26862 /* 69406 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26863 /* 69409 */ GIR_RootConstrainSelectedInstOperands,
26864 /* 69410 */ // GIR_Coverage, 1589,
26865 /* 69410 */ GIR_EraseRootFromParent_Done,
26866 /* 69411 */ // Label 1784: @69411
26867 /* 69411 */ GIM_Reject,
26868 /* 69412 */ // Label 1780: @69412
26869 /* 69412 */ GIM_Reject,
26870 /* 69413 */ // Label 76: @69413
26871 /* 69413 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1789*/ GIMT_Encode4(69652),
26872 /* 69424 */ /*GILLT_s32*//*Label 1785*/ GIMT_Encode4(69448),
26873 /* 69428 */ /*GILLT_s64*//*Label 1786*/ GIMT_Encode4(69496), GIMT_Encode4(0),
26874 /* 69436 */ /*GILLT_v2s64*//*Label 1787*/ GIMT_Encode4(69598), GIMT_Encode4(0),
26875 /* 69444 */ /*GILLT_v4s32*//*Label 1788*/ GIMT_Encode4(69625),
26876 /* 69448 */ // Label 1785: @69448
26877 /* 69448 */ GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(69495),
26878 /* 69453 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26879 /* 69456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26880 /* 69460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26881 /* 69464 */ GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(69479), // Rule ID 132 //
26882 /* 69469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
26883 /* 69472 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
26884 /* 69472 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
26885 /* 69477 */ GIR_RootConstrainSelectedInstOperands,
26886 /* 69478 */ // GIR_Coverage, 132,
26887 /* 69478 */ GIR_Done,
26888 /* 69479 */ // Label 1791: @69479
26889 /* 69479 */ GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(69494), // Rule ID 1162 //
26890 /* 69484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
26891 /* 69487 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
26892 /* 69487 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S_MM),
26893 /* 69492 */ GIR_RootConstrainSelectedInstOperands,
26894 /* 69493 */ // GIR_Coverage, 1162,
26895 /* 69493 */ GIR_Done,
26896 /* 69494 */ // Label 1792: @69494
26897 /* 69494 */ GIM_Reject,
26898 /* 69495 */ // Label 1790: @69495
26899 /* 69495 */ GIM_Reject,
26900 /* 69496 */ // Label 1786: @69496
26901 /* 69496 */ GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(69597),
26902 /* 69501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26903 /* 69504 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(69527), // Rule ID 133 //
26904 /* 69509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
26905 /* 69512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26906 /* 69516 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26907 /* 69520 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
26908 /* 69520 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
26909 /* 69525 */ GIR_RootConstrainSelectedInstOperands,
26910 /* 69526 */ // GIR_Coverage, 133,
26911 /* 69526 */ GIR_Done,
26912 /* 69527 */ // Label 1794: @69527
26913 /* 69527 */ GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(69550), // Rule ID 134 //
26914 /* 69532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
26915 /* 69535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26916 /* 69539 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26917 /* 69543 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
26918 /* 69543 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
26919 /* 69548 */ GIR_RootConstrainSelectedInstOperands,
26920 /* 69549 */ // GIR_Coverage, 134,
26921 /* 69549 */ GIR_Done,
26922 /* 69550 */ // Label 1795: @69550
26923 /* 69550 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(69573), // Rule ID 1148 //
26924 /* 69555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
26925 /* 69558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26926 /* 69562 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26927 /* 69566 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
26928 /* 69566 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32_MM),
26929 /* 69571 */ GIR_RootConstrainSelectedInstOperands,
26930 /* 69572 */ // GIR_Coverage, 1148,
26931 /* 69572 */ GIR_Done,
26932 /* 69573 */ // Label 1796: @69573
26933 /* 69573 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(69596), // Rule ID 1149 //
26934 /* 69578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
26935 /* 69581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26936 /* 69585 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26937 /* 69589 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
26938 /* 69589 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64_MM),
26939 /* 69594 */ GIR_RootConstrainSelectedInstOperands,
26940 /* 69595 */ // GIR_Coverage, 1149,
26941 /* 69595 */ GIR_Done,
26942 /* 69596 */ // Label 1797: @69596
26943 /* 69596 */ GIM_Reject,
26944 /* 69597 */ // Label 1793: @69597
26945 /* 69597 */ GIM_Reject,
26946 /* 69598 */ // Label 1787: @69598
26947 /* 69598 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(69624), // Rule ID 757 //
26948 /* 69603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26949 /* 69606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26950 /* 69609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26951 /* 69613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26952 /* 69617 */ // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
26953 /* 69617 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D),
26954 /* 69622 */ GIR_RootConstrainSelectedInstOperands,
26955 /* 69623 */ // GIR_Coverage, 757,
26956 /* 69623 */ GIR_Done,
26957 /* 69624 */ // Label 1798: @69624
26958 /* 69624 */ GIM_Reject,
26959 /* 69625 */ // Label 1788: @69625
26960 /* 69625 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(69651), // Rule ID 756 //
26961 /* 69630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26962 /* 69633 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26963 /* 69636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26964 /* 69640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26965 /* 69644 */ // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
26966 /* 69644 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_W),
26967 /* 69649 */ GIR_RootConstrainSelectedInstOperands,
26968 /* 69650 */ // GIR_Coverage, 756,
26969 /* 69650 */ GIR_Done,
26970 /* 69651 */ // Label 1799: @69651
26971 /* 69651 */ GIM_Reject,
26972 /* 69652 */ // Label 1789: @69652
26973 /* 69652 */ GIM_Reject,
26974 /* 69653 */ // Label 77: @69653
26975 /* 69653 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1802*/ GIMT_Encode4(69730),
26976 /* 69664 */ /*GILLT_v2s64*//*Label 1800*/ GIMT_Encode4(69676), GIMT_Encode4(0),
26977 /* 69672 */ /*GILLT_v4s32*//*Label 1801*/ GIMT_Encode4(69703),
26978 /* 69676 */ // Label 1800: @69676
26979 /* 69676 */ GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(69702), // Rule ID 739 //
26980 /* 69681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26981 /* 69684 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26982 /* 69687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26983 /* 69691 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26984 /* 69695 */ // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
26985 /* 69695 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_D),
26986 /* 69700 */ GIR_RootConstrainSelectedInstOperands,
26987 /* 69701 */ // GIR_Coverage, 739,
26988 /* 69701 */ GIR_Done,
26989 /* 69702 */ // Label 1803: @69702
26990 /* 69702 */ GIM_Reject,
26991 /* 69703 */ // Label 1801: @69703
26992 /* 69703 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(69729), // Rule ID 738 //
26993 /* 69708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26994 /* 69711 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26995 /* 69714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26996 /* 69718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26997 /* 69722 */ // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
26998 /* 69722 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_W),
26999 /* 69727 */ GIR_RootConstrainSelectedInstOperands,
27000 /* 69728 */ // GIR_Coverage, 738,
27001 /* 69728 */ GIR_Done,
27002 /* 69729 */ // Label 1804: @69729
27003 /* 69729 */ GIM_Reject,
27004 /* 69730 */ // Label 1802: @69730
27005 /* 69730 */ GIM_Reject,
27006 /* 69731 */ // Label 78: @69731
27007 /* 69731 */ GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(69746), // Rule ID 90 //
27008 /* 69736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
27009 /* 69739 */ // (trap) => (TRAP)
27010 /* 69739 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP),
27011 /* 69744 */ GIR_RootConstrainSelectedInstOperands,
27012 /* 69745 */ // GIR_Coverage, 90,
27013 /* 69745 */ GIR_Done,
27014 /* 69746 */ // Label 1805: @69746
27015 /* 69746 */ GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(69761), // Rule ID 1115 //
27016 /* 69751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
27017 /* 69754 */ // (trap) => (TRAP_MM)
27018 /* 69754 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP_MM),
27019 /* 69759 */ GIR_RootConstrainSelectedInstOperands,
27020 /* 69760 */ // GIR_Coverage, 1115,
27021 /* 69760 */ GIR_Done,
27022 /* 69761 */ // Label 1806: @69761
27023 /* 69761 */ GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(69776), // Rule ID 1910 //
27024 /* 69766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
27025 /* 69769 */ // (trap) => (Break16)
27026 /* 69769 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Break16),
27027 /* 69774 */ GIR_RootConstrainSelectedInstOperands,
27028 /* 69775 */ // GIR_Coverage, 1910,
27029 /* 69775 */ GIR_Done,
27030 /* 69776 */ // Label 1807: @69776
27031 /* 69776 */ GIM_Reject,
27032 /* 69777 */ // Label 79: @69777
27033 /* 69777 */ GIM_Reject,
27034 /* 69778 */ }; // Size: 69778 bytes
27035 return MatchTable0;
27036}
27037#undef GIMT_Encode2
27038#undef GIMT_Encode4
27039#undef GIMT_Encode8
27040
27041#endif // ifdef GET_GLOBALISEL_IMPL
27042
27043#ifdef GET_GLOBALISEL_PREDICATES_DECL
27044PredicateBitset AvailableModuleFeatures;
27045mutable PredicateBitset AvailableFunctionFeatures;
27046PredicateBitset getAvailableFeatures() const {
27047 return AvailableModuleFeatures | AvailableFunctionFeatures;
27048}
27049PredicateBitset
27050computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
27051PredicateBitset
27052computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
27053 const MachineFunction *MF) const;
27054void setupGeneratedPerFunctionState(MachineFunction &MF) override;
27055#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
27056#ifdef GET_GLOBALISEL_PREDICATES_INIT
27057AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
27058AvailableFunctionFeatures()
27059#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
27060