1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace Mips {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 FPRBRegBankID = 0,
16 GPRBRegBankID = 1,
17 NumRegisterBanks,
18};
19} // end namespace Mips
20} // end namespace llvm
21#endif // GET_REGBANK_DECLARATIONS
22
23#ifdef GET_TARGET_REGBANK_CLASS
24#undef GET_TARGET_REGBANK_CLASS
25private:
26 static const RegisterBank *RegBanks[];
27 static const unsigned Sizes[];
28
29public:
30 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
31protected:
32 MipsGenRegisterBankInfo(unsigned HwMode = 0);
33
34#endif // GET_TARGET_REGBANK_CLASS
35
36#ifdef GET_TARGET_REGBANK_IMPL
37#undef GET_TARGET_REGBANK_IMPL
38namespace llvm {
39namespace Mips {
40const uint32_t FPRBRegBankCoverageData[] = {
41 // 0-31
42 (1u << (Mips::FGR32RegClassID - 0)) |
43 (1u << (Mips::FGRCCRegClassID - 0)) |
44 0,
45 // 32-63
46 (1u << (Mips::FGR64RegClassID - 32)) |
47 (1u << (Mips::AFGR64RegClassID - 32)) |
48 0,
49 // 64-95
50 (1u << (Mips::MSA128DRegClassID - 64)) |
51 (1u << (Mips::MSA128BRegClassID - 64)) |
52 (1u << (Mips::MSA128HRegClassID - 64)) |
53 (1u << (Mips::MSA128WRegClassID - 64)) |
54 (1u << (Mips::MSA128WEvensRegClassID - 64)) |
55 0,
56};
57const uint32_t GPRBRegBankCoverageData[] = {
58 // 0-31
59 (1u << (Mips::GPR32RegClassID - 0)) |
60 (1u << (Mips::GPR32NONZERORegClassID - 0)) |
61 (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
62 (1u << (Mips::CPU16RegsRegClassID - 0)) |
63 (1u << (Mips::GPRMM16RegClassID - 0)) |
64 (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
65 (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 0)) |
66 (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 0)) |
67 (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 0)) |
68 (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
69 (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
70 (1u << (Mips::CPUSPRegRegClassID - 0)) |
71 (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
72 (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
73 (1u << (Mips::CPURARegRegClassID - 0)) |
74 (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
75 (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
76 (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
77 0,
78 // 32-63
79 (1u << (Mips::SP32RegClassID - 32)) |
80 (1u << (Mips::GP32RegClassID - 32)) |
81 (1u << (Mips::GPR32ZERORegClassID - 32)) |
82 0,
83 // 64-95
84 0,
85};
86
87constexpr RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 70);
88constexpr RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 70);
89} // end namespace Mips
90
91const RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
92 &Mips::FPRBRegBank,
93 &Mips::GPRBRegBank,
94};
95
96const unsigned MipsGenRegisterBankInfo::Sizes[] = {
97 // Mode = 0 (Default)
98 128,
99 32,
100};
101
102MipsGenRegisterBankInfo::MipsGenRegisterBankInfo(unsigned HwMode)
103 : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks, Sizes, HwMode) {
104 // Assert that RegBank indices match their ID's
105#ifndef NDEBUG
106 for (auto RB : enumerate(RegBanks))
107 assert(RB.index() == RB.value()->getID() && "Index != ID");
108#endif // NDEBUG
109}
110const RegisterBank &
111MipsGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
112 constexpr uint32_t InvalidRegBankID = uint32_t(Mips::InvalidRegBankID) & 3;
113 static const uint32_t RegClass2RegBank[5] = {
114 (uint32_t(InvalidRegBankID) << 0) |
115 (uint32_t(InvalidRegBankID) << 2) |
116 (uint32_t(InvalidRegBankID) << 4) |
117 (uint32_t(InvalidRegBankID) << 6) |
118 (uint32_t(InvalidRegBankID) << 8) |
119 (uint32_t(InvalidRegBankID) << 10) |
120 (uint32_t(Mips::FPRBRegBankID) << 12) | // FGR32RegClassID
121 (uint32_t(Mips::FPRBRegBankID) << 14) | // FGRCCRegClassID
122 (uint32_t(Mips::GPRBRegBankID) << 16) | // GPR32RegClassID
123 (uint32_t(InvalidRegBankID) << 18) |
124 (uint32_t(InvalidRegBankID) << 20) |
125 (uint32_t(Mips::GPRBRegBankID) << 22) | // GPR32NONZERORegClassID
126 (uint32_t(Mips::GPRBRegBankID) << 24) | // CPU16RegsPlusSPRegClassID
127 (uint32_t(Mips::GPRBRegBankID) << 26) | // CPU16RegsRegClassID
128 (uint32_t(InvalidRegBankID) << 28) |
129 (uint32_t(Mips::GPRBRegBankID) << 30), // GPRMM16RegClassID
130 (uint32_t(Mips::GPRBRegBankID) << 0) | // GPRMM16MovePRegClassID
131 (uint32_t(Mips::GPRBRegBankID) << 2) | // GPRMM16ZeroRegClassID
132 (uint32_t(Mips::GPRBRegBankID) << 4) | // CPU16Regs_and_GPRMM16ZeroRegClassID
133 (uint32_t(Mips::GPRBRegBankID) << 6) | // GPR32NONZERO_and_GPRMM16MovePRegClassID
134 (uint32_t(Mips::GPRBRegBankID) << 8) | // GPRMM16MovePPairSecondRegClassID
135 (uint32_t(Mips::GPRBRegBankID) << 10) | // CPU16Regs_and_GPRMM16MovePRegClassID
136 (uint32_t(Mips::GPRBRegBankID) << 12) | // GPRMM16MoveP_and_GPRMM16ZeroRegClassID
137 (uint32_t(InvalidRegBankID) << 14) |
138 (uint32_t(InvalidRegBankID) << 16) |
139 (uint32_t(Mips::GPRBRegBankID) << 18) | // CPU16Regs_and_GPRMM16MovePPairSecondRegClassID
140 (uint32_t(Mips::GPRBRegBankID) << 20) | // GPRMM16MovePPairFirstRegClassID
141 (uint32_t(Mips::GPRBRegBankID) << 22) | // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID
142 (uint32_t(Mips::GPRBRegBankID) << 24) | // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID
143 (uint32_t(Mips::GPRBRegBankID) << 26) | // CPURARegRegClassID
144 (uint32_t(Mips::GPRBRegBankID) << 28) | // CPUSPRegRegClassID
145 (uint32_t(InvalidRegBankID) << 30),
146 (uint32_t(Mips::GPRBRegBankID) << 0) | // GP32RegClassID
147 (uint32_t(Mips::GPRBRegBankID) << 2) | // GPR32ZERORegClassID
148 (uint32_t(InvalidRegBankID) << 4) |
149 (uint32_t(InvalidRegBankID) << 6) |
150 (uint32_t(Mips::GPRBRegBankID) << 8) | // SP32RegClassID
151 (uint32_t(Mips::FPRBRegBankID) << 10) | // FGR64RegClassID
152 (uint32_t(InvalidRegBankID) << 12) |
153 (uint32_t(InvalidRegBankID) << 14) |
154 (uint32_t(Mips::FPRBRegBankID) << 16) | // AFGR64RegClassID
155 (uint32_t(InvalidRegBankID) << 18) |
156 (uint32_t(InvalidRegBankID) << 20) |
157 (uint32_t(InvalidRegBankID) << 22) |
158 (uint32_t(InvalidRegBankID) << 24) |
159 (uint32_t(InvalidRegBankID) << 26) |
160 (uint32_t(InvalidRegBankID) << 28) |
161 (uint32_t(InvalidRegBankID) << 30),
162 (uint32_t(InvalidRegBankID) << 0) |
163 (uint32_t(InvalidRegBankID) << 2) |
164 (uint32_t(InvalidRegBankID) << 4) |
165 (uint32_t(InvalidRegBankID) << 6) |
166 (uint32_t(InvalidRegBankID) << 8) |
167 (uint32_t(InvalidRegBankID) << 10) |
168 (uint32_t(InvalidRegBankID) << 12) |
169 (uint32_t(InvalidRegBankID) << 14) |
170 (uint32_t(InvalidRegBankID) << 16) |
171 (uint32_t(InvalidRegBankID) << 18) |
172 (uint32_t(InvalidRegBankID) << 20) |
173 (uint32_t(InvalidRegBankID) << 22) |
174 (uint32_t(InvalidRegBankID) << 24) |
175 (uint32_t(InvalidRegBankID) << 26) |
176 (uint32_t(InvalidRegBankID) << 28) |
177 (uint32_t(InvalidRegBankID) << 30),
178 (uint32_t(Mips::FPRBRegBankID) << 0) | // MSA128BRegClassID
179 (uint32_t(Mips::FPRBRegBankID) << 2) | // MSA128DRegClassID
180 (uint32_t(Mips::FPRBRegBankID) << 4) | // MSA128HRegClassID
181 (uint32_t(Mips::FPRBRegBankID) << 6) | // MSA128WRegClassID
182 (uint32_t(Mips::FPRBRegBankID) << 8) // MSA128WEvensRegClassID
183 };
184 const unsigned RegClassID = RC.getID();
185 if (LLVM_LIKELY(RegClassID < 69)) {
186 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
187 if (RegBankID != InvalidRegBankID)
188 return getRegBank(RegBankID);
189 }
190 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
191}
192} // end namespace llvm
193#endif // GET_TARGET_REGBANK_IMPL
194