1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the PPC target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 41;
11using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15 mutable MatcherState State;
16 typedef ComplexRendererFns(PPCInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17 typedef void(PPCInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
19 static PPCInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20 static PPCInstructionSelector::CustomRendererFn CustomRenderers[];
21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24 const uint8_t *getMatchTable() const override;
25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
26 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
27 bool testSimplePredicate(unsigned PredicateID) const override;
28 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
29#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
30
31#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32, State(0),
33ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
34#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
35
36#ifdef GET_GLOBALISEL_IMPL
37// LLT Objects.
38enum {
39 GILLT_s1,
40 GILLT_s32,
41 GILLT_s64,
42 GILLT_s128,
43 GILLT_v2s64,
44 GILLT_v4s32,
45 GILLT_v8s16,
46 GILLT_v16s8,
47 GILLT_v256s1,
48 GILLT_v512s1,
49 GILLT_v1024s1,
50 GILLT_v2048s1,
51};
52const static size_t NumTypeObjects = 12;
53const static LLT TypeObjects[] = {
54 LLT::scalar(1),
55 LLT::scalar(32),
56 LLT::scalar(64),
57 LLT::scalar(128),
58 LLT::vector(ElementCount::getFixed(2), 64),
59 LLT::vector(ElementCount::getFixed(4), 32),
60 LLT::vector(ElementCount::getFixed(8), 16),
61 LLT::vector(ElementCount::getFixed(16), 8),
62 LLT::vector(ElementCount::getFixed(256), 1),
63 LLT::vector(ElementCount::getFixed(512), 1),
64 LLT::vector(ElementCount::getFixed(1024), 1),
65 LLT::vector(ElementCount::getFixed(2048), 1),
66};
67
68// Bits for subtarget features that participate in instruction matching.
69enum SubtargetFeatureBits : uint8_t {
70 Feature_In32BitModeBit = 1,
71 Feature_In64BitModeBit = 9,
72 Feature_HasOnlyMSYNCBit = 23,
73 Feature_HasSYNCBit = 22,
74 Feature_HasSPEBit = 8,
75 Feature_HasICBTBit = 21,
76 Feature_HasBPERMDBit = 10,
77 Feature_HasExtDivBit = 3,
78 Feature_IsISA2_06Bit = 11,
79 Feature_IsISA2_07Bit = 40,
80 Feature_IsISA3_0Bit = 2,
81 Feature_HasFPUBit = 0,
82 Feature_PCRelativeMemopsBit = 37,
83 Feature_IsNotISA3_1Bit = 39,
84 Feature_IsAIXBit = 24,
85 Feature_NotAIXBit = 25,
86 Feature_IsISAFutureBit = 18,
87 Feature_IsNotISAFutureBit = 19,
88 Feature_HasAltivecBit = 4,
89 Feature_HasP8AltivecBit = 5,
90 Feature_HasP8CryptoBit = 6,
91 Feature_HasP9AltivecBit = 7,
92 Feature_HasVSXBit = 12,
93 Feature_IsLittleEndianBit = 26,
94 Feature_IsBigEndianBit = 27,
95 Feature_IsPPC64Bit = 31,
96 Feature_HasOnlySwappingMemOpsBit = 29,
97 Feature_NoP8VectorBit = 30,
98 Feature_HasP8VectorBit = 13,
99 Feature_HasDirectMoveBit = 14,
100 Feature_NoP9VectorBit = 28,
101 Feature_HasP9VectorBit = 15,
102 Feature_NoP9AltivecBit = 32,
103 Feature_NoP10VectorBit = 33,
104 Feature_HasP10VectorBit = 36,
105 Feature_HasHTMBit = 34,
106 Feature_MMABit = 20,
107 Feature_IsPPC32Bit = 38,
108 Feature_PrefixInstrsBit = 16,
109 Feature_IsISA3_1Bit = 17,
110 Feature_PairedVectorMemopsBit = 35,
111};
112
113PredicateBitset PPCInstructionSelector::
114computeAvailableModuleFeatures(const PPCSubtarget *Subtarget) const {
115 PredicateBitset Features{};
116 if (!Subtarget->isPPC64())
117 Features.set(Feature_In32BitModeBit);
118 if (Subtarget->isPPC64())
119 Features.set(Feature_In64BitModeBit);
120 if (Subtarget->hasOnlyMSYNC())
121 Features.set(Feature_HasOnlyMSYNCBit);
122 if (!Subtarget->hasOnlyMSYNC())
123 Features.set(Feature_HasSYNCBit);
124 if (Subtarget->hasSPE())
125 Features.set(Feature_HasSPEBit);
126 if (Subtarget->hasICBT())
127 Features.set(Feature_HasICBTBit);
128 if (Subtarget->hasBPERMD())
129 Features.set(Feature_HasBPERMDBit);
130 if (Subtarget->hasExtDiv())
131 Features.set(Feature_HasExtDivBit);
132 if (Subtarget->isISA2_06())
133 Features.set(Feature_IsISA2_06Bit);
134 if (Subtarget->isISA2_07())
135 Features.set(Feature_IsISA2_07Bit);
136 if (Subtarget->isISA3_0())
137 Features.set(Feature_IsISA3_0Bit);
138 if (Subtarget->hasFPU())
139 Features.set(Feature_HasFPUBit);
140 if (Subtarget->hasPCRelativeMemops())
141 Features.set(Feature_PCRelativeMemopsBit);
142 if (!Subtarget->isISA3_1())
143 Features.set(Feature_IsNotISA3_1Bit);
144 if (Subtarget->isAIXABI())
145 Features.set(Feature_IsAIXBit);
146 if (!Subtarget->isAIXABI())
147 Features.set(Feature_NotAIXBit);
148 if (Subtarget->isISAFuture())
149 Features.set(Feature_IsISAFutureBit);
150 if (!Subtarget->isISAFuture())
151 Features.set(Feature_IsNotISAFutureBit);
152 if (Subtarget->hasAltivec())
153 Features.set(Feature_HasAltivecBit);
154 if (Subtarget->hasP8Altivec())
155 Features.set(Feature_HasP8AltivecBit);
156 if (Subtarget->hasP8Crypto())
157 Features.set(Feature_HasP8CryptoBit);
158 if (Subtarget->hasP9Altivec())
159 Features.set(Feature_HasP9AltivecBit);
160 if (Subtarget->hasVSX())
161 Features.set(Feature_HasVSXBit);
162 if (Subtarget->isLittleEndian())
163 Features.set(Feature_IsLittleEndianBit);
164 if (!Subtarget->isLittleEndian())
165 Features.set(Feature_IsBigEndianBit);
166 if (Subtarget->isPPC64())
167 Features.set(Feature_IsPPC64Bit);
168 if (!Subtarget->hasP9Vector())
169 Features.set(Feature_HasOnlySwappingMemOpsBit);
170 if (!Subtarget->hasP8Vector())
171 Features.set(Feature_NoP8VectorBit);
172 if (Subtarget->hasP8Vector())
173 Features.set(Feature_HasP8VectorBit);
174 if (Subtarget->hasDirectMove())
175 Features.set(Feature_HasDirectMoveBit);
176 if (!Subtarget->hasP9Vector())
177 Features.set(Feature_NoP9VectorBit);
178 if (Subtarget->hasP9Vector())
179 Features.set(Feature_HasP9VectorBit);
180 if (!Subtarget->hasP9Altivec())
181 Features.set(Feature_NoP9AltivecBit);
182 if (!Subtarget->hasP10Vector())
183 Features.set(Feature_NoP10VectorBit);
184 if (Subtarget->hasP10Vector())
185 Features.set(Feature_HasP10VectorBit);
186 if (Subtarget->hasHTM())
187 Features.set(Feature_HasHTMBit);
188 if (Subtarget->hasMMA())
189 Features.set(Feature_MMABit);
190 if (!Subtarget->isPPC64())
191 Features.set(Feature_IsPPC32Bit);
192 if (Subtarget->hasPrefixInstrs())
193 Features.set(Feature_PrefixInstrsBit);
194 if (Subtarget->isISA3_1())
195 Features.set(Feature_IsISA3_1Bit);
196 if (Subtarget->pairedVectorMemops())
197 Features.set(Feature_PairedVectorMemopsBit);
198 return Features;
199}
200
201void PPCInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
202 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const PPCSubtarget *)&MF.getSubtarget(), &MF);
203}
204PredicateBitset PPCInstructionSelector::
205computeAvailableFunctionFeatures(const PPCSubtarget *Subtarget, const MachineFunction *MF) const {
206 PredicateBitset Features{};
207 return Features;
208}
209
210// Feature bitsets.
211enum {
212 GIFBS_Invalid,
213 GIFBS_HasAltivec,
214 GIFBS_HasBPERMD,
215 GIFBS_HasExtDiv,
216 GIFBS_HasFPU,
217 GIFBS_HasHTM,
218 GIFBS_HasOnlyMSYNC,
219 GIFBS_HasP8Altivec,
220 GIFBS_HasP8Crypto,
221 GIFBS_HasP9Altivec,
222 GIFBS_HasSPE,
223 GIFBS_HasSYNC,
224 GIFBS_HasVSX,
225 GIFBS_In32BitMode,
226 GIFBS_In64BitMode,
227 GIFBS_IsAIX,
228 GIFBS_IsISA3_0,
229 GIFBS_IsISA3_1,
230 GIFBS_IsISAFuture,
231 GIFBS_IsNotISA3_1,
232 GIFBS_NotAIX,
233 GIFBS_PairedVectorMemops,
234 GIFBS_HasDirectMove_HasVSX,
235 GIFBS_HasFPU_IsISA3_1,
236 GIFBS_HasP10Vector_PrefixInstrs,
237 GIFBS_HasP8Altivec_HasVSX,
238 GIFBS_HasP8Vector_HasVSX,
239 GIFBS_HasP9Vector_HasVSX,
240 GIFBS_HasVSX_IsISA3_1,
241 GIFBS_In64BitMode_IsISA3_0,
242 GIFBS_IsISAFuture_MMA,
243 GIFBS_IsNotISAFuture_MMA,
244 GIFBS_HasP8Altivec_HasVSX_IsBigEndian,
245 GIFBS_HasP8Altivec_HasVSX_IsLittleEndian,
246 GIFBS_IsISAFuture_MMA_PrefixInstrs,
247 GIFBS_IsNotISAFuture_MMA_PrefixInstrs,
248 GIFBS_HasDirectMove_HasVSX_IsISA3_0_IsLittleEndian,
249 GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector,
250 GIFBS_HasVSX_IsBigEndian_IsISA3_1_IsPPC32,
251 GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsISA3_0_IsPPC64,
252 GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector,
253};
254constexpr static PredicateBitset FeatureBitsets[] {
255 {}, // GIFBS_Invalid
256 {Feature_HasAltivecBit, },
257 {Feature_HasBPERMDBit, },
258 {Feature_HasExtDivBit, },
259 {Feature_HasFPUBit, },
260 {Feature_HasHTMBit, },
261 {Feature_HasOnlyMSYNCBit, },
262 {Feature_HasP8AltivecBit, },
263 {Feature_HasP8CryptoBit, },
264 {Feature_HasP9AltivecBit, },
265 {Feature_HasSPEBit, },
266 {Feature_HasSYNCBit, },
267 {Feature_HasVSXBit, },
268 {Feature_In32BitModeBit, },
269 {Feature_In64BitModeBit, },
270 {Feature_IsAIXBit, },
271 {Feature_IsISA3_0Bit, },
272 {Feature_IsISA3_1Bit, },
273 {Feature_IsISAFutureBit, },
274 {Feature_IsNotISA3_1Bit, },
275 {Feature_NotAIXBit, },
276 {Feature_PairedVectorMemopsBit, },
277 {Feature_HasDirectMoveBit, Feature_HasVSXBit, },
278 {Feature_HasFPUBit, Feature_IsISA3_1Bit, },
279 {Feature_HasP10VectorBit, Feature_PrefixInstrsBit, },
280 {Feature_HasP8AltivecBit, Feature_HasVSXBit, },
281 {Feature_HasP8VectorBit, Feature_HasVSXBit, },
282 {Feature_HasP9VectorBit, Feature_HasVSXBit, },
283 {Feature_HasVSXBit, Feature_IsISA3_1Bit, },
284 {Feature_In64BitModeBit, Feature_IsISA3_0Bit, },
285 {Feature_IsISAFutureBit, Feature_MMABit, },
286 {Feature_IsNotISAFutureBit, Feature_MMABit, },
287 {Feature_HasP8AltivecBit, Feature_HasVSXBit, Feature_IsBigEndianBit, },
288 {Feature_HasP8AltivecBit, Feature_HasVSXBit, Feature_IsLittleEndianBit, },
289 {Feature_IsISAFutureBit, Feature_MMABit, Feature_PrefixInstrsBit, },
290 {Feature_IsNotISAFutureBit, Feature_MMABit, Feature_PrefixInstrsBit, },
291 {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsISA3_0Bit, Feature_IsLittleEndianBit, },
292 {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsLittleEndianBit, Feature_NoP9VectorBit, },
293 {Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsISA3_1Bit, Feature_IsPPC32Bit, },
294 {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsISA3_0Bit, Feature_IsPPC64Bit, },
295 {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsPPC64Bit, Feature_NoP9VectorBit, },
296};
297
298// ComplexPattern predicates.
299enum {
300 GICP_Invalid,
301};
302// See constructor for table contents
303
304PPCInstructionSelector::ComplexMatcherMemFn
305PPCInstructionSelector::ComplexPredicateFns[] = {
306 nullptr, // GICP_Invalid
307};
308
309// PatFrag predicates.
310bool PPCInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
311 const MachineFunction &MF = *MI.getParent()->getParent();
312 const MachineRegisterInfo &MRI = MF.getRegInfo();
313 const auto &Operands = State.RecordedOperands;
314 (void)Operands;
315 (void)MRI;
316 llvm_unreachable("Unknown predicate");
317 return false;
318}
319// PatFrag predicates.
320bool PPCInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
321 const auto &Operands = State.RecordedOperands;
322 Register Reg = MO.getReg();
323 (void)Operands;
324 (void)Reg;
325 llvm_unreachable("Unknown predicate");
326 return false;
327}
328// PatFrag predicates.
329enum {
330 GICXXPred_I64_Predicate_Msk2Imm = GICXXPred_Invalid + 1,
331 GICXXPred_I64_Predicate_Msk4Imm,
332 GICXXPred_I64_Predicate_Msk8Imm,
333 GICXXPred_I64_Predicate_i32immNonAllOneNonZero,
334 GICXXPred_I64_Predicate_imm32SExt16,
335 GICXXPred_I64_Predicate_imm64SExt16,
336 GICXXPred_I64_Predicate_imm64ZExt32,
337 GICXXPred_I64_Predicate_immNonAllOneAnyExt8,
338 GICXXPred_I64_Predicate_immSExt5NonZero,
339};
340bool PPCInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
341 switch (PredicateID) {
342 case GICXXPred_I64_Predicate_Msk2Imm: {
343 return isUInt<2>(Imm);
344 }
345 case GICXXPred_I64_Predicate_Msk4Imm: {
346 return isUInt<4>(Imm);
347 }
348 case GICXXPred_I64_Predicate_Msk8Imm: {
349 return isUInt<8>(Imm);
350 }
351 case GICXXPred_I64_Predicate_i32immNonAllOneNonZero: {
352 return Imm && (Imm != -1);
353 }
354 case GICXXPred_I64_Predicate_imm32SExt16: {
355
356 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
357 // sign extended field. Used by instructions like 'addi'.
358 return (int32_t)Imm == (short)Imm;
359
360 llvm_unreachable("imm32SExt16 should have returned");
361 }
362 case GICXXPred_I64_Predicate_imm64SExt16: {
363
364 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
365 // sign extended field. Used by instructions like 'addi'.
366 return (int64_t)Imm == (short)Imm;
367
368 llvm_unreachable("imm64SExt16 should have returned");
369 }
370 case GICXXPred_I64_Predicate_imm64ZExt32: {
371
372 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
373 // zero extended field.
374 return isUInt<32>(Imm);
375
376 llvm_unreachable("imm64ZExt32 should have returned");
377 }
378 case GICXXPred_I64_Predicate_immNonAllOneAnyExt8: {
379
380 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF));
381
382 }
383 case GICXXPred_I64_Predicate_immSExt5NonZero: {
384 return Imm && isInt<5>(Imm);
385 }
386 }
387 llvm_unreachable("Unknown predicate");
388 return false;
389}
390// PatFrag predicates.
391bool PPCInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
392 llvm_unreachable("Unknown predicate");
393 return false;
394}
395// PatFrag predicates.
396bool PPCInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
397 llvm_unreachable("Unknown predicate");
398 return false;
399}
400bool PPCInstructionSelector::testSimplePredicate(unsigned) const {
401 llvm_unreachable("PPCInstructionSelector does not support simple predicates!");
402 return false;
403}
404// Custom renderers.
405enum {
406 GICR_Invalid,
407};
408PPCInstructionSelector::CustomRendererFn
409PPCInstructionSelector::CustomRenderers[] = {
410 nullptr, // GICR_Invalid
411};
412
413bool PPCInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
414 const PredicateBitset AvailableFeatures = getAvailableFeatures();
415 MachineIRBuilder B(I);
416 State.MIs.clear();
417 State.MIs.push_back(&I);
418
419 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
420 return true;
421 }
422
423 return false;
424}
425
426bool PPCInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
427 llvm_unreachable("PPCInstructionSelector does not support custom C++ actions!");
428}
429#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
430#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8)
431#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24)
432#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56)
433#else
434#define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val)
435#define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val)
436#define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val)
437#endif
438const uint8_t *PPCInstructionSelector::getMatchTable() const {
439 constexpr static uint8_t MatchTable0[] = {
440 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(53), GIMT_Encode2(289), /*)*//*default:*//*Label 83*/ GIMT_Encode4(211473),
441 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(954),
442 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(1363),
443 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(1804),
444 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(2086),
445 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(2242),
446 /* 30 */ /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(2398),
447 /* 34 */ /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(2560), GIMT_Encode4(0), GIMT_Encode4(0),
448 /* 46 */ /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(2722),
449 /* 50 */ /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5283),
450 /* 54 */ /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(48425), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
451 /* 106 */ /*TargetOpcode::G_BUILD_VECTOR*//*Label 10*/ GIMT_Encode4(57532), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
452 /* 126 */ /*TargetOpcode::G_BITCAST*//*Label 11*/ GIMT_Encode4(58499), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
453 /* 142 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 12*/ GIMT_Encode4(60776),
454 /* 146 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 13*/ GIMT_Encode4(61051),
455 /* 150 */ /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 14*/ GIMT_Encode4(61301),
456 /* 154 */ /*TargetOpcode::G_INTRINSIC_LLRINT*//*Label 15*/ GIMT_Encode4(61432), GIMT_Encode4(0),
457 /* 162 */ /*TargetOpcode::G_READCYCLECOUNTER*//*Label 16*/ GIMT_Encode4(61563), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
458 /* 294 */ /*TargetOpcode::G_FENCE*//*Label 17*/ GIMT_Encode4(61583), GIMT_Encode4(0),
459 /* 302 */ /*TargetOpcode::G_BRCOND*//*Label 18*/ GIMT_Encode4(61708), GIMT_Encode4(0), GIMT_Encode4(0),
460 /* 314 */ /*TargetOpcode::G_INTRINSIC*//*Label 19*/ GIMT_Encode4(61771),
461 /* 318 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 20*/ GIMT_Encode4(91199), GIMT_Encode4(0), GIMT_Encode4(0),
462 /* 330 */ /*TargetOpcode::G_ANYEXT*//*Label 21*/ GIMT_Encode4(94091),
463 /* 334 */ /*TargetOpcode::G_TRUNC*//*Label 22*/ GIMT_Encode4(114847),
464 /* 338 */ /*TargetOpcode::G_CONSTANT*//*Label 23*/ GIMT_Encode4(115033), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
465 /* 354 */ /*TargetOpcode::G_SEXT*//*Label 24*/ GIMT_Encode4(115185),
466 /* 358 */ /*TargetOpcode::G_SEXT_INREG*//*Label 25*/ GIMT_Encode4(130217),
467 /* 362 */ /*TargetOpcode::G_ZEXT*//*Label 26*/ GIMT_Encode4(130570),
468 /* 366 */ /*TargetOpcode::G_SHL*//*Label 27*/ GIMT_Encode4(152040),
469 /* 370 */ /*TargetOpcode::G_LSHR*//*Label 28*/ GIMT_Encode4(152396),
470 /* 374 */ /*TargetOpcode::G_ASHR*//*Label 29*/ GIMT_Encode4(152818), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
471 /* 390 */ /*TargetOpcode::G_ROTL*//*Label 30*/ GIMT_Encode4(153188),
472 /* 394 */ /*TargetOpcode::G_ICMP*//*Label 31*/ GIMT_Encode4(153496),
473 /* 398 */ /*TargetOpcode::G_FCMP*//*Label 32*/ GIMT_Encode4(157498), GIMT_Encode4(0), GIMT_Encode4(0),
474 /* 410 */ /*TargetOpcode::G_SELECT*//*Label 33*/ GIMT_Encode4(160949), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
475 /* 454 */ /*TargetOpcode::G_UMULH*//*Label 34*/ GIMT_Encode4(162073),
476 /* 458 */ /*TargetOpcode::G_SMULH*//*Label 35*/ GIMT_Encode4(162203),
477 /* 462 */ /*TargetOpcode::G_UADDSAT*//*Label 36*/ GIMT_Encode4(162333),
478 /* 466 */ /*TargetOpcode::G_SADDSAT*//*Label 37*/ GIMT_Encode4(162435),
479 /* 470 */ /*TargetOpcode::G_USUBSAT*//*Label 38*/ GIMT_Encode4(162537),
480 /* 474 */ /*TargetOpcode::G_SSUBSAT*//*Label 39*/ GIMT_Encode4(162639), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
481 /* 518 */ /*TargetOpcode::G_FADD*//*Label 40*/ GIMT_Encode4(162741),
482 /* 522 */ /*TargetOpcode::G_FSUB*//*Label 41*/ GIMT_Encode4(163036),
483 /* 526 */ /*TargetOpcode::G_FMUL*//*Label 42*/ GIMT_Encode4(163331),
484 /* 530 */ /*TargetOpcode::G_FMA*//*Label 43*/ GIMT_Encode4(163681), GIMT_Encode4(0),
485 /* 538 */ /*TargetOpcode::G_FDIV*//*Label 44*/ GIMT_Encode4(164262), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
486 /* 586 */ /*TargetOpcode::G_FNEG*//*Label 45*/ GIMT_Encode4(164532),
487 /* 590 */ /*TargetOpcode::G_FPEXT*//*Label 46*/ GIMT_Encode4(167003),
488 /* 594 */ /*TargetOpcode::G_FPTRUNC*//*Label 47*/ GIMT_Encode4(167167),
489 /* 598 */ /*TargetOpcode::G_FPTOSI*//*Label 48*/ GIMT_Encode4(167324),
490 /* 602 */ /*TargetOpcode::G_FPTOUI*//*Label 49*/ GIMT_Encode4(167587),
491 /* 606 */ /*TargetOpcode::G_SITOFP*//*Label 50*/ GIMT_Encode4(167850),
492 /* 610 */ /*TargetOpcode::G_UITOFP*//*Label 51*/ GIMT_Encode4(168097), GIMT_Encode4(0), GIMT_Encode4(0),
493 /* 622 */ /*TargetOpcode::G_FABS*//*Label 52*/ GIMT_Encode4(168344),
494 /* 626 */ /*TargetOpcode::G_FCOPYSIGN*//*Label 53*/ GIMT_Encode4(168636), GIMT_Encode4(0), GIMT_Encode4(0),
495 /* 638 */ /*TargetOpcode::G_FMINNUM*//*Label 54*/ GIMT_Encode4(168952),
496 /* 642 */ /*TargetOpcode::G_FMAXNUM*//*Label 55*/ GIMT_Encode4(169032),
497 /* 646 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 56*/ GIMT_Encode4(169112),
498 /* 650 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 57*/ GIMT_Encode4(169694), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
499 /* 702 */ /*TargetOpcode::G_SMIN*//*Label 58*/ GIMT_Encode4(170276),
500 /* 706 */ /*TargetOpcode::G_SMAX*//*Label 59*/ GIMT_Encode4(170456),
501 /* 710 */ /*TargetOpcode::G_UMIN*//*Label 60*/ GIMT_Encode4(170636),
502 /* 714 */ /*TargetOpcode::G_UMAX*//*Label 61*/ GIMT_Encode4(170816), GIMT_Encode4(0),
503 /* 722 */ /*TargetOpcode::G_LROUND*//*Label 62*/ GIMT_Encode4(170996),
504 /* 726 */ /*TargetOpcode::G_LLROUND*//*Label 63*/ GIMT_Encode4(171298),
505 /* 730 */ /*TargetOpcode::G_BR*//*Label 64*/ GIMT_Encode4(171463), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
506 /* 750 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 65*/ GIMT_Encode4(171479), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
507 /* 774 */ /*TargetOpcode::G_CTTZ*//*Label 66*/ GIMT_Encode4(171597), GIMT_Encode4(0),
508 /* 782 */ /*TargetOpcode::G_CTLZ*//*Label 67*/ GIMT_Encode4(171775), GIMT_Encode4(0),
509 /* 790 */ /*TargetOpcode::G_CTPOP*//*Label 68*/ GIMT_Encode4(171947),
510 /* 794 */ /*TargetOpcode::G_BSWAP*//*Label 69*/ GIMT_Encode4(172119),
511 /* 798 */ /*TargetOpcode::G_BITREVERSE*//*Label 70*/ GIMT_Encode4(172383),
512 /* 802 */ /*TargetOpcode::G_FCEIL*//*Label 71*/ GIMT_Encode4(208389), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
513 /* 850 */ /*TargetOpcode::G_FSQRT*//*Label 72*/ GIMT_Encode4(208664),
514 /* 854 */ /*TargetOpcode::G_FFLOOR*//*Label 73*/ GIMT_Encode4(208881),
515 /* 858 */ /*TargetOpcode::G_FRINT*//*Label 74*/ GIMT_Encode4(209156),
516 /* 862 */ /*TargetOpcode::G_FNEARBYINT*//*Label 75*/ GIMT_Encode4(209368), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
517 /* 890 */ /*TargetOpcode::G_STRICT_FADD*//*Label 76*/ GIMT_Encode4(209605),
518 /* 894 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 77*/ GIMT_Encode4(209875),
519 /* 898 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 78*/ GIMT_Encode4(210145),
520 /* 902 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 79*/ GIMT_Encode4(210415), GIMT_Encode4(0),
521 /* 910 */ /*TargetOpcode::G_STRICT_FMA*//*Label 80*/ GIMT_Encode4(210685),
522 /* 914 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 81*/ GIMT_Encode4(211243), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
523 /* 950 */ /*TargetOpcode::G_TRAP*//*Label 82*/ GIMT_Encode4(211460),
524 /* 954 */ // Label 0: @954
525 /* 954 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 92*/ GIMT_Encode4(1362),
526 /* 965 */ /*GILLT_s1*//*Label 84*/ GIMT_Encode4(997),
527 /* 969 */ /*GILLT_s32*//*Label 85*/ GIMT_Encode4(1020),
528 /* 973 */ /*GILLT_s64*//*Label 86*/ GIMT_Encode4(1080),
529 /* 977 */ /*GILLT_s128*//*Label 87*/ GIMT_Encode4(1140),
530 /* 981 */ /*GILLT_v2s64*//*Label 88*/ GIMT_Encode4(1166),
531 /* 985 */ /*GILLT_v4s32*//*Label 89*/ GIMT_Encode4(1192),
532 /* 989 */ /*GILLT_v8s16*//*Label 90*/ GIMT_Encode4(1218),
533 /* 993 */ /*GILLT_v16s8*//*Label 91*/ GIMT_Encode4(1336),
534 /* 997 */ // Label 84: @997
535 /* 997 */ GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1019), // Rule ID 3669 //
536 /* 1002 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
537 /* 1005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
538 /* 1008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
539 /* 1012 */ // (add:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRXOR:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b)
540 /* 1012 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR),
541 /* 1017 */ GIR_RootConstrainSelectedInstOperands,
542 /* 1018 */ // GIR_Coverage, 3669,
543 /* 1018 */ GIR_Done,
544 /* 1019 */ // Label 93: @1019
545 /* 1019 */ GIM_Reject,
546 /* 1020 */ // Label 85: @1020
547 /* 1020 */ GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1079),
548 /* 1025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
549 /* 1028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
550 /* 1031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
551 /* 1035 */ GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1066), // Rule ID 107 //
552 /* 1040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
553 /* 1044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
554 /* 1048 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
555 /* 1052 */ // MIs[1] Operand 1
556 /* 1052 */ // No operand predicates
557 /* 1052 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
558 /* 1054 */ // (add:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$D) => (ADDI:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] }):$D)
559 /* 1054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDI),
560 /* 1057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
561 /* 1059 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
562 /* 1061 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D
563 /* 1064 */ GIR_RootConstrainSelectedInstOperands,
564 /* 1065 */ // GIR_Coverage, 107,
565 /* 1065 */ GIR_EraseRootFromParent_Done,
566 /* 1066 */ // Label 95: @1066
567 /* 1066 */ GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1078), // Rule ID 199 //
568 /* 1071 */ // (add:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (ADD4:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
569 /* 1071 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ADD4),
570 /* 1076 */ GIR_RootConstrainSelectedInstOperands,
571 /* 1077 */ // GIR_Coverage, 199,
572 /* 1077 */ GIR_Done,
573 /* 1078 */ // Label 96: @1078
574 /* 1078 */ GIM_Reject,
575 /* 1079 */ // Label 94: @1079
576 /* 1079 */ GIM_Reject,
577 /* 1080 */ // Label 86: @1080
578 /* 1080 */ GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1139),
579 /* 1085 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
580 /* 1088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
581 /* 1091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
582 /* 1095 */ GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1126), // Rule ID 663 //
583 /* 1100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
584 /* 1104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
585 /* 1108 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
586 /* 1112 */ // MIs[1] Operand 1
587 /* 1112 */ // No operand predicates
588 /* 1112 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
589 /* 1114 */ // (add:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$D) => (ADDI8:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] }):$D)
590 /* 1114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
591 /* 1117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
592 /* 1119 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
593 /* 1121 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D
594 /* 1124 */ GIR_RootConstrainSelectedInstOperands,
595 /* 1125 */ // GIR_Coverage, 663,
596 /* 1125 */ GIR_EraseRootFromParent_Done,
597 /* 1126 */ // Label 98: @1126
598 /* 1126 */ GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(1138), // Rule ID 659 //
599 /* 1131 */ // (add:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (ADD8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
600 /* 1131 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ADD8),
601 /* 1136 */ GIR_RootConstrainSelectedInstOperands,
602 /* 1137 */ // GIR_Coverage, 659,
603 /* 1137 */ GIR_Done,
604 /* 1138 */ // Label 99: @1138
605 /* 1138 */ GIM_Reject,
606 /* 1139 */ // Label 97: @1139
607 /* 1139 */ GIM_Reject,
608 /* 1140 */ // Label 87: @1140
609 /* 1140 */ GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1165), // Rule ID 470 //
610 /* 1145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
611 /* 1148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
612 /* 1151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
613 /* 1154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
614 /* 1158 */ // (add:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VADDUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
615 /* 1158 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUQM),
616 /* 1163 */ GIR_RootConstrainSelectedInstOperands,
617 /* 1164 */ // GIR_Coverage, 470,
618 /* 1164 */ GIR_Done,
619 /* 1165 */ // Label 100: @1165
620 /* 1165 */ GIM_Reject,
621 /* 1166 */ // Label 88: @1166
622 /* 1166 */ GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(1191), // Rule ID 469 //
623 /* 1171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
624 /* 1174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
625 /* 1177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
626 /* 1180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
627 /* 1184 */ // (add:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VADDUDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
628 /* 1184 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUDM),
629 /* 1189 */ GIR_RootConstrainSelectedInstOperands,
630 /* 1190 */ // GIR_Coverage, 469,
631 /* 1190 */ GIR_Done,
632 /* 1191 */ // Label 101: @1191
633 /* 1191 */ GIM_Reject,
634 /* 1192 */ // Label 89: @1192
635 /* 1192 */ GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(1217), // Rule ID 303 //
636 /* 1197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
637 /* 1200 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
638 /* 1203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
639 /* 1206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
640 /* 1210 */ // (add:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
641 /* 1210 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUWM),
642 /* 1215 */ GIR_RootConstrainSelectedInstOperands,
643 /* 1216 */ // GIR_Coverage, 303,
644 /* 1216 */ GIR_Done,
645 /* 1217 */ // Label 102: @1217
646 /* 1217 */ GIM_Reject,
647 /* 1218 */ // Label 90: @1218
648 /* 1218 */ GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(1335),
649 /* 1223 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
650 /* 1226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
651 /* 1229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
652 /* 1233 */ GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(1276), // Rule ID 1296 //
653 /* 1238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
654 /* 1241 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
655 /* 1245 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
656 /* 1249 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
657 /* 1253 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
658 /* 1257 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
659 /* 1259 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB), v8i16:{ *:[v8i16] }:$vC) => (VMLADDUHM:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB, ?:{ *:[v8i16] }:$vC)
660 /* 1259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMLADDUHM),
661 /* 1262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
662 /* 1264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
663 /* 1268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
664 /* 1272 */ GIR_RootToRootCopy, /*OpIdx*/2, // vC
665 /* 1274 */ GIR_RootConstrainSelectedInstOperands,
666 /* 1275 */ // GIR_Coverage, 1296,
667 /* 1275 */ GIR_EraseRootFromParent_Done,
668 /* 1276 */ // Label 104: @1276
669 /* 1276 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(1319), // Rule ID 4947 //
670 /* 1281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
671 /* 1284 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
672 /* 1288 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
673 /* 1292 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
674 /* 1296 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
675 /* 1300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
676 /* 1302 */ // (add:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vC, (mul:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB)) => (VMLADDUHM:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB, ?:{ *:[v8i16] }:$vC)
677 /* 1302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMLADDUHM),
678 /* 1305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
679 /* 1307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
680 /* 1311 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
681 /* 1315 */ GIR_RootToRootCopy, /*OpIdx*/1, // vC
682 /* 1317 */ GIR_RootConstrainSelectedInstOperands,
683 /* 1318 */ // GIR_Coverage, 4947,
684 /* 1318 */ GIR_EraseRootFromParent_Done,
685 /* 1319 */ // Label 105: @1319
686 /* 1319 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1334), // Rule ID 302 //
687 /* 1324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
688 /* 1327 */ // (add:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
689 /* 1327 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUHM),
690 /* 1332 */ GIR_RootConstrainSelectedInstOperands,
691 /* 1333 */ // GIR_Coverage, 302,
692 /* 1333 */ GIR_Done,
693 /* 1334 */ // Label 106: @1334
694 /* 1334 */ GIM_Reject,
695 /* 1335 */ // Label 103: @1335
696 /* 1335 */ GIM_Reject,
697 /* 1336 */ // Label 91: @1336
698 /* 1336 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1361), // Rule ID 301 //
699 /* 1341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
700 /* 1344 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
701 /* 1347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
702 /* 1350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
703 /* 1354 */ // (add:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDUBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
704 /* 1354 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUBM),
705 /* 1359 */ GIR_RootConstrainSelectedInstOperands,
706 /* 1360 */ // GIR_Coverage, 301,
707 /* 1360 */ GIR_Done,
708 /* 1361 */ // Label 107: @1361
709 /* 1361 */ GIM_Reject,
710 /* 1362 */ // Label 92: @1362
711 /* 1362 */ GIM_Reject,
712 /* 1363 */ // Label 1: @1363
713 /* 1363 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 116*/ GIMT_Encode4(1803),
714 /* 1374 */ /*GILLT_s1*//*Label 108*/ GIMT_Encode4(1406),
715 /* 1378 */ /*GILLT_s32*//*Label 109*/ GIMT_Encode4(1429),
716 /* 1382 */ /*GILLT_s64*//*Label 110*/ GIMT_Encode4(1514),
717 /* 1386 */ /*GILLT_s128*//*Label 111*/ GIMT_Encode4(1599),
718 /* 1390 */ /*GILLT_v2s64*//*Label 112*/ GIMT_Encode4(1625),
719 /* 1394 */ /*GILLT_v4s32*//*Label 113*/ GIMT_Encode4(1688),
720 /* 1398 */ /*GILLT_v8s16*//*Label 114*/ GIMT_Encode4(1751),
721 /* 1402 */ /*GILLT_v16s8*//*Label 115*/ GIMT_Encode4(1777),
722 /* 1406 */ // Label 108: @1406
723 /* 1406 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(1428), // Rule ID 3670 //
724 /* 1411 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
725 /* 1414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
726 /* 1417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
727 /* 1421 */ // (sub:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRXOR:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b)
728 /* 1421 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR),
729 /* 1426 */ GIR_RootConstrainSelectedInstOperands,
730 /* 1427 */ // GIR_Coverage, 3670,
731 /* 1427 */ GIR_Done,
732 /* 1428 */ // Label 117: @1428
733 /* 1428 */ GIM_Reject,
734 /* 1429 */ // Label 109: @1429
735 /* 1429 */ GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(1513),
736 /* 1434 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
737 /* 1437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
738 /* 1440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
739 /* 1444 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(1462), // Rule ID 211 //
740 /* 1449 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
741 /* 1453 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, i32:{ *:[i32] }:$RA) => (NEG:{ *:[i32] } i32:{ *:[i32] }:$RA)
742 /* 1453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NEG),
743 /* 1456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
744 /* 1458 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
745 /* 1460 */ GIR_RootConstrainSelectedInstOperands,
746 /* 1461 */ // GIR_Coverage, 211,
747 /* 1461 */ GIR_EraseRootFromParent_Done,
748 /* 1462 */ // Label 119: @1462
749 /* 1462 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(1496), // Rule ID 1217 //
750 /* 1467 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
751 /* 1471 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
752 /* 1475 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
753 /* 1479 */ // MIs[1] Operand 1
754 /* 1479 */ // No operand predicates
755 /* 1479 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
756 /* 1481 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, i32:{ *:[i32] }:$in) => (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$in, (imm:{ *:[i32] }):$imm)
757 /* 1481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
758 /* 1484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
759 /* 1486 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
760 /* 1488 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
761 /* 1491 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0,
762 /* 1494 */ GIR_RootConstrainSelectedInstOperands,
763 /* 1495 */ // GIR_Coverage, 1217,
764 /* 1495 */ GIR_EraseRootFromParent_Done,
765 /* 1496 */ // Label 120: @1496
766 /* 1496 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(1512), // Rule ID 209 //
767 /* 1501 */ // (sub:{ *:[i32] } i32:{ *:[i32] }:$RB, i32:{ *:[i32] }:$RA) => (SUBF:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
768 /* 1501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBF),
769 /* 1504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
770 /* 1506 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
771 /* 1508 */ GIR_RootToRootCopy, /*OpIdx*/1, // RB
772 /* 1510 */ GIR_RootConstrainSelectedInstOperands,
773 /* 1511 */ // GIR_Coverage, 209,
774 /* 1511 */ GIR_EraseRootFromParent_Done,
775 /* 1512 */ // Label 121: @1512
776 /* 1512 */ GIM_Reject,
777 /* 1513 */ // Label 118: @1513
778 /* 1513 */ GIM_Reject,
779 /* 1514 */ // Label 110: @1514
780 /* 1514 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(1598),
781 /* 1519 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
782 /* 1522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
783 /* 1525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
784 /* 1529 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(1547), // Rule ID 669 //
785 /* 1534 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
786 /* 1538 */ // (sub:{ *:[i64] } 0:{ *:[i64] }, i64:{ *:[i64] }:$RA) => (NEG8:{ *:[i64] } i64:{ *:[i64] }:$RA)
787 /* 1538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NEG8),
788 /* 1541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
789 /* 1543 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
790 /* 1545 */ GIR_RootConstrainSelectedInstOperands,
791 /* 1546 */ // GIR_Coverage, 669,
792 /* 1546 */ GIR_EraseRootFromParent_Done,
793 /* 1547 */ // Label 123: @1547
794 /* 1547 */ GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(1581), // Rule ID 1539 //
795 /* 1552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
796 /* 1556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
797 /* 1560 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
798 /* 1564 */ // MIs[1] Operand 1
799 /* 1564 */ // No operand predicates
800 /* 1564 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
801 /* 1566 */ // (sub:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, i64:{ *:[i64] }:$in) => (SUBFIC8:{ *:[i64] }:{ *:[i32] } ?:{ *:[i64] }:$in, (imm:{ *:[i64] }):$imm)
802 /* 1566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBFIC8),
803 /* 1569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
804 /* 1571 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
805 /* 1573 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
806 /* 1576 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0,
807 /* 1579 */ GIR_RootConstrainSelectedInstOperands,
808 /* 1580 */ // GIR_Coverage, 1539,
809 /* 1580 */ GIR_EraseRootFromParent_Done,
810 /* 1581 */ // Label 124: @1581
811 /* 1581 */ GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(1597), // Rule ID 668 //
812 /* 1586 */ // (sub:{ *:[i64] } i64:{ *:[i64] }:$RB, i64:{ *:[i64] }:$RA) => (SUBF8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
813 /* 1586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBF8),
814 /* 1589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
815 /* 1591 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
816 /* 1593 */ GIR_RootToRootCopy, /*OpIdx*/1, // RB
817 /* 1595 */ GIR_RootConstrainSelectedInstOperands,
818 /* 1596 */ // GIR_Coverage, 668,
819 /* 1596 */ GIR_EraseRootFromParent_Done,
820 /* 1597 */ // Label 125: @1597
821 /* 1597 */ GIM_Reject,
822 /* 1598 */ // Label 122: @1598
823 /* 1598 */ GIM_Reject,
824 /* 1599 */ // Label 111: @1599
825 /* 1599 */ GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(1624), // Rule ID 475 //
826 /* 1604 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
827 /* 1607 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
828 /* 1610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
829 /* 1613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
830 /* 1617 */ // (sub:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VSUBUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
831 /* 1617 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUQM),
832 /* 1622 */ GIR_RootConstrainSelectedInstOperands,
833 /* 1623 */ // GIR_Coverage, 475,
834 /* 1623 */ GIR_Done,
835 /* 1624 */ // Label 126: @1624
836 /* 1624 */ GIM_Reject,
837 /* 1625 */ // Label 112: @1625
838 /* 1625 */ GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(1687),
839 /* 1630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
840 /* 1633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
841 /* 1636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
842 /* 1640 */ GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(1671), // Rule ID 542 //
843 /* 1645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
844 /* 1648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
845 /* 1652 */ GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
846 /* 1658 */ GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
847 /* 1660 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
848 /* 1662 */ // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, v2i64:{ *:[v2i64] }:$VB) => (VNEGD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB)
849 /* 1662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNEGD),
850 /* 1665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
851 /* 1667 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
852 /* 1669 */ GIR_RootConstrainSelectedInstOperands,
853 /* 1670 */ // GIR_Coverage, 542,
854 /* 1670 */ GIR_EraseRootFromParent_Done,
855 /* 1671 */ // Label 128: @1671
856 /* 1671 */ GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(1686), // Rule ID 474 //
857 /* 1676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
858 /* 1679 */ // (sub:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VSUBUDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
859 /* 1679 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUDM),
860 /* 1684 */ GIR_RootConstrainSelectedInstOperands,
861 /* 1685 */ // GIR_Coverage, 474,
862 /* 1685 */ GIR_Done,
863 /* 1686 */ // Label 129: @1686
864 /* 1686 */ GIM_Reject,
865 /* 1687 */ // Label 127: @1687
866 /* 1687 */ GIM_Reject,
867 /* 1688 */ // Label 113: @1688
868 /* 1688 */ GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(1750),
869 /* 1693 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
870 /* 1696 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
871 /* 1699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
872 /* 1703 */ GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(1734), // Rule ID 541 //
873 /* 1708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
874 /* 1711 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
875 /* 1715 */ GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
876 /* 1721 */ GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
877 /* 1723 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
878 /* 1725 */ // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, v4i32:{ *:[v4i32] }:$VB) => (VNEGW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB)
879 /* 1725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNEGW),
880 /* 1728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
881 /* 1730 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
882 /* 1732 */ GIR_RootConstrainSelectedInstOperands,
883 /* 1733 */ // GIR_Coverage, 541,
884 /* 1733 */ GIR_EraseRootFromParent_Done,
885 /* 1734 */ // Label 131: @1734
886 /* 1734 */ GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(1749), // Rule ID 373 //
887 /* 1739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
888 /* 1742 */ // (sub:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
889 /* 1742 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUWM),
890 /* 1747 */ GIR_RootConstrainSelectedInstOperands,
891 /* 1748 */ // GIR_Coverage, 373,
892 /* 1748 */ GIR_Done,
893 /* 1749 */ // Label 132: @1749
894 /* 1749 */ GIM_Reject,
895 /* 1750 */ // Label 130: @1750
896 /* 1750 */ GIM_Reject,
897 /* 1751 */ // Label 114: @1751
898 /* 1751 */ GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(1776), // Rule ID 372 //
899 /* 1756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
900 /* 1759 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
901 /* 1762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
902 /* 1765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
903 /* 1769 */ // (sub:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
904 /* 1769 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUHM),
905 /* 1774 */ GIR_RootConstrainSelectedInstOperands,
906 /* 1775 */ // GIR_Coverage, 372,
907 /* 1775 */ GIR_Done,
908 /* 1776 */ // Label 133: @1776
909 /* 1776 */ GIM_Reject,
910 /* 1777 */ // Label 115: @1777
911 /* 1777 */ GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(1802), // Rule ID 371 //
912 /* 1782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
913 /* 1785 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
914 /* 1788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
915 /* 1791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
916 /* 1795 */ // (sub:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBUBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
917 /* 1795 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUBM),
918 /* 1800 */ GIR_RootConstrainSelectedInstOperands,
919 /* 1801 */ // GIR_Coverage, 371,
920 /* 1801 */ GIR_Done,
921 /* 1802 */ // Label 134: @1802
922 /* 1802 */ GIM_Reject,
923 /* 1803 */ // Label 116: @1803
924 /* 1803 */ GIM_Reject,
925 /* 1804 */ // Label 2: @1804
926 /* 1804 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(7), /*)*//*default:*//*Label 141*/ GIMT_Encode4(2085),
927 /* 1815 */ /*GILLT_s1*//*Label 135*/ GIMT_Encode4(1843),
928 /* 1819 */ /*GILLT_s32*//*Label 136*/ GIMT_Encode4(1866),
929 /* 1823 */ /*GILLT_s64*//*Label 137*/ GIMT_Encode4(1926), GIMT_Encode4(0),
930 /* 1831 */ /*GILLT_v2s64*//*Label 138*/ GIMT_Encode4(1986),
931 /* 1835 */ /*GILLT_v4s32*//*Label 139*/ GIMT_Encode4(2012),
932 /* 1839 */ /*GILLT_v8s16*//*Label 140*/ GIMT_Encode4(2038),
933 /* 1843 */ // Label 135: @1843
934 /* 1843 */ GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(1865), // Rule ID 3671 //
935 /* 1848 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
936 /* 1851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
937 /* 1854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
938 /* 1858 */ // (mul:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRAND:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b)
939 /* 1858 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRAND),
940 /* 1863 */ GIR_RootConstrainSelectedInstOperands,
941 /* 1864 */ // GIR_Coverage, 3671,
942 /* 1864 */ GIR_Done,
943 /* 1865 */ // Label 142: @1865
944 /* 1865 */ GIM_Reject,
945 /* 1866 */ // Label 136: @1866
946 /* 1866 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(1925),
947 /* 1871 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
948 /* 1874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
949 /* 1877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
950 /* 1881 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(1912), // Rule ID 111 //
951 /* 1886 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
952 /* 1890 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
953 /* 1894 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
954 /* 1898 */ // MIs[1] Operand 1
955 /* 1898 */ // No operand predicates
956 /* 1898 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
957 /* 1900 */ // (mul:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$D) => (MULLI:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] }):$D)
958 /* 1900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULLI),
959 /* 1903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
960 /* 1905 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
961 /* 1907 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D
962 /* 1910 */ GIR_RootConstrainSelectedInstOperands,
963 /* 1911 */ // GIR_Coverage, 111,
964 /* 1911 */ GIR_EraseRootFromParent_Done,
965 /* 1912 */ // Label 144: @1912
966 /* 1912 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(1924), // Rule ID 208 //
967 /* 1917 */ // (mul:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MULLW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
968 /* 1917 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULLW),
969 /* 1922 */ GIR_RootConstrainSelectedInstOperands,
970 /* 1923 */ // GIR_Coverage, 208,
971 /* 1923 */ GIR_Done,
972 /* 1924 */ // Label 145: @1924
973 /* 1924 */ GIM_Reject,
974 /* 1925 */ // Label 143: @1925
975 /* 1925 */ GIM_Reject,
976 /* 1926 */ // Label 137: @1926
977 /* 1926 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(1985),
978 /* 1931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
979 /* 1934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
980 /* 1937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
981 /* 1941 */ GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(1972), // Rule ID 706 //
982 /* 1946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
983 /* 1950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
984 /* 1954 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
985 /* 1958 */ // MIs[1] Operand 1
986 /* 1958 */ // No operand predicates
987 /* 1958 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
988 /* 1960 */ // (mul:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$D) => (MULLI8:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] }):$D)
989 /* 1960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULLI8),
990 /* 1963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
991 /* 1965 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
992 /* 1967 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D
993 /* 1970 */ GIR_RootConstrainSelectedInstOperands,
994 /* 1971 */ // GIR_Coverage, 706,
995 /* 1971 */ GIR_EraseRootFromParent_Done,
996 /* 1972 */ // Label 147: @1972
997 /* 1972 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(1984), // Rule ID 705 //
998 /* 1977 */ // (mul:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MULLD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
999 /* 1977 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULLD),
1000 /* 1982 */ GIR_RootConstrainSelectedInstOperands,
1001 /* 1983 */ // GIR_Coverage, 705,
1002 /* 1983 */ GIR_Done,
1003 /* 1984 */ // Label 148: @1984
1004 /* 1984 */ GIM_Reject,
1005 /* 1985 */ // Label 146: @1985
1006 /* 1985 */ GIM_Reject,
1007 /* 1986 */ // Label 138: @1986
1008 /* 1986 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(2011), // Rule ID 1124 //
1009 /* 1991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1010 /* 1994 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1011 /* 1997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1012 /* 2000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1013 /* 2004 */ // (mul:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
1014 /* 2004 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULLD),
1015 /* 2009 */ GIR_RootConstrainSelectedInstOperands,
1016 /* 2010 */ // GIR_Coverage, 1124,
1017 /* 2010 */ GIR_Done,
1018 /* 2011 */ // Label 149: @2011
1019 /* 2011 */ GIM_Reject,
1020 /* 2012 */ // Label 139: @2012
1021 /* 2012 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(2037), // Rule ID 461 //
1022 /* 2017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
1023 /* 2020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1024 /* 2023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1025 /* 2026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1026 /* 2030 */ // (mul:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
1027 /* 2030 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULUWM),
1028 /* 2035 */ GIR_RootConstrainSelectedInstOperands,
1029 /* 2036 */ // GIR_Coverage, 461,
1030 /* 2036 */ GIR_Done,
1031 /* 2037 */ // Label 150: @2037
1032 /* 2037 */ GIM_Reject,
1033 /* 2038 */ // Label 140: @2038
1034 /* 2038 */ GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(2084), // Rule ID 1295 //
1035 /* 2043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
1036 /* 2046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1037 /* 2049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1038 /* 2052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1039 /* 2056 */ // (mul:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMLADDUHM:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB, (V_SET0H:{ *:[v8i16] }))
1040 /* 2056 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
1041 /* 2059 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::V_SET0H),
1042 /* 2063 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1043 /* 2068 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1044 /* 2070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMLADDUHM),
1045 /* 2073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
1046 /* 2075 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
1047 /* 2077 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
1048 /* 2079 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
1049 /* 2082 */ GIR_RootConstrainSelectedInstOperands,
1050 /* 2083 */ // GIR_Coverage, 1295,
1051 /* 2083 */ GIR_EraseRootFromParent_Done,
1052 /* 2084 */ // Label 151: @2084
1053 /* 2084 */ GIM_Reject,
1054 /* 2085 */ // Label 141: @2085
1055 /* 2085 */ GIM_Reject,
1056 /* 2086 */ // Label 3: @2086
1057 /* 2086 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 157*/ GIMT_Encode4(2241),
1058 /* 2097 */ /*GILLT_s32*//*Label 152*/ GIMT_Encode4(2117),
1059 /* 2101 */ /*GILLT_s64*//*Label 153*/ GIMT_Encode4(2140),
1060 /* 2105 */ /*GILLT_s128*//*Label 154*/ GIMT_Encode4(2163),
1061 /* 2109 */ /*GILLT_v2s64*//*Label 155*/ GIMT_Encode4(2189),
1062 /* 2113 */ /*GILLT_v4s32*//*Label 156*/ GIMT_Encode4(2215),
1063 /* 2117 */ // Label 152: @2117
1064 /* 2117 */ GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(2139), // Rule ID 202 //
1065 /* 2122 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1066 /* 2125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1067 /* 2128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
1068 /* 2132 */ // (sdiv:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (DIVW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
1069 /* 2132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVW),
1070 /* 2137 */ GIR_RootConstrainSelectedInstOperands,
1071 /* 2138 */ // GIR_Coverage, 202,
1072 /* 2138 */ GIR_Done,
1073 /* 2139 */ // Label 158: @2139
1074 /* 2139 */ GIM_Reject,
1075 /* 2140 */ // Label 153: @2140
1076 /* 2140 */ GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(2162), // Rule ID 697 //
1077 /* 2145 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1078 /* 2148 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1079 /* 2151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
1080 /* 2155 */ // (sdiv:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (DIVD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
1081 /* 2155 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVD),
1082 /* 2160 */ GIR_RootConstrainSelectedInstOperands,
1083 /* 2161 */ // GIR_Coverage, 697,
1084 /* 2161 */ GIR_Done,
1085 /* 2162 */ // Label 159: @2162
1086 /* 2162 */ GIM_Reject,
1087 /* 2163 */ // Label 154: @2163
1088 /* 2163 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(2188), // Rule ID 1148 //
1089 /* 2168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1090 /* 2171 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
1091 /* 2174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
1092 /* 2177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1093 /* 2181 */ // (sdiv:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVSQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
1094 /* 2181 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSQ),
1095 /* 2186 */ GIR_RootConstrainSelectedInstOperands,
1096 /* 2187 */ // GIR_Coverage, 1148,
1097 /* 2187 */ GIR_Done,
1098 /* 2188 */ // Label 160: @2188
1099 /* 2188 */ GIM_Reject,
1100 /* 2189 */ // Label 155: @2189
1101 /* 2189 */ GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(2214), // Rule ID 1135 //
1102 /* 2194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1103 /* 2197 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1104 /* 2200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1105 /* 2203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1106 /* 2207 */ // (sdiv:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
1107 /* 2207 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSD),
1108 /* 2212 */ GIR_RootConstrainSelectedInstOperands,
1109 /* 2213 */ // GIR_Coverage, 1135,
1110 /* 2213 */ GIR_Done,
1111 /* 2214 */ // Label 161: @2214
1112 /* 2214 */ GIM_Reject,
1113 /* 2215 */ // Label 156: @2215
1114 /* 2215 */ GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(2240), // Rule ID 1133 //
1115 /* 2220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1116 /* 2223 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1117 /* 2226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1118 /* 2229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1119 /* 2233 */ // (sdiv:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
1120 /* 2233 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSW),
1121 /* 2238 */ GIR_RootConstrainSelectedInstOperands,
1122 /* 2239 */ // GIR_Coverage, 1133,
1123 /* 2239 */ GIR_Done,
1124 /* 2240 */ // Label 162: @2240
1125 /* 2240 */ GIM_Reject,
1126 /* 2241 */ // Label 157: @2241
1127 /* 2241 */ GIM_Reject,
1128 /* 2242 */ // Label 4: @2242
1129 /* 2242 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 168*/ GIMT_Encode4(2397),
1130 /* 2253 */ /*GILLT_s32*//*Label 163*/ GIMT_Encode4(2273),
1131 /* 2257 */ /*GILLT_s64*//*Label 164*/ GIMT_Encode4(2296),
1132 /* 2261 */ /*GILLT_s128*//*Label 165*/ GIMT_Encode4(2319),
1133 /* 2265 */ /*GILLT_v2s64*//*Label 166*/ GIMT_Encode4(2345),
1134 /* 2269 */ /*GILLT_v4s32*//*Label 167*/ GIMT_Encode4(2371),
1135 /* 2273 */ // Label 163: @2273
1136 /* 2273 */ GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(2295), // Rule ID 203 //
1137 /* 2278 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1138 /* 2281 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1139 /* 2284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
1140 /* 2288 */ // (udiv:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (DIVWU:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
1141 /* 2288 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVWU),
1142 /* 2293 */ GIR_RootConstrainSelectedInstOperands,
1143 /* 2294 */ // GIR_Coverage, 203,
1144 /* 2294 */ GIR_Done,
1145 /* 2295 */ // Label 169: @2295
1146 /* 2295 */ GIM_Reject,
1147 /* 2296 */ // Label 164: @2296
1148 /* 2296 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(2318), // Rule ID 698 //
1149 /* 2301 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1150 /* 2304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1151 /* 2307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
1152 /* 2311 */ // (udiv:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (DIVDU:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
1153 /* 2311 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVDU),
1154 /* 2316 */ GIR_RootConstrainSelectedInstOperands,
1155 /* 2317 */ // GIR_Coverage, 698,
1156 /* 2317 */ GIR_Done,
1157 /* 2318 */ // Label 170: @2318
1158 /* 2318 */ GIM_Reject,
1159 /* 2319 */ // Label 165: @2319
1160 /* 2319 */ GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(2344), // Rule ID 1149 //
1161 /* 2324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1162 /* 2327 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
1163 /* 2330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
1164 /* 2333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1165 /* 2337 */ // (udiv:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
1166 /* 2337 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUQ),
1167 /* 2342 */ GIR_RootConstrainSelectedInstOperands,
1168 /* 2343 */ // GIR_Coverage, 1149,
1169 /* 2343 */ GIR_Done,
1170 /* 2344 */ // Label 171: @2344
1171 /* 2344 */ GIM_Reject,
1172 /* 2345 */ // Label 166: @2345
1173 /* 2345 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(2370), // Rule ID 1136 //
1174 /* 2350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1175 /* 2353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1176 /* 2356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1177 /* 2359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1178 /* 2363 */ // (udiv:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
1179 /* 2363 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUD),
1180 /* 2368 */ GIR_RootConstrainSelectedInstOperands,
1181 /* 2369 */ // GIR_Coverage, 1136,
1182 /* 2369 */ GIR_Done,
1183 /* 2370 */ // Label 172: @2370
1184 /* 2370 */ GIM_Reject,
1185 /* 2371 */ // Label 167: @2371
1186 /* 2371 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(2396), // Rule ID 1134 //
1187 /* 2376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1188 /* 2379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1189 /* 2382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1190 /* 2385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1191 /* 2389 */ // (udiv:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
1192 /* 2389 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUW),
1193 /* 2394 */ GIR_RootConstrainSelectedInstOperands,
1194 /* 2395 */ // GIR_Coverage, 1134,
1195 /* 2395 */ GIR_Done,
1196 /* 2396 */ // Label 173: @2396
1197 /* 2396 */ GIM_Reject,
1198 /* 2397 */ // Label 168: @2397
1199 /* 2397 */ GIM_Reject,
1200 /* 2398 */ // Label 5: @2398
1201 /* 2398 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 179*/ GIMT_Encode4(2559),
1202 /* 2409 */ /*GILLT_s32*//*Label 174*/ GIMT_Encode4(2429),
1203 /* 2413 */ /*GILLT_s64*//*Label 175*/ GIMT_Encode4(2455),
1204 /* 2417 */ /*GILLT_s128*//*Label 176*/ GIMT_Encode4(2481),
1205 /* 2421 */ /*GILLT_v2s64*//*Label 177*/ GIMT_Encode4(2507),
1206 /* 2425 */ /*GILLT_v4s32*//*Label 178*/ GIMT_Encode4(2533),
1207 /* 2429 */ // Label 174: @2429
1208 /* 2429 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(2454), // Rule ID 197 //
1209 /* 2434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
1210 /* 2437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1211 /* 2440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1212 /* 2443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
1213 /* 2447 */ // (srem:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MODSW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
1214 /* 2447 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODSW),
1215 /* 2452 */ GIR_RootConstrainSelectedInstOperands,
1216 /* 2453 */ // GIR_Coverage, 197,
1217 /* 2453 */ GIR_Done,
1218 /* 2454 */ // Label 180: @2454
1219 /* 2454 */ GIM_Reject,
1220 /* 2455 */ // Label 175: @2455
1221 /* 2455 */ GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(2480), // Rule ID 702 //
1222 /* 2460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
1223 /* 2463 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1224 /* 2466 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1225 /* 2469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
1226 /* 2473 */ // (srem:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MODSD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
1227 /* 2473 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODSD),
1228 /* 2478 */ GIR_RootConstrainSelectedInstOperands,
1229 /* 2479 */ // GIR_Coverage, 702,
1230 /* 2479 */ GIR_Done,
1231 /* 2480 */ // Label 181: @2480
1232 /* 2480 */ GIM_Reject,
1233 /* 2481 */ // Label 176: @2481
1234 /* 2481 */ GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(2506), // Rule ID 1158 //
1235 /* 2486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1236 /* 2489 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
1237 /* 2492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
1238 /* 2495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1239 /* 2499 */ // (srem:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VMODSQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
1240 /* 2499 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSQ),
1241 /* 2504 */ GIR_RootConstrainSelectedInstOperands,
1242 /* 2505 */ // GIR_Coverage, 1158,
1243 /* 2505 */ GIR_Done,
1244 /* 2506 */ // Label 182: @2506
1245 /* 2506 */ GIM_Reject,
1246 /* 2507 */ // Label 177: @2507
1247 /* 2507 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(2532), // Rule ID 1131 //
1248 /* 2512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1249 /* 2515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1250 /* 2518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1251 /* 2521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1252 /* 2525 */ // (srem:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMODSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
1253 /* 2525 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSD),
1254 /* 2530 */ GIR_RootConstrainSelectedInstOperands,
1255 /* 2531 */ // GIR_Coverage, 1131,
1256 /* 2531 */ GIR_Done,
1257 /* 2532 */ // Label 183: @2532
1258 /* 2532 */ GIM_Reject,
1259 /* 2533 */ // Label 178: @2533
1260 /* 2533 */ GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(2558), // Rule ID 1129 //
1261 /* 2538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1262 /* 2541 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1263 /* 2544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1264 /* 2547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1265 /* 2551 */ // (srem:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMODSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
1266 /* 2551 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSW),
1267 /* 2556 */ GIR_RootConstrainSelectedInstOperands,
1268 /* 2557 */ // GIR_Coverage, 1129,
1269 /* 2557 */ GIR_Done,
1270 /* 2558 */ // Label 184: @2558
1271 /* 2558 */ GIM_Reject,
1272 /* 2559 */ // Label 179: @2559
1273 /* 2559 */ GIM_Reject,
1274 /* 2560 */ // Label 6: @2560
1275 /* 2560 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 190*/ GIMT_Encode4(2721),
1276 /* 2571 */ /*GILLT_s32*//*Label 185*/ GIMT_Encode4(2591),
1277 /* 2575 */ /*GILLT_s64*//*Label 186*/ GIMT_Encode4(2617),
1278 /* 2579 */ /*GILLT_s128*//*Label 187*/ GIMT_Encode4(2643),
1279 /* 2583 */ /*GILLT_v2s64*//*Label 188*/ GIMT_Encode4(2669),
1280 /* 2587 */ /*GILLT_v4s32*//*Label 189*/ GIMT_Encode4(2695),
1281 /* 2591 */ // Label 185: @2591
1282 /* 2591 */ GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(2616), // Rule ID 198 //
1283 /* 2596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
1284 /* 2599 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1285 /* 2602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1286 /* 2605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
1287 /* 2609 */ // (urem:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MODUW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
1288 /* 2609 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODUW),
1289 /* 2614 */ GIR_RootConstrainSelectedInstOperands,
1290 /* 2615 */ // GIR_Coverage, 198,
1291 /* 2615 */ GIR_Done,
1292 /* 2616 */ // Label 191: @2616
1293 /* 2616 */ GIM_Reject,
1294 /* 2617 */ // Label 186: @2617
1295 /* 2617 */ GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(2642), // Rule ID 703 //
1296 /* 2622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
1297 /* 2625 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1298 /* 2628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1299 /* 2631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
1300 /* 2635 */ // (urem:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MODUD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
1301 /* 2635 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODUD),
1302 /* 2640 */ GIR_RootConstrainSelectedInstOperands,
1303 /* 2641 */ // GIR_Coverage, 703,
1304 /* 2641 */ GIR_Done,
1305 /* 2642 */ // Label 192: @2642
1306 /* 2642 */ GIM_Reject,
1307 /* 2643 */ // Label 187: @2643
1308 /* 2643 */ GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(2668), // Rule ID 1159 //
1309 /* 2648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1310 /* 2651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
1311 /* 2654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
1312 /* 2657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1313 /* 2661 */ // (urem:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VMODUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
1314 /* 2661 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUQ),
1315 /* 2666 */ GIR_RootConstrainSelectedInstOperands,
1316 /* 2667 */ // GIR_Coverage, 1159,
1317 /* 2667 */ GIR_Done,
1318 /* 2668 */ // Label 193: @2668
1319 /* 2668 */ GIM_Reject,
1320 /* 2669 */ // Label 188: @2669
1321 /* 2669 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(2694), // Rule ID 1132 //
1322 /* 2674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1323 /* 2677 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1324 /* 2680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1325 /* 2683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1326 /* 2687 */ // (urem:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMODUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
1327 /* 2687 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUD),
1328 /* 2692 */ GIR_RootConstrainSelectedInstOperands,
1329 /* 2693 */ // GIR_Coverage, 1132,
1330 /* 2693 */ GIR_Done,
1331 /* 2694 */ // Label 194: @2694
1332 /* 2694 */ GIM_Reject,
1333 /* 2695 */ // Label 189: @2695
1334 /* 2695 */ GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(2720), // Rule ID 1130 //
1335 /* 2700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
1336 /* 2703 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1337 /* 2706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1338 /* 2709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
1339 /* 2713 */ // (urem:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMODUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
1340 /* 2713 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUW),
1341 /* 2718 */ GIR_RootConstrainSelectedInstOperands,
1342 /* 2719 */ // GIR_Coverage, 1130,
1343 /* 2719 */ GIR_Done,
1344 /* 2720 */ // Label 195: @2720
1345 /* 2720 */ GIM_Reject,
1346 /* 2721 */ // Label 190: @2721
1347 /* 2721 */ GIM_Reject,
1348 /* 2722 */ // Label 7: @2722
1349 /* 2722 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 200*/ GIMT_Encode4(5282),
1350 /* 2733 */ /*GILLT_s1*//*Label 196*/ GIMT_Encode4(2757),
1351 /* 2737 */ /*GILLT_s32*//*Label 197*/ GIMT_Encode4(2866),
1352 /* 2741 */ /*GILLT_s64*//*Label 198*/ GIMT_Encode4(2975), GIMT_Encode4(0), GIMT_Encode4(0),
1353 /* 2753 */ /*GILLT_v4s32*//*Label 199*/ GIMT_Encode4(3084),
1354 /* 2757 */ // Label 196: @2757
1355 /* 2757 */ GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(2865),
1356 /* 2762 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
1357 /* 2765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
1358 /* 2768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
1359 /* 2772 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(2812), // Rule ID 4924 //
1360 /* 2777 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1361 /* 2781 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1362 /* 2785 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
1363 /* 2789 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
1364 /* 2793 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
1365 /* 2797 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1366 /* 2799 */ // (and:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRA) => (CRANDC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
1367 /* 2799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC),
1368 /* 2802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
1369 /* 2804 */ GIR_RootToRootCopy, /*OpIdx*/2, // CRA
1370 /* 2806 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB
1371 /* 2810 */ GIR_RootConstrainSelectedInstOperands,
1372 /* 2811 */ // GIR_Coverage, 4924,
1373 /* 2811 */ GIR_EraseRootFromParent_Done,
1374 /* 2812 */ // Label 202: @2812
1375 /* 2812 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(2852), // Rule ID 182 //
1376 /* 2817 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1377 /* 2821 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1378 /* 2825 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
1379 /* 2829 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
1380 /* 2833 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
1381 /* 2837 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1382 /* 2839 */ // (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] })) => (CRANDC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
1383 /* 2839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC),
1384 /* 2842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
1385 /* 2844 */ GIR_RootToRootCopy, /*OpIdx*/1, // CRA
1386 /* 2846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB
1387 /* 2850 */ GIR_RootConstrainSelectedInstOperands,
1388 /* 2851 */ // GIR_Coverage, 182,
1389 /* 2851 */ GIR_EraseRootFromParent_Done,
1390 /* 2852 */ // Label 203: @2852
1391 /* 2852 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(2864), // Rule ID 175 //
1392 /* 2857 */ // (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CRAND:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
1393 /* 2857 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRAND),
1394 /* 2862 */ GIR_RootConstrainSelectedInstOperands,
1395 /* 2863 */ // GIR_Coverage, 175,
1396 /* 2863 */ GIR_Done,
1397 /* 2864 */ // Label 204: @2864
1398 /* 2864 */ GIM_Reject,
1399 /* 2865 */ // Label 201: @2865
1400 /* 2865 */ GIM_Reject,
1401 /* 2866 */ // Label 197: @2866
1402 /* 2866 */ GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(2974),
1403 /* 2871 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1404 /* 2874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1405 /* 2877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
1406 /* 2881 */ GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(2921), // Rule ID 4918 //
1407 /* 2886 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1408 /* 2890 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1409 /* 2894 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1410 /* 2898 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1411 /* 2902 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
1412 /* 2906 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1413 /* 2908 */ // (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] }), i32:{ *:[i32] }:$RST) => (ANDC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
1414 /* 2908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC),
1415 /* 2911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
1416 /* 2913 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
1417 /* 2915 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
1418 /* 2919 */ GIR_RootConstrainSelectedInstOperands,
1419 /* 2920 */ // GIR_Coverage, 4918,
1420 /* 2920 */ GIR_EraseRootFromParent_Done,
1421 /* 2921 */ // Label 206: @2921
1422 /* 2921 */ GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(2961), // Rule ID 123 //
1423 /* 2926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1424 /* 2930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1425 /* 2934 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1426 /* 2938 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1427 /* 2942 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
1428 /* 2946 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1429 /* 2948 */ // (and:{ *:[i32] } i32:{ *:[i32] }:$RST, (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] })) => (ANDC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
1430 /* 2948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC),
1431 /* 2951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
1432 /* 2953 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
1433 /* 2955 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
1434 /* 2959 */ GIR_RootConstrainSelectedInstOperands,
1435 /* 2960 */ // GIR_Coverage, 123,
1436 /* 2960 */ GIR_EraseRootFromParent_Done,
1437 /* 2961 */ // Label 207: @2961
1438 /* 2961 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(2973), // Rule ID 122 //
1439 /* 2966 */ // (and:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (AND:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
1440 /* 2966 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::AND),
1441 /* 2971 */ GIR_RootConstrainSelectedInstOperands,
1442 /* 2972 */ // GIR_Coverage, 122,
1443 /* 2972 */ GIR_Done,
1444 /* 2973 */ // Label 208: @2973
1445 /* 2973 */ GIM_Reject,
1446 /* 2974 */ // Label 205: @2974
1447 /* 2974 */ GIM_Reject,
1448 /* 2975 */ // Label 198: @2975
1449 /* 2975 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(3083),
1450 /* 2980 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1451 /* 2983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1452 /* 2986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
1453 /* 2990 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(3030), // Rule ID 4931 //
1454 /* 2995 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1455 /* 2999 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1456 /* 3003 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1457 /* 3007 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1458 /* 3011 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
1459 /* 3015 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1460 /* 3017 */ // (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] }), i64:{ *:[i64] }:$RST) => (ANDC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
1461 /* 3017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC8),
1462 /* 3020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
1463 /* 3022 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
1464 /* 3024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
1465 /* 3028 */ GIR_RootConstrainSelectedInstOperands,
1466 /* 3029 */ // GIR_Coverage, 4931,
1467 /* 3029 */ GIR_EraseRootFromParent_Done,
1468 /* 3030 */ // Label 210: @3030
1469 /* 3030 */ GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(3070), // Rule ID 647 //
1470 /* 3035 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1471 /* 3039 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1472 /* 3043 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1473 /* 3047 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
1474 /* 3051 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
1475 /* 3055 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1476 /* 3057 */ // (and:{ *:[i64] } i64:{ *:[i64] }:$RST, (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] })) => (ANDC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
1477 /* 3057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC8),
1478 /* 3060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
1479 /* 3062 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
1480 /* 3064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
1481 /* 3068 */ GIR_RootConstrainSelectedInstOperands,
1482 /* 3069 */ // GIR_Coverage, 647,
1483 /* 3069 */ GIR_EraseRootFromParent_Done,
1484 /* 3070 */ // Label 211: @3070
1485 /* 3070 */ GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(3082), // Rule ID 646 //
1486 /* 3075 */ // (and:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (AND8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
1487 /* 3075 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::AND8),
1488 /* 3080 */ GIR_RootConstrainSelectedInstOperands,
1489 /* 3081 */ // GIR_Coverage, 646,
1490 /* 3081 */ GIR_Done,
1491 /* 3082 */ // Label 212: @3082
1492 /* 3082 */ GIM_Reject,
1493 /* 3083 */ // Label 209: @3083
1494 /* 3083 */ GIM_Reject,
1495 /* 3084 */ // Label 199: @3084
1496 /* 3084 */ GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(5281),
1497 /* 3089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1498 /* 3092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1499 /* 3095 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(3173), // Rule ID 5279 //
1500 /* 3100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1501 /* 3103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1502 /* 3107 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1503 /* 3111 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1504 /* 3115 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1505 /* 3119 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1506 /* 3123 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1507 /* 3127 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1508 /* 3131 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1509 /* 3135 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1510 /* 3139 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1511 /* 3143 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1512 /* 3149 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1513 /* 3151 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1514 /* 3153 */ // (and:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 16:{ *:[i32] })
1515 /* 3153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1516 /* 3156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1517 /* 3158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
1518 /* 3162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
1519 /* 3166 */ GIR_RootToRootCopy, /*OpIdx*/2, // vC
1520 /* 3168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
1521 /* 3171 */ GIR_RootConstrainSelectedInstOperands,
1522 /* 3172 */ // GIR_Coverage, 5279,
1523 /* 3172 */ GIR_EraseRootFromParent_Done,
1524 /* 3173 */ // Label 214: @3173
1525 /* 3173 */ GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(3251), // Rule ID 5280 //
1526 /* 3178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1527 /* 3181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1528 /* 3185 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1529 /* 3189 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1530 /* 3193 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1531 /* 3197 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1532 /* 3201 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
1533 /* 3205 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1534 /* 3209 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1535 /* 3213 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1536 /* 3217 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1537 /* 3221 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1538 /* 3227 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1539 /* 3229 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1540 /* 3231 */ // (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })), v4i32:{ *:[v4i32] }:$vC) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 16:{ *:[i32] })
1541 /* 3231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1542 /* 3234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1543 /* 3236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
1544 /* 3240 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
1545 /* 3244 */ GIR_RootToRootCopy, /*OpIdx*/2, // vC
1546 /* 3246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
1547 /* 3249 */ GIR_RootConstrainSelectedInstOperands,
1548 /* 3250 */ // GIR_Coverage, 5280,
1549 /* 3250 */ GIR_EraseRootFromParent_Done,
1550 /* 3251 */ // Label 215: @3251
1551 /* 3251 */ GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(3331), // Rule ID 5281 //
1552 /* 3256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1553 /* 3259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1554 /* 3263 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1555 /* 3267 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1556 /* 3271 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1557 /* 3275 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1558 /* 3279 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1559 /* 3283 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1560 /* 3287 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1561 /* 3291 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1562 /* 3295 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1563 /* 3299 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1564 /* 3305 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1565 /* 3307 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1566 /* 3309 */ // (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 16:{ *:[i32] })
1567 /* 3309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1568 /* 3312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1569 /* 3314 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
1570 /* 3318 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
1571 /* 3322 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
1572 /* 3326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
1573 /* 3329 */ GIR_RootConstrainSelectedInstOperands,
1574 /* 3330 */ // GIR_Coverage, 5281,
1575 /* 3330 */ GIR_EraseRootFromParent_Done,
1576 /* 3331 */ // Label 216: @3331
1577 /* 3331 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(3411), // Rule ID 5284 //
1578 /* 3336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1579 /* 3339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1580 /* 3343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1581 /* 3347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
1582 /* 3351 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1583 /* 3355 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1584 /* 3359 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1585 /* 3363 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1586 /* 3367 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1587 /* 3371 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1588 /* 3375 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1589 /* 3379 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1590 /* 3385 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1591 /* 3387 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1592 /* 3389 */ // (and:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 112:{ *:[i32] })
1593 /* 3389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1594 /* 3392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1595 /* 3394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
1596 /* 3398 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
1597 /* 3402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
1598 /* 3406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/112,
1599 /* 3409 */ GIR_RootConstrainSelectedInstOperands,
1600 /* 3410 */ // GIR_Coverage, 5284,
1601 /* 3410 */ GIR_EraseRootFromParent_Done,
1602 /* 3411 */ // Label 217: @3411
1603 /* 3411 */ GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(3489), // Rule ID 4968 //
1604 /* 3416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1605 /* 3419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1606 /* 3423 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1607 /* 3427 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1608 /* 3431 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1609 /* 3435 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1610 /* 3439 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1611 /* 3443 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
1612 /* 3447 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1613 /* 3451 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1614 /* 3455 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1615 /* 3459 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1616 /* 3465 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1617 /* 3467 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1618 /* 3469 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 14:{ *:[i32] })
1619 /* 3469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1620 /* 3472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1621 /* 3474 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
1622 /* 3476 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1623 /* 3480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
1624 /* 3484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1625 /* 3487 */ GIR_RootConstrainSelectedInstOperands,
1626 /* 3488 */ // GIR_Coverage, 4968,
1627 /* 3488 */ GIR_EraseRootFromParent_Done,
1628 /* 3489 */ // Label 218: @3489
1629 /* 3489 */ GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(3567), // Rule ID 4962 //
1630 /* 3494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1631 /* 3497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1632 /* 3501 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1633 /* 3505 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1634 /* 3509 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1635 /* 3513 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1636 /* 3517 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1637 /* 3521 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1638 /* 3525 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1639 /* 3529 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1640 /* 3533 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1641 /* 3537 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1642 /* 3543 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1643 /* 3545 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1644 /* 3547 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 8:{ *:[i32] })
1645 /* 3547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1646 /* 3550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1647 /* 3552 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
1648 /* 3554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1649 /* 3558 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
1650 /* 3562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
1651 /* 3565 */ GIR_RootConstrainSelectedInstOperands,
1652 /* 3566 */ // GIR_Coverage, 4962,
1653 /* 3566 */ GIR_EraseRootFromParent_Done,
1654 /* 3567 */ // Label 219: @3567
1655 /* 3567 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(3645), // Rule ID 4966 //
1656 /* 3572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1657 /* 3575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1658 /* 3579 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1659 /* 3583 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1660 /* 3587 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1661 /* 3591 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1662 /* 3595 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1663 /* 3599 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1664 /* 3603 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1665 /* 3607 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1666 /* 3611 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1667 /* 3615 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1668 /* 3621 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1669 /* 3623 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1670 /* 3625 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 9:{ *:[i32] })
1671 /* 3625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1672 /* 3628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1673 /* 3630 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
1674 /* 3632 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1675 /* 3636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
1676 /* 3640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
1677 /* 3643 */ GIR_RootConstrainSelectedInstOperands,
1678 /* 3644 */ // GIR_Coverage, 4966,
1679 /* 3644 */ GIR_EraseRootFromParent_Done,
1680 /* 3645 */ // Label 220: @3645
1681 /* 3645 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(3723), // Rule ID 4965 //
1682 /* 3650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1683 /* 3653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1684 /* 3657 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1685 /* 3661 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1686 /* 3665 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1687 /* 3669 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1688 /* 3673 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1689 /* 3677 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1690 /* 3681 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1691 /* 3685 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1692 /* 3689 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1693 /* 3693 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1694 /* 3699 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1695 /* 3701 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1696 /* 3703 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 9:{ *:[i32] })
1697 /* 3703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1698 /* 3706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1699 /* 3708 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
1700 /* 3710 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1701 /* 3714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
1702 /* 3718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
1703 /* 3721 */ GIR_RootConstrainSelectedInstOperands,
1704 /* 3722 */ // GIR_Coverage, 4965,
1705 /* 3722 */ GIR_EraseRootFromParent_Done,
1706 /* 3723 */ // Label 221: @3723
1707 /* 3723 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(3801), // Rule ID 4967 //
1708 /* 3728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1709 /* 3731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1710 /* 3735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1711 /* 3739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1712 /* 3743 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1713 /* 3747 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1714 /* 3751 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
1715 /* 3755 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1716 /* 3759 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1717 /* 3763 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1718 /* 3767 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1719 /* 3771 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1720 /* 3777 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1721 /* 3779 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1722 /* 3781 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] })), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 9:{ *:[i32] })
1723 /* 3781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1724 /* 3784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1725 /* 3786 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
1726 /* 3788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1727 /* 3792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
1728 /* 3796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
1729 /* 3799 */ GIR_RootConstrainSelectedInstOperands,
1730 /* 3800 */ // GIR_Coverage, 4967,
1731 /* 3800 */ GIR_EraseRootFromParent_Done,
1732 /* 3801 */ // Label 222: @3801
1733 /* 3801 */ GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(3881), // Rule ID 3405 //
1734 /* 3806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1735 /* 3809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1736 /* 3813 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1737 /* 3817 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1738 /* 3821 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1739 /* 3825 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1740 /* 3829 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
1741 /* 3833 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1742 /* 3839 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
1743 /* 3841 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
1744 /* 3845 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
1745 /* 3849 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
1746 /* 3853 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
1747 /* 3857 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1748 /* 3859 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 16:{ *:[i32] })
1749 /* 3859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1750 /* 3862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1751 /* 3864 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
1752 /* 3868 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
1753 /* 3872 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
1754 /* 3876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
1755 /* 3879 */ GIR_RootConstrainSelectedInstOperands,
1756 /* 3880 */ // GIR_Coverage, 3405,
1757 /* 3880 */ GIR_EraseRootFromParent_Done,
1758 /* 3881 */ // Label 223: @3881
1759 /* 3881 */ GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(3961), // Rule ID 3406 //
1760 /* 3886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1761 /* 3889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1762 /* 3893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1763 /* 3897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1764 /* 3901 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1765 /* 3905 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1766 /* 3909 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
1767 /* 3913 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1768 /* 3919 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
1769 /* 3921 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
1770 /* 3925 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
1771 /* 3929 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
1772 /* 3933 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
1773 /* 3937 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1774 /* 3939 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 112:{ *:[i32] })
1775 /* 3939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1776 /* 3942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1777 /* 3944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
1778 /* 3948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
1779 /* 3952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
1780 /* 3956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/112,
1781 /* 3959 */ GIR_RootConstrainSelectedInstOperands,
1782 /* 3960 */ // GIR_Coverage, 3406,
1783 /* 3960 */ GIR_EraseRootFromParent_Done,
1784 /* 3961 */ // Label 224: @3961
1785 /* 3961 */ GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(4041), // Rule ID 3404 //
1786 /* 3966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1787 /* 3969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1788 /* 3973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1789 /* 3977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1790 /* 3981 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1791 /* 3985 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1792 /* 3989 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
1793 /* 3993 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1794 /* 3999 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
1795 /* 4001 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
1796 /* 4005 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
1797 /* 4009 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
1798 /* 4013 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
1799 /* 4017 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1800 /* 4019 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 96:{ *:[i32] })
1801 /* 4019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1802 /* 4022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1803 /* 4024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
1804 /* 4028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
1805 /* 4032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
1806 /* 4036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/96,
1807 /* 4039 */ GIR_RootConstrainSelectedInstOperands,
1808 /* 4040 */ // GIR_Coverage, 3404,
1809 /* 4040 */ GIR_EraseRootFromParent_Done,
1810 /* 4041 */ // Label 225: @4041
1811 /* 4041 */ GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(4121), // Rule ID 5278 //
1812 /* 4046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1813 /* 4049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1814 /* 4053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1815 /* 4057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1816 /* 4061 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1817 /* 4065 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1818 /* 4069 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1819 /* 4073 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1820 /* 4077 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1821 /* 4081 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1822 /* 4085 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1823 /* 4089 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1824 /* 4095 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1825 /* 4097 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1826 /* 4099 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 96:{ *:[i32] })
1827 /* 4099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1828 /* 4102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1829 /* 4104 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
1830 /* 4108 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
1831 /* 4112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
1832 /* 4116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/96,
1833 /* 4119 */ GIR_RootConstrainSelectedInstOperands,
1834 /* 4120 */ // GIR_Coverage, 5278,
1835 /* 4120 */ GIR_EraseRootFromParent_Done,
1836 /* 4121 */ // Label 226: @4121
1837 /* 4121 */ GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(4199), // Rule ID 5282 //
1838 /* 4126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1839 /* 4129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1840 /* 4133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1841 /* 4137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1842 /* 4141 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1843 /* 4145 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1844 /* 4149 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1845 /* 4153 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1846 /* 4157 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1847 /* 4161 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1848 /* 4165 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1849 /* 4169 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1850 /* 4175 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1851 /* 4177 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1852 /* 4179 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 16:{ *:[i32] })
1853 /* 4179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1854 /* 4182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1855 /* 4184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
1856 /* 4188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
1857 /* 4192 */ GIR_RootToRootCopy, /*OpIdx*/1, // vC
1858 /* 4194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
1859 /* 4197 */ GIR_RootConstrainSelectedInstOperands,
1860 /* 4198 */ // GIR_Coverage, 5282,
1861 /* 4198 */ GIR_EraseRootFromParent_Done,
1862 /* 4199 */ // Label 227: @4199
1863 /* 4199 */ GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(4277), // Rule ID 5283 //
1864 /* 4204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1865 /* 4207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1866 /* 4211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1867 /* 4215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1868 /* 4219 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1869 /* 4223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1870 /* 4227 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
1871 /* 4231 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1872 /* 4235 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1873 /* 4239 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1874 /* 4243 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1875 /* 4247 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1876 /* 4253 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1877 /* 4255 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1878 /* 4257 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 16:{ *:[i32] })
1879 /* 4257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1880 /* 4260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1881 /* 4262 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
1882 /* 4266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
1883 /* 4270 */ GIR_RootToRootCopy, /*OpIdx*/1, // vC
1884 /* 4272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
1885 /* 4275 */ GIR_RootConstrainSelectedInstOperands,
1886 /* 4276 */ // GIR_Coverage, 5283,
1887 /* 4276 */ GIR_EraseRootFromParent_Done,
1888 /* 4277 */ // Label 228: @4277
1889 /* 4277 */ GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(4355), // Rule ID 3392 //
1890 /* 4282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1891 /* 4285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1892 /* 4289 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1893 /* 4293 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1894 /* 4297 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1895 /* 4301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1896 /* 4305 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1897 /* 4309 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
1898 /* 4313 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1899 /* 4317 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1900 /* 4321 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1901 /* 4325 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1902 /* 4331 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1903 /* 4333 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1904 /* 4335 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 14:{ *:[i32] })
1905 /* 4335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1906 /* 4338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1907 /* 4340 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
1908 /* 4342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1909 /* 4346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
1910 /* 4350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1911 /* 4353 */ GIR_RootConstrainSelectedInstOperands,
1912 /* 4354 */ // GIR_Coverage, 3392,
1913 /* 4354 */ GIR_EraseRootFromParent_Done,
1914 /* 4355 */ // Label 229: @4355
1915 /* 4355 */ GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(4433), // Rule ID 3390 //
1916 /* 4360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1917 /* 4363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1918 /* 4367 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1919 /* 4371 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1920 /* 4375 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1921 /* 4379 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1922 /* 4383 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1923 /* 4387 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1924 /* 4391 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1925 /* 4395 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1926 /* 4399 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1927 /* 4403 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1928 /* 4409 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1929 /* 4411 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1930 /* 4413 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 8:{ *:[i32] })
1931 /* 4413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1932 /* 4416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1933 /* 4418 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
1934 /* 4420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1935 /* 4424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
1936 /* 4428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
1937 /* 4431 */ GIR_RootConstrainSelectedInstOperands,
1938 /* 4432 */ // GIR_Coverage, 3390,
1939 /* 4432 */ GIR_EraseRootFromParent_Done,
1940 /* 4433 */ // Label 230: @4433
1941 /* 4433 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(4511), // Rule ID 4963 //
1942 /* 4438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1943 /* 4441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1944 /* 4445 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1945 /* 4449 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1946 /* 4453 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1947 /* 4457 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1948 /* 4461 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1949 /* 4465 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1950 /* 4469 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1951 /* 4473 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1952 /* 4477 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
1953 /* 4481 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1954 /* 4487 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1955 /* 4489 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1956 /* 4491 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 9:{ *:[i32] })
1957 /* 4491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1958 /* 4494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1959 /* 4496 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
1960 /* 4498 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1961 /* 4502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
1962 /* 4506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
1963 /* 4509 */ GIR_RootConstrainSelectedInstOperands,
1964 /* 4510 */ // GIR_Coverage, 4963,
1965 /* 4510 */ GIR_EraseRootFromParent_Done,
1966 /* 4511 */ // Label 231: @4511
1967 /* 4511 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(4589), // Rule ID 3391 //
1968 /* 4516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1969 /* 4519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1970 /* 4523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1971 /* 4527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1972 /* 4531 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1973 /* 4535 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1974 /* 4539 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1975 /* 4543 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
1976 /* 4547 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1977 /* 4551 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1978 /* 4555 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1979 /* 4559 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
1980 /* 4565 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
1981 /* 4567 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1982 /* 4569 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 9:{ *:[i32] })
1983 /* 4569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
1984 /* 4572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
1985 /* 4574 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
1986 /* 4576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
1987 /* 4580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
1988 /* 4584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
1989 /* 4587 */ GIR_RootConstrainSelectedInstOperands,
1990 /* 4588 */ // GIR_Coverage, 3391,
1991 /* 4588 */ GIR_EraseRootFromParent_Done,
1992 /* 4589 */ // Label 232: @4589
1993 /* 4589 */ GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(4667), // Rule ID 4964 //
1994 /* 4594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
1995 /* 4597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
1996 /* 4601 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1997 /* 4605 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
1998 /* 4609 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1999 /* 4613 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2000 /* 4617 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2001 /* 4621 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
2002 /* 4625 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2003 /* 4629 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2004 /* 4633 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
2005 /* 4637 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2006 /* 4643 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
2007 /* 4645 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
2008 /* 4647 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] }))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 9:{ *:[i32] })
2009 /* 4647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2010 /* 4650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2011 /* 4652 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
2012 /* 4654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
2013 /* 4658 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
2014 /* 4662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
2015 /* 4665 */ GIR_RootConstrainSelectedInstOperands,
2016 /* 4666 */ // GIR_Coverage, 4964,
2017 /* 4666 */ GIR_EraseRootFromParent_Done,
2018 /* 4667 */ // Label 233: @4667
2019 /* 4667 */ GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(4722), // Rule ID 4939 //
2020 /* 4672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
2021 /* 4675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2022 /* 4679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2023 /* 4683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2024 /* 4687 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2025 /* 4691 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2026 /* 4695 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2027 /* 4699 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2028 /* 4705 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
2029 /* 4707 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2030 /* 4709 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XA) => (XXLANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
2031 /* 4709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLANDC),
2032 /* 4712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2033 /* 4714 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
2034 /* 4716 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB
2035 /* 4720 */ GIR_RootConstrainSelectedInstOperands,
2036 /* 4721 */ // GIR_Coverage, 4939,
2037 /* 4721 */ GIR_EraseRootFromParent_Done,
2038 /* 4722 */ // Label 234: @4722
2039 /* 4722 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(4777), // Rule ID 933 //
2040 /* 4727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
2041 /* 4730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2042 /* 4734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2043 /* 4738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2044 /* 4742 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2045 /* 4746 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2046 /* 4750 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2047 /* 4754 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2048 /* 4760 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
2049 /* 4762 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2050 /* 4764 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] })) => (XXLANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
2051 /* 4764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLANDC),
2052 /* 4767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2053 /* 4769 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
2054 /* 4771 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB
2055 /* 4775 */ GIR_RootConstrainSelectedInstOperands,
2056 /* 4776 */ // GIR_Coverage, 933,
2057 /* 4776 */ GIR_EraseRootFromParent_Done,
2058 /* 4777 */ // Label 235: @4777
2059 /* 4777 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(4827), // Rule ID 4959 //
2060 /* 4782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2061 /* 4785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2062 /* 4789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2063 /* 4793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2064 /* 4797 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2065 /* 4801 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2066 /* 4805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2067 /* 4807 */ // (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 1:{ *:[i32] })
2068 /* 4807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2069 /* 4810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2070 /* 4812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
2071 /* 4816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
2072 /* 4820 */ GIR_RootToRootCopy, /*OpIdx*/2, // vC
2073 /* 4822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2074 /* 4825 */ GIR_RootConstrainSelectedInstOperands,
2075 /* 4826 */ // GIR_Coverage, 4959,
2076 /* 4826 */ GIR_EraseRootFromParent_Done,
2077 /* 4827 */ // Label 236: @4827
2078 /* 4827 */ GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(4877), // Rule ID 4961 //
2079 /* 4832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2080 /* 4835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2081 /* 4839 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2082 /* 4843 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2083 /* 4847 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2084 /* 4851 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2085 /* 4855 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2086 /* 4857 */ // (and:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 7:{ *:[i32] })
2087 /* 4857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2088 /* 4860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2089 /* 4862 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
2090 /* 4864 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
2091 /* 4868 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2092 /* 4872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
2093 /* 4875 */ GIR_RootConstrainSelectedInstOperands,
2094 /* 4876 */ // GIR_Coverage, 4961,
2095 /* 4876 */ GIR_EraseRootFromParent_Done,
2096 /* 4877 */ // Label 237: @4877
2097 /* 4877 */ GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(4927), // Rule ID 4960 //
2098 /* 4882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2099 /* 4885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2100 /* 4889 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2101 /* 4893 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2102 /* 4897 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2103 /* 4901 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2104 /* 4905 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2105 /* 4907 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 6:{ *:[i32] })
2106 /* 4907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2107 /* 4910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2108 /* 4912 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
2109 /* 4914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
2110 /* 4918 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2111 /* 4922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/6,
2112 /* 4925 */ GIR_RootConstrainSelectedInstOperands,
2113 /* 4926 */ // GIR_Coverage, 4960,
2114 /* 4926 */ GIR_EraseRootFromParent_Done,
2115 /* 4927 */ // Label 238: @4927
2116 /* 4927 */ GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(4977), // Rule ID 3387 //
2117 /* 4932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2118 /* 4935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2119 /* 4939 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2120 /* 4943 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2121 /* 4947 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2122 /* 4951 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2123 /* 4955 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2124 /* 4957 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 1:{ *:[i32] })
2125 /* 4957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2126 /* 4960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2127 /* 4962 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
2128 /* 4964 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
2129 /* 4968 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2130 /* 4972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2131 /* 4975 */ GIR_RootConstrainSelectedInstOperands,
2132 /* 4976 */ // GIR_Coverage, 3387,
2133 /* 4976 */ GIR_EraseRootFromParent_Done,
2134 /* 4977 */ // Label 239: @4977
2135 /* 4977 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(5027), // Rule ID 3389 //
2136 /* 4982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2137 /* 4985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2138 /* 4989 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2139 /* 4993 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2140 /* 4997 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2141 /* 5001 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2142 /* 5005 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2143 /* 5007 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 7:{ *:[i32] })
2144 /* 5007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2145 /* 5010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2146 /* 5012 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
2147 /* 5014 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
2148 /* 5018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2149 /* 5022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
2150 /* 5025 */ GIR_RootConstrainSelectedInstOperands,
2151 /* 5026 */ // GIR_Coverage, 3389,
2152 /* 5026 */ GIR_EraseRootFromParent_Done,
2153 /* 5027 */ // Label 240: @5027
2154 /* 5027 */ GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(5077), // Rule ID 3388 //
2155 /* 5032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2156 /* 5035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2157 /* 5039 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2158 /* 5043 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2159 /* 5047 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2160 /* 5051 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2161 /* 5055 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2162 /* 5057 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 6:{ *:[i32] })
2163 /* 5057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2164 /* 5060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2165 /* 5062 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
2166 /* 5064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
2167 /* 5068 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2168 /* 5072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/6,
2169 /* 5075 */ GIR_RootConstrainSelectedInstOperands,
2170 /* 5076 */ // GIR_Coverage, 3388,
2171 /* 5076 */ GIR_EraseRootFromParent_Done,
2172 /* 5077 */ // Label 241: @5077
2173 /* 5077 */ GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(5096), // Rule ID 932 //
2174 /* 5082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
2175 /* 5085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2176 /* 5089 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
2177 /* 5089 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLAND),
2178 /* 5094 */ GIR_RootConstrainSelectedInstOperands,
2179 /* 5095 */ // GIR_Coverage, 932,
2180 /* 5095 */ GIR_Done,
2181 /* 5096 */ // Label 242: @5096
2182 /* 5096 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(5151), // Rule ID 4927 //
2183 /* 5101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
2184 /* 5104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
2185 /* 5108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2186 /* 5112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2187 /* 5116 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2188 /* 5120 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2189 /* 5124 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2190 /* 5128 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2191 /* 5134 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
2192 /* 5136 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2193 /* 5138 */ // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VA) => (VANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
2194 /* 5138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VANDC),
2195 /* 5141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
2196 /* 5143 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
2197 /* 5145 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB
2198 /* 5149 */ GIR_RootConstrainSelectedInstOperands,
2199 /* 5150 */ // GIR_Coverage, 4927,
2200 /* 5150 */ GIR_EraseRootFromParent_Done,
2201 /* 5151 */ // Label 243: @5151
2202 /* 5151 */ GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(5206), // Rule ID 312 //
2203 /* 5156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
2204 /* 5159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
2205 /* 5163 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2206 /* 5167 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2207 /* 5171 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2208 /* 5175 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2209 /* 5179 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2210 /* 5183 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2211 /* 5189 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
2212 /* 5191 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2213 /* 5193 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] })) => (VANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
2214 /* 5193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VANDC),
2215 /* 5196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
2216 /* 5198 */ GIR_RootToRootCopy, /*OpIdx*/1, // VA
2217 /* 5200 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB
2218 /* 5204 */ GIR_RootConstrainSelectedInstOperands,
2219 /* 5205 */ // GIR_Coverage, 312,
2220 /* 5205 */ GIR_EraseRootFromParent_Done,
2221 /* 5206 */ // Label 244: @5206
2222 /* 5206 */ GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(5261), // Rule ID 1384 //
2223 /* 5211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
2224 /* 5214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
2225 /* 5218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2226 /* 5222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2227 /* 5226 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2228 /* 5230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2229 /* 5234 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2230 /* 5238 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2231 /* 5244 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
2232 /* 5246 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2233 /* 5248 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$B, immAllOnesV:{ *:[v4i32] })) => (VANDC:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B)
2234 /* 5248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VANDC),
2235 /* 5251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
2236 /* 5253 */ GIR_RootToRootCopy, /*OpIdx*/1, // A
2237 /* 5255 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // B
2238 /* 5259 */ GIR_RootConstrainSelectedInstOperands,
2239 /* 5260 */ // GIR_Coverage, 1384,
2240 /* 5260 */ GIR_EraseRootFromParent_Done,
2241 /* 5261 */ // Label 245: @5261
2242 /* 5261 */ GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(5280), // Rule ID 311 //
2243 /* 5266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
2244 /* 5269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
2245 /* 5273 */ // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
2246 /* 5273 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VAND),
2247 /* 5278 */ GIR_RootConstrainSelectedInstOperands,
2248 /* 5279 */ // GIR_Coverage, 311,
2249 /* 5279 */ GIR_Done,
2250 /* 5280 */ // Label 246: @5280
2251 /* 5280 */ GIM_Reject,
2252 /* 5281 */ // Label 213: @5281
2253 /* 5281 */ GIM_Reject,
2254 /* 5282 */ // Label 200: @5282
2255 /* 5282 */ GIM_Reject,
2256 /* 5283 */ // Label 8: @5283
2257 /* 5283 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 251*/ GIMT_Encode4(48424),
2258 /* 5294 */ /*GILLT_s1*//*Label 247*/ GIMT_Encode4(5318),
2259 /* 5298 */ /*GILLT_s32*//*Label 248*/ GIMT_Encode4(5427),
2260 /* 5302 */ /*GILLT_s64*//*Label 249*/ GIMT_Encode4(5536), GIMT_Encode4(0), GIMT_Encode4(0),
2261 /* 5314 */ /*GILLT_v4s32*//*Label 250*/ GIMT_Encode4(5645),
2262 /* 5318 */ // Label 247: @5318
2263 /* 5318 */ GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(5426),
2264 /* 5323 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
2265 /* 5326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
2266 /* 5329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
2267 /* 5333 */ GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(5373), // Rule ID 4925 //
2268 /* 5338 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2269 /* 5342 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2270 /* 5346 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
2271 /* 5350 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
2272 /* 5354 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
2273 /* 5358 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2274 /* 5360 */ // (or:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRA) => (CRORC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
2275 /* 5360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC),
2276 /* 5363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
2277 /* 5365 */ GIR_RootToRootCopy, /*OpIdx*/2, // CRA
2278 /* 5367 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB
2279 /* 5371 */ GIR_RootConstrainSelectedInstOperands,
2280 /* 5372 */ // GIR_Coverage, 4925,
2281 /* 5372 */ GIR_EraseRootFromParent_Done,
2282 /* 5373 */ // Label 253: @5373
2283 /* 5373 */ GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(5413), // Rule ID 183 //
2284 /* 5378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2285 /* 5382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2286 /* 5386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
2287 /* 5390 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
2288 /* 5394 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
2289 /* 5398 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2290 /* 5400 */ // (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] })) => (CRORC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
2291 /* 5400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC),
2292 /* 5403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
2293 /* 5405 */ GIR_RootToRootCopy, /*OpIdx*/1, // CRA
2294 /* 5407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB
2295 /* 5411 */ GIR_RootConstrainSelectedInstOperands,
2296 /* 5412 */ // GIR_Coverage, 183,
2297 /* 5412 */ GIR_EraseRootFromParent_Done,
2298 /* 5413 */ // Label 254: @5413
2299 /* 5413 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(5425), // Rule ID 177 //
2300 /* 5418 */ // (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CROR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
2301 /* 5418 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CROR),
2302 /* 5423 */ GIR_RootConstrainSelectedInstOperands,
2303 /* 5424 */ // GIR_Coverage, 177,
2304 /* 5424 */ GIR_Done,
2305 /* 5425 */ // Label 255: @5425
2306 /* 5425 */ GIM_Reject,
2307 /* 5426 */ // Label 252: @5426
2308 /* 5426 */ GIM_Reject,
2309 /* 5427 */ // Label 248: @5427
2310 /* 5427 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(5535),
2311 /* 5432 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2312 /* 5435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2313 /* 5438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
2314 /* 5442 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(5482), // Rule ID 4919 //
2315 /* 5447 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2316 /* 5451 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2317 /* 5455 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2318 /* 5459 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2319 /* 5463 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
2320 /* 5467 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2321 /* 5469 */ // (or:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] }), i32:{ *:[i32] }:$RST) => (ORC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
2322 /* 5469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC),
2323 /* 5472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
2324 /* 5474 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
2325 /* 5476 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
2326 /* 5480 */ GIR_RootConstrainSelectedInstOperands,
2327 /* 5481 */ // GIR_Coverage, 4919,
2328 /* 5481 */ GIR_EraseRootFromParent_Done,
2329 /* 5482 */ // Label 257: @5482
2330 /* 5482 */ GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(5522), // Rule ID 126 //
2331 /* 5487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2332 /* 5491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2333 /* 5495 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2334 /* 5499 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2335 /* 5503 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
2336 /* 5507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2337 /* 5509 */ // (or:{ *:[i32] } i32:{ *:[i32] }:$RST, (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] })) => (ORC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
2338 /* 5509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC),
2339 /* 5512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
2340 /* 5514 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
2341 /* 5516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
2342 /* 5520 */ GIR_RootConstrainSelectedInstOperands,
2343 /* 5521 */ // GIR_Coverage, 126,
2344 /* 5521 */ GIR_EraseRootFromParent_Done,
2345 /* 5522 */ // Label 258: @5522
2346 /* 5522 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(5534), // Rule ID 124 //
2347 /* 5527 */ // (or:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (OR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
2348 /* 5527 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::OR),
2349 /* 5532 */ GIR_RootConstrainSelectedInstOperands,
2350 /* 5533 */ // GIR_Coverage, 124,
2351 /* 5533 */ GIR_Done,
2352 /* 5534 */ // Label 259: @5534
2353 /* 5534 */ GIM_Reject,
2354 /* 5535 */ // Label 256: @5535
2355 /* 5535 */ GIM_Reject,
2356 /* 5536 */ // Label 249: @5536
2357 /* 5536 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(5644),
2358 /* 5541 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2359 /* 5544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2360 /* 5547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
2361 /* 5551 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(5591), // Rule ID 4932 //
2362 /* 5556 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2363 /* 5560 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2364 /* 5564 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2365 /* 5568 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2366 /* 5572 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
2367 /* 5576 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2368 /* 5578 */ // (or:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] }), i64:{ *:[i64] }:$RST) => (ORC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
2369 /* 5578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC8),
2370 /* 5581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
2371 /* 5583 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
2372 /* 5585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
2373 /* 5589 */ GIR_RootConstrainSelectedInstOperands,
2374 /* 5590 */ // GIR_Coverage, 4932,
2375 /* 5590 */ GIR_EraseRootFromParent_Done,
2376 /* 5591 */ // Label 261: @5591
2377 /* 5591 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(5631), // Rule ID 650 //
2378 /* 5596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2379 /* 5600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
2380 /* 5604 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2381 /* 5608 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2382 /* 5612 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
2383 /* 5616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2384 /* 5618 */ // (or:{ *:[i64] } i64:{ *:[i64] }:$RST, (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] })) => (ORC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
2385 /* 5618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC8),
2386 /* 5621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
2387 /* 5623 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
2388 /* 5625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
2389 /* 5629 */ GIR_RootConstrainSelectedInstOperands,
2390 /* 5630 */ // GIR_Coverage, 650,
2391 /* 5630 */ GIR_EraseRootFromParent_Done,
2392 /* 5631 */ // Label 262: @5631
2393 /* 5631 */ GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(5643), // Rule ID 648 //
2394 /* 5636 */ // (or:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (OR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
2395 /* 5636 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::OR8),
2396 /* 5641 */ GIR_RootConstrainSelectedInstOperands,
2397 /* 5642 */ // GIR_Coverage, 648,
2398 /* 5642 */ GIR_Done,
2399 /* 5643 */ // Label 263: @5643
2400 /* 5643 */ GIM_Reject,
2401 /* 5644 */ // Label 260: @5644
2402 /* 5644 */ GIM_Reject,
2403 /* 5645 */ // Label 250: @5645
2404 /* 5645 */ GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(48423),
2405 /* 5650 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2406 /* 5653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2407 /* 5656 */ GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(5794), // Rule ID 4979 //
2408 /* 5661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2409 /* 5664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2410 /* 5668 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2411 /* 5672 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2412 /* 5676 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2413 /* 5680 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2414 /* 5684 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2415 /* 5688 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2416 /* 5692 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2417 /* 5696 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2418 /* 5700 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2419 /* 5704 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2420 /* 5708 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2421 /* 5712 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2422 /* 5716 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2423 /* 5720 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2424 /* 5724 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2425 /* 5728 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2426 /* 5732 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2427 /* 5736 */ // MIs[5] vA
2428 /* 5736 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
2429 /* 5741 */ // MIs[5] vB
2430 /* 5741 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2431 /* 5746 */ // MIs[4] vC
2432 /* 5746 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2433 /* 5751 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2434 /* 5755 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2435 /* 5761 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2436 /* 5763 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2437 /* 5765 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2438 /* 5765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2439 /* 5768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2440 /* 5770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
2441 /* 5774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
2442 /* 5778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2443 /* 5782 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2444 /* 5792 */ GIR_RootConstrainSelectedInstOperands,
2445 /* 5793 */ // GIR_Coverage, 4979,
2446 /* 5793 */ GIR_EraseRootFromParent_Done,
2447 /* 5794 */ // Label 265: @5794
2448 /* 5794 */ GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(5932), // Rule ID 4980 //
2449 /* 5799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2450 /* 5802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2451 /* 5806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2452 /* 5810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2453 /* 5814 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2454 /* 5818 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2455 /* 5822 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2456 /* 5826 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2457 /* 5830 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2458 /* 5834 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2459 /* 5838 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2460 /* 5842 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2461 /* 5846 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2462 /* 5850 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2463 /* 5854 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2464 /* 5858 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2465 /* 5862 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2466 /* 5866 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2467 /* 5870 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2468 /* 5874 */ // MIs[5] vB
2469 /* 5874 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
2470 /* 5879 */ // MIs[5] vA
2471 /* 5879 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2472 /* 5884 */ // MIs[4] vC
2473 /* 5884 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2474 /* 5889 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2475 /* 5893 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2476 /* 5899 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2477 /* 5901 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2478 /* 5903 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2479 /* 5903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2480 /* 5906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2481 /* 5908 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
2482 /* 5912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
2483 /* 5916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2484 /* 5920 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2485 /* 5930 */ GIR_RootConstrainSelectedInstOperands,
2486 /* 5931 */ // GIR_Coverage, 4980,
2487 /* 5931 */ GIR_EraseRootFromParent_Done,
2488 /* 5932 */ // Label 266: @5932
2489 /* 5932 */ GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(6070), // Rule ID 4981 //
2490 /* 5937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2491 /* 5940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2492 /* 5944 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2493 /* 5948 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2494 /* 5952 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2495 /* 5956 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2496 /* 5960 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2497 /* 5964 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2498 /* 5968 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2499 /* 5972 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2500 /* 5976 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2501 /* 5980 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2502 /* 5984 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2503 /* 5988 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2504 /* 5992 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2505 /* 5996 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2506 /* 6000 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2507 /* 6004 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2508 /* 6008 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2509 /* 6012 */ // MIs[5] vA
2510 /* 6012 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
2511 /* 6017 */ // MIs[5] vC
2512 /* 6017 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2513 /* 6022 */ // MIs[4] vB
2514 /* 6022 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2515 /* 6027 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2516 /* 6031 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2517 /* 6037 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2518 /* 6039 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2519 /* 6041 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2520 /* 6041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2521 /* 6044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2522 /* 6046 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
2523 /* 6050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
2524 /* 6054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2525 /* 6058 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2526 /* 6068 */ GIR_RootConstrainSelectedInstOperands,
2527 /* 6069 */ // GIR_Coverage, 4981,
2528 /* 6069 */ GIR_EraseRootFromParent_Done,
2529 /* 6070 */ // Label 267: @6070
2530 /* 6070 */ GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(6208), // Rule ID 4982 //
2531 /* 6075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2532 /* 6078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2533 /* 6082 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2534 /* 6086 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2535 /* 6090 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2536 /* 6094 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2537 /* 6098 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2538 /* 6102 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2539 /* 6106 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2540 /* 6110 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2541 /* 6114 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2542 /* 6118 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2543 /* 6122 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2544 /* 6126 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2545 /* 6130 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2546 /* 6134 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2547 /* 6138 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2548 /* 6142 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2549 /* 6146 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2550 /* 6150 */ // MIs[5] vC
2551 /* 6150 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
2552 /* 6155 */ // MIs[5] vA
2553 /* 6155 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2554 /* 6160 */ // MIs[4] vB
2555 /* 6160 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2556 /* 6165 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2557 /* 6169 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2558 /* 6175 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2559 /* 6177 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2560 /* 6179 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2561 /* 6179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2562 /* 6182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2563 /* 6184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
2564 /* 6188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
2565 /* 6192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2566 /* 6196 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2567 /* 6206 */ GIR_RootConstrainSelectedInstOperands,
2568 /* 6207 */ // GIR_Coverage, 4982,
2569 /* 6207 */ GIR_EraseRootFromParent_Done,
2570 /* 6208 */ // Label 268: @6208
2571 /* 6208 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(6346), // Rule ID 4983 //
2572 /* 6213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2573 /* 6216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2574 /* 6220 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2575 /* 6224 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2576 /* 6228 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2577 /* 6232 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2578 /* 6236 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2579 /* 6240 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2580 /* 6244 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2581 /* 6248 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2582 /* 6252 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2583 /* 6256 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2584 /* 6260 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2585 /* 6264 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2586 /* 6268 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2587 /* 6272 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2588 /* 6276 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2589 /* 6280 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2590 /* 6284 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2591 /* 6288 */ // MIs[5] vB
2592 /* 6288 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
2593 /* 6293 */ // MIs[5] vC
2594 /* 6293 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2595 /* 6298 */ // MIs[4] vA
2596 /* 6298 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2597 /* 6303 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2598 /* 6307 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2599 /* 6313 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2600 /* 6315 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2601 /* 6317 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2602 /* 6317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2603 /* 6320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2604 /* 6322 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
2605 /* 6326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
2606 /* 6330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2607 /* 6334 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2608 /* 6344 */ GIR_RootConstrainSelectedInstOperands,
2609 /* 6345 */ // GIR_Coverage, 4983,
2610 /* 6345 */ GIR_EraseRootFromParent_Done,
2611 /* 6346 */ // Label 269: @6346
2612 /* 6346 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(6484), // Rule ID 4984 //
2613 /* 6351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2614 /* 6354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2615 /* 6358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2616 /* 6362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2617 /* 6366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2618 /* 6370 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2619 /* 6374 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2620 /* 6378 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2621 /* 6382 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2622 /* 6386 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2623 /* 6390 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2624 /* 6394 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2625 /* 6398 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2626 /* 6402 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2627 /* 6406 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2628 /* 6410 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2629 /* 6414 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2630 /* 6418 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2631 /* 6422 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2632 /* 6426 */ // MIs[5] vC
2633 /* 6426 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
2634 /* 6431 */ // MIs[5] vB
2635 /* 6431 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2636 /* 6436 */ // MIs[4] vA
2637 /* 6436 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2638 /* 6441 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2639 /* 6445 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2640 /* 6451 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2641 /* 6453 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2642 /* 6455 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2643 /* 6455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2644 /* 6458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2645 /* 6460 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
2646 /* 6464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
2647 /* 6468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2648 /* 6472 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2649 /* 6482 */ GIR_RootConstrainSelectedInstOperands,
2650 /* 6483 */ // GIR_Coverage, 4984,
2651 /* 6483 */ GIR_EraseRootFromParent_Done,
2652 /* 6484 */ // Label 270: @6484
2653 /* 6484 */ GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(6622), // Rule ID 4991 //
2654 /* 6489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2655 /* 6492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2656 /* 6496 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2657 /* 6500 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2658 /* 6504 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2659 /* 6508 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2660 /* 6512 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2661 /* 6516 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2662 /* 6520 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2663 /* 6524 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2664 /* 6528 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2665 /* 6532 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2666 /* 6536 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2667 /* 6540 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2668 /* 6544 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2669 /* 6548 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2670 /* 6552 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2671 /* 6556 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2672 /* 6560 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2673 /* 6564 */ // MIs[5] vA
2674 /* 6564 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
2675 /* 6569 */ // MIs[5] vB
2676 /* 6569 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2677 /* 6574 */ // MIs[4] vC
2678 /* 6574 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2679 /* 6579 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2680 /* 6583 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2681 /* 6589 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2682 /* 6591 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2683 /* 6593 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2684 /* 6593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2685 /* 6596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2686 /* 6598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
2687 /* 6602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
2688 /* 6606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2689 /* 6610 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2690 /* 6620 */ GIR_RootConstrainSelectedInstOperands,
2691 /* 6621 */ // GIR_Coverage, 4991,
2692 /* 6621 */ GIR_EraseRootFromParent_Done,
2693 /* 6622 */ // Label 271: @6622
2694 /* 6622 */ GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(6760), // Rule ID 4992 //
2695 /* 6627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2696 /* 6630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2697 /* 6634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2698 /* 6638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2699 /* 6642 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2700 /* 6646 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2701 /* 6650 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2702 /* 6654 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2703 /* 6658 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2704 /* 6662 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2705 /* 6666 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2706 /* 6670 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2707 /* 6674 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2708 /* 6678 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2709 /* 6682 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2710 /* 6686 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2711 /* 6690 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2712 /* 6694 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2713 /* 6698 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2714 /* 6702 */ // MIs[5] vB
2715 /* 6702 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
2716 /* 6707 */ // MIs[5] vA
2717 /* 6707 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2718 /* 6712 */ // MIs[4] vC
2719 /* 6712 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2720 /* 6717 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2721 /* 6721 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2722 /* 6727 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2723 /* 6729 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2724 /* 6731 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2725 /* 6731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2726 /* 6734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2727 /* 6736 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
2728 /* 6740 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
2729 /* 6744 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2730 /* 6748 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2731 /* 6758 */ GIR_RootConstrainSelectedInstOperands,
2732 /* 6759 */ // GIR_Coverage, 4992,
2733 /* 6759 */ GIR_EraseRootFromParent_Done,
2734 /* 6760 */ // Label 272: @6760
2735 /* 6760 */ GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(6898), // Rule ID 4993 //
2736 /* 6765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2737 /* 6768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2738 /* 6772 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2739 /* 6776 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2740 /* 6780 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2741 /* 6784 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2742 /* 6788 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2743 /* 6792 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2744 /* 6796 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2745 /* 6800 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2746 /* 6804 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2747 /* 6808 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2748 /* 6812 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2749 /* 6816 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2750 /* 6820 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2751 /* 6824 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2752 /* 6828 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2753 /* 6832 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2754 /* 6836 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2755 /* 6840 */ // MIs[5] vA
2756 /* 6840 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
2757 /* 6845 */ // MIs[5] vC
2758 /* 6845 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2759 /* 6850 */ // MIs[4] vB
2760 /* 6850 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2761 /* 6855 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2762 /* 6859 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2763 /* 6865 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2764 /* 6867 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2765 /* 6869 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2766 /* 6869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2767 /* 6872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2768 /* 6874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
2769 /* 6878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
2770 /* 6882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2771 /* 6886 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2772 /* 6896 */ GIR_RootConstrainSelectedInstOperands,
2773 /* 6897 */ // GIR_Coverage, 4993,
2774 /* 6897 */ GIR_EraseRootFromParent_Done,
2775 /* 6898 */ // Label 273: @6898
2776 /* 6898 */ GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(7036), // Rule ID 4994 //
2777 /* 6903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2778 /* 6906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2779 /* 6910 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2780 /* 6914 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2781 /* 6918 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2782 /* 6922 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2783 /* 6926 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2784 /* 6930 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2785 /* 6934 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2786 /* 6938 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2787 /* 6942 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2788 /* 6946 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2789 /* 6950 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2790 /* 6954 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2791 /* 6958 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2792 /* 6962 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2793 /* 6966 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2794 /* 6970 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2795 /* 6974 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2796 /* 6978 */ // MIs[5] vC
2797 /* 6978 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
2798 /* 6983 */ // MIs[5] vA
2799 /* 6983 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2800 /* 6988 */ // MIs[4] vB
2801 /* 6988 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2802 /* 6993 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2803 /* 6997 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2804 /* 7003 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2805 /* 7005 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2806 /* 7007 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2807 /* 7007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2808 /* 7010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2809 /* 7012 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
2810 /* 7016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
2811 /* 7020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2812 /* 7024 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2813 /* 7034 */ GIR_RootConstrainSelectedInstOperands,
2814 /* 7035 */ // GIR_Coverage, 4994,
2815 /* 7035 */ GIR_EraseRootFromParent_Done,
2816 /* 7036 */ // Label 274: @7036
2817 /* 7036 */ GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(7174), // Rule ID 4995 //
2818 /* 7041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2819 /* 7044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2820 /* 7048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2821 /* 7052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2822 /* 7056 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2823 /* 7060 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2824 /* 7064 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2825 /* 7068 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2826 /* 7072 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2827 /* 7076 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2828 /* 7080 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2829 /* 7084 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2830 /* 7088 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2831 /* 7092 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2832 /* 7096 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2833 /* 7100 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2834 /* 7104 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2835 /* 7108 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2836 /* 7112 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2837 /* 7116 */ // MIs[5] vB
2838 /* 7116 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
2839 /* 7121 */ // MIs[5] vC
2840 /* 7121 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2841 /* 7126 */ // MIs[4] vA
2842 /* 7126 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2843 /* 7131 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2844 /* 7135 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2845 /* 7141 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2846 /* 7143 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2847 /* 7145 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2848 /* 7145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2849 /* 7148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2850 /* 7150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
2851 /* 7154 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
2852 /* 7158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2853 /* 7162 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2854 /* 7172 */ GIR_RootConstrainSelectedInstOperands,
2855 /* 7173 */ // GIR_Coverage, 4995,
2856 /* 7173 */ GIR_EraseRootFromParent_Done,
2857 /* 7174 */ // Label 275: @7174
2858 /* 7174 */ GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(7312), // Rule ID 4996 //
2859 /* 7179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2860 /* 7182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2861 /* 7186 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2862 /* 7190 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2863 /* 7194 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2864 /* 7198 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2865 /* 7202 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2866 /* 7206 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2867 /* 7210 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2868 /* 7214 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2869 /* 7218 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2870 /* 7222 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2871 /* 7226 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2872 /* 7230 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2873 /* 7234 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2874 /* 7238 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2875 /* 7242 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2876 /* 7246 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2877 /* 7250 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2878 /* 7254 */ // MIs[5] vC
2879 /* 7254 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
2880 /* 7259 */ // MIs[5] vB
2881 /* 7259 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2882 /* 7264 */ // MIs[4] vA
2883 /* 7264 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2884 /* 7269 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2885 /* 7273 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2886 /* 7279 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2887 /* 7281 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2888 /* 7283 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2889 /* 7283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2890 /* 7286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2891 /* 7288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
2892 /* 7292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
2893 /* 7296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
2894 /* 7300 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2895 /* 7310 */ GIR_RootConstrainSelectedInstOperands,
2896 /* 7311 */ // GIR_Coverage, 4996,
2897 /* 7311 */ GIR_EraseRootFromParent_Done,
2898 /* 7312 */ // Label 276: @7312
2899 /* 7312 */ GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(7450), // Rule ID 5003 //
2900 /* 7317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2901 /* 7320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2902 /* 7324 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2903 /* 7328 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2904 /* 7332 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2905 /* 7336 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2906 /* 7340 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2907 /* 7344 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2908 /* 7348 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2909 /* 7352 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2910 /* 7356 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2911 /* 7360 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2912 /* 7364 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2913 /* 7368 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2914 /* 7372 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2915 /* 7376 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2916 /* 7380 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2917 /* 7384 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2918 /* 7388 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2919 /* 7392 */ // MIs[5] vA
2920 /* 7392 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
2921 /* 7397 */ // MIs[5] vB
2922 /* 7397 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
2923 /* 7402 */ // MIs[4] vC
2924 /* 7402 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2925 /* 7407 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2926 /* 7411 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2927 /* 7417 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2928 /* 7419 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2929 /* 7421 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2930 /* 7421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2931 /* 7424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2932 /* 7426 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
2933 /* 7430 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
2934 /* 7434 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
2935 /* 7438 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2936 /* 7448 */ GIR_RootConstrainSelectedInstOperands,
2937 /* 7449 */ // GIR_Coverage, 5003,
2938 /* 7449 */ GIR_EraseRootFromParent_Done,
2939 /* 7450 */ // Label 277: @7450
2940 /* 7450 */ GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(7588), // Rule ID 5004 //
2941 /* 7455 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2942 /* 7458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2943 /* 7462 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2944 /* 7466 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2945 /* 7470 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2946 /* 7474 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2947 /* 7478 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2948 /* 7482 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2949 /* 7486 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2950 /* 7490 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2951 /* 7494 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2952 /* 7498 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2953 /* 7502 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2954 /* 7506 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2955 /* 7510 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2956 /* 7514 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2957 /* 7518 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2958 /* 7522 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
2959 /* 7526 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
2960 /* 7530 */ // MIs[5] vB
2961 /* 7530 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
2962 /* 7535 */ // MIs[5] vA
2963 /* 7535 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
2964 /* 7540 */ // MIs[4] vC
2965 /* 7540 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
2966 /* 7545 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
2967 /* 7549 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
2968 /* 7555 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
2969 /* 7557 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
2970 /* 7559 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
2971 /* 7559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
2972 /* 7562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
2973 /* 7564 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
2974 /* 7568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
2975 /* 7572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
2976 /* 7576 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
2977 /* 7586 */ GIR_RootConstrainSelectedInstOperands,
2978 /* 7587 */ // GIR_Coverage, 5004,
2979 /* 7587 */ GIR_EraseRootFromParent_Done,
2980 /* 7588 */ // Label 278: @7588
2981 /* 7588 */ GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(7726), // Rule ID 5005 //
2982 /* 7593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
2983 /* 7596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
2984 /* 7600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2985 /* 7604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
2986 /* 7608 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2987 /* 7612 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2988 /* 7616 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2989 /* 7620 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
2990 /* 7624 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2991 /* 7628 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2992 /* 7632 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
2993 /* 7636 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
2994 /* 7640 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
2995 /* 7644 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
2996 /* 7648 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
2997 /* 7652 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
2998 /* 7656 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
2999 /* 7660 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3000 /* 7664 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3001 /* 7668 */ // MIs[5] vA
3002 /* 7668 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3003 /* 7673 */ // MIs[5] vC
3004 /* 7673 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3005 /* 7678 */ // MIs[4] vB
3006 /* 7678 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3007 /* 7683 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3008 /* 7687 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3009 /* 7693 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3010 /* 7695 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3011 /* 7697 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3012 /* 7697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3013 /* 7700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3014 /* 7702 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
3015 /* 7706 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3016 /* 7710 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3017 /* 7714 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3018 /* 7724 */ GIR_RootConstrainSelectedInstOperands,
3019 /* 7725 */ // GIR_Coverage, 5005,
3020 /* 7725 */ GIR_EraseRootFromParent_Done,
3021 /* 7726 */ // Label 279: @7726
3022 /* 7726 */ GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(7864), // Rule ID 5006 //
3023 /* 7731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3024 /* 7734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3025 /* 7738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3026 /* 7742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3027 /* 7746 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3028 /* 7750 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3029 /* 7754 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3030 /* 7758 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3031 /* 7762 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3032 /* 7766 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3033 /* 7770 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3034 /* 7774 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3035 /* 7778 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3036 /* 7782 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3037 /* 7786 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3038 /* 7790 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3039 /* 7794 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3040 /* 7798 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3041 /* 7802 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3042 /* 7806 */ // MIs[5] vC
3043 /* 7806 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3044 /* 7811 */ // MIs[5] vA
3045 /* 7811 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3046 /* 7816 */ // MIs[4] vB
3047 /* 7816 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3048 /* 7821 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3049 /* 7825 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3050 /* 7831 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3051 /* 7833 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3052 /* 7835 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3053 /* 7835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3054 /* 7838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3055 /* 7840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
3056 /* 7844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3057 /* 7848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3058 /* 7852 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3059 /* 7862 */ GIR_RootConstrainSelectedInstOperands,
3060 /* 7863 */ // GIR_Coverage, 5006,
3061 /* 7863 */ GIR_EraseRootFromParent_Done,
3062 /* 7864 */ // Label 280: @7864
3063 /* 7864 */ GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(8002), // Rule ID 5007 //
3064 /* 7869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3065 /* 7872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3066 /* 7876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3067 /* 7880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3068 /* 7884 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3069 /* 7888 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3070 /* 7892 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3071 /* 7896 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3072 /* 7900 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3073 /* 7904 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3074 /* 7908 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3075 /* 7912 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3076 /* 7916 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3077 /* 7920 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3078 /* 7924 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3079 /* 7928 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3080 /* 7932 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3081 /* 7936 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3082 /* 7940 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3083 /* 7944 */ // MIs[5] vB
3084 /* 7944 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3085 /* 7949 */ // MIs[5] vC
3086 /* 7949 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3087 /* 7954 */ // MIs[4] vA
3088 /* 7954 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3089 /* 7959 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3090 /* 7963 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3091 /* 7969 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3092 /* 7971 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3093 /* 7973 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3094 /* 7973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3095 /* 7976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3096 /* 7978 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
3097 /* 7982 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3098 /* 7986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3099 /* 7990 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3100 /* 8000 */ GIR_RootConstrainSelectedInstOperands,
3101 /* 8001 */ // GIR_Coverage, 5007,
3102 /* 8001 */ GIR_EraseRootFromParent_Done,
3103 /* 8002 */ // Label 281: @8002
3104 /* 8002 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(8140), // Rule ID 5008 //
3105 /* 8007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3106 /* 8010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3107 /* 8014 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3108 /* 8018 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3109 /* 8022 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3110 /* 8026 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3111 /* 8030 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3112 /* 8034 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3113 /* 8038 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3114 /* 8042 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3115 /* 8046 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3116 /* 8050 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3117 /* 8054 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3118 /* 8058 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3119 /* 8062 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3120 /* 8066 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3121 /* 8070 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3122 /* 8074 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3123 /* 8078 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3124 /* 8082 */ // MIs[5] vC
3125 /* 8082 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3126 /* 8087 */ // MIs[5] vB
3127 /* 8087 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3128 /* 8092 */ // MIs[4] vA
3129 /* 8092 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3130 /* 8097 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3131 /* 8101 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3132 /* 8107 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3133 /* 8109 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3134 /* 8111 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3135 /* 8111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3136 /* 8114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3137 /* 8116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
3138 /* 8120 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3139 /* 8124 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3140 /* 8128 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3141 /* 8138 */ GIR_RootConstrainSelectedInstOperands,
3142 /* 8139 */ // GIR_Coverage, 5008,
3143 /* 8139 */ GIR_EraseRootFromParent_Done,
3144 /* 8140 */ // Label 282: @8140
3145 /* 8140 */ GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(8278), // Rule ID 5015 //
3146 /* 8145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3147 /* 8148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3148 /* 8152 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3149 /* 8156 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3150 /* 8160 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3151 /* 8164 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3152 /* 8168 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3153 /* 8172 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3154 /* 8176 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3155 /* 8180 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3156 /* 8184 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3157 /* 8188 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3158 /* 8192 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3159 /* 8196 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3160 /* 8200 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3161 /* 8204 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3162 /* 8208 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3163 /* 8212 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3164 /* 8216 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3165 /* 8220 */ // MIs[5] vA
3166 /* 8220 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3167 /* 8225 */ // MIs[5] vB
3168 /* 8225 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3169 /* 8230 */ // MIs[4] vC
3170 /* 8230 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3171 /* 8235 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3172 /* 8239 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3173 /* 8245 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3174 /* 8247 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3175 /* 8249 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3176 /* 8249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3177 /* 8252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3178 /* 8254 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
3179 /* 8258 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3180 /* 8262 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3181 /* 8266 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3182 /* 8276 */ GIR_RootConstrainSelectedInstOperands,
3183 /* 8277 */ // GIR_Coverage, 5015,
3184 /* 8277 */ GIR_EraseRootFromParent_Done,
3185 /* 8278 */ // Label 283: @8278
3186 /* 8278 */ GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(8416), // Rule ID 5016 //
3187 /* 8283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3188 /* 8286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3189 /* 8290 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3190 /* 8294 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3191 /* 8298 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3192 /* 8302 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3193 /* 8306 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3194 /* 8310 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3195 /* 8314 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3196 /* 8318 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3197 /* 8322 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3198 /* 8326 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3199 /* 8330 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3200 /* 8334 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3201 /* 8338 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3202 /* 8342 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3203 /* 8346 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3204 /* 8350 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3205 /* 8354 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3206 /* 8358 */ // MIs[5] vB
3207 /* 8358 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3208 /* 8363 */ // MIs[5] vA
3209 /* 8363 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3210 /* 8368 */ // MIs[4] vC
3211 /* 8368 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3212 /* 8373 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3213 /* 8377 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3214 /* 8383 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3215 /* 8385 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3216 /* 8387 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3217 /* 8387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3218 /* 8390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3219 /* 8392 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
3220 /* 8396 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3221 /* 8400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3222 /* 8404 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3223 /* 8414 */ GIR_RootConstrainSelectedInstOperands,
3224 /* 8415 */ // GIR_Coverage, 5016,
3225 /* 8415 */ GIR_EraseRootFromParent_Done,
3226 /* 8416 */ // Label 284: @8416
3227 /* 8416 */ GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(8554), // Rule ID 5017 //
3228 /* 8421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3229 /* 8424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3230 /* 8428 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3231 /* 8432 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3232 /* 8436 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3233 /* 8440 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3234 /* 8444 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3235 /* 8448 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3236 /* 8452 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3237 /* 8456 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3238 /* 8460 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3239 /* 8464 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3240 /* 8468 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3241 /* 8472 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3242 /* 8476 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3243 /* 8480 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3244 /* 8484 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3245 /* 8488 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3246 /* 8492 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3247 /* 8496 */ // MIs[5] vA
3248 /* 8496 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3249 /* 8501 */ // MIs[5] vC
3250 /* 8501 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3251 /* 8506 */ // MIs[4] vB
3252 /* 8506 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3253 /* 8511 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3254 /* 8515 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3255 /* 8521 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3256 /* 8523 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3257 /* 8525 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3258 /* 8525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3259 /* 8528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3260 /* 8530 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
3261 /* 8534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3262 /* 8538 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3263 /* 8542 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3264 /* 8552 */ GIR_RootConstrainSelectedInstOperands,
3265 /* 8553 */ // GIR_Coverage, 5017,
3266 /* 8553 */ GIR_EraseRootFromParent_Done,
3267 /* 8554 */ // Label 285: @8554
3268 /* 8554 */ GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(8692), // Rule ID 5018 //
3269 /* 8559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3270 /* 8562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3271 /* 8566 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3272 /* 8570 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3273 /* 8574 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3274 /* 8578 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3275 /* 8582 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3276 /* 8586 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3277 /* 8590 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3278 /* 8594 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3279 /* 8598 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3280 /* 8602 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3281 /* 8606 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3282 /* 8610 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3283 /* 8614 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3284 /* 8618 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3285 /* 8622 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3286 /* 8626 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3287 /* 8630 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3288 /* 8634 */ // MIs[5] vC
3289 /* 8634 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3290 /* 8639 */ // MIs[5] vA
3291 /* 8639 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3292 /* 8644 */ // MIs[4] vB
3293 /* 8644 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3294 /* 8649 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3295 /* 8653 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3296 /* 8659 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3297 /* 8661 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3298 /* 8663 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3299 /* 8663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3300 /* 8666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3301 /* 8668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
3302 /* 8672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3303 /* 8676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3304 /* 8680 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3305 /* 8690 */ GIR_RootConstrainSelectedInstOperands,
3306 /* 8691 */ // GIR_Coverage, 5018,
3307 /* 8691 */ GIR_EraseRootFromParent_Done,
3308 /* 8692 */ // Label 286: @8692
3309 /* 8692 */ GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(8830), // Rule ID 5019 //
3310 /* 8697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3311 /* 8700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3312 /* 8704 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3313 /* 8708 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3314 /* 8712 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3315 /* 8716 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3316 /* 8720 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3317 /* 8724 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3318 /* 8728 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3319 /* 8732 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3320 /* 8736 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3321 /* 8740 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3322 /* 8744 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3323 /* 8748 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3324 /* 8752 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3325 /* 8756 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3326 /* 8760 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3327 /* 8764 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3328 /* 8768 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3329 /* 8772 */ // MIs[5] vB
3330 /* 8772 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3331 /* 8777 */ // MIs[5] vC
3332 /* 8777 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3333 /* 8782 */ // MIs[4] vA
3334 /* 8782 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3335 /* 8787 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3336 /* 8791 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3337 /* 8797 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3338 /* 8799 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3339 /* 8801 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3340 /* 8801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3341 /* 8804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3342 /* 8806 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
3343 /* 8810 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3344 /* 8814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3345 /* 8818 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3346 /* 8828 */ GIR_RootConstrainSelectedInstOperands,
3347 /* 8829 */ // GIR_Coverage, 5019,
3348 /* 8829 */ GIR_EraseRootFromParent_Done,
3349 /* 8830 */ // Label 287: @8830
3350 /* 8830 */ GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(8968), // Rule ID 5020 //
3351 /* 8835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3352 /* 8838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3353 /* 8842 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3354 /* 8846 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3355 /* 8850 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3356 /* 8854 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3357 /* 8858 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3358 /* 8862 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3359 /* 8866 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3360 /* 8870 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3361 /* 8874 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3362 /* 8878 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3363 /* 8882 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3364 /* 8886 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3365 /* 8890 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3366 /* 8894 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3367 /* 8898 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3368 /* 8902 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3369 /* 8906 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3370 /* 8910 */ // MIs[5] vC
3371 /* 8910 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3372 /* 8915 */ // MIs[5] vB
3373 /* 8915 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3374 /* 8920 */ // MIs[4] vA
3375 /* 8920 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3376 /* 8925 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3377 /* 8929 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3378 /* 8935 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3379 /* 8937 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3380 /* 8939 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3381 /* 8939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3382 /* 8942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3383 /* 8944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
3384 /* 8948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
3385 /* 8952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3386 /* 8956 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3387 /* 8966 */ GIR_RootConstrainSelectedInstOperands,
3388 /* 8967 */ // GIR_Coverage, 5020,
3389 /* 8967 */ GIR_EraseRootFromParent_Done,
3390 /* 8968 */ // Label 288: @8968
3391 /* 8968 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(9106), // Rule ID 5027 //
3392 /* 8973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3393 /* 8976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3394 /* 8980 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3395 /* 8984 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3396 /* 8988 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3397 /* 8992 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3398 /* 8996 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3399 /* 9000 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3400 /* 9004 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3401 /* 9008 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3402 /* 9012 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3403 /* 9016 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3404 /* 9020 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3405 /* 9024 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3406 /* 9028 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3407 /* 9032 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3408 /* 9036 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3409 /* 9040 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3410 /* 9044 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3411 /* 9048 */ // MIs[5] vA
3412 /* 9048 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3413 /* 9053 */ // MIs[5] vB
3414 /* 9053 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3415 /* 9058 */ // MIs[4] vC
3416 /* 9058 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3417 /* 9063 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3418 /* 9067 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3419 /* 9073 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3420 /* 9075 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3421 /* 9077 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3422 /* 9077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3423 /* 9080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3424 /* 9082 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3425 /* 9086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
3426 /* 9090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3427 /* 9094 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3428 /* 9104 */ GIR_RootConstrainSelectedInstOperands,
3429 /* 9105 */ // GIR_Coverage, 5027,
3430 /* 9105 */ GIR_EraseRootFromParent_Done,
3431 /* 9106 */ // Label 289: @9106
3432 /* 9106 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(9244), // Rule ID 5028 //
3433 /* 9111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3434 /* 9114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3435 /* 9118 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3436 /* 9122 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3437 /* 9126 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3438 /* 9130 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3439 /* 9134 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3440 /* 9138 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3441 /* 9142 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3442 /* 9146 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3443 /* 9150 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3444 /* 9154 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3445 /* 9158 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3446 /* 9162 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3447 /* 9166 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3448 /* 9170 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3449 /* 9174 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3450 /* 9178 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3451 /* 9182 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3452 /* 9186 */ // MIs[5] vB
3453 /* 9186 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3454 /* 9191 */ // MIs[5] vA
3455 /* 9191 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3456 /* 9196 */ // MIs[4] vC
3457 /* 9196 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3458 /* 9201 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3459 /* 9205 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3460 /* 9211 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3461 /* 9213 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3462 /* 9215 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3463 /* 9215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3464 /* 9218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3465 /* 9220 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3466 /* 9224 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
3467 /* 9228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3468 /* 9232 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3469 /* 9242 */ GIR_RootConstrainSelectedInstOperands,
3470 /* 9243 */ // GIR_Coverage, 5028,
3471 /* 9243 */ GIR_EraseRootFromParent_Done,
3472 /* 9244 */ // Label 290: @9244
3473 /* 9244 */ GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(9382), // Rule ID 5029 //
3474 /* 9249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3475 /* 9252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3476 /* 9256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3477 /* 9260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3478 /* 9264 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3479 /* 9268 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3480 /* 9272 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3481 /* 9276 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3482 /* 9280 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3483 /* 9284 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3484 /* 9288 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3485 /* 9292 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3486 /* 9296 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3487 /* 9300 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3488 /* 9304 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3489 /* 9308 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3490 /* 9312 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3491 /* 9316 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3492 /* 9320 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3493 /* 9324 */ // MIs[5] vA
3494 /* 9324 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3495 /* 9329 */ // MIs[5] vC
3496 /* 9329 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3497 /* 9334 */ // MIs[4] vB
3498 /* 9334 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3499 /* 9339 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3500 /* 9343 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3501 /* 9349 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3502 /* 9351 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3503 /* 9353 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3504 /* 9353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3505 /* 9356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3506 /* 9358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3507 /* 9362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
3508 /* 9366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3509 /* 9370 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3510 /* 9380 */ GIR_RootConstrainSelectedInstOperands,
3511 /* 9381 */ // GIR_Coverage, 5029,
3512 /* 9381 */ GIR_EraseRootFromParent_Done,
3513 /* 9382 */ // Label 291: @9382
3514 /* 9382 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(9520), // Rule ID 5030 //
3515 /* 9387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3516 /* 9390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3517 /* 9394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3518 /* 9398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3519 /* 9402 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3520 /* 9406 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3521 /* 9410 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3522 /* 9414 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3523 /* 9418 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3524 /* 9422 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3525 /* 9426 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3526 /* 9430 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3527 /* 9434 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3528 /* 9438 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3529 /* 9442 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3530 /* 9446 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3531 /* 9450 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3532 /* 9454 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3533 /* 9458 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3534 /* 9462 */ // MIs[5] vC
3535 /* 9462 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3536 /* 9467 */ // MIs[5] vA
3537 /* 9467 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3538 /* 9472 */ // MIs[4] vB
3539 /* 9472 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3540 /* 9477 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3541 /* 9481 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3542 /* 9487 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3543 /* 9489 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3544 /* 9491 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3545 /* 9491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3546 /* 9494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3547 /* 9496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3548 /* 9500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
3549 /* 9504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3550 /* 9508 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3551 /* 9518 */ GIR_RootConstrainSelectedInstOperands,
3552 /* 9519 */ // GIR_Coverage, 5030,
3553 /* 9519 */ GIR_EraseRootFromParent_Done,
3554 /* 9520 */ // Label 292: @9520
3555 /* 9520 */ GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(9658), // Rule ID 5031 //
3556 /* 9525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3557 /* 9528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3558 /* 9532 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3559 /* 9536 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3560 /* 9540 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3561 /* 9544 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3562 /* 9548 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3563 /* 9552 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3564 /* 9556 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3565 /* 9560 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3566 /* 9564 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3567 /* 9568 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3568 /* 9572 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3569 /* 9576 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3570 /* 9580 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3571 /* 9584 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3572 /* 9588 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3573 /* 9592 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3574 /* 9596 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3575 /* 9600 */ // MIs[5] vB
3576 /* 9600 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3577 /* 9605 */ // MIs[5] vC
3578 /* 9605 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3579 /* 9610 */ // MIs[4] vA
3580 /* 9610 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3581 /* 9615 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3582 /* 9619 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3583 /* 9625 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3584 /* 9627 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3585 /* 9629 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3586 /* 9629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3587 /* 9632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3588 /* 9634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3589 /* 9638 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
3590 /* 9642 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3591 /* 9646 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3592 /* 9656 */ GIR_RootConstrainSelectedInstOperands,
3593 /* 9657 */ // GIR_Coverage, 5031,
3594 /* 9657 */ GIR_EraseRootFromParent_Done,
3595 /* 9658 */ // Label 293: @9658
3596 /* 9658 */ GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(9796), // Rule ID 5032 //
3597 /* 9663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3598 /* 9666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3599 /* 9670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3600 /* 9674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3601 /* 9678 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3602 /* 9682 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3603 /* 9686 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3604 /* 9690 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3605 /* 9694 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3606 /* 9698 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3607 /* 9702 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3608 /* 9706 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3609 /* 9710 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3610 /* 9714 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3611 /* 9718 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3612 /* 9722 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3613 /* 9726 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3614 /* 9730 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3615 /* 9734 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3616 /* 9738 */ // MIs[5] vC
3617 /* 9738 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3618 /* 9743 */ // MIs[5] vB
3619 /* 9743 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3620 /* 9748 */ // MIs[4] vA
3621 /* 9748 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3622 /* 9753 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3623 /* 9757 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3624 /* 9763 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3625 /* 9765 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3626 /* 9767 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3627 /* 9767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3628 /* 9770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3629 /* 9772 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3630 /* 9776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
3631 /* 9780 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
3632 /* 9784 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3633 /* 9794 */ GIR_RootConstrainSelectedInstOperands,
3634 /* 9795 */ // GIR_Coverage, 5032,
3635 /* 9795 */ GIR_EraseRootFromParent_Done,
3636 /* 9796 */ // Label 294: @9796
3637 /* 9796 */ GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(9934), // Rule ID 5039 //
3638 /* 9801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3639 /* 9804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3640 /* 9808 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3641 /* 9812 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3642 /* 9816 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3643 /* 9820 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3644 /* 9824 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3645 /* 9828 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3646 /* 9832 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3647 /* 9836 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3648 /* 9840 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3649 /* 9844 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3650 /* 9848 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3651 /* 9852 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3652 /* 9856 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3653 /* 9860 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3654 /* 9864 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3655 /* 9868 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3656 /* 9872 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3657 /* 9876 */ // MIs[5] vA
3658 /* 9876 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3659 /* 9881 */ // MIs[5] vB
3660 /* 9881 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3661 /* 9886 */ // MIs[4] vC
3662 /* 9886 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3663 /* 9891 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3664 /* 9895 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3665 /* 9901 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3666 /* 9903 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3667 /* 9905 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3668 /* 9905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3669 /* 9908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3670 /* 9910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3671 /* 9914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
3672 /* 9918 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3673 /* 9922 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3674 /* 9932 */ GIR_RootConstrainSelectedInstOperands,
3675 /* 9933 */ // GIR_Coverage, 5039,
3676 /* 9933 */ GIR_EraseRootFromParent_Done,
3677 /* 9934 */ // Label 295: @9934
3678 /* 9934 */ GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(10072), // Rule ID 5040 //
3679 /* 9939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3680 /* 9942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3681 /* 9946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3682 /* 9950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3683 /* 9954 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3684 /* 9958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3685 /* 9962 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3686 /* 9966 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3687 /* 9970 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3688 /* 9974 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3689 /* 9978 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3690 /* 9982 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3691 /* 9986 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3692 /* 9990 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3693 /* 9994 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3694 /* 9998 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3695 /* 10002 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3696 /* 10006 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3697 /* 10010 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3698 /* 10014 */ // MIs[5] vB
3699 /* 10014 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3700 /* 10019 */ // MIs[5] vA
3701 /* 10019 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3702 /* 10024 */ // MIs[4] vC
3703 /* 10024 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3704 /* 10029 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3705 /* 10033 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3706 /* 10039 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3707 /* 10041 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3708 /* 10043 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3709 /* 10043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3710 /* 10046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3711 /* 10048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3712 /* 10052 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
3713 /* 10056 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3714 /* 10060 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3715 /* 10070 */ GIR_RootConstrainSelectedInstOperands,
3716 /* 10071 */ // GIR_Coverage, 5040,
3717 /* 10071 */ GIR_EraseRootFromParent_Done,
3718 /* 10072 */ // Label 296: @10072
3719 /* 10072 */ GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(10210), // Rule ID 5041 //
3720 /* 10077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3721 /* 10080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3722 /* 10084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3723 /* 10088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3724 /* 10092 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3725 /* 10096 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3726 /* 10100 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3727 /* 10104 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3728 /* 10108 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3729 /* 10112 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3730 /* 10116 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3731 /* 10120 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3732 /* 10124 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3733 /* 10128 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3734 /* 10132 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3735 /* 10136 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3736 /* 10140 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3737 /* 10144 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3738 /* 10148 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3739 /* 10152 */ // MIs[5] vA
3740 /* 10152 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3741 /* 10157 */ // MIs[5] vC
3742 /* 10157 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3743 /* 10162 */ // MIs[4] vB
3744 /* 10162 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3745 /* 10167 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3746 /* 10171 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3747 /* 10177 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3748 /* 10179 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3749 /* 10181 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3750 /* 10181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3751 /* 10184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3752 /* 10186 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3753 /* 10190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
3754 /* 10194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3755 /* 10198 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3756 /* 10208 */ GIR_RootConstrainSelectedInstOperands,
3757 /* 10209 */ // GIR_Coverage, 5041,
3758 /* 10209 */ GIR_EraseRootFromParent_Done,
3759 /* 10210 */ // Label 297: @10210
3760 /* 10210 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(10348), // Rule ID 5042 //
3761 /* 10215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3762 /* 10218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3763 /* 10222 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3764 /* 10226 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3765 /* 10230 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3766 /* 10234 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3767 /* 10238 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3768 /* 10242 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3769 /* 10246 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3770 /* 10250 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3771 /* 10254 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3772 /* 10258 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3773 /* 10262 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3774 /* 10266 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3775 /* 10270 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3776 /* 10274 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3777 /* 10278 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3778 /* 10282 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3779 /* 10286 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3780 /* 10290 */ // MIs[5] vC
3781 /* 10290 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3782 /* 10295 */ // MIs[5] vA
3783 /* 10295 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3784 /* 10300 */ // MIs[4] vB
3785 /* 10300 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3786 /* 10305 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3787 /* 10309 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3788 /* 10315 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3789 /* 10317 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3790 /* 10319 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3791 /* 10319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3792 /* 10322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3793 /* 10324 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3794 /* 10328 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
3795 /* 10332 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3796 /* 10336 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3797 /* 10346 */ GIR_RootConstrainSelectedInstOperands,
3798 /* 10347 */ // GIR_Coverage, 5042,
3799 /* 10347 */ GIR_EraseRootFromParent_Done,
3800 /* 10348 */ // Label 298: @10348
3801 /* 10348 */ GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(10486), // Rule ID 5043 //
3802 /* 10353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3803 /* 10356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3804 /* 10360 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3805 /* 10364 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3806 /* 10368 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3807 /* 10372 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3808 /* 10376 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3809 /* 10380 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3810 /* 10384 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3811 /* 10388 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3812 /* 10392 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3813 /* 10396 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3814 /* 10400 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3815 /* 10404 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3816 /* 10408 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3817 /* 10412 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3818 /* 10416 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3819 /* 10420 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3820 /* 10424 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3821 /* 10428 */ // MIs[5] vB
3822 /* 10428 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3823 /* 10433 */ // MIs[5] vC
3824 /* 10433 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3825 /* 10438 */ // MIs[4] vA
3826 /* 10438 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3827 /* 10443 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3828 /* 10447 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3829 /* 10453 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3830 /* 10455 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3831 /* 10457 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3832 /* 10457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3833 /* 10460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3834 /* 10462 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3835 /* 10466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
3836 /* 10470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3837 /* 10474 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3838 /* 10484 */ GIR_RootConstrainSelectedInstOperands,
3839 /* 10485 */ // GIR_Coverage, 5043,
3840 /* 10485 */ GIR_EraseRootFromParent_Done,
3841 /* 10486 */ // Label 299: @10486
3842 /* 10486 */ GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(10624), // Rule ID 5044 //
3843 /* 10491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3844 /* 10494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3845 /* 10498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3846 /* 10502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3847 /* 10506 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3848 /* 10510 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3849 /* 10514 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3850 /* 10518 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3851 /* 10522 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3852 /* 10526 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3853 /* 10530 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3854 /* 10534 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3855 /* 10538 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3856 /* 10542 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3857 /* 10546 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3858 /* 10550 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3859 /* 10554 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
3860 /* 10558 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
3861 /* 10562 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3862 /* 10566 */ // MIs[5] vC
3863 /* 10566 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3864 /* 10571 */ // MIs[5] vB
3865 /* 10571 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3866 /* 10576 */ // MIs[4] vA
3867 /* 10576 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3868 /* 10581 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3869 /* 10585 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3870 /* 10591 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3871 /* 10593 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3872 /* 10595 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3873 /* 10595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3874 /* 10598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3875 /* 10600 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
3876 /* 10604 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
3877 /* 10608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
3878 /* 10612 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3879 /* 10622 */ GIR_RootConstrainSelectedInstOperands,
3880 /* 10623 */ // GIR_Coverage, 5044,
3881 /* 10623 */ GIR_EraseRootFromParent_Done,
3882 /* 10624 */ // Label 300: @10624
3883 /* 10624 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(10762), // Rule ID 4985 //
3884 /* 10629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3885 /* 10632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3886 /* 10636 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3887 /* 10640 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3888 /* 10644 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3889 /* 10648 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3890 /* 10652 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3891 /* 10656 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3892 /* 10660 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3893 /* 10664 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3894 /* 10668 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3895 /* 10672 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3896 /* 10676 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3897 /* 10680 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3898 /* 10684 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3899 /* 10688 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3900 /* 10692 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
3901 /* 10696 */ // MIs[4] vC
3902 /* 10696 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3903 /* 10701 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
3904 /* 10705 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3905 /* 10709 */ // MIs[5] vA
3906 /* 10709 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3907 /* 10714 */ // MIs[5] vB
3908 /* 10714 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
3909 /* 10719 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3910 /* 10723 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3911 /* 10729 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3912 /* 10731 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3913 /* 10733 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3914 /* 10733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3915 /* 10736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3916 /* 10738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
3917 /* 10742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
3918 /* 10746 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
3919 /* 10750 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3920 /* 10760 */ GIR_RootConstrainSelectedInstOperands,
3921 /* 10761 */ // GIR_Coverage, 4985,
3922 /* 10761 */ GIR_EraseRootFromParent_Done,
3923 /* 10762 */ // Label 301: @10762
3924 /* 10762 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(10900), // Rule ID 4986 //
3925 /* 10767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3926 /* 10770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3927 /* 10774 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3928 /* 10778 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3929 /* 10782 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3930 /* 10786 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3931 /* 10790 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3932 /* 10794 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3933 /* 10798 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3934 /* 10802 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3935 /* 10806 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3936 /* 10810 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3937 /* 10814 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3938 /* 10818 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3939 /* 10822 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3940 /* 10826 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3941 /* 10830 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
3942 /* 10834 */ // MIs[4] vC
3943 /* 10834 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
3944 /* 10839 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
3945 /* 10843 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3946 /* 10847 */ // MIs[5] vB
3947 /* 10847 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3948 /* 10852 */ // MIs[5] vA
3949 /* 10852 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
3950 /* 10857 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3951 /* 10861 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3952 /* 10867 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3953 /* 10869 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3954 /* 10871 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3955 /* 10871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3956 /* 10874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3957 /* 10876 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
3958 /* 10880 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
3959 /* 10884 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
3960 /* 10888 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
3961 /* 10898 */ GIR_RootConstrainSelectedInstOperands,
3962 /* 10899 */ // GIR_Coverage, 4986,
3963 /* 10899 */ GIR_EraseRootFromParent_Done,
3964 /* 10900 */ // Label 302: @10900
3965 /* 10900 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(11038), // Rule ID 4987 //
3966 /* 10905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
3967 /* 10908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
3968 /* 10912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3969 /* 10916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
3970 /* 10920 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3971 /* 10924 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3972 /* 10928 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3973 /* 10932 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
3974 /* 10936 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3975 /* 10940 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
3976 /* 10944 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
3977 /* 10948 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
3978 /* 10952 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
3979 /* 10956 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
3980 /* 10960 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
3981 /* 10964 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
3982 /* 10968 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
3983 /* 10972 */ // MIs[4] vB
3984 /* 10972 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
3985 /* 10977 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
3986 /* 10981 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
3987 /* 10985 */ // MIs[5] vA
3988 /* 10985 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
3989 /* 10990 */ // MIs[5] vC
3990 /* 10990 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
3991 /* 10995 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
3992 /* 10999 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
3993 /* 11005 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
3994 /* 11007 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
3995 /* 11009 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
3996 /* 11009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
3997 /* 11012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
3998 /* 11014 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
3999 /* 11018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
4000 /* 11022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4001 /* 11026 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4002 /* 11036 */ GIR_RootConstrainSelectedInstOperands,
4003 /* 11037 */ // GIR_Coverage, 4987,
4004 /* 11037 */ GIR_EraseRootFromParent_Done,
4005 /* 11038 */ // Label 303: @11038
4006 /* 11038 */ GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(11176), // Rule ID 4988 //
4007 /* 11043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4008 /* 11046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4009 /* 11050 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4010 /* 11054 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4011 /* 11058 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4012 /* 11062 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4013 /* 11066 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4014 /* 11070 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4015 /* 11074 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4016 /* 11078 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4017 /* 11082 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4018 /* 11086 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4019 /* 11090 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4020 /* 11094 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4021 /* 11098 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4022 /* 11102 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4023 /* 11106 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4024 /* 11110 */ // MIs[4] vB
4025 /* 11110 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4026 /* 11115 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4027 /* 11119 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4028 /* 11123 */ // MIs[5] vC
4029 /* 11123 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4030 /* 11128 */ // MIs[5] vA
4031 /* 11128 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4032 /* 11133 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4033 /* 11137 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4034 /* 11143 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4035 /* 11145 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4036 /* 11147 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4037 /* 11147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4038 /* 11150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4039 /* 11152 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4040 /* 11156 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
4041 /* 11160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4042 /* 11164 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4043 /* 11174 */ GIR_RootConstrainSelectedInstOperands,
4044 /* 11175 */ // GIR_Coverage, 4988,
4045 /* 11175 */ GIR_EraseRootFromParent_Done,
4046 /* 11176 */ // Label 304: @11176
4047 /* 11176 */ GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(11314), // Rule ID 4989 //
4048 /* 11181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4049 /* 11184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4050 /* 11188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4051 /* 11192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4052 /* 11196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4053 /* 11200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4054 /* 11204 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4055 /* 11208 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4056 /* 11212 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4057 /* 11216 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4058 /* 11220 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4059 /* 11224 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4060 /* 11228 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4061 /* 11232 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4062 /* 11236 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4063 /* 11240 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4064 /* 11244 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4065 /* 11248 */ // MIs[4] vA
4066 /* 11248 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4067 /* 11253 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4068 /* 11257 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4069 /* 11261 */ // MIs[5] vB
4070 /* 11261 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4071 /* 11266 */ // MIs[5] vC
4072 /* 11266 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4073 /* 11271 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4074 /* 11275 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4075 /* 11281 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4076 /* 11283 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4077 /* 11285 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4078 /* 11285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4079 /* 11288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4080 /* 11290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4081 /* 11294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
4082 /* 11298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4083 /* 11302 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4084 /* 11312 */ GIR_RootConstrainSelectedInstOperands,
4085 /* 11313 */ // GIR_Coverage, 4989,
4086 /* 11313 */ GIR_EraseRootFromParent_Done,
4087 /* 11314 */ // Label 305: @11314
4088 /* 11314 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(11452), // Rule ID 4990 //
4089 /* 11319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4090 /* 11322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4091 /* 11326 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4092 /* 11330 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4093 /* 11334 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4094 /* 11338 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4095 /* 11342 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4096 /* 11346 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4097 /* 11350 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4098 /* 11354 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4099 /* 11358 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4100 /* 11362 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4101 /* 11366 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4102 /* 11370 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4103 /* 11374 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4104 /* 11378 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4105 /* 11382 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4106 /* 11386 */ // MIs[4] vA
4107 /* 11386 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4108 /* 11391 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4109 /* 11395 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4110 /* 11399 */ // MIs[5] vC
4111 /* 11399 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4112 /* 11404 */ // MIs[5] vB
4113 /* 11404 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
4114 /* 11409 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4115 /* 11413 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4116 /* 11419 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4117 /* 11421 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4118 /* 11423 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4119 /* 11423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4120 /* 11426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4121 /* 11428 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4122 /* 11432 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
4123 /* 11436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4124 /* 11440 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4125 /* 11450 */ GIR_RootConstrainSelectedInstOperands,
4126 /* 11451 */ // GIR_Coverage, 4990,
4127 /* 11451 */ GIR_EraseRootFromParent_Done,
4128 /* 11452 */ // Label 306: @11452
4129 /* 11452 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(11590), // Rule ID 4997 //
4130 /* 11457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4131 /* 11460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4132 /* 11464 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4133 /* 11468 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4134 /* 11472 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4135 /* 11476 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4136 /* 11480 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4137 /* 11484 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4138 /* 11488 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4139 /* 11492 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4140 /* 11496 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4141 /* 11500 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4142 /* 11504 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4143 /* 11508 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4144 /* 11512 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4145 /* 11516 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4146 /* 11520 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4147 /* 11524 */ // MIs[4] vC
4148 /* 11524 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4149 /* 11529 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4150 /* 11533 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4151 /* 11537 */ // MIs[5] vA
4152 /* 11537 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4153 /* 11542 */ // MIs[5] vB
4154 /* 11542 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4155 /* 11547 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4156 /* 11551 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4157 /* 11557 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4158 /* 11559 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4159 /* 11561 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4160 /* 11561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4161 /* 11564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4162 /* 11566 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4163 /* 11570 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4164 /* 11574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4165 /* 11578 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4166 /* 11588 */ GIR_RootConstrainSelectedInstOperands,
4167 /* 11589 */ // GIR_Coverage, 4997,
4168 /* 11589 */ GIR_EraseRootFromParent_Done,
4169 /* 11590 */ // Label 307: @11590
4170 /* 11590 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(11728), // Rule ID 4998 //
4171 /* 11595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4172 /* 11598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4173 /* 11602 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4174 /* 11606 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4175 /* 11610 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4176 /* 11614 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4177 /* 11618 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4178 /* 11622 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4179 /* 11626 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4180 /* 11630 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4181 /* 11634 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4182 /* 11638 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4183 /* 11642 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4184 /* 11646 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4185 /* 11650 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4186 /* 11654 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4187 /* 11658 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4188 /* 11662 */ // MIs[4] vC
4189 /* 11662 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4190 /* 11667 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4191 /* 11671 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4192 /* 11675 */ // MIs[5] vB
4193 /* 11675 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4194 /* 11680 */ // MIs[5] vA
4195 /* 11680 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
4196 /* 11685 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4197 /* 11689 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4198 /* 11695 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4199 /* 11697 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4200 /* 11699 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4201 /* 11699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4202 /* 11702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4203 /* 11704 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4204 /* 11708 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4205 /* 11712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4206 /* 11716 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4207 /* 11726 */ GIR_RootConstrainSelectedInstOperands,
4208 /* 11727 */ // GIR_Coverage, 4998,
4209 /* 11727 */ GIR_EraseRootFromParent_Done,
4210 /* 11728 */ // Label 308: @11728
4211 /* 11728 */ GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(11866), // Rule ID 4999 //
4212 /* 11733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4213 /* 11736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4214 /* 11740 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4215 /* 11744 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4216 /* 11748 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4217 /* 11752 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4218 /* 11756 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4219 /* 11760 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4220 /* 11764 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4221 /* 11768 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4222 /* 11772 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4223 /* 11776 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4224 /* 11780 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4225 /* 11784 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4226 /* 11788 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4227 /* 11792 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4228 /* 11796 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4229 /* 11800 */ // MIs[4] vB
4230 /* 11800 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4231 /* 11805 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4232 /* 11809 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4233 /* 11813 */ // MIs[5] vA
4234 /* 11813 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4235 /* 11818 */ // MIs[5] vC
4236 /* 11818 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4237 /* 11823 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4238 /* 11827 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4239 /* 11833 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4240 /* 11835 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4241 /* 11837 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4242 /* 11837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4243 /* 11840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4244 /* 11842 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4245 /* 11846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4246 /* 11850 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4247 /* 11854 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4248 /* 11864 */ GIR_RootConstrainSelectedInstOperands,
4249 /* 11865 */ // GIR_Coverage, 4999,
4250 /* 11865 */ GIR_EraseRootFromParent_Done,
4251 /* 11866 */ // Label 309: @11866
4252 /* 11866 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(12004), // Rule ID 5000 //
4253 /* 11871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4254 /* 11874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4255 /* 11878 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4256 /* 11882 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4257 /* 11886 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4258 /* 11890 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4259 /* 11894 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4260 /* 11898 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4261 /* 11902 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4262 /* 11906 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4263 /* 11910 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4264 /* 11914 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4265 /* 11918 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4266 /* 11922 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4267 /* 11926 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4268 /* 11930 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4269 /* 11934 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4270 /* 11938 */ // MIs[4] vB
4271 /* 11938 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4272 /* 11943 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4273 /* 11947 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4274 /* 11951 */ // MIs[5] vC
4275 /* 11951 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4276 /* 11956 */ // MIs[5] vA
4277 /* 11956 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
4278 /* 11961 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4279 /* 11965 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4280 /* 11971 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4281 /* 11973 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4282 /* 11975 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4283 /* 11975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4284 /* 11978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4285 /* 11980 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4286 /* 11984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4287 /* 11988 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4288 /* 11992 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4289 /* 12002 */ GIR_RootConstrainSelectedInstOperands,
4290 /* 12003 */ // GIR_Coverage, 5000,
4291 /* 12003 */ GIR_EraseRootFromParent_Done,
4292 /* 12004 */ // Label 310: @12004
4293 /* 12004 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(12142), // Rule ID 5001 //
4294 /* 12009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4295 /* 12012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4296 /* 12016 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4297 /* 12020 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4298 /* 12024 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4299 /* 12028 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4300 /* 12032 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4301 /* 12036 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4302 /* 12040 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4303 /* 12044 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4304 /* 12048 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4305 /* 12052 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4306 /* 12056 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4307 /* 12060 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4308 /* 12064 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4309 /* 12068 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4310 /* 12072 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4311 /* 12076 */ // MIs[4] vA
4312 /* 12076 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4313 /* 12081 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4314 /* 12085 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4315 /* 12089 */ // MIs[5] vB
4316 /* 12089 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4317 /* 12094 */ // MIs[5] vC
4318 /* 12094 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4319 /* 12099 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4320 /* 12103 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4321 /* 12109 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4322 /* 12111 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4323 /* 12113 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4324 /* 12113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4325 /* 12116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4326 /* 12118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4327 /* 12122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4328 /* 12126 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4329 /* 12130 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4330 /* 12140 */ GIR_RootConstrainSelectedInstOperands,
4331 /* 12141 */ // GIR_Coverage, 5001,
4332 /* 12141 */ GIR_EraseRootFromParent_Done,
4333 /* 12142 */ // Label 311: @12142
4334 /* 12142 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(12280), // Rule ID 5002 //
4335 /* 12147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4336 /* 12150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4337 /* 12154 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4338 /* 12158 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4339 /* 12162 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4340 /* 12166 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4341 /* 12170 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4342 /* 12174 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4343 /* 12178 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4344 /* 12182 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4345 /* 12186 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4346 /* 12190 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4347 /* 12194 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4348 /* 12198 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4349 /* 12202 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4350 /* 12206 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4351 /* 12210 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4352 /* 12214 */ // MIs[4] vA
4353 /* 12214 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4354 /* 12219 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4355 /* 12223 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4356 /* 12227 */ // MIs[5] vC
4357 /* 12227 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4358 /* 12232 */ // MIs[5] vB
4359 /* 12232 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4360 /* 12237 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4361 /* 12241 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4362 /* 12247 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4363 /* 12249 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4364 /* 12251 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4365 /* 12251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4366 /* 12254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4367 /* 12256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4368 /* 12260 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4369 /* 12264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
4370 /* 12268 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4371 /* 12278 */ GIR_RootConstrainSelectedInstOperands,
4372 /* 12279 */ // GIR_Coverage, 5002,
4373 /* 12279 */ GIR_EraseRootFromParent_Done,
4374 /* 12280 */ // Label 312: @12280
4375 /* 12280 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(12418), // Rule ID 5009 //
4376 /* 12285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4377 /* 12288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4378 /* 12292 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4379 /* 12296 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4380 /* 12300 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4381 /* 12304 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4382 /* 12308 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4383 /* 12312 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4384 /* 12316 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4385 /* 12320 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4386 /* 12324 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4387 /* 12328 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4388 /* 12332 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4389 /* 12336 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4390 /* 12340 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4391 /* 12344 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4392 /* 12348 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4393 /* 12352 */ // MIs[4] vC
4394 /* 12352 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4395 /* 12357 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4396 /* 12361 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4397 /* 12365 */ // MIs[5] vA
4398 /* 12365 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4399 /* 12370 */ // MIs[5] vB
4400 /* 12370 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4401 /* 12375 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4402 /* 12379 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4403 /* 12385 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4404 /* 12387 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4405 /* 12389 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4406 /* 12389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4407 /* 12392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4408 /* 12394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4409 /* 12398 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4410 /* 12402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4411 /* 12406 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4412 /* 12416 */ GIR_RootConstrainSelectedInstOperands,
4413 /* 12417 */ // GIR_Coverage, 5009,
4414 /* 12417 */ GIR_EraseRootFromParent_Done,
4415 /* 12418 */ // Label 313: @12418
4416 /* 12418 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(12556), // Rule ID 5010 //
4417 /* 12423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4418 /* 12426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4419 /* 12430 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4420 /* 12434 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4421 /* 12438 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4422 /* 12442 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4423 /* 12446 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4424 /* 12450 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4425 /* 12454 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4426 /* 12458 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4427 /* 12462 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4428 /* 12466 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4429 /* 12470 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4430 /* 12474 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4431 /* 12478 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4432 /* 12482 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4433 /* 12486 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4434 /* 12490 */ // MIs[4] vC
4435 /* 12490 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4436 /* 12495 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4437 /* 12499 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4438 /* 12503 */ // MIs[5] vB
4439 /* 12503 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4440 /* 12508 */ // MIs[5] vA
4441 /* 12508 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4442 /* 12513 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4443 /* 12517 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4444 /* 12523 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4445 /* 12525 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4446 /* 12527 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4447 /* 12527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4448 /* 12530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4449 /* 12532 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4450 /* 12536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4451 /* 12540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4452 /* 12544 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4453 /* 12554 */ GIR_RootConstrainSelectedInstOperands,
4454 /* 12555 */ // GIR_Coverage, 5010,
4455 /* 12555 */ GIR_EraseRootFromParent_Done,
4456 /* 12556 */ // Label 314: @12556
4457 /* 12556 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(12694), // Rule ID 5011 //
4458 /* 12561 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4459 /* 12564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4460 /* 12568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4461 /* 12572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4462 /* 12576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4463 /* 12580 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4464 /* 12584 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4465 /* 12588 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4466 /* 12592 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4467 /* 12596 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4468 /* 12600 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4469 /* 12604 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4470 /* 12608 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4471 /* 12612 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4472 /* 12616 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4473 /* 12620 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4474 /* 12624 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4475 /* 12628 */ // MIs[4] vB
4476 /* 12628 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4477 /* 12633 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4478 /* 12637 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4479 /* 12641 */ // MIs[5] vA
4480 /* 12641 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4481 /* 12646 */ // MIs[5] vC
4482 /* 12646 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
4483 /* 12651 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4484 /* 12655 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4485 /* 12661 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4486 /* 12663 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4487 /* 12665 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4488 /* 12665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4489 /* 12668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4490 /* 12670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4491 /* 12674 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4492 /* 12678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4493 /* 12682 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4494 /* 12692 */ GIR_RootConstrainSelectedInstOperands,
4495 /* 12693 */ // GIR_Coverage, 5011,
4496 /* 12693 */ GIR_EraseRootFromParent_Done,
4497 /* 12694 */ // Label 315: @12694
4498 /* 12694 */ GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(12832), // Rule ID 5012 //
4499 /* 12699 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4500 /* 12702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4501 /* 12706 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4502 /* 12710 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4503 /* 12714 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4504 /* 12718 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4505 /* 12722 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4506 /* 12726 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4507 /* 12730 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4508 /* 12734 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4509 /* 12738 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4510 /* 12742 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4511 /* 12746 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4512 /* 12750 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4513 /* 12754 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4514 /* 12758 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4515 /* 12762 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4516 /* 12766 */ // MIs[4] vB
4517 /* 12766 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4518 /* 12771 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4519 /* 12775 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4520 /* 12779 */ // MIs[5] vC
4521 /* 12779 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4522 /* 12784 */ // MIs[5] vA
4523 /* 12784 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4524 /* 12789 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4525 /* 12793 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4526 /* 12799 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4527 /* 12801 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4528 /* 12803 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4529 /* 12803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4530 /* 12806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4531 /* 12808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4532 /* 12812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4533 /* 12816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4534 /* 12820 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4535 /* 12830 */ GIR_RootConstrainSelectedInstOperands,
4536 /* 12831 */ // GIR_Coverage, 5012,
4537 /* 12831 */ GIR_EraseRootFromParent_Done,
4538 /* 12832 */ // Label 316: @12832
4539 /* 12832 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(12970), // Rule ID 5013 //
4540 /* 12837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4541 /* 12840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4542 /* 12844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4543 /* 12848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4544 /* 12852 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4545 /* 12856 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4546 /* 12860 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4547 /* 12864 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4548 /* 12868 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4549 /* 12872 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4550 /* 12876 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4551 /* 12880 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4552 /* 12884 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4553 /* 12888 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4554 /* 12892 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4555 /* 12896 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4556 /* 12900 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4557 /* 12904 */ // MIs[4] vA
4558 /* 12904 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4559 /* 12909 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4560 /* 12913 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4561 /* 12917 */ // MIs[5] vB
4562 /* 12917 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4563 /* 12922 */ // MIs[5] vC
4564 /* 12922 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
4565 /* 12927 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4566 /* 12931 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4567 /* 12937 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4568 /* 12939 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4569 /* 12941 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4570 /* 12941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4571 /* 12944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4572 /* 12946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4573 /* 12950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4574 /* 12954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4575 /* 12958 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4576 /* 12968 */ GIR_RootConstrainSelectedInstOperands,
4577 /* 12969 */ // GIR_Coverage, 5013,
4578 /* 12969 */ GIR_EraseRootFromParent_Done,
4579 /* 12970 */ // Label 317: @12970
4580 /* 12970 */ GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(13108), // Rule ID 5014 //
4581 /* 12975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4582 /* 12978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4583 /* 12982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4584 /* 12986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4585 /* 12990 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4586 /* 12994 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4587 /* 12998 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4588 /* 13002 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4589 /* 13006 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4590 /* 13010 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4591 /* 13014 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4592 /* 13018 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4593 /* 13022 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4594 /* 13026 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4595 /* 13030 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4596 /* 13034 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4597 /* 13038 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4598 /* 13042 */ // MIs[4] vA
4599 /* 13042 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4600 /* 13047 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4601 /* 13051 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4602 /* 13055 */ // MIs[5] vC
4603 /* 13055 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4604 /* 13060 */ // MIs[5] vB
4605 /* 13060 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4606 /* 13065 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4607 /* 13069 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4608 /* 13075 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4609 /* 13077 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4610 /* 13079 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4611 /* 13079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4612 /* 13082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4613 /* 13084 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
4614 /* 13088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4615 /* 13092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4616 /* 13096 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4617 /* 13106 */ GIR_RootConstrainSelectedInstOperands,
4618 /* 13107 */ // GIR_Coverage, 5014,
4619 /* 13107 */ GIR_EraseRootFromParent_Done,
4620 /* 13108 */ // Label 318: @13108
4621 /* 13108 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(13246), // Rule ID 5021 //
4622 /* 13113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4623 /* 13116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4624 /* 13120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4625 /* 13124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4626 /* 13128 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4627 /* 13132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4628 /* 13136 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4629 /* 13140 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4630 /* 13144 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4631 /* 13148 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4632 /* 13152 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4633 /* 13156 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4634 /* 13160 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4635 /* 13164 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4636 /* 13168 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4637 /* 13172 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4638 /* 13176 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4639 /* 13180 */ // MIs[4] vC
4640 /* 13180 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4641 /* 13185 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4642 /* 13189 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4643 /* 13193 */ // MIs[5] vA
4644 /* 13193 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4645 /* 13198 */ // MIs[5] vB
4646 /* 13198 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4647 /* 13203 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4648 /* 13207 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4649 /* 13213 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4650 /* 13215 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4651 /* 13217 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4652 /* 13217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4653 /* 13220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4654 /* 13222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4655 /* 13226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4656 /* 13230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
4657 /* 13234 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4658 /* 13244 */ GIR_RootConstrainSelectedInstOperands,
4659 /* 13245 */ // GIR_Coverage, 5021,
4660 /* 13245 */ GIR_EraseRootFromParent_Done,
4661 /* 13246 */ // Label 319: @13246
4662 /* 13246 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(13384), // Rule ID 5022 //
4663 /* 13251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4664 /* 13254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4665 /* 13258 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4666 /* 13262 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4667 /* 13266 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4668 /* 13270 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4669 /* 13274 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4670 /* 13278 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4671 /* 13282 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4672 /* 13286 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4673 /* 13290 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4674 /* 13294 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4675 /* 13298 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4676 /* 13302 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4677 /* 13306 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4678 /* 13310 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4679 /* 13314 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4680 /* 13318 */ // MIs[4] vC
4681 /* 13318 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4682 /* 13323 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4683 /* 13327 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4684 /* 13331 */ // MIs[5] vB
4685 /* 13331 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4686 /* 13336 */ // MIs[5] vA
4687 /* 13336 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
4688 /* 13341 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4689 /* 13345 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4690 /* 13351 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4691 /* 13353 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4692 /* 13355 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4693 /* 13355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4694 /* 13358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4695 /* 13360 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4696 /* 13364 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4697 /* 13368 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
4698 /* 13372 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4699 /* 13382 */ GIR_RootConstrainSelectedInstOperands,
4700 /* 13383 */ // GIR_Coverage, 5022,
4701 /* 13383 */ GIR_EraseRootFromParent_Done,
4702 /* 13384 */ // Label 320: @13384
4703 /* 13384 */ GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(13522), // Rule ID 5023 //
4704 /* 13389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4705 /* 13392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4706 /* 13396 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4707 /* 13400 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4708 /* 13404 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4709 /* 13408 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4710 /* 13412 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4711 /* 13416 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4712 /* 13420 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4713 /* 13424 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4714 /* 13428 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4715 /* 13432 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4716 /* 13436 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4717 /* 13440 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4718 /* 13444 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4719 /* 13448 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4720 /* 13452 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4721 /* 13456 */ // MIs[4] vB
4722 /* 13456 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4723 /* 13461 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4724 /* 13465 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4725 /* 13469 */ // MIs[5] vA
4726 /* 13469 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4727 /* 13474 */ // MIs[5] vC
4728 /* 13474 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4729 /* 13479 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4730 /* 13483 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4731 /* 13489 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4732 /* 13491 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4733 /* 13493 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4734 /* 13493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4735 /* 13496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4736 /* 13498 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4737 /* 13502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4738 /* 13506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
4739 /* 13510 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4740 /* 13520 */ GIR_RootConstrainSelectedInstOperands,
4741 /* 13521 */ // GIR_Coverage, 5023,
4742 /* 13521 */ GIR_EraseRootFromParent_Done,
4743 /* 13522 */ // Label 321: @13522
4744 /* 13522 */ GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(13660), // Rule ID 5024 //
4745 /* 13527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4746 /* 13530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4747 /* 13534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4748 /* 13538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4749 /* 13542 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4750 /* 13546 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4751 /* 13550 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4752 /* 13554 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4753 /* 13558 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4754 /* 13562 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4755 /* 13566 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4756 /* 13570 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4757 /* 13574 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4758 /* 13578 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4759 /* 13582 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4760 /* 13586 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4761 /* 13590 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4762 /* 13594 */ // MIs[4] vB
4763 /* 13594 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4764 /* 13599 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4765 /* 13603 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4766 /* 13607 */ // MIs[5] vC
4767 /* 13607 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4768 /* 13612 */ // MIs[5] vA
4769 /* 13612 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
4770 /* 13617 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4771 /* 13621 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4772 /* 13627 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4773 /* 13629 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4774 /* 13631 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4775 /* 13631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4776 /* 13634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4777 /* 13636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4778 /* 13640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4779 /* 13644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
4780 /* 13648 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4781 /* 13658 */ GIR_RootConstrainSelectedInstOperands,
4782 /* 13659 */ // GIR_Coverage, 5024,
4783 /* 13659 */ GIR_EraseRootFromParent_Done,
4784 /* 13660 */ // Label 322: @13660
4785 /* 13660 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(13798), // Rule ID 5025 //
4786 /* 13665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4787 /* 13668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4788 /* 13672 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4789 /* 13676 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4790 /* 13680 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4791 /* 13684 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4792 /* 13688 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4793 /* 13692 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4794 /* 13696 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4795 /* 13700 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4796 /* 13704 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4797 /* 13708 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4798 /* 13712 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4799 /* 13716 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4800 /* 13720 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4801 /* 13724 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4802 /* 13728 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4803 /* 13732 */ // MIs[4] vA
4804 /* 13732 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4805 /* 13737 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4806 /* 13741 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4807 /* 13745 */ // MIs[5] vB
4808 /* 13745 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4809 /* 13750 */ // MIs[5] vC
4810 /* 13750 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4811 /* 13755 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4812 /* 13759 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4813 /* 13765 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4814 /* 13767 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4815 /* 13769 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4816 /* 13769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4817 /* 13772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4818 /* 13774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4819 /* 13778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4820 /* 13782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
4821 /* 13786 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4822 /* 13796 */ GIR_RootConstrainSelectedInstOperands,
4823 /* 13797 */ // GIR_Coverage, 5025,
4824 /* 13797 */ GIR_EraseRootFromParent_Done,
4825 /* 13798 */ // Label 323: @13798
4826 /* 13798 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(13936), // Rule ID 5026 //
4827 /* 13803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4828 /* 13806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4829 /* 13810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4830 /* 13814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4831 /* 13818 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4832 /* 13822 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4833 /* 13826 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4834 /* 13830 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4835 /* 13834 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4836 /* 13838 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4837 /* 13842 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4838 /* 13846 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4839 /* 13850 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4840 /* 13854 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4841 /* 13858 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4842 /* 13862 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4843 /* 13866 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4844 /* 13870 */ // MIs[4] vA
4845 /* 13870 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4846 /* 13875 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4847 /* 13879 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4848 /* 13883 */ // MIs[5] vC
4849 /* 13883 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4850 /* 13888 */ // MIs[5] vB
4851 /* 13888 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4852 /* 13893 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4853 /* 13897 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4854 /* 13903 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4855 /* 13905 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4856 /* 13907 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4857 /* 13907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4858 /* 13910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4859 /* 13912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
4860 /* 13916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
4861 /* 13920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
4862 /* 13924 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4863 /* 13934 */ GIR_RootConstrainSelectedInstOperands,
4864 /* 13935 */ // GIR_Coverage, 5026,
4865 /* 13935 */ GIR_EraseRootFromParent_Done,
4866 /* 13936 */ // Label 324: @13936
4867 /* 13936 */ GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(14074), // Rule ID 5033 //
4868 /* 13941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4869 /* 13944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4870 /* 13948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4871 /* 13952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4872 /* 13956 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4873 /* 13960 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4874 /* 13964 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4875 /* 13968 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4876 /* 13972 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4877 /* 13976 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4878 /* 13980 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4879 /* 13984 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4880 /* 13988 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4881 /* 13992 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4882 /* 13996 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4883 /* 14000 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4884 /* 14004 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4885 /* 14008 */ // MIs[4] vC
4886 /* 14008 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4887 /* 14013 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4888 /* 14017 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4889 /* 14021 */ // MIs[5] vA
4890 /* 14021 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4891 /* 14026 */ // MIs[5] vB
4892 /* 14026 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
4893 /* 14031 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4894 /* 14035 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4895 /* 14041 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4896 /* 14043 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4897 /* 14045 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4898 /* 14045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4899 /* 14048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4900 /* 14050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
4901 /* 14054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4902 /* 14058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4903 /* 14062 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4904 /* 14072 */ GIR_RootConstrainSelectedInstOperands,
4905 /* 14073 */ // GIR_Coverage, 5033,
4906 /* 14073 */ GIR_EraseRootFromParent_Done,
4907 /* 14074 */ // Label 325: @14074
4908 /* 14074 */ GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(14212), // Rule ID 5034 //
4909 /* 14079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4910 /* 14082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4911 /* 14086 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4912 /* 14090 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4913 /* 14094 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4914 /* 14098 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4915 /* 14102 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4916 /* 14106 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4917 /* 14110 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4918 /* 14114 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4919 /* 14118 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4920 /* 14122 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4921 /* 14126 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4922 /* 14130 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4923 /* 14134 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4924 /* 14138 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4925 /* 14142 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4926 /* 14146 */ // MIs[4] vC
4927 /* 14146 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
4928 /* 14151 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4929 /* 14155 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4930 /* 14159 */ // MIs[5] vB
4931 /* 14159 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4932 /* 14164 */ // MIs[5] vA
4933 /* 14164 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
4934 /* 14169 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4935 /* 14173 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4936 /* 14179 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4937 /* 14181 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4938 /* 14183 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4939 /* 14183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4940 /* 14186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4941 /* 14188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
4942 /* 14192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4943 /* 14196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4944 /* 14200 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4945 /* 14210 */ GIR_RootConstrainSelectedInstOperands,
4946 /* 14211 */ // GIR_Coverage, 5034,
4947 /* 14211 */ GIR_EraseRootFromParent_Done,
4948 /* 14212 */ // Label 326: @14212
4949 /* 14212 */ GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(14350), // Rule ID 5035 //
4950 /* 14217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4951 /* 14220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4952 /* 14224 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4953 /* 14228 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4954 /* 14232 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4955 /* 14236 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4956 /* 14240 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4957 /* 14244 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4958 /* 14248 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4959 /* 14252 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
4960 /* 14256 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
4961 /* 14260 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
4962 /* 14264 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
4963 /* 14268 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
4964 /* 14272 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
4965 /* 14276 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
4966 /* 14280 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
4967 /* 14284 */ // MIs[4] vB
4968 /* 14284 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
4969 /* 14289 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
4970 /* 14293 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
4971 /* 14297 */ // MIs[5] vA
4972 /* 14297 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
4973 /* 14302 */ // MIs[5] vC
4974 /* 14302 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
4975 /* 14307 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
4976 /* 14311 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
4977 /* 14317 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
4978 /* 14319 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
4979 /* 14321 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
4980 /* 14321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
4981 /* 14324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
4982 /* 14326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
4983 /* 14330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
4984 /* 14334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
4985 /* 14338 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
4986 /* 14348 */ GIR_RootConstrainSelectedInstOperands,
4987 /* 14349 */ // GIR_Coverage, 5035,
4988 /* 14349 */ GIR_EraseRootFromParent_Done,
4989 /* 14350 */ // Label 327: @14350
4990 /* 14350 */ GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(14488), // Rule ID 5036 //
4991 /* 14355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
4992 /* 14358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
4993 /* 14362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4994 /* 14366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
4995 /* 14370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4996 /* 14374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4997 /* 14378 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4998 /* 14382 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4999 /* 14386 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5000 /* 14390 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5001 /* 14394 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5002 /* 14398 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5003 /* 14402 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5004 /* 14406 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5005 /* 14410 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5006 /* 14414 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5007 /* 14418 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5008 /* 14422 */ // MIs[4] vB
5009 /* 14422 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5010 /* 14427 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5011 /* 14431 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5012 /* 14435 */ // MIs[5] vC
5013 /* 14435 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5014 /* 14440 */ // MIs[5] vA
5015 /* 14440 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
5016 /* 14445 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5017 /* 14449 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5018 /* 14455 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5019 /* 14457 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5020 /* 14459 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5021 /* 14459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5022 /* 14462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5023 /* 14464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5024 /* 14468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5025 /* 14472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
5026 /* 14476 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5027 /* 14486 */ GIR_RootConstrainSelectedInstOperands,
5028 /* 14487 */ // GIR_Coverage, 5036,
5029 /* 14487 */ GIR_EraseRootFromParent_Done,
5030 /* 14488 */ // Label 328: @14488
5031 /* 14488 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(14626), // Rule ID 5037 //
5032 /* 14493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5033 /* 14496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5034 /* 14500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5035 /* 14504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5036 /* 14508 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5037 /* 14512 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5038 /* 14516 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5039 /* 14520 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5040 /* 14524 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5041 /* 14528 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5042 /* 14532 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5043 /* 14536 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5044 /* 14540 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5045 /* 14544 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5046 /* 14548 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5047 /* 14552 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5048 /* 14556 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5049 /* 14560 */ // MIs[4] vA
5050 /* 14560 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
5051 /* 14565 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5052 /* 14569 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5053 /* 14573 */ // MIs[5] vB
5054 /* 14573 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5055 /* 14578 */ // MIs[5] vC
5056 /* 14578 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5057 /* 14583 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5058 /* 14587 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5059 /* 14593 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5060 /* 14595 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5061 /* 14597 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5062 /* 14597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5063 /* 14600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5064 /* 14602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5065 /* 14606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5066 /* 14610 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
5067 /* 14614 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5068 /* 14624 */ GIR_RootConstrainSelectedInstOperands,
5069 /* 14625 */ // GIR_Coverage, 5037,
5070 /* 14625 */ GIR_EraseRootFromParent_Done,
5071 /* 14626 */ // Label 329: @14626
5072 /* 14626 */ GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(14764), // Rule ID 5038 //
5073 /* 14631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5074 /* 14634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5075 /* 14638 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5076 /* 14642 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5077 /* 14646 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5078 /* 14650 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5079 /* 14654 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5080 /* 14658 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5081 /* 14662 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5082 /* 14666 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5083 /* 14670 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5084 /* 14674 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5085 /* 14678 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5086 /* 14682 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5087 /* 14686 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5088 /* 14690 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5089 /* 14694 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5090 /* 14698 */ // MIs[4] vA
5091 /* 14698 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
5092 /* 14703 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5093 /* 14707 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5094 /* 14711 */ // MIs[5] vC
5095 /* 14711 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5096 /* 14716 */ // MIs[5] vB
5097 /* 14716 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5098 /* 14721 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5099 /* 14725 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5100 /* 14731 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5101 /* 14733 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5102 /* 14735 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5103 /* 14735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5104 /* 14738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5105 /* 14740 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5106 /* 14744 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5107 /* 14748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
5108 /* 14752 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5109 /* 14762 */ GIR_RootConstrainSelectedInstOperands,
5110 /* 14763 */ // GIR_Coverage, 5038,
5111 /* 14763 */ GIR_EraseRootFromParent_Done,
5112 /* 14764 */ // Label 330: @14764
5113 /* 14764 */ GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(14902), // Rule ID 5045 //
5114 /* 14769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5115 /* 14772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5116 /* 14776 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5117 /* 14780 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5118 /* 14784 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5119 /* 14788 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5120 /* 14792 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5121 /* 14796 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5122 /* 14800 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5123 /* 14804 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5124 /* 14808 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5125 /* 14812 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5126 /* 14816 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5127 /* 14820 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5128 /* 14824 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5129 /* 14828 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5130 /* 14832 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5131 /* 14836 */ // MIs[4] vC
5132 /* 14836 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5133 /* 14841 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5134 /* 14845 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5135 /* 14849 */ // MIs[5] vA
5136 /* 14849 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
5137 /* 14854 */ // MIs[5] vB
5138 /* 14854 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5139 /* 14859 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5140 /* 14863 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5141 /* 14869 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5142 /* 14871 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5143 /* 14873 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5144 /* 14873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5145 /* 14876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5146 /* 14878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5147 /* 14882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5148 /* 14886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
5149 /* 14890 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5150 /* 14900 */ GIR_RootConstrainSelectedInstOperands,
5151 /* 14901 */ // GIR_Coverage, 5045,
5152 /* 14901 */ GIR_EraseRootFromParent_Done,
5153 /* 14902 */ // Label 331: @14902
5154 /* 14902 */ GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(15040), // Rule ID 5046 //
5155 /* 14907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5156 /* 14910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5157 /* 14914 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5158 /* 14918 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5159 /* 14922 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5160 /* 14926 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5161 /* 14930 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5162 /* 14934 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5163 /* 14938 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5164 /* 14942 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5165 /* 14946 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5166 /* 14950 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5167 /* 14954 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5168 /* 14958 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5169 /* 14962 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5170 /* 14966 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5171 /* 14970 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5172 /* 14974 */ // MIs[4] vC
5173 /* 14974 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5174 /* 14979 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5175 /* 14983 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5176 /* 14987 */ // MIs[5] vB
5177 /* 14987 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5178 /* 14992 */ // MIs[5] vA
5179 /* 14992 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
5180 /* 14997 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5181 /* 15001 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5182 /* 15007 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5183 /* 15009 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5184 /* 15011 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5185 /* 15011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5186 /* 15014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5187 /* 15016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5188 /* 15020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5189 /* 15024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
5190 /* 15028 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5191 /* 15038 */ GIR_RootConstrainSelectedInstOperands,
5192 /* 15039 */ // GIR_Coverage, 5046,
5193 /* 15039 */ GIR_EraseRootFromParent_Done,
5194 /* 15040 */ // Label 332: @15040
5195 /* 15040 */ GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(15178), // Rule ID 5047 //
5196 /* 15045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5197 /* 15048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5198 /* 15052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5199 /* 15056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5200 /* 15060 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5201 /* 15064 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5202 /* 15068 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5203 /* 15072 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5204 /* 15076 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5205 /* 15080 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5206 /* 15084 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5207 /* 15088 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5208 /* 15092 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5209 /* 15096 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5210 /* 15100 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5211 /* 15104 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5212 /* 15108 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5213 /* 15112 */ // MIs[4] vB
5214 /* 15112 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5215 /* 15117 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5216 /* 15121 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5217 /* 15125 */ // MIs[5] vA
5218 /* 15125 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
5219 /* 15130 */ // MIs[5] vC
5220 /* 15130 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5221 /* 15135 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5222 /* 15139 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5223 /* 15145 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5224 /* 15147 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5225 /* 15149 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5226 /* 15149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5227 /* 15152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5228 /* 15154 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5229 /* 15158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5230 /* 15162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
5231 /* 15166 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5232 /* 15176 */ GIR_RootConstrainSelectedInstOperands,
5233 /* 15177 */ // GIR_Coverage, 5047,
5234 /* 15177 */ GIR_EraseRootFromParent_Done,
5235 /* 15178 */ // Label 333: @15178
5236 /* 15178 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(15316), // Rule ID 5048 //
5237 /* 15183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5238 /* 15186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5239 /* 15190 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5240 /* 15194 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5241 /* 15198 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5242 /* 15202 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5243 /* 15206 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5244 /* 15210 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5245 /* 15214 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5246 /* 15218 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5247 /* 15222 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5248 /* 15226 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5249 /* 15230 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5250 /* 15234 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5251 /* 15238 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5252 /* 15242 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5253 /* 15246 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5254 /* 15250 */ // MIs[4] vB
5255 /* 15250 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5256 /* 15255 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5257 /* 15259 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5258 /* 15263 */ // MIs[5] vC
5259 /* 15263 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5260 /* 15268 */ // MIs[5] vA
5261 /* 15268 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
5262 /* 15273 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5263 /* 15277 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5264 /* 15283 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5265 /* 15285 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5266 /* 15287 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5267 /* 15287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5268 /* 15290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5269 /* 15292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5270 /* 15296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5271 /* 15300 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
5272 /* 15304 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5273 /* 15314 */ GIR_RootConstrainSelectedInstOperands,
5274 /* 15315 */ // GIR_Coverage, 5048,
5275 /* 15315 */ GIR_EraseRootFromParent_Done,
5276 /* 15316 */ // Label 334: @15316
5277 /* 15316 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(15454), // Rule ID 5049 //
5278 /* 15321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5279 /* 15324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5280 /* 15328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5281 /* 15332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5282 /* 15336 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5283 /* 15340 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5284 /* 15344 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5285 /* 15348 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5286 /* 15352 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5287 /* 15356 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5288 /* 15360 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5289 /* 15364 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5290 /* 15368 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5291 /* 15372 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5292 /* 15376 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5293 /* 15380 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5294 /* 15384 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5295 /* 15388 */ // MIs[4] vA
5296 /* 15388 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
5297 /* 15393 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5298 /* 15397 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5299 /* 15401 */ // MIs[5] vB
5300 /* 15401 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5301 /* 15406 */ // MIs[5] vC
5302 /* 15406 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5303 /* 15411 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5304 /* 15415 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5305 /* 15421 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5306 /* 15423 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5307 /* 15425 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5308 /* 15425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5309 /* 15428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5310 /* 15430 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5311 /* 15434 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5312 /* 15438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
5313 /* 15442 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5314 /* 15452 */ GIR_RootConstrainSelectedInstOperands,
5315 /* 15453 */ // GIR_Coverage, 5049,
5316 /* 15453 */ GIR_EraseRootFromParent_Done,
5317 /* 15454 */ // Label 335: @15454
5318 /* 15454 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(15592), // Rule ID 5050 //
5319 /* 15459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5320 /* 15462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5321 /* 15466 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5322 /* 15470 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5323 /* 15474 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5324 /* 15478 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5325 /* 15482 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5326 /* 15486 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5327 /* 15490 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5328 /* 15494 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5329 /* 15498 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5330 /* 15502 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5331 /* 15506 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5332 /* 15510 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5333 /* 15514 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5334 /* 15518 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5335 /* 15522 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
5336 /* 15526 */ // MIs[4] vA
5337 /* 15526 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
5338 /* 15531 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
5339 /* 15535 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5340 /* 15539 */ // MIs[5] vC
5341 /* 15539 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5342 /* 15544 */ // MIs[5] vB
5343 /* 15544 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5344 /* 15549 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5345 /* 15553 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5346 /* 15559 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5347 /* 15561 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5348 /* 15563 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5349 /* 15563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5350 /* 15566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5351 /* 15568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
5352 /* 15572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5353 /* 15576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
5354 /* 15580 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5355 /* 15590 */ GIR_RootConstrainSelectedInstOperands,
5356 /* 15591 */ // GIR_Coverage, 5050,
5357 /* 15591 */ GIR_EraseRootFromParent_Done,
5358 /* 15592 */ // Label 336: @15592
5359 /* 15592 */ GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(15730), // Rule ID 5051 //
5360 /* 15597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5361 /* 15600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5362 /* 15604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5363 /* 15608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5364 /* 15612 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5365 /* 15616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5366 /* 15620 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5367 /* 15624 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5368 /* 15628 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5369 /* 15632 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5370 /* 15636 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5371 /* 15640 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5372 /* 15644 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5373 /* 15648 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5374 /* 15652 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5375 /* 15656 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5376 /* 15660 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5377 /* 15664 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5378 /* 15668 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5379 /* 15672 */ // MIs[5] vA
5380 /* 15672 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5381 /* 15677 */ // MIs[5] vB
5382 /* 15677 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5383 /* 15682 */ // MIs[4] vC
5384 /* 15682 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5385 /* 15687 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5386 /* 15691 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5387 /* 15697 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5388 /* 15699 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5389 /* 15701 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5390 /* 15701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5391 /* 15704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5392 /* 15706 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5393 /* 15710 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5394 /* 15714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5395 /* 15718 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5396 /* 15728 */ GIR_RootConstrainSelectedInstOperands,
5397 /* 15729 */ // GIR_Coverage, 5051,
5398 /* 15729 */ GIR_EraseRootFromParent_Done,
5399 /* 15730 */ // Label 337: @15730
5400 /* 15730 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(15868), // Rule ID 5052 //
5401 /* 15735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5402 /* 15738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5403 /* 15742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5404 /* 15746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5405 /* 15750 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5406 /* 15754 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5407 /* 15758 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5408 /* 15762 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5409 /* 15766 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5410 /* 15770 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5411 /* 15774 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5412 /* 15778 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5413 /* 15782 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5414 /* 15786 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5415 /* 15790 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5416 /* 15794 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5417 /* 15798 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5418 /* 15802 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5419 /* 15806 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5420 /* 15810 */ // MIs[5] vB
5421 /* 15810 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5422 /* 15815 */ // MIs[5] vA
5423 /* 15815 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5424 /* 15820 */ // MIs[4] vC
5425 /* 15820 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5426 /* 15825 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5427 /* 15829 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5428 /* 15835 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5429 /* 15837 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5430 /* 15839 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5431 /* 15839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5432 /* 15842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5433 /* 15844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5434 /* 15848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5435 /* 15852 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5436 /* 15856 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5437 /* 15866 */ GIR_RootConstrainSelectedInstOperands,
5438 /* 15867 */ // GIR_Coverage, 5052,
5439 /* 15867 */ GIR_EraseRootFromParent_Done,
5440 /* 15868 */ // Label 338: @15868
5441 /* 15868 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(16006), // Rule ID 5053 //
5442 /* 15873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5443 /* 15876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5444 /* 15880 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5445 /* 15884 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5446 /* 15888 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5447 /* 15892 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5448 /* 15896 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5449 /* 15900 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5450 /* 15904 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5451 /* 15908 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5452 /* 15912 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5453 /* 15916 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5454 /* 15920 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5455 /* 15924 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5456 /* 15928 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5457 /* 15932 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5458 /* 15936 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5459 /* 15940 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5460 /* 15944 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5461 /* 15948 */ // MIs[5] vA
5462 /* 15948 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5463 /* 15953 */ // MIs[5] vC
5464 /* 15953 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5465 /* 15958 */ // MIs[4] vB
5466 /* 15958 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5467 /* 15963 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5468 /* 15967 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5469 /* 15973 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5470 /* 15975 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5471 /* 15977 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5472 /* 15977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5473 /* 15980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5474 /* 15982 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5475 /* 15986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5476 /* 15990 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5477 /* 15994 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5478 /* 16004 */ GIR_RootConstrainSelectedInstOperands,
5479 /* 16005 */ // GIR_Coverage, 5053,
5480 /* 16005 */ GIR_EraseRootFromParent_Done,
5481 /* 16006 */ // Label 339: @16006
5482 /* 16006 */ GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(16144), // Rule ID 5054 //
5483 /* 16011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5484 /* 16014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5485 /* 16018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5486 /* 16022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5487 /* 16026 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5488 /* 16030 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5489 /* 16034 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5490 /* 16038 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5491 /* 16042 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5492 /* 16046 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5493 /* 16050 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5494 /* 16054 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5495 /* 16058 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5496 /* 16062 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5497 /* 16066 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5498 /* 16070 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5499 /* 16074 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5500 /* 16078 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5501 /* 16082 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5502 /* 16086 */ // MIs[5] vC
5503 /* 16086 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
5504 /* 16091 */ // MIs[5] vA
5505 /* 16091 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5506 /* 16096 */ // MIs[4] vB
5507 /* 16096 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5508 /* 16101 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5509 /* 16105 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5510 /* 16111 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5511 /* 16113 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5512 /* 16115 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5513 /* 16115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5514 /* 16118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5515 /* 16120 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5516 /* 16124 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5517 /* 16128 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5518 /* 16132 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5519 /* 16142 */ GIR_RootConstrainSelectedInstOperands,
5520 /* 16143 */ // GIR_Coverage, 5054,
5521 /* 16143 */ GIR_EraseRootFromParent_Done,
5522 /* 16144 */ // Label 340: @16144
5523 /* 16144 */ GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(16282), // Rule ID 5055 //
5524 /* 16149 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5525 /* 16152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5526 /* 16156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5527 /* 16160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5528 /* 16164 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5529 /* 16168 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5530 /* 16172 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5531 /* 16176 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5532 /* 16180 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5533 /* 16184 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5534 /* 16188 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5535 /* 16192 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5536 /* 16196 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5537 /* 16200 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5538 /* 16204 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5539 /* 16208 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5540 /* 16212 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5541 /* 16216 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5542 /* 16220 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5543 /* 16224 */ // MIs[5] vB
5544 /* 16224 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5545 /* 16229 */ // MIs[5] vC
5546 /* 16229 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5547 /* 16234 */ // MIs[4] vA
5548 /* 16234 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5549 /* 16239 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5550 /* 16243 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5551 /* 16249 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5552 /* 16251 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5553 /* 16253 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5554 /* 16253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5555 /* 16256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5556 /* 16258 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5557 /* 16262 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5558 /* 16266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5559 /* 16270 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5560 /* 16280 */ GIR_RootConstrainSelectedInstOperands,
5561 /* 16281 */ // GIR_Coverage, 5055,
5562 /* 16281 */ GIR_EraseRootFromParent_Done,
5563 /* 16282 */ // Label 341: @16282
5564 /* 16282 */ GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(16420), // Rule ID 5056 //
5565 /* 16287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5566 /* 16290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5567 /* 16294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5568 /* 16298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5569 /* 16302 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5570 /* 16306 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5571 /* 16310 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5572 /* 16314 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5573 /* 16318 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5574 /* 16322 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5575 /* 16326 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5576 /* 16330 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5577 /* 16334 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5578 /* 16338 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5579 /* 16342 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5580 /* 16346 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5581 /* 16350 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5582 /* 16354 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5583 /* 16358 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5584 /* 16362 */ // MIs[5] vC
5585 /* 16362 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
5586 /* 16367 */ // MIs[5] vB
5587 /* 16367 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5588 /* 16372 */ // MIs[4] vA
5589 /* 16372 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5590 /* 16377 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5591 /* 16381 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5592 /* 16387 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5593 /* 16389 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5594 /* 16391 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5595 /* 16391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5596 /* 16394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5597 /* 16396 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5598 /* 16400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
5599 /* 16404 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5600 /* 16408 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5601 /* 16418 */ GIR_RootConstrainSelectedInstOperands,
5602 /* 16419 */ // GIR_Coverage, 5056,
5603 /* 16419 */ GIR_EraseRootFromParent_Done,
5604 /* 16420 */ // Label 342: @16420
5605 /* 16420 */ GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(16558), // Rule ID 5063 //
5606 /* 16425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5607 /* 16428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5608 /* 16432 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5609 /* 16436 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5610 /* 16440 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5611 /* 16444 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5612 /* 16448 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5613 /* 16452 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5614 /* 16456 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5615 /* 16460 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5616 /* 16464 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5617 /* 16468 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5618 /* 16472 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5619 /* 16476 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5620 /* 16480 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5621 /* 16484 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5622 /* 16488 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5623 /* 16492 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5624 /* 16496 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5625 /* 16500 */ // MIs[5] vA
5626 /* 16500 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5627 /* 16505 */ // MIs[5] vB
5628 /* 16505 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5629 /* 16510 */ // MIs[4] vC
5630 /* 16510 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5631 /* 16515 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5632 /* 16519 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5633 /* 16525 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5634 /* 16527 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5635 /* 16529 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5636 /* 16529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5637 /* 16532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5638 /* 16534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
5639 /* 16538 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5640 /* 16542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5641 /* 16546 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5642 /* 16556 */ GIR_RootConstrainSelectedInstOperands,
5643 /* 16557 */ // GIR_Coverage, 5063,
5644 /* 16557 */ GIR_EraseRootFromParent_Done,
5645 /* 16558 */ // Label 343: @16558
5646 /* 16558 */ GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(16696), // Rule ID 5064 //
5647 /* 16563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5648 /* 16566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5649 /* 16570 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5650 /* 16574 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5651 /* 16578 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5652 /* 16582 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5653 /* 16586 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5654 /* 16590 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5655 /* 16594 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5656 /* 16598 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5657 /* 16602 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5658 /* 16606 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5659 /* 16610 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5660 /* 16614 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5661 /* 16618 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5662 /* 16622 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5663 /* 16626 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5664 /* 16630 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5665 /* 16634 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5666 /* 16638 */ // MIs[5] vB
5667 /* 16638 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5668 /* 16643 */ // MIs[5] vA
5669 /* 16643 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5670 /* 16648 */ // MIs[4] vC
5671 /* 16648 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5672 /* 16653 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5673 /* 16657 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5674 /* 16663 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5675 /* 16665 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5676 /* 16667 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5677 /* 16667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5678 /* 16670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5679 /* 16672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
5680 /* 16676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5681 /* 16680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5682 /* 16684 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5683 /* 16694 */ GIR_RootConstrainSelectedInstOperands,
5684 /* 16695 */ // GIR_Coverage, 5064,
5685 /* 16695 */ GIR_EraseRootFromParent_Done,
5686 /* 16696 */ // Label 344: @16696
5687 /* 16696 */ GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(16834), // Rule ID 5065 //
5688 /* 16701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5689 /* 16704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5690 /* 16708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5691 /* 16712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5692 /* 16716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5693 /* 16720 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5694 /* 16724 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5695 /* 16728 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5696 /* 16732 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5697 /* 16736 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5698 /* 16740 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5699 /* 16744 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5700 /* 16748 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5701 /* 16752 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5702 /* 16756 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5703 /* 16760 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5704 /* 16764 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5705 /* 16768 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5706 /* 16772 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5707 /* 16776 */ // MIs[5] vA
5708 /* 16776 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5709 /* 16781 */ // MIs[5] vC
5710 /* 16781 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5711 /* 16786 */ // MIs[4] vB
5712 /* 16786 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5713 /* 16791 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5714 /* 16795 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5715 /* 16801 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5716 /* 16803 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5717 /* 16805 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5718 /* 16805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5719 /* 16808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5720 /* 16810 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
5721 /* 16814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5722 /* 16818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5723 /* 16822 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5724 /* 16832 */ GIR_RootConstrainSelectedInstOperands,
5725 /* 16833 */ // GIR_Coverage, 5065,
5726 /* 16833 */ GIR_EraseRootFromParent_Done,
5727 /* 16834 */ // Label 345: @16834
5728 /* 16834 */ GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(16972), // Rule ID 5066 //
5729 /* 16839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5730 /* 16842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5731 /* 16846 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5732 /* 16850 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5733 /* 16854 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5734 /* 16858 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5735 /* 16862 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5736 /* 16866 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5737 /* 16870 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5738 /* 16874 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5739 /* 16878 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5740 /* 16882 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5741 /* 16886 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5742 /* 16890 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5743 /* 16894 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5744 /* 16898 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5745 /* 16902 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5746 /* 16906 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5747 /* 16910 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5748 /* 16914 */ // MIs[5] vC
5749 /* 16914 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
5750 /* 16919 */ // MIs[5] vA
5751 /* 16919 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5752 /* 16924 */ // MIs[4] vB
5753 /* 16924 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5754 /* 16929 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5755 /* 16933 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5756 /* 16939 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5757 /* 16941 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5758 /* 16943 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5759 /* 16943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5760 /* 16946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5761 /* 16948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
5762 /* 16952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5763 /* 16956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5764 /* 16960 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5765 /* 16970 */ GIR_RootConstrainSelectedInstOperands,
5766 /* 16971 */ // GIR_Coverage, 5066,
5767 /* 16971 */ GIR_EraseRootFromParent_Done,
5768 /* 16972 */ // Label 346: @16972
5769 /* 16972 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(17110), // Rule ID 5067 //
5770 /* 16977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5771 /* 16980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5772 /* 16984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5773 /* 16988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5774 /* 16992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5775 /* 16996 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5776 /* 17000 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5777 /* 17004 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5778 /* 17008 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5779 /* 17012 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5780 /* 17016 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5781 /* 17020 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5782 /* 17024 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5783 /* 17028 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5784 /* 17032 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5785 /* 17036 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5786 /* 17040 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5787 /* 17044 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5788 /* 17048 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5789 /* 17052 */ // MIs[5] vB
5790 /* 17052 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5791 /* 17057 */ // MIs[5] vC
5792 /* 17057 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5793 /* 17062 */ // MIs[4] vA
5794 /* 17062 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5795 /* 17067 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5796 /* 17071 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5797 /* 17077 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5798 /* 17079 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5799 /* 17081 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5800 /* 17081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5801 /* 17084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5802 /* 17086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
5803 /* 17090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5804 /* 17094 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5805 /* 17098 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5806 /* 17108 */ GIR_RootConstrainSelectedInstOperands,
5807 /* 17109 */ // GIR_Coverage, 5067,
5808 /* 17109 */ GIR_EraseRootFromParent_Done,
5809 /* 17110 */ // Label 347: @17110
5810 /* 17110 */ GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(17248), // Rule ID 5068 //
5811 /* 17115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5812 /* 17118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5813 /* 17122 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5814 /* 17126 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5815 /* 17130 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5816 /* 17134 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5817 /* 17138 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5818 /* 17142 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5819 /* 17146 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5820 /* 17150 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5821 /* 17154 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5822 /* 17158 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5823 /* 17162 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5824 /* 17166 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5825 /* 17170 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5826 /* 17174 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5827 /* 17178 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5828 /* 17182 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5829 /* 17186 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5830 /* 17190 */ // MIs[5] vC
5831 /* 17190 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
5832 /* 17195 */ // MIs[5] vB
5833 /* 17195 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5834 /* 17200 */ // MIs[4] vA
5835 /* 17200 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5836 /* 17205 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5837 /* 17209 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5838 /* 17215 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5839 /* 17217 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5840 /* 17219 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5841 /* 17219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5842 /* 17222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5843 /* 17224 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
5844 /* 17228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
5845 /* 17232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
5846 /* 17236 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5847 /* 17246 */ GIR_RootConstrainSelectedInstOperands,
5848 /* 17247 */ // GIR_Coverage, 5068,
5849 /* 17247 */ GIR_EraseRootFromParent_Done,
5850 /* 17248 */ // Label 348: @17248
5851 /* 17248 */ GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(17386), // Rule ID 5075 //
5852 /* 17253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5853 /* 17256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5854 /* 17260 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5855 /* 17264 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5856 /* 17268 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5857 /* 17272 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5858 /* 17276 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5859 /* 17280 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5860 /* 17284 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5861 /* 17288 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5862 /* 17292 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5863 /* 17296 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5864 /* 17300 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5865 /* 17304 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5866 /* 17308 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5867 /* 17312 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5868 /* 17316 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5869 /* 17320 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5870 /* 17324 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5871 /* 17328 */ // MIs[5] vA
5872 /* 17328 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5873 /* 17333 */ // MIs[5] vB
5874 /* 17333 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5875 /* 17338 */ // MIs[4] vC
5876 /* 17338 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5877 /* 17343 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5878 /* 17347 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5879 /* 17353 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5880 /* 17355 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5881 /* 17357 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5882 /* 17357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5883 /* 17360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5884 /* 17362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5885 /* 17366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
5886 /* 17370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
5887 /* 17374 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5888 /* 17384 */ GIR_RootConstrainSelectedInstOperands,
5889 /* 17385 */ // GIR_Coverage, 5075,
5890 /* 17385 */ GIR_EraseRootFromParent_Done,
5891 /* 17386 */ // Label 349: @17386
5892 /* 17386 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(17524), // Rule ID 5076 //
5893 /* 17391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5894 /* 17394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5895 /* 17398 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5896 /* 17402 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5897 /* 17406 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5898 /* 17410 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5899 /* 17414 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5900 /* 17418 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5901 /* 17422 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5902 /* 17426 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5903 /* 17430 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5904 /* 17434 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5905 /* 17438 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5906 /* 17442 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5907 /* 17446 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5908 /* 17450 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5909 /* 17454 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5910 /* 17458 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5911 /* 17462 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5912 /* 17466 */ // MIs[5] vB
5913 /* 17466 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
5914 /* 17471 */ // MIs[5] vA
5915 /* 17471 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5916 /* 17476 */ // MIs[4] vC
5917 /* 17476 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5918 /* 17481 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5919 /* 17485 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5920 /* 17491 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5921 /* 17493 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5922 /* 17495 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5923 /* 17495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5924 /* 17498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5925 /* 17500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5926 /* 17504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
5927 /* 17508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
5928 /* 17512 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5929 /* 17522 */ GIR_RootConstrainSelectedInstOperands,
5930 /* 17523 */ // GIR_Coverage, 5076,
5931 /* 17523 */ GIR_EraseRootFromParent_Done,
5932 /* 17524 */ // Label 350: @17524
5933 /* 17524 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(17662), // Rule ID 5077 //
5934 /* 17529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5935 /* 17532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5936 /* 17536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5937 /* 17540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5938 /* 17544 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5939 /* 17548 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5940 /* 17552 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5941 /* 17556 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5942 /* 17560 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5943 /* 17564 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5944 /* 17568 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5945 /* 17572 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5946 /* 17576 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5947 /* 17580 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5948 /* 17584 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5949 /* 17588 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5950 /* 17592 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5951 /* 17596 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5952 /* 17600 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5953 /* 17604 */ // MIs[5] vA
5954 /* 17604 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5955 /* 17609 */ // MIs[5] vC
5956 /* 17609 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
5957 /* 17614 */ // MIs[4] vB
5958 /* 17614 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
5959 /* 17619 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
5960 /* 17623 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
5961 /* 17629 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
5962 /* 17631 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
5963 /* 17633 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
5964 /* 17633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
5965 /* 17636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
5966 /* 17638 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
5967 /* 17642 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
5968 /* 17646 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
5969 /* 17650 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
5970 /* 17660 */ GIR_RootConstrainSelectedInstOperands,
5971 /* 17661 */ // GIR_Coverage, 5077,
5972 /* 17661 */ GIR_EraseRootFromParent_Done,
5973 /* 17662 */ // Label 351: @17662
5974 /* 17662 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(17800), // Rule ID 5078 //
5975 /* 17667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
5976 /* 17670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
5977 /* 17674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5978 /* 17678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
5979 /* 17682 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5980 /* 17686 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5981 /* 17690 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5982 /* 17694 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5983 /* 17698 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
5984 /* 17702 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
5985 /* 17706 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5986 /* 17710 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
5987 /* 17714 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
5988 /* 17718 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
5989 /* 17722 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5990 /* 17726 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
5991 /* 17730 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
5992 /* 17734 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
5993 /* 17738 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
5994 /* 17742 */ // MIs[5] vC
5995 /* 17742 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
5996 /* 17747 */ // MIs[5] vA
5997 /* 17747 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
5998 /* 17752 */ // MIs[4] vB
5999 /* 17752 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6000 /* 17757 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6001 /* 17761 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6002 /* 17767 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6003 /* 17769 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6004 /* 17771 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6005 /* 17771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6006 /* 17774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6007 /* 17776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
6008 /* 17780 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6009 /* 17784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6010 /* 17788 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6011 /* 17798 */ GIR_RootConstrainSelectedInstOperands,
6012 /* 17799 */ // GIR_Coverage, 5078,
6013 /* 17799 */ GIR_EraseRootFromParent_Done,
6014 /* 17800 */ // Label 352: @17800
6015 /* 17800 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(17938), // Rule ID 5079 //
6016 /* 17805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6017 /* 17808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6018 /* 17812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6019 /* 17816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6020 /* 17820 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6021 /* 17824 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6022 /* 17828 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6023 /* 17832 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6024 /* 17836 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6025 /* 17840 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6026 /* 17844 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6027 /* 17848 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6028 /* 17852 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6029 /* 17856 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6030 /* 17860 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6031 /* 17864 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6032 /* 17868 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6033 /* 17872 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6034 /* 17876 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6035 /* 17880 */ // MIs[5] vB
6036 /* 17880 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6037 /* 17885 */ // MIs[5] vC
6038 /* 17885 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6039 /* 17890 */ // MIs[4] vA
6040 /* 17890 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6041 /* 17895 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6042 /* 17899 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6043 /* 17905 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6044 /* 17907 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6045 /* 17909 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6046 /* 17909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6047 /* 17912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6048 /* 17914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
6049 /* 17918 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6050 /* 17922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6051 /* 17926 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6052 /* 17936 */ GIR_RootConstrainSelectedInstOperands,
6053 /* 17937 */ // GIR_Coverage, 5079,
6054 /* 17937 */ GIR_EraseRootFromParent_Done,
6055 /* 17938 */ // Label 353: @17938
6056 /* 17938 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(18076), // Rule ID 5080 //
6057 /* 17943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6058 /* 17946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6059 /* 17950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6060 /* 17954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6061 /* 17958 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6062 /* 17962 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6063 /* 17966 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6064 /* 17970 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6065 /* 17974 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6066 /* 17978 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6067 /* 17982 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6068 /* 17986 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6069 /* 17990 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6070 /* 17994 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6071 /* 17998 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6072 /* 18002 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6073 /* 18006 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6074 /* 18010 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6075 /* 18014 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6076 /* 18018 */ // MIs[5] vC
6077 /* 18018 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6078 /* 18023 */ // MIs[5] vB
6079 /* 18023 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6080 /* 18028 */ // MIs[4] vA
6081 /* 18028 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6082 /* 18033 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6083 /* 18037 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6084 /* 18043 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6085 /* 18045 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6086 /* 18047 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6087 /* 18047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6088 /* 18050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6089 /* 18052 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
6090 /* 18056 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6091 /* 18060 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6092 /* 18064 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6093 /* 18074 */ GIR_RootConstrainSelectedInstOperands,
6094 /* 18075 */ // GIR_Coverage, 5080,
6095 /* 18075 */ GIR_EraseRootFromParent_Done,
6096 /* 18076 */ // Label 354: @18076
6097 /* 18076 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(18214), // Rule ID 5087 //
6098 /* 18081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6099 /* 18084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6100 /* 18088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6101 /* 18092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6102 /* 18096 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6103 /* 18100 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6104 /* 18104 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6105 /* 18108 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6106 /* 18112 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6107 /* 18116 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6108 /* 18120 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6109 /* 18124 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6110 /* 18128 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6111 /* 18132 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6112 /* 18136 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6113 /* 18140 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6114 /* 18144 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6115 /* 18148 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6116 /* 18152 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6117 /* 18156 */ // MIs[5] vA
6118 /* 18156 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6119 /* 18161 */ // MIs[5] vB
6120 /* 18161 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6121 /* 18166 */ // MIs[4] vC
6122 /* 18166 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6123 /* 18171 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6124 /* 18175 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6125 /* 18181 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6126 /* 18183 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6127 /* 18185 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6128 /* 18185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6129 /* 18188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6130 /* 18190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
6131 /* 18194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6132 /* 18198 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6133 /* 18202 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6134 /* 18212 */ GIR_RootConstrainSelectedInstOperands,
6135 /* 18213 */ // GIR_Coverage, 5087,
6136 /* 18213 */ GIR_EraseRootFromParent_Done,
6137 /* 18214 */ // Label 355: @18214
6138 /* 18214 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(18352), // Rule ID 5088 //
6139 /* 18219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6140 /* 18222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6141 /* 18226 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6142 /* 18230 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6143 /* 18234 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6144 /* 18238 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6145 /* 18242 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6146 /* 18246 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6147 /* 18250 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6148 /* 18254 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6149 /* 18258 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6150 /* 18262 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6151 /* 18266 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6152 /* 18270 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6153 /* 18274 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6154 /* 18278 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6155 /* 18282 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6156 /* 18286 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6157 /* 18290 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6158 /* 18294 */ // MIs[5] vB
6159 /* 18294 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6160 /* 18299 */ // MIs[5] vA
6161 /* 18299 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6162 /* 18304 */ // MIs[4] vC
6163 /* 18304 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6164 /* 18309 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6165 /* 18313 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6166 /* 18319 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6167 /* 18321 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6168 /* 18323 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6169 /* 18323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6170 /* 18326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6171 /* 18328 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
6172 /* 18332 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6173 /* 18336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6174 /* 18340 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6175 /* 18350 */ GIR_RootConstrainSelectedInstOperands,
6176 /* 18351 */ // GIR_Coverage, 5088,
6177 /* 18351 */ GIR_EraseRootFromParent_Done,
6178 /* 18352 */ // Label 356: @18352
6179 /* 18352 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(18490), // Rule ID 5089 //
6180 /* 18357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6181 /* 18360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6182 /* 18364 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6183 /* 18368 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6184 /* 18372 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6185 /* 18376 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6186 /* 18380 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6187 /* 18384 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6188 /* 18388 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6189 /* 18392 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6190 /* 18396 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6191 /* 18400 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6192 /* 18404 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6193 /* 18408 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6194 /* 18412 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6195 /* 18416 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6196 /* 18420 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6197 /* 18424 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6198 /* 18428 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6199 /* 18432 */ // MIs[5] vA
6200 /* 18432 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6201 /* 18437 */ // MIs[5] vC
6202 /* 18437 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6203 /* 18442 */ // MIs[4] vB
6204 /* 18442 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6205 /* 18447 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6206 /* 18451 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6207 /* 18457 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6208 /* 18459 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6209 /* 18461 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6210 /* 18461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6211 /* 18464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6212 /* 18466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
6213 /* 18470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6214 /* 18474 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6215 /* 18478 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6216 /* 18488 */ GIR_RootConstrainSelectedInstOperands,
6217 /* 18489 */ // GIR_Coverage, 5089,
6218 /* 18489 */ GIR_EraseRootFromParent_Done,
6219 /* 18490 */ // Label 357: @18490
6220 /* 18490 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(18628), // Rule ID 5090 //
6221 /* 18495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6222 /* 18498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6223 /* 18502 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6224 /* 18506 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6225 /* 18510 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6226 /* 18514 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6227 /* 18518 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6228 /* 18522 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6229 /* 18526 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6230 /* 18530 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6231 /* 18534 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6232 /* 18538 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6233 /* 18542 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6234 /* 18546 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6235 /* 18550 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6236 /* 18554 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6237 /* 18558 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6238 /* 18562 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6239 /* 18566 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6240 /* 18570 */ // MIs[5] vC
6241 /* 18570 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6242 /* 18575 */ // MIs[5] vA
6243 /* 18575 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6244 /* 18580 */ // MIs[4] vB
6245 /* 18580 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6246 /* 18585 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6247 /* 18589 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6248 /* 18595 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6249 /* 18597 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6250 /* 18599 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6251 /* 18599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6252 /* 18602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6253 /* 18604 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
6254 /* 18608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6255 /* 18612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6256 /* 18616 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6257 /* 18626 */ GIR_RootConstrainSelectedInstOperands,
6258 /* 18627 */ // GIR_Coverage, 5090,
6259 /* 18627 */ GIR_EraseRootFromParent_Done,
6260 /* 18628 */ // Label 358: @18628
6261 /* 18628 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(18766), // Rule ID 5091 //
6262 /* 18633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6263 /* 18636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6264 /* 18640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6265 /* 18644 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6266 /* 18648 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6267 /* 18652 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6268 /* 18656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6269 /* 18660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6270 /* 18664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6271 /* 18668 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6272 /* 18672 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6273 /* 18676 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6274 /* 18680 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6275 /* 18684 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6276 /* 18688 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6277 /* 18692 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6278 /* 18696 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6279 /* 18700 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6280 /* 18704 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6281 /* 18708 */ // MIs[5] vB
6282 /* 18708 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6283 /* 18713 */ // MIs[5] vC
6284 /* 18713 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6285 /* 18718 */ // MIs[4] vA
6286 /* 18718 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6287 /* 18723 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6288 /* 18727 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6289 /* 18733 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6290 /* 18735 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6291 /* 18737 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6292 /* 18737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6293 /* 18740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6294 /* 18742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
6295 /* 18746 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6296 /* 18750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6297 /* 18754 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6298 /* 18764 */ GIR_RootConstrainSelectedInstOperands,
6299 /* 18765 */ // GIR_Coverage, 5091,
6300 /* 18765 */ GIR_EraseRootFromParent_Done,
6301 /* 18766 */ // Label 359: @18766
6302 /* 18766 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(18904), // Rule ID 5092 //
6303 /* 18771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6304 /* 18774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6305 /* 18778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6306 /* 18782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6307 /* 18786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6308 /* 18790 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6309 /* 18794 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6310 /* 18798 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6311 /* 18802 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6312 /* 18806 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6313 /* 18810 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6314 /* 18814 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6315 /* 18818 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6316 /* 18822 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6317 /* 18826 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6318 /* 18830 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6319 /* 18834 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6320 /* 18838 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6321 /* 18842 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6322 /* 18846 */ // MIs[5] vC
6323 /* 18846 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6324 /* 18851 */ // MIs[5] vB
6325 /* 18851 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6326 /* 18856 */ // MIs[4] vA
6327 /* 18856 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6328 /* 18861 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6329 /* 18865 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6330 /* 18871 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6331 /* 18873 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6332 /* 18875 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6333 /* 18875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6334 /* 18878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6335 /* 18880 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
6336 /* 18884 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
6337 /* 18888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6338 /* 18892 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6339 /* 18902 */ GIR_RootConstrainSelectedInstOperands,
6340 /* 18903 */ // GIR_Coverage, 5092,
6341 /* 18903 */ GIR_EraseRootFromParent_Done,
6342 /* 18904 */ // Label 360: @18904
6343 /* 18904 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(19042), // Rule ID 5099 //
6344 /* 18909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6345 /* 18912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6346 /* 18916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6347 /* 18920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6348 /* 18924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6349 /* 18928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6350 /* 18932 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6351 /* 18936 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6352 /* 18940 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6353 /* 18944 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6354 /* 18948 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6355 /* 18952 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6356 /* 18956 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6357 /* 18960 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6358 /* 18964 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6359 /* 18968 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6360 /* 18972 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6361 /* 18976 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6362 /* 18980 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6363 /* 18984 */ // MIs[5] vA
6364 /* 18984 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6365 /* 18989 */ // MIs[5] vB
6366 /* 18989 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6367 /* 18994 */ // MIs[4] vC
6368 /* 18994 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6369 /* 18999 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6370 /* 19003 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6371 /* 19009 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6372 /* 19011 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6373 /* 19013 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6374 /* 19013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6375 /* 19016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6376 /* 19018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6377 /* 19022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
6378 /* 19026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6379 /* 19030 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6380 /* 19040 */ GIR_RootConstrainSelectedInstOperands,
6381 /* 19041 */ // GIR_Coverage, 5099,
6382 /* 19041 */ GIR_EraseRootFromParent_Done,
6383 /* 19042 */ // Label 361: @19042
6384 /* 19042 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(19180), // Rule ID 5100 //
6385 /* 19047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6386 /* 19050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6387 /* 19054 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6388 /* 19058 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6389 /* 19062 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6390 /* 19066 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6391 /* 19070 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6392 /* 19074 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6393 /* 19078 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6394 /* 19082 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6395 /* 19086 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6396 /* 19090 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6397 /* 19094 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6398 /* 19098 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6399 /* 19102 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6400 /* 19106 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6401 /* 19110 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6402 /* 19114 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6403 /* 19118 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6404 /* 19122 */ // MIs[5] vB
6405 /* 19122 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6406 /* 19127 */ // MIs[5] vA
6407 /* 19127 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6408 /* 19132 */ // MIs[4] vC
6409 /* 19132 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6410 /* 19137 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6411 /* 19141 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6412 /* 19147 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6413 /* 19149 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6414 /* 19151 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6415 /* 19151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6416 /* 19154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6417 /* 19156 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6418 /* 19160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
6419 /* 19164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6420 /* 19168 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6421 /* 19178 */ GIR_RootConstrainSelectedInstOperands,
6422 /* 19179 */ // GIR_Coverage, 5100,
6423 /* 19179 */ GIR_EraseRootFromParent_Done,
6424 /* 19180 */ // Label 362: @19180
6425 /* 19180 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(19318), // Rule ID 5101 //
6426 /* 19185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6427 /* 19188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6428 /* 19192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6429 /* 19196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6430 /* 19200 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6431 /* 19204 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6432 /* 19208 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6433 /* 19212 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6434 /* 19216 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6435 /* 19220 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6436 /* 19224 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6437 /* 19228 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6438 /* 19232 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6439 /* 19236 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6440 /* 19240 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6441 /* 19244 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6442 /* 19248 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6443 /* 19252 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6444 /* 19256 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6445 /* 19260 */ // MIs[5] vA
6446 /* 19260 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6447 /* 19265 */ // MIs[5] vC
6448 /* 19265 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6449 /* 19270 */ // MIs[4] vB
6450 /* 19270 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6451 /* 19275 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6452 /* 19279 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6453 /* 19285 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6454 /* 19287 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6455 /* 19289 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6456 /* 19289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6457 /* 19292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6458 /* 19294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6459 /* 19298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
6460 /* 19302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6461 /* 19306 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6462 /* 19316 */ GIR_RootConstrainSelectedInstOperands,
6463 /* 19317 */ // GIR_Coverage, 5101,
6464 /* 19317 */ GIR_EraseRootFromParent_Done,
6465 /* 19318 */ // Label 363: @19318
6466 /* 19318 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(19456), // Rule ID 5102 //
6467 /* 19323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6468 /* 19326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6469 /* 19330 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6470 /* 19334 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6471 /* 19338 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6472 /* 19342 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6473 /* 19346 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6474 /* 19350 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6475 /* 19354 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6476 /* 19358 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6477 /* 19362 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6478 /* 19366 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6479 /* 19370 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6480 /* 19374 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6481 /* 19378 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6482 /* 19382 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6483 /* 19386 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6484 /* 19390 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6485 /* 19394 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6486 /* 19398 */ // MIs[5] vC
6487 /* 19398 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6488 /* 19403 */ // MIs[5] vA
6489 /* 19403 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6490 /* 19408 */ // MIs[4] vB
6491 /* 19408 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6492 /* 19413 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6493 /* 19417 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6494 /* 19423 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6495 /* 19425 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6496 /* 19427 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6497 /* 19427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6498 /* 19430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6499 /* 19432 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6500 /* 19436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
6501 /* 19440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6502 /* 19444 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6503 /* 19454 */ GIR_RootConstrainSelectedInstOperands,
6504 /* 19455 */ // GIR_Coverage, 5102,
6505 /* 19455 */ GIR_EraseRootFromParent_Done,
6506 /* 19456 */ // Label 364: @19456
6507 /* 19456 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(19594), // Rule ID 5103 //
6508 /* 19461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6509 /* 19464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6510 /* 19468 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6511 /* 19472 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6512 /* 19476 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6513 /* 19480 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6514 /* 19484 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6515 /* 19488 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6516 /* 19492 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6517 /* 19496 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6518 /* 19500 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6519 /* 19504 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6520 /* 19508 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6521 /* 19512 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6522 /* 19516 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6523 /* 19520 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6524 /* 19524 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6525 /* 19528 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6526 /* 19532 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6527 /* 19536 */ // MIs[5] vB
6528 /* 19536 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6529 /* 19541 */ // MIs[5] vC
6530 /* 19541 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6531 /* 19546 */ // MIs[4] vA
6532 /* 19546 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6533 /* 19551 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6534 /* 19555 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6535 /* 19561 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6536 /* 19563 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6537 /* 19565 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6538 /* 19565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6539 /* 19568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6540 /* 19570 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6541 /* 19574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
6542 /* 19578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6543 /* 19582 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6544 /* 19592 */ GIR_RootConstrainSelectedInstOperands,
6545 /* 19593 */ // GIR_Coverage, 5103,
6546 /* 19593 */ GIR_EraseRootFromParent_Done,
6547 /* 19594 */ // Label 365: @19594
6548 /* 19594 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(19732), // Rule ID 5104 //
6549 /* 19599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6550 /* 19602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6551 /* 19606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6552 /* 19610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6553 /* 19614 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6554 /* 19618 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6555 /* 19622 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6556 /* 19626 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6557 /* 19630 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6558 /* 19634 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6559 /* 19638 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6560 /* 19642 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6561 /* 19646 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6562 /* 19650 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6563 /* 19654 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6564 /* 19658 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6565 /* 19662 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6566 /* 19666 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6567 /* 19670 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6568 /* 19674 */ // MIs[5] vC
6569 /* 19674 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6570 /* 19679 */ // MIs[5] vB
6571 /* 19679 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6572 /* 19684 */ // MIs[4] vA
6573 /* 19684 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6574 /* 19689 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6575 /* 19693 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6576 /* 19699 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6577 /* 19701 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6578 /* 19703 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6579 /* 19703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6580 /* 19706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6581 /* 19708 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6582 /* 19712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
6583 /* 19716 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6584 /* 19720 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6585 /* 19730 */ GIR_RootConstrainSelectedInstOperands,
6586 /* 19731 */ // GIR_Coverage, 5104,
6587 /* 19731 */ GIR_EraseRootFromParent_Done,
6588 /* 19732 */ // Label 366: @19732
6589 /* 19732 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(19870), // Rule ID 5110 //
6590 /* 19737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6591 /* 19740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6592 /* 19744 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6593 /* 19748 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6594 /* 19752 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6595 /* 19756 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6596 /* 19760 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6597 /* 19764 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6598 /* 19768 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6599 /* 19772 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6600 /* 19776 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6601 /* 19780 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6602 /* 19784 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6603 /* 19788 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6604 /* 19792 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6605 /* 19796 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6606 /* 19800 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6607 /* 19804 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6608 /* 19808 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6609 /* 19812 */ // MIs[5] vA
6610 /* 19812 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6611 /* 19817 */ // MIs[5] vB
6612 /* 19817 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6613 /* 19822 */ // MIs[4] vC
6614 /* 19822 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6615 /* 19827 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6616 /* 19831 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6617 /* 19837 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6618 /* 19839 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6619 /* 19841 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6620 /* 19841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6621 /* 19844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6622 /* 19846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6623 /* 19850 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6624 /* 19854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6625 /* 19858 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6626 /* 19868 */ GIR_RootConstrainSelectedInstOperands,
6627 /* 19869 */ // GIR_Coverage, 5110,
6628 /* 19869 */ GIR_EraseRootFromParent_Done,
6629 /* 19870 */ // Label 367: @19870
6630 /* 19870 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(20008), // Rule ID 5111 //
6631 /* 19875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6632 /* 19878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6633 /* 19882 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6634 /* 19886 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6635 /* 19890 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6636 /* 19894 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6637 /* 19898 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6638 /* 19902 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6639 /* 19906 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6640 /* 19910 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6641 /* 19914 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6642 /* 19918 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6643 /* 19922 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6644 /* 19926 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6645 /* 19930 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6646 /* 19934 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6647 /* 19938 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6648 /* 19942 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6649 /* 19946 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6650 /* 19950 */ // MIs[5] vB
6651 /* 19950 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6652 /* 19955 */ // MIs[5] vA
6653 /* 19955 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6654 /* 19960 */ // MIs[4] vC
6655 /* 19960 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6656 /* 19965 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6657 /* 19969 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6658 /* 19975 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6659 /* 19977 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6660 /* 19979 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6661 /* 19979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6662 /* 19982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6663 /* 19984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6664 /* 19988 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6665 /* 19992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6666 /* 19996 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6667 /* 20006 */ GIR_RootConstrainSelectedInstOperands,
6668 /* 20007 */ // GIR_Coverage, 5111,
6669 /* 20007 */ GIR_EraseRootFromParent_Done,
6670 /* 20008 */ // Label 368: @20008
6671 /* 20008 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(20146), // Rule ID 5112 //
6672 /* 20013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6673 /* 20016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6674 /* 20020 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6675 /* 20024 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6676 /* 20028 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6677 /* 20032 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6678 /* 20036 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6679 /* 20040 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6680 /* 20044 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6681 /* 20048 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6682 /* 20052 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6683 /* 20056 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6684 /* 20060 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6685 /* 20064 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6686 /* 20068 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6687 /* 20072 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6688 /* 20076 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6689 /* 20080 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6690 /* 20084 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6691 /* 20088 */ // MIs[5] vA
6692 /* 20088 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6693 /* 20093 */ // MIs[5] vC
6694 /* 20093 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6695 /* 20098 */ // MIs[4] vB
6696 /* 20098 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6697 /* 20103 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6698 /* 20107 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6699 /* 20113 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6700 /* 20115 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6701 /* 20117 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6702 /* 20117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6703 /* 20120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6704 /* 20122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6705 /* 20126 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6706 /* 20130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6707 /* 20134 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6708 /* 20144 */ GIR_RootConstrainSelectedInstOperands,
6709 /* 20145 */ // GIR_Coverage, 5112,
6710 /* 20145 */ GIR_EraseRootFromParent_Done,
6711 /* 20146 */ // Label 369: @20146
6712 /* 20146 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(20284), // Rule ID 5113 //
6713 /* 20151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6714 /* 20154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6715 /* 20158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6716 /* 20162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6717 /* 20166 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6718 /* 20170 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6719 /* 20174 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6720 /* 20178 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6721 /* 20182 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6722 /* 20186 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6723 /* 20190 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6724 /* 20194 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6725 /* 20198 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6726 /* 20202 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6727 /* 20206 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6728 /* 20210 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6729 /* 20214 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6730 /* 20218 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6731 /* 20222 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6732 /* 20226 */ // MIs[5] vC
6733 /* 20226 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6734 /* 20231 */ // MIs[5] vA
6735 /* 20231 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6736 /* 20236 */ // MIs[4] vB
6737 /* 20236 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6738 /* 20241 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6739 /* 20245 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6740 /* 20251 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6741 /* 20253 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6742 /* 20255 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6743 /* 20255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6744 /* 20258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6745 /* 20260 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6746 /* 20264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6747 /* 20268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6748 /* 20272 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6749 /* 20282 */ GIR_RootConstrainSelectedInstOperands,
6750 /* 20283 */ // GIR_Coverage, 5113,
6751 /* 20283 */ GIR_EraseRootFromParent_Done,
6752 /* 20284 */ // Label 370: @20284
6753 /* 20284 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(20422), // Rule ID 5114 //
6754 /* 20289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6755 /* 20292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6756 /* 20296 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6757 /* 20300 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6758 /* 20304 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6759 /* 20308 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6760 /* 20312 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6761 /* 20316 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6762 /* 20320 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6763 /* 20324 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6764 /* 20328 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6765 /* 20332 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6766 /* 20336 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6767 /* 20340 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6768 /* 20344 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6769 /* 20348 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6770 /* 20352 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6771 /* 20356 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6772 /* 20360 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6773 /* 20364 */ // MIs[5] vB
6774 /* 20364 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6775 /* 20369 */ // MIs[5] vC
6776 /* 20369 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6777 /* 20374 */ // MIs[4] vA
6778 /* 20374 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6779 /* 20379 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6780 /* 20383 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6781 /* 20389 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6782 /* 20391 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6783 /* 20393 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6784 /* 20393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6785 /* 20396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6786 /* 20398 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6787 /* 20402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6788 /* 20406 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6789 /* 20410 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6790 /* 20420 */ GIR_RootConstrainSelectedInstOperands,
6791 /* 20421 */ // GIR_Coverage, 5114,
6792 /* 20421 */ GIR_EraseRootFromParent_Done,
6793 /* 20422 */ // Label 371: @20422
6794 /* 20422 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(20560), // Rule ID 5115 //
6795 /* 20427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6796 /* 20430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6797 /* 20434 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6798 /* 20438 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6799 /* 20442 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6800 /* 20446 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6801 /* 20450 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6802 /* 20454 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6803 /* 20458 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6804 /* 20462 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6805 /* 20466 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6806 /* 20470 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6807 /* 20474 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6808 /* 20478 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6809 /* 20482 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6810 /* 20486 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6811 /* 20490 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
6812 /* 20494 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
6813 /* 20498 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6814 /* 20502 */ // MIs[5] vC
6815 /* 20502 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6816 /* 20507 */ // MIs[5] vB
6817 /* 20507 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6818 /* 20512 */ // MIs[4] vA
6819 /* 20512 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6820 /* 20517 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6821 /* 20521 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6822 /* 20527 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6823 /* 20529 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6824 /* 20531 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6825 /* 20531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6826 /* 20534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6827 /* 20536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6828 /* 20540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6829 /* 20544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
6830 /* 20548 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6831 /* 20558 */ GIR_RootConstrainSelectedInstOperands,
6832 /* 20559 */ // GIR_Coverage, 5115,
6833 /* 20559 */ GIR_EraseRootFromParent_Done,
6834 /* 20560 */ // Label 372: @20560
6835 /* 20560 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(20698), // Rule ID 3399 //
6836 /* 20565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6837 /* 20568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6838 /* 20572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6839 /* 20576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6840 /* 20580 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6841 /* 20584 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6842 /* 20588 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6843 /* 20592 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6844 /* 20596 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6845 /* 20600 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6846 /* 20604 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6847 /* 20608 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6848 /* 20612 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6849 /* 20616 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6850 /* 20620 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6851 /* 20624 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6852 /* 20628 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
6853 /* 20632 */ // MIs[4] vA
6854 /* 20632 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6855 /* 20637 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
6856 /* 20641 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6857 /* 20645 */ // MIs[5] vB
6858 /* 20645 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6859 /* 20650 */ // MIs[5] vC
6860 /* 20650 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6861 /* 20655 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6862 /* 20659 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6863 /* 20665 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6864 /* 20667 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6865 /* 20669 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6866 /* 20669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6867 /* 20672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6868 /* 20674 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
6869 /* 20678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
6870 /* 20682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
6871 /* 20686 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6872 /* 20696 */ GIR_RootConstrainSelectedInstOperands,
6873 /* 20697 */ // GIR_Coverage, 3399,
6874 /* 20697 */ GIR_EraseRootFromParent_Done,
6875 /* 20698 */ // Label 373: @20698
6876 /* 20698 */ GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(20836), // Rule ID 5057 //
6877 /* 20703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6878 /* 20706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6879 /* 20710 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6880 /* 20714 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6881 /* 20718 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6882 /* 20722 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6883 /* 20726 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6884 /* 20730 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6885 /* 20734 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6886 /* 20738 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6887 /* 20742 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6888 /* 20746 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6889 /* 20750 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6890 /* 20754 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6891 /* 20758 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6892 /* 20762 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6893 /* 20766 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
6894 /* 20770 */ // MIs[4] vC
6895 /* 20770 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6896 /* 20775 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
6897 /* 20779 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6898 /* 20783 */ // MIs[5] vA
6899 /* 20783 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6900 /* 20788 */ // MIs[5] vB
6901 /* 20788 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
6902 /* 20793 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6903 /* 20797 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6904 /* 20803 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6905 /* 20805 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6906 /* 20807 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6907 /* 20807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6908 /* 20810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6909 /* 20812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
6910 /* 20816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6911 /* 20820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
6912 /* 20824 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6913 /* 20834 */ GIR_RootConstrainSelectedInstOperands,
6914 /* 20835 */ // GIR_Coverage, 5057,
6915 /* 20835 */ GIR_EraseRootFromParent_Done,
6916 /* 20836 */ // Label 374: @20836
6917 /* 20836 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(20974), // Rule ID 5058 //
6918 /* 20841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6919 /* 20844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6920 /* 20848 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6921 /* 20852 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6922 /* 20856 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6923 /* 20860 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6924 /* 20864 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6925 /* 20868 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6926 /* 20872 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6927 /* 20876 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6928 /* 20880 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6929 /* 20884 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6930 /* 20888 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6931 /* 20892 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6932 /* 20896 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6933 /* 20900 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6934 /* 20904 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
6935 /* 20908 */ // MIs[4] vC
6936 /* 20908 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
6937 /* 20913 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
6938 /* 20917 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6939 /* 20921 */ // MIs[5] vB
6940 /* 20921 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6941 /* 20926 */ // MIs[5] vA
6942 /* 20926 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
6943 /* 20931 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6944 /* 20935 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6945 /* 20941 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6946 /* 20943 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6947 /* 20945 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6948 /* 20945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6949 /* 20948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6950 /* 20950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
6951 /* 20954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6952 /* 20958 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
6953 /* 20962 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6954 /* 20972 */ GIR_RootConstrainSelectedInstOperands,
6955 /* 20973 */ // GIR_Coverage, 5058,
6956 /* 20973 */ GIR_EraseRootFromParent_Done,
6957 /* 20974 */ // Label 375: @20974
6958 /* 20974 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(21112), // Rule ID 5059 //
6959 /* 20979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
6960 /* 20982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
6961 /* 20986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6962 /* 20990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
6963 /* 20994 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6964 /* 20998 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6965 /* 21002 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6966 /* 21006 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
6967 /* 21010 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6968 /* 21014 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
6969 /* 21018 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6970 /* 21022 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
6971 /* 21026 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
6972 /* 21030 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
6973 /* 21034 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6974 /* 21038 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
6975 /* 21042 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
6976 /* 21046 */ // MIs[4] vB
6977 /* 21046 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
6978 /* 21051 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
6979 /* 21055 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
6980 /* 21059 */ // MIs[5] vA
6981 /* 21059 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6982 /* 21064 */ // MIs[5] vC
6983 /* 21064 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
6984 /* 21069 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
6985 /* 21073 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
6986 /* 21079 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
6987 /* 21081 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
6988 /* 21083 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
6989 /* 21083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
6990 /* 21086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
6991 /* 21088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
6992 /* 21092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
6993 /* 21096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
6994 /* 21100 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
6995 /* 21110 */ GIR_RootConstrainSelectedInstOperands,
6996 /* 21111 */ // GIR_Coverage, 5059,
6997 /* 21111 */ GIR_EraseRootFromParent_Done,
6998 /* 21112 */ // Label 376: @21112
6999 /* 21112 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(21250), // Rule ID 5060 //
7000 /* 21117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7001 /* 21120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7002 /* 21124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7003 /* 21128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7004 /* 21132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7005 /* 21136 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7006 /* 21140 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7007 /* 21144 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7008 /* 21148 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7009 /* 21152 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7010 /* 21156 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7011 /* 21160 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7012 /* 21164 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7013 /* 21168 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7014 /* 21172 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7015 /* 21176 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7016 /* 21180 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7017 /* 21184 */ // MIs[4] vB
7018 /* 21184 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7019 /* 21189 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7020 /* 21193 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7021 /* 21197 */ // MIs[5] vC
7022 /* 21197 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7023 /* 21202 */ // MIs[5] vA
7024 /* 21202 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
7025 /* 21207 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7026 /* 21211 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7027 /* 21217 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7028 /* 21219 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7029 /* 21221 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7030 /* 21221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7031 /* 21224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7032 /* 21226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7033 /* 21230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
7034 /* 21234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7035 /* 21238 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7036 /* 21248 */ GIR_RootConstrainSelectedInstOperands,
7037 /* 21249 */ // GIR_Coverage, 5060,
7038 /* 21249 */ GIR_EraseRootFromParent_Done,
7039 /* 21250 */ // Label 377: @21250
7040 /* 21250 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(21388), // Rule ID 5061 //
7041 /* 21255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7042 /* 21258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7043 /* 21262 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7044 /* 21266 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7045 /* 21270 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7046 /* 21274 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7047 /* 21278 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7048 /* 21282 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7049 /* 21286 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7050 /* 21290 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7051 /* 21294 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7052 /* 21298 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7053 /* 21302 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7054 /* 21306 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7055 /* 21310 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7056 /* 21314 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7057 /* 21318 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7058 /* 21322 */ // MIs[4] vA
7059 /* 21322 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7060 /* 21327 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7061 /* 21331 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7062 /* 21335 */ // MIs[5] vB
7063 /* 21335 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7064 /* 21340 */ // MIs[5] vC
7065 /* 21340 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
7066 /* 21345 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7067 /* 21349 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7068 /* 21355 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7069 /* 21357 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7070 /* 21359 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7071 /* 21359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7072 /* 21362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7073 /* 21364 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7074 /* 21368 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
7075 /* 21372 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7076 /* 21376 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7077 /* 21386 */ GIR_RootConstrainSelectedInstOperands,
7078 /* 21387 */ // GIR_Coverage, 5061,
7079 /* 21387 */ GIR_EraseRootFromParent_Done,
7080 /* 21388 */ // Label 378: @21388
7081 /* 21388 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(21526), // Rule ID 5062 //
7082 /* 21393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7083 /* 21396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7084 /* 21400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7085 /* 21404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7086 /* 21408 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7087 /* 21412 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7088 /* 21416 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7089 /* 21420 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7090 /* 21424 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7091 /* 21428 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7092 /* 21432 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7093 /* 21436 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7094 /* 21440 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7095 /* 21444 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7096 /* 21448 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7097 /* 21452 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7098 /* 21456 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7099 /* 21460 */ // MIs[4] vA
7100 /* 21460 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7101 /* 21465 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7102 /* 21469 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7103 /* 21473 */ // MIs[5] vC
7104 /* 21473 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7105 /* 21478 */ // MIs[5] vB
7106 /* 21478 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
7107 /* 21483 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7108 /* 21487 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7109 /* 21493 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7110 /* 21495 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7111 /* 21497 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7112 /* 21497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7113 /* 21500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7114 /* 21502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7115 /* 21506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
7116 /* 21510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7117 /* 21514 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7118 /* 21524 */ GIR_RootConstrainSelectedInstOperands,
7119 /* 21525 */ // GIR_Coverage, 5062,
7120 /* 21525 */ GIR_EraseRootFromParent_Done,
7121 /* 21526 */ // Label 379: @21526
7122 /* 21526 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(21664), // Rule ID 5069 //
7123 /* 21531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7124 /* 21534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7125 /* 21538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7126 /* 21542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7127 /* 21546 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7128 /* 21550 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7129 /* 21554 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7130 /* 21558 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7131 /* 21562 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7132 /* 21566 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7133 /* 21570 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7134 /* 21574 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7135 /* 21578 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7136 /* 21582 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7137 /* 21586 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7138 /* 21590 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7139 /* 21594 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7140 /* 21598 */ // MIs[4] vC
7141 /* 21598 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7142 /* 21603 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7143 /* 21607 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7144 /* 21611 */ // MIs[5] vA
7145 /* 21611 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7146 /* 21616 */ // MIs[5] vB
7147 /* 21616 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
7148 /* 21621 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7149 /* 21625 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7150 /* 21631 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7151 /* 21633 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7152 /* 21635 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7153 /* 21635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7154 /* 21638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7155 /* 21640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7156 /* 21644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7157 /* 21648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7158 /* 21652 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7159 /* 21662 */ GIR_RootConstrainSelectedInstOperands,
7160 /* 21663 */ // GIR_Coverage, 5069,
7161 /* 21663 */ GIR_EraseRootFromParent_Done,
7162 /* 21664 */ // Label 380: @21664
7163 /* 21664 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(21802), // Rule ID 5070 //
7164 /* 21669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7165 /* 21672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7166 /* 21676 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7167 /* 21680 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7168 /* 21684 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7169 /* 21688 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7170 /* 21692 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7171 /* 21696 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7172 /* 21700 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7173 /* 21704 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7174 /* 21708 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7175 /* 21712 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7176 /* 21716 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7177 /* 21720 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7178 /* 21724 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7179 /* 21728 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7180 /* 21732 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7181 /* 21736 */ // MIs[4] vC
7182 /* 21736 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7183 /* 21741 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7184 /* 21745 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7185 /* 21749 */ // MIs[5] vB
7186 /* 21749 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7187 /* 21754 */ // MIs[5] vA
7188 /* 21754 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
7189 /* 21759 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7190 /* 21763 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7191 /* 21769 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7192 /* 21771 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7193 /* 21773 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7194 /* 21773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7195 /* 21776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7196 /* 21778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7197 /* 21782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7198 /* 21786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7199 /* 21790 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7200 /* 21800 */ GIR_RootConstrainSelectedInstOperands,
7201 /* 21801 */ // GIR_Coverage, 5070,
7202 /* 21801 */ GIR_EraseRootFromParent_Done,
7203 /* 21802 */ // Label 381: @21802
7204 /* 21802 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(21940), // Rule ID 5071 //
7205 /* 21807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7206 /* 21810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7207 /* 21814 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7208 /* 21818 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7209 /* 21822 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7210 /* 21826 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7211 /* 21830 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7212 /* 21834 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7213 /* 21838 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7214 /* 21842 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7215 /* 21846 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7216 /* 21850 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7217 /* 21854 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7218 /* 21858 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7219 /* 21862 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7220 /* 21866 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7221 /* 21870 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7222 /* 21874 */ // MIs[4] vB
7223 /* 21874 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7224 /* 21879 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7225 /* 21883 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7226 /* 21887 */ // MIs[5] vA
7227 /* 21887 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7228 /* 21892 */ // MIs[5] vC
7229 /* 21892 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
7230 /* 21897 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7231 /* 21901 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7232 /* 21907 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7233 /* 21909 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7234 /* 21911 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7235 /* 21911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7236 /* 21914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7237 /* 21916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7238 /* 21920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7239 /* 21924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7240 /* 21928 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7241 /* 21938 */ GIR_RootConstrainSelectedInstOperands,
7242 /* 21939 */ // GIR_Coverage, 5071,
7243 /* 21939 */ GIR_EraseRootFromParent_Done,
7244 /* 21940 */ // Label 382: @21940
7245 /* 21940 */ GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(22078), // Rule ID 5072 //
7246 /* 21945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7247 /* 21948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7248 /* 21952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7249 /* 21956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7250 /* 21960 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7251 /* 21964 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7252 /* 21968 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7253 /* 21972 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7254 /* 21976 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7255 /* 21980 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7256 /* 21984 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7257 /* 21988 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7258 /* 21992 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7259 /* 21996 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7260 /* 22000 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7261 /* 22004 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7262 /* 22008 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7263 /* 22012 */ // MIs[4] vB
7264 /* 22012 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7265 /* 22017 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7266 /* 22021 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7267 /* 22025 */ // MIs[5] vC
7268 /* 22025 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7269 /* 22030 */ // MIs[5] vA
7270 /* 22030 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
7271 /* 22035 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7272 /* 22039 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7273 /* 22045 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7274 /* 22047 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7275 /* 22049 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7276 /* 22049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7277 /* 22052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7278 /* 22054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7279 /* 22058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7280 /* 22062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7281 /* 22066 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7282 /* 22076 */ GIR_RootConstrainSelectedInstOperands,
7283 /* 22077 */ // GIR_Coverage, 5072,
7284 /* 22077 */ GIR_EraseRootFromParent_Done,
7285 /* 22078 */ // Label 383: @22078
7286 /* 22078 */ GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(22216), // Rule ID 5073 //
7287 /* 22083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7288 /* 22086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7289 /* 22090 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7290 /* 22094 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7291 /* 22098 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7292 /* 22102 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7293 /* 22106 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7294 /* 22110 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7295 /* 22114 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7296 /* 22118 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7297 /* 22122 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7298 /* 22126 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7299 /* 22130 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7300 /* 22134 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7301 /* 22138 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7302 /* 22142 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7303 /* 22146 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7304 /* 22150 */ // MIs[4] vA
7305 /* 22150 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7306 /* 22155 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7307 /* 22159 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7308 /* 22163 */ // MIs[5] vB
7309 /* 22163 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7310 /* 22168 */ // MIs[5] vC
7311 /* 22168 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
7312 /* 22173 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7313 /* 22177 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7314 /* 22183 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7315 /* 22185 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7316 /* 22187 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7317 /* 22187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7318 /* 22190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7319 /* 22192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7320 /* 22196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7321 /* 22200 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7322 /* 22204 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7323 /* 22214 */ GIR_RootConstrainSelectedInstOperands,
7324 /* 22215 */ // GIR_Coverage, 5073,
7325 /* 22215 */ GIR_EraseRootFromParent_Done,
7326 /* 22216 */ // Label 384: @22216
7327 /* 22216 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(22354), // Rule ID 5074 //
7328 /* 22221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7329 /* 22224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7330 /* 22228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7331 /* 22232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7332 /* 22236 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7333 /* 22240 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7334 /* 22244 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7335 /* 22248 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7336 /* 22252 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7337 /* 22256 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7338 /* 22260 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7339 /* 22264 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7340 /* 22268 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7341 /* 22272 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7342 /* 22276 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7343 /* 22280 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7344 /* 22284 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7345 /* 22288 */ // MIs[4] vA
7346 /* 22288 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7347 /* 22293 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7348 /* 22297 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7349 /* 22301 */ // MIs[5] vC
7350 /* 22301 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7351 /* 22306 */ // MIs[5] vB
7352 /* 22306 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
7353 /* 22311 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7354 /* 22315 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7355 /* 22321 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7356 /* 22323 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7357 /* 22325 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7358 /* 22325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7359 /* 22328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7360 /* 22330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7361 /* 22334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7362 /* 22338 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
7363 /* 22342 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7364 /* 22352 */ GIR_RootConstrainSelectedInstOperands,
7365 /* 22353 */ // GIR_Coverage, 5074,
7366 /* 22353 */ GIR_EraseRootFromParent_Done,
7367 /* 22354 */ // Label 385: @22354
7368 /* 22354 */ GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(22492), // Rule ID 5081 //
7369 /* 22359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7370 /* 22362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7371 /* 22366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7372 /* 22370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7373 /* 22374 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7374 /* 22378 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7375 /* 22382 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7376 /* 22386 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7377 /* 22390 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7378 /* 22394 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7379 /* 22398 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7380 /* 22402 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7381 /* 22406 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7382 /* 22410 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7383 /* 22414 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7384 /* 22418 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7385 /* 22422 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7386 /* 22426 */ // MIs[4] vC
7387 /* 22426 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7388 /* 22431 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7389 /* 22435 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7390 /* 22439 */ // MIs[5] vA
7391 /* 22439 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7392 /* 22444 */ // MIs[5] vB
7393 /* 22444 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
7394 /* 22449 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7395 /* 22453 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7396 /* 22459 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7397 /* 22461 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7398 /* 22463 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7399 /* 22463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7400 /* 22466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7401 /* 22468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7402 /* 22472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7403 /* 22476 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7404 /* 22480 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7405 /* 22490 */ GIR_RootConstrainSelectedInstOperands,
7406 /* 22491 */ // GIR_Coverage, 5081,
7407 /* 22491 */ GIR_EraseRootFromParent_Done,
7408 /* 22492 */ // Label 386: @22492
7409 /* 22492 */ GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(22630), // Rule ID 5082 //
7410 /* 22497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7411 /* 22500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7412 /* 22504 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7413 /* 22508 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7414 /* 22512 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7415 /* 22516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7416 /* 22520 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7417 /* 22524 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7418 /* 22528 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7419 /* 22532 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7420 /* 22536 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7421 /* 22540 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7422 /* 22544 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7423 /* 22548 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7424 /* 22552 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7425 /* 22556 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7426 /* 22560 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7427 /* 22564 */ // MIs[4] vC
7428 /* 22564 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7429 /* 22569 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7430 /* 22573 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7431 /* 22577 */ // MIs[5] vB
7432 /* 22577 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7433 /* 22582 */ // MIs[5] vA
7434 /* 22582 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
7435 /* 22587 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7436 /* 22591 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7437 /* 22597 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7438 /* 22599 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7439 /* 22601 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7440 /* 22601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7441 /* 22604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7442 /* 22606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7443 /* 22610 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7444 /* 22614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7445 /* 22618 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7446 /* 22628 */ GIR_RootConstrainSelectedInstOperands,
7447 /* 22629 */ // GIR_Coverage, 5082,
7448 /* 22629 */ GIR_EraseRootFromParent_Done,
7449 /* 22630 */ // Label 387: @22630
7450 /* 22630 */ GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(22768), // Rule ID 5083 //
7451 /* 22635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7452 /* 22638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7453 /* 22642 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7454 /* 22646 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7455 /* 22650 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7456 /* 22654 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7457 /* 22658 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7458 /* 22662 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7459 /* 22666 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7460 /* 22670 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7461 /* 22674 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7462 /* 22678 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7463 /* 22682 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7464 /* 22686 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7465 /* 22690 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7466 /* 22694 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7467 /* 22698 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7468 /* 22702 */ // MIs[4] vB
7469 /* 22702 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7470 /* 22707 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7471 /* 22711 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7472 /* 22715 */ // MIs[5] vA
7473 /* 22715 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7474 /* 22720 */ // MIs[5] vC
7475 /* 22720 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
7476 /* 22725 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7477 /* 22729 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7478 /* 22735 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7479 /* 22737 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7480 /* 22739 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7481 /* 22739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7482 /* 22742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7483 /* 22744 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7484 /* 22748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7485 /* 22752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7486 /* 22756 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7487 /* 22766 */ GIR_RootConstrainSelectedInstOperands,
7488 /* 22767 */ // GIR_Coverage, 5083,
7489 /* 22767 */ GIR_EraseRootFromParent_Done,
7490 /* 22768 */ // Label 388: @22768
7491 /* 22768 */ GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(22906), // Rule ID 5084 //
7492 /* 22773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7493 /* 22776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7494 /* 22780 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7495 /* 22784 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7496 /* 22788 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7497 /* 22792 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7498 /* 22796 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7499 /* 22800 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7500 /* 22804 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7501 /* 22808 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7502 /* 22812 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7503 /* 22816 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7504 /* 22820 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7505 /* 22824 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7506 /* 22828 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7507 /* 22832 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7508 /* 22836 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7509 /* 22840 */ // MIs[4] vB
7510 /* 22840 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7511 /* 22845 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7512 /* 22849 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7513 /* 22853 */ // MIs[5] vC
7514 /* 22853 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7515 /* 22858 */ // MIs[5] vA
7516 /* 22858 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
7517 /* 22863 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7518 /* 22867 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7519 /* 22873 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7520 /* 22875 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7521 /* 22877 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7522 /* 22877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7523 /* 22880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7524 /* 22882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7525 /* 22886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7526 /* 22890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7527 /* 22894 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7528 /* 22904 */ GIR_RootConstrainSelectedInstOperands,
7529 /* 22905 */ // GIR_Coverage, 5084,
7530 /* 22905 */ GIR_EraseRootFromParent_Done,
7531 /* 22906 */ // Label 389: @22906
7532 /* 22906 */ GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(23044), // Rule ID 5085 //
7533 /* 22911 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7534 /* 22914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7535 /* 22918 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7536 /* 22922 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7537 /* 22926 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7538 /* 22930 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7539 /* 22934 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7540 /* 22938 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7541 /* 22942 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7542 /* 22946 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7543 /* 22950 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7544 /* 22954 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7545 /* 22958 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7546 /* 22962 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7547 /* 22966 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7548 /* 22970 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7549 /* 22974 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7550 /* 22978 */ // MIs[4] vA
7551 /* 22978 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7552 /* 22983 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7553 /* 22987 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7554 /* 22991 */ // MIs[5] vB
7555 /* 22991 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7556 /* 22996 */ // MIs[5] vC
7557 /* 22996 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
7558 /* 23001 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7559 /* 23005 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7560 /* 23011 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7561 /* 23013 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7562 /* 23015 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7563 /* 23015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7564 /* 23018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7565 /* 23020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7566 /* 23024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7567 /* 23028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7568 /* 23032 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7569 /* 23042 */ GIR_RootConstrainSelectedInstOperands,
7570 /* 23043 */ // GIR_Coverage, 5085,
7571 /* 23043 */ GIR_EraseRootFromParent_Done,
7572 /* 23044 */ // Label 390: @23044
7573 /* 23044 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(23182), // Rule ID 5086 //
7574 /* 23049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7575 /* 23052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7576 /* 23056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7577 /* 23060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7578 /* 23064 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7579 /* 23068 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7580 /* 23072 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7581 /* 23076 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7582 /* 23080 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7583 /* 23084 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7584 /* 23088 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7585 /* 23092 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7586 /* 23096 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7587 /* 23100 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7588 /* 23104 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7589 /* 23108 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7590 /* 23112 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7591 /* 23116 */ // MIs[4] vA
7592 /* 23116 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7593 /* 23121 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7594 /* 23125 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7595 /* 23129 */ // MIs[5] vC
7596 /* 23129 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7597 /* 23134 */ // MIs[5] vB
7598 /* 23134 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
7599 /* 23139 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7600 /* 23143 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7601 /* 23149 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7602 /* 23151 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7603 /* 23153 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7604 /* 23153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7605 /* 23156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7606 /* 23158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
7607 /* 23162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7608 /* 23166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7609 /* 23170 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7610 /* 23180 */ GIR_RootConstrainSelectedInstOperands,
7611 /* 23181 */ // GIR_Coverage, 5086,
7612 /* 23181 */ GIR_EraseRootFromParent_Done,
7613 /* 23182 */ // Label 391: @23182
7614 /* 23182 */ GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(23320), // Rule ID 5093 //
7615 /* 23187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7616 /* 23190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7617 /* 23194 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7618 /* 23198 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7619 /* 23202 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7620 /* 23206 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7621 /* 23210 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7622 /* 23214 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7623 /* 23218 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7624 /* 23222 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7625 /* 23226 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7626 /* 23230 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7627 /* 23234 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7628 /* 23238 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7629 /* 23242 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7630 /* 23246 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7631 /* 23250 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7632 /* 23254 */ // MIs[4] vC
7633 /* 23254 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7634 /* 23259 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7635 /* 23263 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7636 /* 23267 */ // MIs[5] vA
7637 /* 23267 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7638 /* 23272 */ // MIs[5] vB
7639 /* 23272 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
7640 /* 23277 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7641 /* 23281 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7642 /* 23287 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7643 /* 23289 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7644 /* 23291 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7645 /* 23291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7646 /* 23294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7647 /* 23296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7648 /* 23300 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7649 /* 23304 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
7650 /* 23308 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7651 /* 23318 */ GIR_RootConstrainSelectedInstOperands,
7652 /* 23319 */ // GIR_Coverage, 5093,
7653 /* 23319 */ GIR_EraseRootFromParent_Done,
7654 /* 23320 */ // Label 392: @23320
7655 /* 23320 */ GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(23458), // Rule ID 5094 //
7656 /* 23325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7657 /* 23328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7658 /* 23332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7659 /* 23336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7660 /* 23340 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7661 /* 23344 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7662 /* 23348 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7663 /* 23352 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7664 /* 23356 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7665 /* 23360 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7666 /* 23364 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7667 /* 23368 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7668 /* 23372 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7669 /* 23376 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7670 /* 23380 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7671 /* 23384 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7672 /* 23388 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7673 /* 23392 */ // MIs[4] vC
7674 /* 23392 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7675 /* 23397 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7676 /* 23401 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7677 /* 23405 */ // MIs[5] vB
7678 /* 23405 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7679 /* 23410 */ // MIs[5] vA
7680 /* 23410 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
7681 /* 23415 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7682 /* 23419 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7683 /* 23425 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7684 /* 23427 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7685 /* 23429 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7686 /* 23429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7687 /* 23432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7688 /* 23434 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7689 /* 23438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7690 /* 23442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
7691 /* 23446 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7692 /* 23456 */ GIR_RootConstrainSelectedInstOperands,
7693 /* 23457 */ // GIR_Coverage, 5094,
7694 /* 23457 */ GIR_EraseRootFromParent_Done,
7695 /* 23458 */ // Label 393: @23458
7696 /* 23458 */ GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(23596), // Rule ID 5095 //
7697 /* 23463 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7698 /* 23466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7699 /* 23470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7700 /* 23474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7701 /* 23478 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7702 /* 23482 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7703 /* 23486 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7704 /* 23490 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7705 /* 23494 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7706 /* 23498 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7707 /* 23502 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7708 /* 23506 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7709 /* 23510 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7710 /* 23514 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7711 /* 23518 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7712 /* 23522 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7713 /* 23526 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7714 /* 23530 */ // MIs[4] vB
7715 /* 23530 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7716 /* 23535 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7717 /* 23539 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7718 /* 23543 */ // MIs[5] vA
7719 /* 23543 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7720 /* 23548 */ // MIs[5] vC
7721 /* 23548 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
7722 /* 23553 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7723 /* 23557 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7724 /* 23563 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7725 /* 23565 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7726 /* 23567 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7727 /* 23567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7728 /* 23570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7729 /* 23572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7730 /* 23576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7731 /* 23580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
7732 /* 23584 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7733 /* 23594 */ GIR_RootConstrainSelectedInstOperands,
7734 /* 23595 */ // GIR_Coverage, 5095,
7735 /* 23595 */ GIR_EraseRootFromParent_Done,
7736 /* 23596 */ // Label 394: @23596
7737 /* 23596 */ GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(23734), // Rule ID 5096 //
7738 /* 23601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7739 /* 23604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7740 /* 23608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7741 /* 23612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7742 /* 23616 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7743 /* 23620 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7744 /* 23624 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7745 /* 23628 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7746 /* 23632 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7747 /* 23636 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7748 /* 23640 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7749 /* 23644 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7750 /* 23648 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7751 /* 23652 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7752 /* 23656 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7753 /* 23660 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7754 /* 23664 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7755 /* 23668 */ // MIs[4] vB
7756 /* 23668 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7757 /* 23673 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7758 /* 23677 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7759 /* 23681 */ // MIs[5] vC
7760 /* 23681 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7761 /* 23686 */ // MIs[5] vA
7762 /* 23686 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
7763 /* 23691 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7764 /* 23695 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7765 /* 23701 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7766 /* 23703 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7767 /* 23705 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7768 /* 23705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7769 /* 23708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7770 /* 23710 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7771 /* 23714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7772 /* 23718 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
7773 /* 23722 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7774 /* 23732 */ GIR_RootConstrainSelectedInstOperands,
7775 /* 23733 */ // GIR_Coverage, 5096,
7776 /* 23733 */ GIR_EraseRootFromParent_Done,
7777 /* 23734 */ // Label 395: @23734
7778 /* 23734 */ GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(23872), // Rule ID 5097 //
7779 /* 23739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7780 /* 23742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7781 /* 23746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7782 /* 23750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7783 /* 23754 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7784 /* 23758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7785 /* 23762 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7786 /* 23766 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7787 /* 23770 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7788 /* 23774 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7789 /* 23778 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7790 /* 23782 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7791 /* 23786 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7792 /* 23790 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7793 /* 23794 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7794 /* 23798 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7795 /* 23802 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7796 /* 23806 */ // MIs[4] vA
7797 /* 23806 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7798 /* 23811 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7799 /* 23815 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7800 /* 23819 */ // MIs[5] vB
7801 /* 23819 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7802 /* 23824 */ // MIs[5] vC
7803 /* 23824 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
7804 /* 23829 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7805 /* 23833 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7806 /* 23839 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7807 /* 23841 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7808 /* 23843 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7809 /* 23843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7810 /* 23846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7811 /* 23848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7812 /* 23852 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7813 /* 23856 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
7814 /* 23860 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7815 /* 23870 */ GIR_RootConstrainSelectedInstOperands,
7816 /* 23871 */ // GIR_Coverage, 5097,
7817 /* 23871 */ GIR_EraseRootFromParent_Done,
7818 /* 23872 */ // Label 396: @23872
7819 /* 23872 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(24010), // Rule ID 5098 //
7820 /* 23877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7821 /* 23880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7822 /* 23884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7823 /* 23888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7824 /* 23892 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7825 /* 23896 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7826 /* 23900 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7827 /* 23904 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7828 /* 23908 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7829 /* 23912 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7830 /* 23916 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7831 /* 23920 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7832 /* 23924 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7833 /* 23928 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7834 /* 23932 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7835 /* 23936 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7836 /* 23940 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7837 /* 23944 */ // MIs[4] vA
7838 /* 23944 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7839 /* 23949 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7840 /* 23953 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7841 /* 23957 */ // MIs[5] vC
7842 /* 23957 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7843 /* 23962 */ // MIs[5] vB
7844 /* 23962 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
7845 /* 23967 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7846 /* 23971 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7847 /* 23977 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7848 /* 23979 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7849 /* 23981 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7850 /* 23981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7851 /* 23984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7852 /* 23986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
7853 /* 23990 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
7854 /* 23994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
7855 /* 23998 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7856 /* 24008 */ GIR_RootConstrainSelectedInstOperands,
7857 /* 24009 */ // GIR_Coverage, 5098,
7858 /* 24009 */ GIR_EraseRootFromParent_Done,
7859 /* 24010 */ // Label 397: @24010
7860 /* 24010 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(24148), // Rule ID 5105 //
7861 /* 24015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7862 /* 24018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7863 /* 24022 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7864 /* 24026 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7865 /* 24030 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7866 /* 24034 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7867 /* 24038 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7868 /* 24042 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7869 /* 24046 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7870 /* 24050 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7871 /* 24054 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7872 /* 24058 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7873 /* 24062 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7874 /* 24066 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7875 /* 24070 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7876 /* 24074 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7877 /* 24078 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7878 /* 24082 */ // MIs[4] vC
7879 /* 24082 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7880 /* 24087 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7881 /* 24091 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7882 /* 24095 */ // MIs[5] vA
7883 /* 24095 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7884 /* 24100 */ // MIs[5] vB
7885 /* 24100 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
7886 /* 24105 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7887 /* 24109 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7888 /* 24115 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7889 /* 24117 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7890 /* 24119 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7891 /* 24119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7892 /* 24122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7893 /* 24124 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
7894 /* 24128 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7895 /* 24132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7896 /* 24136 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7897 /* 24146 */ GIR_RootConstrainSelectedInstOperands,
7898 /* 24147 */ // GIR_Coverage, 5105,
7899 /* 24147 */ GIR_EraseRootFromParent_Done,
7900 /* 24148 */ // Label 398: @24148
7901 /* 24148 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(24286), // Rule ID 5106 //
7902 /* 24153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7903 /* 24156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7904 /* 24160 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7905 /* 24164 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7906 /* 24168 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7907 /* 24172 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7908 /* 24176 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7909 /* 24180 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7910 /* 24184 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7911 /* 24188 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7912 /* 24192 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7913 /* 24196 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7914 /* 24200 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7915 /* 24204 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7916 /* 24208 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7917 /* 24212 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7918 /* 24216 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7919 /* 24220 */ // MIs[4] vC
7920 /* 24220 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
7921 /* 24225 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7922 /* 24229 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7923 /* 24233 */ // MIs[5] vB
7924 /* 24233 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7925 /* 24238 */ // MIs[5] vA
7926 /* 24238 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
7927 /* 24243 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7928 /* 24247 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7929 /* 24253 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7930 /* 24255 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7931 /* 24257 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7932 /* 24257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7933 /* 24260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7934 /* 24262 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
7935 /* 24266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7936 /* 24270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7937 /* 24274 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7938 /* 24284 */ GIR_RootConstrainSelectedInstOperands,
7939 /* 24285 */ // GIR_Coverage, 5106,
7940 /* 24285 */ GIR_EraseRootFromParent_Done,
7941 /* 24286 */ // Label 399: @24286
7942 /* 24286 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(24424), // Rule ID 5107 //
7943 /* 24291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7944 /* 24294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7945 /* 24298 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7946 /* 24302 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7947 /* 24306 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7948 /* 24310 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7949 /* 24314 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7950 /* 24318 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7951 /* 24322 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7952 /* 24326 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7953 /* 24330 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7954 /* 24334 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7955 /* 24338 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7956 /* 24342 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7957 /* 24346 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7958 /* 24350 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
7959 /* 24354 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
7960 /* 24358 */ // MIs[4] vB
7961 /* 24358 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7962 /* 24363 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
7963 /* 24367 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
7964 /* 24371 */ // MIs[5] vA
7965 /* 24371 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
7966 /* 24376 */ // MIs[5] vC
7967 /* 24376 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
7968 /* 24381 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
7969 /* 24385 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
7970 /* 24391 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
7971 /* 24393 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
7972 /* 24395 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
7973 /* 24395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
7974 /* 24398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
7975 /* 24400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
7976 /* 24404 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
7977 /* 24408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
7978 /* 24412 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
7979 /* 24422 */ GIR_RootConstrainSelectedInstOperands,
7980 /* 24423 */ // GIR_Coverage, 5107,
7981 /* 24423 */ GIR_EraseRootFromParent_Done,
7982 /* 24424 */ // Label 400: @24424
7983 /* 24424 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(24562), // Rule ID 5108 //
7984 /* 24429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
7985 /* 24432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
7986 /* 24436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7987 /* 24440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7988 /* 24444 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
7989 /* 24448 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
7990 /* 24452 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7991 /* 24456 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7992 /* 24460 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
7993 /* 24464 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
7994 /* 24468 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7995 /* 24472 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
7996 /* 24476 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
7997 /* 24480 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
7998 /* 24484 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7999 /* 24488 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
8000 /* 24492 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
8001 /* 24496 */ // MIs[4] vB
8002 /* 24496 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
8003 /* 24501 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
8004 /* 24505 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
8005 /* 24509 */ // MIs[5] vC
8006 /* 24509 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8007 /* 24514 */ // MIs[5] vA
8008 /* 24514 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
8009 /* 24519 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
8010 /* 24523 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8011 /* 24529 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
8012 /* 24531 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8013 /* 24533 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8014 /* 24533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8015 /* 24536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8016 /* 24538 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
8017 /* 24542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
8018 /* 24546 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8019 /* 24550 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8020 /* 24560 */ GIR_RootConstrainSelectedInstOperands,
8021 /* 24561 */ // GIR_Coverage, 5108,
8022 /* 24561 */ GIR_EraseRootFromParent_Done,
8023 /* 24562 */ // Label 401: @24562
8024 /* 24562 */ GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(24700), // Rule ID 5109 //
8025 /* 24567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8026 /* 24570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8027 /* 24574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8028 /* 24578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8029 /* 24582 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8030 /* 24586 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8031 /* 24590 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8032 /* 24594 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8033 /* 24598 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8034 /* 24602 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8035 /* 24606 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8036 /* 24610 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
8037 /* 24614 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8038 /* 24618 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8039 /* 24622 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
8040 /* 24626 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
8041 /* 24630 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
8042 /* 24634 */ // MIs[4] vA
8043 /* 24634 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
8044 /* 24639 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
8045 /* 24643 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
8046 /* 24647 */ // MIs[5] vC
8047 /* 24647 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8048 /* 24652 */ // MIs[5] vB
8049 /* 24652 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
8050 /* 24657 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
8051 /* 24661 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8052 /* 24667 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
8053 /* 24669 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8054 /* 24671 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8055 /* 24671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8056 /* 24674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8057 /* 24676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
8058 /* 24680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
8059 /* 24684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8060 /* 24688 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8061 /* 24698 */ GIR_RootConstrainSelectedInstOperands,
8062 /* 24699 */ // GIR_Coverage, 5109,
8063 /* 24699 */ GIR_EraseRootFromParent_Done,
8064 /* 24700 */ // Label 402: @24700
8065 /* 24700 */ GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(24838), // Rule ID 5116 //
8066 /* 24705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8067 /* 24708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8068 /* 24712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8069 /* 24716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8070 /* 24720 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8071 /* 24724 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8072 /* 24728 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8073 /* 24732 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8074 /* 24736 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8075 /* 24740 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8076 /* 24744 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8077 /* 24748 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
8078 /* 24752 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8079 /* 24756 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8080 /* 24760 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
8081 /* 24764 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
8082 /* 24768 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
8083 /* 24772 */ // MIs[4] vC
8084 /* 24772 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
8085 /* 24777 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
8086 /* 24781 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
8087 /* 24785 */ // MIs[5] vA
8088 /* 24785 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
8089 /* 24790 */ // MIs[5] vB
8090 /* 24790 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8091 /* 24795 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
8092 /* 24799 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8093 /* 24805 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
8094 /* 24807 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8095 /* 24809 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8096 /* 24809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8097 /* 24812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8098 /* 24814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
8099 /* 24818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8100 /* 24822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
8101 /* 24826 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8102 /* 24836 */ GIR_RootConstrainSelectedInstOperands,
8103 /* 24837 */ // GIR_Coverage, 5116,
8104 /* 24837 */ GIR_EraseRootFromParent_Done,
8105 /* 24838 */ // Label 403: @24838
8106 /* 24838 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(24976), // Rule ID 5117 //
8107 /* 24843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8108 /* 24846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8109 /* 24850 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8110 /* 24854 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8111 /* 24858 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8112 /* 24862 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8113 /* 24866 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8114 /* 24870 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8115 /* 24874 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8116 /* 24878 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8117 /* 24882 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8118 /* 24886 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
8119 /* 24890 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8120 /* 24894 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8121 /* 24898 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
8122 /* 24902 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
8123 /* 24906 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
8124 /* 24910 */ // MIs[4] vC
8125 /* 24910 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
8126 /* 24915 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
8127 /* 24919 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
8128 /* 24923 */ // MIs[5] vB
8129 /* 24923 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8130 /* 24928 */ // MIs[5] vA
8131 /* 24928 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
8132 /* 24933 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
8133 /* 24937 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8134 /* 24943 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
8135 /* 24945 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8136 /* 24947 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8137 /* 24947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8138 /* 24950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8139 /* 24952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
8140 /* 24956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8141 /* 24960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
8142 /* 24964 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8143 /* 24974 */ GIR_RootConstrainSelectedInstOperands,
8144 /* 24975 */ // GIR_Coverage, 5117,
8145 /* 24975 */ GIR_EraseRootFromParent_Done,
8146 /* 24976 */ // Label 404: @24976
8147 /* 24976 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(25114), // Rule ID 5118 //
8148 /* 24981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8149 /* 24984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8150 /* 24988 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8151 /* 24992 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8152 /* 24996 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8153 /* 25000 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8154 /* 25004 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8155 /* 25008 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8156 /* 25012 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8157 /* 25016 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8158 /* 25020 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8159 /* 25024 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
8160 /* 25028 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8161 /* 25032 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8162 /* 25036 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
8163 /* 25040 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
8164 /* 25044 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
8165 /* 25048 */ // MIs[4] vB
8166 /* 25048 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8167 /* 25053 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
8168 /* 25057 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
8169 /* 25061 */ // MIs[5] vA
8170 /* 25061 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
8171 /* 25066 */ // MIs[5] vC
8172 /* 25066 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
8173 /* 25071 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
8174 /* 25075 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8175 /* 25081 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
8176 /* 25083 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8177 /* 25085 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8178 /* 25085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8179 /* 25088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8180 /* 25090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
8181 /* 25094 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8182 /* 25098 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
8183 /* 25102 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8184 /* 25112 */ GIR_RootConstrainSelectedInstOperands,
8185 /* 25113 */ // GIR_Coverage, 5118,
8186 /* 25113 */ GIR_EraseRootFromParent_Done,
8187 /* 25114 */ // Label 405: @25114
8188 /* 25114 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(25252), // Rule ID 5119 //
8189 /* 25119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8190 /* 25122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8191 /* 25126 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8192 /* 25130 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8193 /* 25134 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8194 /* 25138 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8195 /* 25142 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8196 /* 25146 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8197 /* 25150 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8198 /* 25154 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8199 /* 25158 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8200 /* 25162 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
8201 /* 25166 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8202 /* 25170 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8203 /* 25174 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
8204 /* 25178 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
8205 /* 25182 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
8206 /* 25186 */ // MIs[4] vB
8207 /* 25186 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8208 /* 25191 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
8209 /* 25195 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
8210 /* 25199 */ // MIs[5] vC
8211 /* 25199 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
8212 /* 25204 */ // MIs[5] vA
8213 /* 25204 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
8214 /* 25209 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
8215 /* 25213 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8216 /* 25219 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
8217 /* 25221 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8218 /* 25223 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8219 /* 25223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8220 /* 25226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8221 /* 25228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
8222 /* 25232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8223 /* 25236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
8224 /* 25240 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8225 /* 25250 */ GIR_RootConstrainSelectedInstOperands,
8226 /* 25251 */ // GIR_Coverage, 5119,
8227 /* 25251 */ GIR_EraseRootFromParent_Done,
8228 /* 25252 */ // Label 406: @25252
8229 /* 25252 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(25390), // Rule ID 5120 //
8230 /* 25257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8231 /* 25260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8232 /* 25264 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8233 /* 25268 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8234 /* 25272 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8235 /* 25276 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8236 /* 25280 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8237 /* 25284 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8238 /* 25288 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8239 /* 25292 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8240 /* 25296 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8241 /* 25300 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
8242 /* 25304 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8243 /* 25308 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8244 /* 25312 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
8245 /* 25316 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
8246 /* 25320 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
8247 /* 25324 */ // MIs[4] vA
8248 /* 25324 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
8249 /* 25329 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
8250 /* 25333 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
8251 /* 25337 */ // MIs[5] vB
8252 /* 25337 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8253 /* 25342 */ // MIs[5] vC
8254 /* 25342 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
8255 /* 25347 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
8256 /* 25351 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8257 /* 25357 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
8258 /* 25359 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8259 /* 25361 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8260 /* 25361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8261 /* 25364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8262 /* 25366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
8263 /* 25370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8264 /* 25374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
8265 /* 25378 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8266 /* 25388 */ GIR_RootConstrainSelectedInstOperands,
8267 /* 25389 */ // GIR_Coverage, 5120,
8268 /* 25389 */ GIR_EraseRootFromParent_Done,
8269 /* 25390 */ // Label 407: @25390
8270 /* 25390 */ GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(25528), // Rule ID 5121 //
8271 /* 25395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8272 /* 25398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8273 /* 25402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8274 /* 25406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8275 /* 25410 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8276 /* 25414 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8277 /* 25418 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8278 /* 25422 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8279 /* 25426 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8280 /* 25430 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8281 /* 25434 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8282 /* 25438 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
8283 /* 25442 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8284 /* 25446 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8285 /* 25450 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
8286 /* 25454 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_OR),
8287 /* 25458 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
8288 /* 25462 */ // MIs[4] vA
8289 /* 25462 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
8290 /* 25467 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
8291 /* 25471 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_OR),
8292 /* 25475 */ // MIs[5] vC
8293 /* 25475 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
8294 /* 25480 */ // MIs[5] vB
8295 /* 25480 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8296 /* 25485 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6]
8297 /* 25489 */ GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8298 /* 25495 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
8299 /* 25497 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8300 /* 25499 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8301 /* 25499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8302 /* 25502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8303 /* 25504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
8304 /* 25508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8305 /* 25512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
8306 /* 25516 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8307 /* 25526 */ GIR_RootConstrainSelectedInstOperands,
8308 /* 25527 */ // GIR_Coverage, 5121,
8309 /* 25527 */ GIR_EraseRootFromParent_Done,
8310 /* 25528 */ // Label 408: @25528
8311 /* 25528 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(25666), // Rule ID 5122 //
8312 /* 25533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8313 /* 25536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8314 /* 25540 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8315 /* 25544 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8316 /* 25548 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8317 /* 25552 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8318 /* 25556 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8319 /* 25560 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8320 /* 25564 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8321 /* 25568 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8322 /* 25572 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8323 /* 25576 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8324 /* 25580 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8325 /* 25584 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8326 /* 25588 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8327 /* 25592 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8328 /* 25598 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8329 /* 25600 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8330 /* 25604 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8331 /* 25608 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8332 /* 25612 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8333 /* 25616 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8334 /* 25620 */ // MIs[6] vA
8335 /* 25620 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
8336 /* 25625 */ // MIs[6] vB
8337 /* 25625 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8338 /* 25630 */ // MIs[5] vC
8339 /* 25630 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8340 /* 25635 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8341 /* 25637 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8342 /* 25637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8343 /* 25640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8344 /* 25642 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8345 /* 25646 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
8346 /* 25650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8347 /* 25654 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8348 /* 25664 */ GIR_RootConstrainSelectedInstOperands,
8349 /* 25665 */ // GIR_Coverage, 5122,
8350 /* 25665 */ GIR_EraseRootFromParent_Done,
8351 /* 25666 */ // Label 409: @25666
8352 /* 25666 */ GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(25804), // Rule ID 5123 //
8353 /* 25671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8354 /* 25674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8355 /* 25678 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8356 /* 25682 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8357 /* 25686 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8358 /* 25690 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8359 /* 25694 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8360 /* 25698 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8361 /* 25702 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8362 /* 25706 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8363 /* 25710 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8364 /* 25714 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8365 /* 25718 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8366 /* 25722 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8367 /* 25726 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8368 /* 25730 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8369 /* 25736 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8370 /* 25738 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8371 /* 25742 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8372 /* 25746 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8373 /* 25750 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8374 /* 25754 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8375 /* 25758 */ // MIs[6] vB
8376 /* 25758 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
8377 /* 25763 */ // MIs[6] vA
8378 /* 25763 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8379 /* 25768 */ // MIs[5] vC
8380 /* 25768 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8381 /* 25773 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8382 /* 25775 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8383 /* 25775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8384 /* 25778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8385 /* 25780 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8386 /* 25784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
8387 /* 25788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8388 /* 25792 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8389 /* 25802 */ GIR_RootConstrainSelectedInstOperands,
8390 /* 25803 */ // GIR_Coverage, 5123,
8391 /* 25803 */ GIR_EraseRootFromParent_Done,
8392 /* 25804 */ // Label 410: @25804
8393 /* 25804 */ GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(25942), // Rule ID 5124 //
8394 /* 25809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8395 /* 25812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8396 /* 25816 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8397 /* 25820 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8398 /* 25824 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8399 /* 25828 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8400 /* 25832 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8401 /* 25836 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8402 /* 25840 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8403 /* 25844 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8404 /* 25848 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8405 /* 25852 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8406 /* 25856 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8407 /* 25860 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8408 /* 25864 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8409 /* 25868 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8410 /* 25874 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8411 /* 25876 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8412 /* 25880 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8413 /* 25884 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8414 /* 25888 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8415 /* 25892 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8416 /* 25896 */ // MIs[6] vA
8417 /* 25896 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
8418 /* 25901 */ // MIs[6] vC
8419 /* 25901 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8420 /* 25906 */ // MIs[5] vB
8421 /* 25906 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8422 /* 25911 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8423 /* 25913 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8424 /* 25913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8425 /* 25916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8426 /* 25918 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8427 /* 25922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
8428 /* 25926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8429 /* 25930 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8430 /* 25940 */ GIR_RootConstrainSelectedInstOperands,
8431 /* 25941 */ // GIR_Coverage, 5124,
8432 /* 25941 */ GIR_EraseRootFromParent_Done,
8433 /* 25942 */ // Label 411: @25942
8434 /* 25942 */ GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(26080), // Rule ID 5125 //
8435 /* 25947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8436 /* 25950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8437 /* 25954 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8438 /* 25958 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8439 /* 25962 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8440 /* 25966 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8441 /* 25970 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8442 /* 25974 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8443 /* 25978 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8444 /* 25982 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8445 /* 25986 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8446 /* 25990 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8447 /* 25994 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8448 /* 25998 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8449 /* 26002 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8450 /* 26006 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8451 /* 26012 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8452 /* 26014 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8453 /* 26018 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8454 /* 26022 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8455 /* 26026 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8456 /* 26030 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8457 /* 26034 */ // MIs[6] vC
8458 /* 26034 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8459 /* 26039 */ // MIs[6] vA
8460 /* 26039 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8461 /* 26044 */ // MIs[5] vB
8462 /* 26044 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8463 /* 26049 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8464 /* 26051 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8465 /* 26051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8466 /* 26054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8467 /* 26056 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8468 /* 26060 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
8469 /* 26064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8470 /* 26068 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8471 /* 26078 */ GIR_RootConstrainSelectedInstOperands,
8472 /* 26079 */ // GIR_Coverage, 5125,
8473 /* 26079 */ GIR_EraseRootFromParent_Done,
8474 /* 26080 */ // Label 412: @26080
8475 /* 26080 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(26218), // Rule ID 5126 //
8476 /* 26085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8477 /* 26088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8478 /* 26092 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8479 /* 26096 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8480 /* 26100 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8481 /* 26104 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8482 /* 26108 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8483 /* 26112 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8484 /* 26116 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8485 /* 26120 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8486 /* 26124 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8487 /* 26128 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8488 /* 26132 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8489 /* 26136 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8490 /* 26140 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8491 /* 26144 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8492 /* 26150 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8493 /* 26152 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8494 /* 26156 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8495 /* 26160 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8496 /* 26164 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8497 /* 26168 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8498 /* 26172 */ // MIs[6] vB
8499 /* 26172 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
8500 /* 26177 */ // MIs[6] vC
8501 /* 26177 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8502 /* 26182 */ // MIs[5] vA
8503 /* 26182 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8504 /* 26187 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8505 /* 26189 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8506 /* 26189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8507 /* 26192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8508 /* 26194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8509 /* 26198 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
8510 /* 26202 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8511 /* 26206 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8512 /* 26216 */ GIR_RootConstrainSelectedInstOperands,
8513 /* 26217 */ // GIR_Coverage, 5126,
8514 /* 26217 */ GIR_EraseRootFromParent_Done,
8515 /* 26218 */ // Label 413: @26218
8516 /* 26218 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(26356), // Rule ID 5127 //
8517 /* 26223 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8518 /* 26226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8519 /* 26230 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8520 /* 26234 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8521 /* 26238 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8522 /* 26242 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8523 /* 26246 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8524 /* 26250 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8525 /* 26254 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8526 /* 26258 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8527 /* 26262 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8528 /* 26266 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8529 /* 26270 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8530 /* 26274 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8531 /* 26278 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8532 /* 26282 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8533 /* 26288 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8534 /* 26290 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8535 /* 26294 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8536 /* 26298 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8537 /* 26302 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8538 /* 26306 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8539 /* 26310 */ // MIs[6] vC
8540 /* 26310 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8541 /* 26315 */ // MIs[6] vB
8542 /* 26315 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8543 /* 26320 */ // MIs[5] vA
8544 /* 26320 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8545 /* 26325 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8546 /* 26327 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8547 /* 26327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8548 /* 26330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8549 /* 26332 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8550 /* 26336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
8551 /* 26340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8552 /* 26344 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8553 /* 26354 */ GIR_RootConstrainSelectedInstOperands,
8554 /* 26355 */ // GIR_Coverage, 5127,
8555 /* 26355 */ GIR_EraseRootFromParent_Done,
8556 /* 26356 */ // Label 414: @26356
8557 /* 26356 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(26494), // Rule ID 5134 //
8558 /* 26361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8559 /* 26364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8560 /* 26368 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8561 /* 26372 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8562 /* 26376 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8563 /* 26380 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8564 /* 26384 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8565 /* 26388 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8566 /* 26392 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8567 /* 26396 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8568 /* 26400 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8569 /* 26404 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8570 /* 26408 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8571 /* 26412 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8572 /* 26416 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8573 /* 26420 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8574 /* 26426 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8575 /* 26428 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8576 /* 26432 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8577 /* 26436 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8578 /* 26440 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8579 /* 26444 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8580 /* 26448 */ // MIs[6] vA
8581 /* 26448 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
8582 /* 26453 */ // MIs[6] vB
8583 /* 26453 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8584 /* 26458 */ // MIs[5] vC
8585 /* 26458 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8586 /* 26463 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8587 /* 26465 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8588 /* 26465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8589 /* 26468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8590 /* 26470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
8591 /* 26474 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
8592 /* 26478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8593 /* 26482 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8594 /* 26492 */ GIR_RootConstrainSelectedInstOperands,
8595 /* 26493 */ // GIR_Coverage, 5134,
8596 /* 26493 */ GIR_EraseRootFromParent_Done,
8597 /* 26494 */ // Label 415: @26494
8598 /* 26494 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(26632), // Rule ID 5135 //
8599 /* 26499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8600 /* 26502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8601 /* 26506 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8602 /* 26510 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8603 /* 26514 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8604 /* 26518 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8605 /* 26522 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8606 /* 26526 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8607 /* 26530 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8608 /* 26534 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8609 /* 26538 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8610 /* 26542 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8611 /* 26546 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8612 /* 26550 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8613 /* 26554 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8614 /* 26558 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8615 /* 26564 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8616 /* 26566 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8617 /* 26570 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8618 /* 26574 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8619 /* 26578 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8620 /* 26582 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8621 /* 26586 */ // MIs[6] vB
8622 /* 26586 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
8623 /* 26591 */ // MIs[6] vA
8624 /* 26591 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8625 /* 26596 */ // MIs[5] vC
8626 /* 26596 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8627 /* 26601 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8628 /* 26603 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8629 /* 26603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8630 /* 26606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8631 /* 26608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
8632 /* 26612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
8633 /* 26616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8634 /* 26620 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8635 /* 26630 */ GIR_RootConstrainSelectedInstOperands,
8636 /* 26631 */ // GIR_Coverage, 5135,
8637 /* 26631 */ GIR_EraseRootFromParent_Done,
8638 /* 26632 */ // Label 416: @26632
8639 /* 26632 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(26770), // Rule ID 5136 //
8640 /* 26637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8641 /* 26640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8642 /* 26644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8643 /* 26648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8644 /* 26652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8645 /* 26656 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8646 /* 26660 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8647 /* 26664 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8648 /* 26668 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8649 /* 26672 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8650 /* 26676 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8651 /* 26680 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8652 /* 26684 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8653 /* 26688 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8654 /* 26692 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8655 /* 26696 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8656 /* 26702 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8657 /* 26704 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8658 /* 26708 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8659 /* 26712 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8660 /* 26716 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8661 /* 26720 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8662 /* 26724 */ // MIs[6] vA
8663 /* 26724 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
8664 /* 26729 */ // MIs[6] vC
8665 /* 26729 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8666 /* 26734 */ // MIs[5] vB
8667 /* 26734 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8668 /* 26739 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8669 /* 26741 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8670 /* 26741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8671 /* 26744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8672 /* 26746 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
8673 /* 26750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
8674 /* 26754 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8675 /* 26758 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8676 /* 26768 */ GIR_RootConstrainSelectedInstOperands,
8677 /* 26769 */ // GIR_Coverage, 5136,
8678 /* 26769 */ GIR_EraseRootFromParent_Done,
8679 /* 26770 */ // Label 417: @26770
8680 /* 26770 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(26908), // Rule ID 5137 //
8681 /* 26775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8682 /* 26778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8683 /* 26782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8684 /* 26786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8685 /* 26790 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8686 /* 26794 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8687 /* 26798 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8688 /* 26802 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8689 /* 26806 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8690 /* 26810 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8691 /* 26814 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8692 /* 26818 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8693 /* 26822 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8694 /* 26826 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8695 /* 26830 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8696 /* 26834 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8697 /* 26840 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8698 /* 26842 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8699 /* 26846 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8700 /* 26850 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8701 /* 26854 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8702 /* 26858 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8703 /* 26862 */ // MIs[6] vC
8704 /* 26862 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8705 /* 26867 */ // MIs[6] vA
8706 /* 26867 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8707 /* 26872 */ // MIs[5] vB
8708 /* 26872 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8709 /* 26877 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8710 /* 26879 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8711 /* 26879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8712 /* 26882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8713 /* 26884 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
8714 /* 26888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
8715 /* 26892 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8716 /* 26896 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8717 /* 26906 */ GIR_RootConstrainSelectedInstOperands,
8718 /* 26907 */ // GIR_Coverage, 5137,
8719 /* 26907 */ GIR_EraseRootFromParent_Done,
8720 /* 26908 */ // Label 418: @26908
8721 /* 26908 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(27046), // Rule ID 5138 //
8722 /* 26913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8723 /* 26916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8724 /* 26920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8725 /* 26924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8726 /* 26928 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8727 /* 26932 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8728 /* 26936 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8729 /* 26940 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8730 /* 26944 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8731 /* 26948 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8732 /* 26952 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8733 /* 26956 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8734 /* 26960 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8735 /* 26964 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8736 /* 26968 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8737 /* 26972 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8738 /* 26978 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8739 /* 26980 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8740 /* 26984 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8741 /* 26988 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8742 /* 26992 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8743 /* 26996 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8744 /* 27000 */ // MIs[6] vB
8745 /* 27000 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
8746 /* 27005 */ // MIs[6] vC
8747 /* 27005 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8748 /* 27010 */ // MIs[5] vA
8749 /* 27010 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8750 /* 27015 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8751 /* 27017 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8752 /* 27017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8753 /* 27020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8754 /* 27022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
8755 /* 27026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
8756 /* 27030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8757 /* 27034 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8758 /* 27044 */ GIR_RootConstrainSelectedInstOperands,
8759 /* 27045 */ // GIR_Coverage, 5138,
8760 /* 27045 */ GIR_EraseRootFromParent_Done,
8761 /* 27046 */ // Label 419: @27046
8762 /* 27046 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(27184), // Rule ID 5139 //
8763 /* 27051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8764 /* 27054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8765 /* 27058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8766 /* 27062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8767 /* 27066 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8768 /* 27070 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8769 /* 27074 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8770 /* 27078 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8771 /* 27082 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8772 /* 27086 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8773 /* 27090 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8774 /* 27094 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8775 /* 27098 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8776 /* 27102 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8777 /* 27106 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8778 /* 27110 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8779 /* 27116 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8780 /* 27118 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8781 /* 27122 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8782 /* 27126 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8783 /* 27130 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8784 /* 27134 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8785 /* 27138 */ // MIs[6] vC
8786 /* 27138 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8787 /* 27143 */ // MIs[6] vB
8788 /* 27143 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8789 /* 27148 */ // MIs[5] vA
8790 /* 27148 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8791 /* 27153 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8792 /* 27155 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8793 /* 27155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8794 /* 27158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8795 /* 27160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
8796 /* 27164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
8797 /* 27168 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
8798 /* 27172 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8799 /* 27182 */ GIR_RootConstrainSelectedInstOperands,
8800 /* 27183 */ // GIR_Coverage, 5139,
8801 /* 27183 */ GIR_EraseRootFromParent_Done,
8802 /* 27184 */ // Label 420: @27184
8803 /* 27184 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(27322), // Rule ID 5146 //
8804 /* 27189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8805 /* 27192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8806 /* 27196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8807 /* 27200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8808 /* 27204 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8809 /* 27208 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8810 /* 27212 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8811 /* 27216 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8812 /* 27220 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8813 /* 27224 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8814 /* 27228 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8815 /* 27232 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8816 /* 27236 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8817 /* 27240 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8818 /* 27244 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8819 /* 27248 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8820 /* 27254 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8821 /* 27256 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8822 /* 27260 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8823 /* 27264 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8824 /* 27268 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8825 /* 27272 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8826 /* 27276 */ // MIs[6] vA
8827 /* 27276 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
8828 /* 27281 */ // MIs[6] vB
8829 /* 27281 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8830 /* 27286 */ // MIs[5] vC
8831 /* 27286 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8832 /* 27291 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8833 /* 27293 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8834 /* 27293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8835 /* 27296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8836 /* 27298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8837 /* 27302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8838 /* 27306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
8839 /* 27310 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8840 /* 27320 */ GIR_RootConstrainSelectedInstOperands,
8841 /* 27321 */ // GIR_Coverage, 5146,
8842 /* 27321 */ GIR_EraseRootFromParent_Done,
8843 /* 27322 */ // Label 421: @27322
8844 /* 27322 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(27460), // Rule ID 5147 //
8845 /* 27327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8846 /* 27330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8847 /* 27334 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8848 /* 27338 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8849 /* 27342 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8850 /* 27346 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8851 /* 27350 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8852 /* 27354 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8853 /* 27358 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8854 /* 27362 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8855 /* 27366 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8856 /* 27370 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8857 /* 27374 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8858 /* 27378 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8859 /* 27382 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8860 /* 27386 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8861 /* 27392 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8862 /* 27394 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8863 /* 27398 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8864 /* 27402 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8865 /* 27406 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8866 /* 27410 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8867 /* 27414 */ // MIs[6] vB
8868 /* 27414 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8869 /* 27419 */ // MIs[6] vA
8870 /* 27419 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8871 /* 27424 */ // MIs[5] vC
8872 /* 27424 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8873 /* 27429 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8874 /* 27431 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8875 /* 27431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8876 /* 27434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8877 /* 27436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8878 /* 27440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8879 /* 27444 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
8880 /* 27448 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8881 /* 27458 */ GIR_RootConstrainSelectedInstOperands,
8882 /* 27459 */ // GIR_Coverage, 5147,
8883 /* 27459 */ GIR_EraseRootFromParent_Done,
8884 /* 27460 */ // Label 422: @27460
8885 /* 27460 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(27598), // Rule ID 5148 //
8886 /* 27465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8887 /* 27468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8888 /* 27472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8889 /* 27476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8890 /* 27480 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8891 /* 27484 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8892 /* 27488 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8893 /* 27492 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8894 /* 27496 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8895 /* 27500 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8896 /* 27504 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8897 /* 27508 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8898 /* 27512 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8899 /* 27516 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8900 /* 27520 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8901 /* 27524 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8902 /* 27530 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8903 /* 27532 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8904 /* 27536 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8905 /* 27540 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8906 /* 27544 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8907 /* 27548 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8908 /* 27552 */ // MIs[6] vA
8909 /* 27552 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
8910 /* 27557 */ // MIs[6] vC
8911 /* 27557 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8912 /* 27562 */ // MIs[5] vB
8913 /* 27562 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8914 /* 27567 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8915 /* 27569 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8916 /* 27569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8917 /* 27572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8918 /* 27574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8919 /* 27578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8920 /* 27582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
8921 /* 27586 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8922 /* 27596 */ GIR_RootConstrainSelectedInstOperands,
8923 /* 27597 */ // GIR_Coverage, 5148,
8924 /* 27597 */ GIR_EraseRootFromParent_Done,
8925 /* 27598 */ // Label 423: @27598
8926 /* 27598 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(27736), // Rule ID 5149 //
8927 /* 27603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8928 /* 27606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8929 /* 27610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8930 /* 27614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8931 /* 27618 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8932 /* 27622 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8933 /* 27626 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8934 /* 27630 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8935 /* 27634 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8936 /* 27638 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8937 /* 27642 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8938 /* 27646 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8939 /* 27650 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8940 /* 27654 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8941 /* 27658 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8942 /* 27662 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8943 /* 27668 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8944 /* 27670 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8945 /* 27674 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8946 /* 27678 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8947 /* 27682 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8948 /* 27686 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8949 /* 27690 */ // MIs[6] vC
8950 /* 27690 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
8951 /* 27695 */ // MIs[6] vA
8952 /* 27695 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8953 /* 27700 */ // MIs[5] vB
8954 /* 27700 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
8955 /* 27705 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8956 /* 27707 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8957 /* 27707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8958 /* 27710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
8959 /* 27712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
8960 /* 27716 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
8961 /* 27720 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
8962 /* 27724 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
8963 /* 27734 */ GIR_RootConstrainSelectedInstOperands,
8964 /* 27735 */ // GIR_Coverage, 5149,
8965 /* 27735 */ GIR_EraseRootFromParent_Done,
8966 /* 27736 */ // Label 424: @27736
8967 /* 27736 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(27874), // Rule ID 5150 //
8968 /* 27741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
8969 /* 27744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
8970 /* 27748 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8971 /* 27752 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8972 /* 27756 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
8973 /* 27760 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
8974 /* 27764 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8975 /* 27768 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
8976 /* 27772 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
8977 /* 27776 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
8978 /* 27780 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8979 /* 27784 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
8980 /* 27788 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
8981 /* 27792 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
8982 /* 27796 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
8983 /* 27800 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8984 /* 27806 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
8985 /* 27808 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
8986 /* 27812 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
8987 /* 27816 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
8988 /* 27820 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
8989 /* 27824 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
8990 /* 27828 */ // MIs[6] vB
8991 /* 27828 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
8992 /* 27833 */ // MIs[6] vC
8993 /* 27833 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
8994 /* 27838 */ // MIs[5] vA
8995 /* 27838 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
8996 /* 27843 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
8997 /* 27845 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
8998 /* 27845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
8999 /* 27848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9000 /* 27850 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
9001 /* 27854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
9002 /* 27858 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
9003 /* 27862 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9004 /* 27872 */ GIR_RootConstrainSelectedInstOperands,
9005 /* 27873 */ // GIR_Coverage, 5150,
9006 /* 27873 */ GIR_EraseRootFromParent_Done,
9007 /* 27874 */ // Label 425: @27874
9008 /* 27874 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(28012), // Rule ID 5151 //
9009 /* 27879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9010 /* 27882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9011 /* 27886 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9012 /* 27890 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9013 /* 27894 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9014 /* 27898 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9015 /* 27902 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9016 /* 27906 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9017 /* 27910 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9018 /* 27914 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9019 /* 27918 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9020 /* 27922 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9021 /* 27926 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9022 /* 27930 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9023 /* 27934 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9024 /* 27938 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9025 /* 27944 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9026 /* 27946 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9027 /* 27950 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9028 /* 27954 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9029 /* 27958 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9030 /* 27962 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9031 /* 27966 */ // MIs[6] vC
9032 /* 27966 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9033 /* 27971 */ // MIs[6] vB
9034 /* 27971 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9035 /* 27976 */ // MIs[5] vA
9036 /* 27976 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9037 /* 27981 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9038 /* 27983 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9039 /* 27983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9040 /* 27986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9041 /* 27988 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
9042 /* 27992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
9043 /* 27996 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
9044 /* 28000 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9045 /* 28010 */ GIR_RootConstrainSelectedInstOperands,
9046 /* 28011 */ // GIR_Coverage, 5151,
9047 /* 28011 */ GIR_EraseRootFromParent_Done,
9048 /* 28012 */ // Label 426: @28012
9049 /* 28012 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(28150), // Rule ID 5158 //
9050 /* 28017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9051 /* 28020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9052 /* 28024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9053 /* 28028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9054 /* 28032 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9055 /* 28036 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9056 /* 28040 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9057 /* 28044 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9058 /* 28048 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9059 /* 28052 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9060 /* 28056 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9061 /* 28060 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9062 /* 28064 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9063 /* 28068 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9064 /* 28072 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9065 /* 28076 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9066 /* 28082 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9067 /* 28084 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9068 /* 28088 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9069 /* 28092 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9070 /* 28096 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9071 /* 28100 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9072 /* 28104 */ // MIs[6] vA
9073 /* 28104 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9074 /* 28109 */ // MIs[6] vB
9075 /* 28109 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9076 /* 28114 */ // MIs[5] vC
9077 /* 28114 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9078 /* 28119 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9079 /* 28121 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9080 /* 28121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9081 /* 28124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9082 /* 28126 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
9083 /* 28130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
9084 /* 28134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9085 /* 28138 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9086 /* 28148 */ GIR_RootConstrainSelectedInstOperands,
9087 /* 28149 */ // GIR_Coverage, 5158,
9088 /* 28149 */ GIR_EraseRootFromParent_Done,
9089 /* 28150 */ // Label 427: @28150
9090 /* 28150 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(28288), // Rule ID 5159 //
9091 /* 28155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9092 /* 28158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9093 /* 28162 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9094 /* 28166 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9095 /* 28170 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9096 /* 28174 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9097 /* 28178 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9098 /* 28182 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9099 /* 28186 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9100 /* 28190 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9101 /* 28194 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9102 /* 28198 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9103 /* 28202 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9104 /* 28206 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9105 /* 28210 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9106 /* 28214 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9107 /* 28220 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9108 /* 28222 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9109 /* 28226 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9110 /* 28230 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9111 /* 28234 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9112 /* 28238 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9113 /* 28242 */ // MIs[6] vB
9114 /* 28242 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9115 /* 28247 */ // MIs[6] vA
9116 /* 28247 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9117 /* 28252 */ // MIs[5] vC
9118 /* 28252 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9119 /* 28257 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9120 /* 28259 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9121 /* 28259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9122 /* 28262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9123 /* 28264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
9124 /* 28268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
9125 /* 28272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9126 /* 28276 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9127 /* 28286 */ GIR_RootConstrainSelectedInstOperands,
9128 /* 28287 */ // GIR_Coverage, 5159,
9129 /* 28287 */ GIR_EraseRootFromParent_Done,
9130 /* 28288 */ // Label 428: @28288
9131 /* 28288 */ GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(28426), // Rule ID 5160 //
9132 /* 28293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9133 /* 28296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9134 /* 28300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9135 /* 28304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9136 /* 28308 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9137 /* 28312 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9138 /* 28316 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9139 /* 28320 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9140 /* 28324 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9141 /* 28328 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9142 /* 28332 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9143 /* 28336 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9144 /* 28340 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9145 /* 28344 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9146 /* 28348 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9147 /* 28352 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9148 /* 28358 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9149 /* 28360 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9150 /* 28364 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9151 /* 28368 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9152 /* 28372 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9153 /* 28376 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9154 /* 28380 */ // MIs[6] vA
9155 /* 28380 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9156 /* 28385 */ // MIs[6] vC
9157 /* 28385 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9158 /* 28390 */ // MIs[5] vB
9159 /* 28390 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9160 /* 28395 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9161 /* 28397 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9162 /* 28397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9163 /* 28400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9164 /* 28402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
9165 /* 28406 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
9166 /* 28410 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9167 /* 28414 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9168 /* 28424 */ GIR_RootConstrainSelectedInstOperands,
9169 /* 28425 */ // GIR_Coverage, 5160,
9170 /* 28425 */ GIR_EraseRootFromParent_Done,
9171 /* 28426 */ // Label 429: @28426
9172 /* 28426 */ GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(28564), // Rule ID 5161 //
9173 /* 28431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9174 /* 28434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9175 /* 28438 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9176 /* 28442 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9177 /* 28446 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9178 /* 28450 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9179 /* 28454 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9180 /* 28458 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9181 /* 28462 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9182 /* 28466 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9183 /* 28470 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9184 /* 28474 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9185 /* 28478 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9186 /* 28482 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9187 /* 28486 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9188 /* 28490 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9189 /* 28496 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9190 /* 28498 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9191 /* 28502 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9192 /* 28506 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9193 /* 28510 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9194 /* 28514 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9195 /* 28518 */ // MIs[6] vC
9196 /* 28518 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9197 /* 28523 */ // MIs[6] vA
9198 /* 28523 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9199 /* 28528 */ // MIs[5] vB
9200 /* 28528 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9201 /* 28533 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9202 /* 28535 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9203 /* 28535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9204 /* 28538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9205 /* 28540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
9206 /* 28544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
9207 /* 28548 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9208 /* 28552 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9209 /* 28562 */ GIR_RootConstrainSelectedInstOperands,
9210 /* 28563 */ // GIR_Coverage, 5161,
9211 /* 28563 */ GIR_EraseRootFromParent_Done,
9212 /* 28564 */ // Label 430: @28564
9213 /* 28564 */ GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(28702), // Rule ID 5162 //
9214 /* 28569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9215 /* 28572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9216 /* 28576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9217 /* 28580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9218 /* 28584 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9219 /* 28588 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9220 /* 28592 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9221 /* 28596 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9222 /* 28600 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9223 /* 28604 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9224 /* 28608 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9225 /* 28612 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9226 /* 28616 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9227 /* 28620 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9228 /* 28624 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9229 /* 28628 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9230 /* 28634 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9231 /* 28636 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9232 /* 28640 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9233 /* 28644 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9234 /* 28648 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9235 /* 28652 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9236 /* 28656 */ // MIs[6] vB
9237 /* 28656 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9238 /* 28661 */ // MIs[6] vC
9239 /* 28661 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9240 /* 28666 */ // MIs[5] vA
9241 /* 28666 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9242 /* 28671 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9243 /* 28673 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9244 /* 28673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9245 /* 28676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9246 /* 28678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
9247 /* 28682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
9248 /* 28686 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9249 /* 28690 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9250 /* 28700 */ GIR_RootConstrainSelectedInstOperands,
9251 /* 28701 */ // GIR_Coverage, 5162,
9252 /* 28701 */ GIR_EraseRootFromParent_Done,
9253 /* 28702 */ // Label 431: @28702
9254 /* 28702 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(28840), // Rule ID 5163 //
9255 /* 28707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9256 /* 28710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9257 /* 28714 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9258 /* 28718 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9259 /* 28722 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9260 /* 28726 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9261 /* 28730 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9262 /* 28734 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9263 /* 28738 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9264 /* 28742 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9265 /* 28746 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9266 /* 28750 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9267 /* 28754 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9268 /* 28758 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9269 /* 28762 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9270 /* 28766 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9271 /* 28772 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9272 /* 28774 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9273 /* 28778 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9274 /* 28782 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9275 /* 28786 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9276 /* 28790 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9277 /* 28794 */ // MIs[6] vC
9278 /* 28794 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9279 /* 28799 */ // MIs[6] vB
9280 /* 28799 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9281 /* 28804 */ // MIs[5] vA
9282 /* 28804 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9283 /* 28809 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9284 /* 28811 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9285 /* 28811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9286 /* 28814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9287 /* 28816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
9288 /* 28820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
9289 /* 28824 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9290 /* 28828 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9291 /* 28838 */ GIR_RootConstrainSelectedInstOperands,
9292 /* 28839 */ // GIR_Coverage, 5163,
9293 /* 28839 */ GIR_EraseRootFromParent_Done,
9294 /* 28840 */ // Label 432: @28840
9295 /* 28840 */ GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(28978), // Rule ID 5170 //
9296 /* 28845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9297 /* 28848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9298 /* 28852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9299 /* 28856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9300 /* 28860 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9301 /* 28864 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9302 /* 28868 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9303 /* 28872 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9304 /* 28876 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9305 /* 28880 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9306 /* 28884 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9307 /* 28888 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9308 /* 28892 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9309 /* 28896 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9310 /* 28900 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9311 /* 28904 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9312 /* 28910 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9313 /* 28912 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9314 /* 28916 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9315 /* 28920 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9316 /* 28924 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9317 /* 28928 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9318 /* 28932 */ // MIs[6] vA
9319 /* 28932 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9320 /* 28937 */ // MIs[6] vB
9321 /* 28937 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9322 /* 28942 */ // MIs[5] vC
9323 /* 28942 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9324 /* 28947 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9325 /* 28949 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9326 /* 28949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9327 /* 28952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9328 /* 28954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9329 /* 28958 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
9330 /* 28962 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
9331 /* 28966 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9332 /* 28976 */ GIR_RootConstrainSelectedInstOperands,
9333 /* 28977 */ // GIR_Coverage, 5170,
9334 /* 28977 */ GIR_EraseRootFromParent_Done,
9335 /* 28978 */ // Label 433: @28978
9336 /* 28978 */ GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(29116), // Rule ID 5171 //
9337 /* 28983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9338 /* 28986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9339 /* 28990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9340 /* 28994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9341 /* 28998 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9342 /* 29002 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9343 /* 29006 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9344 /* 29010 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9345 /* 29014 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9346 /* 29018 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9347 /* 29022 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9348 /* 29026 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9349 /* 29030 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9350 /* 29034 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9351 /* 29038 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9352 /* 29042 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9353 /* 29048 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9354 /* 29050 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9355 /* 29054 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9356 /* 29058 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9357 /* 29062 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9358 /* 29066 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9359 /* 29070 */ // MIs[6] vB
9360 /* 29070 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9361 /* 29075 */ // MIs[6] vA
9362 /* 29075 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9363 /* 29080 */ // MIs[5] vC
9364 /* 29080 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9365 /* 29085 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9366 /* 29087 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9367 /* 29087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9368 /* 29090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9369 /* 29092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9370 /* 29096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
9371 /* 29100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
9372 /* 29104 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9373 /* 29114 */ GIR_RootConstrainSelectedInstOperands,
9374 /* 29115 */ // GIR_Coverage, 5171,
9375 /* 29115 */ GIR_EraseRootFromParent_Done,
9376 /* 29116 */ // Label 434: @29116
9377 /* 29116 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(29254), // Rule ID 5172 //
9378 /* 29121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9379 /* 29124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9380 /* 29128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9381 /* 29132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9382 /* 29136 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9383 /* 29140 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9384 /* 29144 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9385 /* 29148 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9386 /* 29152 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9387 /* 29156 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9388 /* 29160 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9389 /* 29164 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9390 /* 29168 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9391 /* 29172 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9392 /* 29176 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9393 /* 29180 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9394 /* 29186 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9395 /* 29188 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9396 /* 29192 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9397 /* 29196 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9398 /* 29200 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9399 /* 29204 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9400 /* 29208 */ // MIs[6] vA
9401 /* 29208 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9402 /* 29213 */ // MIs[6] vC
9403 /* 29213 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9404 /* 29218 */ // MIs[5] vB
9405 /* 29218 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9406 /* 29223 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9407 /* 29225 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9408 /* 29225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9409 /* 29228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9410 /* 29230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9411 /* 29234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
9412 /* 29238 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
9413 /* 29242 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9414 /* 29252 */ GIR_RootConstrainSelectedInstOperands,
9415 /* 29253 */ // GIR_Coverage, 5172,
9416 /* 29253 */ GIR_EraseRootFromParent_Done,
9417 /* 29254 */ // Label 435: @29254
9418 /* 29254 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(29392), // Rule ID 5173 //
9419 /* 29259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9420 /* 29262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9421 /* 29266 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9422 /* 29270 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9423 /* 29274 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9424 /* 29278 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9425 /* 29282 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9426 /* 29286 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9427 /* 29290 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9428 /* 29294 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9429 /* 29298 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9430 /* 29302 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9431 /* 29306 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9432 /* 29310 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9433 /* 29314 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9434 /* 29318 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9435 /* 29324 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9436 /* 29326 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9437 /* 29330 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9438 /* 29334 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9439 /* 29338 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9440 /* 29342 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9441 /* 29346 */ // MIs[6] vC
9442 /* 29346 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9443 /* 29351 */ // MIs[6] vA
9444 /* 29351 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9445 /* 29356 */ // MIs[5] vB
9446 /* 29356 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9447 /* 29361 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9448 /* 29363 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9449 /* 29363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9450 /* 29366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9451 /* 29368 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9452 /* 29372 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
9453 /* 29376 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
9454 /* 29380 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9455 /* 29390 */ GIR_RootConstrainSelectedInstOperands,
9456 /* 29391 */ // GIR_Coverage, 5173,
9457 /* 29391 */ GIR_EraseRootFromParent_Done,
9458 /* 29392 */ // Label 436: @29392
9459 /* 29392 */ GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(29530), // Rule ID 5174 //
9460 /* 29397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9461 /* 29400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9462 /* 29404 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9463 /* 29408 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9464 /* 29412 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9465 /* 29416 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9466 /* 29420 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9467 /* 29424 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9468 /* 29428 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9469 /* 29432 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9470 /* 29436 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9471 /* 29440 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9472 /* 29444 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9473 /* 29448 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9474 /* 29452 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9475 /* 29456 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9476 /* 29462 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9477 /* 29464 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9478 /* 29468 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9479 /* 29472 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9480 /* 29476 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9481 /* 29480 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9482 /* 29484 */ // MIs[6] vB
9483 /* 29484 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9484 /* 29489 */ // MIs[6] vC
9485 /* 29489 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9486 /* 29494 */ // MIs[5] vA
9487 /* 29494 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9488 /* 29499 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9489 /* 29501 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9490 /* 29501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9491 /* 29504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9492 /* 29506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9493 /* 29510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
9494 /* 29514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
9495 /* 29518 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9496 /* 29528 */ GIR_RootConstrainSelectedInstOperands,
9497 /* 29529 */ // GIR_Coverage, 5174,
9498 /* 29529 */ GIR_EraseRootFromParent_Done,
9499 /* 29530 */ // Label 437: @29530
9500 /* 29530 */ GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(29668), // Rule ID 5175 //
9501 /* 29535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9502 /* 29538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9503 /* 29542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9504 /* 29546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9505 /* 29550 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9506 /* 29554 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9507 /* 29558 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9508 /* 29562 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9509 /* 29566 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9510 /* 29570 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9511 /* 29574 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9512 /* 29578 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9513 /* 29582 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9514 /* 29586 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9515 /* 29590 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9516 /* 29594 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9517 /* 29600 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9518 /* 29602 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9519 /* 29606 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9520 /* 29610 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9521 /* 29614 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9522 /* 29618 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9523 /* 29622 */ // MIs[6] vC
9524 /* 29622 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9525 /* 29627 */ // MIs[6] vB
9526 /* 29627 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9527 /* 29632 */ // MIs[5] vA
9528 /* 29632 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9529 /* 29637 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9530 /* 29639 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9531 /* 29639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9532 /* 29642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9533 /* 29644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9534 /* 29648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
9535 /* 29652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
9536 /* 29656 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9537 /* 29666 */ GIR_RootConstrainSelectedInstOperands,
9538 /* 29667 */ // GIR_Coverage, 5175,
9539 /* 29667 */ GIR_EraseRootFromParent_Done,
9540 /* 29668 */ // Label 438: @29668
9541 /* 29668 */ GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(29806), // Rule ID 5182 //
9542 /* 29673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9543 /* 29676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9544 /* 29680 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9545 /* 29684 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9546 /* 29688 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9547 /* 29692 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9548 /* 29696 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9549 /* 29700 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9550 /* 29704 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9551 /* 29708 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9552 /* 29712 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9553 /* 29716 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9554 /* 29720 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9555 /* 29724 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9556 /* 29728 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9557 /* 29732 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9558 /* 29738 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9559 /* 29740 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9560 /* 29744 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9561 /* 29748 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9562 /* 29752 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9563 /* 29756 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9564 /* 29760 */ // MIs[6] vA
9565 /* 29760 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9566 /* 29765 */ // MIs[6] vB
9567 /* 29765 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9568 /* 29770 */ // MIs[5] vC
9569 /* 29770 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9570 /* 29775 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9571 /* 29777 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9572 /* 29777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9573 /* 29780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9574 /* 29782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9575 /* 29786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9576 /* 29790 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9577 /* 29794 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9578 /* 29804 */ GIR_RootConstrainSelectedInstOperands,
9579 /* 29805 */ // GIR_Coverage, 5182,
9580 /* 29805 */ GIR_EraseRootFromParent_Done,
9581 /* 29806 */ // Label 439: @29806
9582 /* 29806 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(29944), // Rule ID 5183 //
9583 /* 29811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9584 /* 29814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9585 /* 29818 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9586 /* 29822 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9587 /* 29826 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9588 /* 29830 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9589 /* 29834 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9590 /* 29838 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9591 /* 29842 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9592 /* 29846 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9593 /* 29850 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9594 /* 29854 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9595 /* 29858 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9596 /* 29862 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9597 /* 29866 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9598 /* 29870 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9599 /* 29876 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9600 /* 29878 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9601 /* 29882 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9602 /* 29886 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9603 /* 29890 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9604 /* 29894 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9605 /* 29898 */ // MIs[6] vB
9606 /* 29898 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9607 /* 29903 */ // MIs[6] vA
9608 /* 29903 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9609 /* 29908 */ // MIs[5] vC
9610 /* 29908 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9611 /* 29913 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9612 /* 29915 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9613 /* 29915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9614 /* 29918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9615 /* 29920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9616 /* 29924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9617 /* 29928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9618 /* 29932 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9619 /* 29942 */ GIR_RootConstrainSelectedInstOperands,
9620 /* 29943 */ // GIR_Coverage, 5183,
9621 /* 29943 */ GIR_EraseRootFromParent_Done,
9622 /* 29944 */ // Label 440: @29944
9623 /* 29944 */ GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(30082), // Rule ID 5184 //
9624 /* 29949 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9625 /* 29952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9626 /* 29956 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9627 /* 29960 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9628 /* 29964 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9629 /* 29968 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9630 /* 29972 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9631 /* 29976 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9632 /* 29980 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9633 /* 29984 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9634 /* 29988 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9635 /* 29992 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9636 /* 29996 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9637 /* 30000 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9638 /* 30004 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9639 /* 30008 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9640 /* 30014 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9641 /* 30016 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9642 /* 30020 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9643 /* 30024 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9644 /* 30028 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9645 /* 30032 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9646 /* 30036 */ // MIs[6] vA
9647 /* 30036 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9648 /* 30041 */ // MIs[6] vC
9649 /* 30041 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9650 /* 30046 */ // MIs[5] vB
9651 /* 30046 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9652 /* 30051 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9653 /* 30053 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9654 /* 30053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9655 /* 30056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9656 /* 30058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9657 /* 30062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9658 /* 30066 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9659 /* 30070 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9660 /* 30080 */ GIR_RootConstrainSelectedInstOperands,
9661 /* 30081 */ // GIR_Coverage, 5184,
9662 /* 30081 */ GIR_EraseRootFromParent_Done,
9663 /* 30082 */ // Label 441: @30082
9664 /* 30082 */ GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(30220), // Rule ID 5185 //
9665 /* 30087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9666 /* 30090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9667 /* 30094 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9668 /* 30098 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9669 /* 30102 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9670 /* 30106 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9671 /* 30110 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9672 /* 30114 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9673 /* 30118 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9674 /* 30122 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9675 /* 30126 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9676 /* 30130 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9677 /* 30134 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9678 /* 30138 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9679 /* 30142 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9680 /* 30146 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9681 /* 30152 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9682 /* 30154 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9683 /* 30158 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9684 /* 30162 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9685 /* 30166 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9686 /* 30170 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9687 /* 30174 */ // MIs[6] vC
9688 /* 30174 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9689 /* 30179 */ // MIs[6] vA
9690 /* 30179 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9691 /* 30184 */ // MIs[5] vB
9692 /* 30184 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9693 /* 30189 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9694 /* 30191 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9695 /* 30191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9696 /* 30194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9697 /* 30196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9698 /* 30200 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9699 /* 30204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9700 /* 30208 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9701 /* 30218 */ GIR_RootConstrainSelectedInstOperands,
9702 /* 30219 */ // GIR_Coverage, 5185,
9703 /* 30219 */ GIR_EraseRootFromParent_Done,
9704 /* 30220 */ // Label 442: @30220
9705 /* 30220 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(30358), // Rule ID 5186 //
9706 /* 30225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9707 /* 30228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9708 /* 30232 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9709 /* 30236 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9710 /* 30240 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9711 /* 30244 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9712 /* 30248 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9713 /* 30252 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9714 /* 30256 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9715 /* 30260 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9716 /* 30264 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9717 /* 30268 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9718 /* 30272 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9719 /* 30276 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9720 /* 30280 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9721 /* 30284 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9722 /* 30290 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9723 /* 30292 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9724 /* 30296 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9725 /* 30300 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9726 /* 30304 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9727 /* 30308 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9728 /* 30312 */ // MIs[6] vB
9729 /* 30312 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9730 /* 30317 */ // MIs[6] vC
9731 /* 30317 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9732 /* 30322 */ // MIs[5] vA
9733 /* 30322 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9734 /* 30327 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9735 /* 30329 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9736 /* 30329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9737 /* 30332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9738 /* 30334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9739 /* 30338 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9740 /* 30342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9741 /* 30346 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9742 /* 30356 */ GIR_RootConstrainSelectedInstOperands,
9743 /* 30357 */ // GIR_Coverage, 5186,
9744 /* 30357 */ GIR_EraseRootFromParent_Done,
9745 /* 30358 */ // Label 443: @30358
9746 /* 30358 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(30496), // Rule ID 5187 //
9747 /* 30363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9748 /* 30366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9749 /* 30370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9750 /* 30374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9751 /* 30378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9752 /* 30382 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9753 /* 30386 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9754 /* 30390 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9755 /* 30394 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9756 /* 30398 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9757 /* 30402 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9758 /* 30406 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9759 /* 30410 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9760 /* 30414 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9761 /* 30418 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9762 /* 30422 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9763 /* 30428 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9764 /* 30430 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9765 /* 30434 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9766 /* 30438 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
9767 /* 30442 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
9768 /* 30446 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9769 /* 30450 */ // MIs[6] vC
9770 /* 30450 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9771 /* 30455 */ // MIs[6] vB
9772 /* 30455 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9773 /* 30460 */ // MIs[5] vA
9774 /* 30460 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9775 /* 30465 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9776 /* 30467 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9777 /* 30467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9778 /* 30470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9779 /* 30472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
9780 /* 30476 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9781 /* 30480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
9782 /* 30484 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9783 /* 30494 */ GIR_RootConstrainSelectedInstOperands,
9784 /* 30495 */ // GIR_Coverage, 5187,
9785 /* 30495 */ GIR_EraseRootFromParent_Done,
9786 /* 30496 */ // Label 444: @30496
9787 /* 30496 */ GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(30634), // Rule ID 5128 //
9788 /* 30501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9789 /* 30504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9790 /* 30508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9791 /* 30512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9792 /* 30516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9793 /* 30520 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9794 /* 30524 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9795 /* 30528 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9796 /* 30532 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9797 /* 30536 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9798 /* 30540 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9799 /* 30544 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9800 /* 30548 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9801 /* 30552 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9802 /* 30556 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9803 /* 30560 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9804 /* 30566 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9805 /* 30568 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9806 /* 30572 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9807 /* 30576 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
9808 /* 30580 */ // MIs[5] vC
9809 /* 30580 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9810 /* 30585 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
9811 /* 30589 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9812 /* 30593 */ // MIs[6] vA
9813 /* 30593 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9814 /* 30598 */ // MIs[6] vB
9815 /* 30598 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
9816 /* 30603 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9817 /* 30605 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9818 /* 30605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9819 /* 30608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9820 /* 30610 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
9821 /* 30614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9822 /* 30618 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
9823 /* 30622 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9824 /* 30632 */ GIR_RootConstrainSelectedInstOperands,
9825 /* 30633 */ // GIR_Coverage, 5128,
9826 /* 30633 */ GIR_EraseRootFromParent_Done,
9827 /* 30634 */ // Label 445: @30634
9828 /* 30634 */ GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(30772), // Rule ID 5129 //
9829 /* 30639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9830 /* 30642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9831 /* 30646 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9832 /* 30650 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9833 /* 30654 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9834 /* 30658 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9835 /* 30662 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9836 /* 30666 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9837 /* 30670 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9838 /* 30674 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9839 /* 30678 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9840 /* 30682 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9841 /* 30686 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9842 /* 30690 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9843 /* 30694 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9844 /* 30698 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9845 /* 30704 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9846 /* 30706 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9847 /* 30710 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9848 /* 30714 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
9849 /* 30718 */ // MIs[5] vC
9850 /* 30718 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9851 /* 30723 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
9852 /* 30727 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9853 /* 30731 */ // MIs[6] vB
9854 /* 30731 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9855 /* 30736 */ // MIs[6] vA
9856 /* 30736 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9857 /* 30741 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9858 /* 30743 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9859 /* 30743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9860 /* 30746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9861 /* 30748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
9862 /* 30752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9863 /* 30756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
9864 /* 30760 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9865 /* 30770 */ GIR_RootConstrainSelectedInstOperands,
9866 /* 30771 */ // GIR_Coverage, 5129,
9867 /* 30771 */ GIR_EraseRootFromParent_Done,
9868 /* 30772 */ // Label 446: @30772
9869 /* 30772 */ GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(30910), // Rule ID 5130 //
9870 /* 30777 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9871 /* 30780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9872 /* 30784 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9873 /* 30788 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9874 /* 30792 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9875 /* 30796 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9876 /* 30800 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9877 /* 30804 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9878 /* 30808 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9879 /* 30812 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9880 /* 30816 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9881 /* 30820 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9882 /* 30824 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9883 /* 30828 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9884 /* 30832 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9885 /* 30836 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9886 /* 30842 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9887 /* 30844 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9888 /* 30848 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9889 /* 30852 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
9890 /* 30856 */ // MIs[5] vB
9891 /* 30856 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9892 /* 30861 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
9893 /* 30865 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9894 /* 30869 */ // MIs[6] vA
9895 /* 30869 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9896 /* 30874 */ // MIs[6] vC
9897 /* 30874 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9898 /* 30879 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9899 /* 30881 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9900 /* 30881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9901 /* 30884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9902 /* 30886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
9903 /* 30890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9904 /* 30894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
9905 /* 30898 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9906 /* 30908 */ GIR_RootConstrainSelectedInstOperands,
9907 /* 30909 */ // GIR_Coverage, 5130,
9908 /* 30909 */ GIR_EraseRootFromParent_Done,
9909 /* 30910 */ // Label 447: @30910
9910 /* 30910 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(31048), // Rule ID 5131 //
9911 /* 30915 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9912 /* 30918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9913 /* 30922 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9914 /* 30926 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9915 /* 30930 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9916 /* 30934 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9917 /* 30938 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9918 /* 30942 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9919 /* 30946 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9920 /* 30950 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9921 /* 30954 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9922 /* 30958 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9923 /* 30962 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9924 /* 30966 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9925 /* 30970 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9926 /* 30974 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9927 /* 30980 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9928 /* 30982 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9929 /* 30986 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9930 /* 30990 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
9931 /* 30994 */ // MIs[5] vB
9932 /* 30994 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9933 /* 30999 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
9934 /* 31003 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9935 /* 31007 */ // MIs[6] vC
9936 /* 31007 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
9937 /* 31012 */ // MIs[6] vA
9938 /* 31012 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
9939 /* 31017 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9940 /* 31019 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9941 /* 31019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9942 /* 31022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9943 /* 31024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
9944 /* 31028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9945 /* 31032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
9946 /* 31036 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9947 /* 31046 */ GIR_RootConstrainSelectedInstOperands,
9948 /* 31047 */ // GIR_Coverage, 5131,
9949 /* 31047 */ GIR_EraseRootFromParent_Done,
9950 /* 31048 */ // Label 448: @31048
9951 /* 31048 */ GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(31186), // Rule ID 5132 //
9952 /* 31053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9953 /* 31056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9954 /* 31060 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9955 /* 31064 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9956 /* 31068 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9957 /* 31072 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9958 /* 31076 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9959 /* 31080 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
9960 /* 31084 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9961 /* 31088 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
9962 /* 31092 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
9963 /* 31096 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
9964 /* 31100 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
9965 /* 31104 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
9966 /* 31108 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
9967 /* 31112 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9968 /* 31118 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
9969 /* 31120 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
9970 /* 31124 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
9971 /* 31128 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
9972 /* 31132 */ // MIs[5] vA
9973 /* 31132 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
9974 /* 31137 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
9975 /* 31141 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
9976 /* 31145 */ // MIs[6] vB
9977 /* 31145 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
9978 /* 31150 */ // MIs[6] vC
9979 /* 31150 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
9980 /* 31155 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
9981 /* 31157 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
9982 /* 31157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
9983 /* 31160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
9984 /* 31162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
9985 /* 31166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
9986 /* 31170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
9987 /* 31174 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
9988 /* 31184 */ GIR_RootConstrainSelectedInstOperands,
9989 /* 31185 */ // GIR_Coverage, 5132,
9990 /* 31185 */ GIR_EraseRootFromParent_Done,
9991 /* 31186 */ // Label 449: @31186
9992 /* 31186 */ GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(31324), // Rule ID 5133 //
9993 /* 31191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
9994 /* 31194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
9995 /* 31198 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9996 /* 31202 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9997 /* 31206 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
9998 /* 31210 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
9999 /* 31214 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10000 /* 31218 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10001 /* 31222 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10002 /* 31226 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10003 /* 31230 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10004 /* 31234 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10005 /* 31238 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10006 /* 31242 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10007 /* 31246 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10008 /* 31250 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10009 /* 31256 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10010 /* 31258 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10011 /* 31262 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10012 /* 31266 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10013 /* 31270 */ // MIs[5] vA
10014 /* 31270 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10015 /* 31275 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10016 /* 31279 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10017 /* 31283 */ // MIs[6] vC
10018 /* 31283 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10019 /* 31288 */ // MIs[6] vB
10020 /* 31288 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10021 /* 31293 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10022 /* 31295 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10023 /* 31295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10024 /* 31298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10025 /* 31300 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
10026 /* 31304 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
10027 /* 31308 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
10028 /* 31312 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10029 /* 31322 */ GIR_RootConstrainSelectedInstOperands,
10030 /* 31323 */ // GIR_Coverage, 5133,
10031 /* 31323 */ GIR_EraseRootFromParent_Done,
10032 /* 31324 */ // Label 450: @31324
10033 /* 31324 */ GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(31462), // Rule ID 5140 //
10034 /* 31329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10035 /* 31332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10036 /* 31336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10037 /* 31340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10038 /* 31344 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10039 /* 31348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10040 /* 31352 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10041 /* 31356 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10042 /* 31360 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10043 /* 31364 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10044 /* 31368 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10045 /* 31372 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10046 /* 31376 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10047 /* 31380 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10048 /* 31384 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10049 /* 31388 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10050 /* 31394 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10051 /* 31396 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10052 /* 31400 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10053 /* 31404 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10054 /* 31408 */ // MIs[5] vC
10055 /* 31408 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10056 /* 31413 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10057 /* 31417 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10058 /* 31421 */ // MIs[6] vA
10059 /* 31421 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10060 /* 31426 */ // MIs[6] vB
10061 /* 31426 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
10062 /* 31431 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10063 /* 31433 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10064 /* 31433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10065 /* 31436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10066 /* 31438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10067 /* 31442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10068 /* 31446 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
10069 /* 31450 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10070 /* 31460 */ GIR_RootConstrainSelectedInstOperands,
10071 /* 31461 */ // GIR_Coverage, 5140,
10072 /* 31461 */ GIR_EraseRootFromParent_Done,
10073 /* 31462 */ // Label 451: @31462
10074 /* 31462 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(31600), // Rule ID 5141 //
10075 /* 31467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10076 /* 31470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10077 /* 31474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10078 /* 31478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10079 /* 31482 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10080 /* 31486 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10081 /* 31490 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10082 /* 31494 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10083 /* 31498 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10084 /* 31502 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10085 /* 31506 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10086 /* 31510 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10087 /* 31514 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10088 /* 31518 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10089 /* 31522 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10090 /* 31526 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10091 /* 31532 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10092 /* 31534 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10093 /* 31538 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10094 /* 31542 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10095 /* 31546 */ // MIs[5] vC
10096 /* 31546 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10097 /* 31551 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10098 /* 31555 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10099 /* 31559 */ // MIs[6] vB
10100 /* 31559 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10101 /* 31564 */ // MIs[6] vA
10102 /* 31564 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10103 /* 31569 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10104 /* 31571 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10105 /* 31571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10106 /* 31574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10107 /* 31576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10108 /* 31580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10109 /* 31584 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
10110 /* 31588 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10111 /* 31598 */ GIR_RootConstrainSelectedInstOperands,
10112 /* 31599 */ // GIR_Coverage, 5141,
10113 /* 31599 */ GIR_EraseRootFromParent_Done,
10114 /* 31600 */ // Label 452: @31600
10115 /* 31600 */ GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(31738), // Rule ID 5142 //
10116 /* 31605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10117 /* 31608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10118 /* 31612 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10119 /* 31616 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10120 /* 31620 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10121 /* 31624 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10122 /* 31628 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10123 /* 31632 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10124 /* 31636 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10125 /* 31640 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10126 /* 31644 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10127 /* 31648 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10128 /* 31652 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10129 /* 31656 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10130 /* 31660 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10131 /* 31664 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10132 /* 31670 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10133 /* 31672 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10134 /* 31676 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10135 /* 31680 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10136 /* 31684 */ // MIs[5] vB
10137 /* 31684 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10138 /* 31689 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10139 /* 31693 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10140 /* 31697 */ // MIs[6] vA
10141 /* 31697 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10142 /* 31702 */ // MIs[6] vC
10143 /* 31702 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
10144 /* 31707 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10145 /* 31709 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10146 /* 31709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10147 /* 31712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10148 /* 31714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10149 /* 31718 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10150 /* 31722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
10151 /* 31726 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10152 /* 31736 */ GIR_RootConstrainSelectedInstOperands,
10153 /* 31737 */ // GIR_Coverage, 5142,
10154 /* 31737 */ GIR_EraseRootFromParent_Done,
10155 /* 31738 */ // Label 453: @31738
10156 /* 31738 */ GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(31876), // Rule ID 5143 //
10157 /* 31743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10158 /* 31746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10159 /* 31750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10160 /* 31754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10161 /* 31758 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10162 /* 31762 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10163 /* 31766 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10164 /* 31770 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10165 /* 31774 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10166 /* 31778 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10167 /* 31782 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10168 /* 31786 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10169 /* 31790 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10170 /* 31794 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10171 /* 31798 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10172 /* 31802 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10173 /* 31808 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10174 /* 31810 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10175 /* 31814 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10176 /* 31818 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10177 /* 31822 */ // MIs[5] vB
10178 /* 31822 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10179 /* 31827 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10180 /* 31831 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10181 /* 31835 */ // MIs[6] vC
10182 /* 31835 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10183 /* 31840 */ // MIs[6] vA
10184 /* 31840 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10185 /* 31845 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10186 /* 31847 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10187 /* 31847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10188 /* 31850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10189 /* 31852 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10190 /* 31856 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10191 /* 31860 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
10192 /* 31864 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10193 /* 31874 */ GIR_RootConstrainSelectedInstOperands,
10194 /* 31875 */ // GIR_Coverage, 5143,
10195 /* 31875 */ GIR_EraseRootFromParent_Done,
10196 /* 31876 */ // Label 454: @31876
10197 /* 31876 */ GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(32014), // Rule ID 5144 //
10198 /* 31881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10199 /* 31884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10200 /* 31888 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10201 /* 31892 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10202 /* 31896 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10203 /* 31900 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10204 /* 31904 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10205 /* 31908 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10206 /* 31912 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10207 /* 31916 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10208 /* 31920 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10209 /* 31924 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10210 /* 31928 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10211 /* 31932 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10212 /* 31936 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10213 /* 31940 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10214 /* 31946 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10215 /* 31948 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10216 /* 31952 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10217 /* 31956 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10218 /* 31960 */ // MIs[5] vA
10219 /* 31960 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10220 /* 31965 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10221 /* 31969 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10222 /* 31973 */ // MIs[6] vB
10223 /* 31973 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10224 /* 31978 */ // MIs[6] vC
10225 /* 31978 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
10226 /* 31983 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10227 /* 31985 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10228 /* 31985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10229 /* 31988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10230 /* 31990 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10231 /* 31994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10232 /* 31998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
10233 /* 32002 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10234 /* 32012 */ GIR_RootConstrainSelectedInstOperands,
10235 /* 32013 */ // GIR_Coverage, 5144,
10236 /* 32013 */ GIR_EraseRootFromParent_Done,
10237 /* 32014 */ // Label 455: @32014
10238 /* 32014 */ GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(32152), // Rule ID 5145 //
10239 /* 32019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10240 /* 32022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10241 /* 32026 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10242 /* 32030 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10243 /* 32034 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10244 /* 32038 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10245 /* 32042 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10246 /* 32046 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10247 /* 32050 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10248 /* 32054 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10249 /* 32058 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10250 /* 32062 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10251 /* 32066 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10252 /* 32070 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10253 /* 32074 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10254 /* 32078 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10255 /* 32084 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10256 /* 32086 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10257 /* 32090 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10258 /* 32094 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10259 /* 32098 */ // MIs[5] vA
10260 /* 32098 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10261 /* 32103 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10262 /* 32107 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10263 /* 32111 */ // MIs[6] vC
10264 /* 32111 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10265 /* 32116 */ // MIs[6] vB
10266 /* 32116 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
10267 /* 32121 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10268 /* 32123 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10269 /* 32123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10270 /* 32126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10271 /* 32128 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10272 /* 32132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10273 /* 32136 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
10274 /* 32140 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10275 /* 32150 */ GIR_RootConstrainSelectedInstOperands,
10276 /* 32151 */ // GIR_Coverage, 5145,
10277 /* 32151 */ GIR_EraseRootFromParent_Done,
10278 /* 32152 */ // Label 456: @32152
10279 /* 32152 */ GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(32290), // Rule ID 5152 //
10280 /* 32157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10281 /* 32160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10282 /* 32164 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10283 /* 32168 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10284 /* 32172 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10285 /* 32176 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10286 /* 32180 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10287 /* 32184 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10288 /* 32188 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10289 /* 32192 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10290 /* 32196 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10291 /* 32200 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10292 /* 32204 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10293 /* 32208 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10294 /* 32212 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10295 /* 32216 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10296 /* 32222 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10297 /* 32224 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10298 /* 32228 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10299 /* 32232 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10300 /* 32236 */ // MIs[5] vC
10301 /* 32236 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10302 /* 32241 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10303 /* 32245 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10304 /* 32249 */ // MIs[6] vA
10305 /* 32249 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10306 /* 32254 */ // MIs[6] vB
10307 /* 32254 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
10308 /* 32259 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10309 /* 32261 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10310 /* 32261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10311 /* 32264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10312 /* 32266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
10313 /* 32270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10314 /* 32274 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10315 /* 32278 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10316 /* 32288 */ GIR_RootConstrainSelectedInstOperands,
10317 /* 32289 */ // GIR_Coverage, 5152,
10318 /* 32289 */ GIR_EraseRootFromParent_Done,
10319 /* 32290 */ // Label 457: @32290
10320 /* 32290 */ GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(32428), // Rule ID 5153 //
10321 /* 32295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10322 /* 32298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10323 /* 32302 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10324 /* 32306 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10325 /* 32310 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10326 /* 32314 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10327 /* 32318 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10328 /* 32322 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10329 /* 32326 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10330 /* 32330 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10331 /* 32334 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10332 /* 32338 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10333 /* 32342 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10334 /* 32346 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10335 /* 32350 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10336 /* 32354 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10337 /* 32360 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10338 /* 32362 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10339 /* 32366 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10340 /* 32370 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10341 /* 32374 */ // MIs[5] vC
10342 /* 32374 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10343 /* 32379 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10344 /* 32383 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10345 /* 32387 */ // MIs[6] vB
10346 /* 32387 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10347 /* 32392 */ // MIs[6] vA
10348 /* 32392 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
10349 /* 32397 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10350 /* 32399 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10351 /* 32399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10352 /* 32402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10353 /* 32404 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
10354 /* 32408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10355 /* 32412 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10356 /* 32416 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10357 /* 32426 */ GIR_RootConstrainSelectedInstOperands,
10358 /* 32427 */ // GIR_Coverage, 5153,
10359 /* 32427 */ GIR_EraseRootFromParent_Done,
10360 /* 32428 */ // Label 458: @32428
10361 /* 32428 */ GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(32566), // Rule ID 5154 //
10362 /* 32433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10363 /* 32436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10364 /* 32440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10365 /* 32444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10366 /* 32448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10367 /* 32452 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10368 /* 32456 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10369 /* 32460 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10370 /* 32464 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10371 /* 32468 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10372 /* 32472 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10373 /* 32476 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10374 /* 32480 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10375 /* 32484 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10376 /* 32488 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10377 /* 32492 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10378 /* 32498 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10379 /* 32500 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10380 /* 32504 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10381 /* 32508 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10382 /* 32512 */ // MIs[5] vB
10383 /* 32512 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10384 /* 32517 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10385 /* 32521 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10386 /* 32525 */ // MIs[6] vA
10387 /* 32525 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10388 /* 32530 */ // MIs[6] vC
10389 /* 32530 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10390 /* 32535 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10391 /* 32537 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10392 /* 32537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10393 /* 32540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10394 /* 32542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
10395 /* 32546 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10396 /* 32550 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10397 /* 32554 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10398 /* 32564 */ GIR_RootConstrainSelectedInstOperands,
10399 /* 32565 */ // GIR_Coverage, 5154,
10400 /* 32565 */ GIR_EraseRootFromParent_Done,
10401 /* 32566 */ // Label 459: @32566
10402 /* 32566 */ GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(32704), // Rule ID 5155 //
10403 /* 32571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10404 /* 32574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10405 /* 32578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10406 /* 32582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10407 /* 32586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10408 /* 32590 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10409 /* 32594 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10410 /* 32598 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10411 /* 32602 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10412 /* 32606 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10413 /* 32610 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10414 /* 32614 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10415 /* 32618 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10416 /* 32622 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10417 /* 32626 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10418 /* 32630 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10419 /* 32636 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10420 /* 32638 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10421 /* 32642 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10422 /* 32646 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10423 /* 32650 */ // MIs[5] vB
10424 /* 32650 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10425 /* 32655 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10426 /* 32659 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10427 /* 32663 */ // MIs[6] vC
10428 /* 32663 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10429 /* 32668 */ // MIs[6] vA
10430 /* 32668 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
10431 /* 32673 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10432 /* 32675 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10433 /* 32675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10434 /* 32678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10435 /* 32680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
10436 /* 32684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10437 /* 32688 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10438 /* 32692 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10439 /* 32702 */ GIR_RootConstrainSelectedInstOperands,
10440 /* 32703 */ // GIR_Coverage, 5155,
10441 /* 32703 */ GIR_EraseRootFromParent_Done,
10442 /* 32704 */ // Label 460: @32704
10443 /* 32704 */ GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(32842), // Rule ID 5156 //
10444 /* 32709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10445 /* 32712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10446 /* 32716 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10447 /* 32720 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10448 /* 32724 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10449 /* 32728 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10450 /* 32732 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10451 /* 32736 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10452 /* 32740 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10453 /* 32744 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10454 /* 32748 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10455 /* 32752 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10456 /* 32756 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10457 /* 32760 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10458 /* 32764 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10459 /* 32768 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10460 /* 32774 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10461 /* 32776 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10462 /* 32780 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10463 /* 32784 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10464 /* 32788 */ // MIs[5] vA
10465 /* 32788 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10466 /* 32793 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10467 /* 32797 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10468 /* 32801 */ // MIs[6] vB
10469 /* 32801 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10470 /* 32806 */ // MIs[6] vC
10471 /* 32806 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10472 /* 32811 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10473 /* 32813 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10474 /* 32813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10475 /* 32816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10476 /* 32818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
10477 /* 32822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10478 /* 32826 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10479 /* 32830 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10480 /* 32840 */ GIR_RootConstrainSelectedInstOperands,
10481 /* 32841 */ // GIR_Coverage, 5156,
10482 /* 32841 */ GIR_EraseRootFromParent_Done,
10483 /* 32842 */ // Label 461: @32842
10484 /* 32842 */ GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(32980), // Rule ID 5157 //
10485 /* 32847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10486 /* 32850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10487 /* 32854 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10488 /* 32858 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10489 /* 32862 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10490 /* 32866 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10491 /* 32870 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10492 /* 32874 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10493 /* 32878 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10494 /* 32882 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10495 /* 32886 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10496 /* 32890 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10497 /* 32894 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10498 /* 32898 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10499 /* 32902 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10500 /* 32906 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10501 /* 32912 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10502 /* 32914 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10503 /* 32918 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10504 /* 32922 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10505 /* 32926 */ // MIs[5] vA
10506 /* 32926 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10507 /* 32931 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10508 /* 32935 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10509 /* 32939 */ // MIs[6] vC
10510 /* 32939 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10511 /* 32944 */ // MIs[6] vB
10512 /* 32944 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
10513 /* 32949 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10514 /* 32951 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10515 /* 32951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10516 /* 32954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10517 /* 32956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
10518 /* 32960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10519 /* 32964 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10520 /* 32968 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10521 /* 32978 */ GIR_RootConstrainSelectedInstOperands,
10522 /* 32979 */ // GIR_Coverage, 5157,
10523 /* 32979 */ GIR_EraseRootFromParent_Done,
10524 /* 32980 */ // Label 462: @32980
10525 /* 32980 */ GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(33118), // Rule ID 5164 //
10526 /* 32985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10527 /* 32988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10528 /* 32992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10529 /* 32996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10530 /* 33000 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10531 /* 33004 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10532 /* 33008 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10533 /* 33012 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10534 /* 33016 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10535 /* 33020 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10536 /* 33024 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10537 /* 33028 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10538 /* 33032 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10539 /* 33036 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10540 /* 33040 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10541 /* 33044 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10542 /* 33050 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10543 /* 33052 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10544 /* 33056 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10545 /* 33060 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10546 /* 33064 */ // MIs[5] vC
10547 /* 33064 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10548 /* 33069 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10549 /* 33073 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10550 /* 33077 */ // MIs[6] vA
10551 /* 33077 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10552 /* 33082 */ // MIs[6] vB
10553 /* 33082 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
10554 /* 33087 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10555 /* 33089 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10556 /* 33089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10557 /* 33092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10558 /* 33094 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10559 /* 33098 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10560 /* 33102 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
10561 /* 33106 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10562 /* 33116 */ GIR_RootConstrainSelectedInstOperands,
10563 /* 33117 */ // GIR_Coverage, 5164,
10564 /* 33117 */ GIR_EraseRootFromParent_Done,
10565 /* 33118 */ // Label 463: @33118
10566 /* 33118 */ GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(33256), // Rule ID 5165 //
10567 /* 33123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10568 /* 33126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10569 /* 33130 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10570 /* 33134 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10571 /* 33138 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10572 /* 33142 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10573 /* 33146 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10574 /* 33150 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10575 /* 33154 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10576 /* 33158 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10577 /* 33162 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10578 /* 33166 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10579 /* 33170 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10580 /* 33174 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10581 /* 33178 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10582 /* 33182 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10583 /* 33188 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10584 /* 33190 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10585 /* 33194 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10586 /* 33198 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10587 /* 33202 */ // MIs[5] vC
10588 /* 33202 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10589 /* 33207 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10590 /* 33211 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10591 /* 33215 */ // MIs[6] vB
10592 /* 33215 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10593 /* 33220 */ // MIs[6] vA
10594 /* 33220 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10595 /* 33225 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10596 /* 33227 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10597 /* 33227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10598 /* 33230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10599 /* 33232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10600 /* 33236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10601 /* 33240 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
10602 /* 33244 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10603 /* 33254 */ GIR_RootConstrainSelectedInstOperands,
10604 /* 33255 */ // GIR_Coverage, 5165,
10605 /* 33255 */ GIR_EraseRootFromParent_Done,
10606 /* 33256 */ // Label 464: @33256
10607 /* 33256 */ GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(33394), // Rule ID 5166 //
10608 /* 33261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10609 /* 33264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10610 /* 33268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10611 /* 33272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10612 /* 33276 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10613 /* 33280 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10614 /* 33284 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10615 /* 33288 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10616 /* 33292 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10617 /* 33296 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10618 /* 33300 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10619 /* 33304 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10620 /* 33308 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10621 /* 33312 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10622 /* 33316 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10623 /* 33320 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10624 /* 33326 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10625 /* 33328 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10626 /* 33332 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10627 /* 33336 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10628 /* 33340 */ // MIs[5] vB
10629 /* 33340 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10630 /* 33345 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10631 /* 33349 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10632 /* 33353 */ // MIs[6] vA
10633 /* 33353 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10634 /* 33358 */ // MIs[6] vC
10635 /* 33358 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
10636 /* 33363 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10637 /* 33365 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10638 /* 33365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10639 /* 33368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10640 /* 33370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10641 /* 33374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10642 /* 33378 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
10643 /* 33382 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10644 /* 33392 */ GIR_RootConstrainSelectedInstOperands,
10645 /* 33393 */ // GIR_Coverage, 5166,
10646 /* 33393 */ GIR_EraseRootFromParent_Done,
10647 /* 33394 */ // Label 465: @33394
10648 /* 33394 */ GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(33532), // Rule ID 5167 //
10649 /* 33399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10650 /* 33402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10651 /* 33406 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10652 /* 33410 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10653 /* 33414 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10654 /* 33418 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10655 /* 33422 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10656 /* 33426 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10657 /* 33430 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10658 /* 33434 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10659 /* 33438 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10660 /* 33442 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10661 /* 33446 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10662 /* 33450 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10663 /* 33454 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10664 /* 33458 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10665 /* 33464 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10666 /* 33466 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10667 /* 33470 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10668 /* 33474 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10669 /* 33478 */ // MIs[5] vB
10670 /* 33478 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10671 /* 33483 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10672 /* 33487 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10673 /* 33491 */ // MIs[6] vC
10674 /* 33491 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10675 /* 33496 */ // MIs[6] vA
10676 /* 33496 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10677 /* 33501 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10678 /* 33503 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10679 /* 33503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10680 /* 33506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10681 /* 33508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10682 /* 33512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10683 /* 33516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
10684 /* 33520 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10685 /* 33530 */ GIR_RootConstrainSelectedInstOperands,
10686 /* 33531 */ // GIR_Coverage, 5167,
10687 /* 33531 */ GIR_EraseRootFromParent_Done,
10688 /* 33532 */ // Label 466: @33532
10689 /* 33532 */ GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(33670), // Rule ID 5168 //
10690 /* 33537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10691 /* 33540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10692 /* 33544 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10693 /* 33548 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10694 /* 33552 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10695 /* 33556 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10696 /* 33560 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10697 /* 33564 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10698 /* 33568 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10699 /* 33572 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10700 /* 33576 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10701 /* 33580 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10702 /* 33584 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10703 /* 33588 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10704 /* 33592 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10705 /* 33596 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10706 /* 33602 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10707 /* 33604 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10708 /* 33608 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10709 /* 33612 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10710 /* 33616 */ // MIs[5] vA
10711 /* 33616 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10712 /* 33621 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10713 /* 33625 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10714 /* 33629 */ // MIs[6] vB
10715 /* 33629 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10716 /* 33634 */ // MIs[6] vC
10717 /* 33634 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
10718 /* 33639 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10719 /* 33641 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10720 /* 33641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10721 /* 33644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10722 /* 33646 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10723 /* 33650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10724 /* 33654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
10725 /* 33658 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10726 /* 33668 */ GIR_RootConstrainSelectedInstOperands,
10727 /* 33669 */ // GIR_Coverage, 5168,
10728 /* 33669 */ GIR_EraseRootFromParent_Done,
10729 /* 33670 */ // Label 467: @33670
10730 /* 33670 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(33808), // Rule ID 5169 //
10731 /* 33675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10732 /* 33678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10733 /* 33682 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10734 /* 33686 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10735 /* 33690 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10736 /* 33694 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10737 /* 33698 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10738 /* 33702 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10739 /* 33706 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10740 /* 33710 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10741 /* 33714 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10742 /* 33718 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10743 /* 33722 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10744 /* 33726 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10745 /* 33730 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10746 /* 33734 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10747 /* 33740 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10748 /* 33742 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10749 /* 33746 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10750 /* 33750 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10751 /* 33754 */ // MIs[5] vA
10752 /* 33754 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10753 /* 33759 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10754 /* 33763 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10755 /* 33767 */ // MIs[6] vC
10756 /* 33767 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10757 /* 33772 */ // MIs[6] vB
10758 /* 33772 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
10759 /* 33777 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10760 /* 33779 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10761 /* 33779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10762 /* 33782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10763 /* 33784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
10764 /* 33788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
10765 /* 33792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
10766 /* 33796 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10767 /* 33806 */ GIR_RootConstrainSelectedInstOperands,
10768 /* 33807 */ // GIR_Coverage, 5169,
10769 /* 33807 */ GIR_EraseRootFromParent_Done,
10770 /* 33808 */ // Label 468: @33808
10771 /* 33808 */ GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(33946), // Rule ID 5176 //
10772 /* 33813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10773 /* 33816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10774 /* 33820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10775 /* 33824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10776 /* 33828 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10777 /* 33832 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10778 /* 33836 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10779 /* 33840 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10780 /* 33844 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10781 /* 33848 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10782 /* 33852 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10783 /* 33856 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10784 /* 33860 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10785 /* 33864 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10786 /* 33868 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10787 /* 33872 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10788 /* 33878 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10789 /* 33880 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10790 /* 33884 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10791 /* 33888 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10792 /* 33892 */ // MIs[5] vC
10793 /* 33892 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10794 /* 33897 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10795 /* 33901 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10796 /* 33905 */ // MIs[6] vA
10797 /* 33905 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10798 /* 33910 */ // MIs[6] vB
10799 /* 33910 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
10800 /* 33915 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10801 /* 33917 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10802 /* 33917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10803 /* 33920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10804 /* 33922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
10805 /* 33926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10806 /* 33930 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10807 /* 33934 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10808 /* 33944 */ GIR_RootConstrainSelectedInstOperands,
10809 /* 33945 */ // GIR_Coverage, 5176,
10810 /* 33945 */ GIR_EraseRootFromParent_Done,
10811 /* 33946 */ // Label 469: @33946
10812 /* 33946 */ GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(34084), // Rule ID 5177 //
10813 /* 33951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10814 /* 33954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10815 /* 33958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10816 /* 33962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10817 /* 33966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10818 /* 33970 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10819 /* 33974 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10820 /* 33978 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10821 /* 33982 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10822 /* 33986 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10823 /* 33990 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10824 /* 33994 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10825 /* 33998 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10826 /* 34002 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10827 /* 34006 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10828 /* 34010 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10829 /* 34016 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10830 /* 34018 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10831 /* 34022 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10832 /* 34026 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10833 /* 34030 */ // MIs[5] vC
10834 /* 34030 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10835 /* 34035 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10836 /* 34039 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10837 /* 34043 */ // MIs[6] vB
10838 /* 34043 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10839 /* 34048 */ // MIs[6] vA
10840 /* 34048 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
10841 /* 34053 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10842 /* 34055 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10843 /* 34055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10844 /* 34058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10845 /* 34060 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
10846 /* 34064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10847 /* 34068 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10848 /* 34072 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10849 /* 34082 */ GIR_RootConstrainSelectedInstOperands,
10850 /* 34083 */ // GIR_Coverage, 5177,
10851 /* 34083 */ GIR_EraseRootFromParent_Done,
10852 /* 34084 */ // Label 470: @34084
10853 /* 34084 */ GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(34222), // Rule ID 5178 //
10854 /* 34089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10855 /* 34092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10856 /* 34096 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10857 /* 34100 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10858 /* 34104 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10859 /* 34108 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10860 /* 34112 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10861 /* 34116 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10862 /* 34120 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10863 /* 34124 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10864 /* 34128 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10865 /* 34132 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10866 /* 34136 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10867 /* 34140 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10868 /* 34144 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10869 /* 34148 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10870 /* 34154 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10871 /* 34156 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10872 /* 34160 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10873 /* 34164 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10874 /* 34168 */ // MIs[5] vB
10875 /* 34168 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10876 /* 34173 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10877 /* 34177 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10878 /* 34181 */ // MIs[6] vA
10879 /* 34181 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10880 /* 34186 */ // MIs[6] vC
10881 /* 34186 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10882 /* 34191 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10883 /* 34193 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10884 /* 34193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10885 /* 34196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10886 /* 34198 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
10887 /* 34202 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10888 /* 34206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10889 /* 34210 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10890 /* 34220 */ GIR_RootConstrainSelectedInstOperands,
10891 /* 34221 */ // GIR_Coverage, 5178,
10892 /* 34221 */ GIR_EraseRootFromParent_Done,
10893 /* 34222 */ // Label 471: @34222
10894 /* 34222 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(34360), // Rule ID 5179 //
10895 /* 34227 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10896 /* 34230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10897 /* 34234 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10898 /* 34238 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10899 /* 34242 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10900 /* 34246 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10901 /* 34250 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10902 /* 34254 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10903 /* 34258 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10904 /* 34262 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10905 /* 34266 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10906 /* 34270 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10907 /* 34274 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10908 /* 34278 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10909 /* 34282 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10910 /* 34286 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10911 /* 34292 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10912 /* 34294 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10913 /* 34298 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10914 /* 34302 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10915 /* 34306 */ // MIs[5] vB
10916 /* 34306 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10917 /* 34311 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10918 /* 34315 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10919 /* 34319 */ // MIs[6] vC
10920 /* 34319 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
10921 /* 34324 */ // MIs[6] vA
10922 /* 34324 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
10923 /* 34329 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10924 /* 34331 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10925 /* 34331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10926 /* 34334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10927 /* 34336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
10928 /* 34340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10929 /* 34344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10930 /* 34348 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10931 /* 34358 */ GIR_RootConstrainSelectedInstOperands,
10932 /* 34359 */ // GIR_Coverage, 5179,
10933 /* 34359 */ GIR_EraseRootFromParent_Done,
10934 /* 34360 */ // Label 472: @34360
10935 /* 34360 */ GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(34498), // Rule ID 5180 //
10936 /* 34365 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10937 /* 34368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10938 /* 34372 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10939 /* 34376 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10940 /* 34380 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10941 /* 34384 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10942 /* 34388 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10943 /* 34392 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10944 /* 34396 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10945 /* 34400 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10946 /* 34404 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10947 /* 34408 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10948 /* 34412 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10949 /* 34416 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10950 /* 34420 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10951 /* 34424 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10952 /* 34430 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10953 /* 34432 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10954 /* 34436 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10955 /* 34440 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10956 /* 34444 */ // MIs[5] vA
10957 /* 34444 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10958 /* 34449 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
10959 /* 34453 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
10960 /* 34457 */ // MIs[6] vB
10961 /* 34457 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
10962 /* 34462 */ // MIs[6] vC
10963 /* 34462 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
10964 /* 34467 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
10965 /* 34469 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
10966 /* 34469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
10967 /* 34472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
10968 /* 34474 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
10969 /* 34478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
10970 /* 34482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
10971 /* 34486 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
10972 /* 34496 */ GIR_RootConstrainSelectedInstOperands,
10973 /* 34497 */ // GIR_Coverage, 5180,
10974 /* 34497 */ GIR_EraseRootFromParent_Done,
10975 /* 34498 */ // Label 473: @34498
10976 /* 34498 */ GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(34636), // Rule ID 5181 //
10977 /* 34503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
10978 /* 34506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
10979 /* 34510 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10980 /* 34514 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
10981 /* 34518 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10982 /* 34522 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10983 /* 34526 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
10984 /* 34530 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
10985 /* 34534 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
10986 /* 34538 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
10987 /* 34542 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
10988 /* 34546 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
10989 /* 34550 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
10990 /* 34554 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
10991 /* 34558 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
10992 /* 34562 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10993 /* 34568 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
10994 /* 34570 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
10995 /* 34574 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
10996 /* 34578 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
10997 /* 34582 */ // MIs[5] vA
10998 /* 34582 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
10999 /* 34587 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
11000 /* 34591 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11001 /* 34595 */ // MIs[6] vC
11002 /* 34595 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11003 /* 34600 */ // MIs[6] vB
11004 /* 34600 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11005 /* 34605 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11006 /* 34607 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11007 /* 34607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11008 /* 34610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11009 /* 34612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
11010 /* 34616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
11011 /* 34620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
11012 /* 34624 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11013 /* 34634 */ GIR_RootConstrainSelectedInstOperands,
11014 /* 34635 */ // GIR_Coverage, 5181,
11015 /* 34635 */ GIR_EraseRootFromParent_Done,
11016 /* 34636 */ // Label 474: @34636
11017 /* 34636 */ GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(34774), // Rule ID 5188 //
11018 /* 34641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11019 /* 34644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11020 /* 34648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11021 /* 34652 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11022 /* 34656 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11023 /* 34660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11024 /* 34664 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11025 /* 34668 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11026 /* 34672 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11027 /* 34676 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11028 /* 34680 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
11029 /* 34684 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11030 /* 34688 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11031 /* 34692 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11032 /* 34696 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11033 /* 34700 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11034 /* 34706 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11035 /* 34708 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11036 /* 34712 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11037 /* 34716 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
11038 /* 34720 */ // MIs[5] vC
11039 /* 34720 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11040 /* 34725 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
11041 /* 34729 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11042 /* 34733 */ // MIs[6] vA
11043 /* 34733 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
11044 /* 34738 */ // MIs[6] vB
11045 /* 34738 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11046 /* 34743 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11047 /* 34745 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11048 /* 34745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11049 /* 34748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11050 /* 34750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
11051 /* 34754 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11052 /* 34758 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
11053 /* 34762 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11054 /* 34772 */ GIR_RootConstrainSelectedInstOperands,
11055 /* 34773 */ // GIR_Coverage, 5188,
11056 /* 34773 */ GIR_EraseRootFromParent_Done,
11057 /* 34774 */ // Label 475: @34774
11058 /* 34774 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(34912), // Rule ID 5189 //
11059 /* 34779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11060 /* 34782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11061 /* 34786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11062 /* 34790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11063 /* 34794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11064 /* 34798 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11065 /* 34802 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11066 /* 34806 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11067 /* 34810 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11068 /* 34814 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11069 /* 34818 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
11070 /* 34822 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11071 /* 34826 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11072 /* 34830 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11073 /* 34834 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11074 /* 34838 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11075 /* 34844 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11076 /* 34846 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11077 /* 34850 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11078 /* 34854 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
11079 /* 34858 */ // MIs[5] vC
11080 /* 34858 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11081 /* 34863 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
11082 /* 34867 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11083 /* 34871 */ // MIs[6] vB
11084 /* 34871 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11085 /* 34876 */ // MIs[6] vA
11086 /* 34876 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
11087 /* 34881 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11088 /* 34883 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11089 /* 34883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11090 /* 34886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11091 /* 34888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
11092 /* 34892 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11093 /* 34896 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
11094 /* 34900 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11095 /* 34910 */ GIR_RootConstrainSelectedInstOperands,
11096 /* 34911 */ // GIR_Coverage, 5189,
11097 /* 34911 */ GIR_EraseRootFromParent_Done,
11098 /* 34912 */ // Label 476: @34912
11099 /* 34912 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(35050), // Rule ID 5190 //
11100 /* 34917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11101 /* 34920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11102 /* 34924 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11103 /* 34928 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11104 /* 34932 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11105 /* 34936 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11106 /* 34940 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11107 /* 34944 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11108 /* 34948 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11109 /* 34952 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11110 /* 34956 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
11111 /* 34960 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11112 /* 34964 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11113 /* 34968 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11114 /* 34972 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11115 /* 34976 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11116 /* 34982 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11117 /* 34984 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11118 /* 34988 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11119 /* 34992 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
11120 /* 34996 */ // MIs[5] vB
11121 /* 34996 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11122 /* 35001 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
11123 /* 35005 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11124 /* 35009 */ // MIs[6] vA
11125 /* 35009 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
11126 /* 35014 */ // MIs[6] vC
11127 /* 35014 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11128 /* 35019 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11129 /* 35021 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11130 /* 35021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11131 /* 35024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11132 /* 35026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
11133 /* 35030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11134 /* 35034 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
11135 /* 35038 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11136 /* 35048 */ GIR_RootConstrainSelectedInstOperands,
11137 /* 35049 */ // GIR_Coverage, 5190,
11138 /* 35049 */ GIR_EraseRootFromParent_Done,
11139 /* 35050 */ // Label 477: @35050
11140 /* 35050 */ GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(35188), // Rule ID 5191 //
11141 /* 35055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11142 /* 35058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11143 /* 35062 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11144 /* 35066 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11145 /* 35070 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11146 /* 35074 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11147 /* 35078 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11148 /* 35082 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11149 /* 35086 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11150 /* 35090 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11151 /* 35094 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
11152 /* 35098 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11153 /* 35102 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11154 /* 35106 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11155 /* 35110 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11156 /* 35114 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11157 /* 35120 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11158 /* 35122 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11159 /* 35126 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11160 /* 35130 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
11161 /* 35134 */ // MIs[5] vB
11162 /* 35134 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11163 /* 35139 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
11164 /* 35143 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11165 /* 35147 */ // MIs[6] vC
11166 /* 35147 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11167 /* 35152 */ // MIs[6] vA
11168 /* 35152 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
11169 /* 35157 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11170 /* 35159 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11171 /* 35159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11172 /* 35162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11173 /* 35164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
11174 /* 35168 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11175 /* 35172 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
11176 /* 35176 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11177 /* 35186 */ GIR_RootConstrainSelectedInstOperands,
11178 /* 35187 */ // GIR_Coverage, 5191,
11179 /* 35187 */ GIR_EraseRootFromParent_Done,
11180 /* 35188 */ // Label 478: @35188
11181 /* 35188 */ GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(35326), // Rule ID 5192 //
11182 /* 35193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11183 /* 35196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11184 /* 35200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11185 /* 35204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11186 /* 35208 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11187 /* 35212 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11188 /* 35216 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11189 /* 35220 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11190 /* 35224 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11191 /* 35228 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11192 /* 35232 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
11193 /* 35236 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11194 /* 35240 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11195 /* 35244 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11196 /* 35248 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11197 /* 35252 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11198 /* 35258 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11199 /* 35260 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11200 /* 35264 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11201 /* 35268 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
11202 /* 35272 */ // MIs[5] vA
11203 /* 35272 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
11204 /* 35277 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
11205 /* 35281 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11206 /* 35285 */ // MIs[6] vB
11207 /* 35285 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11208 /* 35290 */ // MIs[6] vC
11209 /* 35290 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11210 /* 35295 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11211 /* 35297 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11212 /* 35297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11213 /* 35300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11214 /* 35302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
11215 /* 35306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11216 /* 35310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
11217 /* 35314 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11218 /* 35324 */ GIR_RootConstrainSelectedInstOperands,
11219 /* 35325 */ // GIR_Coverage, 5192,
11220 /* 35325 */ GIR_EraseRootFromParent_Done,
11221 /* 35326 */ // Label 479: @35326
11222 /* 35326 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(35464), // Rule ID 5193 //
11223 /* 35331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11224 /* 35334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11225 /* 35338 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11226 /* 35342 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11227 /* 35346 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11228 /* 35350 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11229 /* 35354 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11230 /* 35358 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11231 /* 35362 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11232 /* 35366 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11233 /* 35370 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
11234 /* 35374 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11235 /* 35378 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11236 /* 35382 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11237 /* 35386 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11238 /* 35390 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11239 /* 35396 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11240 /* 35398 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11241 /* 35402 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11242 /* 35406 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
11243 /* 35410 */ // MIs[5] vA
11244 /* 35410 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
11245 /* 35415 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
11246 /* 35419 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11247 /* 35423 */ // MIs[6] vC
11248 /* 35423 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11249 /* 35428 */ // MIs[6] vB
11250 /* 35428 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11251 /* 35433 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11252 /* 35435 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11253 /* 35435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11254 /* 35438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11255 /* 35440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vA
11256 /* 35444 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11257 /* 35448 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
11258 /* 35452 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11259 /* 35462 */ GIR_RootConstrainSelectedInstOperands,
11260 /* 35463 */ // GIR_Coverage, 5193,
11261 /* 35463 */ GIR_EraseRootFromParent_Done,
11262 /* 35464 */ // Label 480: @35464
11263 /* 35464 */ GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(35602), // Rule ID 5194 //
11264 /* 35469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11265 /* 35472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11266 /* 35476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11267 /* 35480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11268 /* 35484 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11269 /* 35488 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11270 /* 35492 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11271 /* 35496 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11272 /* 35500 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11273 /* 35504 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11274 /* 35508 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11275 /* 35512 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11276 /* 35516 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11277 /* 35520 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11278 /* 35524 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11279 /* 35528 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11280 /* 35534 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11281 /* 35536 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11282 /* 35540 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11283 /* 35544 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11284 /* 35548 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11285 /* 35552 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11286 /* 35556 */ // MIs[6] vA
11287 /* 35556 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11288 /* 35561 */ // MIs[6] vB
11289 /* 35561 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11290 /* 35566 */ // MIs[5] vC
11291 /* 35566 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11292 /* 35571 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11293 /* 35573 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11294 /* 35573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11295 /* 35576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11296 /* 35578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11297 /* 35582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11298 /* 35586 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11299 /* 35590 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11300 /* 35600 */ GIR_RootConstrainSelectedInstOperands,
11301 /* 35601 */ // GIR_Coverage, 5194,
11302 /* 35601 */ GIR_EraseRootFromParent_Done,
11303 /* 35602 */ // Label 481: @35602
11304 /* 35602 */ GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(35740), // Rule ID 5195 //
11305 /* 35607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11306 /* 35610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11307 /* 35614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11308 /* 35618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11309 /* 35622 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11310 /* 35626 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11311 /* 35630 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11312 /* 35634 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11313 /* 35638 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11314 /* 35642 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11315 /* 35646 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11316 /* 35650 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11317 /* 35654 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11318 /* 35658 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11319 /* 35662 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11320 /* 35666 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11321 /* 35672 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11322 /* 35674 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11323 /* 35678 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11324 /* 35682 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11325 /* 35686 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11326 /* 35690 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11327 /* 35694 */ // MIs[6] vB
11328 /* 35694 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11329 /* 35699 */ // MIs[6] vA
11330 /* 35699 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11331 /* 35704 */ // MIs[5] vC
11332 /* 35704 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11333 /* 35709 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11334 /* 35711 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11335 /* 35711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11336 /* 35714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11337 /* 35716 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11338 /* 35720 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11339 /* 35724 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11340 /* 35728 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11341 /* 35738 */ GIR_RootConstrainSelectedInstOperands,
11342 /* 35739 */ // GIR_Coverage, 5195,
11343 /* 35739 */ GIR_EraseRootFromParent_Done,
11344 /* 35740 */ // Label 482: @35740
11345 /* 35740 */ GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(35878), // Rule ID 5196 //
11346 /* 35745 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11347 /* 35748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11348 /* 35752 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11349 /* 35756 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11350 /* 35760 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11351 /* 35764 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11352 /* 35768 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11353 /* 35772 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11354 /* 35776 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11355 /* 35780 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11356 /* 35784 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11357 /* 35788 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11358 /* 35792 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11359 /* 35796 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11360 /* 35800 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11361 /* 35804 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11362 /* 35810 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11363 /* 35812 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11364 /* 35816 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11365 /* 35820 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11366 /* 35824 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11367 /* 35828 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11368 /* 35832 */ // MIs[6] vA
11369 /* 35832 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11370 /* 35837 */ // MIs[6] vC
11371 /* 35837 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11372 /* 35842 */ // MIs[5] vB
11373 /* 35842 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11374 /* 35847 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11375 /* 35849 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11376 /* 35849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11377 /* 35852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11378 /* 35854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11379 /* 35858 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11380 /* 35862 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11381 /* 35866 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11382 /* 35876 */ GIR_RootConstrainSelectedInstOperands,
11383 /* 35877 */ // GIR_Coverage, 5196,
11384 /* 35877 */ GIR_EraseRootFromParent_Done,
11385 /* 35878 */ // Label 483: @35878
11386 /* 35878 */ GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(36016), // Rule ID 5197 //
11387 /* 35883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11388 /* 35886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11389 /* 35890 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11390 /* 35894 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11391 /* 35898 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11392 /* 35902 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11393 /* 35906 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11394 /* 35910 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11395 /* 35914 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11396 /* 35918 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11397 /* 35922 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11398 /* 35926 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11399 /* 35930 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11400 /* 35934 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11401 /* 35938 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11402 /* 35942 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11403 /* 35948 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11404 /* 35950 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11405 /* 35954 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11406 /* 35958 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11407 /* 35962 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11408 /* 35966 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11409 /* 35970 */ // MIs[6] vC
11410 /* 35970 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
11411 /* 35975 */ // MIs[6] vA
11412 /* 35975 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11413 /* 35980 */ // MIs[5] vB
11414 /* 35980 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11415 /* 35985 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11416 /* 35987 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11417 /* 35987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11418 /* 35990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11419 /* 35992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11420 /* 35996 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11421 /* 36000 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11422 /* 36004 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11423 /* 36014 */ GIR_RootConstrainSelectedInstOperands,
11424 /* 36015 */ // GIR_Coverage, 5197,
11425 /* 36015 */ GIR_EraseRootFromParent_Done,
11426 /* 36016 */ // Label 484: @36016
11427 /* 36016 */ GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(36154), // Rule ID 5198 //
11428 /* 36021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11429 /* 36024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11430 /* 36028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11431 /* 36032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11432 /* 36036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11433 /* 36040 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11434 /* 36044 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11435 /* 36048 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11436 /* 36052 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11437 /* 36056 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11438 /* 36060 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11439 /* 36064 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11440 /* 36068 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11441 /* 36072 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11442 /* 36076 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11443 /* 36080 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11444 /* 36086 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11445 /* 36088 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11446 /* 36092 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11447 /* 36096 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11448 /* 36100 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11449 /* 36104 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11450 /* 36108 */ // MIs[6] vB
11451 /* 36108 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11452 /* 36113 */ // MIs[6] vC
11453 /* 36113 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11454 /* 36118 */ // MIs[5] vA
11455 /* 36118 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11456 /* 36123 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11457 /* 36125 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11458 /* 36125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11459 /* 36128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11460 /* 36130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11461 /* 36134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11462 /* 36138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11463 /* 36142 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11464 /* 36152 */ GIR_RootConstrainSelectedInstOperands,
11465 /* 36153 */ // GIR_Coverage, 5198,
11466 /* 36153 */ GIR_EraseRootFromParent_Done,
11467 /* 36154 */ // Label 485: @36154
11468 /* 36154 */ GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(36292), // Rule ID 5199 //
11469 /* 36159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11470 /* 36162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11471 /* 36166 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11472 /* 36170 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11473 /* 36174 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11474 /* 36178 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11475 /* 36182 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11476 /* 36186 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11477 /* 36190 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11478 /* 36194 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11479 /* 36198 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11480 /* 36202 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11481 /* 36206 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11482 /* 36210 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11483 /* 36214 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11484 /* 36218 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11485 /* 36224 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11486 /* 36226 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11487 /* 36230 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11488 /* 36234 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11489 /* 36238 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11490 /* 36242 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11491 /* 36246 */ // MIs[6] vC
11492 /* 36246 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
11493 /* 36251 */ // MIs[6] vB
11494 /* 36251 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11495 /* 36256 */ // MIs[5] vA
11496 /* 36256 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11497 /* 36261 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11498 /* 36263 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11499 /* 36263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11500 /* 36266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11501 /* 36268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11502 /* 36272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
11503 /* 36276 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11504 /* 36280 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11505 /* 36290 */ GIR_RootConstrainSelectedInstOperands,
11506 /* 36291 */ // GIR_Coverage, 5199,
11507 /* 36291 */ GIR_EraseRootFromParent_Done,
11508 /* 36292 */ // Label 486: @36292
11509 /* 36292 */ GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(36430), // Rule ID 5206 //
11510 /* 36297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11511 /* 36300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11512 /* 36304 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11513 /* 36308 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11514 /* 36312 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11515 /* 36316 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11516 /* 36320 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11517 /* 36324 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11518 /* 36328 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11519 /* 36332 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11520 /* 36336 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11521 /* 36340 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11522 /* 36344 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11523 /* 36348 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11524 /* 36352 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11525 /* 36356 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11526 /* 36362 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11527 /* 36364 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11528 /* 36368 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11529 /* 36372 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11530 /* 36376 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11531 /* 36380 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11532 /* 36384 */ // MIs[6] vA
11533 /* 36384 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11534 /* 36389 */ // MIs[6] vB
11535 /* 36389 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11536 /* 36394 */ // MIs[5] vC
11537 /* 36394 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11538 /* 36399 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11539 /* 36401 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11540 /* 36401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11541 /* 36404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11542 /* 36406 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
11543 /* 36410 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
11544 /* 36414 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11545 /* 36418 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11546 /* 36428 */ GIR_RootConstrainSelectedInstOperands,
11547 /* 36429 */ // GIR_Coverage, 5206,
11548 /* 36429 */ GIR_EraseRootFromParent_Done,
11549 /* 36430 */ // Label 487: @36430
11550 /* 36430 */ GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(36568), // Rule ID 5207 //
11551 /* 36435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11552 /* 36438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11553 /* 36442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11554 /* 36446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11555 /* 36450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11556 /* 36454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11557 /* 36458 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11558 /* 36462 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11559 /* 36466 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11560 /* 36470 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11561 /* 36474 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11562 /* 36478 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11563 /* 36482 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11564 /* 36486 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11565 /* 36490 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11566 /* 36494 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11567 /* 36500 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11568 /* 36502 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11569 /* 36506 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11570 /* 36510 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11571 /* 36514 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11572 /* 36518 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11573 /* 36522 */ // MIs[6] vB
11574 /* 36522 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11575 /* 36527 */ // MIs[6] vA
11576 /* 36527 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11577 /* 36532 */ // MIs[5] vC
11578 /* 36532 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11579 /* 36537 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11580 /* 36539 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11581 /* 36539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11582 /* 36542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11583 /* 36544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
11584 /* 36548 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
11585 /* 36552 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11586 /* 36556 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11587 /* 36566 */ GIR_RootConstrainSelectedInstOperands,
11588 /* 36567 */ // GIR_Coverage, 5207,
11589 /* 36567 */ GIR_EraseRootFromParent_Done,
11590 /* 36568 */ // Label 488: @36568
11591 /* 36568 */ GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(36706), // Rule ID 5208 //
11592 /* 36573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11593 /* 36576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11594 /* 36580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11595 /* 36584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11596 /* 36588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11597 /* 36592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11598 /* 36596 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11599 /* 36600 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11600 /* 36604 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11601 /* 36608 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11602 /* 36612 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11603 /* 36616 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11604 /* 36620 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11605 /* 36624 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11606 /* 36628 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11607 /* 36632 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11608 /* 36638 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11609 /* 36640 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11610 /* 36644 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11611 /* 36648 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11612 /* 36652 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11613 /* 36656 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11614 /* 36660 */ // MIs[6] vA
11615 /* 36660 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11616 /* 36665 */ // MIs[6] vC
11617 /* 36665 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11618 /* 36670 */ // MIs[5] vB
11619 /* 36670 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11620 /* 36675 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11621 /* 36677 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11622 /* 36677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11623 /* 36680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11624 /* 36682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
11625 /* 36686 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
11626 /* 36690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11627 /* 36694 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11628 /* 36704 */ GIR_RootConstrainSelectedInstOperands,
11629 /* 36705 */ // GIR_Coverage, 5208,
11630 /* 36705 */ GIR_EraseRootFromParent_Done,
11631 /* 36706 */ // Label 489: @36706
11632 /* 36706 */ GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(36844), // Rule ID 5209 //
11633 /* 36711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11634 /* 36714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11635 /* 36718 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11636 /* 36722 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11637 /* 36726 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11638 /* 36730 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11639 /* 36734 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11640 /* 36738 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11641 /* 36742 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11642 /* 36746 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11643 /* 36750 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11644 /* 36754 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11645 /* 36758 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11646 /* 36762 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11647 /* 36766 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11648 /* 36770 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11649 /* 36776 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11650 /* 36778 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11651 /* 36782 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11652 /* 36786 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11653 /* 36790 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11654 /* 36794 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11655 /* 36798 */ // MIs[6] vC
11656 /* 36798 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
11657 /* 36803 */ // MIs[6] vA
11658 /* 36803 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11659 /* 36808 */ // MIs[5] vB
11660 /* 36808 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11661 /* 36813 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11662 /* 36815 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11663 /* 36815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11664 /* 36818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11665 /* 36820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
11666 /* 36824 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
11667 /* 36828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11668 /* 36832 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11669 /* 36842 */ GIR_RootConstrainSelectedInstOperands,
11670 /* 36843 */ // GIR_Coverage, 5209,
11671 /* 36843 */ GIR_EraseRootFromParent_Done,
11672 /* 36844 */ // Label 490: @36844
11673 /* 36844 */ GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(36982), // Rule ID 5210 //
11674 /* 36849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11675 /* 36852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11676 /* 36856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11677 /* 36860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11678 /* 36864 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11679 /* 36868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11680 /* 36872 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11681 /* 36876 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11682 /* 36880 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11683 /* 36884 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11684 /* 36888 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11685 /* 36892 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11686 /* 36896 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11687 /* 36900 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11688 /* 36904 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11689 /* 36908 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11690 /* 36914 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11691 /* 36916 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11692 /* 36920 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11693 /* 36924 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11694 /* 36928 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11695 /* 36932 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11696 /* 36936 */ // MIs[6] vB
11697 /* 36936 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11698 /* 36941 */ // MIs[6] vC
11699 /* 36941 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11700 /* 36946 */ // MIs[5] vA
11701 /* 36946 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11702 /* 36951 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11703 /* 36953 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11704 /* 36953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11705 /* 36956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11706 /* 36958 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
11707 /* 36962 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
11708 /* 36966 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11709 /* 36970 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11710 /* 36980 */ GIR_RootConstrainSelectedInstOperands,
11711 /* 36981 */ // GIR_Coverage, 5210,
11712 /* 36981 */ GIR_EraseRootFromParent_Done,
11713 /* 36982 */ // Label 491: @36982
11714 /* 36982 */ GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(37120), // Rule ID 5211 //
11715 /* 36987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11716 /* 36990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11717 /* 36994 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11718 /* 36998 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11719 /* 37002 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11720 /* 37006 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11721 /* 37010 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11722 /* 37014 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11723 /* 37018 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11724 /* 37022 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11725 /* 37026 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11726 /* 37030 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11727 /* 37034 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11728 /* 37038 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11729 /* 37042 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11730 /* 37046 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11731 /* 37052 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11732 /* 37054 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11733 /* 37058 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11734 /* 37062 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11735 /* 37066 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11736 /* 37070 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11737 /* 37074 */ // MIs[6] vC
11738 /* 37074 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
11739 /* 37079 */ // MIs[6] vB
11740 /* 37079 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11741 /* 37084 */ // MIs[5] vA
11742 /* 37084 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11743 /* 37089 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11744 /* 37091 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11745 /* 37091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11746 /* 37094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11747 /* 37096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
11748 /* 37100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
11749 /* 37104 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
11750 /* 37108 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11751 /* 37118 */ GIR_RootConstrainSelectedInstOperands,
11752 /* 37119 */ // GIR_Coverage, 5211,
11753 /* 37119 */ GIR_EraseRootFromParent_Done,
11754 /* 37120 */ // Label 492: @37120
11755 /* 37120 */ GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(37258), // Rule ID 5218 //
11756 /* 37125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11757 /* 37128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11758 /* 37132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11759 /* 37136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11760 /* 37140 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11761 /* 37144 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11762 /* 37148 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11763 /* 37152 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11764 /* 37156 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11765 /* 37160 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11766 /* 37164 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11767 /* 37168 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11768 /* 37172 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11769 /* 37176 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11770 /* 37180 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11771 /* 37184 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11772 /* 37190 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11773 /* 37192 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11774 /* 37196 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11775 /* 37200 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11776 /* 37204 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11777 /* 37208 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11778 /* 37212 */ // MIs[6] vA
11779 /* 37212 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11780 /* 37217 */ // MIs[6] vB
11781 /* 37217 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11782 /* 37222 */ // MIs[5] vC
11783 /* 37222 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11784 /* 37227 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11785 /* 37229 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11786 /* 37229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11787 /* 37232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11788 /* 37234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11789 /* 37238 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
11790 /* 37242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
11791 /* 37246 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11792 /* 37256 */ GIR_RootConstrainSelectedInstOperands,
11793 /* 37257 */ // GIR_Coverage, 5218,
11794 /* 37257 */ GIR_EraseRootFromParent_Done,
11795 /* 37258 */ // Label 493: @37258
11796 /* 37258 */ GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(37396), // Rule ID 5219 //
11797 /* 37263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11798 /* 37266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11799 /* 37270 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11800 /* 37274 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11801 /* 37278 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11802 /* 37282 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11803 /* 37286 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11804 /* 37290 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11805 /* 37294 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11806 /* 37298 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11807 /* 37302 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11808 /* 37306 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11809 /* 37310 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11810 /* 37314 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11811 /* 37318 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11812 /* 37322 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11813 /* 37328 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11814 /* 37330 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11815 /* 37334 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11816 /* 37338 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11817 /* 37342 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11818 /* 37346 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11819 /* 37350 */ // MIs[6] vB
11820 /* 37350 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
11821 /* 37355 */ // MIs[6] vA
11822 /* 37355 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11823 /* 37360 */ // MIs[5] vC
11824 /* 37360 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11825 /* 37365 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11826 /* 37367 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11827 /* 37367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11828 /* 37370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11829 /* 37372 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11830 /* 37376 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
11831 /* 37380 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
11832 /* 37384 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11833 /* 37394 */ GIR_RootConstrainSelectedInstOperands,
11834 /* 37395 */ // GIR_Coverage, 5219,
11835 /* 37395 */ GIR_EraseRootFromParent_Done,
11836 /* 37396 */ // Label 494: @37396
11837 /* 37396 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(37534), // Rule ID 5220 //
11838 /* 37401 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11839 /* 37404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11840 /* 37408 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11841 /* 37412 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11842 /* 37416 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11843 /* 37420 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11844 /* 37424 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11845 /* 37428 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11846 /* 37432 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11847 /* 37436 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11848 /* 37440 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11849 /* 37444 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11850 /* 37448 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11851 /* 37452 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11852 /* 37456 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11853 /* 37460 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11854 /* 37466 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11855 /* 37468 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11856 /* 37472 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11857 /* 37476 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11858 /* 37480 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11859 /* 37484 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11860 /* 37488 */ // MIs[6] vA
11861 /* 37488 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
11862 /* 37493 */ // MIs[6] vC
11863 /* 37493 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11864 /* 37498 */ // MIs[5] vB
11865 /* 37498 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11866 /* 37503 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11867 /* 37505 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11868 /* 37505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11869 /* 37508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11870 /* 37510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11871 /* 37514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
11872 /* 37518 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
11873 /* 37522 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11874 /* 37532 */ GIR_RootConstrainSelectedInstOperands,
11875 /* 37533 */ // GIR_Coverage, 5220,
11876 /* 37533 */ GIR_EraseRootFromParent_Done,
11877 /* 37534 */ // Label 495: @37534
11878 /* 37534 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(37672), // Rule ID 5221 //
11879 /* 37539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11880 /* 37542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11881 /* 37546 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11882 /* 37550 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11883 /* 37554 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11884 /* 37558 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11885 /* 37562 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11886 /* 37566 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11887 /* 37570 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11888 /* 37574 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11889 /* 37578 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11890 /* 37582 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11891 /* 37586 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11892 /* 37590 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11893 /* 37594 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11894 /* 37598 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11895 /* 37604 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11896 /* 37606 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11897 /* 37610 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11898 /* 37614 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11899 /* 37618 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11900 /* 37622 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11901 /* 37626 */ // MIs[6] vC
11902 /* 37626 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11903 /* 37631 */ // MIs[6] vA
11904 /* 37631 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11905 /* 37636 */ // MIs[5] vB
11906 /* 37636 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11907 /* 37641 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11908 /* 37643 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11909 /* 37643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11910 /* 37646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11911 /* 37648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11912 /* 37652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
11913 /* 37656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
11914 /* 37660 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11915 /* 37670 */ GIR_RootConstrainSelectedInstOperands,
11916 /* 37671 */ // GIR_Coverage, 5221,
11917 /* 37671 */ GIR_EraseRootFromParent_Done,
11918 /* 37672 */ // Label 496: @37672
11919 /* 37672 */ GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(37810), // Rule ID 5222 //
11920 /* 37677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11921 /* 37680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11922 /* 37684 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11923 /* 37688 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11924 /* 37692 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11925 /* 37696 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11926 /* 37700 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11927 /* 37704 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11928 /* 37708 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11929 /* 37712 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11930 /* 37716 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11931 /* 37720 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11932 /* 37724 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11933 /* 37728 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11934 /* 37732 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11935 /* 37736 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11936 /* 37742 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11937 /* 37744 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11938 /* 37748 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11939 /* 37752 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11940 /* 37756 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11941 /* 37760 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11942 /* 37764 */ // MIs[6] vB
11943 /* 37764 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
11944 /* 37769 */ // MIs[6] vC
11945 /* 37769 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
11946 /* 37774 */ // MIs[5] vA
11947 /* 37774 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11948 /* 37779 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11949 /* 37781 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11950 /* 37781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11951 /* 37784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11952 /* 37786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11953 /* 37790 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
11954 /* 37794 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
11955 /* 37798 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11956 /* 37808 */ GIR_RootConstrainSelectedInstOperands,
11957 /* 37809 */ // GIR_Coverage, 5222,
11958 /* 37809 */ GIR_EraseRootFromParent_Done,
11959 /* 37810 */ // Label 497: @37810
11960 /* 37810 */ GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(37948), // Rule ID 5223 //
11961 /* 37815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
11962 /* 37818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
11963 /* 37822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11964 /* 37826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11965 /* 37830 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11966 /* 37834 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11967 /* 37838 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11968 /* 37842 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
11969 /* 37846 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
11970 /* 37850 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
11971 /* 37854 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11972 /* 37858 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
11973 /* 37862 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
11974 /* 37866 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
11975 /* 37870 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
11976 /* 37874 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11977 /* 37880 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
11978 /* 37882 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
11979 /* 37886 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
11980 /* 37890 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
11981 /* 37894 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
11982 /* 37898 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
11983 /* 37902 */ // MIs[6] vC
11984 /* 37902 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
11985 /* 37907 */ // MIs[6] vB
11986 /* 37907 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
11987 /* 37912 */ // MIs[5] vA
11988 /* 37912 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
11989 /* 37917 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
11990 /* 37919 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
11991 /* 37919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
11992 /* 37922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
11993 /* 37924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
11994 /* 37928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
11995 /* 37932 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
11996 /* 37936 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
11997 /* 37946 */ GIR_RootConstrainSelectedInstOperands,
11998 /* 37947 */ // GIR_Coverage, 5223,
11999 /* 37947 */ GIR_EraseRootFromParent_Done,
12000 /* 37948 */ // Label 498: @37948
12001 /* 37948 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(38086), // Rule ID 5230 //
12002 /* 37953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12003 /* 37956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12004 /* 37960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12005 /* 37964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12006 /* 37968 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12007 /* 37972 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12008 /* 37976 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12009 /* 37980 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12010 /* 37984 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12011 /* 37988 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12012 /* 37992 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12013 /* 37996 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12014 /* 38000 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12015 /* 38004 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12016 /* 38008 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12017 /* 38012 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12018 /* 38018 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12019 /* 38020 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12020 /* 38024 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12021 /* 38028 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12022 /* 38032 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12023 /* 38036 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12024 /* 38040 */ // MIs[6] vA
12025 /* 38040 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12026 /* 38045 */ // MIs[6] vB
12027 /* 38045 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12028 /* 38050 */ // MIs[5] vC
12029 /* 38050 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12030 /* 38055 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12031 /* 38057 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12032 /* 38057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12033 /* 38060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12034 /* 38062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
12035 /* 38066 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
12036 /* 38070 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12037 /* 38074 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12038 /* 38084 */ GIR_RootConstrainSelectedInstOperands,
12039 /* 38085 */ // GIR_Coverage, 5230,
12040 /* 38085 */ GIR_EraseRootFromParent_Done,
12041 /* 38086 */ // Label 499: @38086
12042 /* 38086 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(38224), // Rule ID 5231 //
12043 /* 38091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12044 /* 38094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12045 /* 38098 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12046 /* 38102 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12047 /* 38106 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12048 /* 38110 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12049 /* 38114 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12050 /* 38118 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12051 /* 38122 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12052 /* 38126 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12053 /* 38130 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12054 /* 38134 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12055 /* 38138 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12056 /* 38142 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12057 /* 38146 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12058 /* 38150 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12059 /* 38156 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12060 /* 38158 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12061 /* 38162 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12062 /* 38166 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12063 /* 38170 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12064 /* 38174 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12065 /* 38178 */ // MIs[6] vB
12066 /* 38178 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12067 /* 38183 */ // MIs[6] vA
12068 /* 38183 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12069 /* 38188 */ // MIs[5] vC
12070 /* 38188 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12071 /* 38193 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12072 /* 38195 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12073 /* 38195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12074 /* 38198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12075 /* 38200 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
12076 /* 38204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
12077 /* 38208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12078 /* 38212 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12079 /* 38222 */ GIR_RootConstrainSelectedInstOperands,
12080 /* 38223 */ // GIR_Coverage, 5231,
12081 /* 38223 */ GIR_EraseRootFromParent_Done,
12082 /* 38224 */ // Label 500: @38224
12083 /* 38224 */ GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(38362), // Rule ID 5232 //
12084 /* 38229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12085 /* 38232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12086 /* 38236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12087 /* 38240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12088 /* 38244 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12089 /* 38248 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12090 /* 38252 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12091 /* 38256 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12092 /* 38260 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12093 /* 38264 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12094 /* 38268 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12095 /* 38272 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12096 /* 38276 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12097 /* 38280 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12098 /* 38284 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12099 /* 38288 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12100 /* 38294 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12101 /* 38296 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12102 /* 38300 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12103 /* 38304 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12104 /* 38308 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12105 /* 38312 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12106 /* 38316 */ // MIs[6] vA
12107 /* 38316 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12108 /* 38321 */ // MIs[6] vC
12109 /* 38321 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12110 /* 38326 */ // MIs[5] vB
12111 /* 38326 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12112 /* 38331 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12113 /* 38333 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12114 /* 38333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12115 /* 38336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12116 /* 38338 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
12117 /* 38342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
12118 /* 38346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12119 /* 38350 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12120 /* 38360 */ GIR_RootConstrainSelectedInstOperands,
12121 /* 38361 */ // GIR_Coverage, 5232,
12122 /* 38361 */ GIR_EraseRootFromParent_Done,
12123 /* 38362 */ // Label 501: @38362
12124 /* 38362 */ GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(38500), // Rule ID 5233 //
12125 /* 38367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12126 /* 38370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12127 /* 38374 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12128 /* 38378 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12129 /* 38382 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12130 /* 38386 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12131 /* 38390 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12132 /* 38394 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12133 /* 38398 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12134 /* 38402 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12135 /* 38406 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12136 /* 38410 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12137 /* 38414 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12138 /* 38418 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12139 /* 38422 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12140 /* 38426 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12141 /* 38432 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12142 /* 38434 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12143 /* 38438 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12144 /* 38442 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12145 /* 38446 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12146 /* 38450 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12147 /* 38454 */ // MIs[6] vC
12148 /* 38454 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12149 /* 38459 */ // MIs[6] vA
12150 /* 38459 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12151 /* 38464 */ // MIs[5] vB
12152 /* 38464 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12153 /* 38469 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12154 /* 38471 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12155 /* 38471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12156 /* 38474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12157 /* 38476 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
12158 /* 38480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
12159 /* 38484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12160 /* 38488 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12161 /* 38498 */ GIR_RootConstrainSelectedInstOperands,
12162 /* 38499 */ // GIR_Coverage, 5233,
12163 /* 38499 */ GIR_EraseRootFromParent_Done,
12164 /* 38500 */ // Label 502: @38500
12165 /* 38500 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(38638), // Rule ID 5234 //
12166 /* 38505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12167 /* 38508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12168 /* 38512 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12169 /* 38516 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12170 /* 38520 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12171 /* 38524 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12172 /* 38528 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12173 /* 38532 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12174 /* 38536 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12175 /* 38540 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12176 /* 38544 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12177 /* 38548 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12178 /* 38552 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12179 /* 38556 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12180 /* 38560 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12181 /* 38564 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12182 /* 38570 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12183 /* 38572 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12184 /* 38576 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12185 /* 38580 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12186 /* 38584 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12187 /* 38588 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12188 /* 38592 */ // MIs[6] vB
12189 /* 38592 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12190 /* 38597 */ // MIs[6] vC
12191 /* 38597 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12192 /* 38602 */ // MIs[5] vA
12193 /* 38602 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12194 /* 38607 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12195 /* 38609 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12196 /* 38609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12197 /* 38612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12198 /* 38614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
12199 /* 38618 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
12200 /* 38622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12201 /* 38626 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12202 /* 38636 */ GIR_RootConstrainSelectedInstOperands,
12203 /* 38637 */ // GIR_Coverage, 5234,
12204 /* 38637 */ GIR_EraseRootFromParent_Done,
12205 /* 38638 */ // Label 503: @38638
12206 /* 38638 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(38776), // Rule ID 5235 //
12207 /* 38643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12208 /* 38646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12209 /* 38650 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12210 /* 38654 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12211 /* 38658 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12212 /* 38662 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12213 /* 38666 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12214 /* 38670 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12215 /* 38674 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12216 /* 38678 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12217 /* 38682 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12218 /* 38686 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12219 /* 38690 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12220 /* 38694 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12221 /* 38698 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12222 /* 38702 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12223 /* 38708 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12224 /* 38710 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12225 /* 38714 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12226 /* 38718 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12227 /* 38722 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12228 /* 38726 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12229 /* 38730 */ // MIs[6] vC
12230 /* 38730 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12231 /* 38735 */ // MIs[6] vB
12232 /* 38735 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12233 /* 38740 */ // MIs[5] vA
12234 /* 38740 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12235 /* 38745 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12236 /* 38747 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12237 /* 38747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12238 /* 38750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12239 /* 38752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
12240 /* 38756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
12241 /* 38760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12242 /* 38764 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12243 /* 38774 */ GIR_RootConstrainSelectedInstOperands,
12244 /* 38775 */ // GIR_Coverage, 5235,
12245 /* 38775 */ GIR_EraseRootFromParent_Done,
12246 /* 38776 */ // Label 504: @38776
12247 /* 38776 */ GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(38914), // Rule ID 5242 //
12248 /* 38781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12249 /* 38784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12250 /* 38788 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12251 /* 38792 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12252 /* 38796 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12253 /* 38800 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12254 /* 38804 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12255 /* 38808 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12256 /* 38812 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12257 /* 38816 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12258 /* 38820 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12259 /* 38824 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12260 /* 38828 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12261 /* 38832 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12262 /* 38836 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12263 /* 38840 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12264 /* 38846 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12265 /* 38848 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12266 /* 38852 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12267 /* 38856 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12268 /* 38860 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12269 /* 38864 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12270 /* 38868 */ // MIs[6] vA
12271 /* 38868 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12272 /* 38873 */ // MIs[6] vB
12273 /* 38873 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12274 /* 38878 */ // MIs[5] vC
12275 /* 38878 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12276 /* 38883 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12277 /* 38885 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12278 /* 38885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12279 /* 38888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12280 /* 38890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12281 /* 38894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
12282 /* 38898 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
12283 /* 38902 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12284 /* 38912 */ GIR_RootConstrainSelectedInstOperands,
12285 /* 38913 */ // GIR_Coverage, 5242,
12286 /* 38913 */ GIR_EraseRootFromParent_Done,
12287 /* 38914 */ // Label 505: @38914
12288 /* 38914 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(39052), // Rule ID 5243 //
12289 /* 38919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12290 /* 38922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12291 /* 38926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12292 /* 38930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12293 /* 38934 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12294 /* 38938 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12295 /* 38942 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12296 /* 38946 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12297 /* 38950 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12298 /* 38954 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12299 /* 38958 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12300 /* 38962 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12301 /* 38966 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12302 /* 38970 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12303 /* 38974 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12304 /* 38978 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12305 /* 38984 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12306 /* 38986 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12307 /* 38990 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12308 /* 38994 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12309 /* 38998 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12310 /* 39002 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12311 /* 39006 */ // MIs[6] vB
12312 /* 39006 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12313 /* 39011 */ // MIs[6] vA
12314 /* 39011 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12315 /* 39016 */ // MIs[5] vC
12316 /* 39016 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12317 /* 39021 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12318 /* 39023 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12319 /* 39023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12320 /* 39026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12321 /* 39028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12322 /* 39032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
12323 /* 39036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
12324 /* 39040 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12325 /* 39050 */ GIR_RootConstrainSelectedInstOperands,
12326 /* 39051 */ // GIR_Coverage, 5243,
12327 /* 39051 */ GIR_EraseRootFromParent_Done,
12328 /* 39052 */ // Label 506: @39052
12329 /* 39052 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(39190), // Rule ID 5244 //
12330 /* 39057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12331 /* 39060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12332 /* 39064 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12333 /* 39068 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12334 /* 39072 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12335 /* 39076 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12336 /* 39080 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12337 /* 39084 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12338 /* 39088 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12339 /* 39092 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12340 /* 39096 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12341 /* 39100 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12342 /* 39104 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12343 /* 39108 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12344 /* 39112 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12345 /* 39116 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12346 /* 39122 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12347 /* 39124 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12348 /* 39128 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12349 /* 39132 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12350 /* 39136 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12351 /* 39140 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12352 /* 39144 */ // MIs[6] vA
12353 /* 39144 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12354 /* 39149 */ // MIs[6] vC
12355 /* 39149 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12356 /* 39154 */ // MIs[5] vB
12357 /* 39154 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12358 /* 39159 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12359 /* 39161 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12360 /* 39161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12361 /* 39164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12362 /* 39166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12363 /* 39170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
12364 /* 39174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
12365 /* 39178 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12366 /* 39188 */ GIR_RootConstrainSelectedInstOperands,
12367 /* 39189 */ // GIR_Coverage, 5244,
12368 /* 39189 */ GIR_EraseRootFromParent_Done,
12369 /* 39190 */ // Label 507: @39190
12370 /* 39190 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(39328), // Rule ID 5245 //
12371 /* 39195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12372 /* 39198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12373 /* 39202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12374 /* 39206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12375 /* 39210 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12376 /* 39214 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12377 /* 39218 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12378 /* 39222 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12379 /* 39226 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12380 /* 39230 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12381 /* 39234 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12382 /* 39238 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12383 /* 39242 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12384 /* 39246 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12385 /* 39250 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12386 /* 39254 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12387 /* 39260 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12388 /* 39262 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12389 /* 39266 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12390 /* 39270 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12391 /* 39274 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12392 /* 39278 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12393 /* 39282 */ // MIs[6] vC
12394 /* 39282 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12395 /* 39287 */ // MIs[6] vA
12396 /* 39287 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12397 /* 39292 */ // MIs[5] vB
12398 /* 39292 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12399 /* 39297 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12400 /* 39299 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12401 /* 39299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12402 /* 39302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12403 /* 39304 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12404 /* 39308 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
12405 /* 39312 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
12406 /* 39316 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12407 /* 39326 */ GIR_RootConstrainSelectedInstOperands,
12408 /* 39327 */ // GIR_Coverage, 5245,
12409 /* 39327 */ GIR_EraseRootFromParent_Done,
12410 /* 39328 */ // Label 508: @39328
12411 /* 39328 */ GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(39466), // Rule ID 5246 //
12412 /* 39333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12413 /* 39336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12414 /* 39340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12415 /* 39344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12416 /* 39348 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12417 /* 39352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12418 /* 39356 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12419 /* 39360 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12420 /* 39364 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12421 /* 39368 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12422 /* 39372 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12423 /* 39376 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12424 /* 39380 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12425 /* 39384 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12426 /* 39388 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12427 /* 39392 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12428 /* 39398 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12429 /* 39400 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12430 /* 39404 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12431 /* 39408 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12432 /* 39412 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12433 /* 39416 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12434 /* 39420 */ // MIs[6] vB
12435 /* 39420 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12436 /* 39425 */ // MIs[6] vC
12437 /* 39425 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12438 /* 39430 */ // MIs[5] vA
12439 /* 39430 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12440 /* 39435 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12441 /* 39437 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12442 /* 39437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12443 /* 39440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12444 /* 39442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12445 /* 39446 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
12446 /* 39450 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
12447 /* 39454 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12448 /* 39464 */ GIR_RootConstrainSelectedInstOperands,
12449 /* 39465 */ // GIR_Coverage, 5246,
12450 /* 39465 */ GIR_EraseRootFromParent_Done,
12451 /* 39466 */ // Label 509: @39466
12452 /* 39466 */ GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(39604), // Rule ID 5247 //
12453 /* 39471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12454 /* 39474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12455 /* 39478 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12456 /* 39482 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12457 /* 39486 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12458 /* 39490 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12459 /* 39494 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12460 /* 39498 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12461 /* 39502 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12462 /* 39506 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12463 /* 39510 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12464 /* 39514 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12465 /* 39518 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12466 /* 39522 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12467 /* 39526 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12468 /* 39530 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12469 /* 39536 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12470 /* 39538 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12471 /* 39542 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12472 /* 39546 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12473 /* 39550 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12474 /* 39554 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12475 /* 39558 */ // MIs[6] vC
12476 /* 39558 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12477 /* 39563 */ // MIs[6] vB
12478 /* 39563 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12479 /* 39568 */ // MIs[5] vA
12480 /* 39568 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12481 /* 39573 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12482 /* 39575 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12483 /* 39575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12484 /* 39578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12485 /* 39580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12486 /* 39584 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
12487 /* 39588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
12488 /* 39592 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12489 /* 39602 */ GIR_RootConstrainSelectedInstOperands,
12490 /* 39603 */ // GIR_Coverage, 5247,
12491 /* 39603 */ GIR_EraseRootFromParent_Done,
12492 /* 39604 */ // Label 510: @39604
12493 /* 39604 */ GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(39742), // Rule ID 5254 //
12494 /* 39609 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12495 /* 39612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12496 /* 39616 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12497 /* 39620 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12498 /* 39624 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12499 /* 39628 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12500 /* 39632 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12501 /* 39636 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12502 /* 39640 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12503 /* 39644 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12504 /* 39648 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12505 /* 39652 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12506 /* 39656 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12507 /* 39660 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12508 /* 39664 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12509 /* 39668 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12510 /* 39674 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12511 /* 39676 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12512 /* 39680 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12513 /* 39684 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12514 /* 39688 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12515 /* 39692 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12516 /* 39696 */ // MIs[6] vA
12517 /* 39696 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12518 /* 39701 */ // MIs[6] vB
12519 /* 39701 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12520 /* 39706 */ // MIs[5] vC
12521 /* 39706 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12522 /* 39711 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12523 /* 39713 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12524 /* 39713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12525 /* 39716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12526 /* 39718 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12527 /* 39722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12528 /* 39726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12529 /* 39730 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12530 /* 39740 */ GIR_RootConstrainSelectedInstOperands,
12531 /* 39741 */ // GIR_Coverage, 5254,
12532 /* 39741 */ GIR_EraseRootFromParent_Done,
12533 /* 39742 */ // Label 511: @39742
12534 /* 39742 */ GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(39880), // Rule ID 5255 //
12535 /* 39747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12536 /* 39750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12537 /* 39754 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12538 /* 39758 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12539 /* 39762 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12540 /* 39766 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12541 /* 39770 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12542 /* 39774 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12543 /* 39778 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12544 /* 39782 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12545 /* 39786 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12546 /* 39790 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12547 /* 39794 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12548 /* 39798 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12549 /* 39802 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12550 /* 39806 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12551 /* 39812 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12552 /* 39814 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12553 /* 39818 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12554 /* 39822 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12555 /* 39826 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12556 /* 39830 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12557 /* 39834 */ // MIs[6] vB
12558 /* 39834 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12559 /* 39839 */ // MIs[6] vA
12560 /* 39839 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12561 /* 39844 */ // MIs[5] vC
12562 /* 39844 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12563 /* 39849 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12564 /* 39851 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12565 /* 39851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12566 /* 39854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12567 /* 39856 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12568 /* 39860 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12569 /* 39864 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12570 /* 39868 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12571 /* 39878 */ GIR_RootConstrainSelectedInstOperands,
12572 /* 39879 */ // GIR_Coverage, 5255,
12573 /* 39879 */ GIR_EraseRootFromParent_Done,
12574 /* 39880 */ // Label 512: @39880
12575 /* 39880 */ GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(40018), // Rule ID 5256 //
12576 /* 39885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12577 /* 39888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12578 /* 39892 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12579 /* 39896 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12580 /* 39900 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12581 /* 39904 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12582 /* 39908 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12583 /* 39912 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12584 /* 39916 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12585 /* 39920 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12586 /* 39924 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12587 /* 39928 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12588 /* 39932 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12589 /* 39936 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12590 /* 39940 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12591 /* 39944 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12592 /* 39950 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12593 /* 39952 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12594 /* 39956 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12595 /* 39960 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12596 /* 39964 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12597 /* 39968 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12598 /* 39972 */ // MIs[6] vA
12599 /* 39972 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12600 /* 39977 */ // MIs[6] vC
12601 /* 39977 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12602 /* 39982 */ // MIs[5] vB
12603 /* 39982 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12604 /* 39987 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12605 /* 39989 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12606 /* 39989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12607 /* 39992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12608 /* 39994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12609 /* 39998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12610 /* 40002 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12611 /* 40006 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12612 /* 40016 */ GIR_RootConstrainSelectedInstOperands,
12613 /* 40017 */ // GIR_Coverage, 5256,
12614 /* 40017 */ GIR_EraseRootFromParent_Done,
12615 /* 40018 */ // Label 513: @40018
12616 /* 40018 */ GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(40156), // Rule ID 5257 //
12617 /* 40023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12618 /* 40026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12619 /* 40030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12620 /* 40034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12621 /* 40038 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12622 /* 40042 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12623 /* 40046 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12624 /* 40050 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12625 /* 40054 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12626 /* 40058 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12627 /* 40062 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12628 /* 40066 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12629 /* 40070 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12630 /* 40074 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12631 /* 40078 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12632 /* 40082 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12633 /* 40088 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12634 /* 40090 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12635 /* 40094 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12636 /* 40098 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12637 /* 40102 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12638 /* 40106 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12639 /* 40110 */ // MIs[6] vC
12640 /* 40110 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12641 /* 40115 */ // MIs[6] vA
12642 /* 40115 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12643 /* 40120 */ // MIs[5] vB
12644 /* 40120 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12645 /* 40125 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12646 /* 40127 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12647 /* 40127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12648 /* 40130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12649 /* 40132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12650 /* 40136 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12651 /* 40140 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12652 /* 40144 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12653 /* 40154 */ GIR_RootConstrainSelectedInstOperands,
12654 /* 40155 */ // GIR_Coverage, 5257,
12655 /* 40155 */ GIR_EraseRootFromParent_Done,
12656 /* 40156 */ // Label 514: @40156
12657 /* 40156 */ GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(40294), // Rule ID 5258 //
12658 /* 40161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12659 /* 40164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12660 /* 40168 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12661 /* 40172 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12662 /* 40176 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12663 /* 40180 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12664 /* 40184 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12665 /* 40188 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12666 /* 40192 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12667 /* 40196 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12668 /* 40200 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12669 /* 40204 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12670 /* 40208 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12671 /* 40212 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12672 /* 40216 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12673 /* 40220 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12674 /* 40226 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12675 /* 40228 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12676 /* 40232 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12677 /* 40236 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12678 /* 40240 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12679 /* 40244 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12680 /* 40248 */ // MIs[6] vB
12681 /* 40248 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12682 /* 40253 */ // MIs[6] vC
12683 /* 40253 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12684 /* 40258 */ // MIs[5] vA
12685 /* 40258 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12686 /* 40263 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12687 /* 40265 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12688 /* 40265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12689 /* 40268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12690 /* 40270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12691 /* 40274 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12692 /* 40278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12693 /* 40282 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12694 /* 40292 */ GIR_RootConstrainSelectedInstOperands,
12695 /* 40293 */ // GIR_Coverage, 5258,
12696 /* 40293 */ GIR_EraseRootFromParent_Done,
12697 /* 40294 */ // Label 515: @40294
12698 /* 40294 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(40432), // Rule ID 5259 //
12699 /* 40299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12700 /* 40302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12701 /* 40306 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12702 /* 40310 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12703 /* 40314 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12704 /* 40318 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12705 /* 40322 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12706 /* 40326 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12707 /* 40330 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12708 /* 40334 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12709 /* 40338 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12710 /* 40342 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12711 /* 40346 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12712 /* 40350 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12713 /* 40354 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12714 /* 40358 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12715 /* 40364 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12716 /* 40366 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12717 /* 40370 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12718 /* 40374 */ GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v4s32,
12719 /* 40378 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
12720 /* 40382 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12721 /* 40386 */ // MIs[6] vC
12722 /* 40386 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12723 /* 40391 */ // MIs[6] vB
12724 /* 40391 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12725 /* 40396 */ // MIs[5] vA
12726 /* 40396 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12727 /* 40401 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12728 /* 40403 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vA)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12729 /* 40403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12730 /* 40406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12731 /* 40408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
12732 /* 40412 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12733 /* 40416 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
12734 /* 40420 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12735 /* 40430 */ GIR_RootConstrainSelectedInstOperands,
12736 /* 40431 */ // GIR_Coverage, 5259,
12737 /* 40431 */ GIR_EraseRootFromParent_Done,
12738 /* 40432 */ // Label 516: @40432
12739 /* 40432 */ GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(40570), // Rule ID 5200 //
12740 /* 40437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12741 /* 40440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12742 /* 40444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12743 /* 40448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12744 /* 40452 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12745 /* 40456 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12746 /* 40460 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12747 /* 40464 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12748 /* 40468 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12749 /* 40472 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12750 /* 40476 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12751 /* 40480 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12752 /* 40484 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12753 /* 40488 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12754 /* 40492 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12755 /* 40496 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12756 /* 40502 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12757 /* 40504 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12758 /* 40508 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12759 /* 40512 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
12760 /* 40516 */ // MIs[5] vC
12761 /* 40516 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12762 /* 40521 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
12763 /* 40525 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12764 /* 40529 */ // MIs[6] vA
12765 /* 40529 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12766 /* 40534 */ // MIs[6] vB
12767 /* 40534 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12768 /* 40539 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12769 /* 40541 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12770 /* 40541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12771 /* 40544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12772 /* 40546 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
12773 /* 40550 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12774 /* 40554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
12775 /* 40558 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12776 /* 40568 */ GIR_RootConstrainSelectedInstOperands,
12777 /* 40569 */ // GIR_Coverage, 5200,
12778 /* 40569 */ GIR_EraseRootFromParent_Done,
12779 /* 40570 */ // Label 517: @40570
12780 /* 40570 */ GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(40708), // Rule ID 5201 //
12781 /* 40575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12782 /* 40578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12783 /* 40582 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12784 /* 40586 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12785 /* 40590 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12786 /* 40594 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12787 /* 40598 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12788 /* 40602 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12789 /* 40606 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12790 /* 40610 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12791 /* 40614 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12792 /* 40618 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12793 /* 40622 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12794 /* 40626 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12795 /* 40630 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12796 /* 40634 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12797 /* 40640 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12798 /* 40642 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12799 /* 40646 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12800 /* 40650 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
12801 /* 40654 */ // MIs[5] vC
12802 /* 40654 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12803 /* 40659 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
12804 /* 40663 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12805 /* 40667 */ // MIs[6] vB
12806 /* 40667 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12807 /* 40672 */ // MIs[6] vA
12808 /* 40672 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12809 /* 40677 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12810 /* 40679 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12811 /* 40679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12812 /* 40682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12813 /* 40684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
12814 /* 40688 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12815 /* 40692 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
12816 /* 40696 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12817 /* 40706 */ GIR_RootConstrainSelectedInstOperands,
12818 /* 40707 */ // GIR_Coverage, 5201,
12819 /* 40707 */ GIR_EraseRootFromParent_Done,
12820 /* 40708 */ // Label 518: @40708
12821 /* 40708 */ GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(40846), // Rule ID 5202 //
12822 /* 40713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12823 /* 40716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12824 /* 40720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12825 /* 40724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12826 /* 40728 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12827 /* 40732 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12828 /* 40736 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12829 /* 40740 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12830 /* 40744 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12831 /* 40748 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12832 /* 40752 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12833 /* 40756 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12834 /* 40760 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12835 /* 40764 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12836 /* 40768 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12837 /* 40772 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12838 /* 40778 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12839 /* 40780 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12840 /* 40784 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12841 /* 40788 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
12842 /* 40792 */ // MIs[5] vB
12843 /* 40792 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12844 /* 40797 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
12845 /* 40801 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12846 /* 40805 */ // MIs[6] vA
12847 /* 40805 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12848 /* 40810 */ // MIs[6] vC
12849 /* 40810 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12850 /* 40815 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12851 /* 40817 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12852 /* 40817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12853 /* 40820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12854 /* 40822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
12855 /* 40826 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12856 /* 40830 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
12857 /* 40834 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12858 /* 40844 */ GIR_RootConstrainSelectedInstOperands,
12859 /* 40845 */ // GIR_Coverage, 5202,
12860 /* 40845 */ GIR_EraseRootFromParent_Done,
12861 /* 40846 */ // Label 519: @40846
12862 /* 40846 */ GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(40984), // Rule ID 5203 //
12863 /* 40851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12864 /* 40854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12865 /* 40858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12866 /* 40862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12867 /* 40866 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12868 /* 40870 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12869 /* 40874 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12870 /* 40878 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12871 /* 40882 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12872 /* 40886 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12873 /* 40890 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12874 /* 40894 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12875 /* 40898 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12876 /* 40902 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12877 /* 40906 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12878 /* 40910 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12879 /* 40916 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12880 /* 40918 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12881 /* 40922 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12882 /* 40926 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
12883 /* 40930 */ // MIs[5] vB
12884 /* 40930 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12885 /* 40935 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
12886 /* 40939 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12887 /* 40943 */ // MIs[6] vC
12888 /* 40943 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12889 /* 40948 */ // MIs[6] vA
12890 /* 40948 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
12891 /* 40953 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12892 /* 40955 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12893 /* 40955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12894 /* 40958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12895 /* 40960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
12896 /* 40964 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12897 /* 40968 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
12898 /* 40972 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12899 /* 40982 */ GIR_RootConstrainSelectedInstOperands,
12900 /* 40983 */ // GIR_Coverage, 5203,
12901 /* 40983 */ GIR_EraseRootFromParent_Done,
12902 /* 40984 */ // Label 520: @40984
12903 /* 40984 */ GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(41122), // Rule ID 5204 //
12904 /* 40989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12905 /* 40992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12906 /* 40996 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12907 /* 41000 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12908 /* 41004 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12909 /* 41008 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12910 /* 41012 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12911 /* 41016 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12912 /* 41020 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12913 /* 41024 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12914 /* 41028 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12915 /* 41032 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12916 /* 41036 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12917 /* 41040 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12918 /* 41044 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12919 /* 41048 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12920 /* 41054 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12921 /* 41056 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12922 /* 41060 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12923 /* 41064 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
12924 /* 41068 */ // MIs[5] vA
12925 /* 41068 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12926 /* 41073 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
12927 /* 41077 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12928 /* 41081 */ // MIs[6] vB
12929 /* 41081 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
12930 /* 41086 */ // MIs[6] vC
12931 /* 41086 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12932 /* 41091 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12933 /* 41093 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12934 /* 41093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12935 /* 41096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12936 /* 41098 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
12937 /* 41102 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12938 /* 41106 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
12939 /* 41110 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12940 /* 41120 */ GIR_RootConstrainSelectedInstOperands,
12941 /* 41121 */ // GIR_Coverage, 5204,
12942 /* 41121 */ GIR_EraseRootFromParent_Done,
12943 /* 41122 */ // Label 521: @41122
12944 /* 41122 */ GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(41260), // Rule ID 5205 //
12945 /* 41127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12946 /* 41130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12947 /* 41134 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12948 /* 41138 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12949 /* 41142 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12950 /* 41146 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12951 /* 41150 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12952 /* 41154 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12953 /* 41158 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12954 /* 41162 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12955 /* 41166 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12956 /* 41170 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12957 /* 41174 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12958 /* 41178 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
12959 /* 41182 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
12960 /* 41186 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12961 /* 41192 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12962 /* 41194 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
12963 /* 41198 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
12964 /* 41202 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
12965 /* 41206 */ // MIs[5] vA
12966 /* 41206 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
12967 /* 41211 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
12968 /* 41215 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
12969 /* 41219 */ // MIs[6] vC
12970 /* 41219 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12971 /* 41224 */ // MIs[6] vB
12972 /* 41224 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
12973 /* 41229 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
12974 /* 41231 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
12975 /* 41231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
12976 /* 41234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
12977 /* 41236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
12978 /* 41240 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
12979 /* 41244 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
12980 /* 41248 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
12981 /* 41258 */ GIR_RootConstrainSelectedInstOperands,
12982 /* 41259 */ // GIR_Coverage, 5205,
12983 /* 41259 */ GIR_EraseRootFromParent_Done,
12984 /* 41260 */ // Label 522: @41260
12985 /* 41260 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(41398), // Rule ID 5212 //
12986 /* 41265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
12987 /* 41268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
12988 /* 41272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12989 /* 41276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12990 /* 41280 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12991 /* 41284 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12992 /* 41288 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12993 /* 41292 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
12994 /* 41296 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
12995 /* 41300 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
12996 /* 41304 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12997 /* 41308 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
12998 /* 41312 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
12999 /* 41316 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13000 /* 41320 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13001 /* 41324 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13002 /* 41330 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13003 /* 41332 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13004 /* 41336 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13005 /* 41340 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13006 /* 41344 */ // MIs[5] vC
13007 /* 41344 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13008 /* 41349 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13009 /* 41353 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13010 /* 41357 */ // MIs[6] vA
13011 /* 41357 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13012 /* 41362 */ // MIs[6] vB
13013 /* 41362 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
13014 /* 41367 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13015 /* 41369 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13016 /* 41369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13017 /* 41372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13018 /* 41374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13019 /* 41378 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13020 /* 41382 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
13021 /* 41386 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13022 /* 41396 */ GIR_RootConstrainSelectedInstOperands,
13023 /* 41397 */ // GIR_Coverage, 5212,
13024 /* 41397 */ GIR_EraseRootFromParent_Done,
13025 /* 41398 */ // Label 523: @41398
13026 /* 41398 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(41536), // Rule ID 5213 //
13027 /* 41403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13028 /* 41406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13029 /* 41410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13030 /* 41414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13031 /* 41418 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13032 /* 41422 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13033 /* 41426 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13034 /* 41430 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13035 /* 41434 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13036 /* 41438 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13037 /* 41442 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13038 /* 41446 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13039 /* 41450 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13040 /* 41454 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13041 /* 41458 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13042 /* 41462 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13043 /* 41468 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13044 /* 41470 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13045 /* 41474 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13046 /* 41478 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13047 /* 41482 */ // MIs[5] vC
13048 /* 41482 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13049 /* 41487 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13050 /* 41491 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13051 /* 41495 */ // MIs[6] vB
13052 /* 41495 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13053 /* 41500 */ // MIs[6] vA
13054 /* 41500 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13055 /* 41505 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13056 /* 41507 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13057 /* 41507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13058 /* 41510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13059 /* 41512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13060 /* 41516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13061 /* 41520 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
13062 /* 41524 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13063 /* 41534 */ GIR_RootConstrainSelectedInstOperands,
13064 /* 41535 */ // GIR_Coverage, 5213,
13065 /* 41535 */ GIR_EraseRootFromParent_Done,
13066 /* 41536 */ // Label 524: @41536
13067 /* 41536 */ GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(41674), // Rule ID 5214 //
13068 /* 41541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13069 /* 41544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13070 /* 41548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13071 /* 41552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13072 /* 41556 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13073 /* 41560 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13074 /* 41564 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13075 /* 41568 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13076 /* 41572 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13077 /* 41576 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13078 /* 41580 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13079 /* 41584 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13080 /* 41588 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13081 /* 41592 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13082 /* 41596 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13083 /* 41600 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13084 /* 41606 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13085 /* 41608 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13086 /* 41612 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13087 /* 41616 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13088 /* 41620 */ // MIs[5] vB
13089 /* 41620 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13090 /* 41625 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13091 /* 41629 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13092 /* 41633 */ // MIs[6] vA
13093 /* 41633 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13094 /* 41638 */ // MIs[6] vC
13095 /* 41638 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13096 /* 41643 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13097 /* 41645 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13098 /* 41645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13099 /* 41648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13100 /* 41650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13101 /* 41654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13102 /* 41658 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
13103 /* 41662 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13104 /* 41672 */ GIR_RootConstrainSelectedInstOperands,
13105 /* 41673 */ // GIR_Coverage, 5214,
13106 /* 41673 */ GIR_EraseRootFromParent_Done,
13107 /* 41674 */ // Label 525: @41674
13108 /* 41674 */ GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(41812), // Rule ID 5215 //
13109 /* 41679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13110 /* 41682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13111 /* 41686 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13112 /* 41690 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13113 /* 41694 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13114 /* 41698 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13115 /* 41702 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13116 /* 41706 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13117 /* 41710 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13118 /* 41714 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13119 /* 41718 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13120 /* 41722 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13121 /* 41726 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13122 /* 41730 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13123 /* 41734 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13124 /* 41738 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13125 /* 41744 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13126 /* 41746 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13127 /* 41750 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13128 /* 41754 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13129 /* 41758 */ // MIs[5] vB
13130 /* 41758 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13131 /* 41763 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13132 /* 41767 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13133 /* 41771 */ // MIs[6] vC
13134 /* 41771 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13135 /* 41776 */ // MIs[6] vA
13136 /* 41776 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13137 /* 41781 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13138 /* 41783 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13139 /* 41783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13140 /* 41786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13141 /* 41788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13142 /* 41792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13143 /* 41796 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
13144 /* 41800 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13145 /* 41810 */ GIR_RootConstrainSelectedInstOperands,
13146 /* 41811 */ // GIR_Coverage, 5215,
13147 /* 41811 */ GIR_EraseRootFromParent_Done,
13148 /* 41812 */ // Label 526: @41812
13149 /* 41812 */ GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(41950), // Rule ID 5216 //
13150 /* 41817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13151 /* 41820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13152 /* 41824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13153 /* 41828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13154 /* 41832 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13155 /* 41836 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13156 /* 41840 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13157 /* 41844 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13158 /* 41848 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13159 /* 41852 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13160 /* 41856 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13161 /* 41860 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13162 /* 41864 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13163 /* 41868 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13164 /* 41872 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13165 /* 41876 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13166 /* 41882 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13167 /* 41884 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13168 /* 41888 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13169 /* 41892 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13170 /* 41896 */ // MIs[5] vA
13171 /* 41896 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13172 /* 41901 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13173 /* 41905 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13174 /* 41909 */ // MIs[6] vB
13175 /* 41909 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13176 /* 41914 */ // MIs[6] vC
13177 /* 41914 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13178 /* 41919 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13179 /* 41921 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13180 /* 41921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13181 /* 41924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13182 /* 41926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13183 /* 41930 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13184 /* 41934 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
13185 /* 41938 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13186 /* 41948 */ GIR_RootConstrainSelectedInstOperands,
13187 /* 41949 */ // GIR_Coverage, 5216,
13188 /* 41949 */ GIR_EraseRootFromParent_Done,
13189 /* 41950 */ // Label 527: @41950
13190 /* 41950 */ GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(42088), // Rule ID 5217 //
13191 /* 41955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13192 /* 41958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13193 /* 41962 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13194 /* 41966 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13195 /* 41970 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13196 /* 41974 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13197 /* 41978 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13198 /* 41982 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13199 /* 41986 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13200 /* 41990 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13201 /* 41994 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13202 /* 41998 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13203 /* 42002 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13204 /* 42006 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13205 /* 42010 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13206 /* 42014 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13207 /* 42020 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13208 /* 42022 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13209 /* 42026 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13210 /* 42030 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13211 /* 42034 */ // MIs[5] vA
13212 /* 42034 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13213 /* 42039 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13214 /* 42043 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13215 /* 42047 */ // MIs[6] vC
13216 /* 42047 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13217 /* 42052 */ // MIs[6] vB
13218 /* 42052 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
13219 /* 42057 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13220 /* 42059 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13221 /* 42059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13222 /* 42062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13223 /* 42064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13224 /* 42068 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13225 /* 42072 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vC
13226 /* 42076 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13227 /* 42086 */ GIR_RootConstrainSelectedInstOperands,
13228 /* 42087 */ // GIR_Coverage, 5217,
13229 /* 42087 */ GIR_EraseRootFromParent_Done,
13230 /* 42088 */ // Label 528: @42088
13231 /* 42088 */ GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(42226), // Rule ID 5224 //
13232 /* 42093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13233 /* 42096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13234 /* 42100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13235 /* 42104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13236 /* 42108 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13237 /* 42112 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13238 /* 42116 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13239 /* 42120 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13240 /* 42124 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13241 /* 42128 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13242 /* 42132 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13243 /* 42136 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13244 /* 42140 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13245 /* 42144 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13246 /* 42148 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13247 /* 42152 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13248 /* 42158 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13249 /* 42160 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13250 /* 42164 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13251 /* 42168 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13252 /* 42172 */ // MIs[5] vC
13253 /* 42172 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13254 /* 42177 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13255 /* 42181 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13256 /* 42185 */ // MIs[6] vA
13257 /* 42185 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13258 /* 42190 */ // MIs[6] vB
13259 /* 42190 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13260 /* 42195 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13261 /* 42197 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13262 /* 42197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13263 /* 42200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13264 /* 42202 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
13265 /* 42206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13266 /* 42210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13267 /* 42214 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13268 /* 42224 */ GIR_RootConstrainSelectedInstOperands,
13269 /* 42225 */ // GIR_Coverage, 5224,
13270 /* 42225 */ GIR_EraseRootFromParent_Done,
13271 /* 42226 */ // Label 529: @42226
13272 /* 42226 */ GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(42364), // Rule ID 5225 //
13273 /* 42231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13274 /* 42234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13275 /* 42238 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13276 /* 42242 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13277 /* 42246 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13278 /* 42250 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13279 /* 42254 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13280 /* 42258 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13281 /* 42262 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13282 /* 42266 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13283 /* 42270 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13284 /* 42274 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13285 /* 42278 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13286 /* 42282 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13287 /* 42286 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13288 /* 42290 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13289 /* 42296 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13290 /* 42298 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13291 /* 42302 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13292 /* 42306 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13293 /* 42310 */ // MIs[5] vC
13294 /* 42310 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13295 /* 42315 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13296 /* 42319 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13297 /* 42323 */ // MIs[6] vB
13298 /* 42323 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13299 /* 42328 */ // MIs[6] vA
13300 /* 42328 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
13301 /* 42333 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13302 /* 42335 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13303 /* 42335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13304 /* 42338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13305 /* 42340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
13306 /* 42344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13307 /* 42348 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13308 /* 42352 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13309 /* 42362 */ GIR_RootConstrainSelectedInstOperands,
13310 /* 42363 */ // GIR_Coverage, 5225,
13311 /* 42363 */ GIR_EraseRootFromParent_Done,
13312 /* 42364 */ // Label 530: @42364
13313 /* 42364 */ GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(42502), // Rule ID 5226 //
13314 /* 42369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13315 /* 42372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13316 /* 42376 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13317 /* 42380 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13318 /* 42384 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13319 /* 42388 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13320 /* 42392 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13321 /* 42396 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13322 /* 42400 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13323 /* 42404 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13324 /* 42408 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13325 /* 42412 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13326 /* 42416 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13327 /* 42420 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13328 /* 42424 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13329 /* 42428 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13330 /* 42434 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13331 /* 42436 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13332 /* 42440 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13333 /* 42444 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13334 /* 42448 */ // MIs[5] vB
13335 /* 42448 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13336 /* 42453 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13337 /* 42457 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13338 /* 42461 */ // MIs[6] vA
13339 /* 42461 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13340 /* 42466 */ // MIs[6] vC
13341 /* 42466 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13342 /* 42471 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13343 /* 42473 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13344 /* 42473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13345 /* 42476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13346 /* 42478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
13347 /* 42482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13348 /* 42486 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13349 /* 42490 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13350 /* 42500 */ GIR_RootConstrainSelectedInstOperands,
13351 /* 42501 */ // GIR_Coverage, 5226,
13352 /* 42501 */ GIR_EraseRootFromParent_Done,
13353 /* 42502 */ // Label 531: @42502
13354 /* 42502 */ GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(42640), // Rule ID 5227 //
13355 /* 42507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13356 /* 42510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13357 /* 42514 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13358 /* 42518 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13359 /* 42522 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13360 /* 42526 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13361 /* 42530 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13362 /* 42534 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13363 /* 42538 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13364 /* 42542 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13365 /* 42546 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13366 /* 42550 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13367 /* 42554 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13368 /* 42558 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13369 /* 42562 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13370 /* 42566 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13371 /* 42572 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13372 /* 42574 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13373 /* 42578 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13374 /* 42582 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13375 /* 42586 */ // MIs[5] vB
13376 /* 42586 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13377 /* 42591 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13378 /* 42595 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13379 /* 42599 */ // MIs[6] vC
13380 /* 42599 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13381 /* 42604 */ // MIs[6] vA
13382 /* 42604 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
13383 /* 42609 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13384 /* 42611 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13385 /* 42611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13386 /* 42614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13387 /* 42616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
13388 /* 42620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13389 /* 42624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13390 /* 42628 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13391 /* 42638 */ GIR_RootConstrainSelectedInstOperands,
13392 /* 42639 */ // GIR_Coverage, 5227,
13393 /* 42639 */ GIR_EraseRootFromParent_Done,
13394 /* 42640 */ // Label 532: @42640
13395 /* 42640 */ GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(42778), // Rule ID 5228 //
13396 /* 42645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13397 /* 42648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13398 /* 42652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13399 /* 42656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13400 /* 42660 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13401 /* 42664 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13402 /* 42668 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13403 /* 42672 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13404 /* 42676 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13405 /* 42680 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13406 /* 42684 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13407 /* 42688 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13408 /* 42692 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13409 /* 42696 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13410 /* 42700 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13411 /* 42704 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13412 /* 42710 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13413 /* 42712 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13414 /* 42716 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13415 /* 42720 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13416 /* 42724 */ // MIs[5] vA
13417 /* 42724 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13418 /* 42729 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13419 /* 42733 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13420 /* 42737 */ // MIs[6] vB
13421 /* 42737 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13422 /* 42742 */ // MIs[6] vC
13423 /* 42742 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13424 /* 42747 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13425 /* 42749 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13426 /* 42749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13427 /* 42752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13428 /* 42754 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
13429 /* 42758 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13430 /* 42762 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13431 /* 42766 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13432 /* 42776 */ GIR_RootConstrainSelectedInstOperands,
13433 /* 42777 */ // GIR_Coverage, 5228,
13434 /* 42777 */ GIR_EraseRootFromParent_Done,
13435 /* 42778 */ // Label 533: @42778
13436 /* 42778 */ GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(42916), // Rule ID 5229 //
13437 /* 42783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13438 /* 42786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13439 /* 42790 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13440 /* 42794 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13441 /* 42798 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13442 /* 42802 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13443 /* 42806 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13444 /* 42810 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13445 /* 42814 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13446 /* 42818 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13447 /* 42822 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13448 /* 42826 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13449 /* 42830 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13450 /* 42834 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13451 /* 42838 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13452 /* 42842 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13453 /* 42848 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13454 /* 42850 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13455 /* 42854 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13456 /* 42858 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13457 /* 42862 */ // MIs[5] vA
13458 /* 42862 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13459 /* 42867 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13460 /* 42871 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13461 /* 42875 */ // MIs[6] vC
13462 /* 42875 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13463 /* 42880 */ // MIs[6] vB
13464 /* 42880 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13465 /* 42885 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13466 /* 42887 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13467 /* 42887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13468 /* 42890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13469 /* 42892 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vA
13470 /* 42896 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13471 /* 42900 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13472 /* 42904 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13473 /* 42914 */ GIR_RootConstrainSelectedInstOperands,
13474 /* 42915 */ // GIR_Coverage, 5229,
13475 /* 42915 */ GIR_EraseRootFromParent_Done,
13476 /* 42916 */ // Label 534: @42916
13477 /* 42916 */ GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(43054), // Rule ID 5236 //
13478 /* 42921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13479 /* 42924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13480 /* 42928 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13481 /* 42932 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13482 /* 42936 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13483 /* 42940 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13484 /* 42944 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13485 /* 42948 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13486 /* 42952 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13487 /* 42956 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13488 /* 42960 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13489 /* 42964 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13490 /* 42968 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13491 /* 42972 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13492 /* 42976 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13493 /* 42980 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13494 /* 42986 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13495 /* 42988 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13496 /* 42992 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13497 /* 42996 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13498 /* 43000 */ // MIs[5] vC
13499 /* 43000 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13500 /* 43005 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13501 /* 43009 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13502 /* 43013 */ // MIs[6] vA
13503 /* 43013 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13504 /* 43018 */ // MIs[6] vB
13505 /* 43018 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13506 /* 43023 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13507 /* 43025 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13508 /* 43025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13509 /* 43028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13510 /* 43030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13511 /* 43034 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13512 /* 43038 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
13513 /* 43042 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13514 /* 43052 */ GIR_RootConstrainSelectedInstOperands,
13515 /* 43053 */ // GIR_Coverage, 5236,
13516 /* 43053 */ GIR_EraseRootFromParent_Done,
13517 /* 43054 */ // Label 535: @43054
13518 /* 43054 */ GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(43192), // Rule ID 5237 //
13519 /* 43059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13520 /* 43062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13521 /* 43066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13522 /* 43070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13523 /* 43074 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13524 /* 43078 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13525 /* 43082 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13526 /* 43086 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13527 /* 43090 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13528 /* 43094 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13529 /* 43098 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13530 /* 43102 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13531 /* 43106 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13532 /* 43110 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13533 /* 43114 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13534 /* 43118 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13535 /* 43124 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13536 /* 43126 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13537 /* 43130 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13538 /* 43134 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13539 /* 43138 */ // MIs[5] vC
13540 /* 43138 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13541 /* 43143 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13542 /* 43147 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13543 /* 43151 */ // MIs[6] vB
13544 /* 43151 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13545 /* 43156 */ // MIs[6] vA
13546 /* 43156 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13547 /* 43161 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13548 /* 43163 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13549 /* 43163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13550 /* 43166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13551 /* 43168 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13552 /* 43172 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13553 /* 43176 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
13554 /* 43180 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13555 /* 43190 */ GIR_RootConstrainSelectedInstOperands,
13556 /* 43191 */ // GIR_Coverage, 5237,
13557 /* 43191 */ GIR_EraseRootFromParent_Done,
13558 /* 43192 */ // Label 536: @43192
13559 /* 43192 */ GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(43330), // Rule ID 5238 //
13560 /* 43197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13561 /* 43200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13562 /* 43204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13563 /* 43208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13564 /* 43212 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13565 /* 43216 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13566 /* 43220 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13567 /* 43224 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13568 /* 43228 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13569 /* 43232 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13570 /* 43236 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13571 /* 43240 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13572 /* 43244 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13573 /* 43248 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13574 /* 43252 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13575 /* 43256 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13576 /* 43262 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13577 /* 43264 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13578 /* 43268 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13579 /* 43272 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13580 /* 43276 */ // MIs[5] vB
13581 /* 43276 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13582 /* 43281 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13583 /* 43285 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13584 /* 43289 */ // MIs[6] vA
13585 /* 43289 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13586 /* 43294 */ // MIs[6] vC
13587 /* 43294 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
13588 /* 43299 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13589 /* 43301 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13590 /* 43301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13591 /* 43304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13592 /* 43306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13593 /* 43310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13594 /* 43314 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
13595 /* 43318 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13596 /* 43328 */ GIR_RootConstrainSelectedInstOperands,
13597 /* 43329 */ // GIR_Coverage, 5238,
13598 /* 43329 */ GIR_EraseRootFromParent_Done,
13599 /* 43330 */ // Label 537: @43330
13600 /* 43330 */ GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(43468), // Rule ID 5239 //
13601 /* 43335 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13602 /* 43338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13603 /* 43342 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13604 /* 43346 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13605 /* 43350 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13606 /* 43354 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13607 /* 43358 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13608 /* 43362 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13609 /* 43366 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13610 /* 43370 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13611 /* 43374 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13612 /* 43378 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13613 /* 43382 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13614 /* 43386 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13615 /* 43390 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13616 /* 43394 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13617 /* 43400 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13618 /* 43402 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13619 /* 43406 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13620 /* 43410 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13621 /* 43414 */ // MIs[5] vB
13622 /* 43414 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13623 /* 43419 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13624 /* 43423 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13625 /* 43427 */ // MIs[6] vC
13626 /* 43427 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13627 /* 43432 */ // MIs[6] vA
13628 /* 43432 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13629 /* 43437 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13630 /* 43439 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13631 /* 43439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13632 /* 43442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13633 /* 43444 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13634 /* 43448 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13635 /* 43452 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
13636 /* 43456 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13637 /* 43466 */ GIR_RootConstrainSelectedInstOperands,
13638 /* 43467 */ // GIR_Coverage, 5239,
13639 /* 43467 */ GIR_EraseRootFromParent_Done,
13640 /* 43468 */ // Label 538: @43468
13641 /* 43468 */ GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(43606), // Rule ID 5240 //
13642 /* 43473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13643 /* 43476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13644 /* 43480 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13645 /* 43484 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13646 /* 43488 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13647 /* 43492 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13648 /* 43496 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13649 /* 43500 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13650 /* 43504 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13651 /* 43508 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13652 /* 43512 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13653 /* 43516 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13654 /* 43520 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13655 /* 43524 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13656 /* 43528 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13657 /* 43532 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13658 /* 43538 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13659 /* 43540 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13660 /* 43544 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13661 /* 43548 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13662 /* 43552 */ // MIs[5] vA
13663 /* 43552 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13664 /* 43557 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13665 /* 43561 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13666 /* 43565 */ // MIs[6] vB
13667 /* 43565 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13668 /* 43570 */ // MIs[6] vC
13669 /* 43570 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
13670 /* 43575 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13671 /* 43577 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13672 /* 43577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13673 /* 43580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13674 /* 43582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13675 /* 43586 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13676 /* 43590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
13677 /* 43594 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13678 /* 43604 */ GIR_RootConstrainSelectedInstOperands,
13679 /* 43605 */ // GIR_Coverage, 5240,
13680 /* 43605 */ GIR_EraseRootFromParent_Done,
13681 /* 43606 */ // Label 539: @43606
13682 /* 43606 */ GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(43744), // Rule ID 5241 //
13683 /* 43611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13684 /* 43614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13685 /* 43618 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13686 /* 43622 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13687 /* 43626 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13688 /* 43630 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13689 /* 43634 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13690 /* 43638 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13691 /* 43642 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13692 /* 43646 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13693 /* 43650 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13694 /* 43654 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13695 /* 43658 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13696 /* 43662 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13697 /* 43666 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13698 /* 43670 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13699 /* 43676 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13700 /* 43678 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13701 /* 43682 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13702 /* 43686 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13703 /* 43690 */ // MIs[5] vA
13704 /* 43690 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13705 /* 43695 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13706 /* 43699 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13707 /* 43703 */ // MIs[6] vC
13708 /* 43703 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13709 /* 43708 */ // MIs[6] vB
13710 /* 43708 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13711 /* 43713 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13712 /* 43715 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13713 /* 43715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13714 /* 43718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13715 /* 43720 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vA
13716 /* 43724 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
13717 /* 43728 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
13718 /* 43732 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13719 /* 43742 */ GIR_RootConstrainSelectedInstOperands,
13720 /* 43743 */ // GIR_Coverage, 5241,
13721 /* 43743 */ GIR_EraseRootFromParent_Done,
13722 /* 43744 */ // Label 540: @43744
13723 /* 43744 */ GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(43882), // Rule ID 5248 //
13724 /* 43749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13725 /* 43752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13726 /* 43756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13727 /* 43760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13728 /* 43764 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13729 /* 43768 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13730 /* 43772 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13731 /* 43776 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13732 /* 43780 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13733 /* 43784 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13734 /* 43788 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13735 /* 43792 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13736 /* 43796 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13737 /* 43800 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13738 /* 43804 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13739 /* 43808 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13740 /* 43814 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13741 /* 43816 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13742 /* 43820 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13743 /* 43824 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13744 /* 43828 */ // MIs[5] vC
13745 /* 43828 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13746 /* 43833 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13747 /* 43837 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13748 /* 43841 */ // MIs[6] vA
13749 /* 43841 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13750 /* 43846 */ // MIs[6] vB
13751 /* 43846 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
13752 /* 43851 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13753 /* 43853 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13754 /* 43853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13755 /* 43856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13756 /* 43858 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
13757 /* 43862 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13758 /* 43866 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13759 /* 43870 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13760 /* 43880 */ GIR_RootConstrainSelectedInstOperands,
13761 /* 43881 */ // GIR_Coverage, 5248,
13762 /* 43881 */ GIR_EraseRootFromParent_Done,
13763 /* 43882 */ // Label 541: @43882
13764 /* 43882 */ GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(44020), // Rule ID 5249 //
13765 /* 43887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13766 /* 43890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13767 /* 43894 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13768 /* 43898 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13769 /* 43902 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13770 /* 43906 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13771 /* 43910 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13772 /* 43914 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13773 /* 43918 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13774 /* 43922 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13775 /* 43926 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13776 /* 43930 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13777 /* 43934 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13778 /* 43938 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13779 /* 43942 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13780 /* 43946 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13781 /* 43952 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13782 /* 43954 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13783 /* 43958 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13784 /* 43962 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13785 /* 43966 */ // MIs[5] vC
13786 /* 43966 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13787 /* 43971 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13788 /* 43975 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13789 /* 43979 */ // MIs[6] vB
13790 /* 43979 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13791 /* 43984 */ // MIs[6] vA
13792 /* 43984 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13793 /* 43989 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13794 /* 43991 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13795 /* 43991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13796 /* 43994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13797 /* 43996 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
13798 /* 44000 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13799 /* 44004 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13800 /* 44008 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13801 /* 44018 */ GIR_RootConstrainSelectedInstOperands,
13802 /* 44019 */ // GIR_Coverage, 5249,
13803 /* 44019 */ GIR_EraseRootFromParent_Done,
13804 /* 44020 */ // Label 542: @44020
13805 /* 44020 */ GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(44158), // Rule ID 5250 //
13806 /* 44025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13807 /* 44028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13808 /* 44032 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13809 /* 44036 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13810 /* 44040 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13811 /* 44044 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13812 /* 44048 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13813 /* 44052 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13814 /* 44056 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13815 /* 44060 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13816 /* 44064 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13817 /* 44068 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13818 /* 44072 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13819 /* 44076 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13820 /* 44080 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13821 /* 44084 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13822 /* 44090 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13823 /* 44092 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13824 /* 44096 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13825 /* 44100 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13826 /* 44104 */ // MIs[5] vB
13827 /* 44104 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13828 /* 44109 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13829 /* 44113 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13830 /* 44117 */ // MIs[6] vA
13831 /* 44117 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13832 /* 44122 */ // MIs[6] vC
13833 /* 44122 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13834 /* 44127 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13835 /* 44129 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13836 /* 44129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13837 /* 44132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13838 /* 44134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
13839 /* 44138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13840 /* 44142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13841 /* 44146 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13842 /* 44156 */ GIR_RootConstrainSelectedInstOperands,
13843 /* 44157 */ // GIR_Coverage, 5250,
13844 /* 44157 */ GIR_EraseRootFromParent_Done,
13845 /* 44158 */ // Label 543: @44158
13846 /* 44158 */ GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(44296), // Rule ID 5251 //
13847 /* 44163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13848 /* 44166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13849 /* 44170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13850 /* 44174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13851 /* 44178 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13852 /* 44182 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13853 /* 44186 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13854 /* 44190 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13855 /* 44194 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13856 /* 44198 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13857 /* 44202 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13858 /* 44206 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13859 /* 44210 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13860 /* 44214 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13861 /* 44218 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13862 /* 44222 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13863 /* 44228 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13864 /* 44230 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13865 /* 44234 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13866 /* 44238 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13867 /* 44242 */ // MIs[5] vB
13868 /* 44242 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13869 /* 44247 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13870 /* 44251 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13871 /* 44255 */ // MIs[6] vC
13872 /* 44255 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13873 /* 44260 */ // MIs[6] vA
13874 /* 44260 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13875 /* 44265 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13876 /* 44267 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13877 /* 44267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13878 /* 44270 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13879 /* 44272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
13880 /* 44276 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13881 /* 44280 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13882 /* 44284 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13883 /* 44294 */ GIR_RootConstrainSelectedInstOperands,
13884 /* 44295 */ // GIR_Coverage, 5251,
13885 /* 44295 */ GIR_EraseRootFromParent_Done,
13886 /* 44296 */ // Label 544: @44296
13887 /* 44296 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(44434), // Rule ID 5252 //
13888 /* 44301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13889 /* 44304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13890 /* 44308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13891 /* 44312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13892 /* 44316 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13893 /* 44320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13894 /* 44324 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13895 /* 44328 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13896 /* 44332 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13897 /* 44336 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13898 /* 44340 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13899 /* 44344 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13900 /* 44348 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13901 /* 44352 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13902 /* 44356 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13903 /* 44360 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13904 /* 44366 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13905 /* 44368 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13906 /* 44372 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13907 /* 44376 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13908 /* 44380 */ // MIs[5] vA
13909 /* 44380 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13910 /* 44385 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13911 /* 44389 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13912 /* 44393 */ // MIs[6] vB
13913 /* 44393 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13914 /* 44398 */ // MIs[6] vC
13915 /* 44398 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13916 /* 44403 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13917 /* 44405 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13918 /* 44405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13919 /* 44408 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13920 /* 44410 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
13921 /* 44414 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13922 /* 44418 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13923 /* 44422 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13924 /* 44432 */ GIR_RootConstrainSelectedInstOperands,
13925 /* 44433 */ // GIR_Coverage, 5252,
13926 /* 44433 */ GIR_EraseRootFromParent_Done,
13927 /* 44434 */ // Label 545: @44434
13928 /* 44434 */ GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(44572), // Rule ID 5253 //
13929 /* 44439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13930 /* 44442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13931 /* 44446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13932 /* 44450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13933 /* 44454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13934 /* 44458 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13935 /* 44462 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13936 /* 44466 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13937 /* 44470 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13938 /* 44474 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13939 /* 44478 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13940 /* 44482 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13941 /* 44486 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13942 /* 44490 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13943 /* 44494 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13944 /* 44498 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13945 /* 44504 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13946 /* 44506 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13947 /* 44510 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13948 /* 44514 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13949 /* 44518 */ // MIs[5] vA
13950 /* 44518 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13951 /* 44523 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13952 /* 44527 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13953 /* 44531 */ // MIs[6] vC
13954 /* 44531 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
13955 /* 44536 */ // MIs[6] vB
13956 /* 44536 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
13957 /* 44541 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13958 /* 44543 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
13959 /* 44543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
13960 /* 44546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
13961 /* 44548 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
13962 /* 44552 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
13963 /* 44556 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
13964 /* 44560 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
13965 /* 44570 */ GIR_RootConstrainSelectedInstOperands,
13966 /* 44571 */ // GIR_Coverage, 5253,
13967 /* 44571 */ GIR_EraseRootFromParent_Done,
13968 /* 44572 */ // Label 546: @44572
13969 /* 44572 */ GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(44710), // Rule ID 5260 //
13970 /* 44577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
13971 /* 44580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
13972 /* 44584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13973 /* 44588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13974 /* 44592 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
13975 /* 44596 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
13976 /* 44600 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13977 /* 44604 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
13978 /* 44608 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
13979 /* 44612 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
13980 /* 44616 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13981 /* 44620 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
13982 /* 44624 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
13983 /* 44628 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
13984 /* 44632 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
13985 /* 44636 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13986 /* 44642 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13987 /* 44644 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
13988 /* 44648 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
13989 /* 44652 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
13990 /* 44656 */ // MIs[5] vC
13991 /* 44656 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
13992 /* 44661 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
13993 /* 44665 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
13994 /* 44669 */ // MIs[6] vA
13995 /* 44669 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13996 /* 44674 */ // MIs[6] vB
13997 /* 44674 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
13998 /* 44679 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
13999 /* 44681 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
14000 /* 44681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14001 /* 44684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14002 /* 44686 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14003 /* 44690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
14004 /* 44694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
14005 /* 44698 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
14006 /* 44708 */ GIR_RootConstrainSelectedInstOperands,
14007 /* 44709 */ // GIR_Coverage, 5260,
14008 /* 44709 */ GIR_EraseRootFromParent_Done,
14009 /* 44710 */ // Label 547: @44710
14010 /* 44710 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(44848), // Rule ID 5261 //
14011 /* 44715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14012 /* 44718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14013 /* 44722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14014 /* 44726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14015 /* 44730 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14016 /* 44734 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14017 /* 44738 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14018 /* 44742 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
14019 /* 44746 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14020 /* 44750 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14021 /* 44754 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14022 /* 44758 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
14023 /* 44762 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
14024 /* 44766 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14025 /* 44770 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
14026 /* 44774 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14027 /* 44780 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14028 /* 44782 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
14029 /* 44786 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
14030 /* 44790 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
14031 /* 44794 */ // MIs[5] vC
14032 /* 44794 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
14033 /* 44799 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
14034 /* 44803 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
14035 /* 44807 */ // MIs[6] vB
14036 /* 44807 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
14037 /* 44812 */ // MIs[6] vA
14038 /* 44812 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
14039 /* 44817 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
14040 /* 44819 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
14041 /* 44819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14042 /* 44822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14043 /* 44824 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14044 /* 44828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
14045 /* 44832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
14046 /* 44836 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
14047 /* 44846 */ GIR_RootConstrainSelectedInstOperands,
14048 /* 44847 */ // GIR_Coverage, 5261,
14049 /* 44847 */ GIR_EraseRootFromParent_Done,
14050 /* 44848 */ // Label 548: @44848
14051 /* 44848 */ GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(44986), // Rule ID 5262 //
14052 /* 44853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14053 /* 44856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14054 /* 44860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14055 /* 44864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14056 /* 44868 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14057 /* 44872 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14058 /* 44876 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14059 /* 44880 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
14060 /* 44884 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14061 /* 44888 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14062 /* 44892 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14063 /* 44896 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
14064 /* 44900 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
14065 /* 44904 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14066 /* 44908 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
14067 /* 44912 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14068 /* 44918 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14069 /* 44920 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
14070 /* 44924 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
14071 /* 44928 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
14072 /* 44932 */ // MIs[5] vB
14073 /* 44932 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
14074 /* 44937 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
14075 /* 44941 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
14076 /* 44945 */ // MIs[6] vA
14077 /* 44945 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14078 /* 44950 */ // MIs[6] vC
14079 /* 44950 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
14080 /* 44955 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
14081 /* 44957 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
14082 /* 44957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14083 /* 44960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14084 /* 44962 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14085 /* 44966 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
14086 /* 44970 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
14087 /* 44974 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
14088 /* 44984 */ GIR_RootConstrainSelectedInstOperands,
14089 /* 44985 */ // GIR_Coverage, 5262,
14090 /* 44985 */ GIR_EraseRootFromParent_Done,
14091 /* 44986 */ // Label 549: @44986
14092 /* 44986 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(45124), // Rule ID 5263 //
14093 /* 44991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14094 /* 44994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14095 /* 44998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14096 /* 45002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14097 /* 45006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14098 /* 45010 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14099 /* 45014 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14100 /* 45018 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
14101 /* 45022 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14102 /* 45026 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14103 /* 45030 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14104 /* 45034 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
14105 /* 45038 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
14106 /* 45042 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14107 /* 45046 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
14108 /* 45050 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14109 /* 45056 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14110 /* 45058 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
14111 /* 45062 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
14112 /* 45066 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
14113 /* 45070 */ // MIs[5] vB
14114 /* 45070 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
14115 /* 45075 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
14116 /* 45079 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
14117 /* 45083 */ // MIs[6] vC
14118 /* 45083 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
14119 /* 45088 */ // MIs[6] vA
14120 /* 45088 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
14121 /* 45093 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
14122 /* 45095 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vA))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
14123 /* 45095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14124 /* 45098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14125 /* 45100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14126 /* 45104 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
14127 /* 45108 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
14128 /* 45112 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
14129 /* 45122 */ GIR_RootConstrainSelectedInstOperands,
14130 /* 45123 */ // GIR_Coverage, 5263,
14131 /* 45123 */ GIR_EraseRootFromParent_Done,
14132 /* 45124 */ // Label 550: @45124
14133 /* 45124 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(45262), // Rule ID 5264 //
14134 /* 45129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14135 /* 45132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14136 /* 45136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14137 /* 45140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14138 /* 45144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14139 /* 45148 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14140 /* 45152 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14141 /* 45156 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
14142 /* 45160 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14143 /* 45164 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14144 /* 45168 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14145 /* 45172 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
14146 /* 45176 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
14147 /* 45180 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14148 /* 45184 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
14149 /* 45188 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14150 /* 45194 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14151 /* 45196 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
14152 /* 45200 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
14153 /* 45204 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
14154 /* 45208 */ // MIs[5] vA
14155 /* 45208 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14156 /* 45213 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
14157 /* 45217 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
14158 /* 45221 */ // MIs[6] vB
14159 /* 45221 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/2,
14160 /* 45226 */ // MIs[6] vC
14161 /* 45226 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
14162 /* 45231 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
14163 /* 45233 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
14164 /* 45233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14165 /* 45236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14166 /* 45238 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14167 /* 45242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
14168 /* 45246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
14169 /* 45250 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
14170 /* 45260 */ GIR_RootConstrainSelectedInstOperands,
14171 /* 45261 */ // GIR_Coverage, 5264,
14172 /* 45261 */ GIR_EraseRootFromParent_Done,
14173 /* 45262 */ // Label 551: @45262
14174 /* 45262 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(45400), // Rule ID 5265 //
14175 /* 45267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14176 /* 45270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14177 /* 45274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14178 /* 45278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14179 /* 45282 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14180 /* 45286 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14181 /* 45290 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14182 /* 45294 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
14183 /* 45298 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14184 /* 45302 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14185 /* 45306 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14186 /* 45310 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
14187 /* 45314 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
14188 /* 45318 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14189 /* 45322 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
14190 /* 45326 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14191 /* 45332 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14192 /* 45334 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
14193 /* 45338 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
14194 /* 45342 */ GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_v4s32,
14195 /* 45346 */ // MIs[5] vA
14196 /* 45346 */ GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14197 /* 45351 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
14198 /* 45355 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
14199 /* 45359 */ // MIs[6] vC
14200 /* 45359 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
14201 /* 45364 */ // MIs[6] vB
14202 /* 45364 */ GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
14203 /* 45369 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
14204 /* 45371 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB)), immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, v4i32:{ *:[v4i32] }:$vB))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 150:{ *:[i32] })
14205 /* 45371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14206 /* 45374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14207 /* 45376 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14208 /* 45380 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vB
14209 /* 45384 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vC
14210 /* 45388 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(150),
14211 /* 45398 */ GIR_RootConstrainSelectedInstOperands,
14212 /* 45399 */ // GIR_Coverage, 5265,
14213 /* 45399 */ GIR_EraseRootFromParent_Done,
14214 /* 45400 */ // Label 552: @45400
14215 /* 45400 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(45494), // Rule ID 4952 //
14216 /* 45405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
14217 /* 45408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14218 /* 45412 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14219 /* 45416 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14220 /* 45420 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14221 /* 45424 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14222 /* 45428 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14223 /* 45432 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14224 /* 45436 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14225 /* 45440 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14226 /* 45444 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14227 /* 45448 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14228 /* 45454 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14229 /* 45456 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14230 /* 45460 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14231 /* 45464 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
14232 /* 45468 */ // MIs[4] C
14233 /* 45468 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14234 /* 45473 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
14235 /* 45475 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$A), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, v4i32:{ *:[v4i32] }:$B)) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
14236 /* 45475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
14237 /* 45478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14238 /* 45480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // A
14239 /* 45484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // B
14240 /* 45488 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // C
14241 /* 45492 */ GIR_RootConstrainSelectedInstOperands,
14242 /* 45493 */ // GIR_Coverage, 4952,
14243 /* 45493 */ GIR_EraseRootFromParent_Done,
14244 /* 45494 */ // Label 553: @45494
14245 /* 45494 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(45588), // Rule ID 1588 //
14246 /* 45499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
14247 /* 45502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14248 /* 45506 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14249 /* 45510 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14250 /* 45514 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14251 /* 45518 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14252 /* 45522 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14253 /* 45526 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14254 /* 45530 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14255 /* 45534 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14256 /* 45538 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14257 /* 45542 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14258 /* 45548 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14259 /* 45550 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14260 /* 45554 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14261 /* 45558 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
14262 /* 45562 */ // MIs[4] C
14263 /* 45562 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
14264 /* 45567 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
14265 /* 45569 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$A), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$B, v4i32:{ *:[v4i32] }:$C)) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
14266 /* 45569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
14267 /* 45572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14268 /* 45574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // A
14269 /* 45578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // B
14270 /* 45582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // C
14271 /* 45586 */ GIR_RootConstrainSelectedInstOperands,
14272 /* 45587 */ // GIR_Coverage, 1588,
14273 /* 45587 */ GIR_EraseRootFromParent_Done,
14274 /* 45588 */ // Label 554: @45588
14275 /* 45588 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(45682), // Rule ID 4954 //
14276 /* 45593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
14277 /* 45596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14278 /* 45600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14279 /* 45604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14280 /* 45608 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14281 /* 45612 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14282 /* 45616 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14283 /* 45620 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14284 /* 45624 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14285 /* 45628 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14286 /* 45632 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14287 /* 45636 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14288 /* 45642 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14289 /* 45644 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14290 /* 45648 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14291 /* 45652 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
14292 /* 45656 */ // MIs[4] C
14293 /* 45656 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14294 /* 45661 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
14295 /* 45663 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, v4i32:{ *:[v4i32] }:$B)) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
14296 /* 45663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
14297 /* 45666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14298 /* 45668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
14299 /* 45672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // B
14300 /* 45676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // C
14301 /* 45680 */ GIR_RootConstrainSelectedInstOperands,
14302 /* 45681 */ // GIR_Coverage, 4954,
14303 /* 45681 */ GIR_EraseRootFromParent_Done,
14304 /* 45682 */ // Label 555: @45682
14305 /* 45682 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(45776), // Rule ID 4953 //
14306 /* 45687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
14307 /* 45690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14308 /* 45694 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14309 /* 45698 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14310 /* 45702 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14311 /* 45706 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14312 /* 45710 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14313 /* 45714 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14314 /* 45718 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14315 /* 45722 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14316 /* 45726 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14317 /* 45730 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14318 /* 45736 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14319 /* 45738 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14320 /* 45742 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14321 /* 45746 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
14322 /* 45750 */ // MIs[4] C
14323 /* 45750 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
14324 /* 45755 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
14325 /* 45757 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$B, v4i32:{ *:[v4i32] }:$C)) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
14326 /* 45757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
14327 /* 45760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14328 /* 45762 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
14329 /* 45766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // B
14330 /* 45770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // C
14331 /* 45774 */ GIR_RootConstrainSelectedInstOperands,
14332 /* 45775 */ // GIR_Coverage, 4953,
14333 /* 45775 */ GIR_EraseRootFromParent_Done,
14334 /* 45776 */ // Label 556: @45776
14335 /* 45776 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(45870), // Rule ID 4955 //
14336 /* 45781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
14337 /* 45784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14338 /* 45788 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14339 /* 45792 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14340 /* 45796 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14341 /* 45800 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14342 /* 45804 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14343 /* 45808 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14344 /* 45812 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14345 /* 45816 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14346 /* 45820 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14347 /* 45824 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14348 /* 45828 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14349 /* 45832 */ // MIs[3] C
14350 /* 45832 */ GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
14351 /* 45837 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14352 /* 45841 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14353 /* 45847 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14354 /* 45849 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
14355 /* 45851 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$B, v4i32:{ *:[v4i32] }:$C), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$A)) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
14356 /* 45851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
14357 /* 45854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14358 /* 45856 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // A
14359 /* 45860 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // B
14360 /* 45864 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // C
14361 /* 45868 */ GIR_RootConstrainSelectedInstOperands,
14362 /* 45869 */ // GIR_Coverage, 4955,
14363 /* 45869 */ GIR_EraseRootFromParent_Done,
14364 /* 45870 */ // Label 557: @45870
14365 /* 45870 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(45964), // Rule ID 4957 //
14366 /* 45875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
14367 /* 45878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14368 /* 45882 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14369 /* 45886 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14370 /* 45890 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14371 /* 45894 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14372 /* 45898 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14373 /* 45902 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14374 /* 45906 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14375 /* 45910 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14376 /* 45914 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14377 /* 45918 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14378 /* 45922 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14379 /* 45926 */ // MIs[3] C
14380 /* 45926 */ GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
14381 /* 45931 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14382 /* 45935 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14383 /* 45941 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14384 /* 45943 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
14385 /* 45945 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, v4i32:{ *:[v4i32] }:$B), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$A)) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
14386 /* 45945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
14387 /* 45948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14388 /* 45950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // A
14389 /* 45954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // B
14390 /* 45958 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // C
14391 /* 45962 */ GIR_RootConstrainSelectedInstOperands,
14392 /* 45963 */ // GIR_Coverage, 4957,
14393 /* 45963 */ GIR_EraseRootFromParent_Done,
14394 /* 45964 */ // Label 558: @45964
14395 /* 45964 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(46058), // Rule ID 4956 //
14396 /* 45969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
14397 /* 45972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14398 /* 45976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14399 /* 45980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14400 /* 45984 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14401 /* 45988 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14402 /* 45992 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14403 /* 45996 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14404 /* 46000 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14405 /* 46004 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14406 /* 46008 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14407 /* 46012 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14408 /* 46016 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14409 /* 46020 */ // MIs[3] C
14410 /* 46020 */ GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
14411 /* 46025 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14412 /* 46029 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14413 /* 46035 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14414 /* 46037 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
14415 /* 46039 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$B, v4i32:{ *:[v4i32] }:$C), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, immAllOnesV:{ *:[v4i32] }))) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
14416 /* 46039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
14417 /* 46042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14418 /* 46044 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // A
14419 /* 46048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // B
14420 /* 46052 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // C
14421 /* 46056 */ GIR_RootConstrainSelectedInstOperands,
14422 /* 46057 */ // GIR_Coverage, 4956,
14423 /* 46057 */ GIR_EraseRootFromParent_Done,
14424 /* 46058 */ // Label 559: @46058
14425 /* 46058 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(46152), // Rule ID 4958 //
14426 /* 46063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
14427 /* 46066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14428 /* 46070 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14429 /* 46074 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14430 /* 46078 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14431 /* 46082 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14432 /* 46086 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14433 /* 46090 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14434 /* 46094 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14435 /* 46098 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14436 /* 46102 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14437 /* 46106 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14438 /* 46110 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14439 /* 46114 */ // MIs[3] C
14440 /* 46114 */ GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
14441 /* 46119 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14442 /* 46123 */ GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14443 /* 46129 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14444 /* 46131 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
14445 /* 46133 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, v4i32:{ *:[v4i32] }:$B), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$C, immAllOnesV:{ *:[v4i32] }))) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
14446 /* 46133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
14447 /* 46136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14448 /* 46138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // A
14449 /* 46142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // B
14450 /* 46146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // C
14451 /* 46150 */ GIR_RootConstrainSelectedInstOperands,
14452 /* 46151 */ // GIR_Coverage, 4958,
14453 /* 46151 */ GIR_EraseRootFromParent_Done,
14454 /* 46152 */ // Label 560: @46152
14455 /* 46152 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(46239), // Rule ID 4978 //
14456 /* 46157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14457 /* 46160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14458 /* 46164 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14459 /* 46168 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14460 /* 46172 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14461 /* 46176 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14462 /* 46180 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14463 /* 46184 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14464 /* 46188 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14465 /* 46192 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14466 /* 46196 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14467 /* 46200 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14468 /* 46206 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14469 /* 46208 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14470 /* 46210 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 241:{ *:[i32] })
14471 /* 46210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14472 /* 46213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14473 /* 46215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14474 /* 46219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
14475 /* 46223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
14476 /* 46227 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(241),
14477 /* 46237 */ GIR_RootConstrainSelectedInstOperands,
14478 /* 46238 */ // GIR_Coverage, 4978,
14479 /* 46238 */ GIR_EraseRootFromParent_Done,
14480 /* 46239 */ // Label 561: @46239
14481 /* 46239 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(46324), // Rule ID 4972 //
14482 /* 46244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14483 /* 46247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14484 /* 46251 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14485 /* 46255 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
14486 /* 46259 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14487 /* 46263 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14488 /* 46267 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14489 /* 46271 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14490 /* 46275 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14491 /* 46279 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14492 /* 46283 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14493 /* 46287 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14494 /* 46293 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14495 /* 46295 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14496 /* 46297 */ // (or:{ *:[v4i32] } (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 247:{ *:[i32] })
14497 /* 46297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14498 /* 46300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14499 /* 46302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14500 /* 46306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
14501 /* 46310 */ GIR_RootToRootCopy, /*OpIdx*/2, // vC
14502 /* 46312 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(247),
14503 /* 46322 */ GIR_RootConstrainSelectedInstOperands,
14504 /* 46323 */ // GIR_Coverage, 4972,
14505 /* 46323 */ GIR_EraseRootFromParent_Done,
14506 /* 46324 */ // Label 562: @46324
14507 /* 46324 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(46409), // Rule ID 4973 //
14508 /* 46329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14509 /* 46332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14510 /* 46336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14511 /* 46340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
14512 /* 46344 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14513 /* 46348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14514 /* 46352 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14515 /* 46356 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14516 /* 46360 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14517 /* 46364 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14518 /* 46368 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14519 /* 46372 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14520 /* 46378 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14521 /* 46380 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14522 /* 46382 */ // (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })), v4i32:{ *:[v4i32] }:$vC) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 247:{ *:[i32] })
14523 /* 46382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14524 /* 46385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14525 /* 46387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14526 /* 46391 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
14527 /* 46395 */ GIR_RootToRootCopy, /*OpIdx*/2, // vC
14528 /* 46397 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(247),
14529 /* 46407 */ GIR_RootConstrainSelectedInstOperands,
14530 /* 46408 */ // GIR_Coverage, 4973,
14531 /* 46408 */ GIR_EraseRootFromParent_Done,
14532 /* 46409 */ // Label 563: @46409
14533 /* 46409 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(46496), // Rule ID 4974 //
14534 /* 46414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14535 /* 46417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14536 /* 46421 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14537 /* 46425 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
14538 /* 46429 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14539 /* 46433 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14540 /* 46437 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14541 /* 46441 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14542 /* 46445 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14543 /* 46449 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14544 /* 46453 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14545 /* 46457 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14546 /* 46463 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14547 /* 46465 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14548 /* 46467 */ // (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 247:{ *:[i32] })
14549 /* 46467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14550 /* 46470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14551 /* 46472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14552 /* 46476 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
14553 /* 46480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
14554 /* 46484 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(247),
14555 /* 46494 */ GIR_RootConstrainSelectedInstOperands,
14556 /* 46495 */ // GIR_Coverage, 4974,
14557 /* 46495 */ GIR_EraseRootFromParent_Done,
14558 /* 46496 */ // Label 564: @46496
14559 /* 46496 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(46581), // Rule ID 5293 //
14560 /* 46501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14561 /* 46504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14562 /* 46508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14563 /* 46512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14564 /* 46516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14565 /* 46520 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14566 /* 46524 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14567 /* 46528 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14568 /* 46532 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14569 /* 46536 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14570 /* 46540 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
14571 /* 46544 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14572 /* 46550 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14573 /* 46552 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14574 /* 46554 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 239:{ *:[i32] })
14575 /* 46554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14576 /* 46557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14577 /* 46559 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
14578 /* 46561 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14579 /* 46565 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
14580 /* 46569 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(239),
14581 /* 46579 */ GIR_RootConstrainSelectedInstOperands,
14582 /* 46580 */ // GIR_Coverage, 5293,
14583 /* 46580 */ GIR_EraseRootFromParent_Done,
14584 /* 46581 */ // Label 565: @46581
14585 /* 46581 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(46666), // Rule ID 5294 //
14586 /* 46586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14587 /* 46589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14588 /* 46593 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14589 /* 46597 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14590 /* 46601 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14591 /* 46605 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14592 /* 46609 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14593 /* 46613 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
14594 /* 46617 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14595 /* 46621 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14596 /* 46625 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
14597 /* 46629 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14598 /* 46635 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14599 /* 46637 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14600 /* 46639 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 143:{ *:[i32] })
14601 /* 46639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14602 /* 46642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14603 /* 46644 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
14604 /* 46646 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14605 /* 46650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
14606 /* 46654 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(143),
14607 /* 46664 */ GIR_RootConstrainSelectedInstOperands,
14608 /* 46665 */ // GIR_Coverage, 5294,
14609 /* 46665 */ GIR_EraseRootFromParent_Done,
14610 /* 46666 */ // Label 566: @46666
14611 /* 46666 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(46751), // Rule ID 5291 //
14612 /* 46671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14613 /* 46674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14614 /* 46678 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14615 /* 46682 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14616 /* 46686 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14617 /* 46690 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14618 /* 46694 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14619 /* 46698 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14620 /* 46702 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14621 /* 46706 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14622 /* 46710 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14623 /* 46714 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14624 /* 46720 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14625 /* 46722 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14626 /* 46724 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 159:{ *:[i32] })
14627 /* 46724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14628 /* 46727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14629 /* 46729 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
14630 /* 46731 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14631 /* 46735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
14632 /* 46739 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(159),
14633 /* 46749 */ GIR_RootConstrainSelectedInstOperands,
14634 /* 46750 */ // GIR_Coverage, 5291,
14635 /* 46750 */ GIR_EraseRootFromParent_Done,
14636 /* 46751 */ // Label 567: @46751
14637 /* 46751 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(46836), // Rule ID 5290 //
14638 /* 46756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14639 /* 46759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14640 /* 46763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14641 /* 46767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14642 /* 46771 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14643 /* 46775 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14644 /* 46779 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14645 /* 46783 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14646 /* 46787 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14647 /* 46791 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14648 /* 46795 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
14649 /* 46799 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14650 /* 46805 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14651 /* 46807 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14652 /* 46809 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 159:{ *:[i32] })
14653 /* 46809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14654 /* 46812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14655 /* 46814 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
14656 /* 46816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14657 /* 46820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
14658 /* 46824 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(159),
14659 /* 46834 */ GIR_RootConstrainSelectedInstOperands,
14660 /* 46835 */ // GIR_Coverage, 5290,
14661 /* 46835 */ GIR_EraseRootFromParent_Done,
14662 /* 46836 */ // Label 568: @46836
14663 /* 46836 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(46921), // Rule ID 5292 //
14664 /* 46841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14665 /* 46844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14666 /* 46848 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14667 /* 46852 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14668 /* 46856 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14669 /* 46860 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14670 /* 46864 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14671 /* 46868 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14672 /* 46872 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14673 /* 46876 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14674 /* 46880 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14675 /* 46884 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14676 /* 46890 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14677 /* 46892 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14678 /* 46894 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] })), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 159:{ *:[i32] })
14679 /* 46894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14680 /* 46897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14681 /* 46899 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
14682 /* 46901 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14683 /* 46905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
14684 /* 46909 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(159),
14685 /* 46919 */ GIR_RootConstrainSelectedInstOperands,
14686 /* 46920 */ // GIR_Coverage, 5292,
14687 /* 46920 */ GIR_EraseRootFromParent_Done,
14688 /* 46921 */ // Label 569: @46921
14689 /* 46921 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(47008), // Rule ID 3398 //
14690 /* 46926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14691 /* 46929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14692 /* 46933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14693 /* 46937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14694 /* 46941 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14695 /* 46945 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14696 /* 46949 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14697 /* 46953 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14698 /* 46959 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
14699 /* 46961 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
14700 /* 46965 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
14701 /* 46969 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
14702 /* 46973 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14703 /* 46977 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14704 /* 46979 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 241:{ *:[i32] })
14705 /* 46979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14706 /* 46982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14707 /* 46984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
14708 /* 46988 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
14709 /* 46992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
14710 /* 46996 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(241),
14711 /* 47006 */ GIR_RootConstrainSelectedInstOperands,
14712 /* 47007 */ // GIR_Coverage, 3398,
14713 /* 47007 */ GIR_EraseRootFromParent_Done,
14714 /* 47008 */ // Label 570: @47008
14715 /* 47008 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(47095), // Rule ID 3396 //
14716 /* 47013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14717 /* 47016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14718 /* 47020 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14719 /* 47024 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14720 /* 47028 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14721 /* 47032 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14722 /* 47036 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14723 /* 47040 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14724 /* 47046 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
14725 /* 47048 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
14726 /* 47052 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
14727 /* 47056 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
14728 /* 47060 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14729 /* 47064 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14730 /* 47066 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 247:{ *:[i32] })
14731 /* 47066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14732 /* 47069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14733 /* 47071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
14734 /* 47075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
14735 /* 47079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
14736 /* 47083 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(247),
14737 /* 47093 */ GIR_RootConstrainSelectedInstOperands,
14738 /* 47094 */ // GIR_Coverage, 3396,
14739 /* 47094 */ GIR_EraseRootFromParent_Done,
14740 /* 47095 */ // Label 571: @47095
14741 /* 47095 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(47182), // Rule ID 3397 //
14742 /* 47100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14743 /* 47103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14744 /* 47107 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14745 /* 47111 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14746 /* 47115 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14747 /* 47119 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14748 /* 47123 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14749 /* 47127 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14750 /* 47133 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
14751 /* 47135 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
14752 /* 47139 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14753 /* 47143 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
14754 /* 47147 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14755 /* 47151 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14756 /* 47153 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 246:{ *:[i32] })
14757 /* 47153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14758 /* 47156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14759 /* 47158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
14760 /* 47162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
14761 /* 47166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
14762 /* 47170 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(246),
14763 /* 47180 */ GIR_RootConstrainSelectedInstOperands,
14764 /* 47181 */ // GIR_Coverage, 3397,
14765 /* 47181 */ GIR_EraseRootFromParent_Done,
14766 /* 47182 */ // Label 572: @47182
14767 /* 47182 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(47269), // Rule ID 4977 //
14768 /* 47187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14769 /* 47190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14770 /* 47194 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14771 /* 47198 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14772 /* 47202 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14773 /* 47206 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14774 /* 47210 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14775 /* 47214 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14776 /* 47218 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14777 /* 47222 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14778 /* 47226 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14779 /* 47230 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14780 /* 47236 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14781 /* 47238 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14782 /* 47240 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 246:{ *:[i32] })
14783 /* 47240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14784 /* 47243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14785 /* 47245 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14786 /* 47249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
14787 /* 47253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
14788 /* 47257 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(246),
14789 /* 47267 */ GIR_RootConstrainSelectedInstOperands,
14790 /* 47268 */ // GIR_Coverage, 4977,
14791 /* 47268 */ GIR_EraseRootFromParent_Done,
14792 /* 47269 */ // Label 573: @47269
14793 /* 47269 */ GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(47354), // Rule ID 4975 //
14794 /* 47274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14795 /* 47277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14796 /* 47281 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14797 /* 47285 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
14798 /* 47289 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14799 /* 47293 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14800 /* 47297 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14801 /* 47301 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14802 /* 47305 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14803 /* 47309 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14804 /* 47313 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14805 /* 47317 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14806 /* 47323 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14807 /* 47325 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14808 /* 47327 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vB)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 247:{ *:[i32] })
14809 /* 47327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14810 /* 47330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14811 /* 47332 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14812 /* 47336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
14813 /* 47340 */ GIR_RootToRootCopy, /*OpIdx*/1, // vC
14814 /* 47342 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(247),
14815 /* 47352 */ GIR_RootConstrainSelectedInstOperands,
14816 /* 47353 */ // GIR_Coverage, 4975,
14817 /* 47353 */ GIR_EraseRootFromParent_Done,
14818 /* 47354 */ // Label 574: @47354
14819 /* 47354 */ GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(47439), // Rule ID 4976 //
14820 /* 47359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14821 /* 47362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14822 /* 47366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14823 /* 47370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
14824 /* 47374 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14825 /* 47378 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14826 /* 47382 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14827 /* 47386 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14828 /* 47390 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14829 /* 47394 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14830 /* 47398 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14831 /* 47402 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14832 /* 47408 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14833 /* 47410 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14834 /* 47412 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 247:{ *:[i32] })
14835 /* 47412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14836 /* 47415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14837 /* 47417 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
14838 /* 47421 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
14839 /* 47425 */ GIR_RootToRootCopy, /*OpIdx*/1, // vC
14840 /* 47427 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(247),
14841 /* 47437 */ GIR_RootConstrainSelectedInstOperands,
14842 /* 47438 */ // GIR_Coverage, 4976,
14843 /* 47438 */ GIR_EraseRootFromParent_Done,
14844 /* 47439 */ // Label 575: @47439
14845 /* 47439 */ GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(47524), // Rule ID 3411 //
14846 /* 47444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14847 /* 47447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14848 /* 47451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14849 /* 47455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14850 /* 47459 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14851 /* 47463 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14852 /* 47467 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14853 /* 47471 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14854 /* 47475 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14855 /* 47479 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14856 /* 47483 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
14857 /* 47487 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14858 /* 47493 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14859 /* 47495 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14860 /* 47497 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 239:{ *:[i32] })
14861 /* 47497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14862 /* 47500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14863 /* 47502 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
14864 /* 47504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14865 /* 47508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
14866 /* 47512 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(239),
14867 /* 47522 */ GIR_RootConstrainSelectedInstOperands,
14868 /* 47523 */ // GIR_Coverage, 3411,
14869 /* 47523 */ GIR_EraseRootFromParent_Done,
14870 /* 47524 */ // Label 576: @47524
14871 /* 47524 */ GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(47609), // Rule ID 3412 //
14872 /* 47529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14873 /* 47532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14874 /* 47536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14875 /* 47540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14876 /* 47544 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14877 /* 47548 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14878 /* 47552 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14879 /* 47556 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
14880 /* 47560 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14881 /* 47564 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14882 /* 47568 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
14883 /* 47572 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14884 /* 47578 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14885 /* 47580 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14886 /* 47582 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 143:{ *:[i32] })
14887 /* 47582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14888 /* 47585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14889 /* 47587 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
14890 /* 47589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14891 /* 47593 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
14892 /* 47597 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(143),
14893 /* 47607 */ GIR_RootConstrainSelectedInstOperands,
14894 /* 47608 */ // GIR_Coverage, 3412,
14895 /* 47608 */ GIR_EraseRootFromParent_Done,
14896 /* 47609 */ // Label 577: @47609
14897 /* 47609 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(47694), // Rule ID 5288 //
14898 /* 47614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14899 /* 47617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14900 /* 47621 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14901 /* 47625 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14902 /* 47629 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14903 /* 47633 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14904 /* 47637 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14905 /* 47641 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14906 /* 47645 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14907 /* 47649 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14908 /* 47653 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14909 /* 47657 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14910 /* 47663 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14911 /* 47665 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14912 /* 47667 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 159:{ *:[i32] })
14913 /* 47667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14914 /* 47670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14915 /* 47672 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
14916 /* 47674 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14917 /* 47678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
14918 /* 47682 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(159),
14919 /* 47692 */ GIR_RootConstrainSelectedInstOperands,
14920 /* 47693 */ // GIR_Coverage, 5288,
14921 /* 47693 */ GIR_EraseRootFromParent_Done,
14922 /* 47694 */ // Label 578: @47694
14923 /* 47694 */ GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(47779), // Rule ID 3410 //
14924 /* 47699 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14925 /* 47702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14926 /* 47706 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14927 /* 47710 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14928 /* 47714 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14929 /* 47718 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14930 /* 47722 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14931 /* 47726 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14932 /* 47730 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14933 /* 47734 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14934 /* 47738 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
14935 /* 47742 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14936 /* 47748 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14937 /* 47750 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14938 /* 47752 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 159:{ *:[i32] })
14939 /* 47752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14940 /* 47755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14941 /* 47757 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
14942 /* 47759 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14943 /* 47763 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
14944 /* 47767 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(159),
14945 /* 47777 */ GIR_RootConstrainSelectedInstOperands,
14946 /* 47778 */ // GIR_Coverage, 3410,
14947 /* 47778 */ GIR_EraseRootFromParent_Done,
14948 /* 47779 */ // Label 579: @47779
14949 /* 47779 */ GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(47864), // Rule ID 5289 //
14950 /* 47784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
14951 /* 47787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14952 /* 47791 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14953 /* 47795 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14954 /* 47799 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14955 /* 47803 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14956 /* 47807 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14957 /* 47811 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14958 /* 47815 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14959 /* 47819 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14960 /* 47823 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14961 /* 47827 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14962 /* 47833 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14963 /* 47835 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
14964 /* 47837 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vC, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, immAllOnesV:{ *:[v4i32] }))) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 159:{ *:[i32] })
14965 /* 47837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
14966 /* 47840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14967 /* 47842 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
14968 /* 47844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
14969 /* 47848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vC
14970 /* 47852 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(159),
14971 /* 47862 */ GIR_RootConstrainSelectedInstOperands,
14972 /* 47863 */ // GIR_Coverage, 5289,
14973 /* 47863 */ GIR_EraseRootFromParent_Done,
14974 /* 47864 */ // Label 580: @47864
14975 /* 47864 */ GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(47919), // Rule ID 4942 //
14976 /* 47869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
14977 /* 47872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14978 /* 47876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14979 /* 47880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14980 /* 47884 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14981 /* 47888 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14982 /* 47892 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14983 /* 47896 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14984 /* 47902 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
14985 /* 47904 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14986 /* 47906 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XA) => (XXLORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
14987 /* 47906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLORC),
14988 /* 47909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
14989 /* 47911 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
14990 /* 47913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB
14991 /* 47917 */ GIR_RootConstrainSelectedInstOperands,
14992 /* 47918 */ // GIR_Coverage, 4942,
14993 /* 47918 */ GIR_EraseRootFromParent_Done,
14994 /* 47919 */ // Label 581: @47919
14995 /* 47919 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(47974), // Rule ID 946 //
14996 /* 47924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
14997 /* 47927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
14998 /* 47931 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14999 /* 47935 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15000 /* 47939 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15001 /* 47943 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15002 /* 47947 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15003 /* 47951 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15004 /* 47957 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15005 /* 47959 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15006 /* 47961 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] })) => (XXLORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
15007 /* 47961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLORC),
15008 /* 47964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
15009 /* 47966 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
15010 /* 47968 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB
15011 /* 47972 */ GIR_RootConstrainSelectedInstOperands,
15012 /* 47973 */ // GIR_Coverage, 946,
15013 /* 47973 */ GIR_EraseRootFromParent_Done,
15014 /* 47974 */ // Label 582: @47974
15015 /* 47974 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(48024), // Rule ID 5287 //
15016 /* 47979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
15017 /* 47982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
15018 /* 47986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15019 /* 47990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15020 /* 47994 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15021 /* 47998 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15022 /* 48002 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15023 /* 48004 */ // (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 31:{ *:[i32] })
15024 /* 48004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
15025 /* 48007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
15026 /* 48009 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
15027 /* 48011 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
15028 /* 48015 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
15029 /* 48019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
15030 /* 48022 */ GIR_RootConstrainSelectedInstOperands,
15031 /* 48023 */ // GIR_Coverage, 5287,
15032 /* 48023 */ GIR_EraseRootFromParent_Done,
15033 /* 48024 */ // Label 583: @48024
15034 /* 48024 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(48074), // Rule ID 5286 //
15035 /* 48029 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
15036 /* 48032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
15037 /* 48036 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15038 /* 48040 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
15039 /* 48044 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15040 /* 48048 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15041 /* 48052 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15042 /* 48054 */ // (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 127:{ *:[i32] })
15043 /* 48054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
15044 /* 48057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
15045 /* 48059 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
15046 /* 48063 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
15047 /* 48067 */ GIR_RootToRootCopy, /*OpIdx*/2, // vC
15048 /* 48069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/127,
15049 /* 48072 */ GIR_RootConstrainSelectedInstOperands,
15050 /* 48073 */ // GIR_Coverage, 5286,
15051 /* 48073 */ GIR_EraseRootFromParent_Done,
15052 /* 48074 */ // Label 584: @48074
15053 /* 48074 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(48124), // Rule ID 5295 //
15054 /* 48079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
15055 /* 48082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
15056 /* 48086 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15057 /* 48090 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15058 /* 48094 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15059 /* 48098 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15060 /* 48102 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15061 /* 48104 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 111:{ *:[i32] })
15062 /* 48104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
15063 /* 48107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
15064 /* 48109 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
15065 /* 48111 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
15066 /* 48115 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
15067 /* 48119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/111,
15068 /* 48122 */ GIR_RootConstrainSelectedInstOperands,
15069 /* 48123 */ // GIR_Coverage, 5295,
15070 /* 48123 */ GIR_EraseRootFromParent_Done,
15071 /* 48124 */ // Label 585: @48124
15072 /* 48124 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(48174), // Rule ID 3409 //
15073 /* 48129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
15074 /* 48132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
15075 /* 48136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15076 /* 48140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15077 /* 48144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15078 /* 48148 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15079 /* 48152 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15080 /* 48154 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 31:{ *:[i32] })
15081 /* 48154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
15082 /* 48157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
15083 /* 48159 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
15084 /* 48161 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
15085 /* 48165 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
15086 /* 48169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
15087 /* 48172 */ GIR_RootConstrainSelectedInstOperands,
15088 /* 48173 */ // GIR_Coverage, 3409,
15089 /* 48173 */ GIR_EraseRootFromParent_Done,
15090 /* 48174 */ // Label 586: @48174
15091 /* 48174 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(48224), // Rule ID 3408 //
15092 /* 48179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
15093 /* 48182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
15094 /* 48186 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15095 /* 48190 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
15096 /* 48194 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15097 /* 48198 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15098 /* 48202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15099 /* 48204 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 127:{ *:[i32] })
15100 /* 48204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
15101 /* 48207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
15102 /* 48209 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
15103 /* 48211 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
15104 /* 48215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
15105 /* 48219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/127,
15106 /* 48222 */ GIR_RootConstrainSelectedInstOperands,
15107 /* 48223 */ // GIR_Coverage, 3408,
15108 /* 48223 */ GIR_EraseRootFromParent_Done,
15109 /* 48224 */ // Label 587: @48224
15110 /* 48224 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(48274), // Rule ID 3413 //
15111 /* 48229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
15112 /* 48232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
15113 /* 48236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15114 /* 48240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15115 /* 48244 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15116 /* 48248 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15117 /* 48252 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15118 /* 48254 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 111:{ *:[i32] })
15119 /* 48254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
15120 /* 48257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
15121 /* 48259 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
15122 /* 48261 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
15123 /* 48265 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
15124 /* 48269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/111,
15125 /* 48272 */ GIR_RootConstrainSelectedInstOperands,
15126 /* 48273 */ // GIR_Coverage, 3413,
15127 /* 48273 */ GIR_EraseRootFromParent_Done,
15128 /* 48274 */ // Label 588: @48274
15129 /* 48274 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(48293), // Rule ID 935 //
15130 /* 48279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
15131 /* 48282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
15132 /* 48286 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
15133 /* 48286 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLOR),
15134 /* 48291 */ GIR_RootConstrainSelectedInstOperands,
15135 /* 48292 */ // GIR_Coverage, 935,
15136 /* 48292 */ GIR_Done,
15137 /* 48293 */ // Label 589: @48293
15138 /* 48293 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(48348), // Rule ID 4930 //
15139 /* 48298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
15140 /* 48301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
15141 /* 48305 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15142 /* 48309 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15143 /* 48313 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15144 /* 48317 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15145 /* 48321 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15146 /* 48325 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15147 /* 48331 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15148 /* 48333 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15149 /* 48335 */ // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VA) => (VORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
15150 /* 48335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VORC),
15151 /* 48338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
15152 /* 48340 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
15153 /* 48342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB
15154 /* 48346 */ GIR_RootConstrainSelectedInstOperands,
15155 /* 48347 */ // GIR_Coverage, 4930,
15156 /* 48347 */ GIR_EraseRootFromParent_Done,
15157 /* 48348 */ // Label 590: @48348
15158 /* 48348 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(48403), // Rule ID 489 //
15159 /* 48353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
15160 /* 48356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
15161 /* 48360 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15162 /* 48364 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15163 /* 48368 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15164 /* 48372 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15165 /* 48376 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15166 /* 48380 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15167 /* 48386 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15168 /* 48388 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15169 /* 48390 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] })) => (VORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
15170 /* 48390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VORC),
15171 /* 48393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
15172 /* 48395 */ GIR_RootToRootCopy, /*OpIdx*/1, // VA
15173 /* 48397 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB
15174 /* 48401 */ GIR_RootConstrainSelectedInstOperands,
15175 /* 48402 */ // GIR_Coverage, 489,
15176 /* 48402 */ GIR_EraseRootFromParent_Done,
15177 /* 48403 */ // Label 591: @48403
15178 /* 48403 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(48422), // Rule ID 386 //
15179 /* 48408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
15180 /* 48411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
15181 /* 48415 */ // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
15182 /* 48415 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VOR),
15183 /* 48420 */ GIR_RootConstrainSelectedInstOperands,
15184 /* 48421 */ // GIR_Coverage, 386,
15185 /* 48421 */ GIR_Done,
15186 /* 48422 */ // Label 592: @48422
15187 /* 48422 */ GIM_Reject,
15188 /* 48423 */ // Label 264: @48423
15189 /* 48423 */ GIM_Reject,
15190 /* 48424 */ // Label 251: @48424
15191 /* 48424 */ GIM_Reject,
15192 /* 48425 */ // Label 9: @48425
15193 /* 48425 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 597*/ GIMT_Encode4(57531),
15194 /* 48436 */ /*GILLT_s1*//*Label 593*/ GIMT_Encode4(48460),
15195 /* 48440 */ /*GILLT_s32*//*Label 594*/ GIMT_Encode4(53897),
15196 /* 48444 */ /*GILLT_s64*//*Label 595*/ GIMT_Encode4(54152), GIMT_Encode4(0), GIMT_Encode4(0),
15197 /* 48456 */ /*GILLT_v4s32*//*Label 596*/ GIMT_Encode4(54407),
15198 /* 48460 */ // Label 593: @48460
15199 /* 48460 */ GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(53896),
15200 /* 48465 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
15201 /* 48468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
15202 /* 48471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
15203 /* 48475 */ GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(48566), // Rule ID 3035 //
15204 /* 48480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
15205 /* 48483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15206 /* 48487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15207 /* 48491 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15208 /* 48495 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15209 /* 48499 */ // MIs[1] Operand 1
15210 /* 48499 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
15211 /* 48504 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15212 /* 48508 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15213 /* 48512 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
15214 /* 48516 */ // MIs[2] Operand 1
15215 /* 48516 */ // No operand predicates
15216 /* 48516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15217 /* 48520 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15218 /* 48522 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] })
15219 /* 48522 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15220 /* 48525 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
15221 /* 48529 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15222 /* 48534 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15223 /* 48538 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15224 /* 48541 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15225 /* 48543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15226 /* 48546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15227 /* 48548 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15228 /* 48555 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15229 /* 48560 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15230 /* 48565 */ // GIR_Coverage, 3035,
15231 /* 48565 */ GIR_EraseRootFromParent_Done,
15232 /* 48566 */ // Label 599: @48566
15233 /* 48566 */ GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(48657), // Rule ID 3051 //
15234 /* 48571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
15235 /* 48574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15236 /* 48578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15237 /* 48582 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15238 /* 48586 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15239 /* 48590 */ // MIs[1] Operand 1
15240 /* 48590 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
15241 /* 48595 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15242 /* 48599 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15243 /* 48603 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
15244 /* 48607 */ // MIs[2] Operand 1
15245 /* 48607 */ // No operand predicates
15246 /* 48607 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15247 /* 48611 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15248 /* 48613 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] })
15249 /* 48613 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15250 /* 48616 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
15251 /* 48620 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15252 /* 48625 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15253 /* 48629 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15254 /* 48632 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15255 /* 48634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15256 /* 48637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15257 /* 48639 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
15258 /* 48646 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15259 /* 48651 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15260 /* 48656 */ // GIR_Coverage, 3051,
15261 /* 48656 */ GIR_EraseRootFromParent_Done,
15262 /* 48657 */ // Label 600: @48657
15263 /* 48657 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(48748), // Rule ID 3059 //
15264 /* 48662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
15265 /* 48665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15266 /* 48669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15267 /* 48673 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15268 /* 48677 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15269 /* 48681 */ // MIs[1] Operand 1
15270 /* 48681 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
15271 /* 48686 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15272 /* 48690 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15273 /* 48694 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
15274 /* 48698 */ // MIs[2] Operand 1
15275 /* 48698 */ // No operand predicates
15276 /* 48698 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15277 /* 48702 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15278 /* 48704 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] })
15279 /* 48704 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15280 /* 48707 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
15281 /* 48711 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15282 /* 48716 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15283 /* 48720 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15284 /* 48723 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15285 /* 48725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15286 /* 48728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15287 /* 48730 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
15288 /* 48737 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15289 /* 48742 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15290 /* 48747 */ // GIR_Coverage, 3059,
15291 /* 48747 */ GIR_EraseRootFromParent_Done,
15292 /* 48748 */ // Label 601: @48748
15293 /* 48748 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(48839), // Rule ID 3131 //
15294 /* 48753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
15295 /* 48756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15296 /* 48760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15297 /* 48764 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15298 /* 48768 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15299 /* 48772 */ // MIs[1] Operand 1
15300 /* 48772 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
15301 /* 48777 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15302 /* 48781 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15303 /* 48785 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
15304 /* 48789 */ // MIs[2] Operand 1
15305 /* 48789 */ // No operand predicates
15306 /* 48789 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15307 /* 48793 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15308 /* 48795 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] })
15309 /* 48795 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15310 /* 48798 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
15311 /* 48802 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15312 /* 48807 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15313 /* 48811 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15314 /* 48814 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15315 /* 48816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15316 /* 48819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15317 /* 48821 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15318 /* 48828 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15319 /* 48833 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15320 /* 48838 */ // GIR_Coverage, 3131,
15321 /* 48838 */ GIR_EraseRootFromParent_Done,
15322 /* 48839 */ // Label 602: @48839
15323 /* 48839 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(48930), // Rule ID 3147 //
15324 /* 48844 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
15325 /* 48847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15326 /* 48851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15327 /* 48855 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15328 /* 48859 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15329 /* 48863 */ // MIs[1] Operand 1
15330 /* 48863 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
15331 /* 48868 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15332 /* 48872 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15333 /* 48876 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
15334 /* 48880 */ // MIs[2] Operand 1
15335 /* 48880 */ // No operand predicates
15336 /* 48880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15337 /* 48884 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15338 /* 48886 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] })
15339 /* 48886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15340 /* 48889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
15341 /* 48893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15342 /* 48898 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15343 /* 48902 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15344 /* 48905 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15345 /* 48907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15346 /* 48910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15347 /* 48912 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
15348 /* 48919 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15349 /* 48924 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15350 /* 48929 */ // GIR_Coverage, 3147,
15351 /* 48929 */ GIR_EraseRootFromParent_Done,
15352 /* 48930 */ // Label 603: @48930
15353 /* 48930 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(49021), // Rule ID 3155 //
15354 /* 48935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
15355 /* 48938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15356 /* 48942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15357 /* 48946 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15358 /* 48950 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15359 /* 48954 */ // MIs[1] Operand 1
15360 /* 48954 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
15361 /* 48959 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15362 /* 48963 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15363 /* 48967 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
15364 /* 48971 */ // MIs[2] Operand 1
15365 /* 48971 */ // No operand predicates
15366 /* 48971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15367 /* 48975 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15368 /* 48977 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] })
15369 /* 48977 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15370 /* 48980 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
15371 /* 48984 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15372 /* 48989 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15373 /* 48993 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15374 /* 48996 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15375 /* 48998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15376 /* 49001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15377 /* 49003 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
15378 /* 49010 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15379 /* 49015 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15380 /* 49020 */ // GIR_Coverage, 3155,
15381 /* 49020 */ GIR_EraseRootFromParent_Done,
15382 /* 49021 */ // Label 604: @49021
15383 /* 49021 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(49112), // Rule ID 3818 //
15384 /* 49026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
15385 /* 49029 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15386 /* 49033 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15387 /* 49037 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15388 /* 49041 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15389 /* 49045 */ // MIs[1] Operand 1
15390 /* 49045 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
15391 /* 49050 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15392 /* 49054 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15393 /* 49058 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
15394 /* 49062 */ // MIs[2] Operand 1
15395 /* 49062 */ // No operand predicates
15396 /* 49062 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15397 /* 49066 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15398 /* 49068 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] })
15399 /* 49068 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15400 /* 49071 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
15401 /* 49075 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15402 /* 49080 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15403 /* 49084 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15404 /* 49087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15405 /* 49089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15406 /* 49092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15407 /* 49094 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15408 /* 49101 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15409 /* 49106 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15410 /* 49111 */ // GIR_Coverage, 3818,
15411 /* 49111 */ GIR_EraseRootFromParent_Done,
15412 /* 49112 */ // Label 605: @49112
15413 /* 49112 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(49203), // Rule ID 3834 //
15414 /* 49117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
15415 /* 49120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15416 /* 49124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15417 /* 49128 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15418 /* 49132 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15419 /* 49136 */ // MIs[1] Operand 1
15420 /* 49136 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
15421 /* 49141 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15422 /* 49145 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15423 /* 49149 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
15424 /* 49153 */ // MIs[2] Operand 1
15425 /* 49153 */ // No operand predicates
15426 /* 49153 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15427 /* 49157 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15428 /* 49159 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] })
15429 /* 49159 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15430 /* 49162 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
15431 /* 49166 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15432 /* 49171 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15433 /* 49175 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15434 /* 49178 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15435 /* 49180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15436 /* 49183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15437 /* 49185 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
15438 /* 49192 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15439 /* 49197 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15440 /* 49202 */ // GIR_Coverage, 3834,
15441 /* 49202 */ GIR_EraseRootFromParent_Done,
15442 /* 49203 */ // Label 606: @49203
15443 /* 49203 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(49294), // Rule ID 3842 //
15444 /* 49208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
15445 /* 49211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15446 /* 49215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15447 /* 49219 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15448 /* 49223 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15449 /* 49227 */ // MIs[1] Operand 1
15450 /* 49227 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
15451 /* 49232 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15452 /* 49236 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15453 /* 49240 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
15454 /* 49244 */ // MIs[2] Operand 1
15455 /* 49244 */ // No operand predicates
15456 /* 49244 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15457 /* 49248 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15458 /* 49250 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] })
15459 /* 49250 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15460 /* 49253 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
15461 /* 49257 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15462 /* 49262 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15463 /* 49266 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15464 /* 49269 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15465 /* 49271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15466 /* 49274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15467 /* 49276 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
15468 /* 49283 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15469 /* 49288 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15470 /* 49293 */ // GIR_Coverage, 3842,
15471 /* 49293 */ GIR_EraseRootFromParent_Done,
15472 /* 49294 */ // Label 607: @49294
15473 /* 49294 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(49385), // Rule ID 3914 //
15474 /* 49299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
15475 /* 49302 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15476 /* 49306 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15477 /* 49310 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15478 /* 49314 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15479 /* 49318 */ // MIs[1] Operand 1
15480 /* 49318 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
15481 /* 49323 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15482 /* 49327 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15483 /* 49331 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
15484 /* 49335 */ // MIs[2] Operand 1
15485 /* 49335 */ // No operand predicates
15486 /* 49335 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15487 /* 49339 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15488 /* 49341 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] })
15489 /* 49341 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15490 /* 49344 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
15491 /* 49348 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15492 /* 49353 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15493 /* 49357 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15494 /* 49360 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15495 /* 49362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15496 /* 49365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15497 /* 49367 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15498 /* 49374 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15499 /* 49379 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15500 /* 49384 */ // GIR_Coverage, 3914,
15501 /* 49384 */ GIR_EraseRootFromParent_Done,
15502 /* 49385 */ // Label 608: @49385
15503 /* 49385 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(49476), // Rule ID 3930 //
15504 /* 49390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
15505 /* 49393 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15506 /* 49397 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15507 /* 49401 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15508 /* 49405 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15509 /* 49409 */ // MIs[1] Operand 1
15510 /* 49409 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
15511 /* 49414 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15512 /* 49418 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15513 /* 49422 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
15514 /* 49426 */ // MIs[2] Operand 1
15515 /* 49426 */ // No operand predicates
15516 /* 49426 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15517 /* 49430 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15518 /* 49432 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] })
15519 /* 49432 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15520 /* 49435 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
15521 /* 49439 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15522 /* 49444 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15523 /* 49448 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15524 /* 49451 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15525 /* 49453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15526 /* 49456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15527 /* 49458 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
15528 /* 49465 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15529 /* 49470 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15530 /* 49475 */ // GIR_Coverage, 3930,
15531 /* 49475 */ GIR_EraseRootFromParent_Done,
15532 /* 49476 */ // Label 609: @49476
15533 /* 49476 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(49567), // Rule ID 3938 //
15534 /* 49481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
15535 /* 49484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15536 /* 49488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15537 /* 49492 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15538 /* 49496 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15539 /* 49500 */ // MIs[1] Operand 1
15540 /* 49500 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
15541 /* 49505 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
15542 /* 49509 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15543 /* 49513 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
15544 /* 49517 */ // MIs[2] Operand 1
15545 /* 49517 */ // No operand predicates
15546 /* 49517 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15547 /* 49521 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15548 /* 49523 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] })
15549 /* 49523 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15550 /* 49526 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
15551 /* 49530 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15552 /* 49535 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15553 /* 49539 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
15554 /* 49542 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15555 /* 49544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15556 /* 49547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15557 /* 49549 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
15558 /* 49556 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15559 /* 49561 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15560 /* 49566 */ // GIR_Coverage, 3938,
15561 /* 49566 */ GIR_EraseRootFromParent_Done,
15562 /* 49567 */ // Label 610: @49567
15563 /* 49567 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(49647), // Rule ID 3179 //
15564 /* 49572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15565 /* 49575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15566 /* 49579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15567 /* 49583 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15568 /* 49587 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15569 /* 49591 */ // MIs[1] Operand 1
15570 /* 49591 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
15571 /* 49596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15572 /* 49600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15573 /* 49602 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] })
15574 /* 49602 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15575 /* 49605 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
15576 /* 49609 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15577 /* 49614 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15578 /* 49618 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15579 /* 49622 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15580 /* 49624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15581 /* 49627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15582 /* 49629 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15583 /* 49636 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15584 /* 49641 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15585 /* 49646 */ // GIR_Coverage, 3179,
15586 /* 49646 */ GIR_EraseRootFromParent_Done,
15587 /* 49647 */ // Label 611: @49647
15588 /* 49647 */ GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(49727), // Rule ID 3195 //
15589 /* 49652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15590 /* 49655 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15591 /* 49659 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15592 /* 49663 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15593 /* 49667 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15594 /* 49671 */ // MIs[1] Operand 1
15595 /* 49671 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
15596 /* 49676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15597 /* 49680 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15598 /* 49682 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
15599 /* 49682 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15600 /* 49685 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
15601 /* 49689 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15602 /* 49694 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15603 /* 49698 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15604 /* 49702 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15605 /* 49704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15606 /* 49707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15607 /* 49709 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
15608 /* 49716 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15609 /* 49721 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15610 /* 49726 */ // GIR_Coverage, 3195,
15611 /* 49726 */ GIR_EraseRootFromParent_Done,
15612 /* 49727 */ // Label 612: @49727
15613 /* 49727 */ GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(49807), // Rule ID 3211 //
15614 /* 49732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15615 /* 49735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15616 /* 49739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15617 /* 49743 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15618 /* 49747 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15619 /* 49751 */ // MIs[1] Operand 1
15620 /* 49751 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
15621 /* 49756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15622 /* 49760 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15623 /* 49762 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] })
15624 /* 49762 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15625 /* 49765 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
15626 /* 49769 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15627 /* 49774 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15628 /* 49778 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15629 /* 49782 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15630 /* 49784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15631 /* 49787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15632 /* 49789 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
15633 /* 49796 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15634 /* 49801 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15635 /* 49806 */ // GIR_Coverage, 3211,
15636 /* 49806 */ GIR_EraseRootFromParent_Done,
15637 /* 49807 */ // Label 613: @49807
15638 /* 49807 */ GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(49887), // Rule ID 3227 //
15639 /* 49812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15640 /* 49815 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15641 /* 49819 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15642 /* 49823 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15643 /* 49827 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15644 /* 49831 */ // MIs[1] Operand 1
15645 /* 49831 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
15646 /* 49836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15647 /* 49840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15648 /* 49842 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] })
15649 /* 49842 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15650 /* 49845 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
15651 /* 49849 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15652 /* 49854 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15653 /* 49858 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15654 /* 49862 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15655 /* 49864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15656 /* 49867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15657 /* 49869 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
15658 /* 49876 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15659 /* 49881 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15660 /* 49886 */ // GIR_Coverage, 3227,
15661 /* 49886 */ GIR_EraseRootFromParent_Done,
15662 /* 49887 */ // Label 614: @49887
15663 /* 49887 */ GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(49967), // Rule ID 3235 //
15664 /* 49892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15665 /* 49895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15666 /* 49899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15667 /* 49903 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15668 /* 49907 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15669 /* 49911 */ // MIs[1] Operand 1
15670 /* 49911 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
15671 /* 49916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15672 /* 49920 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15673 /* 49922 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] })
15674 /* 49922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15675 /* 49925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
15676 /* 49929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15677 /* 49934 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15678 /* 49938 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15679 /* 49942 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15680 /* 49944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15681 /* 49947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15682 /* 49949 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15683 /* 49956 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15684 /* 49961 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15685 /* 49966 */ // GIR_Coverage, 3235,
15686 /* 49966 */ GIR_EraseRootFromParent_Done,
15687 /* 49967 */ // Label 615: @49967
15688 /* 49967 */ GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(50047), // Rule ID 3251 //
15689 /* 49972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15690 /* 49975 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15691 /* 49979 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15692 /* 49983 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15693 /* 49987 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15694 /* 49991 */ // MIs[1] Operand 1
15695 /* 49991 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
15696 /* 49996 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15697 /* 50000 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15698 /* 50002 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
15699 /* 50002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15700 /* 50005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
15701 /* 50009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15702 /* 50014 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15703 /* 50018 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15704 /* 50022 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15705 /* 50024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15706 /* 50027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15707 /* 50029 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
15708 /* 50036 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15709 /* 50041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15710 /* 50046 */ // GIR_Coverage, 3251,
15711 /* 50046 */ GIR_EraseRootFromParent_Done,
15712 /* 50047 */ // Label 616: @50047
15713 /* 50047 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(50127), // Rule ID 3267 //
15714 /* 50052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15715 /* 50055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15716 /* 50059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15717 /* 50063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15718 /* 50067 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15719 /* 50071 */ // MIs[1] Operand 1
15720 /* 50071 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
15721 /* 50076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15722 /* 50080 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15723 /* 50082 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] })
15724 /* 50082 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15725 /* 50085 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
15726 /* 50089 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15727 /* 50094 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15728 /* 50098 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15729 /* 50102 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15730 /* 50104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15731 /* 50107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15732 /* 50109 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
15733 /* 50116 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15734 /* 50121 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15735 /* 50126 */ // GIR_Coverage, 3267,
15736 /* 50126 */ GIR_EraseRootFromParent_Done,
15737 /* 50127 */ // Label 617: @50127
15738 /* 50127 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(50207), // Rule ID 3283 //
15739 /* 50132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15740 /* 50135 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15741 /* 50139 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15742 /* 50143 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15743 /* 50147 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15744 /* 50151 */ // MIs[1] Operand 1
15745 /* 50151 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
15746 /* 50156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15747 /* 50160 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15748 /* 50162 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] })
15749 /* 50162 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15750 /* 50165 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
15751 /* 50169 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15752 /* 50174 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15753 /* 50178 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15754 /* 50182 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15755 /* 50184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15756 /* 50187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15757 /* 50189 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
15758 /* 50196 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15759 /* 50201 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15760 /* 50206 */ // GIR_Coverage, 3283,
15761 /* 50206 */ GIR_EraseRootFromParent_Done,
15762 /* 50207 */ // Label 618: @50207
15763 /* 50207 */ GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(50287), // Rule ID 3291 //
15764 /* 50212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15765 /* 50215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15766 /* 50219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15767 /* 50223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
15768 /* 50227 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
15769 /* 50231 */ // MIs[1] Operand 1
15770 /* 50231 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
15771 /* 50236 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15772 /* 50240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15773 /* 50242 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] })
15774 /* 50242 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15775 /* 50245 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
15776 /* 50249 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15777 /* 50254 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15778 /* 50258 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15779 /* 50262 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15780 /* 50264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15781 /* 50267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15782 /* 50269 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15783 /* 50276 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15784 /* 50281 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15785 /* 50286 */ // GIR_Coverage, 3291,
15786 /* 50286 */ GIR_EraseRootFromParent_Done,
15787 /* 50287 */ // Label 619: @50287
15788 /* 50287 */ GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(50367), // Rule ID 3307 //
15789 /* 50292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15790 /* 50295 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15791 /* 50299 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15792 /* 50303 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
15793 /* 50307 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
15794 /* 50311 */ // MIs[1] Operand 1
15795 /* 50311 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
15796 /* 50316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15797 /* 50320 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15798 /* 50322 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] })
15799 /* 50322 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15800 /* 50325 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
15801 /* 50329 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15802 /* 50334 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15803 /* 50338 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15804 /* 50342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15805 /* 50344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15806 /* 50347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15807 /* 50349 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
15808 /* 50356 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15809 /* 50361 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15810 /* 50366 */ // GIR_Coverage, 3307,
15811 /* 50366 */ GIR_EraseRootFromParent_Done,
15812 /* 50367 */ // Label 620: @50367
15813 /* 50367 */ GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(50447), // Rule ID 3323 //
15814 /* 50372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15815 /* 50375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15816 /* 50379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15817 /* 50383 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
15818 /* 50387 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
15819 /* 50391 */ // MIs[1] Operand 1
15820 /* 50391 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
15821 /* 50396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15822 /* 50400 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15823 /* 50402 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] })
15824 /* 50402 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15825 /* 50405 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
15826 /* 50409 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15827 /* 50414 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15828 /* 50418 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15829 /* 50422 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15830 /* 50424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15831 /* 50427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15832 /* 50429 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
15833 /* 50436 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15834 /* 50441 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15835 /* 50446 */ // GIR_Coverage, 3323,
15836 /* 50446 */ GIR_EraseRootFromParent_Done,
15837 /* 50447 */ // Label 621: @50447
15838 /* 50447 */ GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(50527), // Rule ID 3339 //
15839 /* 50452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
15840 /* 50455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15841 /* 50459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15842 /* 50463 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
15843 /* 50467 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
15844 /* 50471 */ // MIs[1] Operand 1
15845 /* 50471 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
15846 /* 50476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15847 /* 50480 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15848 /* 50482 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] })
15849 /* 50482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15850 /* 50485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
15851 /* 50489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15852 /* 50494 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15853 /* 50498 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15854 /* 50502 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15855 /* 50504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15856 /* 50507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15857 /* 50509 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
15858 /* 50516 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15859 /* 50521 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15860 /* 50526 */ // GIR_Coverage, 3339,
15861 /* 50526 */ GIR_EraseRootFromParent_Done,
15862 /* 50527 */ // Label 622: @50527
15863 /* 50527 */ GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(50607), // Rule ID 4018 //
15864 /* 50532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
15865 /* 50535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15866 /* 50539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15867 /* 50543 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15868 /* 50547 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15869 /* 50551 */ // MIs[1] Operand 1
15870 /* 50551 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
15871 /* 50556 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15872 /* 50560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15873 /* 50562 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] })
15874 /* 50562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15875 /* 50565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
15876 /* 50569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15877 /* 50574 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15878 /* 50578 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15879 /* 50582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15880 /* 50584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15881 /* 50587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15882 /* 50589 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15883 /* 50596 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15884 /* 50601 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15885 /* 50606 */ // GIR_Coverage, 4018,
15886 /* 50606 */ GIR_EraseRootFromParent_Done,
15887 /* 50607 */ // Label 623: @50607
15888 /* 50607 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(50687), // Rule ID 4050 //
15889 /* 50612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
15890 /* 50615 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15891 /* 50619 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15892 /* 50623 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15893 /* 50627 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15894 /* 50631 */ // MIs[1] Operand 1
15895 /* 50631 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
15896 /* 50636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15897 /* 50640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15898 /* 50642 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
15899 /* 50642 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15900 /* 50645 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
15901 /* 50649 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15902 /* 50654 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15903 /* 50658 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15904 /* 50662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15905 /* 50664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15906 /* 50667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15907 /* 50669 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
15908 /* 50676 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15909 /* 50681 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15910 /* 50686 */ // GIR_Coverage, 4050,
15911 /* 50686 */ GIR_EraseRootFromParent_Done,
15912 /* 50687 */ // Label 624: @50687
15913 /* 50687 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(50767), // Rule ID 4082 //
15914 /* 50692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
15915 /* 50695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15916 /* 50699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15917 /* 50703 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15918 /* 50707 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15919 /* 50711 */ // MIs[1] Operand 1
15920 /* 50711 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
15921 /* 50716 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15922 /* 50720 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15923 /* 50722 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] })
15924 /* 50722 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15925 /* 50725 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
15926 /* 50729 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15927 /* 50734 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15928 /* 50738 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15929 /* 50742 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15930 /* 50744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15931 /* 50747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15932 /* 50749 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
15933 /* 50756 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15934 /* 50761 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15935 /* 50766 */ // GIR_Coverage, 4082,
15936 /* 50766 */ GIR_EraseRootFromParent_Done,
15937 /* 50767 */ // Label 625: @50767
15938 /* 50767 */ GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(50847), // Rule ID 4114 //
15939 /* 50772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
15940 /* 50775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15941 /* 50779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15942 /* 50783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15943 /* 50787 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
15944 /* 50791 */ // MIs[1] Operand 1
15945 /* 50791 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
15946 /* 50796 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15947 /* 50800 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15948 /* 50802 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] })
15949 /* 50802 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15950 /* 50805 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
15951 /* 50809 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15952 /* 50814 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15953 /* 50818 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15954 /* 50822 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15955 /* 50824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15956 /* 50827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15957 /* 50829 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
15958 /* 50836 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15959 /* 50841 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15960 /* 50846 */ // GIR_Coverage, 4114,
15961 /* 50846 */ GIR_EraseRootFromParent_Done,
15962 /* 50847 */ // Label 626: @50847
15963 /* 50847 */ GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(50927), // Rule ID 4130 //
15964 /* 50852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
15965 /* 50855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15966 /* 50859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15967 /* 50863 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15968 /* 50867 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15969 /* 50871 */ // MIs[1] Operand 1
15970 /* 50871 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
15971 /* 50876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15972 /* 50880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15973 /* 50882 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] })
15974 /* 50882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15975 /* 50885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
15976 /* 50889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15977 /* 50894 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
15978 /* 50898 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
15979 /* 50902 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15980 /* 50904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15981 /* 50907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15982 /* 50909 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
15983 /* 50916 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
15984 /* 50921 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
15985 /* 50926 */ // GIR_Coverage, 4130,
15986 /* 50926 */ GIR_EraseRootFromParent_Done,
15987 /* 50927 */ // Label 627: @50927
15988 /* 50927 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(51007), // Rule ID 4162 //
15989 /* 50932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
15990 /* 50935 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15991 /* 50939 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
15992 /* 50943 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15993 /* 50947 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15994 /* 50951 */ // MIs[1] Operand 1
15995 /* 50951 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
15996 /* 50956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
15997 /* 50960 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15998 /* 50962 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
15999 /* 50962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16000 /* 50965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
16001 /* 50969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16002 /* 50974 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16003 /* 50978 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16004 /* 50982 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16005 /* 50984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16006 /* 50987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16007 /* 50989 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16008 /* 50996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16009 /* 51001 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16010 /* 51006 */ // GIR_Coverage, 4162,
16011 /* 51006 */ GIR_EraseRootFromParent_Done,
16012 /* 51007 */ // Label 628: @51007
16013 /* 51007 */ GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(51087), // Rule ID 4194 //
16014 /* 51012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
16015 /* 51015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16016 /* 51019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16017 /* 51023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16018 /* 51027 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16019 /* 51031 */ // MIs[1] Operand 1
16020 /* 51031 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
16021 /* 51036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16022 /* 51040 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16023 /* 51042 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] })
16024 /* 51042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16025 /* 51045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
16026 /* 51049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16027 /* 51054 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16028 /* 51058 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16029 /* 51062 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16030 /* 51064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16031 /* 51067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16032 /* 51069 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
16033 /* 51076 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16034 /* 51081 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16035 /* 51086 */ // GIR_Coverage, 4194,
16036 /* 51086 */ GIR_EraseRootFromParent_Done,
16037 /* 51087 */ // Label 629: @51087
16038 /* 51087 */ GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(51167), // Rule ID 4226 //
16039 /* 51092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
16040 /* 51095 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16041 /* 51099 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16042 /* 51103 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16043 /* 51107 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16044 /* 51111 */ // MIs[1] Operand 1
16045 /* 51111 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
16046 /* 51116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16047 /* 51120 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16048 /* 51122 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] })
16049 /* 51122 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16050 /* 51125 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
16051 /* 51129 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16052 /* 51134 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16053 /* 51138 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16054 /* 51142 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16055 /* 51144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16056 /* 51147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16057 /* 51149 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
16058 /* 51156 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16059 /* 51161 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16060 /* 51166 */ // GIR_Coverage, 4226,
16061 /* 51166 */ GIR_EraseRootFromParent_Done,
16062 /* 51167 */ // Label 630: @51167
16063 /* 51167 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(51247), // Rule ID 4256 //
16064 /* 51172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
16065 /* 51175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16066 /* 51179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16067 /* 51183 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
16068 /* 51187 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
16069 /* 51191 */ // MIs[1] Operand 1
16070 /* 51191 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
16071 /* 51196 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16072 /* 51200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16073 /* 51202 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] })
16074 /* 51202 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16075 /* 51205 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
16076 /* 51209 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16077 /* 51214 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16078 /* 51218 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16079 /* 51222 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16080 /* 51224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16081 /* 51227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16082 /* 51229 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16083 /* 51236 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16084 /* 51241 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16085 /* 51246 */ // GIR_Coverage, 4256,
16086 /* 51246 */ GIR_EraseRootFromParent_Done,
16087 /* 51247 */ // Label 631: @51247
16088 /* 51247 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(51327), // Rule ID 4288 //
16089 /* 51252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
16090 /* 51255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16091 /* 51259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16092 /* 51263 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
16093 /* 51267 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
16094 /* 51271 */ // MIs[1] Operand 1
16095 /* 51271 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
16096 /* 51276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16097 /* 51280 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16098 /* 51282 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] })
16099 /* 51282 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16100 /* 51285 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
16101 /* 51289 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16102 /* 51294 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16103 /* 51298 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16104 /* 51302 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16105 /* 51304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16106 /* 51307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16107 /* 51309 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16108 /* 51316 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16109 /* 51321 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16110 /* 51326 */ // GIR_Coverage, 4288,
16111 /* 51326 */ GIR_EraseRootFromParent_Done,
16112 /* 51327 */ // Label 632: @51327
16113 /* 51327 */ GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(51407), // Rule ID 4320 //
16114 /* 51332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
16115 /* 51335 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16116 /* 51339 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16117 /* 51343 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
16118 /* 51347 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
16119 /* 51351 */ // MIs[1] Operand 1
16120 /* 51351 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
16121 /* 51356 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16122 /* 51360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16123 /* 51362 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] })
16124 /* 51362 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16125 /* 51365 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
16126 /* 51369 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16127 /* 51374 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16128 /* 51378 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16129 /* 51382 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16130 /* 51384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16131 /* 51387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16132 /* 51389 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
16133 /* 51396 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16134 /* 51401 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16135 /* 51406 */ // GIR_Coverage, 4320,
16136 /* 51406 */ GIR_EraseRootFromParent_Done,
16137 /* 51407 */ // Label 633: @51407
16138 /* 51407 */ GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(51487), // Rule ID 4352 //
16139 /* 51412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
16140 /* 51415 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16141 /* 51419 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16142 /* 51423 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
16143 /* 51427 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
16144 /* 51431 */ // MIs[1] Operand 1
16145 /* 51431 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
16146 /* 51436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16147 /* 51440 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16148 /* 51442 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] })
16149 /* 51442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16150 /* 51445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
16151 /* 51449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16152 /* 51454 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16153 /* 51458 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16154 /* 51462 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16155 /* 51464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16156 /* 51467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16157 /* 51469 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
16158 /* 51476 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16159 /* 51481 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16160 /* 51486 */ // GIR_Coverage, 4352,
16161 /* 51486 */ GIR_EraseRootFromParent_Done,
16162 /* 51487 */ // Label 634: @51487
16163 /* 51487 */ GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(51567), // Rule ID 4583 //
16164 /* 51492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
16165 /* 51495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16166 /* 51499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16167 /* 51503 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16168 /* 51507 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16169 /* 51511 */ // MIs[1] Operand 1
16170 /* 51511 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
16171 /* 51516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16172 /* 51520 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16173 /* 51522 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
16174 /* 51522 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16175 /* 51525 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
16176 /* 51529 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16177 /* 51534 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16178 /* 51538 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16179 /* 51542 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16180 /* 51544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16181 /* 51547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16182 /* 51549 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16183 /* 51556 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16184 /* 51561 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16185 /* 51566 */ // GIR_Coverage, 4583,
16186 /* 51566 */ GIR_EraseRootFromParent_Done,
16187 /* 51567 */ // Label 635: @51567
16188 /* 51567 */ GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(51647), // Rule ID 4615 //
16189 /* 51572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
16190 /* 51575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16191 /* 51579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16192 /* 51583 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16193 /* 51587 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16194 /* 51591 */ // MIs[1] Operand 1
16195 /* 51591 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
16196 /* 51596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16197 /* 51600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16198 /* 51602 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
16199 /* 51602 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16200 /* 51605 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
16201 /* 51609 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16202 /* 51614 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16203 /* 51618 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16204 /* 51622 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16205 /* 51624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16206 /* 51627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16207 /* 51629 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16208 /* 51636 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16209 /* 51641 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16210 /* 51646 */ // GIR_Coverage, 4615,
16211 /* 51646 */ GIR_EraseRootFromParent_Done,
16212 /* 51647 */ // Label 636: @51647
16213 /* 51647 */ GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(51727), // Rule ID 4647 //
16214 /* 51652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
16215 /* 51655 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16216 /* 51659 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16217 /* 51663 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16218 /* 51667 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16219 /* 51671 */ // MIs[1] Operand 1
16220 /* 51671 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
16221 /* 51676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16222 /* 51680 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16223 /* 51682 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
16224 /* 51682 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16225 /* 51685 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
16226 /* 51689 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16227 /* 51694 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16228 /* 51698 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16229 /* 51702 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16230 /* 51704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16231 /* 51707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16232 /* 51709 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16233 /* 51716 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16234 /* 51721 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16235 /* 51726 */ // GIR_Coverage, 4647,
16236 /* 51726 */ GIR_EraseRootFromParent_Done,
16237 /* 51727 */ // Label 637: @51727
16238 /* 51727 */ GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(51807), // Rule ID 4691 //
16239 /* 51732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
16240 /* 51735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16241 /* 51739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16242 /* 51743 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16243 /* 51747 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16244 /* 51751 */ // MIs[1] Operand 1
16245 /* 51751 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
16246 /* 51756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16247 /* 51760 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16248 /* 51762 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
16249 /* 51762 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16250 /* 51765 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
16251 /* 51769 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16252 /* 51774 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16253 /* 51778 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16254 /* 51782 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16255 /* 51784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16256 /* 51787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16257 /* 51789 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16258 /* 51796 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16259 /* 51801 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16260 /* 51806 */ // GIR_Coverage, 4691,
16261 /* 51806 */ GIR_EraseRootFromParent_Done,
16262 /* 51807 */ // Label 638: @51807
16263 /* 51807 */ GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(51887), // Rule ID 4723 //
16264 /* 51812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
16265 /* 51815 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16266 /* 51819 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16267 /* 51823 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16268 /* 51827 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16269 /* 51831 */ // MIs[1] Operand 1
16270 /* 51831 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
16271 /* 51836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16272 /* 51840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16273 /* 51842 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
16274 /* 51842 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16275 /* 51845 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
16276 /* 51849 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16277 /* 51854 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16278 /* 51858 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16279 /* 51862 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16280 /* 51864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16281 /* 51867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16282 /* 51869 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16283 /* 51876 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16284 /* 51881 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16285 /* 51886 */ // GIR_Coverage, 4723,
16286 /* 51886 */ GIR_EraseRootFromParent_Done,
16287 /* 51887 */ // Label 639: @51887
16288 /* 51887 */ GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(51967), // Rule ID 4755 //
16289 /* 51892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
16290 /* 51895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16291 /* 51899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
16292 /* 51903 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16293 /* 51907 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16294 /* 51911 */ // MIs[1] Operand 1
16295 /* 51911 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
16296 /* 51916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16297 /* 51920 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16298 /* 51922 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
16299 /* 51922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16300 /* 51925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
16301 /* 51929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16302 /* 51934 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16303 /* 51938 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16304 /* 51942 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16305 /* 51944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16306 /* 51947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16307 /* 51949 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16308 /* 51956 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16309 /* 51961 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16310 /* 51966 */ // GIR_Coverage, 4755,
16311 /* 51966 */ GIR_EraseRootFromParent_Done,
16312 /* 51967 */ // Label 640: @51967
16313 /* 51967 */ GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(52047), // Rule ID 2981 //
16314 /* 51972 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16315 /* 51975 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16316 /* 51979 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16317 /* 51983 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16318 /* 51987 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16319 /* 51991 */ // MIs[1] Operand 1
16320 /* 51991 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
16321 /* 51996 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16322 /* 52000 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16323 /* 52002 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })
16324 /* 52002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16325 /* 52005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
16326 /* 52009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16327 /* 52014 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16328 /* 52018 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16329 /* 52022 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16330 /* 52024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16331 /* 52027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16332 /* 52029 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16333 /* 52036 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16334 /* 52041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16335 /* 52046 */ // GIR_Coverage, 2981,
16336 /* 52046 */ GIR_EraseRootFromParent_Done,
16337 /* 52047 */ // Label 641: @52047
16338 /* 52047 */ GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(52127), // Rule ID 2995 //
16339 /* 52052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16340 /* 52055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16341 /* 52059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16342 /* 52063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16343 /* 52067 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16344 /* 52071 */ // MIs[1] Operand 1
16345 /* 52071 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
16346 /* 52076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16347 /* 52080 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16348 /* 52082 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })
16349 /* 52082 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16350 /* 52085 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
16351 /* 52089 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16352 /* 52094 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16353 /* 52098 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16354 /* 52102 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16355 /* 52104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16356 /* 52107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16357 /* 52109 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16358 /* 52116 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16359 /* 52121 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16360 /* 52126 */ // GIR_Coverage, 2995,
16361 /* 52126 */ GIR_EraseRootFromParent_Done,
16362 /* 52127 */ // Label 642: @52127
16363 /* 52127 */ GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(52207), // Rule ID 3003 //
16364 /* 52132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16365 /* 52135 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16366 /* 52139 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16367 /* 52143 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16368 /* 52147 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16369 /* 52151 */ // MIs[1] Operand 1
16370 /* 52151 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
16371 /* 52156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16372 /* 52160 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16373 /* 52162 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })
16374 /* 52162 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16375 /* 52165 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
16376 /* 52169 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16377 /* 52174 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16378 /* 52178 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16379 /* 52182 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16380 /* 52184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16381 /* 52187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16382 /* 52189 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16383 /* 52196 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16384 /* 52201 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16385 /* 52206 */ // GIR_Coverage, 3003,
16386 /* 52206 */ GIR_EraseRootFromParent_Done,
16387 /* 52207 */ // Label 643: @52207
16388 /* 52207 */ GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(52287), // Rule ID 3011 //
16389 /* 52212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16390 /* 52215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16391 /* 52219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16392 /* 52223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16393 /* 52227 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16394 /* 52231 */ // MIs[1] Operand 1
16395 /* 52231 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
16396 /* 52236 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16397 /* 52240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16398 /* 52242 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })
16399 /* 52242 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16400 /* 52245 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
16401 /* 52249 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16402 /* 52254 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16403 /* 52258 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16404 /* 52262 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16405 /* 52264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16406 /* 52267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16407 /* 52269 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16408 /* 52276 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16409 /* 52281 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16410 /* 52286 */ // GIR_Coverage, 3011,
16411 /* 52286 */ GIR_EraseRootFromParent_Done,
16412 /* 52287 */ // Label 644: @52287
16413 /* 52287 */ GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(52367), // Rule ID 3019 //
16414 /* 52292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16415 /* 52295 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16416 /* 52299 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16417 /* 52303 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16418 /* 52307 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16419 /* 52311 */ // MIs[1] Operand 1
16420 /* 52311 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16421 /* 52316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16422 /* 52320 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16423 /* 52322 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] })
16424 /* 52322 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16425 /* 52325 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
16426 /* 52329 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16427 /* 52334 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16428 /* 52338 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16429 /* 52342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16430 /* 52344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16431 /* 52347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16432 /* 52349 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
16433 /* 52356 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16434 /* 52361 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16435 /* 52366 */ // GIR_Coverage, 3019,
16436 /* 52366 */ GIR_EraseRootFromParent_Done,
16437 /* 52367 */ // Label 645: @52367
16438 /* 52367 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(52447), // Rule ID 3083 //
16439 /* 52372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16440 /* 52375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16441 /* 52379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16442 /* 52383 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16443 /* 52387 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16444 /* 52391 */ // MIs[1] Operand 1
16445 /* 52391 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
16446 /* 52396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16447 /* 52400 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16448 /* 52402 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })
16449 /* 52402 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16450 /* 52405 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
16451 /* 52409 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16452 /* 52414 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16453 /* 52418 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16454 /* 52422 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16455 /* 52424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16456 /* 52427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16457 /* 52429 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16458 /* 52436 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16459 /* 52441 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16460 /* 52446 */ // GIR_Coverage, 3083,
16461 /* 52446 */ GIR_EraseRootFromParent_Done,
16462 /* 52447 */ // Label 646: @52447
16463 /* 52447 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(52527), // Rule ID 3091 //
16464 /* 52452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16465 /* 52455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16466 /* 52459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16467 /* 52463 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16468 /* 52467 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16469 /* 52471 */ // MIs[1] Operand 1
16470 /* 52471 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
16471 /* 52476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16472 /* 52480 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16473 /* 52482 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })
16474 /* 52482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16475 /* 52485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
16476 /* 52489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16477 /* 52494 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16478 /* 52498 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16479 /* 52502 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16480 /* 52504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16481 /* 52507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16482 /* 52509 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16483 /* 52516 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16484 /* 52521 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16485 /* 52526 */ // GIR_Coverage, 3091,
16486 /* 52526 */ GIR_EraseRootFromParent_Done,
16487 /* 52527 */ // Label 647: @52527
16488 /* 52527 */ GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(52607), // Rule ID 3099 //
16489 /* 52532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16490 /* 52535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16491 /* 52539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16492 /* 52543 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16493 /* 52547 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16494 /* 52551 */ // MIs[1] Operand 1
16495 /* 52551 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
16496 /* 52556 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16497 /* 52560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16498 /* 52562 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })
16499 /* 52562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16500 /* 52565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
16501 /* 52569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16502 /* 52574 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16503 /* 52578 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16504 /* 52582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16505 /* 52584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16506 /* 52587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16507 /* 52589 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16508 /* 52596 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16509 /* 52601 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16510 /* 52606 */ // GIR_Coverage, 3099,
16511 /* 52606 */ GIR_EraseRootFromParent_Done,
16512 /* 52607 */ // Label 648: @52607
16513 /* 52607 */ GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(52687), // Rule ID 3107 //
16514 /* 52612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16515 /* 52615 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16516 /* 52619 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16517 /* 52623 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16518 /* 52627 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16519 /* 52631 */ // MIs[1] Operand 1
16520 /* 52631 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
16521 /* 52636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16522 /* 52640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16523 /* 52642 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })
16524 /* 52642 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16525 /* 52645 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
16526 /* 52649 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16527 /* 52654 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16528 /* 52658 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16529 /* 52662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16530 /* 52664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16531 /* 52667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16532 /* 52669 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16533 /* 52676 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16534 /* 52681 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16535 /* 52686 */ // GIR_Coverage, 3107,
16536 /* 52686 */ GIR_EraseRootFromParent_Done,
16537 /* 52687 */ // Label 649: @52687
16538 /* 52687 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(52767), // Rule ID 3115 //
16539 /* 52692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
16540 /* 52695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16541 /* 52699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16542 /* 52703 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16543 /* 52707 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16544 /* 52711 */ // MIs[1] Operand 1
16545 /* 52711 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16546 /* 52716 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16547 /* 52720 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16548 /* 52722 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] })
16549 /* 52722 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16550 /* 52725 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
16551 /* 52729 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16552 /* 52734 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16553 /* 52738 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16554 /* 52742 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16555 /* 52744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16556 /* 52747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16557 /* 52749 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
16558 /* 52756 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16559 /* 52761 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16560 /* 52766 */ // GIR_Coverage, 3115,
16561 /* 52766 */ GIR_EraseRootFromParent_Done,
16562 /* 52767 */ // Label 650: @52767
16563 /* 52767 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(52847), // Rule ID 3866 //
16564 /* 52772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16565 /* 52775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16566 /* 52779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16567 /* 52783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16568 /* 52787 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16569 /* 52791 */ // MIs[1] Operand 1
16570 /* 52791 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
16571 /* 52796 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16572 /* 52800 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16573 /* 52802 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })
16574 /* 52802 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16575 /* 52805 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
16576 /* 52809 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16577 /* 52814 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16578 /* 52818 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16579 /* 52822 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16580 /* 52824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16581 /* 52827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16582 /* 52829 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16583 /* 52836 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16584 /* 52841 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16585 /* 52846 */ // GIR_Coverage, 3866,
16586 /* 52846 */ GIR_EraseRootFromParent_Done,
16587 /* 52847 */ // Label 651: @52847
16588 /* 52847 */ GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(52927), // Rule ID 3874 //
16589 /* 52852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16590 /* 52855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16591 /* 52859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16592 /* 52863 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16593 /* 52867 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16594 /* 52871 */ // MIs[1] Operand 1
16595 /* 52871 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
16596 /* 52876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16597 /* 52880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16598 /* 52882 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })
16599 /* 52882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16600 /* 52885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
16601 /* 52889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16602 /* 52894 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16603 /* 52898 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16604 /* 52902 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16605 /* 52904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16606 /* 52907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16607 /* 52909 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16608 /* 52916 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16609 /* 52921 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16610 /* 52926 */ // GIR_Coverage, 3874,
16611 /* 52926 */ GIR_EraseRootFromParent_Done,
16612 /* 52927 */ // Label 652: @52927
16613 /* 52927 */ GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(53007), // Rule ID 3882 //
16614 /* 52932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16615 /* 52935 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16616 /* 52939 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16617 /* 52943 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16618 /* 52947 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16619 /* 52951 */ // MIs[1] Operand 1
16620 /* 52951 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
16621 /* 52956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16622 /* 52960 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16623 /* 52962 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })
16624 /* 52962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16625 /* 52965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
16626 /* 52969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16627 /* 52974 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16628 /* 52978 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16629 /* 52982 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16630 /* 52984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16631 /* 52987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16632 /* 52989 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16633 /* 52996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16634 /* 53001 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16635 /* 53006 */ // GIR_Coverage, 3882,
16636 /* 53006 */ GIR_EraseRootFromParent_Done,
16637 /* 53007 */ // Label 653: @53007
16638 /* 53007 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(53087), // Rule ID 3890 //
16639 /* 53012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16640 /* 53015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16641 /* 53019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16642 /* 53023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16643 /* 53027 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16644 /* 53031 */ // MIs[1] Operand 1
16645 /* 53031 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
16646 /* 53036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16647 /* 53040 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16648 /* 53042 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })
16649 /* 53042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16650 /* 53045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
16651 /* 53049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16652 /* 53054 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16653 /* 53058 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16654 /* 53062 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16655 /* 53064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16656 /* 53067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16657 /* 53069 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16658 /* 53076 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16659 /* 53081 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16660 /* 53086 */ // GIR_Coverage, 3890,
16661 /* 53086 */ GIR_EraseRootFromParent_Done,
16662 /* 53087 */ // Label 654: @53087
16663 /* 53087 */ GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(53167), // Rule ID 3898 //
16664 /* 53092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16665 /* 53095 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16666 /* 53099 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16667 /* 53103 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16668 /* 53107 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
16669 /* 53111 */ // MIs[1] Operand 1
16670 /* 53111 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16671 /* 53116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16672 /* 53120 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16673 /* 53122 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] })
16674 /* 53122 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16675 /* 53125 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
16676 /* 53129 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16677 /* 53134 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16678 /* 53138 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16679 /* 53142 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16680 /* 53144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16681 /* 53147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16682 /* 53149 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
16683 /* 53156 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16684 /* 53161 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16685 /* 53166 */ // GIR_Coverage, 3898,
16686 /* 53166 */ GIR_EraseRootFromParent_Done,
16687 /* 53167 */ // Label 655: @53167
16688 /* 53167 */ GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(53247), // Rule ID 3962 //
16689 /* 53172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16690 /* 53175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16691 /* 53179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16692 /* 53183 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16693 /* 53187 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16694 /* 53191 */ // MIs[1] Operand 1
16695 /* 53191 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
16696 /* 53196 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16697 /* 53200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16698 /* 53202 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })
16699 /* 53202 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16700 /* 53205 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
16701 /* 53209 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16702 /* 53214 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16703 /* 53218 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16704 /* 53222 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16705 /* 53224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16706 /* 53227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16707 /* 53229 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16708 /* 53236 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16709 /* 53241 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16710 /* 53246 */ // GIR_Coverage, 3962,
16711 /* 53246 */ GIR_EraseRootFromParent_Done,
16712 /* 53247 */ // Label 656: @53247
16713 /* 53247 */ GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(53327), // Rule ID 3970 //
16714 /* 53252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16715 /* 53255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16716 /* 53259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16717 /* 53263 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16718 /* 53267 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16719 /* 53271 */ // MIs[1] Operand 1
16720 /* 53271 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
16721 /* 53276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16722 /* 53280 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16723 /* 53282 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })
16724 /* 53282 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16725 /* 53285 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
16726 /* 53289 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16727 /* 53294 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16728 /* 53298 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16729 /* 53302 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16730 /* 53304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16731 /* 53307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16732 /* 53309 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
16733 /* 53316 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16734 /* 53321 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16735 /* 53326 */ // GIR_Coverage, 3970,
16736 /* 53326 */ GIR_EraseRootFromParent_Done,
16737 /* 53327 */ // Label 657: @53327
16738 /* 53327 */ GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(53407), // Rule ID 3978 //
16739 /* 53332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16740 /* 53335 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16741 /* 53339 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16742 /* 53343 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16743 /* 53347 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16744 /* 53351 */ // MIs[1] Operand 1
16745 /* 53351 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
16746 /* 53356 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16747 /* 53360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16748 /* 53362 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })
16749 /* 53362 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16750 /* 53365 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
16751 /* 53369 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16752 /* 53374 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16753 /* 53378 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16754 /* 53382 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16755 /* 53384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16756 /* 53387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16757 /* 53389 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16758 /* 53396 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16759 /* 53401 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16760 /* 53406 */ // GIR_Coverage, 3978,
16761 /* 53406 */ GIR_EraseRootFromParent_Done,
16762 /* 53407 */ // Label 658: @53407
16763 /* 53407 */ GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(53487), // Rule ID 3986 //
16764 /* 53412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16765 /* 53415 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16766 /* 53419 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16767 /* 53423 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16768 /* 53427 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16769 /* 53431 */ // MIs[1] Operand 1
16770 /* 53431 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
16771 /* 53436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16772 /* 53440 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16773 /* 53442 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })
16774 /* 53442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16775 /* 53445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
16776 /* 53449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16777 /* 53454 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16778 /* 53458 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16779 /* 53462 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16780 /* 53464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16781 /* 53467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16782 /* 53469 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
16783 /* 53476 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16784 /* 53481 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16785 /* 53486 */ // GIR_Coverage, 3986,
16786 /* 53486 */ GIR_EraseRootFromParent_Done,
16787 /* 53487 */ // Label 659: @53487
16788 /* 53487 */ GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(53567), // Rule ID 3994 //
16789 /* 53492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
16790 /* 53495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16791 /* 53499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16792 /* 53503 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16793 /* 53507 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16794 /* 53511 */ // MIs[1] Operand 1
16795 /* 53511 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16796 /* 53516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16797 /* 53520 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16798 /* 53522 */ // (xor:{ *:[i1] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] }), -1:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] })
16799 /* 53522 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16800 /* 53525 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
16801 /* 53529 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16802 /* 53534 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
16803 /* 53538 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // s2
16804 /* 53542 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16805 /* 53544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16806 /* 53547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16807 /* 53549 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
16808 /* 53556 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
16809 /* 53561 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
16810 /* 53566 */ // GIR_Coverage, 3994,
16811 /* 53566 */ GIR_EraseRootFromParent_Done,
16812 /* 53567 */ // Label 660: @53567
16813 /* 53567 */ GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(53609), // Rule ID 176 //
16814 /* 53572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16815 /* 53576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16816 /* 53580 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
16817 /* 53584 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
16818 /* 53588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16819 /* 53592 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16820 /* 53594 */ // (xor:{ *:[i1] } (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CRNAND:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
16821 /* 53594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNAND),
16822 /* 53597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
16823 /* 53599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA
16824 /* 53603 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB
16825 /* 53607 */ GIR_RootConstrainSelectedInstOperands,
16826 /* 53608 */ // GIR_Coverage, 176,
16827 /* 53608 */ GIR_EraseRootFromParent_Done,
16828 /* 53609 */ // Label 661: @53609
16829 /* 53609 */ GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(53651), // Rule ID 179 //
16830 /* 53614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16831 /* 53618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
16832 /* 53622 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
16833 /* 53626 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
16834 /* 53630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16835 /* 53634 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16836 /* 53636 */ // (xor:{ *:[i1] } (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CRNOR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
16837 /* 53636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOR),
16838 /* 53639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
16839 /* 53641 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA
16840 /* 53645 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB
16841 /* 53649 */ GIR_RootConstrainSelectedInstOperands,
16842 /* 53650 */ // GIR_Coverage, 179,
16843 /* 53650 */ GIR_EraseRootFromParent_Done,
16844 /* 53651 */ // Label 662: @53651
16845 /* 53651 */ GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(53691), // Rule ID 4922 //
16846 /* 53656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16847 /* 53660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16848 /* 53664 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
16849 /* 53668 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
16850 /* 53672 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16851 /* 53676 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16852 /* 53678 */ // (xor:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRB) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
16853 /* 53678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV),
16854 /* 53681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
16855 /* 53683 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA
16856 /* 53687 */ GIR_RootToRootCopy, /*OpIdx*/2, // CRB
16857 /* 53689 */ GIR_RootConstrainSelectedInstOperands,
16858 /* 53690 */ // GIR_Coverage, 4922,
16859 /* 53690 */ GIR_EraseRootFromParent_Done,
16860 /* 53691 */ // Label 663: @53691
16861 /* 53691 */ GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(53733), // Rule ID 180 //
16862 /* 53696 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16863 /* 53700 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16864 /* 53704 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
16865 /* 53708 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
16866 /* 53712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16867 /* 53716 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16868 /* 53718 */ // (xor:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
16869 /* 53718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV),
16870 /* 53721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
16871 /* 53723 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA
16872 /* 53727 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB
16873 /* 53731 */ GIR_RootConstrainSelectedInstOperands,
16874 /* 53732 */ // GIR_Coverage, 180,
16875 /* 53732 */ GIR_EraseRootFromParent_Done,
16876 /* 53733 */ // Label 664: @53733
16877 /* 53733 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(53770), // Rule ID 4855 //
16878 /* 53738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16879 /* 53742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16880 /* 53746 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16881 /* 53750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16882 /* 53754 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16883 /* 53756 */ // (xor:{ *:[i1] } (trunc:{ *:[i1] } i32:{ *:[i32] }:$in), -1:{ *:[i1] }) => (ANDI_rec_1_EQ_BIT:{ *:[i1] }:{ *:[i32] } ?:{ *:[i32] }:$in)
16884 /* 53756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_EQ_BIT),
16885 /* 53759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16886 /* 53761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // in
16887 /* 53765 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
16888 /* 53768 */ GIR_RootConstrainSelectedInstOperands,
16889 /* 53769 */ // GIR_Coverage, 4855,
16890 /* 53769 */ GIR_EraseRootFromParent_Done,
16891 /* 53770 */ // Label 665: @53770
16892 /* 53770 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(53807), // Rule ID 4856 //
16893 /* 53775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16894 /* 53779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16895 /* 53783 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16896 /* 53787 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16897 /* 53791 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16898 /* 53793 */ // (xor:{ *:[i1] } (trunc:{ *:[i1] } i64:{ *:[i64] }:$in), -1:{ *:[i1] }) => (ANDI_rec_1_EQ_BIT8:{ *:[i1] }:{ *:[i32] } ?:{ *:[i64] }:$in)
16899 /* 53793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_EQ_BIT8),
16900 /* 53796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16901 /* 53798 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // in
16902 /* 53802 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
16903 /* 53805 */ GIR_RootConstrainSelectedInstOperands,
16904 /* 53806 */ // GIR_Coverage, 4856,
16905 /* 53806 */ GIR_EraseRootFromParent_Done,
16906 /* 53807 */ // Label 666: @53807
16907 /* 53807 */ GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(53847), // Rule ID 4923 //
16908 /* 53812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16909 /* 53816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16910 /* 53820 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
16911 /* 53824 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
16912 /* 53828 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16913 /* 53832 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16914 /* 53834 */ // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] })) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
16915 /* 53834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV),
16916 /* 53837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
16917 /* 53839 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA
16918 /* 53843 */ GIR_RootToRootCopy, /*OpIdx*/1, // CRB
16919 /* 53845 */ GIR_RootConstrainSelectedInstOperands,
16920 /* 53846 */ // GIR_Coverage, 4923,
16921 /* 53846 */ GIR_EraseRootFromParent_Done,
16922 /* 53847 */ // Label 667: @53847
16923 /* 53847 */ GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(53865), // Rule ID 181 //
16924 /* 53852 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16925 /* 53856 */ // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] }) => (CRNOT:{ *:[i1] } i1:{ *:[i1] }:$CRA)
16926 /* 53856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
16927 /* 53859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
16928 /* 53861 */ GIR_RootToRootCopy, /*OpIdx*/1, // CRA
16929 /* 53863 */ GIR_RootConstrainSelectedInstOperands,
16930 /* 53864 */ // GIR_Coverage, 181,
16931 /* 53864 */ GIR_EraseRootFromParent_Done,
16932 /* 53865 */ // Label 668: @53865
16933 /* 53865 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(53883), // Rule ID 2909 //
16934 /* 53870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16935 /* 53874 */ // (xor:{ *:[i1] } i1:{ *:[i1] }:$in, -1:{ *:[i1] }) => (CRNOT:{ *:[i1] } ?:{ *:[i1] }:$in)
16936 /* 53874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
16937 /* 53877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
16938 /* 53879 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
16939 /* 53881 */ GIR_RootConstrainSelectedInstOperands,
16940 /* 53882 */ // GIR_Coverage, 2909,
16941 /* 53882 */ GIR_EraseRootFromParent_Done,
16942 /* 53883 */ // Label 669: @53883
16943 /* 53883 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(53895), // Rule ID 178 //
16944 /* 53888 */ // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CRXOR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB)
16945 /* 53888 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR),
16946 /* 53893 */ GIR_RootConstrainSelectedInstOperands,
16947 /* 53894 */ // GIR_Coverage, 178,
16948 /* 53894 */ GIR_Done,
16949 /* 53895 */ // Label 670: @53895
16950 /* 53895 */ GIM_Reject,
16951 /* 53896 */ // Label 598: @53896
16952 /* 53896 */ GIM_Reject,
16953 /* 53897 */ // Label 594: @53897
16954 /* 53897 */ GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(54151),
16955 /* 53902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16956 /* 53905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16957 /* 53908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
16958 /* 53912 */ GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(53954), // Rule ID 121 //
16959 /* 53917 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16960 /* 53921 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16961 /* 53925 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16962 /* 53929 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16963 /* 53933 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16964 /* 53937 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16965 /* 53939 */ // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (NAND:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
16966 /* 53939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NAND),
16967 /* 53942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
16968 /* 53944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
16969 /* 53948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
16970 /* 53952 */ GIR_RootConstrainSelectedInstOperands,
16971 /* 53953 */ // GIR_Coverage, 121,
16972 /* 53953 */ GIR_EraseRootFromParent_Done,
16973 /* 53954 */ // Label 672: @53954
16974 /* 53954 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(53996), // Rule ID 125 //
16975 /* 53959 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16976 /* 53963 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
16977 /* 53967 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16978 /* 53971 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16979 /* 53975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16980 /* 53979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16981 /* 53981 */ // (xor:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (NOR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
16982 /* 53981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR),
16983 /* 53984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
16984 /* 53986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
16985 /* 53990 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
16986 /* 53994 */ GIR_RootConstrainSelectedInstOperands,
16987 /* 53995 */ // GIR_Coverage, 125,
16988 /* 53995 */ GIR_EraseRootFromParent_Done,
16989 /* 53996 */ // Label 673: @53996
16990 /* 53996 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(54036), // Rule ID 4920 //
16991 /* 54001 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16992 /* 54005 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16993 /* 54009 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16994 /* 54013 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16995 /* 54017 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16996 /* 54021 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16997 /* 54023 */ // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, -1:{ *:[i32] }), i32:{ *:[i32] }:$RB) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
16998 /* 54023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV),
16999 /* 54026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17000 /* 54028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
17001 /* 54032 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
17002 /* 54034 */ GIR_RootConstrainSelectedInstOperands,
17003 /* 54035 */ // GIR_Coverage, 4920,
17004 /* 54035 */ GIR_EraseRootFromParent_Done,
17005 /* 54036 */ // Label 674: @54036
17006 /* 54036 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(54078), // Rule ID 127 //
17007 /* 54041 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17008 /* 54045 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17009 /* 54049 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17010 /* 54053 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17011 /* 54057 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
17012 /* 54061 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17013 /* 54063 */ // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
17014 /* 54063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV),
17015 /* 54066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17016 /* 54068 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
17017 /* 54072 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
17018 /* 54076 */ GIR_RootConstrainSelectedInstOperands,
17019 /* 54077 */ // GIR_Coverage, 127,
17020 /* 54077 */ GIR_EraseRootFromParent_Done,
17021 /* 54078 */ // Label 675: @54078
17022 /* 54078 */ GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(54118), // Rule ID 4921 //
17023 /* 54083 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17024 /* 54087 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17025 /* 54091 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17026 /* 54095 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17027 /* 54099 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
17028 /* 54103 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17029 /* 54105 */ // (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, -1:{ *:[i32] })) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
17030 /* 54105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV),
17031 /* 54108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17032 /* 54110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
17033 /* 54114 */ GIR_RootToRootCopy, /*OpIdx*/1, // RB
17034 /* 54116 */ GIR_RootConstrainSelectedInstOperands,
17035 /* 54117 */ // GIR_Coverage, 4921,
17036 /* 54117 */ GIR_EraseRootFromParent_Done,
17037 /* 54118 */ // Label 676: @54118
17038 /* 54118 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(54138), // Rule ID 1213 //
17039 /* 54123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
17040 /* 54127 */ // (xor:{ *:[i32] } i32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } ?:{ *:[i32] }:$in, ?:{ *:[i32] }:$in)
17041 /* 54127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR),
17042 /* 54130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17043 /* 54132 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17044 /* 54134 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17045 /* 54136 */ GIR_RootConstrainSelectedInstOperands,
17046 /* 54137 */ // GIR_Coverage, 1213,
17047 /* 54137 */ GIR_EraseRootFromParent_Done,
17048 /* 54138 */ // Label 677: @54138
17049 /* 54138 */ GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(54150), // Rule ID 128 //
17050 /* 54143 */ // (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (XOR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB)
17051 /* 54143 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XOR),
17052 /* 54148 */ GIR_RootConstrainSelectedInstOperands,
17053 /* 54149 */ // GIR_Coverage, 128,
17054 /* 54149 */ GIR_Done,
17055 /* 54150 */ // Label 678: @54150
17056 /* 54150 */ GIM_Reject,
17057 /* 54151 */ // Label 671: @54151
17058 /* 54151 */ GIM_Reject,
17059 /* 54152 */ // Label 595: @54152
17060 /* 54152 */ GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(54406),
17061 /* 54157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17062 /* 54160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
17063 /* 54163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
17064 /* 54167 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(54209), // Rule ID 645 //
17065 /* 54172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17066 /* 54176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17067 /* 54180 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17068 /* 54184 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17069 /* 54188 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
17070 /* 54192 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17071 /* 54194 */ // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (NAND8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
17072 /* 54194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NAND8),
17073 /* 54197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17074 /* 54199 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
17075 /* 54203 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
17076 /* 54207 */ GIR_RootConstrainSelectedInstOperands,
17077 /* 54208 */ // GIR_Coverage, 645,
17078 /* 54208 */ GIR_EraseRootFromParent_Done,
17079 /* 54209 */ // Label 680: @54209
17080 /* 54209 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(54251), // Rule ID 649 //
17081 /* 54214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17082 /* 54218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17083 /* 54222 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17084 /* 54226 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17085 /* 54230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
17086 /* 54234 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17087 /* 54236 */ // (xor:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (NOR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
17088 /* 54236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR8),
17089 /* 54239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17090 /* 54241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
17091 /* 54245 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
17092 /* 54249 */ GIR_RootConstrainSelectedInstOperands,
17093 /* 54250 */ // GIR_Coverage, 649,
17094 /* 54250 */ GIR_EraseRootFromParent_Done,
17095 /* 54251 */ // Label 681: @54251
17096 /* 54251 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(54291), // Rule ID 4933 //
17097 /* 54256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17098 /* 54260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17099 /* 54264 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17100 /* 54268 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17101 /* 54272 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
17102 /* 54276 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17103 /* 54278 */ // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, -1:{ *:[i64] }), i64:{ *:[i64] }:$RB) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
17104 /* 54278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8),
17105 /* 54281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17106 /* 54283 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
17107 /* 54287 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
17108 /* 54289 */ GIR_RootConstrainSelectedInstOperands,
17109 /* 54290 */ // GIR_Coverage, 4933,
17110 /* 54290 */ GIR_EraseRootFromParent_Done,
17111 /* 54291 */ // Label 682: @54291
17112 /* 54291 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(54333), // Rule ID 651 //
17113 /* 54296 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17114 /* 54300 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17115 /* 54304 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17116 /* 54308 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17117 /* 54312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
17118 /* 54316 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17119 /* 54318 */ // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
17120 /* 54318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8),
17121 /* 54321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17122 /* 54323 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
17123 /* 54327 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
17124 /* 54331 */ GIR_RootConstrainSelectedInstOperands,
17125 /* 54332 */ // GIR_Coverage, 651,
17126 /* 54332 */ GIR_EraseRootFromParent_Done,
17127 /* 54333 */ // Label 683: @54333
17128 /* 54333 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(54373), // Rule ID 4934 //
17129 /* 54338 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17130 /* 54342 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17131 /* 54346 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17132 /* 54350 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17133 /* 54354 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
17134 /* 54358 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17135 /* 54360 */ // (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, -1:{ *:[i64] })) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
17136 /* 54360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8),
17137 /* 54363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17138 /* 54365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST
17139 /* 54369 */ GIR_RootToRootCopy, /*OpIdx*/1, // RB
17140 /* 54371 */ GIR_RootConstrainSelectedInstOperands,
17141 /* 54372 */ // GIR_Coverage, 4934,
17142 /* 54372 */ GIR_EraseRootFromParent_Done,
17143 /* 54373 */ // Label 684: @54373
17144 /* 54373 */ GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(54393), // Rule ID 1525 //
17145 /* 54378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
17146 /* 54382 */ // (xor:{ *:[i64] } i64:{ *:[i64] }:$in, -1:{ *:[i64] }) => (NOR8:{ *:[i64] } ?:{ *:[i64] }:$in, ?:{ *:[i64] }:$in)
17147 /* 54382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR8),
17148 /* 54385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
17149 /* 54387 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17150 /* 54389 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17151 /* 54391 */ GIR_RootConstrainSelectedInstOperands,
17152 /* 54392 */ // GIR_Coverage, 1525,
17153 /* 54392 */ GIR_EraseRootFromParent_Done,
17154 /* 54393 */ // Label 685: @54393
17155 /* 54393 */ GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(54405), // Rule ID 652 //
17156 /* 54398 */ // (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (XOR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
17157 /* 54398 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XOR8),
17158 /* 54403 */ GIR_RootConstrainSelectedInstOperands,
17159 /* 54404 */ // GIR_Coverage, 652,
17160 /* 54404 */ GIR_Done,
17161 /* 54405 */ // Label 686: @54405
17162 /* 54405 */ GIM_Reject,
17163 /* 54406 */ // Label 679: @54406
17164 /* 54406 */ GIM_Reject,
17165 /* 54407 */ // Label 596: @54407
17166 /* 54407 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(57530),
17167 /* 54412 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
17168 /* 54415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17169 /* 54418 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(54505), // Rule ID 4969 //
17170 /* 54423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17171 /* 54426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17172 /* 54430 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17173 /* 54434 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17174 /* 54438 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17175 /* 54442 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17176 /* 54446 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17177 /* 54450 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
17178 /* 54454 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17179 /* 54458 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17180 /* 54462 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17181 /* 54466 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17182 /* 54472 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17183 /* 54474 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17184 /* 54476 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 254:{ *:[i32] })
17185 /* 54476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17186 /* 54479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17187 /* 54481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
17188 /* 54485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
17189 /* 54489 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
17190 /* 54493 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
17191 /* 54503 */ GIR_RootConstrainSelectedInstOperands,
17192 /* 54504 */ // GIR_Coverage, 4969,
17193 /* 54504 */ GIR_EraseRootFromParent_Done,
17194 /* 54505 */ // Label 688: @54505
17195 /* 54505 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(54592), // Rule ID 4971 //
17196 /* 54510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17197 /* 54513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17198 /* 54517 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17199 /* 54521 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17200 /* 54525 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17201 /* 54529 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17202 /* 54533 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17203 /* 54537 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
17204 /* 54541 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17205 /* 54545 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17206 /* 54549 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17207 /* 54553 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17208 /* 54559 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17209 /* 54561 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17210 /* 54563 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 248:{ *:[i32] })
17211 /* 54563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17212 /* 54566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17213 /* 54568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
17214 /* 54572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17215 /* 54576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17216 /* 54580 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(248),
17217 /* 54590 */ GIR_RootConstrainSelectedInstOperands,
17218 /* 54591 */ // GIR_Coverage, 4971,
17219 /* 54591 */ GIR_EraseRootFromParent_Done,
17220 /* 54592 */ // Label 689: @54592
17221 /* 54592 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(54679), // Rule ID 4970 //
17222 /* 54597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17223 /* 54600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17224 /* 54604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17225 /* 54608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17226 /* 54612 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17227 /* 54616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17228 /* 54620 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17229 /* 54624 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17230 /* 54628 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17231 /* 54632 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17232 /* 54636 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17233 /* 54640 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17234 /* 54646 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17235 /* 54648 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17236 /* 54650 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 249:{ *:[i32] })
17237 /* 54650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17238 /* 54653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17239 /* 54655 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
17240 /* 54659 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17241 /* 54663 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17242 /* 54667 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(249),
17243 /* 54677 */ GIR_RootConstrainSelectedInstOperands,
17244 /* 54678 */ // GIR_Coverage, 4970,
17245 /* 54678 */ GIR_EraseRootFromParent_Done,
17246 /* 54679 */ // Label 690: @54679
17247 /* 54679 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(54766), // Rule ID 3393 //
17248 /* 54684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17249 /* 54687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17250 /* 54691 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17251 /* 54695 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17252 /* 54699 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17253 /* 54703 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17254 /* 54707 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17255 /* 54711 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
17256 /* 54715 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17257 /* 54719 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17258 /* 54723 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17259 /* 54727 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17260 /* 54733 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17261 /* 54735 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17262 /* 54737 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 254:{ *:[i32] })
17263 /* 54737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17264 /* 54740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17265 /* 54742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17266 /* 54746 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17267 /* 54750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17268 /* 54754 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
17269 /* 54764 */ GIR_RootConstrainSelectedInstOperands,
17270 /* 54765 */ // GIR_Coverage, 3393,
17271 /* 54765 */ GIR_EraseRootFromParent_Done,
17272 /* 54766 */ // Label 691: @54766
17273 /* 54766 */ GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(54853), // Rule ID 3395 //
17274 /* 54771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17275 /* 54774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17276 /* 54778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17277 /* 54782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17278 /* 54786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17279 /* 54790 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17280 /* 54794 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17281 /* 54798 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
17282 /* 54802 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17283 /* 54806 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17284 /* 54810 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17285 /* 54814 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17286 /* 54820 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17287 /* 54822 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17288 /* 54824 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 248:{ *:[i32] })
17289 /* 54824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17290 /* 54827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17291 /* 54829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17292 /* 54833 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17293 /* 54837 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17294 /* 54841 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(248),
17295 /* 54851 */ GIR_RootConstrainSelectedInstOperands,
17296 /* 54852 */ // GIR_Coverage, 3395,
17297 /* 54852 */ GIR_EraseRootFromParent_Done,
17298 /* 54853 */ // Label 692: @54853
17299 /* 54853 */ GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(54940), // Rule ID 3394 //
17300 /* 54858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17301 /* 54861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17302 /* 54865 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17303 /* 54869 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17304 /* 54873 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17305 /* 54877 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17306 /* 54881 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17307 /* 54885 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17308 /* 54889 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17309 /* 54893 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17310 /* 54897 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17311 /* 54901 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17312 /* 54907 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17313 /* 54909 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17314 /* 54911 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 249:{ *:[i32] })
17315 /* 54911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17316 /* 54914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17317 /* 54916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17318 /* 54920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17319 /* 54924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17320 /* 54928 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(249),
17321 /* 54938 */ GIR_RootConstrainSelectedInstOperands,
17322 /* 54939 */ // GIR_Coverage, 3394,
17323 /* 54939 */ GIR_EraseRootFromParent_Done,
17324 /* 54940 */ // Label 693: @54940
17325 /* 54940 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(55027), // Rule ID 5269 //
17326 /* 54945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17327 /* 54948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17328 /* 54952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17329 /* 54956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17330 /* 54960 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17331 /* 54964 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17332 /* 54968 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
17333 /* 54972 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17334 /* 54976 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17335 /* 54980 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17336 /* 54984 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17337 /* 54988 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17338 /* 54994 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17339 /* 54996 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17340 /* 54998 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 225:{ *:[i32] })
17341 /* 54998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17342 /* 55001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17343 /* 55003 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
17344 /* 55007 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
17345 /* 55011 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
17346 /* 55015 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(225),
17347 /* 55025 */ GIR_RootConstrainSelectedInstOperands,
17348 /* 55026 */ // GIR_Coverage, 5269,
17349 /* 55026 */ GIR_EraseRootFromParent_Done,
17350 /* 55027 */ // Label 694: @55027
17351 /* 55027 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(55114), // Rule ID 5277 //
17352 /* 55032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17353 /* 55035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17354 /* 55039 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17355 /* 55043 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17356 /* 55047 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17357 /* 55051 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17358 /* 55055 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17359 /* 55059 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
17360 /* 55063 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17361 /* 55067 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17362 /* 55071 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17363 /* 55075 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17364 /* 55081 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17365 /* 55083 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17366 /* 55085 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 224:{ *:[i32] })
17367 /* 55085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17368 /* 55088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17369 /* 55090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
17370 /* 55094 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17371 /* 55098 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17372 /* 55102 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(224),
17373 /* 55112 */ GIR_RootConstrainSelectedInstOperands,
17374 /* 55113 */ // GIR_Coverage, 5277,
17375 /* 55113 */ GIR_EraseRootFromParent_Done,
17376 /* 55114 */ // Label 695: @55114
17377 /* 55114 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(55201), // Rule ID 5276 //
17378 /* 55119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17379 /* 55122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17380 /* 55126 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17381 /* 55130 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17382 /* 55134 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17383 /* 55138 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17384 /* 55142 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17385 /* 55146 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
17386 /* 55150 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17387 /* 55154 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17388 /* 55158 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17389 /* 55162 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17390 /* 55168 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17391 /* 55170 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17392 /* 55172 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 128:{ *:[i32] })
17393 /* 55172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17394 /* 55175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17395 /* 55177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
17396 /* 55181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vB
17397 /* 55185 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
17398 /* 55189 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
17399 /* 55199 */ GIR_RootConstrainSelectedInstOperands,
17400 /* 55200 */ // GIR_Coverage, 5276,
17401 /* 55200 */ GIR_EraseRootFromParent_Done,
17402 /* 55201 */ // Label 696: @55201
17403 /* 55201 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(55288), // Rule ID 5285 //
17404 /* 55206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17405 /* 55209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17406 /* 55213 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17407 /* 55217 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17408 /* 55221 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17409 /* 55225 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17410 /* 55229 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17411 /* 55233 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17412 /* 55237 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17413 /* 55241 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17414 /* 55245 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17415 /* 55249 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17416 /* 55255 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17417 /* 55257 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17418 /* 55259 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 144:{ *:[i32] })
17419 /* 55259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17420 /* 55262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17421 /* 55264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
17422 /* 55268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17423 /* 55272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17424 /* 55276 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(144),
17425 /* 55286 */ GIR_RootConstrainSelectedInstOperands,
17426 /* 55287 */ // GIR_Coverage, 5285,
17427 /* 55287 */ GIR_EraseRootFromParent_Done,
17428 /* 55288 */ // Label 697: @55288
17429 /* 55288 */ GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(55375), // Rule ID 3403 //
17430 /* 55293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17431 /* 55296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17432 /* 55300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17433 /* 55304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17434 /* 55308 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17435 /* 55312 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17436 /* 55316 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17437 /* 55320 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
17438 /* 55324 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17439 /* 55328 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17440 /* 55332 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17441 /* 55336 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17442 /* 55342 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17443 /* 55344 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17444 /* 55346 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 224:{ *:[i32] })
17445 /* 55346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17446 /* 55349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17447 /* 55351 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17448 /* 55355 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17449 /* 55359 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17450 /* 55363 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(224),
17451 /* 55373 */ GIR_RootConstrainSelectedInstOperands,
17452 /* 55374 */ // GIR_Coverage, 3403,
17453 /* 55374 */ GIR_EraseRootFromParent_Done,
17454 /* 55375 */ // Label 698: @55375
17455 /* 55375 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(55462), // Rule ID 3402 //
17456 /* 55380 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17457 /* 55383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17458 /* 55387 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17459 /* 55391 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17460 /* 55395 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17461 /* 55399 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17462 /* 55403 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17463 /* 55407 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
17464 /* 55411 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17465 /* 55415 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17466 /* 55419 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17467 /* 55423 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17468 /* 55429 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17469 /* 55431 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17470 /* 55433 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 128:{ *:[i32] })
17471 /* 55433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17472 /* 55436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17473 /* 55438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17474 /* 55442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17475 /* 55446 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17476 /* 55450 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
17477 /* 55460 */ GIR_RootConstrainSelectedInstOperands,
17478 /* 55461 */ // GIR_Coverage, 3402,
17479 /* 55461 */ GIR_EraseRootFromParent_Done,
17480 /* 55462 */ // Label 699: @55462
17481 /* 55462 */ GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(55549), // Rule ID 3407 //
17482 /* 55467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17483 /* 55470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17484 /* 55474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17485 /* 55478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17486 /* 55482 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17487 /* 55486 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17488 /* 55490 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17489 /* 55494 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17490 /* 55498 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17491 /* 55502 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17492 /* 55506 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17493 /* 55510 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17494 /* 55516 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17495 /* 55518 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17496 /* 55520 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 144:{ *:[i32] })
17497 /* 55520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17498 /* 55523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17499 /* 55525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17500 /* 55529 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17501 /* 55533 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17502 /* 55537 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(144),
17503 /* 55547 */ GIR_RootConstrainSelectedInstOperands,
17504 /* 55548 */ // GIR_Coverage, 3407,
17505 /* 55548 */ GIR_EraseRootFromParent_Done,
17506 /* 55549 */ // Label 700: @55549
17507 /* 55549 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(55636), // Rule ID 5274 //
17508 /* 55554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17509 /* 55557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17510 /* 55561 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17511 /* 55565 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17512 /* 55569 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17513 /* 55573 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17514 /* 55577 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
17515 /* 55581 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17516 /* 55585 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17517 /* 55589 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17518 /* 55593 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17519 /* 55597 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17520 /* 55603 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17521 /* 55605 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17522 /* 55607 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 135:{ *:[i32] })
17523 /* 55607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17524 /* 55610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17525 /* 55612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vA
17526 /* 55616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
17527 /* 55620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
17528 /* 55624 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(135),
17529 /* 55634 */ GIR_RootConstrainSelectedInstOperands,
17530 /* 55635 */ // GIR_Coverage, 5274,
17531 /* 55635 */ GIR_EraseRootFromParent_Done,
17532 /* 55636 */ // Label 701: @55636
17533 /* 55636 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(55721), // Rule ID 5268 //
17534 /* 55641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17535 /* 55644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17536 /* 55648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17537 /* 55652 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17538 /* 55656 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17539 /* 55660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17540 /* 55664 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17541 /* 55668 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
17542 /* 55672 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17543 /* 55676 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17544 /* 55680 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
17545 /* 55684 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17546 /* 55690 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17547 /* 55692 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17548 /* 55694 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 225:{ *:[i32] })
17549 /* 55694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17550 /* 55697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17551 /* 55699 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
17552 /* 55701 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17553 /* 55705 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17554 /* 55709 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(225),
17555 /* 55719 */ GIR_RootConstrainSelectedInstOperands,
17556 /* 55720 */ // GIR_Coverage, 5268,
17557 /* 55720 */ GIR_EraseRootFromParent_Done,
17558 /* 55721 */ // Label 702: @55721
17559 /* 55721 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(55808), // Rule ID 5266 //
17560 /* 55726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17561 /* 55729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17562 /* 55733 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17563 /* 55737 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17564 /* 55741 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17565 /* 55745 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17566 /* 55749 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17567 /* 55753 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
17568 /* 55757 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17569 /* 55761 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17570 /* 55765 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17571 /* 55769 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17572 /* 55775 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17573 /* 55777 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17574 /* 55779 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 225:{ *:[i32] })
17575 /* 55779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17576 /* 55782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17577 /* 55784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
17578 /* 55788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17579 /* 55792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17580 /* 55796 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(225),
17581 /* 55806 */ GIR_RootConstrainSelectedInstOperands,
17582 /* 55807 */ // GIR_Coverage, 5266,
17583 /* 55807 */ GIR_EraseRootFromParent_Done,
17584 /* 55808 */ // Label 703: @55808
17585 /* 55808 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(55893), // Rule ID 5273 //
17586 /* 55813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17587 /* 55816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17588 /* 55820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17589 /* 55824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17590 /* 55828 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17591 /* 55832 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17592 /* 55836 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17593 /* 55840 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
17594 /* 55844 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17595 /* 55848 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17596 /* 55852 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
17597 /* 55856 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17598 /* 55862 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17599 /* 55864 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17600 /* 55866 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 135:{ *:[i32] })
17601 /* 55866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17602 /* 55869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17603 /* 55871 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
17604 /* 55873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17605 /* 55877 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17606 /* 55881 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(135),
17607 /* 55891 */ GIR_RootConstrainSelectedInstOperands,
17608 /* 55892 */ // GIR_Coverage, 5273,
17609 /* 55892 */ GIR_EraseRootFromParent_Done,
17610 /* 55893 */ // Label 704: @55893
17611 /* 55893 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(55980), // Rule ID 5271 //
17612 /* 55898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17613 /* 55901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17614 /* 55905 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17615 /* 55909 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17616 /* 55913 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17617 /* 55917 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17618 /* 55921 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17619 /* 55925 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
17620 /* 55929 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17621 /* 55933 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17622 /* 55937 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17623 /* 55941 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17624 /* 55947 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17625 /* 55949 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17626 /* 55951 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 135:{ *:[i32] })
17627 /* 55951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17628 /* 55954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17629 /* 55956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vA
17630 /* 55960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17631 /* 55964 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17632 /* 55968 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(135),
17633 /* 55978 */ GIR_RootConstrainSelectedInstOperands,
17634 /* 55979 */ // GIR_Coverage, 5271,
17635 /* 55979 */ GIR_EraseRootFromParent_Done,
17636 /* 55980 */ // Label 705: @55980
17637 /* 55980 */ GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(56067), // Rule ID 3400 //
17638 /* 55985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17639 /* 55988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17640 /* 55992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17641 /* 55996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17642 /* 56000 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17643 /* 56004 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17644 /* 56008 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17645 /* 56012 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
17646 /* 56016 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17647 /* 56020 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17648 /* 56024 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17649 /* 56028 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17650 /* 56034 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17651 /* 56036 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17652 /* 56038 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 225:{ *:[i32] })
17653 /* 56038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17654 /* 56041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17655 /* 56043 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17656 /* 56047 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17657 /* 56051 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17658 /* 56055 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(225),
17659 /* 56065 */ GIR_RootConstrainSelectedInstOperands,
17660 /* 56066 */ // GIR_Coverage, 3400,
17661 /* 56066 */ GIR_EraseRootFromParent_Done,
17662 /* 56067 */ // Label 706: @56067
17663 /* 56067 */ GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(56154), // Rule ID 3401 //
17664 /* 56072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17665 /* 56075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17666 /* 56079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17667 /* 56083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17668 /* 56087 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17669 /* 56091 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17670 /* 56095 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17671 /* 56099 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
17672 /* 56103 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17673 /* 56107 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17674 /* 56111 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17675 /* 56115 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17676 /* 56121 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17677 /* 56123 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17678 /* 56125 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)), immAllOnesV:{ *:[v4i32] }) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 135:{ *:[i32] })
17679 /* 56125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17680 /* 56128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17681 /* 56130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17682 /* 56134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17683 /* 56138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17684 /* 56142 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(135),
17685 /* 56152 */ GIR_RootConstrainSelectedInstOperands,
17686 /* 56153 */ // GIR_Coverage, 3401,
17687 /* 56153 */ GIR_EraseRootFromParent_Done,
17688 /* 56154 */ // Label 707: @56154
17689 /* 56154 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(56241), // Rule ID 5267 //
17690 /* 56159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17691 /* 56162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17692 /* 56166 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17693 /* 56170 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17694 /* 56174 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17695 /* 56178 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17696 /* 56182 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17697 /* 56186 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17698 /* 56192 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
17699 /* 56194 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17700 /* 56198 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
17701 /* 56202 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
17702 /* 56206 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
17703 /* 56210 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17704 /* 56212 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 225:{ *:[i32] })
17705 /* 56212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17706 /* 56215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17707 /* 56217 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17708 /* 56221 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
17709 /* 56225 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
17710 /* 56229 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(225),
17711 /* 56239 */ GIR_RootConstrainSelectedInstOperands,
17712 /* 56240 */ // GIR_Coverage, 5267,
17713 /* 56240 */ GIR_EraseRootFromParent_Done,
17714 /* 56241 */ // Label 708: @56241
17715 /* 56241 */ GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(56328), // Rule ID 5272 //
17716 /* 56246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17717 /* 56249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17718 /* 56253 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17719 /* 56257 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17720 /* 56261 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17721 /* 56265 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17722 /* 56269 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17723 /* 56273 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17724 /* 56279 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
17725 /* 56281 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
17726 /* 56285 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
17727 /* 56289 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
17728 /* 56293 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
17729 /* 56297 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17730 /* 56299 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }), (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 135:{ *:[i32] })
17731 /* 56299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17732 /* 56302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17733 /* 56304 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17734 /* 56308 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // vB
17735 /* 56312 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // vC
17736 /* 56316 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(135),
17737 /* 56326 */ GIR_RootConstrainSelectedInstOperands,
17738 /* 56327 */ // GIR_Coverage, 5272,
17739 /* 56327 */ GIR_EraseRootFromParent_Done,
17740 /* 56328 */ // Label 709: @56328
17741 /* 56328 */ GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(56413), // Rule ID 5270 //
17742 /* 56333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17743 /* 56336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17744 /* 56340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17745 /* 56344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17746 /* 56348 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17747 /* 56352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17748 /* 56356 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17749 /* 56360 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
17750 /* 56364 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17751 /* 56368 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17752 /* 56372 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
17753 /* 56376 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17754 /* 56382 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17755 /* 56384 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17756 /* 56386 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 225:{ *:[i32] })
17757 /* 56386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17758 /* 56389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17759 /* 56391 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
17760 /* 56393 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17761 /* 56397 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17762 /* 56401 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(225),
17763 /* 56411 */ GIR_RootConstrainSelectedInstOperands,
17764 /* 56412 */ // GIR_Coverage, 5270,
17765 /* 56412 */ GIR_EraseRootFromParent_Done,
17766 /* 56413 */ // Label 710: @56413
17767 /* 56413 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(56498), // Rule ID 5275 //
17768 /* 56418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17769 /* 56421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17770 /* 56425 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17771 /* 56429 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17772 /* 56433 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17773 /* 56437 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17774 /* 56441 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17775 /* 56445 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
17776 /* 56449 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17777 /* 56453 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17778 /* 56457 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
17779 /* 56461 */ GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17780 /* 56467 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17781 /* 56469 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17782 /* 56471 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), immAllOnesV:{ *:[v4i32] })) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 135:{ *:[i32] })
17783 /* 56471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17784 /* 56474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17785 /* 56476 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
17786 /* 56478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vB
17787 /* 56482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // vC
17788 /* 56486 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(135),
17789 /* 56496 */ GIR_RootConstrainSelectedInstOperands,
17790 /* 56497 */ // GIR_Coverage, 5275,
17791 /* 56497 */ GIR_EraseRootFromParent_Done,
17792 /* 56498 */ // Label 711: @56498
17793 /* 56498 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(56555), // Rule ID 944 //
17794 /* 56503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
17795 /* 56506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17796 /* 56510 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17797 /* 56514 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17798 /* 56518 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17799 /* 56522 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17800 /* 56526 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
17801 /* 56530 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17802 /* 56536 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
17803 /* 56538 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17804 /* 56540 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLNAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
17805 /* 56540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNAND),
17806 /* 56543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17807 /* 56545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
17808 /* 56549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
17809 /* 56553 */ GIR_RootConstrainSelectedInstOperands,
17810 /* 56554 */ // GIR_Coverage, 944,
17811 /* 56554 */ GIR_EraseRootFromParent_Done,
17812 /* 56555 */ // Label 712: @56555
17813 /* 56555 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(56612), // Rule ID 934 //
17814 /* 56560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
17815 /* 56563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17816 /* 56567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17817 /* 56571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17818 /* 56575 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17819 /* 56579 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17820 /* 56583 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
17821 /* 56587 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17822 /* 56593 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
17823 /* 56595 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17824 /* 56597 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLNOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
17825 /* 56597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNOR),
17826 /* 56600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17827 /* 56602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
17828 /* 56606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
17829 /* 56610 */ GIR_RootConstrainSelectedInstOperands,
17830 /* 56611 */ // GIR_Coverage, 934,
17831 /* 56611 */ GIR_EraseRootFromParent_Done,
17832 /* 56612 */ // Label 713: @56612
17833 /* 56612 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(56667), // Rule ID 4940 //
17834 /* 56617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
17835 /* 56620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17836 /* 56624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17837 /* 56628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17838 /* 56632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17839 /* 56636 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17840 /* 56640 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17841 /* 56644 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17842 /* 56650 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
17843 /* 56652 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17844 /* 56654 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XB) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
17845 /* 56654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV),
17846 /* 56657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17847 /* 56659 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
17848 /* 56663 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
17849 /* 56665 */ GIR_RootConstrainSelectedInstOperands,
17850 /* 56666 */ // GIR_Coverage, 4940,
17851 /* 56666 */ GIR_EraseRootFromParent_Done,
17852 /* 56667 */ // Label 714: @56667
17853 /* 56667 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(56724), // Rule ID 943 //
17854 /* 56672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
17855 /* 56675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17856 /* 56679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17857 /* 56683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17858 /* 56687 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17859 /* 56691 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17860 /* 56695 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
17861 /* 56699 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17862 /* 56705 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
17863 /* 56707 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17864 /* 56709 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
17865 /* 56709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV),
17866 /* 56712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17867 /* 56714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
17868 /* 56718 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
17869 /* 56722 */ GIR_RootConstrainSelectedInstOperands,
17870 /* 56723 */ // GIR_Coverage, 943,
17871 /* 56723 */ GIR_EraseRootFromParent_Done,
17872 /* 56724 */ // Label 715: @56724
17873 /* 56724 */ GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(56779), // Rule ID 4941 //
17874 /* 56729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
17875 /* 56732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17876 /* 56736 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17877 /* 56740 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17878 /* 56744 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17879 /* 56748 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17880 /* 56752 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17881 /* 56756 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17882 /* 56762 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
17883 /* 56764 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17884 /* 56766 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, immAllOnesV:{ *:[v4i32] })) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
17885 /* 56766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV),
17886 /* 56769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17887 /* 56771 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
17888 /* 56775 */ GIR_RootToRootCopy, /*OpIdx*/1, // XB
17889 /* 56777 */ GIR_RootConstrainSelectedInstOperands,
17890 /* 56778 */ // GIR_Coverage, 4941,
17891 /* 56778 */ GIR_EraseRootFromParent_Done,
17892 /* 56779 */ // Label 716: @56779
17893 /* 56779 */ GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(56816), // Rule ID 1587 //
17894 /* 56784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
17895 /* 56787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17896 /* 56791 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17897 /* 56795 */ GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17898 /* 56801 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17899 /* 56803 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17900 /* 56805 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, immAllOnesV:{ *:[v4i32] }) => (XXLNOR:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$A)
17901 /* 56805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNOR),
17902 /* 56808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17903 /* 56810 */ GIR_RootToRootCopy, /*OpIdx*/1, // A
17904 /* 56812 */ GIR_RootToRootCopy, /*OpIdx*/1, // A
17905 /* 56814 */ GIR_RootConstrainSelectedInstOperands,
17906 /* 56815 */ // GIR_Coverage, 1587,
17907 /* 56815 */ GIR_EraseRootFromParent_Done,
17908 /* 56816 */ // Label 717: @56816
17909 /* 56816 */ GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(56866), // Rule ID 5297 //
17910 /* 56821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17911 /* 56824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17912 /* 56828 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17913 /* 56832 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17914 /* 56836 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17915 /* 56840 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17916 /* 56844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17917 /* 56846 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 30:{ *:[i32] })
17918 /* 56846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17919 /* 56849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17920 /* 56851 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
17921 /* 56853 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
17922 /* 56857 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
17923 /* 56861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/30,
17924 /* 56864 */ GIR_RootConstrainSelectedInstOperands,
17925 /* 56865 */ // GIR_Coverage, 5297,
17926 /* 56865 */ GIR_EraseRootFromParent_Done,
17927 /* 56866 */ // Label 718: @56866
17928 /* 56866 */ GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(56916), // Rule ID 5298 //
17929 /* 56871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17930 /* 56874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17931 /* 56878 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17932 /* 56882 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17933 /* 56886 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17934 /* 56890 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17935 /* 56894 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17936 /* 56896 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC), v4i32:{ *:[v4i32] }:$vA) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 120:{ *:[i32] })
17937 /* 56896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17938 /* 56899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17939 /* 56901 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
17940 /* 56903 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
17941 /* 56907 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
17942 /* 56911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/120,
17943 /* 56914 */ GIR_RootConstrainSelectedInstOperands,
17944 /* 56915 */ // GIR_Coverage, 5298,
17945 /* 56915 */ GIR_EraseRootFromParent_Done,
17946 /* 56916 */ // Label 719: @56916
17947 /* 56916 */ GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(56966), // Rule ID 5296 //
17948 /* 56921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17949 /* 56924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17950 /* 56928 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17951 /* 56932 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17952 /* 56936 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17953 /* 56940 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17954 /* 56944 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17955 /* 56946 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB), v4i32:{ *:[v4i32] }:$vC) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 105:{ *:[i32] })
17956 /* 56946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17957 /* 56949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17958 /* 56951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vA
17959 /* 56955 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vB
17960 /* 56959 */ GIR_RootToRootCopy, /*OpIdx*/2, // vC
17961 /* 56961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/105,
17962 /* 56964 */ GIR_RootConstrainSelectedInstOperands,
17963 /* 56965 */ // GIR_Coverage, 5296,
17964 /* 56965 */ GIR_EraseRootFromParent_Done,
17965 /* 56966 */ // Label 720: @56966
17966 /* 56966 */ GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(57016), // Rule ID 3415 //
17967 /* 56971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17968 /* 56974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17969 /* 56978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17970 /* 56982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17971 /* 56986 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17972 /* 56990 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17973 /* 56994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17974 /* 56996 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 30:{ *:[i32] })
17975 /* 56996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17976 /* 56999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17977 /* 57001 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
17978 /* 57003 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
17979 /* 57007 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
17980 /* 57011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/30,
17981 /* 57014 */ GIR_RootConstrainSelectedInstOperands,
17982 /* 57015 */ // GIR_Coverage, 3415,
17983 /* 57015 */ GIR_EraseRootFromParent_Done,
17984 /* 57016 */ // Label 721: @57016
17985 /* 57016 */ GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(57066), // Rule ID 3416 //
17986 /* 57021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
17987 /* 57024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
17988 /* 57028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17989 /* 57032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
17990 /* 57036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17991 /* 57040 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17992 /* 57044 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17993 /* 57046 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 120:{ *:[i32] })
17994 /* 57046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
17995 /* 57049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
17996 /* 57051 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
17997 /* 57053 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
17998 /* 57057 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
17999 /* 57061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/120,
18000 /* 57064 */ GIR_RootConstrainSelectedInstOperands,
18001 /* 57065 */ // GIR_Coverage, 3416,
18002 /* 57065 */ GIR_EraseRootFromParent_Done,
18003 /* 57066 */ // Label 722: @57066
18004 /* 57066 */ GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(57116), // Rule ID 3414 //
18005 /* 57071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
18006 /* 57074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18007 /* 57078 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18008 /* 57082 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
18009 /* 57086 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18010 /* 57090 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18011 /* 57094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18012 /* 57096 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC)) => (XXEVAL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vC, 105:{ *:[i32] })
18013 /* 57096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
18014 /* 57099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18015 /* 57101 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
18016 /* 57103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vB
18017 /* 57107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // vC
18018 /* 57111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/105,
18019 /* 57114 */ GIR_RootConstrainSelectedInstOperands,
18020 /* 57115 */ // GIR_Coverage, 3414,
18021 /* 57115 */ GIR_EraseRootFromParent_Done,
18022 /* 57116 */ // Label 723: @57116
18023 /* 57116 */ GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(57135), // Rule ID 936 //
18024 /* 57121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18025 /* 57124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18026 /* 57128 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLXOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
18027 /* 57128 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLXOR),
18028 /* 57133 */ GIR_RootConstrainSelectedInstOperands,
18029 /* 57134 */ // GIR_Coverage, 936,
18030 /* 57134 */ GIR_Done,
18031 /* 57135 */ // Label 724: @57135
18032 /* 57135 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(57192), // Rule ID 488 //
18033 /* 57140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
18034 /* 57143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18035 /* 57147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18036 /* 57151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18037 /* 57155 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18038 /* 57159 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18039 /* 57163 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
18040 /* 57167 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18041 /* 57173 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
18042 /* 57175 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
18043 /* 57177 */ // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VNAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
18044 /* 57177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNAND),
18045 /* 57180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
18046 /* 57182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA
18047 /* 57186 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB
18048 /* 57190 */ GIR_RootConstrainSelectedInstOperands,
18049 /* 57191 */ // GIR_Coverage, 488,
18050 /* 57191 */ GIR_EraseRootFromParent_Done,
18051 /* 57192 */ // Label 725: @57192
18052 /* 57192 */ GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(57249), // Rule ID 385 //
18053 /* 57197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18054 /* 57200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18055 /* 57204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18056 /* 57208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
18057 /* 57212 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18058 /* 57216 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18059 /* 57220 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
18060 /* 57224 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18061 /* 57230 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
18062 /* 57232 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
18063 /* 57234 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VNOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
18064 /* 57234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNOR),
18065 /* 57237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
18066 /* 57239 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA
18067 /* 57243 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB
18068 /* 57247 */ GIR_RootConstrainSelectedInstOperands,
18069 /* 57248 */ // GIR_Coverage, 385,
18070 /* 57248 */ GIR_EraseRootFromParent_Done,
18071 /* 57249 */ // Label 726: @57249
18072 /* 57249 */ GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(57306), // Rule ID 1383 //
18073 /* 57254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18074 /* 57257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18075 /* 57261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18076 /* 57265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
18077 /* 57269 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18078 /* 57273 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18079 /* 57277 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
18080 /* 57281 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18081 /* 57287 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
18082 /* 57289 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
18083 /* 57291 */ // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, v4i32:{ *:[v4i32] }:$B), immAllOnesV:{ *:[v4i32] }) => (VNOR:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B)
18084 /* 57291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNOR),
18085 /* 57294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
18086 /* 57296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
18087 /* 57300 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // B
18088 /* 57304 */ GIR_RootConstrainSelectedInstOperands,
18089 /* 57305 */ // GIR_Coverage, 1383,
18090 /* 57305 */ GIR_EraseRootFromParent_Done,
18091 /* 57306 */ // Label 727: @57306
18092 /* 57306 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(57361), // Rule ID 4928 //
18093 /* 57311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
18094 /* 57314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18095 /* 57318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18096 /* 57322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
18097 /* 57326 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18098 /* 57330 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18099 /* 57334 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
18100 /* 57338 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18101 /* 57344 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
18102 /* 57346 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
18103 /* 57348 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VB) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
18104 /* 57348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV),
18105 /* 57351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
18106 /* 57353 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA
18107 /* 57357 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
18108 /* 57359 */ GIR_RootConstrainSelectedInstOperands,
18109 /* 57360 */ // GIR_Coverage, 4928,
18110 /* 57360 */ GIR_EraseRootFromParent_Done,
18111 /* 57361 */ // Label 728: @57361
18112 /* 57361 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(57418), // Rule ID 487 //
18113 /* 57366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
18114 /* 57369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18115 /* 57373 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18116 /* 57377 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
18117 /* 57381 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18118 /* 57385 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18119 /* 57389 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
18120 /* 57393 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18121 /* 57399 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
18122 /* 57401 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
18123 /* 57403 */ // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
18124 /* 57403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV),
18125 /* 57406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
18126 /* 57408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA
18127 /* 57412 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB
18128 /* 57416 */ GIR_RootConstrainSelectedInstOperands,
18129 /* 57417 */ // GIR_Coverage, 487,
18130 /* 57417 */ GIR_EraseRootFromParent_Done,
18131 /* 57418 */ // Label 729: @57418
18132 /* 57418 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(57473), // Rule ID 4929 //
18133 /* 57423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
18134 /* 57426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18135 /* 57430 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18136 /* 57434 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
18137 /* 57438 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18138 /* 57442 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18139 /* 57446 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
18140 /* 57450 */ GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18141 /* 57456 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
18142 /* 57458 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
18143 /* 57460 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, immAllOnesV:{ *:[v4i32] })) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
18144 /* 57460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV),
18145 /* 57463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
18146 /* 57465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA
18147 /* 57469 */ GIR_RootToRootCopy, /*OpIdx*/1, // VB
18148 /* 57471 */ GIR_RootConstrainSelectedInstOperands,
18149 /* 57472 */ // GIR_Coverage, 4929,
18150 /* 57472 */ GIR_EraseRootFromParent_Done,
18151 /* 57473 */ // Label 730: @57473
18152 /* 57473 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(57510), // Rule ID 1382 //
18153 /* 57478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18154 /* 57481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18155 /* 57485 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18156 /* 57489 */ GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18157 /* 57495 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
18158 /* 57497 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18159 /* 57499 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }) => (VNOR:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vA)
18160 /* 57499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNOR),
18161 /* 57502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
18162 /* 57504 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
18163 /* 57506 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
18164 /* 57508 */ GIR_RootConstrainSelectedInstOperands,
18165 /* 57509 */ // GIR_Coverage, 1382,
18166 /* 57509 */ GIR_EraseRootFromParent_Done,
18167 /* 57510 */ // Label 731: @57510
18168 /* 57510 */ GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(57529), // Rule ID 387 //
18169 /* 57515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18170 /* 57518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18171 /* 57522 */ // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VXOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
18172 /* 57522 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VXOR),
18173 /* 57527 */ GIR_RootConstrainSelectedInstOperands,
18174 /* 57528 */ // GIR_Coverage, 387,
18175 /* 57528 */ GIR_Done,
18176 /* 57529 */ // Label 732: @57529
18177 /* 57529 */ GIM_Reject,
18178 /* 57530 */ // Label 687: @57530
18179 /* 57530 */ GIM_Reject,
18180 /* 57531 */ // Label 597: @57531
18181 /* 57531 */ GIM_Reject,
18182 /* 57532 */ // Label 10: @57532
18183 /* 57532 */ GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(57832),
18184 /* 57537 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
18185 /* 57540 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
18186 /* 57543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
18187 /* 57546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
18188 /* 57549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18189 /* 57553 */ GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(57675), // Rule ID 2131 //
18190 /* 57558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector),
18191 /* 57561 */ // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$A, i64:{ *:[i64] }:$B) => (XXPERMDI:{ *:[v2i64] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$A), sub_64:{ *:[i32] }), (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$B), sub_64:{ *:[i32] }), 0:{ *:[i32] })
18192 /* 57561 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
18193 /* 57564 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::MTVSRD),
18194 /* 57568 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18195 /* 57573 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // B
18196 /* 57577 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
18197 /* 57579 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
18198 /* 57582 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18199 /* 57586 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18200 /* 57591 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
18201 /* 57594 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
18202 /* 57597 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
18203 /* 57600 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18204 /* 57605 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID),
18205 /* 57610 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
18206 /* 57613 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRD),
18207 /* 57617 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18208 /* 57622 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
18209 /* 57626 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18210 /* 57628 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18211 /* 57631 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18212 /* 57635 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18213 /* 57640 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
18214 /* 57643 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18215 /* 57646 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
18216 /* 57649 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18217 /* 57654 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID),
18218 /* 57659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI),
18219 /* 57662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18220 /* 57664 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18221 /* 57667 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
18222 /* 57670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18223 /* 57673 */ GIR_RootConstrainSelectedInstOperands,
18224 /* 57674 */ // GIR_Coverage, 2131,
18225 /* 57674 */ GIR_EraseRootFromParent_Done,
18226 /* 57675 */ // Label 734: @57675
18227 /* 57675 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(57797), // Rule ID 2134 //
18228 /* 57680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector),
18229 /* 57683 */ // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$A, i64:{ *:[i64] }:$B) => (XXPERMDI:{ *:[v2i64] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$B), sub_64:{ *:[i32] }), (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$A), sub_64:{ *:[i32] }), 0:{ *:[i32] })
18230 /* 57683 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
18231 /* 57686 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::MTVSRD),
18232 /* 57690 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18233 /* 57695 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // A
18234 /* 57699 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
18235 /* 57701 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
18236 /* 57704 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18237 /* 57708 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18238 /* 57713 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
18239 /* 57716 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
18240 /* 57719 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
18241 /* 57722 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18242 /* 57727 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID),
18243 /* 57732 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
18244 /* 57735 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRD),
18245 /* 57739 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18246 /* 57744 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // B
18247 /* 57748 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18248 /* 57750 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18249 /* 57753 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18250 /* 57757 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18251 /* 57762 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
18252 /* 57765 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18253 /* 57768 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
18254 /* 57771 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18255 /* 57776 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID),
18256 /* 57781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI),
18257 /* 57784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18258 /* 57786 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18259 /* 57789 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
18260 /* 57792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18261 /* 57795 */ GIR_RootConstrainSelectedInstOperands,
18262 /* 57796 */ // GIR_Coverage, 2134,
18263 /* 57796 */ GIR_EraseRootFromParent_Done,
18264 /* 57797 */ // Label 735: @57797
18265 /* 57797 */ GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(57812), // Rule ID 2879 //
18266 /* 57802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsISA3_0_IsPPC64),
18267 /* 57805 */ // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$rB, i64:{ *:[i64] }:$rA) => (MTVSRDD:{ *:[v2i64] } ?:{ *:[i64] }:$rB, ?:{ *:[i64] }:$rA)
18268 /* 57805 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MTVSRDD),
18269 /* 57810 */ GIR_RootConstrainSelectedInstOperands,
18270 /* 57811 */ // GIR_Coverage, 2879,
18271 /* 57811 */ GIR_Done,
18272 /* 57812 */ // Label 736: @57812
18273 /* 57812 */ GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(57831), // Rule ID 2883 //
18274 /* 57817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsISA3_0_IsLittleEndian),
18275 /* 57820 */ // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (MTVSRDD:{ *:[v2i64] } ?:{ *:[i64] }:$rB, ?:{ *:[i64] }:$rA)
18276 /* 57820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRDD),
18277 /* 57823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18278 /* 57825 */ GIR_RootToRootCopy, /*OpIdx*/2, // rB
18279 /* 57827 */ GIR_RootToRootCopy, /*OpIdx*/1, // rA
18280 /* 57829 */ GIR_RootConstrainSelectedInstOperands,
18281 /* 57830 */ // GIR_Coverage, 2883,
18282 /* 57830 */ GIR_EraseRootFromParent_Done,
18283 /* 57831 */ // Label 737: @57831
18284 /* 57831 */ GIM_Reject,
18285 /* 57832 */ // Label 733: @57832
18286 /* 57832 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(58357),
18287 /* 57837 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
18288 /* 57840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18289 /* 57843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18290 /* 57846 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(57897), // Rule ID 2045 //
18291 /* 57851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
18292 /* 57854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18293 /* 57858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18294 /* 57862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18295 /* 57866 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt5NonZero),
18296 /* 57870 */ // MIs[1] Operand 1
18297 /* 57870 */ // No operand predicates
18298 /* 57870 */ // MIs[0] A
18299 /* 57870 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
18300 /* 57875 */ // MIs[0] A
18301 /* 57875 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
18302 /* 57880 */ // MIs[0] A
18303 /* 57880 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
18304 /* 57885 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18305 /* 57887 */ // (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A) => (VSPLTISW:{ *:[v4i32] } (imm:{ *:[i32] }):$A)
18306 /* 57887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSPLTISW),
18307 /* 57890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
18308 /* 57892 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // A
18309 /* 57895 */ GIR_RootConstrainSelectedInstOperands,
18310 /* 57896 */ // GIR_Coverage, 2045,
18311 /* 57896 */ GIR_EraseRootFromParent_Done,
18312 /* 57897 */ // Label 739: @57897
18313 /* 57897 */ GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(57948), // Rule ID 3382 //
18314 /* 57902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
18315 /* 57905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18316 /* 57909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18317 /* 57913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18318 /* 57917 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32immNonAllOneNonZero),
18319 /* 57921 */ // MIs[1] Operand 1
18320 /* 57921 */ // No operand predicates
18321 /* 57921 */ // MIs[0] A
18322 /* 57921 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
18323 /* 57926 */ // MIs[0] A
18324 /* 57926 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
18325 /* 57931 */ // MIs[0] A
18326 /* 57931 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
18327 /* 57936 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18328 /* 57938 */ // (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A) => (XXSPLTIW:{ *:[v4i32] } (imm:{ *:[i32] }):$A)
18329 /* 57938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTIW),
18330 /* 57941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18331 /* 57943 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // A
18332 /* 57946 */ GIR_RootConstrainSelectedInstOperands,
18333 /* 57947 */ // GIR_Coverage, 3382,
18334 /* 57947 */ GIR_EraseRootFromParent_Done,
18335 /* 57948 */ // Label 740: @57948
18336 /* 57948 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(58084), // Rule ID 1735 //
18337 /* 57953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18338 /* 57956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18339 /* 57959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18340 /* 57962 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
18341 /* 57965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18342 /* 57969 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18343 /* 57973 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
18344 /* 57977 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
18345 /* 57981 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
18346 /* 57985 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
18347 /* 57989 */ // MIs[2] A
18348 /* 57989 */ GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
18349 /* 57994 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
18350 /* 57998 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
18351 /* 58002 */ // MIs[3] A
18352 /* 58002 */ GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
18353 /* 58007 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/4, // MIs[4]
18354 /* 58011 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
18355 /* 58015 */ // MIs[4] A
18356 /* 58015 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
18357 /* 58020 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
18358 /* 58022 */ // (build_vector:{ *:[v4f32] } (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A)) => (XXSPLTW:{ *:[v4f32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (XSCVDPSP:{ *:[f64] } f64:{ *:[f64] }:$A), sub_64:{ *:[i32] }), 0:{ *:[i32] })
18359 /* 58022 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
18360 /* 58025 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSP),
18361 /* 58029 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18362 /* 58034 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // A
18363 /* 58038 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18364 /* 58040 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18365 /* 58043 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18366 /* 58047 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18367 /* 58052 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
18368 /* 58055 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18369 /* 58058 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
18370 /* 58061 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18371 /* 58066 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID),
18372 /* 58071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW),
18373 /* 58074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18374 /* 58076 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18375 /* 58079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18376 /* 58082 */ GIR_RootConstrainSelectedInstOperands,
18377 /* 58083 */ // GIR_Coverage, 1735,
18378 /* 58083 */ GIR_EraseRootFromParent_Done,
18379 /* 58084 */ // Label 741: @58084
18380 /* 58084 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(58142), // Rule ID 1736 //
18381 /* 58089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18382 /* 58092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18383 /* 58096 */ // MIs[0] A
18384 /* 58096 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
18385 /* 58101 */ // MIs[0] A
18386 /* 58101 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
18387 /* 58106 */ // MIs[0] A
18388 /* 58106 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
18389 /* 58111 */ // (build_vector:{ *:[v4f32] } f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A) => (XXSPLTW:{ *:[v4f32] } (XSCVDPSPN:{ *:[v4f32] } ?:{ *:[f32] }:$A), 0:{ *:[i32] })
18390 /* 58111 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18391 /* 58114 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSPN),
18392 /* 58118 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18393 /* 58123 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // A
18394 /* 58127 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18395 /* 58129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW),
18396 /* 58132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18397 /* 58134 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18398 /* 58137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18399 /* 58140 */ GIR_RootConstrainSelectedInstOperands,
18400 /* 58141 */ // GIR_Coverage, 1736,
18401 /* 58141 */ GIR_EraseRootFromParent_Done,
18402 /* 58142 */ // Label 742: @58142
18403 /* 58142 */ GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(58231), // Rule ID 2133 //
18404 /* 58147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector),
18405 /* 58150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18406 /* 58154 */ // MIs[0] A
18407 /* 58154 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
18408 /* 58159 */ // MIs[0] A
18409 /* 58159 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
18410 /* 58164 */ // MIs[0] A
18411 /* 58164 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
18412 /* 58169 */ // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (XXSPLTW:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRWZ:{ *:[f64] } ?:{ *:[i32] }:$A), sub_64:{ *:[i32] }), 1:{ *:[i32] })
18413 /* 58169 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
18414 /* 58172 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRWZ),
18415 /* 58176 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18416 /* 58181 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
18417 /* 58185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18418 /* 58187 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18419 /* 58190 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18420 /* 58194 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18421 /* 58199 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
18422 /* 58202 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18423 /* 58205 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
18424 /* 58208 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18425 /* 58213 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID),
18426 /* 58218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW),
18427 /* 58221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18428 /* 58223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18429 /* 58226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18430 /* 58229 */ GIR_RootConstrainSelectedInstOperands,
18431 /* 58230 */ // GIR_Coverage, 2133,
18432 /* 58230 */ GIR_EraseRootFromParent_Done,
18433 /* 58231 */ // Label 743: @58231
18434 /* 58231 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(58320), // Rule ID 2136 //
18435 /* 58236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector),
18436 /* 58239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18437 /* 58243 */ // MIs[0] A
18438 /* 58243 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
18439 /* 58248 */ // MIs[0] A
18440 /* 58248 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
18441 /* 58253 */ // MIs[0] A
18442 /* 58253 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
18443 /* 58258 */ // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (XXSPLTW:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRWZ:{ *:[f64] } ?:{ *:[i32] }:$A), sub_64:{ *:[i32] }), 1:{ *:[i32] })
18444 /* 58258 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
18445 /* 58261 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRWZ),
18446 /* 58265 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18447 /* 58270 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
18448 /* 58274 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18449 /* 58276 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18450 /* 58279 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18451 /* 58283 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18452 /* 58288 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
18453 /* 58291 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18454 /* 58294 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
18455 /* 58297 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18456 /* 58302 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID),
18457 /* 58307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW),
18458 /* 58310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18459 /* 58312 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18460 /* 58315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18461 /* 58318 */ GIR_RootConstrainSelectedInstOperands,
18462 /* 58319 */ // GIR_Coverage, 2136,
18463 /* 58319 */ GIR_EraseRootFromParent_Done,
18464 /* 58320 */ // Label 744: @58320
18465 /* 58320 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(58356), // Rule ID 2269 //
18466 /* 58325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
18467 /* 58328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18468 /* 58332 */ // MIs[0] A
18469 /* 58332 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
18470 /* 58337 */ // MIs[0] A
18471 /* 58337 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
18472 /* 58342 */ // MIs[0] A
18473 /* 58342 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
18474 /* 58347 */ // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (MTVSRWS:{ *:[v4i32] } ?:{ *:[i32] }:$A)
18475 /* 58347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRWS),
18476 /* 58350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18477 /* 58352 */ GIR_RootToRootCopy, /*OpIdx*/1, // A
18478 /* 58354 */ GIR_RootConstrainSelectedInstOperands,
18479 /* 58355 */ // GIR_Coverage, 2269,
18480 /* 58355 */ GIR_EraseRootFromParent_Done,
18481 /* 58356 */ // Label 745: @58356
18482 /* 58356 */ GIM_Reject,
18483 /* 58357 */ // Label 738: @58357
18484 /* 58357 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(58498), // Rule ID 2270 //
18485 /* 58362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
18486 /* 58365 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
18487 /* 58368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
18488 /* 58371 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18489 /* 58374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18490 /* 58378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18491 /* 58382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18492 /* 58386 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immNonAllOneAnyExt8),
18493 /* 58390 */ // MIs[1] Operand 1
18494 /* 58390 */ // No operand predicates
18495 /* 58390 */ // MIs[0] A
18496 /* 58390 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
18497 /* 58395 */ // MIs[0] A
18498 /* 58395 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
18499 /* 58400 */ // MIs[0] A
18500 /* 58400 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
18501 /* 58405 */ // MIs[0] A
18502 /* 58405 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
18503 /* 58410 */ // MIs[0] A
18504 /* 58410 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
18505 /* 58415 */ // MIs[0] A
18506 /* 58415 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
18507 /* 58420 */ // MIs[0] A
18508 /* 58420 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
18509 /* 58425 */ // MIs[0] A
18510 /* 58425 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
18511 /* 58430 */ // MIs[0] A
18512 /* 58430 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
18513 /* 58435 */ // MIs[0] A
18514 /* 58435 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
18515 /* 58440 */ // MIs[0] A
18516 /* 58440 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
18517 /* 58445 */ // MIs[0] A
18518 /* 58445 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
18519 /* 58450 */ // MIs[0] A
18520 /* 58450 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
18521 /* 58455 */ // MIs[0] A
18522 /* 58455 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
18523 /* 58460 */ // MIs[0] A
18524 /* 58460 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
18525 /* 58465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18526 /* 58467 */ // (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXSPLTIB:{ *:[v4i32] } (imm:{ *:[i32] }):$A), VSRC:{ *:[i32] })
18527 /* 58467 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18528 /* 58470 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSPLTIB),
18529 /* 58474 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18530 /* 58479 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // A
18531 /* 58482 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18532 /* 58484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18533 /* 58487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18534 /* 58489 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18535 /* 58492 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18536 /* 58497 */ // GIR_Coverage, 2270,
18537 /* 58497 */ GIR_EraseRootFromParent_Done,
18538 /* 58498 */ // Label 746: @58498
18539 /* 58498 */ GIM_Reject,
18540 /* 58499 */ // Label 11: @58499
18541 /* 58499 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 754*/ GIMT_Encode4(60775),
18542 /* 58510 */ /*GILLT_s32*//*Label 747*/ GIMT_Encode4(58538),
18543 /* 58514 */ /*GILLT_s64*//*Label 748*/ GIMT_Encode4(58611),
18544 /* 58518 */ /*GILLT_s128*//*Label 749*/ GIMT_Encode4(58659),
18545 /* 58522 */ /*GILLT_v2s64*//*Label 750*/ GIMT_Encode4(59063),
18546 /* 58526 */ /*GILLT_v4s32*//*Label 751*/ GIMT_Encode4(59625),
18547 /* 58530 */ /*GILLT_v8s16*//*Label 752*/ GIMT_Encode4(60176),
18548 /* 58534 */ /*GILLT_v16s8*//*Label 753*/ GIMT_Encode4(60504),
18549 /* 58538 */ // Label 747: @58538
18550 /* 58538 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(58610), // Rule ID 2029 //
18551 /* 58543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
18552 /* 58546 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18553 /* 58549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
18554 /* 58553 */ // (bitconvert:{ *:[i32] } f32:{ *:[f32] }:$A) => (MFVSRWZ:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f64] } (XSCVDPSPN:{ *:[v4i32] } ?:{ *:[f32] }:$A), sub_64:{ *:[i32] }))
18555 /* 58553 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
18556 /* 58556 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSPN),
18557 /* 58560 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18558 /* 58565 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
18559 /* 58569 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18560 /* 58571 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18561 /* 58574 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18562 /* 58578 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18563 /* 58583 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_64),
18564 /* 58590 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
18565 /* 58595 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::VSRCRegClassID),
18566 /* 58600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ),
18567 /* 58603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
18568 /* 58605 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18569 /* 58608 */ GIR_RootConstrainSelectedInstOperands,
18570 /* 58609 */ // GIR_Coverage, 2029,
18571 /* 58609 */ GIR_EraseRootFromParent_Done,
18572 /* 58610 */ // Label 755: @58610
18573 /* 58610 */ GIM_Reject,
18574 /* 58611 */ // Label 748: @58611
18575 /* 58611 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(58658),
18576 /* 58616 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
18577 /* 58619 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(58638), // Rule ID 2031 //
18578 /* 58624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
18579 /* 58627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
18580 /* 58631 */ // (bitconvert:{ *:[i64] } f64:{ *:[f64] }:$A) => (MFVSRD:{ *:[i64] } ?:{ *:[f64] }:$A)
18581 /* 58631 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
18582 /* 58636 */ GIR_RootConstrainSelectedInstOperands,
18583 /* 58637 */ // GIR_Coverage, 2031,
18584 /* 58637 */ GIR_Done,
18585 /* 58638 */ // Label 757: @58638
18586 /* 58638 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(58657), // Rule ID 2032 //
18587 /* 58643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
18588 /* 58646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
18589 /* 58650 */ // (bitconvert:{ *:[f64] } i64:{ *:[i64] }:$S) => (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$S)
18590 /* 58650 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MTVSRD),
18591 /* 58655 */ GIR_RootConstrainSelectedInstOperands,
18592 /* 58656 */ // GIR_Coverage, 2032,
18593 /* 58656 */ GIR_Done,
18594 /* 58657 */ // Label 758: @58657
18595 /* 58657 */ GIM_Reject,
18596 /* 58658 */ // Label 756: @58658
18597 /* 58658 */ GIM_Reject,
18598 /* 58659 */ // Label 749: @58659
18599 /* 58659 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(58716), // Rule ID 1935 //
18600 /* 58664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
18601 /* 58667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18602 /* 58670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18603 /* 58674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18604 /* 58678 */ GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18605 /* 58684 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
18606 /* 58686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18607 /* 58688 */ // (bitconvert:{ *:[v1i128] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v1i128] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] })
18608 /* 58688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18609 /* 58691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes),
18610 /* 58695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18611 /* 58700 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18612 /* 58702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18613 /* 58705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18614 /* 58707 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18615 /* 58710 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18616 /* 58715 */ // GIR_Coverage, 1935,
18617 /* 58715 */ GIR_EraseRootFromParent_Done,
18618 /* 58716 */ // Label 759: @58716
18619 /* 58716 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(58742), // Rule ID 1622 //
18620 /* 58721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18621 /* 58724 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
18622 /* 58727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18623 /* 58731 */ // (bitconvert:{ *:[v1i128] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v1i128] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] })
18624 /* 58731 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18625 /* 58736 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18626 /* 58741 */ // GIR_Coverage, 1622,
18627 /* 58741 */ GIR_Done,
18628 /* 58742 */ // Label 760: @58742
18629 /* 58742 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(58774), // Rule ID 1336 //
18630 /* 58747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18631 /* 58750 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18632 /* 58753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18633 /* 58757 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18634 /* 58761 */ // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v1i128] }:$src
18635 /* 58761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18636 /* 58764 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18637 /* 58766 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18638 /* 58768 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18639 /* 58773 */ // GIR_Coverage, 1336,
18640 /* 58773 */ GIR_EraseRootFromParent_Done,
18641 /* 58774 */ // Label 761: @58774
18642 /* 58774 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(58806), // Rule ID 1337 //
18643 /* 58779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18644 /* 58782 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
18645 /* 58785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18646 /* 58789 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18647 /* 58793 */ // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v1i128] }:$src
18648 /* 58793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18649 /* 58796 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18650 /* 58798 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18651 /* 58800 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18652 /* 58805 */ // GIR_Coverage, 1337,
18653 /* 58805 */ GIR_EraseRootFromParent_Done,
18654 /* 58806 */ // Label 762: @58806
18655 /* 58806 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(58838), // Rule ID 1338 //
18656 /* 58811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18657 /* 58814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18658 /* 58817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18659 /* 58821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18660 /* 58825 */ // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v1i128] }:$src
18661 /* 58825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18662 /* 58828 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18663 /* 58830 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18664 /* 58832 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18665 /* 58837 */ // GIR_Coverage, 1338,
18666 /* 58837 */ GIR_EraseRootFromParent_Done,
18667 /* 58838 */ // Label 763: @58838
18668 /* 58838 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(58870), // Rule ID 1339 //
18669 /* 58843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18670 /* 58846 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18671 /* 58849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18672 /* 58853 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18673 /* 58857 */ // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v1i128] }:$src
18674 /* 58857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18675 /* 58860 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18676 /* 58862 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18677 /* 58864 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18678 /* 58869 */ // GIR_Coverage, 1339,
18679 /* 58869 */ GIR_EraseRootFromParent_Done,
18680 /* 58870 */ // Label 764: @58870
18681 /* 58870 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(58902), // Rule ID 1340 //
18682 /* 58875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18683 /* 58878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
18684 /* 58881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18685 /* 58885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18686 /* 58889 */ // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v1i128] }:$src
18687 /* 58889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18688 /* 58892 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18689 /* 58894 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18690 /* 58896 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18691 /* 58901 */ // GIR_Coverage, 1340,
18692 /* 58901 */ GIR_EraseRootFromParent_Done,
18693 /* 58902 */ // Label 765: @58902
18694 /* 58902 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(58934), // Rule ID 1341 //
18695 /* 58907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18696 /* 58910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18697 /* 58913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18698 /* 58917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18699 /* 58921 */ // (bitconvert:{ *:[f128] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[f128] }:$src
18700 /* 58921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18701 /* 58924 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18702 /* 58926 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18703 /* 58928 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18704 /* 58933 */ // GIR_Coverage, 1341,
18705 /* 58933 */ GIR_EraseRootFromParent_Done,
18706 /* 58934 */ // Label 766: @58934
18707 /* 58934 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(58966), // Rule ID 1342 //
18708 /* 58939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18709 /* 58942 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
18710 /* 58945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18711 /* 58949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18712 /* 58953 */ // (bitconvert:{ *:[f128] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[f128] }:$src
18713 /* 58953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18714 /* 58956 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18715 /* 58958 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18716 /* 58960 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18717 /* 58965 */ // GIR_Coverage, 1342,
18718 /* 58965 */ GIR_EraseRootFromParent_Done,
18719 /* 58966 */ // Label 767: @58966
18720 /* 58966 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(58998), // Rule ID 1343 //
18721 /* 58971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18722 /* 58974 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18723 /* 58977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18724 /* 58981 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18725 /* 58985 */ // (bitconvert:{ *:[f128] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[f128] }:$src
18726 /* 58985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18727 /* 58988 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18728 /* 58990 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18729 /* 58992 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18730 /* 58997 */ // GIR_Coverage, 1343,
18731 /* 58997 */ GIR_EraseRootFromParent_Done,
18732 /* 58998 */ // Label 768: @58998
18733 /* 58998 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(59030), // Rule ID 1344 //
18734 /* 59003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18735 /* 59006 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18736 /* 59009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18737 /* 59013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18738 /* 59017 */ // (bitconvert:{ *:[f128] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[f128] }:$src
18739 /* 59017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18740 /* 59020 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18741 /* 59022 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18742 /* 59024 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18743 /* 59029 */ // GIR_Coverage, 1344,
18744 /* 59029 */ GIR_EraseRootFromParent_Done,
18745 /* 59030 */ // Label 769: @59030
18746 /* 59030 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(59062), // Rule ID 1345 //
18747 /* 59035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18748 /* 59038 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
18749 /* 59041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18750 /* 59045 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18751 /* 59049 */ // (bitconvert:{ *:[f128] } VRRC:{ *:[v2f64] }:$src) => VRRC:{ *:[f128] }:$src
18752 /* 59049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18753 /* 59052 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18754 /* 59054 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18755 /* 59056 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18756 /* 59061 */ // GIR_Coverage, 1345,
18757 /* 59061 */ GIR_EraseRootFromParent_Done,
18758 /* 59062 */ // Label 770: @59062
18759 /* 59062 */ GIM_Reject,
18760 /* 59063 */ // Label 750: @59063
18761 /* 59063 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(59120), // Rule ID 1936 //
18762 /* 59068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
18763 /* 59071 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18764 /* 59074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18765 /* 59078 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18766 /* 59082 */ GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18767 /* 59088 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
18768 /* 59090 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18769 /* 59092 */ // (bitconvert:{ *:[v2i64] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] })
18770 /* 59092 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18771 /* 59095 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes),
18772 /* 59099 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18773 /* 59104 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18774 /* 59106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18775 /* 59109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18776 /* 59111 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18777 /* 59114 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18778 /* 59119 */ // GIR_Coverage, 1936,
18779 /* 59119 */ GIR_EraseRootFromParent_Done,
18780 /* 59120 */ // Label 771: @59120
18781 /* 59120 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(59146), // Rule ID 1603 //
18782 /* 59125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18783 /* 59128 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18784 /* 59131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18785 /* 59135 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v4f32] }:$A, VSRC:{ *:[i32] })
18786 /* 59135 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18787 /* 59140 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18788 /* 59145 */ // GIR_Coverage, 1603,
18789 /* 59145 */ GIR_Done,
18790 /* 59146 */ // Label 772: @59146
18791 /* 59146 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(59172), // Rule ID 1604 //
18792 /* 59151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18793 /* 59154 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18794 /* 59157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18795 /* 59161 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v4i32] }:$A, VSRC:{ *:[i32] })
18796 /* 59161 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18797 /* 59166 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18798 /* 59171 */ // GIR_Coverage, 1604,
18799 /* 59171 */ GIR_Done,
18800 /* 59172 */ // Label 773: @59172
18801 /* 59172 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(59198), // Rule ID 1605 //
18802 /* 59177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18803 /* 59180 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
18804 /* 59183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18805 /* 59187 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] })
18806 /* 59187 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18807 /* 59192 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18808 /* 59197 */ // GIR_Coverage, 1605,
18809 /* 59197 */ GIR_Done,
18810 /* 59198 */ // Label 774: @59198
18811 /* 59198 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(59224), // Rule ID 1606 //
18812 /* 59203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18813 /* 59206 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18814 /* 59209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18815 /* 59213 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] })
18816 /* 59213 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18817 /* 59218 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18818 /* 59223 */ // GIR_Coverage, 1606,
18819 /* 59223 */ GIR_Done,
18820 /* 59224 */ // Label 775: @59224
18821 /* 59224 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(59250), // Rule ID 1611 //
18822 /* 59229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18823 /* 59232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18824 /* 59235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18825 /* 59239 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v4f32] }:$A, VSRC:{ *:[i32] })
18826 /* 59239 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18827 /* 59244 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18828 /* 59249 */ // GIR_Coverage, 1611,
18829 /* 59249 */ GIR_Done,
18830 /* 59250 */ // Label 776: @59250
18831 /* 59250 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(59276), // Rule ID 1612 //
18832 /* 59255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18833 /* 59258 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18834 /* 59261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18835 /* 59265 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v4i32] }:$A, VSRC:{ *:[i32] })
18836 /* 59265 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18837 /* 59270 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18838 /* 59275 */ // GIR_Coverage, 1612,
18839 /* 59275 */ GIR_Done,
18840 /* 59276 */ // Label 777: @59276
18841 /* 59276 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(59302), // Rule ID 1613 //
18842 /* 59281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18843 /* 59284 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
18844 /* 59287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18845 /* 59291 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] })
18846 /* 59291 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18847 /* 59296 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18848 /* 59301 */ // GIR_Coverage, 1613,
18849 /* 59301 */ GIR_Done,
18850 /* 59302 */ // Label 778: @59302
18851 /* 59302 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(59328), // Rule ID 1614 //
18852 /* 59307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18853 /* 59310 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18854 /* 59313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18855 /* 59317 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] })
18856 /* 59317 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18857 /* 59322 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
18858 /* 59327 */ // GIR_Coverage, 1614,
18859 /* 59327 */ GIR_Done,
18860 /* 59328 */ // Label 779: @59328
18861 /* 59328 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(59354), // Rule ID 1619 //
18862 /* 59333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18863 /* 59336 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
18864 /* 59339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18865 /* 59343 */ // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] })
18866 /* 59343 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18867 /* 59348 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18868 /* 59353 */ // GIR_Coverage, 1619,
18869 /* 59353 */ GIR_Done,
18870 /* 59354 */ // Label 780: @59354
18871 /* 59354 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(59380), // Rule ID 1620 //
18872 /* 59359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18873 /* 59362 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
18874 /* 59365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18875 /* 59369 */ // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] })
18876 /* 59369 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18877 /* 59374 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18878 /* 59379 */ // GIR_Coverage, 1620,
18879 /* 59379 */ GIR_Done,
18880 /* 59380 */ // Label 781: @59380
18881 /* 59380 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(59406), // Rule ID 1621 //
18882 /* 59385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18883 /* 59388 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
18884 /* 59391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18885 /* 59395 */ // (bitconvert:{ *:[v2f64] } v1i128:{ *:[v1i128] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v1i128] }:$A, VRRC:{ *:[i32] })
18886 /* 59395 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18887 /* 59400 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18888 /* 59405 */ // GIR_Coverage, 1621,
18889 /* 59405 */ GIR_Done,
18890 /* 59406 */ // Label 782: @59406
18891 /* 59406 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(59432), // Rule ID 1623 //
18892 /* 59411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18893 /* 59414 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
18894 /* 59417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18895 /* 59421 */ // (bitconvert:{ *:[v2i64] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] })
18896 /* 59421 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18897 /* 59426 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18898 /* 59431 */ // GIR_Coverage, 1623,
18899 /* 59431 */ GIR_Done,
18900 /* 59432 */ // Label 783: @59432
18901 /* 59432 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(59464), // Rule ID 1331 //
18902 /* 59437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18903 /* 59440 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18904 /* 59443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18905 /* 59447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18906 /* 59451 */ // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v2i64] }:$src
18907 /* 59451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18908 /* 59454 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18909 /* 59456 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18910 /* 59458 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18911 /* 59463 */ // GIR_Coverage, 1331,
18912 /* 59463 */ GIR_EraseRootFromParent_Done,
18913 /* 59464 */ // Label 784: @59464
18914 /* 59464 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(59496), // Rule ID 1332 //
18915 /* 59469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18916 /* 59472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
18917 /* 59475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18918 /* 59479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18919 /* 59483 */ // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v2i64] }:$src
18920 /* 59483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18921 /* 59486 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18922 /* 59488 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18923 /* 59490 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18924 /* 59495 */ // GIR_Coverage, 1332,
18925 /* 59495 */ GIR_EraseRootFromParent_Done,
18926 /* 59496 */ // Label 785: @59496
18927 /* 59496 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(59528), // Rule ID 1333 //
18928 /* 59501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18929 /* 59504 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18930 /* 59507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18931 /* 59511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18932 /* 59515 */ // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v2i64] }:$src
18933 /* 59515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18934 /* 59518 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18935 /* 59520 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18936 /* 59522 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18937 /* 59527 */ // GIR_Coverage, 1333,
18938 /* 59527 */ GIR_EraseRootFromParent_Done,
18939 /* 59528 */ // Label 786: @59528
18940 /* 59528 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(59560), // Rule ID 1334 //
18941 /* 59533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18942 /* 59536 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18943 /* 59539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18944 /* 59543 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18945 /* 59547 */ // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v2i64] }:$src
18946 /* 59547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18947 /* 59550 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18948 /* 59552 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18949 /* 59554 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18950 /* 59559 */ // GIR_Coverage, 1334,
18951 /* 59559 */ GIR_EraseRootFromParent_Done,
18952 /* 59560 */ // Label 787: @59560
18953 /* 59560 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(59592), // Rule ID 1335 //
18954 /* 59565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18955 /* 59568 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
18956 /* 59571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18957 /* 59575 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18958 /* 59579 */ // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v2i64] }:$src
18959 /* 59579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18960 /* 59582 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18961 /* 59584 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18962 /* 59586 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18963 /* 59591 */ // GIR_Coverage, 1335,
18964 /* 59591 */ GIR_EraseRootFromParent_Done,
18965 /* 59592 */ // Label 788: @59592
18966 /* 59592 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(59624), // Rule ID 1350 //
18967 /* 59597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
18968 /* 59600 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
18969 /* 59603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18970 /* 59607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
18971 /* 59611 */ // (bitconvert:{ *:[v2f64] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v2f64] }:$src
18972 /* 59611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18973 /* 59614 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
18974 /* 59616 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
18975 /* 59618 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
18976 /* 59623 */ // GIR_Coverage, 1350,
18977 /* 59623 */ GIR_EraseRootFromParent_Done,
18978 /* 59624 */ // Label 789: @59624
18979 /* 59624 */ GIM_Reject,
18980 /* 59625 */ // Label 751: @59625
18981 /* 59625 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(59661), // Rule ID 945 //
18982 /* 59630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
18983 /* 59633 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18984 /* 59636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
18985 /* 59640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18986 /* 59644 */ GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18987 /* 59650 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
18988 /* 59652 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18989 /* 59654 */ // (bitconvert:{ *:[v4i32] } immAllOnesV:{ *:[v16i8] }) => (XXLEQVOnes:{ *:[v4i32] })
18990 /* 59654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes),
18991 /* 59657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
18992 /* 59659 */ GIR_RootConstrainSelectedInstOperands,
18993 /* 59660 */ // GIR_Coverage, 945,
18994 /* 59660 */ GIR_EraseRootFromParent_Done,
18995 /* 59661 */ // Label 790: @59661
18996 /* 59661 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(59687), // Rule ID 1607 //
18997 /* 59666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
18998 /* 59669 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
18999 /* 59672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19000 /* 59676 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4f32] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] })
19001 /* 59676 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19002 /* 59681 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19003 /* 59686 */ // GIR_Coverage, 1607,
19004 /* 59686 */ GIR_Done,
19005 /* 59687 */ // Label 791: @59687
19006 /* 59687 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(59713), // Rule ID 1608 //
19007 /* 59692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19008 /* 59695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19009 /* 59698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19010 /* 59702 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] })
19011 /* 59702 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19012 /* 59707 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19013 /* 59712 */ // GIR_Coverage, 1608,
19014 /* 59712 */ GIR_Done,
19015 /* 59713 */ // Label 792: @59713
19016 /* 59713 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(59739), // Rule ID 1615 //
19017 /* 59718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19018 /* 59721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19019 /* 59724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19020 /* 59728 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4f32] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] })
19021 /* 59728 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19022 /* 59733 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19023 /* 59738 */ // GIR_Coverage, 1615,
19024 /* 59738 */ GIR_Done,
19025 /* 59739 */ // Label 793: @59739
19026 /* 59739 */ GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(59765), // Rule ID 1616 //
19027 /* 59744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19028 /* 59747 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19029 /* 59750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19030 /* 59754 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] })
19031 /* 59754 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19032 /* 59759 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19033 /* 59764 */ // GIR_Coverage, 1616,
19034 /* 59764 */ GIR_Done,
19035 /* 59765 */ // Label 794: @59765
19036 /* 59765 */ GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(59791), // Rule ID 1624 //
19037 /* 59770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19038 /* 59773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19039 /* 59776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19040 /* 59780 */ // (bitconvert:{ *:[v4i32] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] })
19041 /* 59780 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19042 /* 59785 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19043 /* 59790 */ // GIR_Coverage, 1624,
19044 /* 59790 */ GIR_Done,
19045 /* 59791 */ // Label 795: @59791
19046 /* 59791 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(59823), // Rule ID 1321 //
19047 /* 59796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19048 /* 59799 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
19049 /* 59802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19050 /* 59806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19051 /* 59810 */ // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v4i32] }:$src
19052 /* 59810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19053 /* 59813 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19054 /* 59815 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19055 /* 59817 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19056 /* 59822 */ // GIR_Coverage, 1321,
19057 /* 59822 */ GIR_EraseRootFromParent_Done,
19058 /* 59823 */ // Label 796: @59823
19059 /* 59823 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(59855), // Rule ID 1322 //
19060 /* 59828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19061 /* 59831 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
19062 /* 59834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19063 /* 59838 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19064 /* 59842 */ // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v4i32] }:$src
19065 /* 59842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19066 /* 59845 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19067 /* 59847 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19068 /* 59849 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19069 /* 59854 */ // GIR_Coverage, 1322,
19070 /* 59854 */ GIR_EraseRootFromParent_Done,
19071 /* 59855 */ // Label 797: @59855
19072 /* 59855 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(59887), // Rule ID 1323 //
19073 /* 59860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19074 /* 59863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
19075 /* 59866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19076 /* 59870 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19077 /* 59874 */ // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v4i32] }:$src
19078 /* 59874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19079 /* 59877 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19080 /* 59879 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19081 /* 59881 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19082 /* 59886 */ // GIR_Coverage, 1323,
19083 /* 59886 */ GIR_EraseRootFromParent_Done,
19084 /* 59887 */ // Label 798: @59887
19085 /* 59887 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(59919), // Rule ID 1324 //
19086 /* 59892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19087 /* 59895 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19088 /* 59898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19089 /* 59902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19090 /* 59906 */ // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v4i32] }:$src
19091 /* 59906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19092 /* 59909 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19093 /* 59911 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19094 /* 59913 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19095 /* 59918 */ // GIR_Coverage, 1324,
19096 /* 59918 */ GIR_EraseRootFromParent_Done,
19097 /* 59919 */ // Label 799: @59919
19098 /* 59919 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(59951), // Rule ID 1325 //
19099 /* 59924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19100 /* 59927 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19101 /* 59930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19102 /* 59934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19103 /* 59938 */ // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v4i32] }:$src
19104 /* 59938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19105 /* 59941 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19106 /* 59943 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19107 /* 59945 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19108 /* 59950 */ // GIR_Coverage, 1325,
19109 /* 59950 */ GIR_EraseRootFromParent_Done,
19110 /* 59951 */ // Label 800: @59951
19111 /* 59951 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(59983), // Rule ID 1326 //
19112 /* 59956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19113 /* 59959 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
19114 /* 59962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19115 /* 59966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19116 /* 59970 */ // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v4f32] }:$src
19117 /* 59970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19118 /* 59973 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19119 /* 59975 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19120 /* 59977 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19121 /* 59982 */ // GIR_Coverage, 1326,
19122 /* 59982 */ GIR_EraseRootFromParent_Done,
19123 /* 59983 */ // Label 801: @59983
19124 /* 59983 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(60015), // Rule ID 1327 //
19125 /* 59988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19126 /* 59991 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
19127 /* 59994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19128 /* 59998 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19129 /* 60002 */ // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v4f32] }:$src
19130 /* 60002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19131 /* 60005 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19132 /* 60007 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19133 /* 60009 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19134 /* 60014 */ // GIR_Coverage, 1327,
19135 /* 60014 */ GIR_EraseRootFromParent_Done,
19136 /* 60015 */ // Label 802: @60015
19137 /* 60015 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(60047), // Rule ID 1328 //
19138 /* 60020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19139 /* 60023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
19140 /* 60026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19141 /* 60030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19142 /* 60034 */ // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v4f32] }:$src
19143 /* 60034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19144 /* 60037 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19145 /* 60039 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19146 /* 60041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19147 /* 60046 */ // GIR_Coverage, 1328,
19148 /* 60046 */ GIR_EraseRootFromParent_Done,
19149 /* 60047 */ // Label 803: @60047
19150 /* 60047 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(60079), // Rule ID 1329 //
19151 /* 60052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19152 /* 60055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19153 /* 60058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19154 /* 60062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19155 /* 60066 */ // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v4f32] }:$src
19156 /* 60066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19157 /* 60069 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19158 /* 60071 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19159 /* 60073 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19160 /* 60078 */ // GIR_Coverage, 1329,
19161 /* 60078 */ GIR_EraseRootFromParent_Done,
19162 /* 60079 */ // Label 804: @60079
19163 /* 60079 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(60111), // Rule ID 1330 //
19164 /* 60084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19165 /* 60087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19166 /* 60090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19167 /* 60094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19168 /* 60098 */ // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v4f32] }:$src
19169 /* 60098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19170 /* 60101 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19171 /* 60103 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19172 /* 60105 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19173 /* 60110 */ // GIR_Coverage, 1330,
19174 /* 60110 */ GIR_EraseRootFromParent_Done,
19175 /* 60111 */ // Label 805: @60111
19176 /* 60111 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(60143), // Rule ID 1348 //
19177 /* 60116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19178 /* 60119 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19179 /* 60122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19180 /* 60126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19181 /* 60130 */ // (bitconvert:{ *:[v4i32] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v4i32] }:$src
19182 /* 60130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19183 /* 60133 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19184 /* 60135 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19185 /* 60137 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19186 /* 60142 */ // GIR_Coverage, 1348,
19187 /* 60142 */ GIR_EraseRootFromParent_Done,
19188 /* 60143 */ // Label 806: @60143
19189 /* 60143 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(60175), // Rule ID 1349 //
19190 /* 60148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19191 /* 60151 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19192 /* 60154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19193 /* 60158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19194 /* 60162 */ // (bitconvert:{ *:[v4f32] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v4f32] }:$src
19195 /* 60162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19196 /* 60165 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19197 /* 60167 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19198 /* 60169 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19199 /* 60174 */ // GIR_Coverage, 1349,
19200 /* 60174 */ GIR_EraseRootFromParent_Done,
19201 /* 60175 */ // Label 807: @60175
19202 /* 60175 */ GIM_Reject,
19203 /* 60176 */ // Label 752: @60176
19204 /* 60176 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(60233), // Rule ID 1937 //
19205 /* 60181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
19206 /* 60184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
19207 /* 60187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
19208 /* 60191 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19209 /* 60195 */ GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
19210 /* 60201 */ GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
19211 /* 60203 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19212 /* 60205 */ // (bitconvert:{ *:[v8i16] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] })
19213 /* 60205 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
19214 /* 60208 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes),
19215 /* 60212 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19216 /* 60217 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19217 /* 60219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19218 /* 60222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19219 /* 60224 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19220 /* 60227 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
19221 /* 60232 */ // GIR_Coverage, 1937,
19222 /* 60232 */ GIR_EraseRootFromParent_Done,
19223 /* 60233 */ // Label 808: @60233
19224 /* 60233 */ GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(60259), // Rule ID 1609 //
19225 /* 60238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19226 /* 60241 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19227 /* 60244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19228 /* 60248 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] })
19229 /* 60248 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19230 /* 60253 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19231 /* 60258 */ // GIR_Coverage, 1609,
19232 /* 60258 */ GIR_Done,
19233 /* 60259 */ // Label 809: @60259
19234 /* 60259 */ GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(60285), // Rule ID 1617 //
19235 /* 60264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19236 /* 60267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19237 /* 60270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19238 /* 60274 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] })
19239 /* 60274 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19240 /* 60279 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19241 /* 60284 */ // GIR_Coverage, 1617,
19242 /* 60284 */ GIR_Done,
19243 /* 60285 */ // Label 810: @60285
19244 /* 60285 */ GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(60311), // Rule ID 1625 //
19245 /* 60290 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19246 /* 60293 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19247 /* 60296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19248 /* 60300 */ // (bitconvert:{ *:[v8i16] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] })
19249 /* 60300 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19250 /* 60305 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19251 /* 60310 */ // GIR_Coverage, 1625,
19252 /* 60310 */ GIR_Done,
19253 /* 60311 */ // Label 811: @60311
19254 /* 60311 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(60343), // Rule ID 1316 //
19255 /* 60316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19256 /* 60319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
19257 /* 60322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19258 /* 60326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19259 /* 60330 */ // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v8i16] }:$src
19260 /* 60330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19261 /* 60333 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19262 /* 60335 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19263 /* 60337 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19264 /* 60342 */ // GIR_Coverage, 1316,
19265 /* 60342 */ GIR_EraseRootFromParent_Done,
19266 /* 60343 */ // Label 812: @60343
19267 /* 60343 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(60375), // Rule ID 1317 //
19268 /* 60348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19269 /* 60351 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
19270 /* 60354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19271 /* 60358 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19272 /* 60362 */ // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v8i16] }:$src
19273 /* 60362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19274 /* 60365 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19275 /* 60367 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19276 /* 60369 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19277 /* 60374 */ // GIR_Coverage, 1317,
19278 /* 60374 */ GIR_EraseRootFromParent_Done,
19279 /* 60375 */ // Label 813: @60375
19280 /* 60375 */ GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(60407), // Rule ID 1318 //
19281 /* 60380 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19282 /* 60383 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
19283 /* 60386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19284 /* 60390 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19285 /* 60394 */ // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v8i16] }:$src
19286 /* 60394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19287 /* 60397 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19288 /* 60399 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19289 /* 60401 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19290 /* 60406 */ // GIR_Coverage, 1318,
19291 /* 60406 */ GIR_EraseRootFromParent_Done,
19292 /* 60407 */ // Label 814: @60407
19293 /* 60407 */ GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(60439), // Rule ID 1319 //
19294 /* 60412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19295 /* 60415 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19296 /* 60418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19297 /* 60422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19298 /* 60426 */ // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v8i16] }:$src
19299 /* 60426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19300 /* 60429 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19301 /* 60431 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19302 /* 60433 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19303 /* 60438 */ // GIR_Coverage, 1319,
19304 /* 60438 */ GIR_EraseRootFromParent_Done,
19305 /* 60439 */ // Label 815: @60439
19306 /* 60439 */ GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(60471), // Rule ID 1320 //
19307 /* 60444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19308 /* 60447 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19309 /* 60450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19310 /* 60454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19311 /* 60458 */ // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v8i16] }:$src
19312 /* 60458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19313 /* 60461 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19314 /* 60463 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19315 /* 60465 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19316 /* 60470 */ // GIR_Coverage, 1320,
19317 /* 60470 */ GIR_EraseRootFromParent_Done,
19318 /* 60471 */ // Label 816: @60471
19319 /* 60471 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(60503), // Rule ID 1347 //
19320 /* 60476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19321 /* 60479 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19322 /* 60482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19323 /* 60486 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19324 /* 60490 */ // (bitconvert:{ *:[v8i16] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v8i16] }:$src
19325 /* 60490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19326 /* 60493 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19327 /* 60495 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19328 /* 60497 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19329 /* 60502 */ // GIR_Coverage, 1347,
19330 /* 60502 */ GIR_EraseRootFromParent_Done,
19331 /* 60503 */ // Label 817: @60503
19332 /* 60503 */ GIM_Reject,
19333 /* 60504 */ // Label 753: @60504
19334 /* 60504 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(60530), // Rule ID 1610 //
19335 /* 60509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19336 /* 60512 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19337 /* 60515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19338 /* 60519 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] })
19339 /* 60519 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19340 /* 60524 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19341 /* 60529 */ // GIR_Coverage, 1610,
19342 /* 60529 */ GIR_Done,
19343 /* 60530 */ // Label 818: @60530
19344 /* 60530 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(60556), // Rule ID 1618 //
19345 /* 60535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19346 /* 60538 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19347 /* 60541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19348 /* 60545 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] })
19349 /* 60545 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19350 /* 60550 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19351 /* 60555 */ // GIR_Coverage, 1618,
19352 /* 60555 */ GIR_Done,
19353 /* 60556 */ // Label 819: @60556
19354 /* 60556 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(60582), // Rule ID 1626 //
19355 /* 60561 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19356 /* 60564 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19357 /* 60567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19358 /* 60571 */ // (bitconvert:{ *:[v16i8] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] })
19359 /* 60571 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19360 /* 60576 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19361 /* 60581 */ // GIR_Coverage, 1626,
19362 /* 60581 */ GIR_Done,
19363 /* 60582 */ // Label 820: @60582
19364 /* 60582 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(60614), // Rule ID 1311 //
19365 /* 60587 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19366 /* 60590 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
19367 /* 60593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19368 /* 60597 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19369 /* 60601 */ // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v16i8] }:$src
19370 /* 60601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19371 /* 60604 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19372 /* 60606 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19373 /* 60608 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19374 /* 60613 */ // GIR_Coverage, 1311,
19375 /* 60613 */ GIR_EraseRootFromParent_Done,
19376 /* 60614 */ // Label 821: @60614
19377 /* 60614 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(60646), // Rule ID 1312 //
19378 /* 60619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19379 /* 60622 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
19380 /* 60625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19381 /* 60629 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19382 /* 60633 */ // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v16i8] }:$src
19383 /* 60633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19384 /* 60636 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19385 /* 60638 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19386 /* 60640 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19387 /* 60645 */ // GIR_Coverage, 1312,
19388 /* 60645 */ GIR_EraseRootFromParent_Done,
19389 /* 60646 */ // Label 822: @60646
19390 /* 60646 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(60678), // Rule ID 1313 //
19391 /* 60651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19392 /* 60654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
19393 /* 60657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19394 /* 60661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19395 /* 60665 */ // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v16i8] }:$src
19396 /* 60665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19397 /* 60668 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19398 /* 60670 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19399 /* 60672 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19400 /* 60677 */ // GIR_Coverage, 1313,
19401 /* 60677 */ GIR_EraseRootFromParent_Done,
19402 /* 60678 */ // Label 823: @60678
19403 /* 60678 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(60710), // Rule ID 1314 //
19404 /* 60683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19405 /* 60686 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19406 /* 60689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19407 /* 60693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19408 /* 60697 */ // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v16i8] }:$src
19409 /* 60697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19410 /* 60700 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19411 /* 60702 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19412 /* 60704 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19413 /* 60709 */ // GIR_Coverage, 1314,
19414 /* 60709 */ GIR_EraseRootFromParent_Done,
19415 /* 60710 */ // Label 824: @60710
19416 /* 60710 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(60742), // Rule ID 1315 //
19417 /* 60715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19418 /* 60718 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19419 /* 60721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19420 /* 60725 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19421 /* 60729 */ // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v16i8] }:$src
19422 /* 60729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19423 /* 60732 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19424 /* 60734 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19425 /* 60736 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19426 /* 60741 */ // GIR_Coverage, 1315,
19427 /* 60741 */ GIR_EraseRootFromParent_Done,
19428 /* 60742 */ // Label 825: @60742
19429 /* 60742 */ GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(60774), // Rule ID 1346 //
19430 /* 60747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19431 /* 60750 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19432 /* 60753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19433 /* 60757 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19434 /* 60761 */ // (bitconvert:{ *:[v16i8] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v16i8] }:$src
19435 /* 60761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19436 /* 60764 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
19437 /* 60766 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
19438 /* 60768 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
19439 /* 60773 */ // GIR_Coverage, 1346,
19440 /* 60773 */ GIR_EraseRootFromParent_Done,
19441 /* 60774 */ // Label 826: @60774
19442 /* 60774 */ GIM_Reject,
19443 /* 60775 */ // Label 754: @60775
19444 /* 60775 */ GIM_Reject,
19445 /* 60776 */ // Label 12: @60776
19446 /* 60776 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 832*/ GIMT_Encode4(61050),
19447 /* 60787 */ /*GILLT_s32*//*Label 827*/ GIMT_Encode4(60807),
19448 /* 60791 */ /*GILLT_s64*//*Label 828*/ GIMT_Encode4(60900),
19449 /* 60795 */ /*GILLT_s128*//*Label 829*/ GIMT_Encode4(60948),
19450 /* 60799 */ /*GILLT_v2s64*//*Label 830*/ GIMT_Encode4(60979),
19451 /* 60803 */ /*GILLT_v4s32*//*Label 831*/ GIMT_Encode4(61002),
19452 /* 60807 */ // Label 827: @60807
19453 /* 60807 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(60899),
19454 /* 60812 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19455 /* 60815 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(60879), // Rule ID 1713 //
19456 /* 60820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19457 /* 60823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
19458 /* 60827 */ // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIZ:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
19459 /* 60827 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
19460 /* 60830 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19461 /* 60834 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19462 /* 60839 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
19463 /* 60843 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
19464 /* 60848 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19465 /* 60851 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIZ),
19466 /* 60855 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19467 /* 60860 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19468 /* 60863 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19469 /* 60865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19470 /* 60868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19471 /* 60870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19472 /* 60873 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
19473 /* 60878 */ // GIR_Coverage, 1713,
19474 /* 60878 */ GIR_EraseRootFromParent_Done,
19475 /* 60879 */ // Label 834: @60879
19476 /* 60879 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(60898), // Rule ID 150 //
19477 /* 60884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
19478 /* 60887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
19479 /* 60891 */ // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRIZS:{ *:[f32] } f32:{ *:[f32] }:$RB)
19480 /* 60891 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIZS),
19481 /* 60896 */ GIR_RootConstrainSelectedInstOperands,
19482 /* 60897 */ // GIR_Coverage, 150,
19483 /* 60897 */ GIR_Done,
19484 /* 60898 */ // Label 835: @60898
19485 /* 60898 */ GIM_Reject,
19486 /* 60899 */ // Label 833: @60899
19487 /* 60899 */ GIM_Reject,
19488 /* 60900 */ // Label 828: @60900
19489 /* 60900 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(60947),
19490 /* 60905 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
19491 /* 60908 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(60927), // Rule ID 915 //
19492 /* 60913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19493 /* 60916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
19494 /* 60920 */ // (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIZ:{ *:[f64] } f64:{ *:[f64] }:$XB)
19495 /* 60920 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIZ),
19496 /* 60925 */ GIR_RootConstrainSelectedInstOperands,
19497 /* 60926 */ // GIR_Coverage, 915,
19498 /* 60926 */ GIR_Done,
19499 /* 60927 */ // Label 837: @60927
19500 /* 60927 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(60946), // Rule ID 148 //
19501 /* 60932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
19502 /* 60935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
19503 /* 60939 */ // (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIZD:{ *:[f64] } f64:{ *:[f64] }:$RB)
19504 /* 60939 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIZD),
19505 /* 60944 */ GIR_RootConstrainSelectedInstOperands,
19506 /* 60945 */ // GIR_Coverage, 148,
19507 /* 60945 */ GIR_Done,
19508 /* 60946 */ // Label 838: @60946
19509 /* 60946 */ GIM_Reject,
19510 /* 60947 */ // Label 836: @60947
19511 /* 60947 */ GIM_Reject,
19512 /* 60948 */ // Label 829: @60948
19513 /* 60948 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(60978), // Rule ID 2164 //
19514 /* 60953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
19515 /* 60956 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19516 /* 60959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19517 /* 60963 */ // (ftrunc:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 1:{ *:[i32] }, ?:{ *:[f128] }:$vB, 1:{ *:[i32] })
19518 /* 60963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI),
19519 /* 60966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT]
19520 /* 60968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19521 /* 60971 */ GIR_RootToRootCopy, /*OpIdx*/1, // vB
19522 /* 60973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19523 /* 60976 */ GIR_RootConstrainSelectedInstOperands,
19524 /* 60977 */ // GIR_Coverage, 2164,
19525 /* 60977 */ GIR_EraseRootFromParent_Done,
19526 /* 60978 */ // Label 839: @60978
19527 /* 60978 */ GIM_Reject,
19528 /* 60979 */ // Label 830: @60979
19529 /* 60979 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(61001), // Rule ID 923 //
19530 /* 60984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19531 /* 60987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19532 /* 60990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
19533 /* 60994 */ // (ftrunc:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIZ:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
19534 /* 60994 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIZ),
19535 /* 60999 */ GIR_RootConstrainSelectedInstOperands,
19536 /* 61000 */ // GIR_Coverage, 923,
19537 /* 61000 */ GIR_Done,
19538 /* 61001 */ // Label 840: @61001
19539 /* 61001 */ GIM_Reject,
19540 /* 61002 */ // Label 831: @61002
19541 /* 61002 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(61049),
19542 /* 61007 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
19543 /* 61010 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(61029), // Rule ID 931 //
19544 /* 61015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19545 /* 61018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
19546 /* 61022 */ // (ftrunc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIZ:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
19547 /* 61022 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIZ),
19548 /* 61027 */ GIR_RootConstrainSelectedInstOperands,
19549 /* 61028 */ // GIR_Coverage, 931,
19550 /* 61028 */ GIR_Done,
19551 /* 61029 */ // Label 842: @61029
19552 /* 61029 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(61048), // Rule ID 1421 //
19553 /* 61034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
19554 /* 61037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19555 /* 61041 */ // (ftrunc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIZ:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA)
19556 /* 61041 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIZ),
19557 /* 61046 */ GIR_RootConstrainSelectedInstOperands,
19558 /* 61047 */ // GIR_Coverage, 1421,
19559 /* 61047 */ GIR_Done,
19560 /* 61048 */ // Label 843: @61048
19561 /* 61048 */ GIM_Reject,
19562 /* 61049 */ // Label 841: @61049
19563 /* 61049 */ GIM_Reject,
19564 /* 61050 */ // Label 832: @61050
19565 /* 61050 */ GIM_Reject,
19566 /* 61051 */ // Label 13: @61051
19567 /* 61051 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 849*/ GIMT_Encode4(61300),
19568 /* 61062 */ /*GILLT_s32*//*Label 844*/ GIMT_Encode4(61082),
19569 /* 61066 */ /*GILLT_s64*//*Label 845*/ GIMT_Encode4(61175),
19570 /* 61070 */ /*GILLT_s128*//*Label 846*/ GIMT_Encode4(61223),
19571 /* 61074 */ /*GILLT_v2s64*//*Label 847*/ GIMT_Encode4(61254),
19572 /* 61078 */ /*GILLT_v4s32*//*Label 848*/ GIMT_Encode4(61277),
19573 /* 61082 */ // Label 844: @61082
19574 /* 61082 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(61174),
19575 /* 61087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19576 /* 61090 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(61154), // Rule ID 1707 //
19577 /* 61095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19578 /* 61098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
19579 /* 61102 */ // (fround:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPI:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
19580 /* 61102 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
19581 /* 61105 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19582 /* 61109 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19583 /* 61114 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
19584 /* 61118 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
19585 /* 61123 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19586 /* 61126 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPI),
19587 /* 61130 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19588 /* 61135 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19589 /* 61138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19590 /* 61140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19591 /* 61143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19592 /* 61145 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19593 /* 61148 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
19594 /* 61153 */ // GIR_Coverage, 1707,
19595 /* 61153 */ GIR_EraseRootFromParent_Done,
19596 /* 61154 */ // Label 851: @61154
19597 /* 61154 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(61173), // Rule ID 142 //
19598 /* 61159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
19599 /* 61162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
19600 /* 61166 */ // (fround:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRINS:{ *:[f32] } f32:{ *:[f32] }:$RB)
19601 /* 61166 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRINS),
19602 /* 61171 */ GIR_RootConstrainSelectedInstOperands,
19603 /* 61172 */ // GIR_Coverage, 142,
19604 /* 61172 */ GIR_Done,
19605 /* 61173 */ // Label 852: @61173
19606 /* 61173 */ GIM_Reject,
19607 /* 61174 */ // Label 850: @61174
19608 /* 61174 */ GIM_Reject,
19609 /* 61175 */ // Label 845: @61175
19610 /* 61175 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(61222),
19611 /* 61180 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
19612 /* 61183 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(61202), // Rule ID 909 //
19613 /* 61188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19614 /* 61191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
19615 /* 61195 */ // (fround:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPI:{ *:[f64] } f64:{ *:[f64] }:$XB)
19616 /* 61195 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPI),
19617 /* 61200 */ GIR_RootConstrainSelectedInstOperands,
19618 /* 61201 */ // GIR_Coverage, 909,
19619 /* 61201 */ GIR_Done,
19620 /* 61202 */ // Label 854: @61202
19621 /* 61202 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(61221), // Rule ID 140 //
19622 /* 61207 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
19623 /* 61210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
19624 /* 61214 */ // (fround:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIND:{ *:[f64] } f64:{ *:[f64] }:$RB)
19625 /* 61214 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIND),
19626 /* 61219 */ GIR_RootConstrainSelectedInstOperands,
19627 /* 61220 */ // GIR_Coverage, 140,
19628 /* 61220 */ GIR_Done,
19629 /* 61221 */ // Label 855: @61221
19630 /* 61221 */ GIM_Reject,
19631 /* 61222 */ // Label 853: @61222
19632 /* 61222 */ GIM_Reject,
19633 /* 61223 */ // Label 846: @61223
19634 /* 61223 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(61253), // Rule ID 2162 //
19635 /* 61228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
19636 /* 61231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
19637 /* 61234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
19638 /* 61238 */ // (fround:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 0:{ *:[i32] }, ?:{ *:[f128] }:$vB, 0:{ *:[i32] })
19639 /* 61238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI),
19640 /* 61241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT]
19641 /* 61243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
19642 /* 61246 */ GIR_RootToRootCopy, /*OpIdx*/1, // vB
19643 /* 61248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
19644 /* 61251 */ GIR_RootConstrainSelectedInstOperands,
19645 /* 61252 */ // GIR_Coverage, 2162,
19646 /* 61252 */ GIR_EraseRootFromParent_Done,
19647 /* 61253 */ // Label 856: @61253
19648 /* 61253 */ GIM_Reject,
19649 /* 61254 */ // Label 847: @61254
19650 /* 61254 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(61276), // Rule ID 917 //
19651 /* 61259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19652 /* 61262 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
19653 /* 61265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
19654 /* 61269 */ // (fround:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPI:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
19655 /* 61269 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPI),
19656 /* 61274 */ GIR_RootConstrainSelectedInstOperands,
19657 /* 61275 */ // GIR_Coverage, 917,
19658 /* 61275 */ GIR_Done,
19659 /* 61276 */ // Label 857: @61276
19660 /* 61276 */ GIM_Reject,
19661 /* 61277 */ // Label 848: @61277
19662 /* 61277 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(61299), // Rule ID 925 //
19663 /* 61282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19664 /* 61285 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
19665 /* 61288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
19666 /* 61292 */ // (fround:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPI:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
19667 /* 61292 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPI),
19668 /* 61297 */ GIR_RootConstrainSelectedInstOperands,
19669 /* 61298 */ // GIR_Coverage, 925,
19670 /* 61298 */ GIR_Done,
19671 /* 61299 */ // Label 858: @61299
19672 /* 61299 */ GIM_Reject,
19673 /* 61300 */ // Label 849: @61300
19674 /* 61300 */ GIM_Reject,
19675 /* 61301 */ // Label 14: @61301
19676 /* 61301 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(61431),
19677 /* 61306 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
19678 /* 61309 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 862*/ GIMT_Encode4(61430),
19679 /* 61320 */ /*GILLT_s32*//*Label 860*/ GIMT_Encode4(61328),
19680 /* 61324 */ /*GILLT_s64*//*Label 861*/ GIMT_Encode4(61389),
19681 /* 61328 */ // Label 860: @61328
19682 /* 61328 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(61388), // Rule ID 2034 //
19683 /* 61333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
19684 /* 61336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
19685 /* 61340 */ // (lrint:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, F8RC:{ *:[i32] })))
19686 /* 61340 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
19687 /* 61343 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19688 /* 61347 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19689 /* 61352 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
19690 /* 61356 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::F8RCRegClassID),
19691 /* 61361 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19692 /* 61364 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID),
19693 /* 61368 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19694 /* 61373 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19695 /* 61376 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19696 /* 61378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
19697 /* 61381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
19698 /* 61383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19699 /* 61386 */ GIR_RootConstrainSelectedInstOperands,
19700 /* 61387 */ // GIR_Coverage, 2034,
19701 /* 61387 */ GIR_EraseRootFromParent_Done,
19702 /* 61388 */ // Label 863: @61388
19703 /* 61388 */ GIM_Reject,
19704 /* 61389 */ // Label 861: @61389
19705 /* 61389 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(61429), // Rule ID 2033 //
19706 /* 61394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
19707 /* 61397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
19708 /* 61401 */ // (lrint:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } ?:{ *:[f64] }:$S))
19709 /* 61401 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19710 /* 61404 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID),
19711 /* 61408 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19712 /* 61413 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // S
19713 /* 61417 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19714 /* 61419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
19715 /* 61422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
19716 /* 61424 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19717 /* 61427 */ GIR_RootConstrainSelectedInstOperands,
19718 /* 61428 */ // GIR_Coverage, 2033,
19719 /* 61428 */ GIR_EraseRootFromParent_Done,
19720 /* 61429 */ // Label 864: @61429
19721 /* 61429 */ GIM_Reject,
19722 /* 61430 */ // Label 862: @61430
19723 /* 61430 */ GIM_Reject,
19724 /* 61431 */ // Label 859: @61431
19725 /* 61431 */ GIM_Reject,
19726 /* 61432 */ // Label 15: @61432
19727 /* 61432 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(61562),
19728 /* 61437 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
19729 /* 61440 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 868*/ GIMT_Encode4(61561),
19730 /* 61451 */ /*GILLT_s32*//*Label 866*/ GIMT_Encode4(61459),
19731 /* 61455 */ /*GILLT_s64*//*Label 867*/ GIMT_Encode4(61520),
19732 /* 61459 */ // Label 866: @61459
19733 /* 61459 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(61519), // Rule ID 2036 //
19734 /* 61464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
19735 /* 61467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
19736 /* 61471 */ // (llrint:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, F8RC:{ *:[i32] })))
19737 /* 61471 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
19738 /* 61474 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19739 /* 61478 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19740 /* 61483 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
19741 /* 61487 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::F8RCRegClassID),
19742 /* 61492 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19743 /* 61495 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID),
19744 /* 61499 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19745 /* 61504 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19746 /* 61507 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19747 /* 61509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
19748 /* 61512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
19749 /* 61514 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19750 /* 61517 */ GIR_RootConstrainSelectedInstOperands,
19751 /* 61518 */ // GIR_Coverage, 2036,
19752 /* 61518 */ GIR_EraseRootFromParent_Done,
19753 /* 61519 */ // Label 869: @61519
19754 /* 61519 */ GIM_Reject,
19755 /* 61520 */ // Label 867: @61520
19756 /* 61520 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(61560), // Rule ID 2035 //
19757 /* 61525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
19758 /* 61528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
19759 /* 61532 */ // (llrint:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } ?:{ *:[f64] }:$S))
19760 /* 61532 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19761 /* 61535 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID),
19762 /* 61539 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19763 /* 61544 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // S
19764 /* 61548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19765 /* 61550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
19766 /* 61553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
19767 /* 61555 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19768 /* 61558 */ GIR_RootConstrainSelectedInstOperands,
19769 /* 61559 */ // GIR_Coverage, 2035,
19770 /* 61559 */ GIR_EraseRootFromParent_Done,
19771 /* 61560 */ // Label 870: @61560
19772 /* 61560 */ GIM_Reject,
19773 /* 61561 */ // Label 868: @61561
19774 /* 61561 */ GIM_Reject,
19775 /* 61562 */ // Label 865: @61562
19776 /* 61562 */ GIM_Reject,
19777 /* 61563 */ // Label 16: @61563
19778 /* 61563 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(61582), // Rule ID 639 //
19779 /* 61568 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
19780 /* 61571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
19781 /* 61575 */ // (readcyclecounter:{ *:[i64] }) => (MFTB8:{ *:[i64] })
19782 /* 61575 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MFTB8),
19783 /* 61580 */ GIR_RootConstrainSelectedInstOperands,
19784 /* 61581 */ // GIR_Coverage, 639,
19785 /* 61581 */ GIR_Done,
19786 /* 61582 */ // Label 871: @61582
19787 /* 61582 */ GIM_Reject,
19788 /* 61583 */ // Label 17: @61583
19789 /* 61583 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 874*/ GIMT_Encode4(61658),
19790 /* 61594 */ /*GILLT_s32*//*Label 872*/ GIMT_Encode4(61602),
19791 /* 61598 */ /*GILLT_s64*//*Label 873*/ GIMT_Encode4(61630),
19792 /* 61602 */ // Label 872: @61602
19793 /* 61602 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(61629), // Rule ID 1271 //
19794 /* 61607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC),
19795 /* 61610 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 7,
19796 /* 61614 */ // MIs[0] Operand 1
19797 /* 61614 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
19798 /* 61617 */ // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (SYNC 0:{ *:[i32] })
19799 /* 61617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC),
19800 /* 61620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
19801 /* 61623 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
19802 /* 61627 */ GIR_RootConstrainSelectedInstOperands,
19803 /* 61628 */ // GIR_Coverage, 1271,
19804 /* 61628 */ GIR_EraseRootFromParent_Done,
19805 /* 61629 */ // Label 875: @61629
19806 /* 61629 */ GIM_Reject,
19807 /* 61630 */ // Label 873: @61630
19808 /* 61630 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(61657), // Rule ID 1270 //
19809 /* 61635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC),
19810 /* 61638 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 7,
19811 /* 61642 */ // MIs[0] Operand 1
19812 /* 61642 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
19813 /* 61645 */ // (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] })) => (SYNC 0:{ *:[i32] })
19814 /* 61645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC),
19815 /* 61648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
19816 /* 61651 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
19817 /* 61655 */ GIR_RootConstrainSelectedInstOperands,
19818 /* 61656 */ // GIR_Coverage, 1270,
19819 /* 61656 */ GIR_EraseRootFromParent_Done,
19820 /* 61657 */ // Label 876: @61657
19821 /* 61657 */ GIM_Reject,
19822 /* 61658 */ // Label 874: @61658
19823 /* 61658 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(61707),
19824 /* 61663 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0,
19825 /* 61666 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
19826 /* 61669 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(61689), // Rule ID 1272 //
19827 /* 61674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC),
19828 /* 61677 */ // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (SYNC 1:{ *:[i32] })
19829 /* 61677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC),
19830 /* 61680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19831 /* 61683 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
19832 /* 61687 */ GIR_RootConstrainSelectedInstOperands,
19833 /* 61688 */ // GIR_Coverage, 1272,
19834 /* 61688 */ GIR_EraseRootFromParent_Done,
19835 /* 61689 */ // Label 878: @61689
19836 /* 61689 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(61706), // Rule ID 1273 //
19837 /* 61694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC),
19838 /* 61697 */ // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (MSYNC)
19839 /* 61697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC),
19840 /* 61700 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
19841 /* 61704 */ GIR_RootConstrainSelectedInstOperands,
19842 /* 61705 */ // GIR_Coverage, 1273,
19843 /* 61705 */ GIR_EraseRootFromParent_Done,
19844 /* 61706 */ // Label 879: @61706
19845 /* 61706 */ GIM_Reject,
19846 /* 61707 */ // Label 877: @61707
19847 /* 61707 */ GIM_Reject,
19848 /* 61708 */ // Label 18: @61708
19849 /* 61708 */ GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(61770),
19850 /* 61713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
19851 /* 61716 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
19852 /* 61719 */ GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(61757), // Rule ID 17 //
19853 /* 61724 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
19854 /* 61728 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
19855 /* 61732 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
19856 /* 61736 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
19857 /* 61740 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
19858 /* 61744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19859 /* 61746 */ // (brcond (xor:{ *:[i1] } i1:{ *:[i1] }:$BI, -1:{ *:[i1] }), (bb:{ *:[Other] }):$BD) => (BCn i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD)
19860 /* 61746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCn),
19861 /* 61749 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // BI
19862 /* 61753 */ GIR_RootToRootCopy, /*OpIdx*/1, // BD
19863 /* 61755 */ GIR_RootConstrainSelectedInstOperands,
19864 /* 61756 */ // GIR_Coverage, 17,
19865 /* 61756 */ GIR_EraseRootFromParent_Done,
19866 /* 61757 */ // Label 881: @61757
19867 /* 61757 */ GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(61769), // Rule ID 16 //
19868 /* 61762 */ // (brcond i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD) => (BC i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD)
19869 /* 61762 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::BC),
19870 /* 61767 */ GIR_RootConstrainSelectedInstOperands,
19871 /* 61768 */ // GIR_Coverage, 16,
19872 /* 61768 */ GIR_Done,
19873 /* 61769 */ // Label 882: @61769
19874 /* 61769 */ GIM_Reject,
19875 /* 61770 */ // Label 880: @61770
19876 /* 61770 */ GIM_Reject,
19877 /* 61771 */ // Label 19: @61771
19878 /* 61771 */ GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(61919),
19879 /* 61776 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
19880 /* 61779 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(61806), // Rule ID 1167 //
19881 /* 61784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture),
19882 /* 61787 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmsetdmrz),
19883 /* 61792 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
19884 /* 61795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
19885 /* 61799 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10688:{ *:[iPTR] }) => (DMSETDMRZ:{ *:[v1024i1] })
19886 /* 61799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMSETDMRZ),
19887 /* 61802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
19888 /* 61804 */ GIR_RootConstrainSelectedInstOperands,
19889 /* 61805 */ // GIR_Coverage, 1167,
19890 /* 61805 */ GIR_EraseRootFromParent_Done,
19891 /* 61806 */ // Label 884: @61806
19892 /* 61806 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(61833), // Rule ID 1172 //
19893 /* 61811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
19894 /* 61814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxsetaccz),
19895 /* 61819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
19896 /* 61822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
19897 /* 61826 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10783:{ *:[iPTR] }) => (XXSETACCZ:{ *:[v512i1] })
19898 /* 61826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSETACCZ),
19899 /* 61829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
19900 /* 61831 */ GIR_RootConstrainSelectedInstOperands,
19901 /* 61832 */ // GIR_Coverage, 1172,
19902 /* 61832 */ GIR_EraseRootFromParent_Done,
19903 /* 61833 */ // Label 885: @61833
19904 /* 61833 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(61860), // Rule ID 1173 //
19905 /* 61838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
19906 /* 61841 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxsetaccz),
19907 /* 61846 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
19908 /* 61849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
19909 /* 61853 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10783:{ *:[iPTR] }) => (DMXXSETACCZ:{ *:[v512i1] })
19910 /* 61853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXXSETACCZ),
19911 /* 61856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
19912 /* 61858 */ GIR_RootConstrainSelectedInstOperands,
19913 /* 61859 */ // GIR_Coverage, 1173,
19914 /* 61859 */ GIR_EraseRootFromParent_Done,
19915 /* 61860 */ // Label 886: @61860
19916 /* 61860 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(61884), // Rule ID 4906 //
19917 /* 61865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mfmsr),
19918 /* 61870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19919 /* 61873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
19920 /* 61877 */ // (intrinsic_wo_chain:{ *:[i32] } 10679:{ *:[iPTR] }) => (MFMSR:{ *:[i32] })
19921 /* 61877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFMSR),
19922 /* 61880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
19923 /* 61882 */ GIR_RootConstrainSelectedInstOperands,
19924 /* 61883 */ // GIR_Coverage, 4906,
19925 /* 61883 */ GIR_EraseRootFromParent_Done,
19926 /* 61884 */ // Label 887: @61884
19927 /* 61884 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(61918), // Rule ID 4907 //
19928 /* 61889 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mftbu),
19929 /* 61894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19930 /* 61897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
19931 /* 61901 */ // (intrinsic_wo_chain:{ *:[i32] } 10681:{ *:[iPTR] }) => (MFTB:{ *:[i32] } 269:{ *:[i32] })
19932 /* 61901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFTB),
19933 /* 61904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
19934 /* 61906 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(269),
19935 /* 61916 */ GIR_RootConstrainSelectedInstOperands,
19936 /* 61917 */ // GIR_Coverage, 4907,
19937 /* 61917 */ GIR_EraseRootFromParent_Done,
19938 /* 61918 */ // Label 888: @61918
19939 /* 61918 */ GIM_Reject,
19940 /* 61919 */ // Label 883: @61919
19941 /* 61919 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(65630),
19942 /* 61924 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
19943 /* 61927 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(61963), // Rule ID 1755 //
19944 /* 61932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19945 /* 61935 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrte),
19946 /* 61940 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
19947 /* 61943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
19948 /* 61946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
19949 /* 61950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
19950 /* 61954 */ // (intrinsic_wo_chain:{ *:[f64] } 10650:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XB) => (XSRSQRTEDP:{ *:[f64] } ?:{ *:[f64] }:$XB)
19951 /* 61954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRSQRTEDP),
19952 /* 61957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
19953 /* 61959 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
19954 /* 61961 */ GIR_RootConstrainSelectedInstOperands,
19955 /* 61962 */ // GIR_Coverage, 1755,
19956 /* 61962 */ GIR_EraseRootFromParent_Done,
19957 /* 61963 */ // Label 890: @61963
19958 /* 61963 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(61999), // Rule ID 1946 //
19959 /* 61968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
19960 /* 61971 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrtes),
19961 /* 61976 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19962 /* 61979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19963 /* 61982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
19964 /* 61986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
19965 /* 61990 */ // (intrinsic_wo_chain:{ *:[f32] } 10651:{ *:[iPTR] }, vssrc:{ *:[f32] }:$XB) => (XSRSQRTESP:{ *:[f32] } ?:{ *:[f32] }:$XB)
19966 /* 61990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRSQRTESP),
19967 /* 61993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
19968 /* 61995 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
19969 /* 61997 */ GIR_RootConstrainSelectedInstOperands,
19970 /* 61998 */ // GIR_Coverage, 1946,
19971 /* 61998 */ GIR_EraseRootFromParent_Done,
19972 /* 61999 */ // Label 891: @61999
19973 /* 61999 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(62031), // Rule ID 876 //
19974 /* 62004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19975 /* 62007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpsp),
19976 /* 62012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
19977 /* 62015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
19978 /* 62018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
19979 /* 62022 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10879:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSP:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$XB)
19980 /* 62022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPSP),
19981 /* 62025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
19982 /* 62027 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
19983 /* 62029 */ GIR_RootConstrainSelectedInstOperands,
19984 /* 62030 */ // GIR_Coverage, 876,
19985 /* 62030 */ GIR_EraseRootFromParent_Done,
19986 /* 62031 */ // Label 892: @62031
19987 /* 62031 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(62063), // Rule ID 879 //
19988 /* 62036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
19989 /* 62039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpsxws),
19990 /* 62044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
19991 /* 62047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
19992 /* 62050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
19993 /* 62054 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10880:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSXWS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$XB)
19994 /* 62054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPSXWS),
19995 /* 62057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
19996 /* 62059 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
19997 /* 62061 */ GIR_RootConstrainSelectedInstOperands,
19998 /* 62062 */ // GIR_Coverage, 879,
19999 /* 62062 */ GIR_EraseRootFromParent_Done,
20000 /* 62063 */ // Label 893: @62063
20001 /* 62063 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(62095), // Rule ID 882 //
20002 /* 62068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20003 /* 62071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpuxws),
20004 /* 62076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20005 /* 62079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20006 /* 62082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20007 /* 62086 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10881:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPUXWS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$XB)
20008 /* 62086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPUXWS),
20009 /* 62089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20010 /* 62091 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20011 /* 62093 */ GIR_RootConstrainSelectedInstOperands,
20012 /* 62094 */ // GIR_Coverage, 882,
20013 /* 62094 */ GIR_EraseRootFromParent_Done,
20014 /* 62095 */ // Label 894: @62095
20015 /* 62095 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(62127), // Rule ID 883 //
20016 /* 62100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20017 /* 62103 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspdp),
20018 /* 62108 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20019 /* 62111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20020 /* 62114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20021 /* 62118 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10884:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPDP:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$XB)
20022 /* 62118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPDP),
20023 /* 62121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20024 /* 62123 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20025 /* 62125 */ GIR_RootConstrainSelectedInstOperands,
20026 /* 62126 */ // GIR_Coverage, 883,
20027 /* 62126 */ GIR_EraseRootFromParent_Done,
20028 /* 62127 */ // Label 895: @62127
20029 /* 62127 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(62159), // Rule ID 884 //
20030 /* 62132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20031 /* 62135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspsxds),
20032 /* 62140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20033 /* 62143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20034 /* 62146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20035 /* 62150 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10886:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPSXDS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$XB)
20036 /* 62150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPSXDS),
20037 /* 62153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20038 /* 62155 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20039 /* 62157 */ GIR_RootConstrainSelectedInstOperands,
20040 /* 62158 */ // GIR_Coverage, 884,
20041 /* 62158 */ GIR_EraseRootFromParent_Done,
20042 /* 62159 */ // Label 896: @62159
20043 /* 62159 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(62191), // Rule ID 887 //
20044 /* 62164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20045 /* 62167 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspuxds),
20046 /* 62172 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20047 /* 62175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20048 /* 62178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20049 /* 62182 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10887:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPUXDS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$XB)
20050 /* 62182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPUXDS),
20051 /* 62185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20052 /* 62187 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20053 /* 62189 */ GIR_RootConstrainSelectedInstOperands,
20054 /* 62190 */ // GIR_Coverage, 887,
20055 /* 62190 */ GIR_EraseRootFromParent_Done,
20056 /* 62191 */ // Label 897: @62191
20057 /* 62191 */ GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(62223), // Rule ID 892 //
20058 /* 62196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20059 /* 62199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsxdsp),
20060 /* 62204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20061 /* 62207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20062 /* 62210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20063 /* 62214 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10888:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XB) => (XVCVSXDSP:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$XB)
20064 /* 62214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSXDSP),
20065 /* 62217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20066 /* 62219 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20067 /* 62221 */ GIR_RootConstrainSelectedInstOperands,
20068 /* 62222 */ // GIR_Coverage, 892,
20069 /* 62222 */ GIR_EraseRootFromParent_Done,
20070 /* 62223 */ // Label 898: @62223
20071 /* 62223 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(62255), // Rule ID 897 //
20072 /* 62228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20073 /* 62231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvuxdsp),
20074 /* 62236 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20075 /* 62239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20076 /* 62242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20077 /* 62246 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10890:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XB) => (XVCVUXDSP:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$XB)
20078 /* 62246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVUXDSP),
20079 /* 62249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20080 /* 62251 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20081 /* 62253 */ GIR_RootConstrainSelectedInstOperands,
20082 /* 62254 */ // GIR_Coverage, 897,
20083 /* 62254 */ GIR_EraseRootFromParent_Done,
20084 /* 62255 */ // Label 899: @62255
20085 /* 62255 */ GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(62287), // Rule ID 900 //
20086 /* 62260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20087 /* 62263 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsxwdp),
20088 /* 62268 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20089 /* 62271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20090 /* 62274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20091 /* 62278 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10889:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XB) => (XVCVSXWDP:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$XB)
20092 /* 62278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSXWDP),
20093 /* 62281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20094 /* 62283 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20095 /* 62285 */ GIR_RootConstrainSelectedInstOperands,
20096 /* 62286 */ // GIR_Coverage, 900,
20097 /* 62286 */ GIR_EraseRootFromParent_Done,
20098 /* 62287 */ // Label 900: @62287
20099 /* 62287 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(62319), // Rule ID 901 //
20100 /* 62292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20101 /* 62295 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvuxwdp),
20102 /* 62300 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20103 /* 62303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20104 /* 62306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20105 /* 62310 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10891:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XB) => (XVCVUXWDP:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$XB)
20106 /* 62310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVUXWDP),
20107 /* 62313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20108 /* 62315 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20109 /* 62317 */ GIR_RootConstrainSelectedInstOperands,
20110 /* 62318 */ // GIR_Coverage, 901,
20111 /* 62318 */ GIR_EraseRootFromParent_Done,
20112 /* 62319 */ // Label 901: @62319
20113 /* 62319 */ GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(62351), // Rule ID 1009 //
20114 /* 62324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20115 /* 62327 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_sqrtf128_round_to_odd),
20116 /* 62332 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
20117 /* 62335 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
20118 /* 62338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20119 /* 62342 */ // (intrinsic_wo_chain:{ *:[f128] } 10815:{ *:[iPTR] }, f128:{ *:[f128] }:$RB) => (XSSQRTQPO:{ *:[f128] } f128:{ *:[f128] }:$RB)
20120 /* 62342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSSQRTQPO),
20121 /* 62345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
20122 /* 62347 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
20123 /* 62349 */ GIR_RootConstrainSelectedInstOperands,
20124 /* 62350 */ // GIR_Coverage, 1009,
20125 /* 62350 */ GIR_EraseRootFromParent_Done,
20126 /* 62351 */ // Label 902: @62351
20127 /* 62351 */ GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(62383), // Rule ID 1016 //
20128 /* 62356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20129 /* 62359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_truncf128_round_to_odd),
20130 /* 62364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20131 /* 62367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
20132 /* 62370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VFRCRegClassID),
20133 /* 62374 */ // (intrinsic_wo_chain:{ *:[f64] } 10842:{ *:[iPTR] }, f128:{ *:[f128] }:$RB) => (XSCVQPDPO:{ *:[f64] } f128:{ *:[f128] }:$RB)
20134 /* 62374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVQPDPO),
20135 /* 62377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
20136 /* 62379 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
20137 /* 62381 */ GIR_RootConstrainSelectedInstOperands,
20138 /* 62382 */ // GIR_Coverage, 1016,
20139 /* 62382 */ GIR_EraseRootFromParent_Done,
20140 /* 62383 */ // Label 903: @62383
20141 /* 62383 */ GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(62415), // Rule ID 1025 //
20142 /* 62388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20143 /* 62391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsphp),
20144 /* 62396 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20145 /* 62399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20146 /* 62402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20147 /* 62406 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10885:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPHP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
20148 /* 62406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPHP),
20149 /* 62409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20150 /* 62411 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20151 /* 62413 */ GIR_RootConstrainSelectedInstOperands,
20152 /* 62414 */ // GIR_Coverage, 1025,
20153 /* 62414 */ GIR_EraseRootFromParent_Done,
20154 /* 62415 */ // Label 904: @62415
20155 /* 62415 */ GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(62447), // Rule ID 1029 //
20156 /* 62420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20157 /* 62423 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxexpdp),
20158 /* 62428 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20159 /* 62431 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20160 /* 62434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20161 /* 62438 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10913:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVXEXPDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB)
20162 /* 62438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXEXPDP),
20163 /* 62441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20164 /* 62443 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20165 /* 62445 */ GIR_RootConstrainSelectedInstOperands,
20166 /* 62446 */ // GIR_Coverage, 1029,
20167 /* 62446 */ GIR_EraseRootFromParent_Done,
20168 /* 62447 */ // Label 905: @62447
20169 /* 62447 */ GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(62479), // Rule ID 1030 //
20170 /* 62452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20171 /* 62455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxexpsp),
20172 /* 62460 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20173 /* 62463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20174 /* 62466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20175 /* 62470 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10914:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVXEXPSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB)
20176 /* 62470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXEXPSP),
20177 /* 62473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20178 /* 62475 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20179 /* 62477 */ GIR_RootConstrainSelectedInstOperands,
20180 /* 62478 */ // GIR_Coverage, 1030,
20181 /* 62478 */ GIR_EraseRootFromParent_Done,
20182 /* 62479 */ // Label 906: @62479
20183 /* 62479 */ GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(62511), // Rule ID 1031 //
20184 /* 62484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20185 /* 62487 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxsigdp),
20186 /* 62492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20187 /* 62495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20188 /* 62498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20189 /* 62502 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10915:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVXSIGDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB)
20190 /* 62502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXSIGDP),
20191 /* 62505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20192 /* 62507 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20193 /* 62509 */ GIR_RootConstrainSelectedInstOperands,
20194 /* 62510 */ // GIR_Coverage, 1031,
20195 /* 62510 */ GIR_EraseRootFromParent_Done,
20196 /* 62511 */ // Label 907: @62511
20197 /* 62511 */ GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(62543), // Rule ID 1032 //
20198 /* 62516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20199 /* 62519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxsigsp),
20200 /* 62524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20201 /* 62527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20202 /* 62530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20203 /* 62534 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10916:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVXSIGSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB)
20204 /* 62534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXSIGSP),
20205 /* 62537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20206 /* 62539 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
20207 /* 62541 */ GIR_RootConstrainSelectedInstOperands,
20208 /* 62542 */ // GIR_Coverage, 1032,
20209 /* 62542 */ GIR_EraseRootFromParent_Done,
20210 /* 62543 */ // Label 908: @62543
20211 /* 62543 */ GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(62598), // Rule ID 1663 //
20212 /* 62548 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20213 /* 62551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtsqrtdp),
20214 /* 62556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20215 /* 62559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20216 /* 62562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
20217 /* 62566 */ // (intrinsic_wo_chain:{ *:[i32] } 10909:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTSQRTDP:{ *:[i32] } ?:{ *:[v2f64] }:$A), GPRC:{ *:[i32] })
20218 /* 62566 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20219 /* 62569 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTSQRTDP),
20220 /* 62573 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20221 /* 62578 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A
20222 /* 62582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20223 /* 62584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20224 /* 62587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20225 /* 62589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20226 /* 62592 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
20227 /* 62597 */ // GIR_Coverage, 1663,
20228 /* 62597 */ GIR_EraseRootFromParent_Done,
20229 /* 62598 */ // Label 909: @62598
20230 /* 62598 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(62653), // Rule ID 1664 //
20231 /* 62603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20232 /* 62606 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtsqrtsp),
20233 /* 62611 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20234 /* 62614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20235 /* 62617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
20236 /* 62621 */ // (intrinsic_wo_chain:{ *:[i32] } 10910:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTSQRTSP:{ *:[i32] } ?:{ *:[v4f32] }:$A), GPRC:{ *:[i32] })
20237 /* 62621 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20238 /* 62624 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTSQRTSP),
20239 /* 62628 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20240 /* 62633 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A
20241 /* 62637 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20242 /* 62639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20243 /* 62642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20244 /* 62644 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20245 /* 62647 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
20246 /* 62652 */ // GIR_Coverage, 1664,
20247 /* 62652 */ GIR_EraseRootFromParent_Done,
20248 /* 62653 */ // Label 910: @62653
20249 /* 62653 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(62685), // Rule ID 1665 //
20250 /* 62658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20251 /* 62661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvresp),
20252 /* 62666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20253 /* 62669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20254 /* 62672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20255 /* 62676 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10902:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (XVRESP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A)
20256 /* 62676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRESP),
20257 /* 62679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20258 /* 62681 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
20259 /* 62683 */ GIR_RootConstrainSelectedInstOperands,
20260 /* 62684 */ // GIR_Coverage, 1665,
20261 /* 62684 */ GIR_EraseRootFromParent_Done,
20262 /* 62685 */ // Label 911: @62685
20263 /* 62685 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(62717), // Rule ID 1666 //
20264 /* 62690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20265 /* 62693 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvredp),
20266 /* 62698 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20267 /* 62701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20268 /* 62704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20269 /* 62708 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10901:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (XVREDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A)
20270 /* 62708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVREDP),
20271 /* 62711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20272 /* 62713 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
20273 /* 62715 */ GIR_RootConstrainSelectedInstOperands,
20274 /* 62716 */ // GIR_Coverage, 1666,
20275 /* 62716 */ GIR_EraseRootFromParent_Done,
20276 /* 62717 */ // Label 912: @62717
20277 /* 62717 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(62749), // Rule ID 1667 //
20278 /* 62722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20279 /* 62725 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvrsqrtesp),
20280 /* 62730 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20281 /* 62733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20282 /* 62736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20283 /* 62740 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10905:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (XVRSQRTESP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A)
20284 /* 62740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRSQRTESP),
20285 /* 62743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20286 /* 62745 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
20287 /* 62747 */ GIR_RootConstrainSelectedInstOperands,
20288 /* 62748 */ // GIR_Coverage, 1667,
20289 /* 62748 */ GIR_EraseRootFromParent_Done,
20290 /* 62749 */ // Label 913: @62749
20291 /* 62749 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(62781), // Rule ID 1668 //
20292 /* 62754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20293 /* 62757 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvrsqrtedp),
20294 /* 62762 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20295 /* 62765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20296 /* 62768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20297 /* 62772 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10904:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (XVRSQRTEDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A)
20298 /* 62772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRSQRTEDP),
20299 /* 62775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20300 /* 62777 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
20301 /* 62779 */ GIR_RootConstrainSelectedInstOperands,
20302 /* 62780 */ // GIR_Coverage, 1668,
20303 /* 62780 */ GIR_EraseRootFromParent_Done,
20304 /* 62781 */ // Label 914: @62781
20305 /* 62781 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(62813), // Rule ID 1754 //
20306 /* 62786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20307 /* 62789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fre),
20308 /* 62794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20309 /* 62797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20310 /* 62800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
20311 /* 62804 */ // (intrinsic_wo_chain:{ *:[f64] } 10648:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSREDP:{ *:[f64] } ?:{ *:[f64] }:$A)
20312 /* 62804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSREDP),
20313 /* 62807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20314 /* 62809 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
20315 /* 62811 */ GIR_RootConstrainSelectedInstOperands,
20316 /* 62812 */ // GIR_Coverage, 1754,
20317 /* 62812 */ GIR_EraseRootFromParent_Done,
20318 /* 62813 */ // Label 915: @62813
20319 /* 62813 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(62845), // Rule ID 1756 //
20320 /* 62818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20321 /* 62821 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabs),
20322 /* 62826 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20323 /* 62829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20324 /* 62832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
20325 /* 62836 */ // (intrinsic_wo_chain:{ *:[f64] } 10643:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSNABSDP:{ *:[f64] } ?:{ *:[f64] }:$A)
20326 /* 62836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDP),
20327 /* 62839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20328 /* 62841 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
20329 /* 62843 */ GIR_RootConstrainSelectedInstOperands,
20330 /* 62844 */ // GIR_Coverage, 1756,
20331 /* 62844 */ GIR_EraseRootFromParent_Done,
20332 /* 62845 */ // Label 916: @62845
20333 /* 62845 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(62877), // Rule ID 1757 //
20334 /* 62850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
20335 /* 62853 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabss),
20336 /* 62858 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20337 /* 62861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20338 /* 62864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
20339 /* 62868 */ // (intrinsic_wo_chain:{ *:[f32] } 10644:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (XSNABSDPs:{ *:[f32] } ?:{ *:[f32] }:$A)
20340 /* 62868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDPs),
20341 /* 62871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20342 /* 62873 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
20343 /* 62875 */ GIR_RootConstrainSelectedInstOperands,
20344 /* 62876 */ // GIR_Coverage, 1757,
20345 /* 62876 */ GIR_EraseRootFromParent_Done,
20346 /* 62877 */ // Label 917: @62877
20347 /* 62877 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(62909), // Rule ID 1941 //
20348 /* 62882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
20349 /* 62885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fres),
20350 /* 62890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20351 /* 62893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20352 /* 62896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
20353 /* 62900 */ // (intrinsic_wo_chain:{ *:[f32] } 10649:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (XSRESP:{ *:[f32] } ?:{ *:[f32] }:$A)
20354 /* 62900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRESP),
20355 /* 62903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20356 /* 62905 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
20357 /* 62907 */ GIR_RootConstrainSelectedInstOperands,
20358 /* 62908 */ // GIR_Coverage, 1941,
20359 /* 62908 */ GIR_EraseRootFromParent_Done,
20360 /* 62909 */ // Label 918: @62909
20361 /* 62909 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(62993), // Rule ID 1942 //
20362 /* 62914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
20363 /* 62917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_extract_exp),
20364 /* 62922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20365 /* 62925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20366 /* 62928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
20367 /* 62932 */ // (intrinsic_wo_chain:{ *:[i32] } 10628:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (EXTRACT_SUBREG:{ *:[i32] } (XSXEXPDP:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f64] }:$A, VSFRC:{ *:[i32] })), sub_32:{ *:[i32] })
20368 /* 62932 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
20369 /* 62935 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20370 /* 62939 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20371 /* 62944 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A
20372 /* 62948 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
20373 /* 62953 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20374 /* 62956 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSXEXPDP),
20375 /* 62960 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20376 /* 62965 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20377 /* 62968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20378 /* 62970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20379 /* 62973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20380 /* 62975 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
20381 /* 62982 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
20382 /* 62987 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
20383 /* 62992 */ // GIR_Coverage, 1942,
20384 /* 62992 */ GIR_EraseRootFromParent_Done,
20385 /* 62993 */ // Label 919: @62993
20386 /* 62993 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(63047), // Rule ID 1943 //
20387 /* 62998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
20388 /* 63001 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_extract_sig),
20389 /* 63006 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20390 /* 63009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20391 /* 63012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
20392 /* 63016 */ // (intrinsic_wo_chain:{ *:[i64] } 10629:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSXSIGDP:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f64] }:$A, VSFRC:{ *:[i32] }))
20393 /* 63016 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20394 /* 63019 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20395 /* 63023 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20396 /* 63028 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A
20397 /* 63032 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
20398 /* 63037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSXSIGDP),
20399 /* 63040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
20400 /* 63042 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20401 /* 63045 */ GIR_RootConstrainSelectedInstOperands,
20402 /* 63046 */ // GIR_Coverage, 1943,
20403 /* 63046 */ GIR_EraseRootFromParent_Done,
20404 /* 63047 */ // Label 920: @63047
20405 /* 63047 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(63101), // Rule ID 2158 //
20406 /* 63052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20407 /* 63055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvhpsp),
20408 /* 63060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20409 /* 63063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20410 /* 63066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
20411 /* 63070 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10882:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$A) => (XVCVHPSP:{ *:[v4f32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] }))
20412 /* 63070 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
20413 /* 63073 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20414 /* 63077 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20415 /* 63082 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A
20416 /* 63086 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
20417 /* 63091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVHPSP),
20418 /* 63094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
20419 /* 63096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20420 /* 63099 */ GIR_RootConstrainSelectedInstOperands,
20421 /* 63100 */ // GIR_Coverage, 2158,
20422 /* 63100 */ GIR_EraseRootFromParent_Done,
20423 /* 63101 */ // Label 921: @63101
20424 /* 63101 */ GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(63181), // Rule ID 2172 //
20425 /* 63106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
20426 /* 63109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_scalar_extract_expq),
20427 /* 63114 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20428 /* 63117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
20429 /* 63120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
20430 /* 63124 */ // (intrinsic_wo_chain:{ *:[i64] } 10806:{ *:[iPTR] }, f128:{ *:[f128] }:$vA) => (MFVSRD:{ *:[i64] } (EXTRACT_SUBREG:{ *:[f64] } (XSXEXPQP:{ *:[v2i64] } ?:{ *:[f128] }:$vA), sub_64:{ *:[i32] }))
20431 /* 63124 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
20432 /* 63127 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSXEXPQP),
20433 /* 63131 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20434 /* 63136 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vA
20435 /* 63140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20436 /* 63142 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20437 /* 63145 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20438 /* 63149 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20439 /* 63154 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_64),
20440 /* 63161 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VFRCRegClassID),
20441 /* 63166 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::VRRCRegClassID),
20442 /* 63171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
20443 /* 63174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
20444 /* 63176 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20445 /* 63179 */ GIR_RootConstrainSelectedInstOperands,
20446 /* 63180 */ // GIR_Coverage, 2172,
20447 /* 63180 */ GIR_EraseRootFromParent_Done,
20448 /* 63181 */ // Label 922: @63181
20449 /* 63181 */ GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(63224), // Rule ID 1097 //
20450 /* 63186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
20451 /* 63189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrbm),
20452 /* 63194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20453 /* 63197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20454 /* 63200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20455 /* 63204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20456 /* 63208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20457 /* 63212 */ // MIs[1] Operand 1
20458 /* 63212 */ // No operand predicates
20459 /* 63212 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20460 /* 63214 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10293:{ *:[iPTR] }, (imm:{ *:[i64] }):$D) => (MTVSRBMI:{ *:[v16i8] } (imm:{ *:[i64] }):$D)
20461 /* 63214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRBMI),
20462 /* 63217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
20463 /* 63219 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D
20464 /* 63222 */ GIR_RootConstrainSelectedInstOperands,
20465 /* 63223 */ // GIR_Coverage, 1097,
20466 /* 63223 */ GIR_EraseRootFromParent_Done,
20467 /* 63224 */ // Label 923: @63224
20468 /* 63224 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(63257), // Rule ID 4858 //
20469 /* 63229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrte),
20470 /* 63234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20471 /* 63237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20472 /* 63240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
20473 /* 63244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
20474 /* 63248 */ // (intrinsic_wo_chain:{ *:[f64] } 10650:{ *:[iPTR] }, f8rc:{ *:[f64] }:$frB) => (FRSQRTE:{ *:[f64] } ?:{ *:[f64] }:$frB)
20475 /* 63248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRSQRTE),
20476 /* 63251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
20477 /* 63253 */ GIR_RootToRootCopy, /*OpIdx*/2, // frB
20478 /* 63255 */ GIR_RootConstrainSelectedInstOperands,
20479 /* 63256 */ // GIR_Coverage, 4858,
20480 /* 63256 */ GIR_EraseRootFromParent_Done,
20481 /* 63257 */ // Label 924: @63257
20482 /* 63257 */ GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(63290), // Rule ID 4859 //
20483 /* 63262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrtes),
20484 /* 63267 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20485 /* 63270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20486 /* 63273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
20487 /* 63277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
20488 /* 63281 */ // (intrinsic_wo_chain:{ *:[f32] } 10651:{ *:[iPTR] }, f4rc:{ *:[f32] }:$frB) => (FRSQRTES:{ *:[f32] } ?:{ *:[f32] }:$frB)
20489 /* 63281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRSQRTES),
20490 /* 63284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
20491 /* 63286 */ GIR_RootToRootCopy, /*OpIdx*/2, // frB
20492 /* 63288 */ GIR_RootConstrainSelectedInstOperands,
20493 /* 63289 */ // GIR_Coverage, 4859,
20494 /* 63289 */ GIR_EraseRootFromParent_Done,
20495 /* 63290 */ // Label 925: @63290
20496 /* 63290 */ GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(63319), // Rule ID 73 //
20497 /* 63295 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_popcntb),
20498 /* 63300 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20499 /* 63303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20500 /* 63306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
20501 /* 63310 */ // (intrinsic_wo_chain:{ *:[i32] } 10801:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (POPCNTB:{ *:[i32] } i32:{ *:[i32] }:$RST)
20502 /* 63310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::POPCNTB),
20503 /* 63313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
20504 /* 63315 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
20505 /* 63317 */ GIR_RootConstrainSelectedInstOperands,
20506 /* 63318 */ // GIR_Coverage, 73,
20507 /* 63318 */ GIR_EraseRootFromParent_Done,
20508 /* 63319 */ // Label 926: @63319
20509 /* 63319 */ GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(63348), // Rule ID 74 //
20510 /* 63324 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cdtbcd),
20511 /* 63329 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20512 /* 63332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20513 /* 63335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
20514 /* 63339 */ // (intrinsic_wo_chain:{ *:[i32] } 10587:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (CDTBCD:{ *:[i32] } i32:{ *:[i32] }:$RST)
20515 /* 63339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CDTBCD),
20516 /* 63342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
20517 /* 63344 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
20518 /* 63346 */ GIR_RootConstrainSelectedInstOperands,
20519 /* 63347 */ // GIR_Coverage, 74,
20520 /* 63347 */ GIR_EraseRootFromParent_Done,
20521 /* 63348 */ // Label 927: @63348
20522 /* 63348 */ GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(63377), // Rule ID 75 //
20523 /* 63353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cbcdtd),
20524 /* 63358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20525 /* 63361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20526 /* 63364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
20527 /* 63368 */ // (intrinsic_wo_chain:{ *:[i32] } 10585:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (CBCDTD:{ *:[i32] } i32:{ *:[i32] }:$RST)
20528 /* 63368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CBCDTD),
20529 /* 63371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
20530 /* 63373 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
20531 /* 63375 */ GIR_RootConstrainSelectedInstOperands,
20532 /* 63376 */ // GIR_Coverage, 75,
20533 /* 63376 */ GIR_EraseRootFromParent_Done,
20534 /* 63377 */ // Label 928: @63377
20535 /* 63377 */ GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(63409), // Rule ID 321 //
20536 /* 63382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20537 /* 63385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexptefp),
20538 /* 63390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20539 /* 63393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20540 /* 63396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20541 /* 63400 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10400:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VEXPTEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB)
20542 /* 63400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPTEFP),
20543 /* 63403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20544 /* 63405 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20545 /* 63407 */ GIR_RootConstrainSelectedInstOperands,
20546 /* 63408 */ // GIR_Coverage, 321,
20547 /* 63408 */ GIR_EraseRootFromParent_Done,
20548 /* 63409 */ // Label 929: @63409
20549 /* 63409 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(63441), // Rule ID 322 //
20550 /* 63414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20551 /* 63417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vlogefp),
20552 /* 63422 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20553 /* 63425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20554 /* 63428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20555 /* 63432 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10438:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VLOGEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB)
20556 /* 63432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VLOGEFP),
20557 /* 63435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20558 /* 63437 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20559 /* 63439 */ GIR_RootConstrainSelectedInstOperands,
20560 /* 63440 */ // GIR_Coverage, 322,
20561 /* 63440 */ GIR_EraseRootFromParent_Done,
20562 /* 63441 */ // Label 930: @63441
20563 /* 63441 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(63473), // Rule ID 363 //
20564 /* 63446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20565 /* 63449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrefp),
20566 /* 63454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20567 /* 63457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20568 /* 63460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20569 /* 63464 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10506:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VREFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB)
20570 /* 63464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VREFP),
20571 /* 63467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20572 /* 63469 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20573 /* 63471 */ GIR_RootConstrainSelectedInstOperands,
20574 /* 63472 */ // GIR_Coverage, 363,
20575 /* 63472 */ GIR_EraseRootFromParent_Done,
20576 /* 63473 */ // Label 931: @63473
20577 /* 63473 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(63505), // Rule ID 364 //
20578 /* 63478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20579 /* 63481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfim),
20580 /* 63486 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20581 /* 63489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20582 /* 63492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20583 /* 63496 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10507:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIM:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB)
20584 /* 63496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIM),
20585 /* 63499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20586 /* 63501 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20587 /* 63503 */ GIR_RootConstrainSelectedInstOperands,
20588 /* 63504 */ // GIR_Coverage, 364,
20589 /* 63504 */ GIR_EraseRootFromParent_Done,
20590 /* 63505 */ // Label 932: @63505
20591 /* 63505 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(63537), // Rule ID 365 //
20592 /* 63510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20593 /* 63513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfin),
20594 /* 63518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20595 /* 63521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20596 /* 63524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20597 /* 63528 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10508:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIN:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB)
20598 /* 63528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIN),
20599 /* 63531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20600 /* 63533 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20601 /* 63535 */ GIR_RootConstrainSelectedInstOperands,
20602 /* 63536 */ // GIR_Coverage, 365,
20603 /* 63536 */ GIR_EraseRootFromParent_Done,
20604 /* 63537 */ // Label 933: @63537
20605 /* 63537 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(63569), // Rule ID 366 //
20606 /* 63542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20607 /* 63545 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfip),
20608 /* 63550 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20609 /* 63553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20610 /* 63556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20611 /* 63560 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10509:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB)
20612 /* 63560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIP),
20613 /* 63563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20614 /* 63565 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20615 /* 63567 */ GIR_RootConstrainSelectedInstOperands,
20616 /* 63568 */ // GIR_Coverage, 366,
20617 /* 63568 */ GIR_EraseRootFromParent_Done,
20618 /* 63569 */ // Label 934: @63569
20619 /* 63569 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(63601), // Rule ID 367 //
20620 /* 63574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20621 /* 63577 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfiz),
20622 /* 63582 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20623 /* 63585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20624 /* 63588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20625 /* 63592 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10510:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIZ:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB)
20626 /* 63592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIZ),
20627 /* 63595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20628 /* 63597 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20629 /* 63599 */ GIR_RootConstrainSelectedInstOperands,
20630 /* 63600 */ // GIR_Coverage, 367,
20631 /* 63600 */ GIR_EraseRootFromParent_Done,
20632 /* 63601 */ // Label 935: @63601
20633 /* 63601 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(63633), // Rule ID 368 //
20634 /* 63606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20635 /* 63609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrsqrtefp),
20636 /* 63614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20637 /* 63617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20638 /* 63620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20639 /* 63624 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10521:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRSQRTEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB)
20640 /* 63624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRSQRTEFP),
20641 /* 63627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20642 /* 63629 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20643 /* 63631 */ GIR_RootConstrainSelectedInstOperands,
20644 /* 63632 */ // GIR_Coverage, 368,
20645 /* 63632 */ GIR_EraseRootFromParent_Done,
20646 /* 63633 */ // Label 936: @63633
20647 /* 63633 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(63665), // Rule ID 419 //
20648 /* 63638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20649 /* 63641 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhpx),
20650 /* 63646 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20651 /* 63649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20652 /* 63652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20653 /* 63656 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10563:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKHPX:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB)
20654 /* 63656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHPX),
20655 /* 63659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20656 /* 63661 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20657 /* 63663 */ GIR_RootConstrainSelectedInstOperands,
20658 /* 63664 */ // GIR_Coverage, 419,
20659 /* 63664 */ GIR_EraseRootFromParent_Done,
20660 /* 63665 */ // Label 937: @63665
20661 /* 63665 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(63697), // Rule ID 420 //
20662 /* 63670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20663 /* 63673 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsb),
20664 /* 63678 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20665 /* 63681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20666 /* 63684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20667 /* 63688 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10564:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VUPKHSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VB)
20668 /* 63688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSB),
20669 /* 63691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20670 /* 63693 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20671 /* 63695 */ GIR_RootConstrainSelectedInstOperands,
20672 /* 63696 */ // GIR_Coverage, 420,
20673 /* 63696 */ GIR_EraseRootFromParent_Done,
20674 /* 63697 */ // Label 938: @63697
20675 /* 63697 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(63729), // Rule ID 421 //
20676 /* 63702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20677 /* 63705 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsh),
20678 /* 63710 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20679 /* 63713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20680 /* 63716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20681 /* 63720 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10565:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKHSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB)
20682 /* 63720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSH),
20683 /* 63723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20684 /* 63725 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20685 /* 63727 */ GIR_RootConstrainSelectedInstOperands,
20686 /* 63728 */ // GIR_Coverage, 421,
20687 /* 63728 */ GIR_EraseRootFromParent_Done,
20688 /* 63729 */ // Label 939: @63729
20689 /* 63729 */ GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(63761), // Rule ID 422 //
20690 /* 63734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20691 /* 63737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklpx),
20692 /* 63742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20693 /* 63745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20694 /* 63748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20695 /* 63752 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10567:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKLPX:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB)
20696 /* 63752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLPX),
20697 /* 63755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20698 /* 63757 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20699 /* 63759 */ GIR_RootConstrainSelectedInstOperands,
20700 /* 63760 */ // GIR_Coverage, 422,
20701 /* 63760 */ GIR_EraseRootFromParent_Done,
20702 /* 63761 */ // Label 940: @63761
20703 /* 63761 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(63793), // Rule ID 423 //
20704 /* 63766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20705 /* 63769 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsb),
20706 /* 63774 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20707 /* 63777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20708 /* 63780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20709 /* 63784 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10568:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VUPKLSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VB)
20710 /* 63784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSB),
20711 /* 63787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20712 /* 63789 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20713 /* 63791 */ GIR_RootConstrainSelectedInstOperands,
20714 /* 63792 */ // GIR_Coverage, 423,
20715 /* 63792 */ GIR_EraseRootFromParent_Done,
20716 /* 63793 */ // Label 941: @63793
20717 /* 63793 */ GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(63825), // Rule ID 424 //
20718 /* 63798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
20719 /* 63801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsh),
20720 /* 63806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20721 /* 63809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20722 /* 63812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20723 /* 63816 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10569:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKLSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB)
20724 /* 63816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSH),
20725 /* 63819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20726 /* 63821 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20727 /* 63823 */ GIR_RootConstrainSelectedInstOperands,
20728 /* 63824 */ // GIR_Coverage, 424,
20729 /* 63824 */ GIR_EraseRootFromParent_Done,
20730 /* 63825 */ // Label 942: @63825
20731 /* 63825 */ GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(63857), // Rule ID 504 //
20732 /* 63830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
20733 /* 63833 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsw),
20734 /* 63838 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20735 /* 63841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20736 /* 63844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20737 /* 63848 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10566:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VUPKHSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB)
20738 /* 63848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSW),
20739 /* 63851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20740 /* 63853 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20741 /* 63855 */ GIR_RootConstrainSelectedInstOperands,
20742 /* 63856 */ // GIR_Coverage, 504,
20743 /* 63856 */ GIR_EraseRootFromParent_Done,
20744 /* 63857 */ // Label 943: @63857
20745 /* 63857 */ GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(63889), // Rule ID 505 //
20746 /* 63862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
20747 /* 63865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsw),
20748 /* 63870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20749 /* 63873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20750 /* 63876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20751 /* 63880 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10570:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VUPKLSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB)
20752 /* 63880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSW),
20753 /* 63883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20754 /* 63885 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20755 /* 63887 */ GIR_RootConstrainSelectedInstOperands,
20756 /* 63888 */ // GIR_Coverage, 505,
20757 /* 63888 */ GIR_EraseRootFromParent_Done,
20758 /* 63889 */ // Label 944: @63889
20759 /* 63889 */ GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(63921), // Rule ID 506 //
20760 /* 63894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
20761 /* 63897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vgbbd),
20762 /* 63902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20763 /* 63905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20764 /* 63908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20765 /* 63912 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10420:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VGBBD:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB)
20766 /* 63912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VGBBD),
20767 /* 63915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20768 /* 63917 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20769 /* 63919 */ GIR_RootConstrainSelectedInstOperands,
20770 /* 63920 */ // GIR_Coverage, 506,
20771 /* 63920 */ GIR_EraseRootFromParent_Done,
20772 /* 63921 */ // Label 945: @63921
20773 /* 63921 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(63953), // Rule ID 514 //
20774 /* 63926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto),
20775 /* 63929 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vsbox),
20776 /* 63934 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20777 /* 63937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20778 /* 63940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20779 /* 63944 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10275:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA) => (VSBOX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA)
20780 /* 63944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSBOX),
20781 /* 63947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20782 /* 63949 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
20783 /* 63951 */ GIR_RootConstrainSelectedInstOperands,
20784 /* 63952 */ // GIR_Coverage, 514,
20785 /* 63952 */ GIR_EraseRootFromParent_Done,
20786 /* 63953 */ // Label 946: @63953
20787 /* 63953 */ GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(63985), // Rule ID 530 //
20788 /* 63958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20789 /* 63961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclzlsbb),
20790 /* 63966 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20791 /* 63969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20792 /* 63972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
20793 /* 63976 */ // (intrinsic_wo_chain:{ *:[i32] } 10330:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VCLZLSBB:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB)
20794 /* 63976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLZLSBB),
20795 /* 63979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20796 /* 63981 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20797 /* 63983 */ GIR_RootConstrainSelectedInstOperands,
20798 /* 63984 */ // GIR_Coverage, 530,
20799 /* 63984 */ GIR_EraseRootFromParent_Done,
20800 /* 63985 */ // Label 947: @63985
20801 /* 63985 */ GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(64017), // Rule ID 531 //
20802 /* 63990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20803 /* 63993 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctzlsbb),
20804 /* 63998 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20805 /* 64001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20806 /* 64004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
20807 /* 64008 */ // (intrinsic_wo_chain:{ *:[i32] } 10388:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VCTZLSBB:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB)
20808 /* 64008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTZLSBB),
20809 /* 64011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20810 /* 64013 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20811 /* 64015 */ GIR_RootConstrainSelectedInstOperands,
20812 /* 64016 */ // GIR_Coverage, 531,
20813 /* 64016 */ GIR_EraseRootFromParent_Done,
20814 /* 64017 */ // Label 948: @64017
20815 /* 64017 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(64049), // Rule ID 536 //
20816 /* 64022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20817 /* 64025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsb2w),
20818 /* 64030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20819 /* 64033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20820 /* 64036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20821 /* 64040 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10415:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTSB2W:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$VB)
20822 /* 64040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSB2W),
20823 /* 64043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20824 /* 64045 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20825 /* 64047 */ GIR_RootConstrainSelectedInstOperands,
20826 /* 64048 */ // GIR_Coverage, 536,
20827 /* 64048 */ GIR_EraseRootFromParent_Done,
20828 /* 64049 */ // Label 949: @64049
20829 /* 64049 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(64081), // Rule ID 537 //
20830 /* 64054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20831 /* 64057 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsh2w),
20832 /* 64062 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20833 /* 64065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20834 /* 64068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20835 /* 64072 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10418:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTSH2W:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB)
20836 /* 64072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSH2W),
20837 /* 64075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20838 /* 64077 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20839 /* 64079 */ GIR_RootConstrainSelectedInstOperands,
20840 /* 64080 */ // GIR_Coverage, 537,
20841 /* 64080 */ GIR_EraseRootFromParent_Done,
20842 /* 64081 */ // Label 950: @64081
20843 /* 64081 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(64113), // Rule ID 538 //
20844 /* 64086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20845 /* 64089 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsb2d),
20846 /* 64094 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20847 /* 64097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20848 /* 64100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20849 /* 64104 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10414:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTSB2D:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$VB)
20850 /* 64104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSB2D),
20851 /* 64107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20852 /* 64109 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20853 /* 64111 */ GIR_RootConstrainSelectedInstOperands,
20854 /* 64112 */ // GIR_Coverage, 538,
20855 /* 64112 */ GIR_EraseRootFromParent_Done,
20856 /* 64113 */ // Label 951: @64113
20857 /* 64113 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(64145), // Rule ID 539 //
20858 /* 64118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20859 /* 64121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsh2d),
20860 /* 64126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20861 /* 64129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20862 /* 64132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20863 /* 64136 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10417:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTSH2D:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$VB)
20864 /* 64136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSH2D),
20865 /* 64139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20866 /* 64141 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20867 /* 64143 */ GIR_RootConstrainSelectedInstOperands,
20868 /* 64144 */ // GIR_Coverage, 539,
20869 /* 64144 */ GIR_EraseRootFromParent_Done,
20870 /* 64145 */ // Label 952: @64145
20871 /* 64145 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(64177), // Rule ID 540 //
20872 /* 64150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20873 /* 64153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsw2d),
20874 /* 64158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20875 /* 64161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20876 /* 64164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20877 /* 64168 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10419:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXTSW2D:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB)
20878 /* 64168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSW2D),
20879 /* 64171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20880 /* 64173 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20881 /* 64175 */ GIR_RootConstrainSelectedInstOperands,
20882 /* 64176 */ // GIR_Coverage, 540,
20883 /* 64176 */ GIR_EraseRootFromParent_Done,
20884 /* 64177 */ // Label 953: @64177
20885 /* 64177 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(64209), // Rule ID 543 //
20886 /* 64182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20887 /* 64185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybw),
20888 /* 64190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20889 /* 64193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20890 /* 64196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20891 /* 64200 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10505:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VPRTYBW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB)
20892 /* 64200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBW),
20893 /* 64203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20894 /* 64205 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20895 /* 64207 */ GIR_RootConstrainSelectedInstOperands,
20896 /* 64208 */ // GIR_Coverage, 543,
20897 /* 64208 */ GIR_EraseRootFromParent_Done,
20898 /* 64209 */ // Label 954: @64209
20899 /* 64209 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(64241), // Rule ID 544 //
20900 /* 64214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20901 /* 64217 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybd),
20902 /* 64222 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20903 /* 64225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20904 /* 64228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20905 /* 64232 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10503:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VPRTYBD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB)
20906 /* 64232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBD),
20907 /* 64235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20908 /* 64237 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20909 /* 64239 */ GIR_RootConstrainSelectedInstOperands,
20910 /* 64240 */ // GIR_Coverage, 544,
20911 /* 64240 */ GIR_EraseRootFromParent_Done,
20912 /* 64241 */ // Label 955: @64241
20913 /* 64241 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(64273), // Rule ID 545 //
20914 /* 64246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20915 /* 64249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybq),
20916 /* 64254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
20917 /* 64257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
20918 /* 64260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20919 /* 64264 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10504:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VPRTYBQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VB)
20920 /* 64264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBQ),
20921 /* 64267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20922 /* 64269 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20923 /* 64271 */ GIR_RootConstrainSelectedInstOperands,
20924 /* 64272 */ // GIR_Coverage, 545,
20925 /* 64272 */ GIR_EraseRootFromParent_Done,
20926 /* 64273 */ // Label 956: @64273
20927 /* 64273 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(64308), // Rule ID 555 //
20928 /* 64278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
20929 /* 64281 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_packed2national),
20930 /* 64286 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20931 /* 64289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20932 /* 64292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20933 /* 64296 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10797:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (BCDCTN_rec:{ *:[v16i8] }:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB)
20934 /* 64296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDCTN_rec),
20935 /* 64299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
20936 /* 64301 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20937 /* 64303 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0,
20938 /* 64306 */ GIR_RootConstrainSelectedInstOperands,
20939 /* 64307 */ // GIR_Coverage, 555,
20940 /* 64307 */ GIR_EraseRootFromParent_Done,
20941 /* 64308 */ // Label 957: @64308
20942 /* 64308 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(64337), // Rule ID 693 //
20943 /* 64313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_popcntb),
20944 /* 64318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20945 /* 64321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20946 /* 64324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
20947 /* 64328 */ // (intrinsic_wo_chain:{ *:[i64] } 10801:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (POPCNTB8:{ *:[i64] } i64:{ *:[i64] }:$RST)
20948 /* 64328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::POPCNTB8),
20949 /* 64331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
20950 /* 64333 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
20951 /* 64335 */ GIR_RootConstrainSelectedInstOperands,
20952 /* 64336 */ // GIR_Coverage, 693,
20953 /* 64336 */ GIR_EraseRootFromParent_Done,
20954 /* 64337 */ // Label 958: @64337
20955 /* 64337 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(64366), // Rule ID 694 //
20956 /* 64342 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cdtbcdd),
20957 /* 64347 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20958 /* 64350 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20959 /* 64353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
20960 /* 64357 */ // (intrinsic_wo_chain:{ *:[i64] } 10588:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (CDTBCD8:{ *:[i64] } i64:{ *:[i64] }:$RST)
20961 /* 64357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CDTBCD8),
20962 /* 64360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
20963 /* 64362 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
20964 /* 64364 */ GIR_RootConstrainSelectedInstOperands,
20965 /* 64365 */ // GIR_Coverage, 694,
20966 /* 64365 */ GIR_EraseRootFromParent_Done,
20967 /* 64366 */ // Label 959: @64366
20968 /* 64366 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(64395), // Rule ID 695 //
20969 /* 64371 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cbcdtdd),
20970 /* 64376 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
20971 /* 64379 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20972 /* 64382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
20973 /* 64386 */ // (intrinsic_wo_chain:{ *:[i64] } 10586:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (CBCDTD8:{ *:[i64] } i64:{ *:[i64] }:$RST)
20974 /* 64386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CBCDTD8),
20975 /* 64389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
20976 /* 64391 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
20977 /* 64393 */ GIR_RootConstrainSelectedInstOperands,
20978 /* 64394 */ // GIR_Coverage, 695,
20979 /* 64394 */ GIR_EraseRootFromParent_Done,
20980 /* 64395 */ // Label 960: @64395
20981 /* 64395 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(64427), // Rule ID 1062 //
20982 /* 64400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
20983 /* 64403 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstribr),
20984 /* 64408 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20985 /* 64411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20986 /* 64414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
20987 /* 64418 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10542:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VSTRIBR:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB)
20988 /* 64418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIBR),
20989 /* 64421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT]
20990 /* 64423 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
20991 /* 64425 */ GIR_RootConstrainSelectedInstOperands,
20992 /* 64426 */ // GIR_Coverage, 1062,
20993 /* 64426 */ GIR_EraseRootFromParent_Done,
20994 /* 64427 */ // Label 961: @64427
20995 /* 64427 */ GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(64459), // Rule ID 1063 //
20996 /* 64432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
20997 /* 64435 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstribl),
20998 /* 64440 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20999 /* 64443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21000 /* 64446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21001 /* 64450 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10540:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VSTRIBL:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB)
21002 /* 64450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIBL),
21003 /* 64453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT]
21004 /* 64455 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21005 /* 64457 */ GIR_RootConstrainSelectedInstOperands,
21006 /* 64458 */ // GIR_Coverage, 1063,
21007 /* 64458 */ GIR_EraseRootFromParent_Done,
21008 /* 64459 */ // Label 962: @64459
21009 /* 64459 */ GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(64491), // Rule ID 1064 //
21010 /* 64464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21011 /* 64467 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstrihr),
21012 /* 64472 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21013 /* 64475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21014 /* 64478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21015 /* 64482 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10546:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VSTRIHR:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB)
21016 /* 64482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIHR),
21017 /* 64485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT]
21018 /* 64487 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21019 /* 64489 */ GIR_RootConstrainSelectedInstOperands,
21020 /* 64490 */ // GIR_Coverage, 1064,
21021 /* 64490 */ GIR_EraseRootFromParent_Done,
21022 /* 64491 */ // Label 963: @64491
21023 /* 64491 */ GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(64523), // Rule ID 1065 //
21024 /* 64496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21025 /* 64499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstrihl),
21026 /* 64504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21027 /* 64507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21028 /* 64510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21029 /* 64514 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10544:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VSTRIHL:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB)
21030 /* 64514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIHL),
21031 /* 64517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT]
21032 /* 64519 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21033 /* 64521 */ GIR_RootConstrainSelectedInstOperands,
21034 /* 64522 */ // GIR_Coverage, 1065,
21035 /* 64522 */ GIR_EraseRootFromParent_Done,
21036 /* 64523 */ // Label 964: @64523
21037 /* 64523 */ GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(64555), // Rule ID 1082 //
21038 /* 64528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21039 /* 64531 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractbm),
21040 /* 64536 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21041 /* 64539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21042 /* 64542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
21043 /* 64546 */ // (intrinsic_wo_chain:{ *:[i32] } 10409:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTRACTBM:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB)
21044 /* 64546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTBM),
21045 /* 64549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21046 /* 64551 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21047 /* 64553 */ GIR_RootConstrainSelectedInstOperands,
21048 /* 64554 */ // GIR_Coverage, 1082,
21049 /* 64554 */ GIR_EraseRootFromParent_Done,
21050 /* 64555 */ // Label 965: @64555
21051 /* 64555 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(64587), // Rule ID 1083 //
21052 /* 64560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21053 /* 64563 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextracthm),
21054 /* 64568 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21055 /* 64571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21056 /* 64574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
21057 /* 64578 */ // (intrinsic_wo_chain:{ *:[i32] } 10411:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTRACTHM:{ *:[i32] } v8i16:{ *:[v8i16] }:$VB)
21058 /* 64578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTHM),
21059 /* 64581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21060 /* 64583 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21061 /* 64585 */ GIR_RootConstrainSelectedInstOperands,
21062 /* 64586 */ // GIR_Coverage, 1083,
21063 /* 64586 */ GIR_EraseRootFromParent_Done,
21064 /* 64587 */ // Label 966: @64587
21065 /* 64587 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(64619), // Rule ID 1084 //
21066 /* 64592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21067 /* 64595 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractwm),
21068 /* 64600 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21069 /* 64603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21070 /* 64606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
21071 /* 64610 */ // (intrinsic_wo_chain:{ *:[i32] } 10413:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXTRACTWM:{ *:[i32] } v4i32:{ *:[v4i32] }:$VB)
21072 /* 64610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTWM),
21073 /* 64613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21074 /* 64615 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21075 /* 64617 */ GIR_RootConstrainSelectedInstOperands,
21076 /* 64618 */ // GIR_Coverage, 1084,
21077 /* 64618 */ GIR_EraseRootFromParent_Done,
21078 /* 64619 */ // Label 967: @64619
21079 /* 64619 */ GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(64651), // Rule ID 1085 //
21080 /* 64624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21081 /* 64627 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractdm),
21082 /* 64632 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21083 /* 64635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21084 /* 64638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
21085 /* 64642 */ // (intrinsic_wo_chain:{ *:[i32] } 10410:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXTRACTDM:{ *:[i32] } v2i64:{ *:[v2i64] }:$VB)
21086 /* 64642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTDM),
21087 /* 64645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21088 /* 64647 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21089 /* 64649 */ GIR_RootConstrainSelectedInstOperands,
21090 /* 64650 */ // GIR_Coverage, 1085,
21091 /* 64650 */ GIR_EraseRootFromParent_Done,
21092 /* 64651 */ // Label 968: @64651
21093 /* 64651 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(64683), // Rule ID 1086 //
21094 /* 64656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21095 /* 64659 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractqm),
21096 /* 64664 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21097 /* 64667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
21098 /* 64670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
21099 /* 64674 */ // (intrinsic_wo_chain:{ *:[i32] } 10412:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VEXTRACTQM:{ *:[i32] } v1i128:{ *:[v1i128] }:$VB)
21100 /* 64674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTQM),
21101 /* 64677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21102 /* 64679 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21103 /* 64681 */ GIR_RootConstrainSelectedInstOperands,
21104 /* 64682 */ // GIR_Coverage, 1086,
21105 /* 64682 */ GIR_EraseRootFromParent_Done,
21106 /* 64683 */ // Label 969: @64683
21107 /* 64683 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(64715), // Rule ID 1087 //
21108 /* 64688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21109 /* 64691 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandbm),
21110 /* 64696 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
21111 /* 64699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21112 /* 64702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21113 /* 64706 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10395:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXPANDBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB)
21114 /* 64706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDBM),
21115 /* 64709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21116 /* 64711 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21117 /* 64713 */ GIR_RootConstrainSelectedInstOperands,
21118 /* 64714 */ // GIR_Coverage, 1087,
21119 /* 64714 */ GIR_EraseRootFromParent_Done,
21120 /* 64715 */ // Label 970: @64715
21121 /* 64715 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(64747), // Rule ID 1088 //
21122 /* 64720 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21123 /* 64723 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandhm),
21124 /* 64728 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21125 /* 64731 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21126 /* 64734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21127 /* 64738 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10397:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXPANDHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB)
21128 /* 64738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDHM),
21129 /* 64741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21130 /* 64743 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21131 /* 64745 */ GIR_RootConstrainSelectedInstOperands,
21132 /* 64746 */ // GIR_Coverage, 1088,
21133 /* 64746 */ GIR_EraseRootFromParent_Done,
21134 /* 64747 */ // Label 971: @64747
21135 /* 64747 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(64779), // Rule ID 1089 //
21136 /* 64752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21137 /* 64755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandwm),
21138 /* 64760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21139 /* 64763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21140 /* 64766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21141 /* 64770 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10399:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXPANDWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB)
21142 /* 64770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDWM),
21143 /* 64773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21144 /* 64775 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21145 /* 64777 */ GIR_RootConstrainSelectedInstOperands,
21146 /* 64778 */ // GIR_Coverage, 1089,
21147 /* 64778 */ GIR_EraseRootFromParent_Done,
21148 /* 64779 */ // Label 972: @64779
21149 /* 64779 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(64811), // Rule ID 1090 //
21150 /* 64784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21151 /* 64787 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpanddm),
21152 /* 64792 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21153 /* 64795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21154 /* 64798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21155 /* 64802 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10396:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXPANDDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB)
21156 /* 64802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDDM),
21157 /* 64805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21158 /* 64807 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21159 /* 64809 */ GIR_RootConstrainSelectedInstOperands,
21160 /* 64810 */ // GIR_Coverage, 1090,
21161 /* 64810 */ GIR_EraseRootFromParent_Done,
21162 /* 64811 */ // Label 973: @64811
21163 /* 64811 */ GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(64843), // Rule ID 1091 //
21164 /* 64816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21165 /* 64819 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandqm),
21166 /* 64824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
21167 /* 64827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
21168 /* 64830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21169 /* 64834 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10398:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VEXPANDQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VB)
21170 /* 64834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDQM),
21171 /* 64837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21172 /* 64839 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21173 /* 64841 */ GIR_RootConstrainSelectedInstOperands,
21174 /* 64842 */ // GIR_Coverage, 1091,
21175 /* 64842 */ GIR_EraseRootFromParent_Done,
21176 /* 64843 */ // Label 974: @64843
21177 /* 64843 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(64875), // Rule ID 1092 //
21178 /* 64848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21179 /* 64851 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrbm),
21180 /* 64856 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
21181 /* 64859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21182 /* 64862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21183 /* 64866 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10293:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRBM:{ *:[v16i8] } i64:{ *:[i64] }:$VB)
21184 /* 64866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRBM),
21185 /* 64869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21186 /* 64871 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21187 /* 64873 */ GIR_RootConstrainSelectedInstOperands,
21188 /* 64874 */ // GIR_Coverage, 1092,
21189 /* 64874 */ GIR_EraseRootFromParent_Done,
21190 /* 64875 */ // Label 975: @64875
21191 /* 64875 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(64907), // Rule ID 1093 //
21192 /* 64880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21193 /* 64883 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrhm),
21194 /* 64888 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21195 /* 64891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21196 /* 64894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21197 /* 64898 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10295:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRHM:{ *:[v8i16] } i64:{ *:[i64] }:$VB)
21198 /* 64898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRHM),
21199 /* 64901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21200 /* 64903 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21201 /* 64905 */ GIR_RootConstrainSelectedInstOperands,
21202 /* 64906 */ // GIR_Coverage, 1093,
21203 /* 64906 */ GIR_EraseRootFromParent_Done,
21204 /* 64907 */ // Label 976: @64907
21205 /* 64907 */ GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(64939), // Rule ID 1094 //
21206 /* 64912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21207 /* 64915 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrwm),
21208 /* 64920 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21209 /* 64923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21210 /* 64926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21211 /* 64930 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10297:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRWM:{ *:[v4i32] } i64:{ *:[i64] }:$VB)
21212 /* 64930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRWM),
21213 /* 64933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21214 /* 64935 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21215 /* 64937 */ GIR_RootConstrainSelectedInstOperands,
21216 /* 64938 */ // GIR_Coverage, 1094,
21217 /* 64938 */ GIR_EraseRootFromParent_Done,
21218 /* 64939 */ // Label 977: @64939
21219 /* 64939 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(64971), // Rule ID 1095 //
21220 /* 64944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21221 /* 64947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrdm),
21222 /* 64952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21223 /* 64955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21224 /* 64958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21225 /* 64962 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10294:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRDM:{ *:[v2i64] } i64:{ *:[i64] }:$VB)
21226 /* 64962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRDM),
21227 /* 64965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21228 /* 64967 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21229 /* 64969 */ GIR_RootConstrainSelectedInstOperands,
21230 /* 64970 */ // GIR_Coverage, 1095,
21231 /* 64970 */ GIR_EraseRootFromParent_Done,
21232 /* 64971 */ // Label 978: @64971
21233 /* 64971 */ GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(65003), // Rule ID 1096 //
21234 /* 64976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21235 /* 64979 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrqm),
21236 /* 64984 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
21237 /* 64987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21238 /* 64990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21239 /* 64994 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10296:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRQM:{ *:[v1i128] } i64:{ *:[i64] }:$VB)
21240 /* 64994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRQM),
21241 /* 64997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21242 /* 64999 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21243 /* 65001 */ GIR_RootConstrainSelectedInstOperands,
21244 /* 65002 */ // GIR_Coverage, 1096,
21245 /* 65002 */ GIR_EraseRootFromParent_Done,
21246 /* 65003 */ // Label 979: @65003
21247 /* 65003 */ GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(65035), // Rule ID 1160 //
21248 /* 65008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
21249 /* 65011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsd2q),
21250 /* 65016 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
21251 /* 65019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21252 /* 65022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21253 /* 65026 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10416:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXTSD2Q:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VB)
21254 /* 65026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSD2Q),
21255 /* 65029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
21256 /* 65031 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
21257 /* 65033 */ GIR_RootConstrainSelectedInstOperands,
21258 /* 65034 */ // GIR_Coverage, 1160,
21259 /* 65034 */ GIR_EraseRootFromParent_Done,
21260 /* 65035 */ // Label 980: @65035
21261 /* 65035 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(65067), // Rule ID 1165 //
21262 /* 65040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture),
21263 /* 65043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmmr),
21264 /* 65048 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
21265 /* 65051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
21266 /* 65054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
21267 /* 65058 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10687:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$AB) => (DMMR:{ *:[v1024i1] } v1024i1:{ *:[v1024i1] }:$AB)
21268 /* 65058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMMR),
21269 /* 65061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
21270 /* 65063 */ GIR_RootToRootCopy, /*OpIdx*/2, // AB
21271 /* 65065 */ GIR_RootConstrainSelectedInstOperands,
21272 /* 65066 */ // GIR_Coverage, 1165,
21273 /* 65066 */ GIR_EraseRootFromParent_Done,
21274 /* 65067 */ // Label 981: @65067
21275 /* 65067 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(65099), // Rule ID 1170 //
21276 /* 65072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
21277 /* 65075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxmfacc),
21278 /* 65080 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
21279 /* 65083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
21280 /* 65086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
21281 /* 65090 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10781:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$AT) => (XXMFACC:{ *:[v512i1] } v512i1:{ *:[v512i1] }:$AT)
21282 /* 65090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXMFACC),
21283 /* 65093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[ATo]
21284 /* 65095 */ GIR_RootToRootCopy, /*OpIdx*/2, // AT
21285 /* 65097 */ GIR_RootConstrainSelectedInstOperands,
21286 /* 65098 */ // GIR_Coverage, 1170,
21287 /* 65098 */ GIR_EraseRootFromParent_Done,
21288 /* 65099 */ // Label 982: @65099
21289 /* 65099 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(65131), // Rule ID 1171 //
21290 /* 65104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
21291 /* 65107 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxmtacc),
21292 /* 65112 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
21293 /* 65115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
21294 /* 65118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
21295 /* 65122 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10782:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi) => (XXMTACC:{ *:[v512i1] } v512i1:{ *:[v512i1] }:$ATi)
21296 /* 65122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXMTACC),
21297 /* 65125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
21298 /* 65127 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
21299 /* 65129 */ GIR_RootConstrainSelectedInstOperands,
21300 /* 65130 */ // GIR_Coverage, 1171,
21301 /* 65130 */ GIR_EraseRootFromParent_Done,
21302 /* 65131 */ // Label 983: @65131
21303 /* 65131 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(65160), // Rule ID 1286 //
21304 /* 65136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fre),
21305 /* 65141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21306 /* 65144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21307 /* 65147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
21308 /* 65151 */ // (intrinsic_wo_chain:{ *:[f64] } 10648:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FRE:{ *:[f64] } ?:{ *:[f64] }:$A)
21309 /* 65151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRE),
21310 /* 65154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21311 /* 65156 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21312 /* 65158 */ GIR_RootConstrainSelectedInstOperands,
21313 /* 65159 */ // GIR_Coverage, 1286,
21314 /* 65159 */ GIR_EraseRootFromParent_Done,
21315 /* 65160 */ // Label 984: @65160
21316 /* 65160 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(65189), // Rule ID 1287 //
21317 /* 65165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fres),
21318 /* 65170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21319 /* 65173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21320 /* 65176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
21321 /* 65180 */ // (intrinsic_wo_chain:{ *:[f32] } 10649:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (FRES:{ *:[f32] } ?:{ *:[f32] }:$A)
21322 /* 65180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRES),
21323 /* 65183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21324 /* 65185 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21325 /* 65187 */ GIR_RootConstrainSelectedInstOperands,
21326 /* 65188 */ // GIR_Coverage, 1287,
21327 /* 65188 */ GIR_EraseRootFromParent_Done,
21328 /* 65189 */ // Label 985: @65189
21329 /* 65189 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(65218), // Rule ID 1288 //
21330 /* 65194 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabs),
21331 /* 65199 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21332 /* 65202 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21333 /* 65205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
21334 /* 65209 */ // (intrinsic_wo_chain:{ *:[f64] } 10643:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FNABSD:{ *:[f64] } ?:{ *:[f64] }:$A)
21335 /* 65209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSD),
21336 /* 65212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21337 /* 65214 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21338 /* 65216 */ GIR_RootConstrainSelectedInstOperands,
21339 /* 65217 */ // GIR_Coverage, 1288,
21340 /* 65217 */ GIR_EraseRootFromParent_Done,
21341 /* 65218 */ // Label 986: @65218
21342 /* 65218 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(65247), // Rule ID 1289 //
21343 /* 65223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabss),
21344 /* 65228 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21345 /* 65231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21346 /* 65234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
21347 /* 65238 */ // (intrinsic_wo_chain:{ *:[f32] } 10644:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (FNABSS:{ *:[f32] } ?:{ *:[f32] }:$A)
21348 /* 65238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSS),
21349 /* 65241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21350 /* 65243 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21351 /* 65245 */ GIR_RootConstrainSelectedInstOperands,
21352 /* 65246 */ // GIR_Coverage, 1289,
21353 /* 65246 */ GIR_EraseRootFromParent_Done,
21354 /* 65247 */ // Label 987: @65247
21355 /* 65247 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(65322), // Rule ID 3364 //
21356 /* 65252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1),
21357 /* 65255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspbf16),
21358 /* 65260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
21359 /* 65263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21360 /* 65266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21361 /* 65270 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10883:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XVCVSPBF16:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] })
21362 /* 65270 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
21363 /* 65273 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21364 /* 65277 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21365 /* 65282 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XA
21366 /* 65286 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
21367 /* 65291 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21368 /* 65294 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVCVSPBF16),
21369 /* 65298 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21370 /* 65303 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21371 /* 65306 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21372 /* 65308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21373 /* 65311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21374 /* 65313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21375 /* 65316 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
21376 /* 65321 */ // GIR_Coverage, 3364,
21377 /* 65321 */ GIR_EraseRootFromParent_Done,
21378 /* 65322 */ // Label 988: @65322
21379 /* 65322 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(65397), // Rule ID 3365 //
21380 /* 65327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1),
21381 /* 65330 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvbf16spn),
21382 /* 65335 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
21383 /* 65338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21384 /* 65341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21385 /* 65345 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10878:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XVCVBF16SPN:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] })
21386 /* 65345 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
21387 /* 65348 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21388 /* 65352 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21389 /* 65357 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XA
21390 /* 65361 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
21391 /* 65366 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21392 /* 65369 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVCVBF16SPN),
21393 /* 65373 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21394 /* 65378 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21395 /* 65381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21396 /* 65383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21397 /* 65386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21398 /* 65388 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21399 /* 65391 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
21400 /* 65396 */ // GIR_Coverage, 3365,
21401 /* 65396 */ GIR_EraseRootFromParent_Done,
21402 /* 65397 */ // Label 989: @65397
21403 /* 65397 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(65426), // Rule ID 4898 //
21404 /* 65402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fcfid),
21405 /* 65407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21406 /* 65410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21407 /* 65413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21408 /* 65417 */ // (intrinsic_wo_chain:{ *:[f64] } 10630:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVSXDDP:{ *:[f64] } ?:{ *:[f64] }:$A)
21409 /* 65417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVSXDDP),
21410 /* 65420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21411 /* 65422 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21412 /* 65424 */ GIR_RootConstrainSelectedInstOperands,
21413 /* 65425 */ // GIR_Coverage, 4898,
21414 /* 65425 */ GIR_EraseRootFromParent_Done,
21415 /* 65426 */ // Label 990: @65426
21416 /* 65426 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(65455), // Rule ID 4899 //
21417 /* 65431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fcfud),
21418 /* 65436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21419 /* 65439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21420 /* 65442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21421 /* 65446 */ // (intrinsic_wo_chain:{ *:[f64] } 10631:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVUXDDP:{ *:[f64] } ?:{ *:[f64] }:$A)
21422 /* 65446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVUXDDP),
21423 /* 65449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21424 /* 65451 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21425 /* 65453 */ GIR_RootConstrainSelectedInstOperands,
21426 /* 65454 */ // GIR_Coverage, 4899,
21427 /* 65454 */ GIR_EraseRootFromParent_Done,
21428 /* 65455 */ // Label 991: @65455
21429 /* 65455 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(65484), // Rule ID 4900 //
21430 /* 65460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctid),
21431 /* 65465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21432 /* 65468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21433 /* 65471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
21434 /* 65475 */ // (intrinsic_wo_chain:{ *:[f64] } 10632:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FCTID:{ *:[f64] } ?:{ *:[f64] }:$A)
21435 /* 65475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCTID),
21436 /* 65478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21437 /* 65480 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21438 /* 65482 */ GIR_RootConstrainSelectedInstOperands,
21439 /* 65483 */ // GIR_Coverage, 4900,
21440 /* 65483 */ GIR_EraseRootFromParent_Done,
21441 /* 65484 */ // Label 992: @65484
21442 /* 65484 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(65513), // Rule ID 4901 //
21443 /* 65489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctidz),
21444 /* 65494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21445 /* 65497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21446 /* 65500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21447 /* 65504 */ // (intrinsic_wo_chain:{ *:[f64] } 10633:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPSXDS:{ *:[f64] } ?:{ *:[f64] }:$A)
21448 /* 65504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSXDS),
21449 /* 65507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21450 /* 65509 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21451 /* 65511 */ GIR_RootConstrainSelectedInstOperands,
21452 /* 65512 */ // GIR_Coverage, 4901,
21453 /* 65512 */ GIR_EraseRootFromParent_Done,
21454 /* 65513 */ // Label 993: @65513
21455 /* 65513 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(65542), // Rule ID 4902 //
21456 /* 65518 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctiw),
21457 /* 65523 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21458 /* 65526 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21459 /* 65529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
21460 /* 65533 */ // (intrinsic_wo_chain:{ *:[f64] } 10634:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FCTIW:{ *:[f64] } ?:{ *:[f64] }:$A)
21461 /* 65533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCTIW),
21462 /* 65536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21463 /* 65538 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21464 /* 65540 */ GIR_RootConstrainSelectedInstOperands,
21465 /* 65541 */ // GIR_Coverage, 4902,
21466 /* 65541 */ GIR_EraseRootFromParent_Done,
21467 /* 65542 */ // Label 994: @65542
21468 /* 65542 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(65571), // Rule ID 4903 //
21469 /* 65547 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctiwz),
21470 /* 65552 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21471 /* 65555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21472 /* 65558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21473 /* 65562 */ // (intrinsic_wo_chain:{ *:[f64] } 10635:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPSXWS:{ *:[f64] } ?:{ *:[f64] }:$A)
21474 /* 65562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSXWS),
21475 /* 65565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21476 /* 65567 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21477 /* 65569 */ GIR_RootConstrainSelectedInstOperands,
21478 /* 65570 */ // GIR_Coverage, 4903,
21479 /* 65570 */ GIR_EraseRootFromParent_Done,
21480 /* 65571 */ // Label 995: @65571
21481 /* 65571 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(65600), // Rule ID 4904 //
21482 /* 65576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctudz),
21483 /* 65581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21484 /* 65584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21485 /* 65587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21486 /* 65591 */ // (intrinsic_wo_chain:{ *:[f64] } 10636:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPUXDS:{ *:[f64] } ?:{ *:[f64] }:$A)
21487 /* 65591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPUXDS),
21488 /* 65594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21489 /* 65596 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21490 /* 65598 */ GIR_RootConstrainSelectedInstOperands,
21491 /* 65599 */ // GIR_Coverage, 4904,
21492 /* 65599 */ GIR_EraseRootFromParent_Done,
21493 /* 65600 */ // Label 996: @65600
21494 /* 65600 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(65629), // Rule ID 4905 //
21495 /* 65605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctuwz),
21496 /* 65610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21497 /* 65613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21498 /* 65616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21499 /* 65620 */ // (intrinsic_wo_chain:{ *:[f64] } 10637:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPUXWS:{ *:[f64] } ?:{ *:[f64] }:$A)
21500 /* 65620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPUXWS),
21501 /* 65623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21502 /* 65625 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21503 /* 65627 */ GIR_RootConstrainSelectedInstOperands,
21504 /* 65628 */ // GIR_Coverage, 4905,
21505 /* 65628 */ GIR_EraseRootFromParent_Done,
21506 /* 65629 */ // Label 997: @65629
21507 /* 65629 */ GIM_Reject,
21508 /* 65630 */ // Label 889: @65630
21509 /* 65630 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(74423),
21510 /* 65635 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
21511 /* 65638 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(65709), // Rule ID 2174 //
21512 /* 65643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21513 /* 65646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxextractuw),
21514 /* 65651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21515 /* 65654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21516 /* 65657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21517 /* 65660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21518 /* 65664 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
21519 /* 65668 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
21520 /* 65672 */ // MIs[1] Operand 1
21521 /* 65672 */ // No operand predicates
21522 /* 65672 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21523 /* 65674 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10922:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$A, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXEXTRACTUW:{ *:[f64] } ?:{ *:[v2i64] }:$A, (imm:{ *:[i32] }):$IMM), VSRC:{ *:[i32] })
21524 /* 65674 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21525 /* 65677 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXEXTRACTUW),
21526 /* 65681 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21527 /* 65686 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A
21528 /* 65690 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM
21529 /* 65693 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21530 /* 65695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21531 /* 65698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21532 /* 65700 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21533 /* 65703 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
21534 /* 65708 */ // GIR_Coverage, 2174,
21535 /* 65708 */ GIR_EraseRootFromParent_Done,
21536 /* 65709 */ // Label 999: @65709
21537 /* 65709 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(65746), // Rule ID 1033 //
21538 /* 65714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21539 /* 65717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtstdcsp),
21540 /* 65722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21541 /* 65725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21542 /* 65728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21543 /* 65732 */ // MIs[0] DCMX
21544 /* 65732 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
21545 /* 65735 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10912:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB, (timm:{ *:[i32] }):$DCMX) => (XVTSTDCSP:{ *:[v4i32] } (timm:{ *:[i32] }):$DCMX, v4f32:{ *:[v4f32] }:$XB)
21546 /* 65735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVTSTDCSP),
21547 /* 65738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21548 /* 65740 */ GIR_RootToRootCopy, /*OpIdx*/3, // DCMX
21549 /* 65742 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
21550 /* 65744 */ GIR_RootConstrainSelectedInstOperands,
21551 /* 65745 */ // GIR_Coverage, 1033,
21552 /* 65745 */ GIR_EraseRootFromParent_Done,
21553 /* 65746 */ // Label 1000: @65746
21554 /* 65746 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(65783), // Rule ID 1034 //
21555 /* 65751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21556 /* 65754 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtstdcdp),
21557 /* 65759 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21558 /* 65762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21559 /* 65765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21560 /* 65769 */ // MIs[0] DCMX
21561 /* 65769 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
21562 /* 65772 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10911:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB, (timm:{ *:[i32] }):$DCMX) => (XVTSTDCDP:{ *:[v2i64] } (timm:{ *:[i32] }):$DCMX, v2f64:{ *:[v2f64] }:$XB)
21563 /* 65772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVTSTDCDP),
21564 /* 65775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21565 /* 65777 */ GIR_RootToRootCopy, /*OpIdx*/3, // DCMX
21566 /* 65779 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
21567 /* 65781 */ GIR_RootConstrainSelectedInstOperands,
21568 /* 65782 */ // GIR_Coverage, 1034,
21569 /* 65782 */ GIR_EraseRootFromParent_Done,
21570 /* 65783 */ // Label 1001: @65783
21571 /* 65783 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(65828), // Rule ID 902 //
21572 /* 65788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21573 /* 65791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xsmaxdp),
21574 /* 65796 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21575 /* 65799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21576 /* 65802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21577 /* 65805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21578 /* 65809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21579 /* 65813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21580 /* 65817 */ // (intrinsic_wo_chain:{ *:[f64] } 10864:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) => (XSMAXDP:{ *:[f64] } vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB)
21581 /* 65817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
21582 /* 65820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21583 /* 65822 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21584 /* 65824 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21585 /* 65826 */ GIR_RootConstrainSelectedInstOperands,
21586 /* 65827 */ // GIR_Coverage, 902,
21587 /* 65827 */ GIR_EraseRootFromParent_Done,
21588 /* 65828 */ // Label 1002: @65828
21589 /* 65828 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(65873), // Rule ID 903 //
21590 /* 65833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21591 /* 65836 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xsmindp),
21592 /* 65841 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21593 /* 65844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21594 /* 65847 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21595 /* 65850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21596 /* 65854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21597 /* 65858 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
21598 /* 65862 */ // (intrinsic_wo_chain:{ *:[f64] } 10865:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) => (XSMINDP:{ *:[f64] } vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB)
21599 /* 65862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
21600 /* 65865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21601 /* 65867 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21602 /* 65869 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21603 /* 65871 */ GIR_RootConstrainSelectedInstOperands,
21604 /* 65872 */ // GIR_Coverage, 903,
21605 /* 65872 */ GIR_EraseRootFromParent_Done,
21606 /* 65873 */ // Label 1003: @65873
21607 /* 65873 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(65918), // Rule ID 904 //
21608 /* 65878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21609 /* 65881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmaxdp),
21610 /* 65886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21611 /* 65889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21612 /* 65892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21613 /* 65895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21614 /* 65899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21615 /* 65903 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21616 /* 65907 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10896:{ *:[iPTR] }, vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) => (XVMAXDP:{ *:[v2f64] } vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB)
21617 /* 65907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMAXDP),
21618 /* 65910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21619 /* 65912 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21620 /* 65914 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21621 /* 65916 */ GIR_RootConstrainSelectedInstOperands,
21622 /* 65917 */ // GIR_Coverage, 904,
21623 /* 65917 */ GIR_EraseRootFromParent_Done,
21624 /* 65918 */ // Label 1004: @65918
21625 /* 65918 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(65963), // Rule ID 905 //
21626 /* 65923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21627 /* 65926 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmindp),
21628 /* 65931 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21629 /* 65934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21630 /* 65937 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21631 /* 65940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21632 /* 65944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21633 /* 65948 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21634 /* 65952 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10898:{ *:[iPTR] }, vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) => (XVMINDP:{ *:[v2f64] } vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB)
21635 /* 65952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMINDP),
21636 /* 65955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21637 /* 65957 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21638 /* 65959 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21639 /* 65961 */ GIR_RootConstrainSelectedInstOperands,
21640 /* 65962 */ // GIR_Coverage, 905,
21641 /* 65962 */ GIR_EraseRootFromParent_Done,
21642 /* 65963 */ // Label 1005: @65963
21643 /* 65963 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(66008), // Rule ID 906 //
21644 /* 65968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21645 /* 65971 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmaxsp),
21646 /* 65976 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21647 /* 65979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21648 /* 65982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21649 /* 65985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21650 /* 65989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21651 /* 65993 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21652 /* 65997 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10897:{ *:[iPTR] }, vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) => (XVMAXSP:{ *:[v4f32] } vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB)
21653 /* 65997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMAXSP),
21654 /* 66000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21655 /* 66002 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21656 /* 66004 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21657 /* 66006 */ GIR_RootConstrainSelectedInstOperands,
21658 /* 66007 */ // GIR_Coverage, 906,
21659 /* 66007 */ GIR_EraseRootFromParent_Done,
21660 /* 66008 */ // Label 1006: @66008
21661 /* 66008 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(66053), // Rule ID 907 //
21662 /* 66013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21663 /* 66016 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvminsp),
21664 /* 66021 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21665 /* 66024 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21666 /* 66027 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21667 /* 66030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21668 /* 66034 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21669 /* 66038 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21670 /* 66042 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10899:{ *:[iPTR] }, vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) => (XVMINSP:{ *:[v4f32] } vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB)
21671 /* 66042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMINSP),
21672 /* 66045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21673 /* 66047 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21674 /* 66049 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21675 /* 66051 */ GIR_RootConstrainSelectedInstOperands,
21676 /* 66052 */ // GIR_Coverage, 907,
21677 /* 66052 */ GIR_EraseRootFromParent_Done,
21678 /* 66053 */ // Label 1007: @66053
21679 /* 66053 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(66090), // Rule ID 831 //
21680 /* 66058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21681 /* 66061 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpeqdp),
21682 /* 66066 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21683 /* 66069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21684 /* 66072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21685 /* 66075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21686 /* 66079 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10866:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPEQDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
21687 /* 66079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPEQDP),
21688 /* 66082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21689 /* 66084 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21690 /* 66086 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21691 /* 66088 */ GIR_RootConstrainSelectedInstOperands,
21692 /* 66089 */ // GIR_Coverage, 831,
21693 /* 66089 */ GIR_EraseRootFromParent_Done,
21694 /* 66090 */ // Label 1008: @66090
21695 /* 66090 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(66127), // Rule ID 833 //
21696 /* 66095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21697 /* 66098 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpeqsp),
21698 /* 66103 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21699 /* 66106 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21700 /* 66109 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21701 /* 66112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21702 /* 66116 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10868:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPEQSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
21703 /* 66116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPEQSP),
21704 /* 66119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21705 /* 66121 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21706 /* 66123 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21707 /* 66125 */ GIR_RootConstrainSelectedInstOperands,
21708 /* 66126 */ // GIR_Coverage, 833,
21709 /* 66126 */ GIR_EraseRootFromParent_Done,
21710 /* 66127 */ // Label 1009: @66127
21711 /* 66127 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(66164), // Rule ID 835 //
21712 /* 66132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21713 /* 66135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgedp),
21714 /* 66140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21715 /* 66143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21716 /* 66146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21717 /* 66149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21718 /* 66153 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10870:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPGEDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
21719 /* 66153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGEDP),
21720 /* 66156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21721 /* 66158 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21722 /* 66160 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21723 /* 66162 */ GIR_RootConstrainSelectedInstOperands,
21724 /* 66163 */ // GIR_Coverage, 835,
21725 /* 66163 */ GIR_EraseRootFromParent_Done,
21726 /* 66164 */ // Label 1010: @66164
21727 /* 66164 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(66201), // Rule ID 837 //
21728 /* 66169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21729 /* 66172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgesp),
21730 /* 66177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21731 /* 66180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21732 /* 66183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21733 /* 66186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21734 /* 66190 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10872:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPGESP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
21735 /* 66190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGESP),
21736 /* 66193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21737 /* 66195 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21738 /* 66197 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21739 /* 66199 */ GIR_RootConstrainSelectedInstOperands,
21740 /* 66200 */ // GIR_Coverage, 837,
21741 /* 66200 */ GIR_EraseRootFromParent_Done,
21742 /* 66201 */ // Label 1011: @66201
21743 /* 66201 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(66238), // Rule ID 839 //
21744 /* 66206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21745 /* 66209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgtdp),
21746 /* 66214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21747 /* 66217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21748 /* 66220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21749 /* 66223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21750 /* 66227 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10874:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPGTDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
21751 /* 66227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGTDP),
21752 /* 66230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21753 /* 66232 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21754 /* 66234 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21755 /* 66236 */ GIR_RootConstrainSelectedInstOperands,
21756 /* 66237 */ // GIR_Coverage, 839,
21757 /* 66237 */ GIR_EraseRootFromParent_Done,
21758 /* 66238 */ // Label 1012: @66238
21759 /* 66238 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(66275), // Rule ID 841 //
21760 /* 66243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21761 /* 66246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgtsp),
21762 /* 66251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21763 /* 66254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21764 /* 66257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21765 /* 66260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21766 /* 66264 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10876:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPGTSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
21767 /* 66264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGTSP),
21768 /* 66267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21769 /* 66269 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21770 /* 66271 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21771 /* 66273 */ GIR_RootConstrainSelectedInstOperands,
21772 /* 66274 */ // GIR_Coverage, 841,
21773 /* 66274 */ GIR_EraseRootFromParent_Done,
21774 /* 66275 */ // Label 1013: @66275
21775 /* 66275 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(66312), // Rule ID 1005 //
21776 /* 66280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21777 /* 66283 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addf128_round_to_odd),
21778 /* 66288 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
21779 /* 66291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
21780 /* 66294 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
21781 /* 66297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21782 /* 66301 */ // (intrinsic_wo_chain:{ *:[f128] } 10262:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSADDQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
21783 /* 66301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSADDQPO),
21784 /* 66304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21785 /* 66306 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
21786 /* 66308 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
21787 /* 66310 */ GIR_RootConstrainSelectedInstOperands,
21788 /* 66311 */ // GIR_Coverage, 1005,
21789 /* 66311 */ GIR_EraseRootFromParent_Done,
21790 /* 66312 */ // Label 1014: @66312
21791 /* 66312 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(66349), // Rule ID 1006 //
21792 /* 66317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21793 /* 66320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulf128_round_to_odd),
21794 /* 66325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
21795 /* 66328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
21796 /* 66331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
21797 /* 66334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21798 /* 66338 */ // (intrinsic_wo_chain:{ *:[f128] } 10790:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSMULQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
21799 /* 66338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMULQPO),
21800 /* 66341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21801 /* 66343 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
21802 /* 66345 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
21803 /* 66347 */ GIR_RootConstrainSelectedInstOperands,
21804 /* 66348 */ // GIR_Coverage, 1006,
21805 /* 66348 */ GIR_EraseRootFromParent_Done,
21806 /* 66349 */ // Label 1015: @66349
21807 /* 66349 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(66386), // Rule ID 1007 //
21808 /* 66354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21809 /* 66357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_subf128_round_to_odd),
21810 /* 66362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
21811 /* 66365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
21812 /* 66368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
21813 /* 66371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21814 /* 66375 */ // (intrinsic_wo_chain:{ *:[f128] } 10824:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
21815 /* 66375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSSUBQPO),
21816 /* 66378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21817 /* 66380 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
21818 /* 66382 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
21819 /* 66384 */ GIR_RootConstrainSelectedInstOperands,
21820 /* 66385 */ // GIR_Coverage, 1007,
21821 /* 66385 */ GIR_EraseRootFromParent_Done,
21822 /* 66386 */ // Label 1016: @66386
21823 /* 66386 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(66423), // Rule ID 1008 //
21824 /* 66391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21825 /* 66394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divf128_round_to_odd),
21826 /* 66399 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
21827 /* 66402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
21828 /* 66405 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
21829 /* 66408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21830 /* 66412 */ // (intrinsic_wo_chain:{ *:[f128] } 10624:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSDIVQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
21831 /* 66412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSDIVQPO),
21832 /* 66415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
21833 /* 66417 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
21834 /* 66419 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
21835 /* 66421 */ GIR_RootConstrainSelectedInstOperands,
21836 /* 66422 */ // GIR_Coverage, 1008,
21837 /* 66422 */ GIR_EraseRootFromParent_Done,
21838 /* 66423 */ // Label 1017: @66423
21839 /* 66423 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(66460), // Rule ID 1027 //
21840 /* 66428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21841 /* 66431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xviexpdp),
21842 /* 66436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21843 /* 66439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21844 /* 66442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21845 /* 66445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21846 /* 66449 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10894:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB) => (XVIEXPDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB)
21847 /* 66449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVIEXPDP),
21848 /* 66452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21849 /* 66454 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21850 /* 66456 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21851 /* 66458 */ GIR_RootConstrainSelectedInstOperands,
21852 /* 66459 */ // GIR_Coverage, 1027,
21853 /* 66459 */ GIR_EraseRootFromParent_Done,
21854 /* 66460 */ // Label 1018: @66460
21855 /* 66460 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(66497), // Rule ID 1028 //
21856 /* 66465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21857 /* 66468 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xviexpsp),
21858 /* 66473 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21859 /* 66476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21860 /* 66479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21861 /* 66482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21862 /* 66486 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10895:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XVIEXPSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB)
21863 /* 66486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVIEXPSP),
21864 /* 66489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21865 /* 66491 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
21866 /* 66493 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
21867 /* 66495 */ GIR_RootConstrainSelectedInstOperands,
21868 /* 66496 */ // GIR_Coverage, 1028,
21869 /* 66496 */ GIR_EraseRootFromParent_Done,
21870 /* 66497 */ // Label 1019: @66497
21871 /* 66497 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(66534), // Rule ID 1659 //
21872 /* 66502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21873 /* 66505 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvdivsp),
21874 /* 66510 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21875 /* 66513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21876 /* 66516 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21877 /* 66519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21878 /* 66523 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10893:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B) => (XVDIVSP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B)
21879 /* 66523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVDIVSP),
21880 /* 66526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21881 /* 66528 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21882 /* 66530 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
21883 /* 66532 */ GIR_RootConstrainSelectedInstOperands,
21884 /* 66533 */ // GIR_Coverage, 1659,
21885 /* 66533 */ GIR_EraseRootFromParent_Done,
21886 /* 66534 */ // Label 1020: @66534
21887 /* 66534 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(66571), // Rule ID 1660 //
21888 /* 66539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21889 /* 66542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvdivdp),
21890 /* 66547 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21891 /* 66550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21892 /* 66553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21893 /* 66556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21894 /* 66560 */ // (intrinsic_wo_chain:{ *:[v2f64] } 10892:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A, v2f64:{ *:[v2f64] }:$B) => (XVDIVDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A, ?:{ *:[v2f64] }:$B)
21895 /* 66560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVDIVDP),
21896 /* 66563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21897 /* 66565 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21898 /* 66567 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
21899 /* 66569 */ GIR_RootConstrainSelectedInstOperands,
21900 /* 66570 */ // GIR_Coverage, 1660,
21901 /* 66570 */ GIR_EraseRootFromParent_Done,
21902 /* 66571 */ // Label 1021: @66571
21903 /* 66571 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(66633), // Rule ID 1661 //
21904 /* 66576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21905 /* 66579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtdivdp),
21906 /* 66584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21907 /* 66587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21908 /* 66590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21909 /* 66593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
21910 /* 66597 */ // (intrinsic_wo_chain:{ *:[i32] } 10906:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A, v2f64:{ *:[v2f64] }:$B) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTDIVDP:{ *:[i32] } ?:{ *:[v2f64] }:$A, ?:{ *:[v2f64] }:$B), GPRC:{ *:[i32] })
21911 /* 66597 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21912 /* 66600 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTDIVDP),
21913 /* 66604 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21914 /* 66609 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A
21915 /* 66613 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B
21916 /* 66617 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21917 /* 66619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21918 /* 66622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21919 /* 66624 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21920 /* 66627 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
21921 /* 66632 */ // GIR_Coverage, 1661,
21922 /* 66632 */ GIR_EraseRootFromParent_Done,
21923 /* 66633 */ // Label 1022: @66633
21924 /* 66633 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(66695), // Rule ID 1662 //
21925 /* 66638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
21926 /* 66641 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtdivsp),
21927 /* 66646 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
21928 /* 66649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21929 /* 66652 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21930 /* 66655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
21931 /* 66659 */ // (intrinsic_wo_chain:{ *:[i32] } 10907:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTDIVSP:{ *:[i32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B), GPRC:{ *:[i32] })
21932 /* 66659 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21933 /* 66662 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTDIVSP),
21934 /* 66666 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21935 /* 66671 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A
21936 /* 66675 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B
21937 /* 66679 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21938 /* 66681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21939 /* 66684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21940 /* 66686 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21941 /* 66689 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
21942 /* 66694 */ // GIR_Coverage, 1662,
21943 /* 66694 */ GIR_EraseRootFromParent_Done,
21944 /* 66695 */ // Label 1023: @66695
21945 /* 66695 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(66732), // Rule ID 1906 //
21946 /* 66700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
21947 /* 66703 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxleqv),
21948 /* 66708 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21949 /* 66711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21950 /* 66714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21951 /* 66717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
21952 /* 66721 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10928:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v4i32:{ *:[v4i32] }:$B) => (XXLEQV:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B)
21953 /* 66721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV),
21954 /* 66724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
21955 /* 66726 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
21956 /* 66728 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
21957 /* 66730 */ GIR_RootConstrainSelectedInstOperands,
21958 /* 66731 */ // GIR_Coverage, 1906,
21959 /* 66731 */ GIR_EraseRootFromParent_Done,
21960 /* 66732 */ // Label 1024: @66732
21961 /* 66732 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(66814), // Rule ID 1944 //
21962 /* 66737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
21963 /* 66740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_insert_exp),
21964 /* 66745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21965 /* 66748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21966 /* 66751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21967 /* 66754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
21968 /* 66758 */ // (intrinsic_wo_chain:{ *:[f64] } 10659:{ *:[iPTR] }, f64:{ *:[f64] }:$A, i64:{ *:[i64] }:$B) => (COPY_TO_REGCLASS:{ *:[f64] } (XSIEXPDP:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[i64] } ?:{ *:[f64] }:$A, G8RC:{ *:[i32] }), ?:{ *:[i64] }:$B), F8RC:{ *:[i32] })
21969 /* 66758 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
21970 /* 66761 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21971 /* 66765 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21972 /* 66770 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A
21973 /* 66774 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
21974 /* 66779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
21975 /* 66782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSIEXPDP),
21976 /* 66786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21977 /* 66791 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21978 /* 66794 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B
21979 /* 66798 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21980 /* 66800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21981 /* 66803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21982 /* 66805 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21983 /* 66808 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::F8RCRegClassID),
21984 /* 66813 */ // GIR_Coverage, 1944,
21985 /* 66813 */ GIR_EraseRootFromParent_Done,
21986 /* 66814 */ // Label 1025: @66814
21987 /* 66814 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(66870), // Rule ID 2171 //
21988 /* 66819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
21989 /* 66822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_scalar_insert_exp_qp),
21990 /* 66827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
21991 /* 66830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
21992 /* 66833 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21993 /* 66836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
21994 /* 66840 */ // (intrinsic_wo_chain:{ *:[f128] } 10807:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, i64:{ *:[i64] }:$vB) => (XSIEXPQP:{ *:[f128] } ?:{ *:[f128] }:$vA, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$vB))
21995 /* 66840 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21996 /* 66843 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::MTVSRD),
21997 /* 66847 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21998 /* 66852 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vB
21999 /* 66856 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22000 /* 66858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSIEXPQP),
22001 /* 66861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
22002 /* 66863 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
22003 /* 66865 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22004 /* 66868 */ GIR_RootConstrainSelectedInstOperands,
22005 /* 66869 */ // GIR_Coverage, 2171,
22006 /* 66869 */ GIR_EraseRootFromParent_Done,
22007 /* 66870 */ // Label 1026: @66870
22008 /* 66870 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(66961), // Rule ID 3354 //
22009 /* 66875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22010 /* 66878 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtlsbb),
22011 /* 66883 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22012 /* 66886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22013 /* 66889 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22014 /* 66892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
22015 /* 66896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
22016 /* 66900 */ // (intrinsic_wo_chain:{ *:[i32] } 10908:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XB, 1:{ *:[i32] }) => (EXTRACT_SUBREG:{ *:[i32] } (XVTLSBB:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })), sub_lt:{ *:[i32] })
22017 /* 66900 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
22018 /* 66903 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22019 /* 66907 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22020 /* 66912 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XB
22021 /* 66916 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
22022 /* 66921 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22023 /* 66924 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTLSBB),
22024 /* 66928 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22025 /* 66933 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
22026 /* 66936 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22027 /* 66938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22028 /* 66941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
22029 /* 66943 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
22030 /* 66950 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
22031 /* 66955 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
22032 /* 66960 */ // GIR_Coverage, 3354,
22033 /* 66960 */ GIR_EraseRootFromParent_Done,
22034 /* 66961 */ // Label 1027: @66961
22035 /* 66961 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(67052), // Rule ID 3355 //
22036 /* 66966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22037 /* 66969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtlsbb),
22038 /* 66974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22039 /* 66977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22040 /* 66980 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22041 /* 66983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
22042 /* 66987 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
22043 /* 66991 */ // (intrinsic_wo_chain:{ *:[i32] } 10908:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XB, 0:{ *:[i32] }) => (EXTRACT_SUBREG:{ *:[i32] } (XVTLSBB:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })), sub_eq:{ *:[i32] })
22044 /* 66991 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
22045 /* 66994 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22046 /* 66998 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22047 /* 67003 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XB
22048 /* 67007 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
22049 /* 67012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22050 /* 67015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTLSBB),
22051 /* 67019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22052 /* 67024 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
22053 /* 67027 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22054 /* 67029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22055 /* 67032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
22056 /* 67034 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
22057 /* 67041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
22058 /* 67046 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
22059 /* 67051 */ // GIR_Coverage, 3355,
22060 /* 67051 */ GIR_EraseRootFromParent_Done,
22061 /* 67052 */ // Label 1028: @67052
22062 /* 67052 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(67095), // Rule ID 317 //
22063 /* 67057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22064 /* 67060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfsx),
22065 /* 67065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22066 /* 67068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22067 /* 67071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22068 /* 67075 */ // MIs[0] Operand 3
22069 /* 67075 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
22070 /* 67086 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10324:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, 0:{ *:[i32] }) => (VCFSX_0:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$VB)
22071 /* 67086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFSX_0),
22072 /* 67089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22073 /* 67091 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22074 /* 67093 */ GIR_RootConstrainSelectedInstOperands,
22075 /* 67094 */ // GIR_Coverage, 317,
22076 /* 67094 */ GIR_EraseRootFromParent_Done,
22077 /* 67095 */ // Label 1029: @67095
22078 /* 67095 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(67138), // Rule ID 318 //
22079 /* 67100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22080 /* 67103 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctuxs),
22081 /* 67108 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22082 /* 67111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22083 /* 67114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22084 /* 67118 */ // MIs[0] Operand 3
22085 /* 67118 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
22086 /* 67129 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10386:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, 0:{ *:[i32] }) => (VCTUXS_0:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$VB)
22087 /* 67129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTUXS_0),
22088 /* 67132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22089 /* 67134 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22090 /* 67136 */ GIR_RootConstrainSelectedInstOperands,
22091 /* 67137 */ // GIR_Coverage, 318,
22092 /* 67137 */ GIR_EraseRootFromParent_Done,
22093 /* 67138 */ // Label 1030: @67138
22094 /* 67138 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(67181), // Rule ID 319 //
22095 /* 67143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22096 /* 67146 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfux),
22097 /* 67151 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22098 /* 67154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22099 /* 67157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22100 /* 67161 */ // MIs[0] Operand 3
22101 /* 67161 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
22102 /* 67172 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, 0:{ *:[i32] }) => (VCFUX_0:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$VB)
22103 /* 67172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUX_0),
22104 /* 67175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22105 /* 67177 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22106 /* 67179 */ GIR_RootConstrainSelectedInstOperands,
22107 /* 67180 */ // GIR_Coverage, 319,
22108 /* 67180 */ GIR_EraseRootFromParent_Done,
22109 /* 67181 */ // Label 1031: @67181
22110 /* 67181 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(67224), // Rule ID 320 //
22111 /* 67186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22112 /* 67189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctsxs),
22113 /* 67194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22114 /* 67197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22115 /* 67200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22116 /* 67204 */ // MIs[0] Operand 3
22117 /* 67204 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
22118 /* 67215 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10385:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, 0:{ *:[i32] }) => (VCTSXS_0:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$VB)
22119 /* 67215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTSXS_0),
22120 /* 67218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22121 /* 67220 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22122 /* 67222 */ GIR_RootConstrainSelectedInstOperands,
22123 /* 67223 */ // GIR_Coverage, 320,
22124 /* 67223 */ GIR_EraseRootFromParent_Done,
22125 /* 67224 */ // Label 1032: @67224
22126 /* 67224 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(67295), // Rule ID 3350 //
22127 /* 67229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22128 /* 67232 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvbm),
22129 /* 67237 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22130 /* 67240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22131 /* 67243 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22132 /* 67246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22133 /* 67250 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
22134 /* 67254 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
22135 /* 67258 */ // MIs[1] Operand 1
22136 /* 67258 */ // No operand predicates
22137 /* 67258 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22138 /* 67260 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10923:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXGENPCVBM:{ *:[v4i32] } ?:{ *:[v16i8] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] })
22139 /* 67260 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22140 /* 67263 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVBM),
22141 /* 67267 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22142 /* 67272 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB
22143 /* 67276 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM
22144 /* 67279 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22145 /* 67281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22146 /* 67284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
22147 /* 67286 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22148 /* 67289 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
22149 /* 67294 */ // GIR_Coverage, 3350,
22150 /* 67294 */ GIR_EraseRootFromParent_Done,
22151 /* 67295 */ // Label 1033: @67295
22152 /* 67295 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(67366), // Rule ID 3351 //
22153 /* 67300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22154 /* 67303 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvhm),
22155 /* 67308 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22156 /* 67311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22157 /* 67314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22158 /* 67317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22159 /* 67321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
22160 /* 67325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
22161 /* 67329 */ // MIs[1] Operand 1
22162 /* 67329 */ // No operand predicates
22163 /* 67329 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22164 /* 67331 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10925:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXGENPCVHM:{ *:[v4i32] } ?:{ *:[v8i16] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] })
22165 /* 67331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22166 /* 67334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVHM),
22167 /* 67338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22168 /* 67343 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB
22169 /* 67347 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM
22170 /* 67350 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22171 /* 67352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22172 /* 67355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
22173 /* 67357 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22174 /* 67360 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
22175 /* 67365 */ // GIR_Coverage, 3351,
22176 /* 67365 */ GIR_EraseRootFromParent_Done,
22177 /* 67366 */ // Label 1034: @67366
22178 /* 67366 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(67437), // Rule ID 3352 //
22179 /* 67371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22180 /* 67374 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvwm),
22181 /* 67379 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22182 /* 67382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22183 /* 67385 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22184 /* 67388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22185 /* 67392 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
22186 /* 67396 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
22187 /* 67400 */ // MIs[1] Operand 1
22188 /* 67400 */ // No operand predicates
22189 /* 67400 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22190 /* 67402 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10926:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v4i32] } (XXGENPCVWM:{ *:[v4i32] } ?:{ *:[v4i32] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] })
22191 /* 67402 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22192 /* 67405 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVWM),
22193 /* 67409 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22194 /* 67414 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB
22195 /* 67418 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM
22196 /* 67421 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22197 /* 67423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22198 /* 67426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
22199 /* 67428 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22200 /* 67431 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
22201 /* 67436 */ // GIR_Coverage, 3352,
22202 /* 67436 */ GIR_EraseRootFromParent_Done,
22203 /* 67437 */ // Label 1035: @67437
22204 /* 67437 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(67508), // Rule ID 3353 //
22205 /* 67442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22206 /* 67445 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvdm),
22207 /* 67450 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22208 /* 67453 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22209 /* 67456 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22210 /* 67459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22211 /* 67463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
22212 /* 67467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
22213 /* 67471 */ // MIs[1] Operand 1
22214 /* 67471 */ // No operand predicates
22215 /* 67471 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22216 /* 67473 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10924:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXGENPCVDM:{ *:[v4i32] } ?:{ *:[v2i64] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] })
22217 /* 67473 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
22218 /* 67476 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVDM),
22219 /* 67480 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22220 /* 67485 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB
22221 /* 67489 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM
22222 /* 67492 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22223 /* 67494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22224 /* 67497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
22225 /* 67499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22226 /* 67502 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
22227 /* 67507 */ // GIR_Coverage, 3353,
22228 /* 67507 */ GIR_EraseRootFromParent_Done,
22229 /* 67508 */ // Label 1036: @67508
22230 /* 67508 */ GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(67545), // Rule ID 313 //
22231 /* 67513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22232 /* 67516 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfsx),
22233 /* 67521 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22234 /* 67524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22235 /* 67527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22236 /* 67531 */ // MIs[0] VA
22237 /* 67531 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22238 /* 67534 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10324:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCFSX:{ *:[v4f32] } (timm:{ *:[i32] }):$VA, v4i32:{ *:[v4i32] }:$VB)
22239 /* 67534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFSX),
22240 /* 67537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22241 /* 67539 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
22242 /* 67541 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22243 /* 67543 */ GIR_RootConstrainSelectedInstOperands,
22244 /* 67544 */ // GIR_Coverage, 313,
22245 /* 67544 */ GIR_EraseRootFromParent_Done,
22246 /* 67545 */ // Label 1037: @67545
22247 /* 67545 */ GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(67582), // Rule ID 314 //
22248 /* 67550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22249 /* 67553 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfux),
22250 /* 67558 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22251 /* 67561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22252 /* 67564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22253 /* 67568 */ // MIs[0] VA
22254 /* 67568 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22255 /* 67571 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCFUX:{ *:[v4f32] } (timm:{ *:[i32] }):$VA, v4i32:{ *:[v4i32] }:$VB)
22256 /* 67571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUX),
22257 /* 67574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22258 /* 67576 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
22259 /* 67578 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22260 /* 67580 */ GIR_RootConstrainSelectedInstOperands,
22261 /* 67581 */ // GIR_Coverage, 314,
22262 /* 67581 */ GIR_EraseRootFromParent_Done,
22263 /* 67582 */ // Label 1038: @67582
22264 /* 67582 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(67619), // Rule ID 315 //
22265 /* 67587 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22266 /* 67590 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctsxs),
22267 /* 67595 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22268 /* 67598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22269 /* 67601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22270 /* 67605 */ // MIs[0] VA
22271 /* 67605 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22272 /* 67608 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10385:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCTSXS:{ *:[v4i32] } (timm:{ *:[i32] }):$VA, v4f32:{ *:[v4f32] }:$VB)
22273 /* 67608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTSXS),
22274 /* 67611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22275 /* 67613 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
22276 /* 67615 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22277 /* 67617 */ GIR_RootConstrainSelectedInstOperands,
22278 /* 67618 */ // GIR_Coverage, 315,
22279 /* 67618 */ GIR_EraseRootFromParent_Done,
22280 /* 67619 */ // Label 1039: @67619
22281 /* 67619 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(67656), // Rule ID 316 //
22282 /* 67624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22283 /* 67627 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctuxs),
22284 /* 67632 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22285 /* 67635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22286 /* 67638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22287 /* 67642 */ // MIs[0] VA
22288 /* 67642 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22289 /* 67645 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10386:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCTUXS:{ *:[v4i32] } (timm:{ *:[i32] }):$VA, v4f32:{ *:[v4f32] }:$VB)
22290 /* 67645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTUXS),
22291 /* 67648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22292 /* 67650 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
22293 /* 67652 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22294 /* 67654 */ GIR_RootConstrainSelectedInstOperands,
22295 /* 67655 */ // GIR_Coverage, 316,
22296 /* 67655 */ GIR_EraseRootFromParent_Done,
22297 /* 67656 */ // Label 1040: @67656
22298 /* 67656 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(67696), // Rule ID 553 //
22299 /* 67661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
22300 /* 67664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_national2packed),
22301 /* 67669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22302 /* 67672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22303 /* 67675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22304 /* 67679 */ // MIs[0] PS
22305 /* 67679 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22306 /* 67682 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10795:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$PS) => (BCDCFN_rec:{ *:[v16i8] }:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$PS)
22307 /* 67682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDCFN_rec),
22308 /* 67685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22309 /* 67687 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22310 /* 67689 */ GIR_RootToRootCopy, /*OpIdx*/3, // PS
22311 /* 67691 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0,
22312 /* 67694 */ GIR_RootConstrainSelectedInstOperands,
22313 /* 67695 */ // GIR_Coverage, 553,
22314 /* 67695 */ GIR_EraseRootFromParent_Done,
22315 /* 67696 */ // Label 1041: @67696
22316 /* 67696 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(67736), // Rule ID 554 //
22317 /* 67701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
22318 /* 67704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_zoned2packed),
22319 /* 67709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22320 /* 67712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22321 /* 67715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22322 /* 67719 */ // MIs[0] PS
22323 /* 67719 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22324 /* 67722 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10930:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$PS) => (BCDCFZ_rec:{ *:[v16i8] }:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$PS)
22325 /* 67722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDCFZ_rec),
22326 /* 67725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22327 /* 67727 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22328 /* 67729 */ GIR_RootToRootCopy, /*OpIdx*/3, // PS
22329 /* 67731 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0,
22330 /* 67734 */ GIR_RootConstrainSelectedInstOperands,
22331 /* 67735 */ // GIR_Coverage, 554,
22332 /* 67735 */ GIR_EraseRootFromParent_Done,
22333 /* 67736 */ // Label 1042: @67736
22334 /* 67736 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(67776), // Rule ID 556 //
22335 /* 67741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
22336 /* 67744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_packed2zoned),
22337 /* 67749 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22338 /* 67752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22339 /* 67755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22340 /* 67759 */ // MIs[0] PS
22341 /* 67759 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22342 /* 67762 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10798:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$PS) => (BCDCTZ_rec:{ *:[v16i8] }:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$PS)
22343 /* 67762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDCTZ_rec),
22344 /* 67765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22345 /* 67767 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22346 /* 67769 */ GIR_RootToRootCopy, /*OpIdx*/3, // PS
22347 /* 67771 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0,
22348 /* 67774 */ GIR_RootConstrainSelectedInstOperands,
22349 /* 67775 */ // GIR_Coverage, 556,
22350 /* 67775 */ GIR_EraseRootFromParent_Done,
22351 /* 67776 */ // Label 1043: @67776
22352 /* 67776 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(67813), // Rule ID 1098 //
22353 /* 67781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22354 /* 67784 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbb),
22355 /* 67789 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22356 /* 67792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22357 /* 67795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22358 /* 67799 */ // MIs[0] MP
22359 /* 67799 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22360 /* 67802 */ // (intrinsic_wo_chain:{ *:[i64] } 10381:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBB:{ *:[i64] } v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$MP)
22361 /* 67802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBB),
22362 /* 67805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD]
22363 /* 67807 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22364 /* 67809 */ GIR_RootToRootCopy, /*OpIdx*/3, // MP
22365 /* 67811 */ GIR_RootConstrainSelectedInstOperands,
22366 /* 67812 */ // GIR_Coverage, 1098,
22367 /* 67812 */ GIR_EraseRootFromParent_Done,
22368 /* 67813 */ // Label 1044: @67813
22369 /* 67813 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(67850), // Rule ID 1099 //
22370 /* 67818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22371 /* 67821 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbh),
22372 /* 67826 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22373 /* 67829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22374 /* 67832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22375 /* 67836 */ // MIs[0] MP
22376 /* 67836 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22377 /* 67839 */ // (intrinsic_wo_chain:{ *:[i64] } 10383:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBH:{ *:[i64] } v8i16:{ *:[v8i16] }:$VB, (timm:{ *:[i32] }):$MP)
22378 /* 67839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBH),
22379 /* 67842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD]
22380 /* 67844 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22381 /* 67846 */ GIR_RootToRootCopy, /*OpIdx*/3, // MP
22382 /* 67848 */ GIR_RootConstrainSelectedInstOperands,
22383 /* 67849 */ // GIR_Coverage, 1099,
22384 /* 67849 */ GIR_EraseRootFromParent_Done,
22385 /* 67850 */ // Label 1045: @67850
22386 /* 67850 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(67887), // Rule ID 1100 //
22387 /* 67855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22388 /* 67858 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbw),
22389 /* 67863 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22390 /* 67866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22391 /* 67869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22392 /* 67873 */ // MIs[0] MP
22393 /* 67873 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22394 /* 67876 */ // (intrinsic_wo_chain:{ *:[i64] } 10384:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBW:{ *:[i64] } v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$MP)
22395 /* 67876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBW),
22396 /* 67879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD]
22397 /* 67881 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22398 /* 67883 */ GIR_RootToRootCopy, /*OpIdx*/3, // MP
22399 /* 67885 */ GIR_RootConstrainSelectedInstOperands,
22400 /* 67886 */ // GIR_Coverage, 1100,
22401 /* 67886 */ GIR_EraseRootFromParent_Done,
22402 /* 67887 */ // Label 1046: @67887
22403 /* 67887 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(67924), // Rule ID 1101 //
22404 /* 67892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22405 /* 67895 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbd),
22406 /* 67900 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22407 /* 67903 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22408 /* 67906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22409 /* 67910 */ // MIs[0] MP
22410 /* 67910 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22411 /* 67913 */ // (intrinsic_wo_chain:{ *:[i64] } 10382:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBD:{ *:[i64] } v2i64:{ *:[v2i64] }:$VB, (timm:{ *:[i32] }):$MP)
22412 /* 67913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBD),
22413 /* 67916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD]
22414 /* 67918 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22415 /* 67920 */ GIR_RootToRootCopy, /*OpIdx*/3, // MP
22416 /* 67922 */ GIR_RootConstrainSelectedInstOperands,
22417 /* 67923 */ // GIR_Coverage, 1101,
22418 /* 67923 */ GIR_EraseRootFromParent_Done,
22419 /* 67924 */ // Label 1047: @67924
22420 /* 67924 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(67961), // Rule ID 1115 //
22421 /* 67929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
22422 /* 67932 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vgnb),
22423 /* 67937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22424 /* 67940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
22425 /* 67943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22426 /* 67947 */ // MIs[0] N
22427 /* 67947 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22428 /* 67950 */ // (intrinsic_wo_chain:{ *:[i64] } 10421:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB, (timm:{ *:[i32] }):$N) => (VGNB:{ *:[i64] } v1i128:{ *:[v1i128] }:$VB, (timm:{ *:[i32] }):$N)
22429 /* 67950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VGNB),
22430 /* 67953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD]
22431 /* 67955 */ GIR_RootToRootCopy, /*OpIdx*/2, // VB
22432 /* 67957 */ GIR_RootToRootCopy, /*OpIdx*/3, // N
22433 /* 67959 */ GIR_RootConstrainSelectedInstOperands,
22434 /* 67960 */ // GIR_Coverage, 1115,
22435 /* 67960 */ GIR_EraseRootFromParent_Done,
22436 /* 67961 */ // Label 1048: @67961
22437 /* 67961 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(67998), // Rule ID 1169 //
22438 /* 67966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture),
22439 /* 67969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmsha3hash),
22440 /* 67974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2048s1,
22441 /* 67977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2048s1,
22442 /* 67980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRpRCRegClassID),
22443 /* 67984 */ // MIs[0] SR
22444 /* 67984 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
22445 /* 67987 */ // (intrinsic_wo_chain:{ *:[v2048i1] } 10690:{ *:[iPTR] }, v2048i1:{ *:[v2048i1] }:$ATpi, (timm:{ *:[i32] }):$SR) => (DMSHA3HASH:{ *:[v2048i1] } v2048i1:{ *:[v2048i1] }:$ATpi, (timm:{ *:[i32] }):$SR)
22446 /* 67987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMSHA3HASH),
22447 /* 67990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[ATp]
22448 /* 67992 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATpi
22449 /* 67994 */ GIR_RootToRootCopy, /*OpIdx*/3, // SR
22450 /* 67996 */ GIR_RootConstrainSelectedInstOperands,
22451 /* 67997 */ // GIR_Coverage, 1169,
22452 /* 67997 */ GIR_EraseRootFromParent_Done,
22453 /* 67998 */ // Label 1049: @67998
22454 /* 67998 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(68043), // Rule ID 204 //
22455 /* 68003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv),
22456 /* 68006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divwe),
22457 /* 68011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22458 /* 68014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22459 /* 68017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22460 /* 68020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22461 /* 68024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22462 /* 68028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22463 /* 68032 */ // (intrinsic_wo_chain:{ *:[i32] } 10625:{ *:[iPTR] }, gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) => (DIVWE:{ *:[i32] } gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB)
22464 /* 68032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVWE),
22465 /* 68035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22466 /* 68037 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
22467 /* 68039 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
22468 /* 68041 */ GIR_RootConstrainSelectedInstOperands,
22469 /* 68042 */ // GIR_Coverage, 204,
22470 /* 68042 */ GIR_EraseRootFromParent_Done,
22471 /* 68043 */ // Label 1050: @68043
22472 /* 68043 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(68088), // Rule ID 205 //
22473 /* 68048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv),
22474 /* 68051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divweu),
22475 /* 68056 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22476 /* 68059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22477 /* 68062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22478 /* 68065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22479 /* 68069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22480 /* 68073 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22481 /* 68077 */ // (intrinsic_wo_chain:{ *:[i32] } 10626:{ *:[iPTR] }, gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) => (DIVWEU:{ *:[i32] } gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB)
22482 /* 68077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVWEU),
22483 /* 68080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22484 /* 68082 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
22485 /* 68084 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
22486 /* 68086 */ GIR_RootConstrainSelectedInstOperands,
22487 /* 68087 */ // GIR_Coverage, 205,
22488 /* 68087 */ GIR_EraseRootFromParent_Done,
22489 /* 68088 */ // Label 1051: @68088
22490 /* 68088 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(68133), // Rule ID 690 //
22491 /* 68093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBPERMD),
22492 /* 68096 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bpermd),
22493 /* 68101 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22494 /* 68104 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22495 /* 68107 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22496 /* 68110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22497 /* 68114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22498 /* 68118 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22499 /* 68122 */ // (intrinsic_wo_chain:{ *:[i64] } 10584:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RST, g8rc:{ *:[i64] }:$RB) => (BPERMD:{ *:[i64] } g8rc:{ *:[i64] }:$RST, g8rc:{ *:[i64] }:$RB)
22500 /* 68122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BPERMD),
22501 /* 68125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
22502 /* 68127 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
22503 /* 68129 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
22504 /* 68131 */ GIR_RootConstrainSelectedInstOperands,
22505 /* 68132 */ // GIR_Coverage, 690,
22506 /* 68132 */ GIR_EraseRootFromParent_Done,
22507 /* 68133 */ // Label 1052: @68133
22508 /* 68133 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(68178), // Rule ID 699 //
22509 /* 68138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv),
22510 /* 68141 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divde),
22511 /* 68146 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22512 /* 68149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22513 /* 68152 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22514 /* 68155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22515 /* 68159 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22516 /* 68163 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22517 /* 68167 */ // (intrinsic_wo_chain:{ *:[i64] } 10622:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) => (DIVDE:{ *:[i64] } g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB)
22518 /* 68167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVDE),
22519 /* 68170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22520 /* 68172 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
22521 /* 68174 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
22522 /* 68176 */ GIR_RootConstrainSelectedInstOperands,
22523 /* 68177 */ // GIR_Coverage, 699,
22524 /* 68177 */ GIR_EraseRootFromParent_Done,
22525 /* 68178 */ // Label 1053: @68178
22526 /* 68178 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(68223), // Rule ID 704 //
22527 /* 68183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv),
22528 /* 68186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divdeu),
22529 /* 68191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22530 /* 68194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22531 /* 68197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22532 /* 68200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22533 /* 68204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22534 /* 68208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22535 /* 68212 */ // (intrinsic_wo_chain:{ *:[i64] } 10623:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) => (DIVDEU:{ *:[i64] } g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB)
22536 /* 68212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVDEU),
22537 /* 68215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22538 /* 68217 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
22539 /* 68219 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
22540 /* 68221 */ GIR_RootConstrainSelectedInstOperands,
22541 /* 68222 */ // GIR_Coverage, 704,
22542 /* 68222 */ GIR_EraseRootFromParent_Done,
22543 /* 68223 */ // Label 1054: @68223
22544 /* 68223 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(68289), // Rule ID 1564 //
22545 /* 68228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0),
22546 /* 68231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpeqb),
22547 /* 68236 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22548 /* 68239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22549 /* 68242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22550 /* 68245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22551 /* 68249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22552 /* 68253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22553 /* 68257 */ // (intrinsic_wo_chain:{ *:[i64] } 10592:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (SETB8:{ *:[i64] } (CMPEQB:{ *:[i32] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b))
22554 /* 68257 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22555 /* 68260 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPEQB),
22556 /* 68264 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22557 /* 68269 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // a
22558 /* 68273 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // b
22559 /* 68277 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22560 /* 68279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETB8),
22561 /* 68282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22562 /* 68284 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22563 /* 68287 */ GIR_RootConstrainSelectedInstOperands,
22564 /* 68288 */ // GIR_Coverage, 1564,
22565 /* 68288 */ GIR_EraseRootFromParent_Done,
22566 /* 68289 */ // Label 1055: @68289
22567 /* 68289 */ GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(68355), // Rule ID 1565 //
22568 /* 68294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0),
22569 /* 68297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setb),
22570 /* 68302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22571 /* 68305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22572 /* 68308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22573 /* 68311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22574 /* 68315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22575 /* 68319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22576 /* 68323 */ // (intrinsic_wo_chain:{ *:[i64] } 10812:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (SETB8:{ *:[i64] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b))
22577 /* 68323 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22578 /* 68326 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
22579 /* 68330 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22580 /* 68335 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // a
22581 /* 68339 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // b
22582 /* 68343 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22583 /* 68345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETB8),
22584 /* 68348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22585 /* 68350 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22586 /* 68353 */ GIR_RootConstrainSelectedInstOperands,
22587 /* 68354 */ // GIR_Coverage, 1565,
22588 /* 68354 */ GIR_EraseRootFromParent_Done,
22589 /* 68355 */ // Label 1056: @68355
22590 /* 68355 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(68400), // Rule ID 1569 //
22591 /* 68360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode),
22592 /* 68363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhd),
22593 /* 68368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22594 /* 68371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22595 /* 68374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22596 /* 68377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22597 /* 68381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22598 /* 68385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22599 /* 68389 */ // (intrinsic_wo_chain:{ *:[i64] } 10791:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (MULHD:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b)
22600 /* 68389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHD),
22601 /* 68392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22602 /* 68394 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22603 /* 68396 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22604 /* 68398 */ GIR_RootConstrainSelectedInstOperands,
22605 /* 68399 */ // GIR_Coverage, 1569,
22606 /* 68399 */ GIR_EraseRootFromParent_Done,
22607 /* 68400 */ // Label 1057: @68400
22608 /* 68400 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(68445), // Rule ID 1570 //
22609 /* 68405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode),
22610 /* 68408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhdu),
22611 /* 68413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22612 /* 68416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22613 /* 68419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22614 /* 68422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22615 /* 68426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22616 /* 68430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22617 /* 68434 */ // (intrinsic_wo_chain:{ *:[i64] } 10792:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (MULHDU:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b)
22618 /* 68434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHDU),
22619 /* 68437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22620 /* 68439 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22621 /* 68441 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22622 /* 68443 */ GIR_RootConstrainSelectedInstOperands,
22623 /* 68444 */ // GIR_Coverage, 1570,
22624 /* 68444 */ GIR_EraseRootFromParent_Done,
22625 /* 68445 */ // Label 1058: @68445
22626 /* 68445 */ GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(68487), // Rule ID 1573 //
22627 /* 68450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpb),
22628 /* 68455 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22629 /* 68458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22630 /* 68461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22631 /* 68464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22632 /* 68468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22633 /* 68472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
22634 /* 68476 */ // (intrinsic_wo_chain:{ *:[i64] } 10591:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (CMPB8:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b)
22635 /* 68476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CMPB8),
22636 /* 68479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
22637 /* 68481 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22638 /* 68483 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22639 /* 68485 */ GIR_RootConstrainSelectedInstOperands,
22640 /* 68486 */ // GIR_Coverage, 1573,
22641 /* 68486 */ GIR_EraseRootFromParent_Done,
22642 /* 68487 */ // Label 1059: @68487
22643 /* 68487 */ GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(68529), // Rule ID 4882 //
22644 /* 68492 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhw),
22645 /* 68497 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22646 /* 68500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22647 /* 68503 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22648 /* 68506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22649 /* 68510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22650 /* 68514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22651 /* 68518 */ // (intrinsic_wo_chain:{ *:[i32] } 10793:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (MULHW:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b)
22652 /* 68518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHW),
22653 /* 68521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22654 /* 68523 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22655 /* 68525 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22656 /* 68527 */ GIR_RootConstrainSelectedInstOperands,
22657 /* 68528 */ // GIR_Coverage, 4882,
22658 /* 68528 */ GIR_EraseRootFromParent_Done,
22659 /* 68529 */ // Label 1060: @68529
22660 /* 68529 */ GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(68571), // Rule ID 4883 //
22661 /* 68534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhwu),
22662 /* 68539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22663 /* 68542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22664 /* 68545 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22665 /* 68548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22666 /* 68552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22667 /* 68556 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22668 /* 68560 */ // (intrinsic_wo_chain:{ *:[i32] } 10794:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (MULHWU:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b)
22669 /* 68560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHWU),
22670 /* 68563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22671 /* 68565 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22672 /* 68567 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22673 /* 68569 */ GIR_RootConstrainSelectedInstOperands,
22674 /* 68570 */ // GIR_Coverage, 4883,
22675 /* 68570 */ GIR_EraseRootFromParent_Done,
22676 /* 68571 */ // Label 1061: @68571
22677 /* 68571 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(68613), // Rule ID 4884 //
22678 /* 68576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpb),
22679 /* 68581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22680 /* 68584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22681 /* 68587 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22682 /* 68590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22683 /* 68594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22684 /* 68598 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22685 /* 68602 */ // (intrinsic_wo_chain:{ *:[i32] } 10591:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (CMPB:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b)
22686 /* 68602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CMPB),
22687 /* 68605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
22688 /* 68607 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22689 /* 68609 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22690 /* 68611 */ GIR_RootConstrainSelectedInstOperands,
22691 /* 68612 */ // GIR_Coverage, 4884,
22692 /* 68612 */ GIR_EraseRootFromParent_Done,
22693 /* 68613 */ // Label 1062: @68613
22694 /* 68613 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(68647), // Rule ID 76 //
22695 /* 68618 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addg6s),
22696 /* 68623 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22697 /* 68626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22698 /* 68629 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22699 /* 68632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
22700 /* 68636 */ // (intrinsic_wo_chain:{ *:[i32] } 10263:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (ADDG6S:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
22701 /* 68636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDG6S),
22702 /* 68639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
22703 /* 68641 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
22704 /* 68643 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
22705 /* 68645 */ GIR_RootConstrainSelectedInstOperands,
22706 /* 68646 */ // GIR_Coverage, 76,
22707 /* 68646 */ GIR_EraseRootFromParent_Done,
22708 /* 68647 */ // Label 1063: @68647
22709 /* 68647 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(68684), // Rule ID 304 //
22710 /* 68652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22711 /* 68655 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddcuw),
22712 /* 68660 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22713 /* 68663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22714 /* 68666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22715 /* 68669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22716 /* 68673 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10307:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDCUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
22717 /* 68673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDCUW),
22718 /* 68676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22719 /* 68678 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22720 /* 68680 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22721 /* 68682 */ GIR_RootConstrainSelectedInstOperands,
22722 /* 68683 */ // GIR_Coverage, 304,
22723 /* 68683 */ GIR_EraseRootFromParent_Done,
22724 /* 68684 */ // Label 1064: @68684
22725 /* 68684 */ GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(68721), // Rule ID 305 //
22726 /* 68689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22727 /* 68692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddsbs),
22728 /* 68697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22729 /* 68700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22730 /* 68703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22731 /* 68706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22732 /* 68710 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10310:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDSBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
22733 /* 68710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSBS),
22734 /* 68713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22735 /* 68715 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22736 /* 68717 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22737 /* 68719 */ GIR_RootConstrainSelectedInstOperands,
22738 /* 68720 */ // GIR_Coverage, 305,
22739 /* 68720 */ GIR_EraseRootFromParent_Done,
22740 /* 68721 */ // Label 1065: @68721
22741 /* 68721 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(68758), // Rule ID 306 //
22742 /* 68726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22743 /* 68729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddshs),
22744 /* 68734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22745 /* 68737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22746 /* 68740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22747 /* 68743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22748 /* 68747 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10311:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
22749 /* 68747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSHS),
22750 /* 68750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22751 /* 68752 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22752 /* 68754 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22753 /* 68756 */ GIR_RootConstrainSelectedInstOperands,
22754 /* 68757 */ // GIR_Coverage, 306,
22755 /* 68757 */ GIR_EraseRootFromParent_Done,
22756 /* 68758 */ // Label 1066: @68758
22757 /* 68758 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(68795), // Rule ID 307 //
22758 /* 68763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22759 /* 68766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddsws),
22760 /* 68771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22761 /* 68774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22762 /* 68777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22763 /* 68780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22764 /* 68784 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10312:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
22765 /* 68784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSWS),
22766 /* 68787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22767 /* 68789 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22768 /* 68791 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22769 /* 68793 */ GIR_RootConstrainSelectedInstOperands,
22770 /* 68794 */ // GIR_Coverage, 307,
22771 /* 68794 */ GIR_EraseRootFromParent_Done,
22772 /* 68795 */ // Label 1067: @68795
22773 /* 68795 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(68832), // Rule ID 308 //
22774 /* 68800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22775 /* 68803 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddubs),
22776 /* 68808 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22777 /* 68811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22778 /* 68814 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22779 /* 68817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22780 /* 68821 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10313:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDUBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
22781 /* 68821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUBS),
22782 /* 68824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22783 /* 68826 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22784 /* 68828 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22785 /* 68830 */ GIR_RootConstrainSelectedInstOperands,
22786 /* 68831 */ // GIR_Coverage, 308,
22787 /* 68831 */ GIR_EraseRootFromParent_Done,
22788 /* 68832 */ // Label 1068: @68832
22789 /* 68832 */ GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(68869), // Rule ID 309 //
22790 /* 68837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22791 /* 68840 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vadduhs),
22792 /* 68845 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22793 /* 68848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22794 /* 68851 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22795 /* 68854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22796 /* 68858 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10314:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDUHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
22797 /* 68858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUHS),
22798 /* 68861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22799 /* 68863 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22800 /* 68865 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22801 /* 68867 */ GIR_RootConstrainSelectedInstOperands,
22802 /* 68868 */ // GIR_Coverage, 309,
22803 /* 68868 */ GIR_EraseRootFromParent_Done,
22804 /* 68869 */ // Label 1069: @68869
22805 /* 68869 */ GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(68906), // Rule ID 310 //
22806 /* 68874 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22807 /* 68877 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vadduws),
22808 /* 68882 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22809 /* 68885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22810 /* 68888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22811 /* 68891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22812 /* 68895 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10315:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDUWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
22813 /* 68895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUWS),
22814 /* 68898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22815 /* 68900 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22816 /* 68902 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22817 /* 68904 */ GIR_RootConstrainSelectedInstOperands,
22818 /* 68905 */ // GIR_Coverage, 310,
22819 /* 68905 */ GIR_EraseRootFromParent_Done,
22820 /* 68906 */ // Label 1070: @68906
22821 /* 68906 */ GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(68943), // Rule ID 323 //
22822 /* 68911 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22823 /* 68914 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsb),
22824 /* 68919 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22825 /* 68922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22826 /* 68925 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22827 /* 68928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22828 /* 68932 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10316:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VAVGSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
22829 /* 68932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSB),
22830 /* 68935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22831 /* 68937 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22832 /* 68939 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22833 /* 68941 */ GIR_RootConstrainSelectedInstOperands,
22834 /* 68942 */ // GIR_Coverage, 323,
22835 /* 68942 */ GIR_EraseRootFromParent_Done,
22836 /* 68943 */ // Label 1071: @68943
22837 /* 68943 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(68980), // Rule ID 324 //
22838 /* 68948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22839 /* 68951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsh),
22840 /* 68956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22841 /* 68959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22842 /* 68962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22843 /* 68965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22844 /* 68969 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10317:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VAVGSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
22845 /* 68969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSH),
22846 /* 68972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22847 /* 68974 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22848 /* 68976 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22849 /* 68978 */ GIR_RootConstrainSelectedInstOperands,
22850 /* 68979 */ // GIR_Coverage, 324,
22851 /* 68979 */ GIR_EraseRootFromParent_Done,
22852 /* 68980 */ // Label 1072: @68980
22853 /* 68980 */ GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(69017), // Rule ID 325 //
22854 /* 68985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22855 /* 68988 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsw),
22856 /* 68993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22857 /* 68996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22858 /* 68999 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22859 /* 69002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22860 /* 69006 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10318:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAVGSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
22861 /* 69006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSW),
22862 /* 69009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22863 /* 69011 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22864 /* 69013 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22865 /* 69015 */ GIR_RootConstrainSelectedInstOperands,
22866 /* 69016 */ // GIR_Coverage, 325,
22867 /* 69016 */ GIR_EraseRootFromParent_Done,
22868 /* 69017 */ // Label 1073: @69017
22869 /* 69017 */ GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(69054), // Rule ID 326 //
22870 /* 69022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22871 /* 69025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgub),
22872 /* 69030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22873 /* 69033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22874 /* 69036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22875 /* 69039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22876 /* 69043 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10319:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VAVGUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
22877 /* 69043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUB),
22878 /* 69046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22879 /* 69048 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22880 /* 69050 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22881 /* 69052 */ GIR_RootConstrainSelectedInstOperands,
22882 /* 69053 */ // GIR_Coverage, 326,
22883 /* 69053 */ GIR_EraseRootFromParent_Done,
22884 /* 69054 */ // Label 1074: @69054
22885 /* 69054 */ GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(69091), // Rule ID 327 //
22886 /* 69059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22887 /* 69062 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavguh),
22888 /* 69067 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22889 /* 69070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22890 /* 69073 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22891 /* 69076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22892 /* 69080 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10320:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VAVGUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
22893 /* 69080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUH),
22894 /* 69083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22895 /* 69085 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22896 /* 69087 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22897 /* 69089 */ GIR_RootConstrainSelectedInstOperands,
22898 /* 69090 */ // GIR_Coverage, 327,
22899 /* 69090 */ GIR_EraseRootFromParent_Done,
22900 /* 69091 */ // Label 1075: @69091
22901 /* 69091 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(69128), // Rule ID 328 //
22902 /* 69096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22903 /* 69099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavguw),
22904 /* 69104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22905 /* 69107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22906 /* 69110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22907 /* 69113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22908 /* 69117 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10321:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAVGUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
22909 /* 69117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUW),
22910 /* 69120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22911 /* 69122 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22912 /* 69124 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22913 /* 69126 */ GIR_RootConstrainSelectedInstOperands,
22914 /* 69127 */ // GIR_Coverage, 328,
22915 /* 69127 */ GIR_EraseRootFromParent_Done,
22916 /* 69128 */ // Label 1076: @69128
22917 /* 69128 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(69165), // Rule ID 329 //
22918 /* 69133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22919 /* 69136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxfp),
22920 /* 69141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22921 /* 69144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22922 /* 69147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22923 /* 69150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22924 /* 69154 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10440:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VMAXFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB)
22925 /* 69154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXFP),
22926 /* 69157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22927 /* 69159 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22928 /* 69161 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22929 /* 69163 */ GIR_RootConstrainSelectedInstOperands,
22930 /* 69164 */ // GIR_Coverage, 329,
22931 /* 69164 */ GIR_EraseRootFromParent_Done,
22932 /* 69165 */ // Label 1077: @69165
22933 /* 69165 */ GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(69202), // Rule ID 330 //
22934 /* 69170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22935 /* 69173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsb),
22936 /* 69178 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22937 /* 69181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22938 /* 69184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22939 /* 69187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22940 /* 69191 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10441:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMAXSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
22941 /* 69191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSB),
22942 /* 69194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22943 /* 69196 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22944 /* 69198 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22945 /* 69200 */ GIR_RootConstrainSelectedInstOperands,
22946 /* 69201 */ // GIR_Coverage, 330,
22947 /* 69201 */ GIR_EraseRootFromParent_Done,
22948 /* 69202 */ // Label 1078: @69202
22949 /* 69202 */ GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(69239), // Rule ID 331 //
22950 /* 69207 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22951 /* 69210 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsh),
22952 /* 69215 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22953 /* 69218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22954 /* 69221 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22955 /* 69224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22956 /* 69228 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10443:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMAXSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
22957 /* 69228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSH),
22958 /* 69231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22959 /* 69233 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22960 /* 69235 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22961 /* 69237 */ GIR_RootConstrainSelectedInstOperands,
22962 /* 69238 */ // GIR_Coverage, 331,
22963 /* 69238 */ GIR_EraseRootFromParent_Done,
22964 /* 69239 */ // Label 1079: @69239
22965 /* 69239 */ GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(69276), // Rule ID 332 //
22966 /* 69244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22967 /* 69247 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsw),
22968 /* 69252 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22969 /* 69255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22970 /* 69258 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22971 /* 69261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22972 /* 69265 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10444:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMAXSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
22973 /* 69265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSW),
22974 /* 69268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22975 /* 69270 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22976 /* 69272 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22977 /* 69274 */ GIR_RootConstrainSelectedInstOperands,
22978 /* 69275 */ // GIR_Coverage, 332,
22979 /* 69275 */ GIR_EraseRootFromParent_Done,
22980 /* 69276 */ // Label 1080: @69276
22981 /* 69276 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(69313), // Rule ID 333 //
22982 /* 69281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22983 /* 69284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxub),
22984 /* 69289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22985 /* 69292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22986 /* 69295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22987 /* 69298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
22988 /* 69302 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10445:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMAXUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
22989 /* 69302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUB),
22990 /* 69305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
22991 /* 69307 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
22992 /* 69309 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
22993 /* 69311 */ GIR_RootConstrainSelectedInstOperands,
22994 /* 69312 */ // GIR_Coverage, 333,
22995 /* 69312 */ GIR_EraseRootFromParent_Done,
22996 /* 69313 */ // Label 1081: @69313
22997 /* 69313 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(69350), // Rule ID 334 //
22998 /* 69318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
22999 /* 69321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxuh),
23000 /* 69326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23001 /* 69329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23002 /* 69332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23003 /* 69335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23004 /* 69339 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10447:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMAXUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23005 /* 69339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUH),
23006 /* 69342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23007 /* 69344 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23008 /* 69346 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23009 /* 69348 */ GIR_RootConstrainSelectedInstOperands,
23010 /* 69349 */ // GIR_Coverage, 334,
23011 /* 69349 */ GIR_EraseRootFromParent_Done,
23012 /* 69350 */ // Label 1082: @69350
23013 /* 69350 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(69387), // Rule ID 335 //
23014 /* 69355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23015 /* 69358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxuw),
23016 /* 69363 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23017 /* 69366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23018 /* 69369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23019 /* 69372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23020 /* 69376 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10448:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMAXUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23021 /* 69376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUW),
23022 /* 69379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23023 /* 69381 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23024 /* 69383 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23025 /* 69385 */ GIR_RootConstrainSelectedInstOperands,
23026 /* 69386 */ // GIR_Coverage, 335,
23027 /* 69386 */ GIR_EraseRootFromParent_Done,
23028 /* 69387 */ // Label 1083: @69387
23029 /* 69387 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(69424), // Rule ID 336 //
23030 /* 69392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23031 /* 69395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminfp),
23032 /* 69400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23033 /* 69403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23034 /* 69406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23035 /* 69409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23036 /* 69413 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10451:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VMINFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB)
23037 /* 69413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINFP),
23038 /* 69416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23039 /* 69418 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23040 /* 69420 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23041 /* 69422 */ GIR_RootConstrainSelectedInstOperands,
23042 /* 69423 */ // GIR_Coverage, 336,
23043 /* 69423 */ GIR_EraseRootFromParent_Done,
23044 /* 69424 */ // Label 1084: @69424
23045 /* 69424 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(69461), // Rule ID 337 //
23046 /* 69429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23047 /* 69432 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsb),
23048 /* 69437 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23049 /* 69440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23050 /* 69443 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23051 /* 69446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23052 /* 69450 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10452:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMINSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23053 /* 69450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSB),
23054 /* 69453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23055 /* 69455 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23056 /* 69457 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23057 /* 69459 */ GIR_RootConstrainSelectedInstOperands,
23058 /* 69460 */ // GIR_Coverage, 337,
23059 /* 69460 */ GIR_EraseRootFromParent_Done,
23060 /* 69461 */ // Label 1085: @69461
23061 /* 69461 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(69498), // Rule ID 338 //
23062 /* 69466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23063 /* 69469 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsh),
23064 /* 69474 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23065 /* 69477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23066 /* 69480 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23067 /* 69483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23068 /* 69487 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10454:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMINSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23069 /* 69487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSH),
23070 /* 69490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23071 /* 69492 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23072 /* 69494 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23073 /* 69496 */ GIR_RootConstrainSelectedInstOperands,
23074 /* 69497 */ // GIR_Coverage, 338,
23075 /* 69497 */ GIR_EraseRootFromParent_Done,
23076 /* 69498 */ // Label 1086: @69498
23077 /* 69498 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(69535), // Rule ID 339 //
23078 /* 69503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23079 /* 69506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsw),
23080 /* 69511 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23081 /* 69514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23082 /* 69517 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23083 /* 69520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23084 /* 69524 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10455:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMINSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23085 /* 69524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSW),
23086 /* 69527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23087 /* 69529 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23088 /* 69531 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23089 /* 69533 */ GIR_RootConstrainSelectedInstOperands,
23090 /* 69534 */ // GIR_Coverage, 339,
23091 /* 69534 */ GIR_EraseRootFromParent_Done,
23092 /* 69535 */ // Label 1087: @69535
23093 /* 69535 */ GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(69572), // Rule ID 340 //
23094 /* 69540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23095 /* 69543 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminub),
23096 /* 69548 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23097 /* 69551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23098 /* 69554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23099 /* 69557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23100 /* 69561 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10456:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMINUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23101 /* 69561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUB),
23102 /* 69564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23103 /* 69566 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23104 /* 69568 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23105 /* 69570 */ GIR_RootConstrainSelectedInstOperands,
23106 /* 69571 */ // GIR_Coverage, 340,
23107 /* 69571 */ GIR_EraseRootFromParent_Done,
23108 /* 69572 */ // Label 1088: @69572
23109 /* 69572 */ GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(69609), // Rule ID 341 //
23110 /* 69577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23111 /* 69580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminuh),
23112 /* 69585 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23113 /* 69588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23114 /* 69591 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23115 /* 69594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23116 /* 69598 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10458:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMINUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23117 /* 69598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUH),
23118 /* 69601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23119 /* 69603 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23120 /* 69605 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23121 /* 69607 */ GIR_RootConstrainSelectedInstOperands,
23122 /* 69608 */ // GIR_Coverage, 341,
23123 /* 69608 */ GIR_EraseRootFromParent_Done,
23124 /* 69609 */ // Label 1089: @69609
23125 /* 69609 */ GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(69646), // Rule ID 342 //
23126 /* 69614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23127 /* 69617 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminuw),
23128 /* 69622 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23129 /* 69625 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23130 /* 69628 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23131 /* 69631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23132 /* 69635 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10459:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMINUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23133 /* 69635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUW),
23134 /* 69638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23135 /* 69640 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23136 /* 69642 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23137 /* 69644 */ GIR_RootConstrainSelectedInstOperands,
23138 /* 69645 */ // GIR_Coverage, 342,
23139 /* 69645 */ GIR_EraseRootFromParent_Done,
23140 /* 69646 */ // Label 1090: @69646
23141 /* 69646 */ GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(69683), // Rule ID 355 //
23142 /* 69651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23143 /* 69654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesb),
23144 /* 69659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23145 /* 69662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23146 /* 69665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23147 /* 69668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23148 /* 69672 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10469:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULESB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23149 /* 69672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESB),
23150 /* 69675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23151 /* 69677 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23152 /* 69679 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23153 /* 69681 */ GIR_RootConstrainSelectedInstOperands,
23154 /* 69682 */ // GIR_Coverage, 355,
23155 /* 69682 */ GIR_EraseRootFromParent_Done,
23156 /* 69683 */ // Label 1091: @69683
23157 /* 69683 */ GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(69720), // Rule ID 356 //
23158 /* 69688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23159 /* 69691 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesh),
23160 /* 69696 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23161 /* 69699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23162 /* 69702 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23163 /* 69705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23164 /* 69709 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10471:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULESH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23165 /* 69709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESH),
23166 /* 69712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23167 /* 69714 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23168 /* 69716 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23169 /* 69718 */ GIR_RootConstrainSelectedInstOperands,
23170 /* 69719 */ // GIR_Coverage, 356,
23171 /* 69719 */ GIR_EraseRootFromParent_Done,
23172 /* 69720 */ // Label 1092: @69720
23173 /* 69720 */ GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(69757), // Rule ID 357 //
23174 /* 69725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23175 /* 69728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleub),
23176 /* 69733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23177 /* 69736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23178 /* 69739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23179 /* 69742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23180 /* 69746 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10473:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULEUB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23181 /* 69746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUB),
23182 /* 69749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23183 /* 69751 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23184 /* 69753 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23185 /* 69755 */ GIR_RootConstrainSelectedInstOperands,
23186 /* 69756 */ // GIR_Coverage, 357,
23187 /* 69756 */ GIR_EraseRootFromParent_Done,
23188 /* 69757 */ // Label 1093: @69757
23189 /* 69757 */ GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(69794), // Rule ID 358 //
23190 /* 69762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23191 /* 69765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleuh),
23192 /* 69770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23193 /* 69773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23194 /* 69776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23195 /* 69779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23196 /* 69783 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10475:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULEUH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23197 /* 69783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUH),
23198 /* 69786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23199 /* 69788 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23200 /* 69790 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23201 /* 69792 */ GIR_RootConstrainSelectedInstOperands,
23202 /* 69793 */ // GIR_Coverage, 358,
23203 /* 69793 */ GIR_EraseRootFromParent_Done,
23204 /* 69794 */ // Label 1094: @69794
23205 /* 69794 */ GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(69831), // Rule ID 359 //
23206 /* 69799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23207 /* 69802 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosb),
23208 /* 69807 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23209 /* 69810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23210 /* 69813 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23211 /* 69816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23212 /* 69820 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10481:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULOSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23213 /* 69820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSB),
23214 /* 69823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23215 /* 69825 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23216 /* 69827 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23217 /* 69829 */ GIR_RootConstrainSelectedInstOperands,
23218 /* 69830 */ // GIR_Coverage, 359,
23219 /* 69830 */ GIR_EraseRootFromParent_Done,
23220 /* 69831 */ // Label 1095: @69831
23221 /* 69831 */ GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(69868), // Rule ID 360 //
23222 /* 69836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23223 /* 69839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosh),
23224 /* 69844 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23225 /* 69847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23226 /* 69850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23227 /* 69853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23228 /* 69857 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10483:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULOSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23229 /* 69857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSH),
23230 /* 69860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23231 /* 69862 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23232 /* 69864 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23233 /* 69866 */ GIR_RootConstrainSelectedInstOperands,
23234 /* 69867 */ // GIR_Coverage, 360,
23235 /* 69867 */ GIR_EraseRootFromParent_Done,
23236 /* 69868 */ // Label 1096: @69868
23237 /* 69868 */ GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(69905), // Rule ID 361 //
23238 /* 69873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23239 /* 69876 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuloub),
23240 /* 69881 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23241 /* 69884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23242 /* 69887 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23243 /* 69890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23244 /* 69894 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10485:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULOUB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23245 /* 69894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUB),
23246 /* 69897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23247 /* 69899 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23248 /* 69901 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23249 /* 69903 */ GIR_RootConstrainSelectedInstOperands,
23250 /* 69904 */ // GIR_Coverage, 361,
23251 /* 69904 */ GIR_EraseRootFromParent_Done,
23252 /* 69905 */ // Label 1097: @69905
23253 /* 69905 */ GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(69942), // Rule ID 362 //
23254 /* 69910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23255 /* 69913 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulouh),
23256 /* 69918 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23257 /* 69921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23258 /* 69924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23259 /* 69927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23260 /* 69931 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10487:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULOUH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23261 /* 69931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUH),
23262 /* 69934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23263 /* 69936 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23264 /* 69938 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23265 /* 69940 */ GIR_RootConstrainSelectedInstOperands,
23266 /* 69941 */ // GIR_Coverage, 362,
23267 /* 69941 */ GIR_EraseRootFromParent_Done,
23268 /* 69942 */ // Label 1098: @69942
23269 /* 69942 */ GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(69979), // Rule ID 369 //
23270 /* 69947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23271 /* 69950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubcuw),
23272 /* 69955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23273 /* 69958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23274 /* 69961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23275 /* 69964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23276 /* 69968 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10549:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBCUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23277 /* 69968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBCUW),
23278 /* 69971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23279 /* 69973 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23280 /* 69975 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23281 /* 69977 */ GIR_RootConstrainSelectedInstOperands,
23282 /* 69978 */ // GIR_Coverage, 369,
23283 /* 69978 */ GIR_EraseRootFromParent_Done,
23284 /* 69979 */ // Label 1099: @69979
23285 /* 69979 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(70016), // Rule ID 374 //
23286 /* 69984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23287 /* 69987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubsbs),
23288 /* 69992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23289 /* 69995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23290 /* 69998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23291 /* 70001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23292 /* 70005 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10552:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBSBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23293 /* 70005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSBS),
23294 /* 70008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23295 /* 70010 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23296 /* 70012 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23297 /* 70014 */ GIR_RootConstrainSelectedInstOperands,
23298 /* 70015 */ // GIR_Coverage, 374,
23299 /* 70015 */ GIR_EraseRootFromParent_Done,
23300 /* 70016 */ // Label 1100: @70016
23301 /* 70016 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(70053), // Rule ID 375 //
23302 /* 70021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23303 /* 70024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubshs),
23304 /* 70029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23305 /* 70032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23306 /* 70035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23307 /* 70038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23308 /* 70042 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10553:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23309 /* 70042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSHS),
23310 /* 70045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23311 /* 70047 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23312 /* 70049 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23313 /* 70051 */ GIR_RootConstrainSelectedInstOperands,
23314 /* 70052 */ // GIR_Coverage, 375,
23315 /* 70052 */ GIR_EraseRootFromParent_Done,
23316 /* 70053 */ // Label 1101: @70053
23317 /* 70053 */ GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(70090), // Rule ID 376 //
23318 /* 70058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23319 /* 70061 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubsws),
23320 /* 70066 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23321 /* 70069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23322 /* 70072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23323 /* 70075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23324 /* 70079 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10554:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23325 /* 70079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSWS),
23326 /* 70082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23327 /* 70084 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23328 /* 70086 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23329 /* 70088 */ GIR_RootConstrainSelectedInstOperands,
23330 /* 70089 */ // GIR_Coverage, 376,
23331 /* 70089 */ GIR_EraseRootFromParent_Done,
23332 /* 70090 */ // Label 1102: @70090
23333 /* 70090 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(70127), // Rule ID 377 //
23334 /* 70095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23335 /* 70098 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsububs),
23336 /* 70103 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23337 /* 70106 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23338 /* 70109 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23339 /* 70112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23340 /* 70116 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10555:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBUBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23341 /* 70116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUBS),
23342 /* 70119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23343 /* 70121 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23344 /* 70123 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23345 /* 70125 */ GIR_RootConstrainSelectedInstOperands,
23346 /* 70126 */ // GIR_Coverage, 377,
23347 /* 70126 */ GIR_EraseRootFromParent_Done,
23348 /* 70127 */ // Label 1103: @70127
23349 /* 70127 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(70164), // Rule ID 378 //
23350 /* 70132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23351 /* 70135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubuhs),
23352 /* 70140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23353 /* 70143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23354 /* 70146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23355 /* 70149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23356 /* 70153 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10556:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBUHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23357 /* 70153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUHS),
23358 /* 70156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23359 /* 70158 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23360 /* 70160 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23361 /* 70162 */ GIR_RootConstrainSelectedInstOperands,
23362 /* 70163 */ // GIR_Coverage, 378,
23363 /* 70163 */ GIR_EraseRootFromParent_Done,
23364 /* 70164 */ // Label 1104: @70164
23365 /* 70164 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(70201), // Rule ID 379 //
23366 /* 70169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23367 /* 70172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubuws),
23368 /* 70177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23369 /* 70180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23370 /* 70183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23371 /* 70186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23372 /* 70190 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10557:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBUWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23373 /* 70190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUWS),
23374 /* 70193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23375 /* 70195 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23376 /* 70197 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23377 /* 70199 */ GIR_RootConstrainSelectedInstOperands,
23378 /* 70200 */ // GIR_Coverage, 379,
23379 /* 70200 */ GIR_EraseRootFromParent_Done,
23380 /* 70201 */ // Label 1105: @70201
23381 /* 70201 */ GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(70238), // Rule ID 388 //
23382 /* 70206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23383 /* 70209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlb),
23384 /* 70214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23385 /* 70217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23386 /* 70220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23387 /* 70223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23388 /* 70227 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10511:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23389 /* 70227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLB),
23390 /* 70230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23391 /* 70232 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23392 /* 70234 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23393 /* 70236 */ GIR_RootConstrainSelectedInstOperands,
23394 /* 70237 */ // GIR_Coverage, 388,
23395 /* 70237 */ GIR_EraseRootFromParent_Done,
23396 /* 70238 */ // Label 1106: @70238
23397 /* 70238 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(70275), // Rule ID 389 //
23398 /* 70243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23399 /* 70246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlh),
23400 /* 70251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23401 /* 70254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23402 /* 70257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23403 /* 70260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23404 /* 70264 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10515:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VRLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23405 /* 70264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLH),
23406 /* 70267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23407 /* 70269 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23408 /* 70271 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23409 /* 70273 */ GIR_RootConstrainSelectedInstOperands,
23410 /* 70274 */ // GIR_Coverage, 389,
23411 /* 70274 */ GIR_EraseRootFromParent_Done,
23412 /* 70275 */ // Label 1107: @70275
23413 /* 70275 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(70312), // Rule ID 390 //
23414 /* 70280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23415 /* 70283 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlw),
23416 /* 70288 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23417 /* 70291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23418 /* 70294 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23419 /* 70297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23420 /* 70301 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10518:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VRLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23421 /* 70301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLW),
23422 /* 70304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23423 /* 70306 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23424 /* 70308 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23425 /* 70310 */ GIR_RootConstrainSelectedInstOperands,
23426 /* 70311 */ // GIR_Coverage, 390,
23427 /* 70311 */ GIR_EraseRootFromParent_Done,
23428 /* 70312 */ // Label 1108: @70312
23429 /* 70312 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(70349), // Rule ID 391 //
23430 /* 70317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23431 /* 70320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsl),
23432 /* 70325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23433 /* 70328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23434 /* 70331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23435 /* 70334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23436 /* 70338 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10523:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSL:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23437 /* 70338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSL),
23438 /* 70341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23439 /* 70343 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23440 /* 70345 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23441 /* 70347 */ GIR_RootConstrainSelectedInstOperands,
23442 /* 70348 */ // GIR_Coverage, 391,
23443 /* 70348 */ GIR_EraseRootFromParent_Done,
23444 /* 70349 */ // Label 1109: @70349
23445 /* 70349 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(70386), // Rule ID 392 //
23446 /* 70354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23447 /* 70357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslo),
23448 /* 70362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23449 /* 70365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23450 /* 70368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23451 /* 70371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23452 /* 70375 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10527:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSLO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23453 /* 70375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLO),
23454 /* 70378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23455 /* 70380 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23456 /* 70382 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23457 /* 70384 */ GIR_RootConstrainSelectedInstOperands,
23458 /* 70385 */ // GIR_Coverage, 392,
23459 /* 70385 */ GIR_EraseRootFromParent_Done,
23460 /* 70386 */ // Label 1110: @70386
23461 /* 70386 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(70423), // Rule ID 393 //
23462 /* 70391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23463 /* 70394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslb),
23464 /* 70399 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23465 /* 70402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23466 /* 70405 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23467 /* 70408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23468 /* 70412 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10524:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23469 /* 70412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLB),
23470 /* 70415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23471 /* 70417 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23472 /* 70419 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23473 /* 70421 */ GIR_RootConstrainSelectedInstOperands,
23474 /* 70422 */ // GIR_Coverage, 393,
23475 /* 70422 */ GIR_EraseRootFromParent_Done,
23476 /* 70423 */ // Label 1111: @70423
23477 /* 70423 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(70460), // Rule ID 394 //
23478 /* 70428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23479 /* 70431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslh),
23480 /* 70436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23481 /* 70439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23482 /* 70442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23483 /* 70445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23484 /* 70449 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10526:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23485 /* 70449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLH),
23486 /* 70452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23487 /* 70454 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23488 /* 70456 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23489 /* 70458 */ GIR_RootConstrainSelectedInstOperands,
23490 /* 70459 */ // GIR_Coverage, 394,
23491 /* 70459 */ GIR_EraseRootFromParent_Done,
23492 /* 70460 */ // Label 1112: @70460
23493 /* 70460 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(70497), // Rule ID 395 //
23494 /* 70465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23495 /* 70468 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslw),
23496 /* 70473 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23497 /* 70476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23498 /* 70479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23499 /* 70482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23500 /* 70486 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10529:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23501 /* 70486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLW),
23502 /* 70489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23503 /* 70491 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23504 /* 70493 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23505 /* 70495 */ GIR_RootConstrainSelectedInstOperands,
23506 /* 70496 */ // GIR_Coverage, 395,
23507 /* 70496 */ GIR_EraseRootFromParent_Done,
23508 /* 70497 */ // Label 1113: @70497
23509 /* 70497 */ GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(70534), // Rule ID 399 //
23510 /* 70502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23511 /* 70505 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsr),
23512 /* 70510 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23513 /* 70513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23514 /* 70516 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23515 /* 70519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23516 /* 70523 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10530:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23517 /* 70523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSR),
23518 /* 70526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23519 /* 70528 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23520 /* 70530 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23521 /* 70532 */ GIR_RootConstrainSelectedInstOperands,
23522 /* 70533 */ // GIR_Coverage, 399,
23523 /* 70533 */ GIR_EraseRootFromParent_Done,
23524 /* 70534 */ // Label 1114: @70534
23525 /* 70534 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(70571), // Rule ID 400 //
23526 /* 70539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23527 /* 70542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsro),
23528 /* 70547 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23529 /* 70550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23530 /* 70553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23531 /* 70556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23532 /* 70560 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10537:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23533 /* 70560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRO),
23534 /* 70563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23535 /* 70565 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23536 /* 70567 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23537 /* 70569 */ GIR_RootConstrainSelectedInstOperands,
23538 /* 70570 */ // GIR_Coverage, 400,
23539 /* 70570 */ GIR_EraseRootFromParent_Done,
23540 /* 70571 */ // Label 1115: @70571
23541 /* 70571 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(70608), // Rule ID 401 //
23542 /* 70576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23543 /* 70579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrab),
23544 /* 70584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23545 /* 70587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23546 /* 70590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23547 /* 70593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23548 /* 70597 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10531:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRAB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23549 /* 70597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAB),
23550 /* 70600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23551 /* 70602 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23552 /* 70604 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23553 /* 70606 */ GIR_RootConstrainSelectedInstOperands,
23554 /* 70607 */ // GIR_Coverage, 401,
23555 /* 70607 */ GIR_EraseRootFromParent_Done,
23556 /* 70608 */ // Label 1116: @70608
23557 /* 70608 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(70645), // Rule ID 402 //
23558 /* 70613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23559 /* 70616 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrah),
23560 /* 70621 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23561 /* 70624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23562 /* 70627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23563 /* 70630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23564 /* 70634 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10532:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSRAH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23565 /* 70634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAH),
23566 /* 70637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23567 /* 70639 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23568 /* 70641 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23569 /* 70643 */ GIR_RootConstrainSelectedInstOperands,
23570 /* 70644 */ // GIR_Coverage, 402,
23571 /* 70644 */ GIR_EraseRootFromParent_Done,
23572 /* 70645 */ // Label 1117: @70645
23573 /* 70645 */ GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(70682), // Rule ID 403 //
23574 /* 70650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23575 /* 70653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsraw),
23576 /* 70658 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23577 /* 70661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23578 /* 70664 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23579 /* 70667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23580 /* 70671 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10533:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRAW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23581 /* 70671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAW),
23582 /* 70674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23583 /* 70676 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23584 /* 70678 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23585 /* 70680 */ GIR_RootConstrainSelectedInstOperands,
23586 /* 70681 */ // GIR_Coverage, 403,
23587 /* 70681 */ GIR_EraseRootFromParent_Done,
23588 /* 70682 */ // Label 1118: @70682
23589 /* 70682 */ GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(70719), // Rule ID 404 //
23590 /* 70687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23591 /* 70690 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrb),
23592 /* 70695 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23593 /* 70698 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23594 /* 70701 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23595 /* 70704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23596 /* 70708 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10534:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23597 /* 70708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRB),
23598 /* 70711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23599 /* 70713 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23600 /* 70715 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23601 /* 70717 */ GIR_RootConstrainSelectedInstOperands,
23602 /* 70718 */ // GIR_Coverage, 404,
23603 /* 70718 */ GIR_EraseRootFromParent_Done,
23604 /* 70719 */ // Label 1119: @70719
23605 /* 70719 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(70756), // Rule ID 405 //
23606 /* 70724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23607 /* 70727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrh),
23608 /* 70732 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23609 /* 70735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23610 /* 70738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23611 /* 70741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23612 /* 70745 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10536:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSRH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23613 /* 70745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRH),
23614 /* 70748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23615 /* 70750 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23616 /* 70752 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23617 /* 70754 */ GIR_RootConstrainSelectedInstOperands,
23618 /* 70755 */ // GIR_Coverage, 405,
23619 /* 70755 */ GIR_EraseRootFromParent_Done,
23620 /* 70756 */ // Label 1120: @70756
23621 /* 70756 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(70793), // Rule ID 406 //
23622 /* 70761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23623 /* 70764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrw),
23624 /* 70769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23625 /* 70772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23626 /* 70775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23627 /* 70778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23628 /* 70782 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10539:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23629 /* 70782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRW),
23630 /* 70785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23631 /* 70787 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23632 /* 70789 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23633 /* 70791 */ GIR_RootConstrainSelectedInstOperands,
23634 /* 70792 */ // GIR_Coverage, 406,
23635 /* 70792 */ GIR_EraseRootFromParent_Done,
23636 /* 70793 */ // Label 1121: @70793
23637 /* 70793 */ GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(70830), // Rule ID 410 //
23638 /* 70798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
23639 /* 70801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkpx),
23640 /* 70806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23641 /* 70809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23642 /* 70812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23643 /* 70815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23644 /* 70819 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10493:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKPX:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23645 /* 70819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKPX),
23646 /* 70822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23647 /* 70824 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23648 /* 70826 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23649 /* 70828 */ GIR_RootConstrainSelectedInstOperands,
23650 /* 70829 */ // GIR_Coverage, 410,
23651 /* 70829 */ GIR_EraseRootFromParent_Done,
23652 /* 70830 */ // Label 1122: @70830
23653 /* 70830 */ GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(70867), // Rule ID 457 //
23654 /* 70835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23655 /* 70838 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesw),
23656 /* 70843 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23657 /* 70846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23658 /* 70849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23659 /* 70852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23660 /* 70856 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10472:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULESW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23661 /* 70856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESW),
23662 /* 70859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23663 /* 70861 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23664 /* 70863 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23665 /* 70865 */ GIR_RootConstrainSelectedInstOperands,
23666 /* 70866 */ // GIR_Coverage, 457,
23667 /* 70866 */ GIR_EraseRootFromParent_Done,
23668 /* 70867 */ // Label 1123: @70867
23669 /* 70867 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(70904), // Rule ID 458 //
23670 /* 70872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23671 /* 70875 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleuw),
23672 /* 70880 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23673 /* 70883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23674 /* 70886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23675 /* 70889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23676 /* 70893 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10476:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULEUW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23677 /* 70893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUW),
23678 /* 70896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23679 /* 70898 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23680 /* 70900 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23681 /* 70902 */ GIR_RootConstrainSelectedInstOperands,
23682 /* 70903 */ // GIR_Coverage, 458,
23683 /* 70903 */ GIR_EraseRootFromParent_Done,
23684 /* 70904 */ // Label 1124: @70904
23685 /* 70904 */ GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(70941), // Rule ID 459 //
23686 /* 70909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23687 /* 70912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosw),
23688 /* 70917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23689 /* 70920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23690 /* 70923 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23691 /* 70926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23692 /* 70930 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10484:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULOSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23693 /* 70930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSW),
23694 /* 70933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23695 /* 70935 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23696 /* 70937 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23697 /* 70939 */ GIR_RootConstrainSelectedInstOperands,
23698 /* 70940 */ // GIR_Coverage, 459,
23699 /* 70940 */ GIR_EraseRootFromParent_Done,
23700 /* 70941 */ // Label 1125: @70941
23701 /* 70941 */ GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(70978), // Rule ID 460 //
23702 /* 70946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23703 /* 70949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulouw),
23704 /* 70954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23705 /* 70957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23706 /* 70960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23707 /* 70963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23708 /* 70967 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10488:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULOUW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23709 /* 70967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUW),
23710 /* 70970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23711 /* 70972 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23712 /* 70974 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23713 /* 70976 */ GIR_RootConstrainSelectedInstOperands,
23714 /* 70977 */ // GIR_Coverage, 460,
23715 /* 70977 */ GIR_EraseRootFromParent_Done,
23716 /* 70978 */ // Label 1126: @70978
23717 /* 70978 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(71015), // Rule ID 462 //
23718 /* 70983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23719 /* 70986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsd),
23720 /* 70991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23721 /* 70994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23722 /* 70997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23723 /* 71000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23724 /* 71004 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10442:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMAXSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23725 /* 71004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSD),
23726 /* 71007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23727 /* 71009 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23728 /* 71011 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23729 /* 71013 */ GIR_RootConstrainSelectedInstOperands,
23730 /* 71014 */ // GIR_Coverage, 462,
23731 /* 71014 */ GIR_EraseRootFromParent_Done,
23732 /* 71015 */ // Label 1127: @71015
23733 /* 71015 */ GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(71052), // Rule ID 463 //
23734 /* 71020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23735 /* 71023 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxud),
23736 /* 71028 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23737 /* 71031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23738 /* 71034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23739 /* 71037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23740 /* 71041 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10446:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMAXUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23741 /* 71041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUD),
23742 /* 71044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23743 /* 71046 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23744 /* 71048 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23745 /* 71050 */ GIR_RootConstrainSelectedInstOperands,
23746 /* 71051 */ // GIR_Coverage, 463,
23747 /* 71051 */ GIR_EraseRootFromParent_Done,
23748 /* 71052 */ // Label 1128: @71052
23749 /* 71052 */ GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(71089), // Rule ID 464 //
23750 /* 71057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23751 /* 71060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsd),
23752 /* 71065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23753 /* 71068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23754 /* 71071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23755 /* 71074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23756 /* 71078 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10453:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMINSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23757 /* 71078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSD),
23758 /* 71081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23759 /* 71083 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23760 /* 71085 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23761 /* 71087 */ GIR_RootConstrainSelectedInstOperands,
23762 /* 71088 */ // GIR_Coverage, 464,
23763 /* 71088 */ GIR_EraseRootFromParent_Done,
23764 /* 71089 */ // Label 1129: @71089
23765 /* 71089 */ GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(71126), // Rule ID 465 //
23766 /* 71094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23767 /* 71097 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminud),
23768 /* 71102 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23769 /* 71105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23770 /* 71108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23771 /* 71111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23772 /* 71115 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10457:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMINUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23773 /* 71115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUD),
23774 /* 71118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23775 /* 71120 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23776 /* 71122 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23777 /* 71124 */ GIR_RootConstrainSelectedInstOperands,
23778 /* 71125 */ // GIR_Coverage, 465,
23779 /* 71125 */ GIR_EraseRootFromParent_Done,
23780 /* 71126 */ // Label 1130: @71126
23781 /* 71126 */ GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(71163), // Rule ID 468 //
23782 /* 71131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23783 /* 71134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrld),
23784 /* 71139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23785 /* 71142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23786 /* 71145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23787 /* 71148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23788 /* 71152 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10512:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VRLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23789 /* 71152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLD),
23790 /* 71155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23791 /* 71157 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23792 /* 71159 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23793 /* 71161 */ GIR_RootConstrainSelectedInstOperands,
23794 /* 71162 */ // GIR_Coverage, 468,
23795 /* 71162 */ GIR_EraseRootFromParent_Done,
23796 /* 71163 */ // Label 1131: @71163
23797 /* 71163 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(71200), // Rule ID 472 //
23798 /* 71168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23799 /* 71171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddcuq),
23800 /* 71176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
23801 /* 71179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
23802 /* 71182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
23803 /* 71185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23804 /* 71189 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10306:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VADDCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
23805 /* 71189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDCUQ),
23806 /* 71192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23807 /* 71194 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23808 /* 71196 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23809 /* 71198 */ GIR_RootConstrainSelectedInstOperands,
23810 /* 71199 */ // GIR_Coverage, 472,
23811 /* 71199 */ GIR_EraseRootFromParent_Done,
23812 /* 71200 */ // Label 1132: @71200
23813 /* 71200 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(71237), // Rule ID 477 //
23814 /* 71205 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23815 /* 71208 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubcuq),
23816 /* 71213 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
23817 /* 71216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
23818 /* 71219 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
23819 /* 71222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23820 /* 71226 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10548:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VSUBCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
23821 /* 71226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBCUQ),
23822 /* 71229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23823 /* 71231 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23824 /* 71233 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23825 /* 71235 */ GIR_RootConstrainSelectedInstOperands,
23826 /* 71236 */ // GIR_Coverage, 477,
23827 /* 71236 */ GIR_EraseRootFromParent_Done,
23828 /* 71237 */ // Label 1133: @71237
23829 /* 71237 */ GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(71274), // Rule ID 496 //
23830 /* 71242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23831 /* 71245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumb),
23832 /* 71250 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23833 /* 71253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23834 /* 71256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23835 /* 71259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23836 /* 71263 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10271:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VPMSUMB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23837 /* 71263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMB),
23838 /* 71266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23839 /* 71268 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23840 /* 71270 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23841 /* 71272 */ GIR_RootConstrainSelectedInstOperands,
23842 /* 71273 */ // GIR_Coverage, 496,
23843 /* 71273 */ GIR_EraseRootFromParent_Done,
23844 /* 71274 */ // Label 1134: @71274
23845 /* 71274 */ GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(71311), // Rule ID 497 //
23846 /* 71279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23847 /* 71282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumh),
23848 /* 71287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23849 /* 71290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23850 /* 71293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23851 /* 71296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23852 /* 71300 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10273:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPMSUMH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
23853 /* 71300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMH),
23854 /* 71303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23855 /* 71305 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23856 /* 71307 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23857 /* 71309 */ GIR_RootConstrainSelectedInstOperands,
23858 /* 71310 */ // GIR_Coverage, 497,
23859 /* 71310 */ GIR_EraseRootFromParent_Done,
23860 /* 71311 */ // Label 1135: @71311
23861 /* 71311 */ GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(71348), // Rule ID 498 //
23862 /* 71316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23863 /* 71319 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumw),
23864 /* 71324 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23865 /* 71327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23866 /* 71330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23867 /* 71333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23868 /* 71337 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10274:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPMSUMW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23869 /* 71337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMW),
23870 /* 71340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23871 /* 71342 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23872 /* 71344 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23873 /* 71346 */ GIR_RootConstrainSelectedInstOperands,
23874 /* 71347 */ // GIR_Coverage, 498,
23875 /* 71347 */ GIR_EraseRootFromParent_Done,
23876 /* 71348 */ // Label 1136: @71348
23877 /* 71348 */ GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(71385), // Rule ID 499 //
23878 /* 71353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23879 /* 71356 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumd),
23880 /* 71361 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23881 /* 71364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23882 /* 71367 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23883 /* 71370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23884 /* 71374 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10272:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPMSUMD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23885 /* 71374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMD),
23886 /* 71377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23887 /* 71379 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23888 /* 71381 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23889 /* 71383 */ GIR_RootConstrainSelectedInstOperands,
23890 /* 71384 */ // GIR_Coverage, 499,
23891 /* 71384 */ GIR_EraseRootFromParent_Done,
23892 /* 71385 */ // Label 1137: @71385
23893 /* 71385 */ GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(71422), // Rule ID 507 //
23894 /* 71390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
23895 /* 71393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vbpermq),
23896 /* 71398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23897 /* 71401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23898 /* 71404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23899 /* 71407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23900 /* 71411 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10323:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VBPERMQ:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23901 /* 71411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VBPERMQ),
23902 /* 71414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23903 /* 71416 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23904 /* 71418 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23905 /* 71420 */ GIR_RootConstrainSelectedInstOperands,
23906 /* 71421 */ // GIR_Coverage, 507,
23907 /* 71421 */ GIR_EraseRootFromParent_Done,
23908 /* 71422 */ // Label 1138: @71422
23909 /* 71422 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(71459), // Rule ID 510 //
23910 /* 71427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto),
23911 /* 71430 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vcipher),
23912 /* 71435 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23913 /* 71438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23914 /* 71441 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23915 /* 71444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23916 /* 71448 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10265:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCIPHER:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23917 /* 71448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCIPHER),
23918 /* 71451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23919 /* 71453 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23920 /* 71455 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23921 /* 71457 */ GIR_RootConstrainSelectedInstOperands,
23922 /* 71458 */ // GIR_Coverage, 510,
23923 /* 71458 */ GIR_EraseRootFromParent_Done,
23924 /* 71459 */ // Label 1139: @71459
23925 /* 71459 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(71496), // Rule ID 511 //
23926 /* 71464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto),
23927 /* 71467 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vcipherlast),
23928 /* 71472 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23929 /* 71475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23930 /* 71478 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23931 /* 71481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23932 /* 71485 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10266:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCIPHERLAST:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23933 /* 71485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCIPHERLAST),
23934 /* 71488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23935 /* 71490 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23936 /* 71492 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23937 /* 71494 */ GIR_RootConstrainSelectedInstOperands,
23938 /* 71495 */ // GIR_Coverage, 511,
23939 /* 71495 */ GIR_EraseRootFromParent_Done,
23940 /* 71496 */ // Label 1140: @71496
23941 /* 71496 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(71533), // Rule ID 512 //
23942 /* 71501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto),
23943 /* 71504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vncipher),
23944 /* 71509 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23945 /* 71512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23946 /* 71515 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23947 /* 71518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23948 /* 71522 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10267:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VNCIPHER:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23949 /* 71522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNCIPHER),
23950 /* 71525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23951 /* 71527 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23952 /* 71529 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23953 /* 71531 */ GIR_RootConstrainSelectedInstOperands,
23954 /* 71532 */ // GIR_Coverage, 512,
23955 /* 71532 */ GIR_EraseRootFromParent_Done,
23956 /* 71533 */ // Label 1141: @71533
23957 /* 71533 */ GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(71570), // Rule ID 513 //
23958 /* 71538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto),
23959 /* 71541 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vncipherlast),
23960 /* 71546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23961 /* 71549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23962 /* 71552 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23963 /* 71555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23964 /* 71559 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10268:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VNCIPHERLAST:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
23965 /* 71559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNCIPHERLAST),
23966 /* 71562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23967 /* 71564 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23968 /* 71566 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23969 /* 71568 */ GIR_RootConstrainSelectedInstOperands,
23970 /* 71569 */ // GIR_Coverage, 513,
23971 /* 71569 */ GIR_EraseRootFromParent_Done,
23972 /* 71570 */ // Label 1142: @71570
23973 /* 71570 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(71607), // Rule ID 546 //
23974 /* 71575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
23975 /* 71578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vbpermd),
23976 /* 71583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23977 /* 71586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23978 /* 71589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23979 /* 71592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23980 /* 71596 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10322:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VBPERMD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v16i8:{ *:[v16i8] }:$VB)
23981 /* 71596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VBPERMD),
23982 /* 71599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23983 /* 71601 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
23984 /* 71603 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
23985 /* 71605 */ GIR_RootConstrainSelectedInstOperands,
23986 /* 71606 */ // GIR_Coverage, 546,
23987 /* 71606 */ GIR_EraseRootFromParent_Done,
23988 /* 71607 */ // Label 1143: @71607
23989 /* 71607 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(71644), // Rule ID 547 //
23990 /* 71612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
23991 /* 71615 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlwnm),
23992 /* 71620 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23993 /* 71623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23994 /* 71626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23995 /* 71629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
23996 /* 71633 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10520:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VRLWNM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
23997 /* 71633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLWNM),
23998 /* 71636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
23999 /* 71638 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24000 /* 71640 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24001 /* 71642 */ GIR_RootConstrainSelectedInstOperands,
24002 /* 71643 */ // GIR_Coverage, 547,
24003 /* 71643 */ GIR_EraseRootFromParent_Done,
24004 /* 71644 */ // Label 1144: @71644
24005 /* 71644 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(71681), // Rule ID 549 //
24006 /* 71649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
24007 /* 71652 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrldnm),
24008 /* 71657 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24009 /* 71660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24010 /* 71663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24011 /* 71666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24012 /* 71670 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10514:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VRLDNM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24013 /* 71670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLDNM),
24014 /* 71673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24015 /* 71675 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24016 /* 71677 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24017 /* 71679 */ GIR_RootConstrainSelectedInstOperands,
24018 /* 71680 */ // GIR_Coverage, 549,
24019 /* 71680 */ GIR_EraseRootFromParent_Done,
24020 /* 71681 */ // Label 1145: @71681
24021 /* 71681 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(71718), // Rule ID 551 //
24022 /* 71686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
24023 /* 71689 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslv),
24024 /* 71694 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24025 /* 71697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24026 /* 71700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24027 /* 71703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24028 /* 71707 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10528:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSLV:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
24029 /* 71707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLV),
24030 /* 71710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24031 /* 71712 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24032 /* 71714 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24033 /* 71716 */ GIR_RootConstrainSelectedInstOperands,
24034 /* 71717 */ // GIR_Coverage, 551,
24035 /* 71717 */ GIR_EraseRootFromParent_Done,
24036 /* 71718 */ // Label 1146: @71718
24037 /* 71718 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(71755), // Rule ID 552 //
24038 /* 71723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
24039 /* 71726 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrv),
24040 /* 71731 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24041 /* 71734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24042 /* 71737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24043 /* 71740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24044 /* 71744 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10538:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRV:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
24045 /* 71744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRV),
24046 /* 71747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24047 /* 71749 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24048 /* 71751 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24049 /* 71753 */ GIR_RootConstrainSelectedInstOperands,
24050 /* 71754 */ // GIR_Coverage, 552,
24051 /* 71754 */ GIR_EraseRootFromParent_Done,
24052 /* 71755 */ // Label 1147: @71755
24053 /* 71755 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(71792), // Rule ID 557 //
24054 /* 71760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
24055 /* 71763 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsdub),
24056 /* 71768 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24057 /* 71771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24058 /* 71774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24059 /* 71777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24060 /* 71781 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10303:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VABSDUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB)
24061 /* 71781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUB),
24062 /* 71784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24063 /* 71786 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24064 /* 71788 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24065 /* 71790 */ GIR_RootConstrainSelectedInstOperands,
24066 /* 71791 */ // GIR_Coverage, 557,
24067 /* 71791 */ GIR_EraseRootFromParent_Done,
24068 /* 71792 */ // Label 1148: @71792
24069 /* 71792 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(71829), // Rule ID 558 //
24070 /* 71797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
24071 /* 71800 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsduh),
24072 /* 71805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24073 /* 71808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24074 /* 71811 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24075 /* 71814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24076 /* 71818 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10304:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VABSDUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
24077 /* 71818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUH),
24078 /* 71821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24079 /* 71823 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24080 /* 71825 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24081 /* 71827 */ GIR_RootConstrainSelectedInstOperands,
24082 /* 71828 */ // GIR_Coverage, 558,
24083 /* 71828 */ GIR_EraseRootFromParent_Done,
24084 /* 71829 */ // Label 1149: @71829
24085 /* 71829 */ GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(71866), // Rule ID 559 //
24086 /* 71834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
24087 /* 71837 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsduw),
24088 /* 71842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24089 /* 71845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24090 /* 71848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24091 /* 71851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24092 /* 71855 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10305:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VABSDUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
24093 /* 71855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUW),
24094 /* 71858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24095 /* 71860 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24096 /* 71862 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24097 /* 71864 */ GIR_RootConstrainSelectedInstOperands,
24098 /* 71865 */ // GIR_Coverage, 559,
24099 /* 71865 */ GIR_EraseRootFromParent_Done,
24100 /* 71866 */ // Label 1150: @71866
24101 /* 71866 */ GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(71900), // Rule ID 696 //
24102 /* 71871 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addg6sd),
24103 /* 71876 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
24104 /* 71879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24105 /* 71882 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24106 /* 71885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
24107 /* 71889 */ // (intrinsic_wo_chain:{ *:[i64] } 10264:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (ADDG6S8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
24108 /* 71889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDG6S8),
24109 /* 71892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
24110 /* 71894 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
24111 /* 71896 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
24112 /* 71898 */ GIR_RootConstrainSelectedInstOperands,
24113 /* 71899 */ // GIR_Coverage, 696,
24114 /* 71899 */ GIR_EraseRootFromParent_Done,
24115 /* 71900 */ // Label 1151: @71900
24116 /* 71900 */ GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(71937), // Rule ID 1110 //
24117 /* 71905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24118 /* 71908 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpdepd),
24119 /* 71913 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24120 /* 71916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24121 /* 71919 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24122 /* 71922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24123 /* 71926 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10490:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPDEPD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24124 /* 71926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPDEPD),
24125 /* 71929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24126 /* 71931 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24127 /* 71933 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24128 /* 71935 */ GIR_RootConstrainSelectedInstOperands,
24129 /* 71936 */ // GIR_Coverage, 1110,
24130 /* 71936 */ GIR_EraseRootFromParent_Done,
24131 /* 71937 */ // Label 1152: @71937
24132 /* 71937 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(71974), // Rule ID 1111 //
24133 /* 71942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24134 /* 71945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpextd),
24135 /* 71950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24136 /* 71953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24137 /* 71956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24138 /* 71959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24139 /* 71963 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10492:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPEXTD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24140 /* 71963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPEXTD),
24141 /* 71966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24142 /* 71968 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24143 /* 71970 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24144 /* 71972 */ GIR_RootConstrainSelectedInstOperands,
24145 /* 71973 */ // GIR_Coverage, 1111,
24146 /* 71973 */ GIR_EraseRootFromParent_Done,
24147 /* 71974 */ // Label 1153: @71974
24148 /* 71974 */ GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(72011), // Rule ID 1112 //
24149 /* 71979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24150 /* 71982 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_pdepd),
24151 /* 71987 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
24152 /* 71990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24153 /* 71993 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24154 /* 71996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
24155 /* 72000 */ // (intrinsic_wo_chain:{ *:[i64] } 10799:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (PDEPD:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
24156 /* 72000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PDEPD),
24157 /* 72003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
24158 /* 72005 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
24159 /* 72007 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
24160 /* 72009 */ GIR_RootConstrainSelectedInstOperands,
24161 /* 72010 */ // GIR_Coverage, 1112,
24162 /* 72010 */ GIR_EraseRootFromParent_Done,
24163 /* 72011 */ // Label 1154: @72011
24164 /* 72011 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(72048), // Rule ID 1113 //
24165 /* 72016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24166 /* 72019 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_pextd),
24167 /* 72024 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
24168 /* 72027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24169 /* 72030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24170 /* 72033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
24171 /* 72037 */ // (intrinsic_wo_chain:{ *:[i64] } 10800:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (PEXTD:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
24172 /* 72037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PEXTD),
24173 /* 72040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
24174 /* 72042 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
24175 /* 72044 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
24176 /* 72046 */ GIR_RootConstrainSelectedInstOperands,
24177 /* 72047 */ // GIR_Coverage, 1113,
24178 /* 72047 */ GIR_EraseRootFromParent_Done,
24179 /* 72048 */ // Label 1155: @72048
24180 /* 72048 */ GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(72085), // Rule ID 1114 //
24181 /* 72053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24182 /* 72056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfuged),
24183 /* 72061 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24184 /* 72064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24185 /* 72067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24186 /* 72070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24187 /* 72074 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10325:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCFUGED:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24188 /* 72074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUGED),
24189 /* 72077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24190 /* 72079 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24191 /* 72081 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24192 /* 72083 */ GIR_RootConstrainSelectedInstOperands,
24193 /* 72084 */ // GIR_Coverage, 1114,
24194 /* 72084 */ GIR_EraseRootFromParent_Done,
24195 /* 72085 */ // Label 1156: @72085
24196 /* 72085 */ GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(72122), // Rule ID 1116 //
24197 /* 72090 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24198 /* 72093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cfuged),
24199 /* 72098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
24200 /* 72101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24201 /* 72104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24202 /* 72107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
24203 /* 72111 */ // (intrinsic_wo_chain:{ *:[i64] } 10590:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CFUGED:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
24204 /* 72111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CFUGED),
24205 /* 72114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
24206 /* 72116 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
24207 /* 72118 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
24208 /* 72120 */ GIR_RootConstrainSelectedInstOperands,
24209 /* 72121 */ // GIR_Coverage, 1116,
24210 /* 72121 */ GIR_EraseRootFromParent_Done,
24211 /* 72122 */ // Label 1157: @72122
24212 /* 72122 */ GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(72159), // Rule ID 1118 //
24213 /* 72127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24214 /* 72130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclzdm),
24215 /* 72135 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24216 /* 72138 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24217 /* 72141 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24218 /* 72144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24219 /* 72148 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10329:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCLZDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24220 /* 72148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLZDM),
24221 /* 72151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24222 /* 72153 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24223 /* 72155 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24224 /* 72157 */ GIR_RootConstrainSelectedInstOperands,
24225 /* 72158 */ // GIR_Coverage, 1118,
24226 /* 72158 */ GIR_EraseRootFromParent_Done,
24227 /* 72159 */ // Label 1158: @72159
24228 /* 72159 */ GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(72196), // Rule ID 1119 //
24229 /* 72164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24230 /* 72167 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctzdm),
24231 /* 72172 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24232 /* 72175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24233 /* 72178 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24234 /* 72181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24235 /* 72185 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10387:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCTZDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24236 /* 72185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTZDM),
24237 /* 72188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24238 /* 72190 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24239 /* 72192 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24240 /* 72194 */ GIR_RootConstrainSelectedInstOperands,
24241 /* 72195 */ // GIR_Coverage, 1119,
24242 /* 72195 */ GIR_EraseRootFromParent_Done,
24243 /* 72196 */ // Label 1159: @72196
24244 /* 72196 */ GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(72233), // Rule ID 1120 //
24245 /* 72201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24246 /* 72204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cntlzdm),
24247 /* 72209 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
24248 /* 72212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24249 /* 72215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24250 /* 72218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
24251 /* 72222 */ // (intrinsic_wo_chain:{ *:[i64] } 10595:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CNTLZDM:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
24252 /* 72222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CNTLZDM),
24253 /* 72225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
24254 /* 72227 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
24255 /* 72229 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
24256 /* 72231 */ GIR_RootConstrainSelectedInstOperands,
24257 /* 72232 */ // GIR_Coverage, 1120,
24258 /* 72232 */ GIR_EraseRootFromParent_Done,
24259 /* 72233 */ // Label 1160: @72233
24260 /* 72233 */ GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(72270), // Rule ID 1121 //
24261 /* 72238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24262 /* 72241 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cnttzdm),
24263 /* 72246 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
24264 /* 72249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24265 /* 72252 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24266 /* 72255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
24267 /* 72259 */ // (intrinsic_wo_chain:{ *:[i64] } 10596:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CNTTZDM:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB)
24268 /* 72259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CNTTZDM),
24269 /* 72262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
24270 /* 72264 */ GIR_RootToRootCopy, /*OpIdx*/2, // RST
24271 /* 72266 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
24272 /* 72268 */ GIR_RootConstrainSelectedInstOperands,
24273 /* 72269 */ // GIR_Coverage, 1121,
24274 /* 72269 */ GIR_EraseRootFromParent_Done,
24275 /* 72270 */ // Label 1161: @72270
24276 /* 72270 */ GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(72307), // Rule ID 1122 //
24277 /* 72275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24278 /* 72278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclrlb),
24279 /* 72283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24280 /* 72286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24281 /* 72289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24282 /* 72292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24283 /* 72296 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10327:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) => (VCLRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB)
24284 /* 72296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLRLB),
24285 /* 72299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24286 /* 72301 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24287 /* 72303 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24288 /* 72305 */ GIR_RootConstrainSelectedInstOperands,
24289 /* 72306 */ // GIR_Coverage, 1122,
24290 /* 72306 */ GIR_EraseRootFromParent_Done,
24291 /* 72307 */ // Label 1162: @72307
24292 /* 72307 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(72344), // Rule ID 1123 //
24293 /* 72312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24294 /* 72315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclrrb),
24295 /* 72320 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24296 /* 72323 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24297 /* 72326 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24298 /* 72329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24299 /* 72333 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10328:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) => (VCLRRB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB)
24300 /* 72333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLRRB),
24301 /* 72336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24302 /* 72338 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24303 /* 72340 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24304 /* 72342 */ GIR_RootConstrainSelectedInstOperands,
24305 /* 72343 */ // GIR_Coverage, 1123,
24306 /* 72343 */ GIR_EraseRootFromParent_Done,
24307 /* 72344 */ // Label 1163: @72344
24308 /* 72344 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(72381), // Rule ID 1137 //
24309 /* 72349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24310 /* 72352 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesw),
24311 /* 72357 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24312 /* 72360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24313 /* 72363 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24314 /* 72366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24315 /* 72370 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10391:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVESW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
24316 /* 72370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESW),
24317 /* 72373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24318 /* 72375 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24319 /* 72377 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24320 /* 72379 */ GIR_RootConstrainSelectedInstOperands,
24321 /* 72380 */ // GIR_Coverage, 1137,
24322 /* 72380 */ GIR_EraseRootFromParent_Done,
24323 /* 72381 */ // Label 1164: @72381
24324 /* 72381 */ GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(72418), // Rule ID 1138 //
24325 /* 72386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24326 /* 72389 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveuw),
24327 /* 72394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24328 /* 72397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24329 /* 72400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24330 /* 72403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24331 /* 72407 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10394:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVEUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
24332 /* 72407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUW),
24333 /* 72410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24334 /* 72412 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24335 /* 72414 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24336 /* 72416 */ GIR_RootConstrainSelectedInstOperands,
24337 /* 72417 */ // GIR_Coverage, 1138,
24338 /* 72417 */ GIR_EraseRootFromParent_Done,
24339 /* 72418 */ // Label 1165: @72418
24340 /* 72418 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(72455), // Rule ID 1139 //
24341 /* 72423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24342 /* 72426 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesd),
24343 /* 72431 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24344 /* 72434 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24345 /* 72437 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24346 /* 72440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24347 /* 72444 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10389:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVESD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24348 /* 72444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESD),
24349 /* 72447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24350 /* 72449 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24351 /* 72451 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24352 /* 72453 */ GIR_RootConstrainSelectedInstOperands,
24353 /* 72454 */ // GIR_Coverage, 1139,
24354 /* 72454 */ GIR_EraseRootFromParent_Done,
24355 /* 72455 */ // Label 1166: @72455
24356 /* 72455 */ GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(72492), // Rule ID 1140 //
24357 /* 72460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24358 /* 72463 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveud),
24359 /* 72468 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24360 /* 72471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24361 /* 72474 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24362 /* 72477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24363 /* 72481 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10392:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVEUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24364 /* 72481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUD),
24365 /* 72484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24366 /* 72486 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24367 /* 72488 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24368 /* 72490 */ GIR_RootConstrainSelectedInstOperands,
24369 /* 72491 */ // GIR_Coverage, 1140,
24370 /* 72491 */ GIR_EraseRootFromParent_Done,
24371 /* 72492 */ // Label 1167: @72492
24372 /* 72492 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(72529), // Rule ID 1143 //
24373 /* 72497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24374 /* 72500 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesd),
24375 /* 72505 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
24376 /* 72508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24377 /* 72511 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24378 /* 72514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24379 /* 72518 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10470:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULESD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24380 /* 72518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESD),
24381 /* 72521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24382 /* 72523 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24383 /* 72525 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24384 /* 72527 */ GIR_RootConstrainSelectedInstOperands,
24385 /* 72528 */ // GIR_Coverage, 1143,
24386 /* 72528 */ GIR_EraseRootFromParent_Done,
24387 /* 72529 */ // Label 1168: @72529
24388 /* 72529 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(72566), // Rule ID 1144 //
24389 /* 72534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24390 /* 72537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleud),
24391 /* 72542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
24392 /* 72545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24393 /* 72548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24394 /* 72551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24395 /* 72555 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10474:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULEUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24396 /* 72555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUD),
24397 /* 72558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24398 /* 72560 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24399 /* 72562 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24400 /* 72564 */ GIR_RootConstrainSelectedInstOperands,
24401 /* 72565 */ // GIR_Coverage, 1144,
24402 /* 72565 */ GIR_EraseRootFromParent_Done,
24403 /* 72566 */ // Label 1169: @72566
24404 /* 72566 */ GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(72603), // Rule ID 1145 //
24405 /* 72571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24406 /* 72574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosd),
24407 /* 72579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
24408 /* 72582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24409 /* 72585 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24410 /* 72588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24411 /* 72592 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10482:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULOSD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24412 /* 72592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSD),
24413 /* 72595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24414 /* 72597 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24415 /* 72599 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24416 /* 72601 */ GIR_RootConstrainSelectedInstOperands,
24417 /* 72602 */ // GIR_Coverage, 1145,
24418 /* 72602 */ GIR_EraseRootFromParent_Done,
24419 /* 72603 */ // Label 1170: @72603
24420 /* 72603 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(72640), // Rule ID 1146 //
24421 /* 72608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24422 /* 72611 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuloud),
24423 /* 72616 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
24424 /* 72619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24425 /* 72622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24426 /* 72625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24427 /* 72629 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10486:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULOUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
24428 /* 72629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUD),
24429 /* 72632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24430 /* 72634 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24431 /* 72636 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24432 /* 72638 */ GIR_RootConstrainSelectedInstOperands,
24433 /* 72639 */ // GIR_Coverage, 1146,
24434 /* 72639 */ GIR_EraseRootFromParent_Done,
24435 /* 72640 */ // Label 1171: @72640
24436 /* 72640 */ GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(72677), // Rule ID 1150 //
24437 /* 72645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24438 /* 72648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesq),
24439 /* 72653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
24440 /* 72656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
24441 /* 72659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
24442 /* 72662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24443 /* 72666 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10390:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVESQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
24444 /* 72666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESQ),
24445 /* 72669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24446 /* 72671 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24447 /* 72673 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24448 /* 72675 */ GIR_RootConstrainSelectedInstOperands,
24449 /* 72676 */ // GIR_Coverage, 1150,
24450 /* 72676 */ GIR_EraseRootFromParent_Done,
24451 /* 72677 */ // Label 1172: @72677
24452 /* 72677 */ GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(72714), // Rule ID 1151 //
24453 /* 72682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24454 /* 72685 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveuq),
24455 /* 72690 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
24456 /* 72693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
24457 /* 72696 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
24458 /* 72699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24459 /* 72703 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10393:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVEUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
24460 /* 72703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUQ),
24461 /* 72706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24462 /* 72708 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24463 /* 72710 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24464 /* 72712 */ GIR_RootConstrainSelectedInstOperands,
24465 /* 72713 */ // GIR_Coverage, 1151,
24466 /* 72713 */ GIR_EraseRootFromParent_Done,
24467 /* 72714 */ // Label 1173: @72714
24468 /* 72714 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(72751), // Rule ID 1161 //
24469 /* 72719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24470 /* 72722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlqnm),
24471 /* 72727 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
24472 /* 72730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
24473 /* 72733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
24474 /* 72736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24475 /* 72740 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10517:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VRLQNM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB)
24476 /* 72740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLQNM),
24477 /* 72743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24478 /* 72745 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
24479 /* 72747 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
24480 /* 72749 */ GIR_RootConstrainSelectedInstOperands,
24481 /* 72750 */ // GIR_Coverage, 1161,
24482 /* 72750 */ GIR_EraseRootFromParent_Done,
24483 /* 72751 */ // Label 1174: @72751
24484 /* 72751 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(72788), // Rule ID 1166 //
24485 /* 72756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture),
24486 /* 72759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxor),
24487 /* 72764 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
24488 /* 72767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
24489 /* 72770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v1024s1,
24490 /* 72773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
24491 /* 72777 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10691:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v1024i1:{ *:[v1024i1] }:$AB) => (DMXOR:{ *:[v1024i1] } v1024i1:{ *:[v1024i1] }:$ATi, v1024i1:{ *:[v1024i1] }:$AB)
24492 /* 72777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXOR),
24493 /* 72780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24494 /* 72782 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
24495 /* 72784 */ GIR_RootToRootCopy, /*OpIdx*/3, // AB
24496 /* 72786 */ GIR_RootConstrainSelectedInstOperands,
24497 /* 72787 */ // GIR_Coverage, 1166,
24498 /* 72787 */ GIR_EraseRootFromParent_Done,
24499 /* 72788 */ // Label 1175: @72788
24500 /* 72788 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(72845), // Rule ID 2911 //
24501 /* 72793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_PairedVectorMemops),
24502 /* 72796 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_assemble_pair),
24503 /* 72801 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v256s1,
24504 /* 72804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24505 /* 72807 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24506 /* 72810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRpRCRegClassID),
24507 /* 72814 */ // (intrinsic_wo_chain:{ *:[v256i1] } 10848:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vs1, v16i8:{ *:[v16i8] }:$vs0) => (REG_SEQUENCE:{ *:[v256i1] } VSRpRC:{ *:[i32] }, ?:{ *:[v16i8] }:$vs0, sub_vsx1:{ *:[i32] }, ?:{ *:[v16i8] }:$vs1, sub_vsx0:{ *:[i32] })
24508 /* 72814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
24509 /* 72817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24510 /* 72819 */ GIR_RootToRootCopy, /*OpIdx*/3, // vs0
24511 /* 72821 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/22,
24512 /* 72824 */ GIR_RootToRootCopy, /*OpIdx*/2, // vs1
24513 /* 72826 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/21,
24514 /* 72829 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRpRCRegClassID),
24515 /* 72834 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::VSRCRegClassID),
24516 /* 72839 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(PPC::VSRCRegClassID),
24517 /* 72844 */ // GIR_Coverage, 2911,
24518 /* 72844 */ GIR_EraseRootFromParent_Done,
24519 /* 72845 */ // Label 1176: @72845
24520 /* 72845 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(72882), // Rule ID 3346 //
24521 /* 72850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24522 /* 72853 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhsw),
24523 /* 72858 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24524 /* 72861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24525 /* 72864 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24526 /* 72867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24527 /* 72871 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10478:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULHSW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
24528 /* 72871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHSW),
24529 /* 72874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24530 /* 72876 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
24531 /* 72878 */ GIR_RootToRootCopy, /*OpIdx*/3, // vB
24532 /* 72880 */ GIR_RootConstrainSelectedInstOperands,
24533 /* 72881 */ // GIR_Coverage, 3346,
24534 /* 72881 */ GIR_EraseRootFromParent_Done,
24535 /* 72882 */ // Label 1177: @72882
24536 /* 72882 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(72919), // Rule ID 3347 //
24537 /* 72887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24538 /* 72890 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhuw),
24539 /* 72895 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24540 /* 72898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24541 /* 72901 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24542 /* 72904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24543 /* 72908 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10480:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULHUW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
24544 /* 72908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHUW),
24545 /* 72911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24546 /* 72913 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
24547 /* 72915 */ GIR_RootToRootCopy, /*OpIdx*/3, // vB
24548 /* 72917 */ GIR_RootConstrainSelectedInstOperands,
24549 /* 72918 */ // GIR_Coverage, 3347,
24550 /* 72918 */ GIR_EraseRootFromParent_Done,
24551 /* 72919 */ // Label 1178: @72919
24552 /* 72919 */ GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(72956), // Rule ID 3348 //
24553 /* 72924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24554 /* 72927 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhsd),
24555 /* 72932 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24556 /* 72935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24557 /* 72938 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24558 /* 72941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24559 /* 72945 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10477:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULHSD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB)
24560 /* 72945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHSD),
24561 /* 72948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24562 /* 72950 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
24563 /* 72952 */ GIR_RootToRootCopy, /*OpIdx*/3, // vB
24564 /* 72954 */ GIR_RootConstrainSelectedInstOperands,
24565 /* 72955 */ // GIR_Coverage, 3348,
24566 /* 72955 */ GIR_EraseRootFromParent_Done,
24567 /* 72956 */ // Label 1179: @72956
24568 /* 72956 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(72993), // Rule ID 3349 //
24569 /* 72961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
24570 /* 72964 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhud),
24571 /* 72969 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
24572 /* 72972 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24573 /* 72975 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24574 /* 72978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
24575 /* 72982 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10479:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULHUD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB)
24576 /* 72982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHUD),
24577 /* 72985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
24578 /* 72987 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
24579 /* 72989 */ GIR_RootToRootCopy, /*OpIdx*/3, // vB
24580 /* 72991 */ GIR_RootConstrainSelectedInstOperands,
24581 /* 72992 */ // GIR_Coverage, 3349,
24582 /* 72992 */ GIR_EraseRootFromParent_Done,
24583 /* 72993 */ // Label 1180: @72993
24584 /* 72993 */ GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(73052), // Rule ID 3516 //
24585 /* 72998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24586 /* 73001 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvi8gerx4),
24587 /* 73006 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
24588 /* 73009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
24589 /* 73012 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24590 /* 73015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
24591 /* 73019 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10702:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVI8GERX4:{ *:[v1024i1] } ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24592 /* 73019 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24593 /* 73022 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24594 /* 73026 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24595 /* 73031 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
24596 /* 73035 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24597 /* 73040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVI8GERX4),
24598 /* 73043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24599 /* 73045 */ GIR_RootToRootCopy, /*OpIdx*/2, // XAp
24600 /* 73047 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24601 /* 73050 */ GIR_RootConstrainSelectedInstOperands,
24602 /* 73051 */ // GIR_Coverage, 3516,
24603 /* 73051 */ GIR_EraseRootFromParent_Done,
24604 /* 73052 */ // Label 1181: @73052
24605 /* 73052 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(73111), // Rule ID 3519 //
24606 /* 73057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24607 /* 73060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvbf16gerx2),
24608 /* 73065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
24609 /* 73068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
24610 /* 73071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24611 /* 73074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
24612 /* 73078 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10692:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVBF16GERX2:{ *:[v1024i1] } ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24613 /* 73078 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24614 /* 73081 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24615 /* 73085 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24616 /* 73090 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
24617 /* 73094 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24618 /* 73099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVBF16GERX2),
24619 /* 73102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24620 /* 73104 */ GIR_RootToRootCopy, /*OpIdx*/2, // XAp
24621 /* 73106 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24622 /* 73109 */ GIR_RootConstrainSelectedInstOperands,
24623 /* 73110 */ // GIR_Coverage, 3519,
24624 /* 73110 */ GIR_EraseRootFromParent_Done,
24625 /* 73111 */ // Label 1182: @73111
24626 /* 73111 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(73170), // Rule ID 3524 //
24627 /* 73116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24628 /* 73119 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvf16gerx2),
24629 /* 73124 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
24630 /* 73127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
24631 /* 73130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24632 /* 73133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
24633 /* 73137 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10697:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVF16GERX2:{ *:[v1024i1] } ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24634 /* 73137 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24635 /* 73140 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24636 /* 73144 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24637 /* 73149 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
24638 /* 73153 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24639 /* 73158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVF16GERX2),
24640 /* 73161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24641 /* 73163 */ GIR_RootToRootCopy, /*OpIdx*/2, // XAp
24642 /* 73165 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24643 /* 73168 */ GIR_RootConstrainSelectedInstOperands,
24644 /* 73169 */ // GIR_Coverage, 3524,
24645 /* 73169 */ GIR_EraseRootFromParent_Done,
24646 /* 73170 */ // Label 1183: @73170
24647 /* 73170 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(73251), // Rule ID 3543 //
24648 /* 73175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
24649 /* 73178 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8),
24650 /* 73183 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24651 /* 73186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24652 /* 73189 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24653 /* 73192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
24654 /* 73196 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10776:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24655 /* 73196 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24656 /* 73199 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24657 /* 73203 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24658 /* 73208 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24659 /* 73212 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24660 /* 73217 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24661 /* 73220 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24662 /* 73224 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24663 /* 73229 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24664 /* 73233 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24665 /* 73238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8),
24666 /* 73241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24667 /* 73243 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24668 /* 73246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24669 /* 73249 */ GIR_RootConstrainSelectedInstOperands,
24670 /* 73250 */ // GIR_Coverage, 3543,
24671 /* 73250 */ GIR_EraseRootFromParent_Done,
24672 /* 73251 */ // Label 1184: @73251
24673 /* 73251 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(73332), // Rule ID 3545 //
24674 /* 73256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
24675 /* 73259 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4),
24676 /* 73264 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24677 /* 73267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24678 /* 73270 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24679 /* 73273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
24680 /* 73277 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10778:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24681 /* 73277 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24682 /* 73280 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24683 /* 73284 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24684 /* 73289 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24685 /* 73293 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24686 /* 73298 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24687 /* 73301 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24688 /* 73305 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24689 /* 73310 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24690 /* 73314 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24691 /* 73319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4),
24692 /* 73322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24693 /* 73324 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24694 /* 73327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24695 /* 73330 */ GIR_RootConstrainSelectedInstOperands,
24696 /* 73331 */ // GIR_Coverage, 3545,
24697 /* 73331 */ GIR_EraseRootFromParent_Done,
24698 /* 73332 */ // Label 1185: @73332
24699 /* 73332 */ GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(73413), // Rule ID 3547 //
24700 /* 73337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
24701 /* 73340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2s),
24702 /* 73345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24703 /* 73348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24704 /* 73351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24705 /* 73354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
24706 /* 73358 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10774:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2S:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24707 /* 73358 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24708 /* 73361 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24709 /* 73365 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24710 /* 73370 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24711 /* 73374 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24712 /* 73379 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24713 /* 73382 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24714 /* 73386 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24715 /* 73391 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24716 /* 73395 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24717 /* 73400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2S),
24718 /* 73403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24719 /* 73405 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24720 /* 73408 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24721 /* 73411 */ GIR_RootConstrainSelectedInstOperands,
24722 /* 73412 */ // GIR_Coverage, 3547,
24723 /* 73412 */ GIR_EraseRootFromParent_Done,
24724 /* 73413 */ // Label 1186: @73413
24725 /* 73413 */ GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(73494), // Rule ID 3549 //
24726 /* 73418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24727 /* 73421 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8),
24728 /* 73426 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24729 /* 73429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24730 /* 73432 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24731 /* 73435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
24732 /* 73439 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10776:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24733 /* 73439 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24734 /* 73442 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24735 /* 73446 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24736 /* 73451 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24737 /* 73455 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24738 /* 73460 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24739 /* 73463 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24740 /* 73467 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24741 /* 73472 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24742 /* 73476 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24743 /* 73481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8W),
24744 /* 73484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24745 /* 73486 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24746 /* 73489 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24747 /* 73492 */ GIR_RootConstrainSelectedInstOperands,
24748 /* 73493 */ // GIR_Coverage, 3549,
24749 /* 73493 */ GIR_EraseRootFromParent_Done,
24750 /* 73494 */ // Label 1187: @73494
24751 /* 73494 */ GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(73575), // Rule ID 3551 //
24752 /* 73499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24753 /* 73502 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4),
24754 /* 73507 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24755 /* 73510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24756 /* 73513 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24757 /* 73516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
24758 /* 73520 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10778:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24759 /* 73520 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24760 /* 73523 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24761 /* 73527 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24762 /* 73532 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24763 /* 73536 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24764 /* 73541 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24765 /* 73544 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24766 /* 73548 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24767 /* 73553 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24768 /* 73557 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24769 /* 73562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4W),
24770 /* 73565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24771 /* 73567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24772 /* 73570 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24773 /* 73573 */ GIR_RootConstrainSelectedInstOperands,
24774 /* 73574 */ // GIR_Coverage, 3551,
24775 /* 73574 */ GIR_EraseRootFromParent_Done,
24776 /* 73575 */ // Label 1188: @73575
24777 /* 73575 */ GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(73656), // Rule ID 3553 //
24778 /* 73580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24779 /* 73583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2s),
24780 /* 73588 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24781 /* 73591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24782 /* 73594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24783 /* 73597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
24784 /* 73601 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10774:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24785 /* 73601 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24786 /* 73604 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24787 /* 73608 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24788 /* 73613 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24789 /* 73617 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24790 /* 73622 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24791 /* 73625 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24792 /* 73629 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24793 /* 73634 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24794 /* 73638 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24795 /* 73643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SW),
24796 /* 73646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24797 /* 73648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24798 /* 73651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24799 /* 73654 */ GIR_RootConstrainSelectedInstOperands,
24800 /* 73655 */ // GIR_Coverage, 3553,
24801 /* 73655 */ GIR_EraseRootFromParent_Done,
24802 /* 73656 */ // Label 1189: @73656
24803 /* 73656 */ GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(73737), // Rule ID 3555 //
24804 /* 73661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
24805 /* 73664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2),
24806 /* 73669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24807 /* 73672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24808 /* 73675 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24809 /* 73678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
24810 /* 73682 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10757:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24811 /* 73682 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24812 /* 73685 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24813 /* 73689 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24814 /* 73694 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24815 /* 73698 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24816 /* 73703 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24817 /* 73706 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24818 /* 73710 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24819 /* 73715 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24820 /* 73719 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24821 /* 73724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2),
24822 /* 73727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24823 /* 73729 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24824 /* 73732 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24825 /* 73735 */ GIR_RootConstrainSelectedInstOperands,
24826 /* 73736 */ // GIR_Coverage, 3555,
24827 /* 73736 */ GIR_EraseRootFromParent_Done,
24828 /* 73737 */ // Label 1190: @73737
24829 /* 73737 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(73818), // Rule ID 3560 //
24830 /* 73742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24831 /* 73745 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2),
24832 /* 73750 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24833 /* 73753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24834 /* 73756 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24835 /* 73759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
24836 /* 73763 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10757:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24837 /* 73763 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24838 /* 73766 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24839 /* 73770 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24840 /* 73775 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24841 /* 73779 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24842 /* 73784 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24843 /* 73787 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24844 /* 73791 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24845 /* 73796 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24846 /* 73800 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24847 /* 73805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2W),
24848 /* 73808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24849 /* 73810 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24850 /* 73813 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24851 /* 73816 */ GIR_RootConstrainSelectedInstOperands,
24852 /* 73817 */ // GIR_Coverage, 3560,
24853 /* 73817 */ GIR_EraseRootFromParent_Done,
24854 /* 73818 */ // Label 1191: @73818
24855 /* 73818 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(73899), // Rule ID 3565 //
24856 /* 73823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
24857 /* 73826 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32ger),
24858 /* 73831 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24859 /* 73834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24860 /* 73837 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24861 /* 73840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
24862 /* 73844 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10762:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GER:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24863 /* 73844 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24864 /* 73847 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24865 /* 73851 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24866 /* 73856 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24867 /* 73860 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24868 /* 73865 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24869 /* 73868 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24870 /* 73872 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24871 /* 73877 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24872 /* 73881 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24873 /* 73886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GER),
24874 /* 73889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24875 /* 73891 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24876 /* 73894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24877 /* 73897 */ GIR_RootConstrainSelectedInstOperands,
24878 /* 73898 */ // GIR_Coverage, 3565,
24879 /* 73898 */ GIR_EraseRootFromParent_Done,
24880 /* 73899 */ // Label 1192: @73899
24881 /* 73899 */ GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(73958), // Rule ID 3570 //
24882 /* 73904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
24883 /* 73907 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64ger),
24884 /* 73912 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24885 /* 73915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
24886 /* 73918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24887 /* 73921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
24888 /* 73925 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10767:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GER:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24889 /* 73925 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24890 /* 73928 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24891 /* 73932 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24892 /* 73937 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
24893 /* 73941 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24894 /* 73946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GER),
24895 /* 73949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24896 /* 73951 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
24897 /* 73953 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24898 /* 73956 */ GIR_RootConstrainSelectedInstOperands,
24899 /* 73957 */ // GIR_Coverage, 3570,
24900 /* 73957 */ GIR_EraseRootFromParent_Done,
24901 /* 73958 */ // Label 1193: @73958
24902 /* 73958 */ GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(74039), // Rule ID 3575 //
24903 /* 73963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
24904 /* 73966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2),
24905 /* 73971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24906 /* 73974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24907 /* 73977 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24908 /* 73980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
24909 /* 73984 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10752:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24910 /* 73984 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24911 /* 73987 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24912 /* 73991 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24913 /* 73996 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24914 /* 74000 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24915 /* 74005 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24916 /* 74008 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24917 /* 74012 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24918 /* 74017 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24919 /* 74021 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24920 /* 74026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2),
24921 /* 74029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24922 /* 74031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24923 /* 74034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24924 /* 74037 */ GIR_RootConstrainSelectedInstOperands,
24925 /* 74038 */ // GIR_Coverage, 3575,
24926 /* 74038 */ GIR_EraseRootFromParent_Done,
24927 /* 74039 */ // Label 1194: @74039
24928 /* 74039 */ GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(74120), // Rule ID 3580 //
24929 /* 74044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
24930 /* 74047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2),
24931 /* 74052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24932 /* 74055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24933 /* 74058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24934 /* 74061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
24935 /* 74065 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10772:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24936 /* 74065 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24937 /* 74068 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24938 /* 74072 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24939 /* 74077 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24940 /* 74081 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24941 /* 74086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24942 /* 74089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24943 /* 74093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24944 /* 74098 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24945 /* 74102 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24946 /* 74107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2),
24947 /* 74110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24948 /* 74112 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24949 /* 74115 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24950 /* 74118 */ GIR_RootConstrainSelectedInstOperands,
24951 /* 74119 */ // GIR_Coverage, 3580,
24952 /* 74119 */ GIR_EraseRootFromParent_Done,
24953 /* 74120 */ // Label 1195: @74120
24954 /* 74120 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(74201), // Rule ID 3583 //
24955 /* 74125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24956 /* 74128 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32ger),
24957 /* 74133 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24958 /* 74136 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24959 /* 74139 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24960 /* 74142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
24961 /* 74146 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10762:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24962 /* 74146 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
24963 /* 74149 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24964 /* 74153 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24965 /* 74158 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
24966 /* 74162 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24967 /* 74167 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24968 /* 74170 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24969 /* 74174 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24970 /* 74179 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
24971 /* 74183 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24972 /* 74188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERW),
24973 /* 74191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24974 /* 74193 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24975 /* 74196 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24976 /* 74199 */ GIR_RootConstrainSelectedInstOperands,
24977 /* 74200 */ // GIR_Coverage, 3583,
24978 /* 74200 */ GIR_EraseRootFromParent_Done,
24979 /* 74201 */ // Label 1196: @74201
24980 /* 74201 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(74260), // Rule ID 3588 //
24981 /* 74206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
24982 /* 74209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64ger),
24983 /* 74214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
24984 /* 74217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
24985 /* 74220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24986 /* 74223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
24987 /* 74227 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10767:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERW:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
24988 /* 74227 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24989 /* 74230 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24990 /* 74234 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24991 /* 74239 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
24992 /* 74243 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
24993 /* 74248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERW),
24994 /* 74251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
24995 /* 74253 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
24996 /* 74255 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24997 /* 74258 */ GIR_RootConstrainSelectedInstOperands,
24998 /* 74259 */ // GIR_Coverage, 3588,
24999 /* 74259 */ GIR_EraseRootFromParent_Done,
25000 /* 74260 */ // Label 1197: @74260
25001 /* 74260 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(74341), // Rule ID 3593 //
25002 /* 74265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
25003 /* 74268 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2),
25004 /* 74273 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
25005 /* 74276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25006 /* 74279 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25007 /* 74282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
25008 /* 74286 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10752:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
25009 /* 74286 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
25010 /* 74289 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25011 /* 74293 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25012 /* 74298 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
25013 /* 74302 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
25014 /* 74307 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25015 /* 74310 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25016 /* 74314 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25017 /* 74319 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
25018 /* 74323 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
25019 /* 74328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2W),
25020 /* 74331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
25021 /* 74333 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25022 /* 74336 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
25023 /* 74339 */ GIR_RootConstrainSelectedInstOperands,
25024 /* 74340 */ // GIR_Coverage, 3593,
25025 /* 74340 */ GIR_EraseRootFromParent_Done,
25026 /* 74341 */ // Label 1198: @74341
25027 /* 74341 */ GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(74422), // Rule ID 3598 //
25028 /* 74346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
25029 /* 74349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2),
25030 /* 74354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
25031 /* 74357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25032 /* 74360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25033 /* 74363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
25034 /* 74367 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10772:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
25035 /* 74367 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
25036 /* 74370 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25037 /* 74374 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25038 /* 74379 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
25039 /* 74383 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
25040 /* 74388 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25041 /* 74391 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25042 /* 74395 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25043 /* 74400 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
25044 /* 74404 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
25045 /* 74409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2W),
25046 /* 74412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
25047 /* 74414 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25048 /* 74417 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
25049 /* 74420 */ GIR_RootConstrainSelectedInstOperands,
25050 /* 74421 */ // GIR_Coverage, 3598,
25051 /* 74421 */ GIR_EraseRootFromParent_Done,
25052 /* 74422 */ // Label 1199: @74422
25053 /* 74422 */ GIM_Reject,
25054 /* 74423 */ // Label 998: @74423
25055 /* 74423 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(81793),
25056 /* 74428 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
25057 /* 74431 */ GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(74489), // Rule ID 1011 //
25058 /* 74436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
25059 /* 74439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd),
25060 /* 74444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
25061 /* 74447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
25062 /* 74450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
25063 /* 74453 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
25064 /* 74456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25065 /* 74460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25066 /* 74464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
25067 /* 74468 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128,
25068 /* 74472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25069 /* 74474 */ // (intrinsic_wo_chain:{ *:[f128] } 10640:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi)) => (XSMSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
25070 /* 74474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBQPO),
25071 /* 74477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
25072 /* 74479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RSTi
25073 /* 74483 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25074 /* 74485 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25075 /* 74487 */ GIR_RootConstrainSelectedInstOperands,
25076 /* 74488 */ // GIR_Coverage, 1011,
25077 /* 74488 */ GIR_EraseRootFromParent_Done,
25078 /* 74489 */ // Label 1201: @74489
25079 /* 74489 */ GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(74542), // Rule ID 2173 //
25080 /* 74494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
25081 /* 74497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxinsertw),
25082 /* 74502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25083 /* 74505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25084 /* 74508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
25085 /* 74511 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25086 /* 74514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
25087 /* 74518 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25088 /* 74522 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25089 /* 74526 */ // MIs[1] Operand 1
25090 /* 74526 */ // No operand predicates
25091 /* 74526 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25092 /* 74528 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10927:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v2i64:{ *:[v2i64] }:$B, (imm:{ *:[i32] }):$IMM) => (XXINSERTW:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v2i64] }:$B, (imm:{ *:[i32] }):$IMM)
25093 /* 74528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXINSERTW),
25094 /* 74531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
25095 /* 74533 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
25096 /* 74535 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
25097 /* 74537 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // IMM
25098 /* 74540 */ GIR_RootConstrainSelectedInstOperands,
25099 /* 74541 */ // GIR_Coverage, 2173,
25100 /* 74541 */ GIR_EraseRootFromParent_Done,
25101 /* 74542 */ // Label 1202: @74542
25102 /* 74542 */ GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(74584), // Rule ID 1010 //
25103 /* 74547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
25104 /* 74550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd),
25105 /* 74555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
25106 /* 74558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
25107 /* 74561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
25108 /* 74564 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
25109 /* 74567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25110 /* 74571 */ // (intrinsic_wo_chain:{ *:[f128] } 10640:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi) => (XSMADDQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
25111 /* 74571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDQPO),
25112 /* 74574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
25113 /* 74576 */ GIR_RootToRootCopy, /*OpIdx*/4, // RSTi
25114 /* 74578 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25115 /* 74580 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25116 /* 74582 */ GIR_RootConstrainSelectedInstOperands,
25117 /* 74583 */ // GIR_Coverage, 1010,
25118 /* 74583 */ GIR_EraseRootFromParent_Done,
25119 /* 74584 */ // Label 1203: @74584
25120 /* 74584 */ GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(74626), // Rule ID 1752 //
25121 /* 74589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
25122 /* 74592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsub),
25123 /* 74597 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
25124 /* 74600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25125 /* 74603 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25126 /* 74606 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
25127 /* 74609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
25128 /* 74613 */ // (intrinsic_wo_chain:{ *:[f64] } 10641:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (XSMSUBMDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C)
25129 /* 74613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBMDP),
25130 /* 74616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
25131 /* 74618 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
25132 /* 74620 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
25133 /* 74622 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
25134 /* 74624 */ GIR_RootConstrainSelectedInstOperands,
25135 /* 74625 */ // GIR_Coverage, 1752,
25136 /* 74625 */ GIR_EraseRootFromParent_Done,
25137 /* 74626 */ // Label 1204: @74626
25138 /* 74626 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(74668), // Rule ID 1753 //
25139 /* 74631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
25140 /* 74634 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadd),
25141 /* 74639 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
25142 /* 74642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25143 /* 74645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25144 /* 74648 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
25145 /* 74651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
25146 /* 74655 */ // (intrinsic_wo_chain:{ *:[f64] } 10645:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (XSNMADDMDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C)
25147 /* 74655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDMDP),
25148 /* 74658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
25149 /* 74660 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
25150 /* 74662 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
25151 /* 74664 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
25152 /* 74666 */ GIR_RootConstrainSelectedInstOperands,
25153 /* 74667 */ // GIR_Coverage, 1753,
25154 /* 74667 */ GIR_EraseRootFromParent_Done,
25155 /* 74668 */ // Label 1205: @74668
25156 /* 74668 */ GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(74710), // Rule ID 1939 //
25157 /* 74673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
25158 /* 74676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsubs),
25159 /* 74681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25160 /* 74684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25161 /* 74687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25162 /* 74690 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25163 /* 74693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
25164 /* 74697 */ // (intrinsic_wo_chain:{ *:[f32] } 10642:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (XSMSUBMSP:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C)
25165 /* 74697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBMSP),
25166 /* 74700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
25167 /* 74702 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
25168 /* 74704 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
25169 /* 74706 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
25170 /* 74708 */ GIR_RootConstrainSelectedInstOperands,
25171 /* 74709 */ // GIR_Coverage, 1939,
25172 /* 74709 */ GIR_EraseRootFromParent_Done,
25173 /* 74710 */ // Label 1206: @74710
25174 /* 74710 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(74752), // Rule ID 1940 //
25175 /* 74715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
25176 /* 74718 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadds),
25177 /* 74723 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25178 /* 74726 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25179 /* 74729 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25180 /* 74732 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25181 /* 74735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
25182 /* 74739 */ // (intrinsic_wo_chain:{ *:[f32] } 10646:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (XSNMADDMSP:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C)
25183 /* 74739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDMSP),
25184 /* 74742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
25185 /* 74744 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
25186 /* 74746 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
25187 /* 74748 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
25188 /* 74750 */ GIR_RootConstrainSelectedInstOperands,
25189 /* 74751 */ // GIR_Coverage, 1940,
25190 /* 74751 */ GIR_EraseRootFromParent_Done,
25191 /* 74752 */ // Label 1207: @74752
25192 /* 74752 */ GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(74794), // Rule ID 508 //
25193 /* 74757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto),
25194 /* 74760 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vshasigmaw),
25195 /* 74765 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25196 /* 74768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25197 /* 74771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25198 /* 74775 */ // MIs[0] ST
25199 /* 74775 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
25200 /* 74778 */ // MIs[0] SIX
25201 /* 74778 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25202 /* 74781 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10277:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) => (VSHASIGMAW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX)
25203 /* 74781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSHASIGMAW),
25204 /* 74784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25205 /* 74786 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
25206 /* 74788 */ GIR_RootToRootCopy, /*OpIdx*/3, // ST
25207 /* 74790 */ GIR_RootToRootCopy, /*OpIdx*/4, // SIX
25208 /* 74792 */ GIR_RootConstrainSelectedInstOperands,
25209 /* 74793 */ // GIR_Coverage, 508,
25210 /* 74793 */ GIR_EraseRootFromParent_Done,
25211 /* 74794 */ // Label 1208: @74794
25212 /* 74794 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(74836), // Rule ID 509 //
25213 /* 74799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto),
25214 /* 74802 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vshasigmad),
25215 /* 74807 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
25216 /* 74810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25217 /* 74813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25218 /* 74817 */ // MIs[0] ST
25219 /* 74817 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
25220 /* 74820 */ // MIs[0] SIX
25221 /* 74820 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25222 /* 74823 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10276:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) => (VSHASIGMAD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX)
25223 /* 74823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSHASIGMAD),
25224 /* 74826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25225 /* 74828 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
25226 /* 74830 */ GIR_RootToRootCopy, /*OpIdx*/3, // ST
25227 /* 74832 */ GIR_RootToRootCopy, /*OpIdx*/4, // SIX
25228 /* 74834 */ GIR_RootConstrainSelectedInstOperands,
25229 /* 74835 */ // GIR_Coverage, 509,
25230 /* 74835 */ GIR_EraseRootFromParent_Done,
25231 /* 74836 */ // Label 1209: @74836
25232 /* 74836 */ GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(74878), // Rule ID 1060 //
25233 /* 74841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25234 /* 74844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsldbi),
25235 /* 74849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25236 /* 74852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25237 /* 74855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25238 /* 74858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25239 /* 74862 */ // MIs[0] SD
25240 /* 74862 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25241 /* 74865 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10525:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) => (VSLDBI:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD)
25242 /* 74865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLDBI),
25243 /* 74868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT]
25244 /* 74870 */ GIR_RootToRootCopy, /*OpIdx*/2, // VRA
25245 /* 74872 */ GIR_RootToRootCopy, /*OpIdx*/3, // VRB
25246 /* 74874 */ GIR_RootToRootCopy, /*OpIdx*/4, // SD
25247 /* 74876 */ GIR_RootConstrainSelectedInstOperands,
25248 /* 74877 */ // GIR_Coverage, 1060,
25249 /* 74877 */ GIR_EraseRootFromParent_Done,
25250 /* 74878 */ // Label 1210: @74878
25251 /* 74878 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(74920), // Rule ID 1061 //
25252 /* 74883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25253 /* 74886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrdbi),
25254 /* 74891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25255 /* 74894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25256 /* 74897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25257 /* 74900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25258 /* 74904 */ // MIs[0] SD
25259 /* 74904 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25260 /* 74907 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10535:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) => (VSRDBI:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD)
25261 /* 74907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRDBI),
25262 /* 74910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT]
25263 /* 74912 */ GIR_RootToRootCopy, /*OpIdx*/2, // VRA
25264 /* 74914 */ GIR_RootToRootCopy, /*OpIdx*/3, // VRB
25265 /* 74916 */ GIR_RootToRootCopy, /*OpIdx*/4, // SD
25266 /* 74918 */ GIR_RootConstrainSelectedInstOperands,
25267 /* 74919 */ // GIR_Coverage, 1061,
25268 /* 74919 */ GIR_EraseRootFromParent_Done,
25269 /* 74920 */ // Label 1211: @74920
25270 /* 74920 */ GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(74962), // Rule ID 1066 //
25271 /* 74925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25272 /* 74928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsw),
25273 /* 74933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25274 /* 74936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25275 /* 74939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25276 /* 74942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25277 /* 74946 */ // MIs[0] VA
25278 /* 74946 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25279 /* 74949 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10433:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VINSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, (timm:{ *:[i32] }):$VA, i32:{ *:[i32] }:$VB)
25280 /* 74949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSW),
25281 /* 74952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25282 /* 74954 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25283 /* 74956 */ GIR_RootToRootCopy, /*OpIdx*/4, // VA
25284 /* 74958 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
25285 /* 74960 */ GIR_RootConstrainSelectedInstOperands,
25286 /* 74961 */ // GIR_Coverage, 1066,
25287 /* 74961 */ GIR_EraseRootFromParent_Done,
25288 /* 74962 */ // Label 1212: @74962
25289 /* 74962 */ GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(75004), // Rule ID 1067 //
25290 /* 74967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25291 /* 74970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsd),
25292 /* 74975 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
25293 /* 74978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25294 /* 74981 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25295 /* 74984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25296 /* 74988 */ // MIs[0] VA
25297 /* 74988 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25298 /* 74991 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10426:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VB, (timm:{ *:[i32] }):$VA) => (VINSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, (timm:{ *:[i32] }):$VA, i64:{ *:[i64] }:$VB)
25299 /* 74991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSD),
25300 /* 74994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25301 /* 74996 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25302 /* 74998 */ GIR_RootToRootCopy, /*OpIdx*/4, // VA
25303 /* 75000 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
25304 /* 75002 */ GIR_RootConstrainSelectedInstOperands,
25305 /* 75003 */ // GIR_Coverage, 1067,
25306 /* 75003 */ GIR_EraseRootFromParent_Done,
25307 /* 75004 */ // Label 1213: @75004
25308 /* 75004 */ GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(75046), // Rule ID 1168 //
25309 /* 75009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture),
25310 /* 75012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmsha2hash),
25311 /* 75017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
25312 /* 75020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
25313 /* 75023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v1024s1,
25314 /* 75026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
25315 /* 75030 */ // MIs[0] T
25316 /* 75030 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25317 /* 75033 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10689:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v1024i1:{ *:[v1024i1] }:$AB, (timm:{ *:[i32] }):$T) => (DMSHA2HASH:{ *:[v1024i1] } v1024i1:{ *:[v1024i1] }:$ATi, v1024i1:{ *:[v1024i1] }:$AB, (timm:{ *:[i32] }):$T)
25318 /* 75033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMSHA2HASH),
25319 /* 75036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
25320 /* 75038 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
25321 /* 75040 */ GIR_RootToRootCopy, /*OpIdx*/3, // AB
25322 /* 75042 */ GIR_RootToRootCopy, /*OpIdx*/4, // T
25323 /* 75044 */ GIR_RootConstrainSelectedInstOperands,
25324 /* 75045 */ // GIR_Coverage, 1168,
25325 /* 75045 */ GIR_EraseRootFromParent_Done,
25326 /* 75046 */ // Label 1214: @75046
25327 /* 75046 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(75091), // Rule ID 1450 //
25328 /* 75051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
25329 /* 75054 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bcdadd),
25330 /* 75059 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25331 /* 75062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25332 /* 75065 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25333 /* 75068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25334 /* 75072 */ // MIs[0] PS
25335 /* 75072 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25336 /* 75075 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10580:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, (timm:{ *:[i32] }):$PS) => (BCDADD_rec:{ *:[v16i8] }:{ *:[i32] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB, ?:{ *:[i32] }:$PS)
25337 /* 75075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDADD_rec),
25338 /* 75078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25339 /* 75080 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
25340 /* 75082 */ GIR_RootToRootCopy, /*OpIdx*/3, // vB
25341 /* 75084 */ GIR_RootToRootCopy, /*OpIdx*/4, // PS
25342 /* 75086 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0,
25343 /* 75089 */ GIR_RootConstrainSelectedInstOperands,
25344 /* 75090 */ // GIR_Coverage, 1450,
25345 /* 75090 */ GIR_EraseRootFromParent_Done,
25346 /* 75091 */ // Label 1215: @75091
25347 /* 75091 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(75136), // Rule ID 1451 //
25348 /* 75096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
25349 /* 75099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bcdsub),
25350 /* 75104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25351 /* 75107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25352 /* 75110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25353 /* 75113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25354 /* 75117 */ // MIs[0] PS
25355 /* 75117 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
25356 /* 75120 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10582:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, (timm:{ *:[i32] }):$PS) => (BCDSUB_rec:{ *:[v16i8] }:{ *:[i32] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB, ?:{ *:[i32] }:$PS)
25357 /* 75120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDSUB_rec),
25358 /* 75123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25359 /* 75125 */ GIR_RootToRootCopy, /*OpIdx*/2, // vA
25360 /* 75127 */ GIR_RootToRootCopy, /*OpIdx*/3, // vB
25361 /* 75129 */ GIR_RootToRootCopy, /*OpIdx*/4, // PS
25362 /* 75131 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0,
25363 /* 75134 */ GIR_RootConstrainSelectedInstOperands,
25364 /* 75135 */ // GIR_Coverage, 1451,
25365 /* 75135 */ GIR_EraseRootFromParent_Done,
25366 /* 75136 */ // Label 1216: @75136
25367 /* 75136 */ GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(75190), // Rule ID 1566 //
25368 /* 75141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0),
25369 /* 75144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddhd),
25370 /* 75149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
25371 /* 75152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25372 /* 75155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25373 /* 75158 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
25374 /* 75161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25375 /* 75165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25376 /* 75169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25377 /* 75173 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25378 /* 75177 */ // (intrinsic_wo_chain:{ *:[i64] } 10672:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDHD:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c)
25379 /* 75177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDHD),
25380 /* 75180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25381 /* 75182 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
25382 /* 75184 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
25383 /* 75186 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
25384 /* 75188 */ GIR_RootConstrainSelectedInstOperands,
25385 /* 75189 */ // GIR_Coverage, 1566,
25386 /* 75189 */ GIR_EraseRootFromParent_Done,
25387 /* 75190 */ // Label 1217: @75190
25388 /* 75190 */ GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(75244), // Rule ID 1567 //
25389 /* 75195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0),
25390 /* 75198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddhdu),
25391 /* 75203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
25392 /* 75206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25393 /* 75209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25394 /* 75212 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
25395 /* 75215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25396 /* 75219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25397 /* 75223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25398 /* 75227 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25399 /* 75231 */ // (intrinsic_wo_chain:{ *:[i64] } 10673:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDHDU:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c)
25400 /* 75231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDHDU),
25401 /* 75234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25402 /* 75236 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
25403 /* 75238 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
25404 /* 75240 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
25405 /* 75242 */ GIR_RootConstrainSelectedInstOperands,
25406 /* 75243 */ // GIR_Coverage, 1567,
25407 /* 75243 */ GIR_EraseRootFromParent_Done,
25408 /* 75244 */ // Label 1218: @75244
25409 /* 75244 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(75298), // Rule ID 1568 //
25410 /* 75249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0),
25411 /* 75252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddld),
25412 /* 75257 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
25413 /* 75260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25414 /* 75263 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25415 /* 75266 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
25416 /* 75269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25417 /* 75273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25418 /* 75277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25419 /* 75281 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
25420 /* 75285 */ // (intrinsic_wo_chain:{ *:[i64] } 10674:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDLD8:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c)
25421 /* 75285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDLD8),
25422 /* 75288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25423 /* 75290 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
25424 /* 75292 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
25425 /* 75294 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
25426 /* 75296 */ GIR_RootConstrainSelectedInstOperands,
25427 /* 75297 */ // GIR_Coverage, 1568,
25428 /* 75297 */ GIR_EraseRootFromParent_Done,
25429 /* 75298 */ // Label 1219: @75298
25430 /* 75298 */ GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(75349), // Rule ID 4857 //
25431 /* 75303 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fsel),
25432 /* 75308 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
25433 /* 75311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25434 /* 75314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25435 /* 75317 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
25436 /* 75320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
25437 /* 75324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
25438 /* 75328 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
25439 /* 75332 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
25440 /* 75336 */ // (intrinsic_wo_chain:{ *:[f64] } 10652:{ *:[iPTR] }, f8rc:{ *:[f64] }:$FRA, f8rc:{ *:[f64] }:$FRC, f8rc:{ *:[f64] }:$FRB) => (FSELD:{ *:[f64] } ?:{ *:[f64] }:$FRA, ?:{ *:[f64] }:$FRC, ?:{ *:[f64] }:$FRB)
25441 /* 75336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FSELD),
25442 /* 75339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
25443 /* 75341 */ GIR_RootToRootCopy, /*OpIdx*/2, // FRA
25444 /* 75343 */ GIR_RootToRootCopy, /*OpIdx*/3, // FRC
25445 /* 75345 */ GIR_RootToRootCopy, /*OpIdx*/4, // FRB
25446 /* 75347 */ GIR_RootConstrainSelectedInstOperands,
25447 /* 75348 */ // GIR_Coverage, 4857,
25448 /* 75348 */ GIR_EraseRootFromParent_Done,
25449 /* 75349 */ // Label 1220: @75349
25450 /* 75349 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(75391), // Rule ID 296 //
25451 /* 75354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
25452 /* 75357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmladduhm),
25453 /* 75362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25454 /* 75365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25455 /* 75368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25456 /* 75371 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
25457 /* 75374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25458 /* 75378 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10460:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) => (VMLADDUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC)
25459 /* 75378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMLADDUHM),
25460 /* 75381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25461 /* 75383 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25462 /* 75385 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25463 /* 75387 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25464 /* 75389 */ GIR_RootConstrainSelectedInstOperands,
25465 /* 75390 */ // GIR_Coverage, 296,
25466 /* 75390 */ GIR_EraseRootFromParent_Done,
25467 /* 75391 */ // Label 1221: @75391
25468 /* 75391 */ GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(75433), // Rule ID 297 //
25469 /* 75396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
25470 /* 75399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vperm),
25471 /* 75404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25472 /* 75407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25473 /* 75410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25474 /* 75413 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
25475 /* 75416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25476 /* 75420 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10491:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v16i8:{ *:[v16i8] }:$RC) => (VPERM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v16i8:{ *:[v16i8] }:$RC)
25477 /* 75420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERM),
25478 /* 75423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25479 /* 75425 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25480 /* 75427 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25481 /* 75429 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25482 /* 75431 */ GIR_RootConstrainSelectedInstOperands,
25483 /* 75432 */ // GIR_Coverage, 297,
25484 /* 75432 */ GIR_EraseRootFromParent_Done,
25485 /* 75433 */ // Label 1222: @75433
25486 /* 75433 */ GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(75475), // Rule ID 298 //
25487 /* 75438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
25488 /* 75441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsel),
25489 /* 75446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25490 /* 75449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25491 /* 75452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25492 /* 75455 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
25493 /* 75458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25494 /* 75462 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10522:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VSEL:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v4i32:{ *:[v4i32] }:$RC)
25495 /* 75462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL),
25496 /* 75465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25497 /* 75467 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25498 /* 75469 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25499 /* 75471 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25500 /* 75473 */ GIR_RootConstrainSelectedInstOperands,
25501 /* 75474 */ // GIR_Coverage, 298,
25502 /* 75474 */ GIR_EraseRootFromParent_Done,
25503 /* 75475 */ // Label 1223: @75475
25504 /* 75475 */ GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(75517), // Rule ID 349 //
25505 /* 75480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
25506 /* 75483 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsummbm),
25507 /* 75488 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25508 /* 75491 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25509 /* 75494 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25510 /* 75497 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
25511 /* 75500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25512 /* 75504 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10462:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMMBM:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC)
25513 /* 75504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMMBM),
25514 /* 75507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25515 /* 75509 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25516 /* 75511 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25517 /* 75513 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25518 /* 75515 */ GIR_RootConstrainSelectedInstOperands,
25519 /* 75516 */ // GIR_Coverage, 349,
25520 /* 75516 */ GIR_EraseRootFromParent_Done,
25521 /* 75517 */ // Label 1224: @75517
25522 /* 75517 */ GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(75559), // Rule ID 350 //
25523 /* 75522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
25524 /* 75525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumshm),
25525 /* 75530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25526 /* 75533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25527 /* 75536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25528 /* 75539 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
25529 /* 75542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25530 /* 75546 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10463:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMSHM:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC)
25531 /* 75546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMSHM),
25532 /* 75549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25533 /* 75551 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25534 /* 75553 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25535 /* 75555 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25536 /* 75557 */ GIR_RootConstrainSelectedInstOperands,
25537 /* 75558 */ // GIR_Coverage, 350,
25538 /* 75558 */ GIR_EraseRootFromParent_Done,
25539 /* 75559 */ // Label 1225: @75559
25540 /* 75559 */ GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(75601), // Rule ID 351 //
25541 /* 75564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
25542 /* 75567 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumubm),
25543 /* 75572 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25544 /* 75575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25545 /* 75578 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25546 /* 75581 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
25547 /* 75584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25548 /* 75588 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10465:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMUBM:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC)
25549 /* 75588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUBM),
25550 /* 75591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25551 /* 75593 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25552 /* 75595 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25553 /* 75597 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25554 /* 75599 */ GIR_RootConstrainSelectedInstOperands,
25555 /* 75600 */ // GIR_Coverage, 351,
25556 /* 75600 */ GIR_EraseRootFromParent_Done,
25557 /* 75601 */ // Label 1226: @75601
25558 /* 75601 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(75643), // Rule ID 352 //
25559 /* 75606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
25560 /* 75609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumuhm),
25561 /* 75614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25562 /* 75617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25563 /* 75620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25564 /* 75623 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
25565 /* 75626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25566 /* 75630 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10467:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMUHM:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC)
25567 /* 75630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUHM),
25568 /* 75633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25569 /* 75635 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25570 /* 75637 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25571 /* 75639 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25572 /* 75641 */ GIR_RootConstrainSelectedInstOperands,
25573 /* 75642 */ // GIR_Coverage, 352,
25574 /* 75642 */ GIR_EraseRootFromParent_Done,
25575 /* 75643 */ // Label 1227: @75643
25576 /* 75643 */ GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(75685), // Rule ID 471 //
25577 /* 75648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
25578 /* 75651 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddeuqm),
25579 /* 75656 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
25580 /* 75659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
25581 /* 75662 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
25582 /* 75665 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
25583 /* 75668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25584 /* 75672 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10309:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VADDEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC)
25585 /* 75672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDEUQM),
25586 /* 75675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25587 /* 75677 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25588 /* 75679 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25589 /* 75681 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25590 /* 75683 */ GIR_RootConstrainSelectedInstOperands,
25591 /* 75684 */ // GIR_Coverage, 471,
25592 /* 75684 */ GIR_EraseRootFromParent_Done,
25593 /* 75685 */ // Label 1228: @75685
25594 /* 75685 */ GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(75727), // Rule ID 473 //
25595 /* 75690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
25596 /* 75693 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddecuq),
25597 /* 75698 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
25598 /* 75701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
25599 /* 75704 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
25600 /* 75707 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
25601 /* 75710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25602 /* 75714 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10308:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VADDECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC)
25603 /* 75714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDECUQ),
25604 /* 75717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25605 /* 75719 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25606 /* 75721 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25607 /* 75723 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25608 /* 75725 */ GIR_RootConstrainSelectedInstOperands,
25609 /* 75726 */ // GIR_Coverage, 473,
25610 /* 75726 */ GIR_EraseRootFromParent_Done,
25611 /* 75727 */ // Label 1229: @75727
25612 /* 75727 */ GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(75769), // Rule ID 476 //
25613 /* 75732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
25614 /* 75735 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubeuqm),
25615 /* 75740 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
25616 /* 75743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
25617 /* 75746 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
25618 /* 75749 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
25619 /* 75752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25620 /* 75756 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10551:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VSUBEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC)
25621 /* 75756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBEUQM),
25622 /* 75759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25623 /* 75761 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25624 /* 75763 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25625 /* 75765 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25626 /* 75767 */ GIR_RootConstrainSelectedInstOperands,
25627 /* 75768 */ // GIR_Coverage, 476,
25628 /* 75768 */ GIR_EraseRootFromParent_Done,
25629 /* 75769 */ // Label 1230: @75769
25630 /* 75769 */ GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(75811), // Rule ID 478 //
25631 /* 75774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
25632 /* 75777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubecuq),
25633 /* 75782 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
25634 /* 75785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
25635 /* 75788 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
25636 /* 75791 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
25637 /* 75794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25638 /* 75798 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10550:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VSUBECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC)
25639 /* 75798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBECUQ),
25640 /* 75801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25641 /* 75803 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25642 /* 75805 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25643 /* 75807 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25644 /* 75809 */ GIR_RootConstrainSelectedInstOperands,
25645 /* 75810 */ // GIR_Coverage, 478,
25646 /* 75810 */ GIR_EraseRootFromParent_Done,
25647 /* 75811 */ // Label 1231: @75811
25648 /* 75811 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(75853), // Rule ID 515 //
25649 /* 75816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
25650 /* 75819 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumudm),
25651 /* 75824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
25652 /* 75827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25653 /* 75830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
25654 /* 75833 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
25655 /* 75836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25656 /* 75840 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10466:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VMSUMUDM:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC)
25657 /* 75840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUDM),
25658 /* 75843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25659 /* 75845 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25660 /* 75847 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25661 /* 75849 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25662 /* 75851 */ GIR_RootConstrainSelectedInstOperands,
25663 /* 75852 */ // GIR_Coverage, 515,
25664 /* 75852 */ GIR_EraseRootFromParent_Done,
25665 /* 75853 */ // Label 1232: @75853
25666 /* 75853 */ GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(75895), // Rule ID 548 //
25667 /* 75858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
25668 /* 75861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlwmi),
25669 /* 75866 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25670 /* 75869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25671 /* 75872 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25672 /* 75875 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
25673 /* 75878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25674 /* 75882 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10519:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB, v4i32:{ *:[v4i32] }:$VDi) => (VRLWMI:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB, v4i32:{ *:[v4i32] }:$VDi)
25675 /* 75882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLWMI),
25676 /* 75885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25677 /* 75887 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
25678 /* 75889 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
25679 /* 75891 */ GIR_RootToRootCopy, /*OpIdx*/4, // VDi
25680 /* 75893 */ GIR_RootConstrainSelectedInstOperands,
25681 /* 75894 */ // GIR_Coverage, 548,
25682 /* 75894 */ GIR_EraseRootFromParent_Done,
25683 /* 75895 */ // Label 1233: @75895
25684 /* 75895 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(75937), // Rule ID 550 //
25685 /* 75900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
25686 /* 75903 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrldmi),
25687 /* 75908 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
25688 /* 75911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25689 /* 75914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
25690 /* 75917 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
25691 /* 75920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25692 /* 75924 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10513:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB, v2i64:{ *:[v2i64] }:$VDi) => (VRLDMI:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB, v2i64:{ *:[v2i64] }:$VDi)
25693 /* 75924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLDMI),
25694 /* 75927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25695 /* 75929 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
25696 /* 75931 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
25697 /* 75933 */ GIR_RootToRootCopy, /*OpIdx*/4, // VDi
25698 /* 75935 */ GIR_RootConstrainSelectedInstOperands,
25699 /* 75936 */ // GIR_Coverage, 550,
25700 /* 75936 */ GIR_EraseRootFromParent_Done,
25701 /* 75937 */ // Label 1234: @75937
25702 /* 75937 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(75979), // Rule ID 1068 //
25703 /* 75942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25704 /* 75945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbvlx),
25705 /* 75950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25706 /* 75953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25707 /* 75956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25708 /* 75959 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
25709 /* 75962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25710 /* 75966 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10424:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VINSBVLX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB)
25711 /* 75966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBVLX),
25712 /* 75969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25713 /* 75971 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25714 /* 75973 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25715 /* 75975 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25716 /* 75977 */ GIR_RootConstrainSelectedInstOperands,
25717 /* 75978 */ // GIR_Coverage, 1068,
25718 /* 75978 */ GIR_EraseRootFromParent_Done,
25719 /* 75979 */ // Label 1235: @75979
25720 /* 75979 */ GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(76021), // Rule ID 1069 //
25721 /* 75984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25722 /* 75987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbvrx),
25723 /* 75992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25724 /* 75995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25725 /* 75998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25726 /* 76001 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
25727 /* 76004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25728 /* 76008 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10425:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VINSBVRX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB)
25729 /* 76008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBVRX),
25730 /* 76011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25731 /* 76013 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25732 /* 76015 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25733 /* 76017 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25734 /* 76019 */ GIR_RootConstrainSelectedInstOperands,
25735 /* 76020 */ // GIR_Coverage, 1069,
25736 /* 76020 */ GIR_EraseRootFromParent_Done,
25737 /* 76021 */ // Label 1236: @76021
25738 /* 76021 */ GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(76063), // Rule ID 1070 //
25739 /* 76026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25740 /* 76029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshvlx),
25741 /* 76034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25742 /* 76037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25743 /* 76040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25744 /* 76043 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
25745 /* 76046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25746 /* 76050 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10431:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VINSHVLX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB)
25747 /* 76050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHVLX),
25748 /* 76053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25749 /* 76055 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25750 /* 76057 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25751 /* 76059 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25752 /* 76061 */ GIR_RootConstrainSelectedInstOperands,
25753 /* 76062 */ // GIR_Coverage, 1070,
25754 /* 76062 */ GIR_EraseRootFromParent_Done,
25755 /* 76063 */ // Label 1237: @76063
25756 /* 76063 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(76105), // Rule ID 1071 //
25757 /* 76068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25758 /* 76071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshvrx),
25759 /* 76076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25760 /* 76079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25761 /* 76082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25762 /* 76085 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
25763 /* 76088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25764 /* 76092 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10432:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VINSHVRX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB)
25765 /* 76092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHVRX),
25766 /* 76095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25767 /* 76097 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25768 /* 76099 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25769 /* 76101 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25770 /* 76103 */ GIR_RootConstrainSelectedInstOperands,
25771 /* 76104 */ // GIR_Coverage, 1071,
25772 /* 76104 */ GIR_EraseRootFromParent_Done,
25773 /* 76105 */ // Label 1238: @76105
25774 /* 76105 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(76147), // Rule ID 1072 //
25775 /* 76110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25776 /* 76113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswvlx),
25777 /* 76118 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25778 /* 76121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25779 /* 76124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25780 /* 76127 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
25781 /* 76130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25782 /* 76134 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10436:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VINSWVLX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
25783 /* 76134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWVLX),
25784 /* 76137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25785 /* 76139 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25786 /* 76141 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25787 /* 76143 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25788 /* 76145 */ GIR_RootConstrainSelectedInstOperands,
25789 /* 76146 */ // GIR_Coverage, 1072,
25790 /* 76146 */ GIR_EraseRootFromParent_Done,
25791 /* 76147 */ // Label 1239: @76147
25792 /* 76147 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(76189), // Rule ID 1073 //
25793 /* 76152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25794 /* 76155 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswvrx),
25795 /* 76160 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25796 /* 76163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25797 /* 76166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25798 /* 76169 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
25799 /* 76172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25800 /* 76176 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10437:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VINSWVRX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
25801 /* 76176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWVRX),
25802 /* 76179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25803 /* 76181 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25804 /* 76183 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25805 /* 76185 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25806 /* 76187 */ GIR_RootConstrainSelectedInstOperands,
25807 /* 76188 */ // GIR_Coverage, 1073,
25808 /* 76188 */ GIR_EraseRootFromParent_Done,
25809 /* 76189 */ // Label 1240: @76189
25810 /* 76189 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(76231), // Rule ID 1074 //
25811 /* 76194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25812 /* 76197 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsblx),
25813 /* 76202 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25814 /* 76205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25815 /* 76208 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25816 /* 76211 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25817 /* 76214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25818 /* 76218 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10422:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSBLX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB)
25819 /* 76218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBLX),
25820 /* 76221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25821 /* 76223 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25822 /* 76225 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25823 /* 76227 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25824 /* 76229 */ GIR_RootConstrainSelectedInstOperands,
25825 /* 76230 */ // GIR_Coverage, 1074,
25826 /* 76230 */ GIR_EraseRootFromParent_Done,
25827 /* 76231 */ // Label 1241: @76231
25828 /* 76231 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(76273), // Rule ID 1075 //
25829 /* 76236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25830 /* 76239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbrx),
25831 /* 76244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25832 /* 76247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25833 /* 76250 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25834 /* 76253 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25835 /* 76256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25836 /* 76260 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10423:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSBRX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB)
25837 /* 76260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBRX),
25838 /* 76263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25839 /* 76265 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25840 /* 76267 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25841 /* 76269 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25842 /* 76271 */ GIR_RootConstrainSelectedInstOperands,
25843 /* 76272 */ // GIR_Coverage, 1075,
25844 /* 76272 */ GIR_EraseRootFromParent_Done,
25845 /* 76273 */ // Label 1242: @76273
25846 /* 76273 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(76315), // Rule ID 1076 //
25847 /* 76278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25848 /* 76281 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshlx),
25849 /* 76286 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25850 /* 76289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25851 /* 76292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25852 /* 76295 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25853 /* 76298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25854 /* 76302 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10429:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSHLX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB)
25855 /* 76302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHLX),
25856 /* 76305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25857 /* 76307 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25858 /* 76309 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25859 /* 76311 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25860 /* 76313 */ GIR_RootConstrainSelectedInstOperands,
25861 /* 76314 */ // GIR_Coverage, 1076,
25862 /* 76314 */ GIR_EraseRootFromParent_Done,
25863 /* 76315 */ // Label 1243: @76315
25864 /* 76315 */ GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(76357), // Rule ID 1077 //
25865 /* 76320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25866 /* 76323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshrx),
25867 /* 76328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25868 /* 76331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25869 /* 76334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25870 /* 76337 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25871 /* 76340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25872 /* 76344 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10430:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSHRX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB)
25873 /* 76344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHRX),
25874 /* 76347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25875 /* 76349 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25876 /* 76351 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25877 /* 76353 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25878 /* 76355 */ GIR_RootConstrainSelectedInstOperands,
25879 /* 76356 */ // GIR_Coverage, 1077,
25880 /* 76356 */ GIR_EraseRootFromParent_Done,
25881 /* 76357 */ // Label 1244: @76357
25882 /* 76357 */ GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(76399), // Rule ID 1078 //
25883 /* 76362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25884 /* 76365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswlx),
25885 /* 76370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25886 /* 76373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25887 /* 76376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25888 /* 76379 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25889 /* 76382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25890 /* 76386 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10434:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSWLX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB)
25891 /* 76386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWLX),
25892 /* 76389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25893 /* 76391 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25894 /* 76393 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25895 /* 76395 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25896 /* 76397 */ GIR_RootConstrainSelectedInstOperands,
25897 /* 76398 */ // GIR_Coverage, 1078,
25898 /* 76398 */ GIR_EraseRootFromParent_Done,
25899 /* 76399 */ // Label 1245: @76399
25900 /* 76399 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(76441), // Rule ID 1079 //
25901 /* 76404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25902 /* 76407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswrx),
25903 /* 76412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25904 /* 76415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25905 /* 76418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25906 /* 76421 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25907 /* 76424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25908 /* 76428 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10435:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSWRX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB)
25909 /* 76428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWRX),
25910 /* 76431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25911 /* 76433 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25912 /* 76435 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25913 /* 76437 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25914 /* 76439 */ GIR_RootConstrainSelectedInstOperands,
25915 /* 76440 */ // GIR_Coverage, 1079,
25916 /* 76440 */ GIR_EraseRootFromParent_Done,
25917 /* 76441 */ // Label 1246: @76441
25918 /* 76441 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(76483), // Rule ID 1080 //
25919 /* 76446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25920 /* 76449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsdlx),
25921 /* 76454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
25922 /* 76457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25923 /* 76460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25924 /* 76463 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
25925 /* 76466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25926 /* 76470 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10427:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) => (VINSDLX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB)
25927 /* 76470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSDLX),
25928 /* 76473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25929 /* 76475 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25930 /* 76477 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25931 /* 76479 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25932 /* 76481 */ GIR_RootConstrainSelectedInstOperands,
25933 /* 76482 */ // GIR_Coverage, 1080,
25934 /* 76482 */ GIR_EraseRootFromParent_Done,
25935 /* 76483 */ // Label 1247: @76483
25936 /* 76483 */ GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(76525), // Rule ID 1081 //
25937 /* 76488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25938 /* 76491 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsdrx),
25939 /* 76496 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
25940 /* 76499 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25941 /* 76502 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25942 /* 76505 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
25943 /* 76508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25944 /* 76512 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10428:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) => (VINSDRX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB)
25945 /* 76512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSDRX),
25946 /* 76515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
25947 /* 76517 */ GIR_RootToRootCopy, /*OpIdx*/2, // VDi
25948 /* 76519 */ GIR_RootToRootCopy, /*OpIdx*/3, // VA
25949 /* 76521 */ GIR_RootToRootCopy, /*OpIdx*/4, // VB
25950 /* 76523 */ GIR_RootConstrainSelectedInstOperands,
25951 /* 76524 */ // GIR_Coverage, 1081,
25952 /* 76524 */ GIR_EraseRootFromParent_Done,
25953 /* 76525 */ // Label 1248: @76525
25954 /* 76525 */ GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(76567), // Rule ID 1102 //
25955 /* 76530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25956 /* 76533 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextdubvlx),
25957 /* 76538 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
25958 /* 76541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25959 /* 76544 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25960 /* 76547 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25961 /* 76550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25962 /* 76554 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10403:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUBVLX:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC)
25963 /* 76554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUBVLX),
25964 /* 76557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25965 /* 76559 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25966 /* 76561 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25967 /* 76563 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25968 /* 76565 */ GIR_RootConstrainSelectedInstOperands,
25969 /* 76566 */ // GIR_Coverage, 1102,
25970 /* 76566 */ GIR_EraseRootFromParent_Done,
25971 /* 76567 */ // Label 1249: @76567
25972 /* 76567 */ GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(76609), // Rule ID 1103 //
25973 /* 76572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25974 /* 76575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextdubvrx),
25975 /* 76580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
25976 /* 76583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25977 /* 76586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25978 /* 76589 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25979 /* 76592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25980 /* 76596 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10404:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUBVRX:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC)
25981 /* 76596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUBVRX),
25982 /* 76599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
25983 /* 76601 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
25984 /* 76603 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
25985 /* 76605 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
25986 /* 76607 */ GIR_RootConstrainSelectedInstOperands,
25987 /* 76608 */ // GIR_Coverage, 1103,
25988 /* 76608 */ GIR_EraseRootFromParent_Done,
25989 /* 76609 */ // Label 1250: @76609
25990 /* 76609 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(76651), // Rule ID 1104 //
25991 /* 76614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
25992 /* 76617 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduhvlx),
25993 /* 76622 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
25994 /* 76625 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25995 /* 76628 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25996 /* 76631 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25997 /* 76634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
25998 /* 76638 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10405:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUHVLX:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC)
25999 /* 76638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUHVLX),
26000 /* 76641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26001 /* 76643 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
26002 /* 76645 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
26003 /* 76647 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
26004 /* 76649 */ GIR_RootConstrainSelectedInstOperands,
26005 /* 76650 */ // GIR_Coverage, 1104,
26006 /* 76650 */ GIR_EraseRootFromParent_Done,
26007 /* 76651 */ // Label 1251: @76651
26008 /* 76651 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(76693), // Rule ID 1105 //
26009 /* 76656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
26010 /* 76659 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduhvrx),
26011 /* 76664 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
26012 /* 76667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26013 /* 76670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26014 /* 76673 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26015 /* 76676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26016 /* 76680 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10406:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUHVRX:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC)
26017 /* 76680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUHVRX),
26018 /* 76683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26019 /* 76685 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
26020 /* 76687 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
26021 /* 76689 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
26022 /* 76691 */ GIR_RootConstrainSelectedInstOperands,
26023 /* 76692 */ // GIR_Coverage, 1105,
26024 /* 76692 */ GIR_EraseRootFromParent_Done,
26025 /* 76693 */ // Label 1252: @76693
26026 /* 76693 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(76735), // Rule ID 1106 //
26027 /* 76698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
26028 /* 76701 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduwvlx),
26029 /* 76706 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
26030 /* 76709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26031 /* 76712 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26032 /* 76715 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26033 /* 76718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26034 /* 76722 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10407:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUWVLX:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC)
26035 /* 76722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUWVLX),
26036 /* 76725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26037 /* 76727 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
26038 /* 76729 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
26039 /* 76731 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
26040 /* 76733 */ GIR_RootConstrainSelectedInstOperands,
26041 /* 76734 */ // GIR_Coverage, 1106,
26042 /* 76734 */ GIR_EraseRootFromParent_Done,
26043 /* 76735 */ // Label 1253: @76735
26044 /* 76735 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(76777), // Rule ID 1107 //
26045 /* 76740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
26046 /* 76743 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduwvrx),
26047 /* 76748 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
26048 /* 76751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26049 /* 76754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26050 /* 76757 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26051 /* 76760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26052 /* 76764 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10408:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUWVRX:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC)
26053 /* 76764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUWVRX),
26054 /* 76767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26055 /* 76769 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
26056 /* 76771 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
26057 /* 76773 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
26058 /* 76775 */ GIR_RootConstrainSelectedInstOperands,
26059 /* 76776 */ // GIR_Coverage, 1107,
26060 /* 76776 */ GIR_EraseRootFromParent_Done,
26061 /* 76777 */ // Label 1254: @76777
26062 /* 76777 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(76819), // Rule ID 1108 //
26063 /* 76782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
26064 /* 76785 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextddvlx),
26065 /* 76790 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
26066 /* 76793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26067 /* 76796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
26068 /* 76799 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26069 /* 76802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26070 /* 76806 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10401:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDDVLX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC)
26071 /* 76806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDDVLX),
26072 /* 76809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26073 /* 76811 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
26074 /* 76813 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
26075 /* 76815 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
26076 /* 76817 */ GIR_RootConstrainSelectedInstOperands,
26077 /* 76818 */ // GIR_Coverage, 1108,
26078 /* 76818 */ GIR_EraseRootFromParent_Done,
26079 /* 76819 */ // Label 1255: @76819
26080 /* 76819 */ GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(76861), // Rule ID 1109 //
26081 /* 76824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
26082 /* 76827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextddvrx),
26083 /* 76832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
26084 /* 76835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26085 /* 76838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
26086 /* 76841 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26087 /* 76844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26088 /* 76848 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10402:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDDVRX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC)
26089 /* 76848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDDVRX),
26090 /* 76851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26091 /* 76853 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
26092 /* 76855 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
26093 /* 76857 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
26094 /* 76859 */ GIR_RootConstrainSelectedInstOperands,
26095 /* 76860 */ // GIR_Coverage, 1109,
26096 /* 76860 */ GIR_EraseRootFromParent_Done,
26097 /* 76861 */ // Label 1256: @76861
26098 /* 76861 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(76903), // Rule ID 1147 //
26099 /* 76866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
26100 /* 76869 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumcud),
26101 /* 76874 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
26102 /* 76877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26103 /* 76880 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
26104 /* 76883 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
26105 /* 76886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26106 /* 76890 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10461:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VMSUMCUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC)
26107 /* 76890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMCUD),
26108 /* 76893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26109 /* 76895 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
26110 /* 76897 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
26111 /* 76899 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
26112 /* 76901 */ GIR_RootConstrainSelectedInstOperands,
26113 /* 76902 */ // GIR_Coverage, 1147,
26114 /* 76902 */ GIR_EraseRootFromParent_Done,
26115 /* 76903 */ // Label 1257: @76903
26116 /* 76903 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(76945), // Rule ID 1162 //
26117 /* 76908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
26118 /* 76911 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlqmi),
26119 /* 76916 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128,
26120 /* 76919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
26121 /* 76922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
26122 /* 76925 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128,
26123 /* 76928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26124 /* 76932 */ // (intrinsic_wo_chain:{ *:[v1i128] } 10516:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB, v1i128:{ *:[v1i128] }:$VDi) => (VRLQMI:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB, v1i128:{ *:[v1i128] }:$VDi)
26125 /* 76932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLQMI),
26126 /* 76935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
26127 /* 76937 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
26128 /* 76939 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
26129 /* 76941 */ GIR_RootToRootCopy, /*OpIdx*/4, // VDi
26130 /* 76943 */ GIR_RootConstrainSelectedInstOperands,
26131 /* 76944 */ // GIR_Coverage, 1162,
26132 /* 76944 */ GIR_EraseRootFromParent_Done,
26133 /* 76945 */ // Label 1258: @76945
26134 /* 76945 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(76984), // Rule ID 1282 //
26135 /* 76950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsub),
26136 /* 76955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
26137 /* 76958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26138 /* 76961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26139 /* 76964 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
26140 /* 76967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
26141 /* 76971 */ // (intrinsic_wo_chain:{ *:[f64] } 10641:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (FMSUB:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C)
26142 /* 76971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUB),
26143 /* 76974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
26144 /* 76976 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
26145 /* 76978 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
26146 /* 76980 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
26147 /* 76982 */ GIR_RootConstrainSelectedInstOperands,
26148 /* 76983 */ // GIR_Coverage, 1282,
26149 /* 76983 */ GIR_EraseRootFromParent_Done,
26150 /* 76984 */ // Label 1259: @76984
26151 /* 76984 */ GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(77023), // Rule ID 1283 //
26152 /* 76989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsubs),
26153 /* 76994 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26154 /* 76997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26155 /* 77000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26156 /* 77003 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26157 /* 77006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
26158 /* 77010 */ // (intrinsic_wo_chain:{ *:[f32] } 10642:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (FMSUBS:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C)
26159 /* 77010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUBS),
26160 /* 77013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
26161 /* 77015 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
26162 /* 77017 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
26163 /* 77019 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
26164 /* 77021 */ GIR_RootConstrainSelectedInstOperands,
26165 /* 77022 */ // GIR_Coverage, 1283,
26166 /* 77022 */ GIR_EraseRootFromParent_Done,
26167 /* 77023 */ // Label 1260: @77023
26168 /* 77023 */ GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(77062), // Rule ID 1284 //
26169 /* 77028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadd),
26170 /* 77033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
26171 /* 77036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26172 /* 77039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26173 /* 77042 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
26174 /* 77045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
26175 /* 77049 */ // (intrinsic_wo_chain:{ *:[f64] } 10645:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (FNMADD:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C)
26176 /* 77049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADD),
26177 /* 77052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
26178 /* 77054 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
26179 /* 77056 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
26180 /* 77058 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
26181 /* 77060 */ GIR_RootConstrainSelectedInstOperands,
26182 /* 77061 */ // GIR_Coverage, 1284,
26183 /* 77061 */ GIR_EraseRootFromParent_Done,
26184 /* 77062 */ // Label 1261: @77062
26185 /* 77062 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(77101), // Rule ID 1285 //
26186 /* 77067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadds),
26187 /* 77072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26188 /* 77075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26189 /* 77078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26190 /* 77081 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26191 /* 77084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
26192 /* 77088 */ // (intrinsic_wo_chain:{ *:[f32] } 10646:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (FNMADDS:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C)
26193 /* 77088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADDS),
26194 /* 77091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
26195 /* 77093 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
26196 /* 77095 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
26197 /* 77097 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
26198 /* 77099 */ GIR_RootConstrainSelectedInstOperands,
26199 /* 77100 */ // GIR_Coverage, 1285,
26200 /* 77100 */ GIR_EraseRootFromParent_Done,
26201 /* 77101 */ // Label 1262: @77101
26202 /* 77101 */ GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(77143), // Rule ID 1387 //
26203 /* 77106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
26204 /* 77109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaddfp),
26205 /* 77114 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26206 /* 77117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26207 /* 77120 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26208 /* 77123 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26209 /* 77126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26210 /* 77130 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10439:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B, v4f32:{ *:[v4f32] }:$C) => (VMADDFP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B, ?:{ *:[v4f32] }:$C)
26211 /* 77130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMADDFP),
26212 /* 77133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26213 /* 77135 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
26214 /* 77137 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
26215 /* 77139 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
26216 /* 77141 */ GIR_RootConstrainSelectedInstOperands,
26217 /* 77142 */ // GIR_Coverage, 1387,
26218 /* 77142 */ GIR_EraseRootFromParent_Done,
26219 /* 77143 */ // Label 1263: @77143
26220 /* 77143 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(77185), // Rule ID 1388 //
26221 /* 77148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
26222 /* 77151 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vnmsubfp),
26223 /* 77156 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26224 /* 77159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26225 /* 77162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26226 /* 77165 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26227 /* 77168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26228 /* 77172 */ // (intrinsic_wo_chain:{ *:[v4f32] } 10489:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B, v4f32:{ *:[v4f32] }:$C) => (VNMSUBFP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B, ?:{ *:[v4f32] }:$C)
26229 /* 77172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNMSUBFP),
26230 /* 77175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26231 /* 77177 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
26232 /* 77179 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
26233 /* 77181 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
26234 /* 77183 */ GIR_RootConstrainSelectedInstOperands,
26235 /* 77184 */ // GIR_Coverage, 1388,
26236 /* 77184 */ GIR_EraseRootFromParent_Done,
26237 /* 77185 */ // Label 1264: @77185
26238 /* 77185 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(77290), // Rule ID 1584 //
26239 /* 77190 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX_IsLittleEndian),
26240 /* 77193 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor),
26241 /* 77198 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26242 /* 77201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26243 /* 77204 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26244 /* 77207 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26245 /* 77210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26246 /* 77214 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10269:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, (XXLNOR:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$c, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$c, VSRC:{ *:[i32] })))
26247 /* 77214 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
26248 /* 77217 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26249 /* 77221 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26250 /* 77226 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // c
26251 /* 77230 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26252 /* 77235 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26253 /* 77238 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26254 /* 77242 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26255 /* 77247 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // c
26256 /* 77251 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26257 /* 77256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26258 /* 77259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLNOR),
26259 /* 77263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26260 /* 77268 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26261 /* 77271 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
26262 /* 77274 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26263 /* 77276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR),
26264 /* 77279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26265 /* 77281 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
26266 /* 77283 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
26267 /* 77285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26268 /* 77288 */ GIR_RootConstrainSelectedInstOperands,
26269 /* 77289 */ // GIR_Coverage, 1584,
26270 /* 77289 */ GIR_EraseRootFromParent_Done,
26271 /* 77290 */ // Label 1265: @77290
26272 /* 77290 */ GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(77332), // Rule ID 1585 //
26273 /* 77295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX_IsBigEndian),
26274 /* 77298 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor),
26275 /* 77303 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26276 /* 77306 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26277 /* 77309 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26278 /* 77312 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26279 /* 77315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26280 /* 77319 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10269:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, ?:{ *:[v16i8] }:$c)
26281 /* 77319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR),
26282 /* 77322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26283 /* 77324 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
26284 /* 77326 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
26285 /* 77328 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
26286 /* 77330 */ GIR_RootConstrainSelectedInstOperands,
26287 /* 77331 */ // GIR_Coverage, 1585,
26288 /* 77331 */ GIR_EraseRootFromParent_Done,
26289 /* 77332 */ // Label 1266: @77332
26290 /* 77332 */ GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(77374), // Rule ID 1586 //
26291 /* 77337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX),
26292 /* 77340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor_be),
26293 /* 77345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26294 /* 77348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26295 /* 77351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26296 /* 77354 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26297 /* 77357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
26298 /* 77361 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10270:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, ?:{ *:[v16i8] }:$c)
26299 /* 77361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR),
26300 /* 77364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
26301 /* 77366 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
26302 /* 77368 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
26303 /* 77370 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
26304 /* 77372 */ GIR_RootConstrainSelectedInstOperands,
26305 /* 77373 */ // GIR_Coverage, 1586,
26306 /* 77373 */ GIR_EraseRootFromParent_Done,
26307 /* 77374 */ // Label 1267: @77374
26308 /* 77374 */ GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(77503), // Rule ID 3432 //
26309 /* 77379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
26310 /* 77382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvb),
26311 /* 77387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26312 /* 77390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26313 /* 77393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26314 /* 77396 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26315 /* 77399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
26316 /* 77403 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10917:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$A, v16i8:{ *:[v16i8] }:$B, v16i8:{ *:[v16i8] }:$C) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXBLENDVB:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$C, VSRC:{ *:[i32] })), VSRC:{ *:[i32] })
26317 /* 77403 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
26318 /* 77406 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26319 /* 77410 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26320 /* 77415 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C
26321 /* 77419 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26322 /* 77424 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
26323 /* 77427 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26324 /* 77431 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26325 /* 77436 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B
26326 /* 77440 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26327 /* 77445 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26328 /* 77448 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26329 /* 77452 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26330 /* 77457 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A
26331 /* 77461 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26332 /* 77466 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26333 /* 77469 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVB),
26334 /* 77473 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26335 /* 77478 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26336 /* 77481 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
26337 /* 77484 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
26338 /* 77487 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26339 /* 77489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26340 /* 77492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
26341 /* 77494 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26342 /* 77497 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26343 /* 77502 */ // GIR_Coverage, 3432,
26344 /* 77502 */ GIR_EraseRootFromParent_Done,
26345 /* 77503 */ // Label 1268: @77503
26346 /* 77503 */ GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(77632), // Rule ID 3433 //
26347 /* 77508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
26348 /* 77511 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvh),
26349 /* 77516 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26350 /* 77519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26351 /* 77522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26352 /* 77525 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
26353 /* 77528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
26354 /* 77532 */ // (intrinsic_wo_chain:{ *:[v8i16] } 10919:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$A, v8i16:{ *:[v8i16] }:$B, v8i16:{ *:[v8i16] }:$C) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXBLENDVH:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$C, VSRC:{ *:[i32] })), VSRC:{ *:[i32] })
26355 /* 77532 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
26356 /* 77535 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26357 /* 77539 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26358 /* 77544 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C
26359 /* 77548 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26360 /* 77553 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
26361 /* 77556 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26362 /* 77560 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26363 /* 77565 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B
26364 /* 77569 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26365 /* 77574 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26366 /* 77577 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26367 /* 77581 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26368 /* 77586 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A
26369 /* 77590 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26370 /* 77595 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26371 /* 77598 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVH),
26372 /* 77602 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26373 /* 77607 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26374 /* 77610 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
26375 /* 77613 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
26376 /* 77616 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26377 /* 77618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26378 /* 77621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
26379 /* 77623 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26380 /* 77626 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26381 /* 77631 */ // GIR_Coverage, 3433,
26382 /* 77631 */ GIR_EraseRootFromParent_Done,
26383 /* 77632 */ // Label 1269: @77632
26384 /* 77632 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(77674), // Rule ID 3434 //
26385 /* 77637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
26386 /* 77640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvw),
26387 /* 77645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26388 /* 77648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26389 /* 77651 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26390 /* 77654 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26391 /* 77657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
26392 /* 77661 */ // (intrinsic_wo_chain:{ *:[v4i32] } 10920:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v4i32:{ *:[v4i32] }:$B, v4i32:{ *:[v4i32] }:$C) => (XXBLENDVW:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C)
26393 /* 77661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVW),
26394 /* 77664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
26395 /* 77666 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
26396 /* 77668 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
26397 /* 77670 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
26398 /* 77672 */ GIR_RootConstrainSelectedInstOperands,
26399 /* 77673 */ // GIR_Coverage, 3434,
26400 /* 77673 */ GIR_EraseRootFromParent_Done,
26401 /* 77674 */ // Label 1270: @77674
26402 /* 77674 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(77716), // Rule ID 3435 //
26403 /* 77679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
26404 /* 77682 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvd),
26405 /* 77687 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
26406 /* 77690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26407 /* 77693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
26408 /* 77696 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
26409 /* 77699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
26410 /* 77703 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10918:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$A, v2i64:{ *:[v2i64] }:$B, v2i64:{ *:[v2i64] }:$C) => (XXBLENDVD:{ *:[v2i64] } ?:{ *:[v2i64] }:$A, ?:{ *:[v2i64] }:$B, ?:{ *:[v2i64] }:$C)
26411 /* 77703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVD),
26412 /* 77706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
26413 /* 77708 */ GIR_RootToRootCopy, /*OpIdx*/2, // A
26414 /* 77710 */ GIR_RootToRootCopy, /*OpIdx*/3, // B
26415 /* 77712 */ GIR_RootToRootCopy, /*OpIdx*/4, // C
26416 /* 77714 */ GIR_RootConstrainSelectedInstOperands,
26417 /* 77715 */ // GIR_Coverage, 3435,
26418 /* 77715 */ GIR_EraseRootFromParent_Done,
26419 /* 77716 */ // Label 1271: @77716
26420 /* 77716 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(77780), // Rule ID 3517 //
26421 /* 77721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26422 /* 77724 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvi8gerx4pp),
26423 /* 77729 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26424 /* 77732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26425 /* 77735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26426 /* 77738 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26427 /* 77741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26428 /* 77745 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10703:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVI8GERX4PP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26429 /* 77745 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26430 /* 77748 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26431 /* 77752 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26432 /* 77757 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26433 /* 77761 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26434 /* 77766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVI8GERX4PP),
26435 /* 77769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26436 /* 77771 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26437 /* 77773 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26438 /* 77775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26439 /* 77778 */ GIR_RootConstrainSelectedInstOperands,
26440 /* 77779 */ // GIR_Coverage, 3517,
26441 /* 77779 */ GIR_EraseRootFromParent_Done,
26442 /* 77780 */ // Label 1272: @77780
26443 /* 77780 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(77844), // Rule ID 3518 //
26444 /* 77785 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26445 /* 77788 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvi8gerx4spp),
26446 /* 77793 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26447 /* 77796 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26448 /* 77799 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26449 /* 77802 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26450 /* 77805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26451 /* 77809 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10704:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVI8GERX4SPP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26452 /* 77809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26453 /* 77812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26454 /* 77816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26455 /* 77821 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26456 /* 77825 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26457 /* 77830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVI8GERX4SPP),
26458 /* 77833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26459 /* 77835 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26460 /* 77837 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26461 /* 77839 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26462 /* 77842 */ GIR_RootConstrainSelectedInstOperands,
26463 /* 77843 */ // GIR_Coverage, 3518,
26464 /* 77843 */ GIR_EraseRootFromParent_Done,
26465 /* 77844 */ // Label 1273: @77844
26466 /* 77844 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(77908), // Rule ID 3520 //
26467 /* 77849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26468 /* 77852 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvbf16gerx2pp),
26469 /* 77857 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26470 /* 77860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26471 /* 77863 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26472 /* 77866 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26473 /* 77869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26474 /* 77873 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10696:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVBF16GERX2PP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26475 /* 77873 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26476 /* 77876 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26477 /* 77880 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26478 /* 77885 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26479 /* 77889 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26480 /* 77894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVBF16GERX2PP),
26481 /* 77897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26482 /* 77899 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26483 /* 77901 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26484 /* 77903 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26485 /* 77906 */ GIR_RootConstrainSelectedInstOperands,
26486 /* 77907 */ // GIR_Coverage, 3520,
26487 /* 77907 */ GIR_EraseRootFromParent_Done,
26488 /* 77908 */ // Label 1274: @77908
26489 /* 77908 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(77972), // Rule ID 3521 //
26490 /* 77913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26491 /* 77916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvbf16gerx2pn),
26492 /* 77921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26493 /* 77924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26494 /* 77927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26495 /* 77930 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26496 /* 77933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26497 /* 77937 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10695:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVBF16GERX2PN:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26498 /* 77937 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26499 /* 77940 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26500 /* 77944 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26501 /* 77949 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26502 /* 77953 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26503 /* 77958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVBF16GERX2PN),
26504 /* 77961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26505 /* 77963 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26506 /* 77965 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26507 /* 77967 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26508 /* 77970 */ GIR_RootConstrainSelectedInstOperands,
26509 /* 77971 */ // GIR_Coverage, 3521,
26510 /* 77971 */ GIR_EraseRootFromParent_Done,
26511 /* 77972 */ // Label 1275: @77972
26512 /* 77972 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(78036), // Rule ID 3522 //
26513 /* 77977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26514 /* 77980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvbf16gerx2np),
26515 /* 77985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26516 /* 77988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26517 /* 77991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26518 /* 77994 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26519 /* 77997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26520 /* 78001 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10694:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVBF16GERX2NP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26521 /* 78001 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26522 /* 78004 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26523 /* 78008 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26524 /* 78013 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26525 /* 78017 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26526 /* 78022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVBF16GERX2NP),
26527 /* 78025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26528 /* 78027 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26529 /* 78029 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26530 /* 78031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26531 /* 78034 */ GIR_RootConstrainSelectedInstOperands,
26532 /* 78035 */ // GIR_Coverage, 3522,
26533 /* 78035 */ GIR_EraseRootFromParent_Done,
26534 /* 78036 */ // Label 1276: @78036
26535 /* 78036 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(78100), // Rule ID 3523 //
26536 /* 78041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26537 /* 78044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvbf16gerx2nn),
26538 /* 78049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26539 /* 78052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26540 /* 78055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26541 /* 78058 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26542 /* 78061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26543 /* 78065 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10693:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVBF16GERX2NN:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26544 /* 78065 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26545 /* 78068 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26546 /* 78072 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26547 /* 78077 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26548 /* 78081 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26549 /* 78086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVBF16GERX2NN),
26550 /* 78089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26551 /* 78091 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26552 /* 78093 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26553 /* 78095 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26554 /* 78098 */ GIR_RootConstrainSelectedInstOperands,
26555 /* 78099 */ // GIR_Coverage, 3523,
26556 /* 78099 */ GIR_EraseRootFromParent_Done,
26557 /* 78100 */ // Label 1277: @78100
26558 /* 78100 */ GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(78164), // Rule ID 3525 //
26559 /* 78105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26560 /* 78108 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvf16gerx2pp),
26561 /* 78113 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26562 /* 78116 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26563 /* 78119 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26564 /* 78122 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26565 /* 78125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26566 /* 78129 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10701:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVF16GERX2PP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26567 /* 78129 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26568 /* 78132 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26569 /* 78136 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26570 /* 78141 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26571 /* 78145 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26572 /* 78150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVF16GERX2PP),
26573 /* 78153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26574 /* 78155 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26575 /* 78157 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26576 /* 78159 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26577 /* 78162 */ GIR_RootConstrainSelectedInstOperands,
26578 /* 78163 */ // GIR_Coverage, 3525,
26579 /* 78163 */ GIR_EraseRootFromParent_Done,
26580 /* 78164 */ // Label 1278: @78164
26581 /* 78164 */ GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(78228), // Rule ID 3526 //
26582 /* 78169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26583 /* 78172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvf16gerx2pn),
26584 /* 78177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26585 /* 78180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26586 /* 78183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26587 /* 78186 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26588 /* 78189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26589 /* 78193 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10700:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVF16GERX2PN:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26590 /* 78193 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26591 /* 78196 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26592 /* 78200 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26593 /* 78205 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26594 /* 78209 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26595 /* 78214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVF16GERX2PN),
26596 /* 78217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26597 /* 78219 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26598 /* 78221 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26599 /* 78223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26600 /* 78226 */ GIR_RootConstrainSelectedInstOperands,
26601 /* 78227 */ // GIR_Coverage, 3526,
26602 /* 78227 */ GIR_EraseRootFromParent_Done,
26603 /* 78228 */ // Label 1279: @78228
26604 /* 78228 */ GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(78292), // Rule ID 3527 //
26605 /* 78233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26606 /* 78236 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvf16gerx2np),
26607 /* 78241 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26608 /* 78244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26609 /* 78247 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26610 /* 78250 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26611 /* 78253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26612 /* 78257 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10699:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVF16GERX2NP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26613 /* 78257 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26614 /* 78260 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26615 /* 78264 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26616 /* 78269 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26617 /* 78273 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26618 /* 78278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVF16GERX2NP),
26619 /* 78281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26620 /* 78283 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26621 /* 78285 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26622 /* 78287 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26623 /* 78290 */ GIR_RootConstrainSelectedInstOperands,
26624 /* 78291 */ // GIR_Coverage, 3527,
26625 /* 78291 */ GIR_EraseRootFromParent_Done,
26626 /* 78292 */ // Label 1280: @78292
26627 /* 78292 */ GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(78356), // Rule ID 3528 //
26628 /* 78297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26629 /* 78300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxvf16gerx2nn),
26630 /* 78305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
26631 /* 78308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
26632 /* 78311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
26633 /* 78314 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26634 /* 78317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
26635 /* 78321 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10698:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB) => (DMXVF16GERX2NN:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26636 /* 78321 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26637 /* 78324 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26638 /* 78328 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26639 /* 78333 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
26640 /* 78337 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26641 /* 78342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXVF16GERX2NN),
26642 /* 78345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26643 /* 78347 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26644 /* 78349 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
26645 /* 78351 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26646 /* 78354 */ GIR_RootConstrainSelectedInstOperands,
26647 /* 78355 */ // GIR_Coverage, 3528,
26648 /* 78355 */ GIR_EraseRootFromParent_Done,
26649 /* 78356 */ // Label 1281: @78356
26650 /* 78356 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(78442), // Rule ID 3544 //
26651 /* 78361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
26652 /* 78364 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8pp),
26653 /* 78369 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26654 /* 78372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26655 /* 78375 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26656 /* 78378 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26657 /* 78381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
26658 /* 78385 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10777:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26659 /* 78385 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26660 /* 78388 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26661 /* 78392 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26662 /* 78397 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26663 /* 78401 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26664 /* 78406 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26665 /* 78409 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26666 /* 78413 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26667 /* 78418 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26668 /* 78422 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26669 /* 78427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8PP),
26670 /* 78430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26671 /* 78432 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26672 /* 78434 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26673 /* 78437 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26674 /* 78440 */ GIR_RootConstrainSelectedInstOperands,
26675 /* 78441 */ // GIR_Coverage, 3544,
26676 /* 78441 */ GIR_EraseRootFromParent_Done,
26677 /* 78442 */ // Label 1282: @78442
26678 /* 78442 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(78528), // Rule ID 3546 //
26679 /* 78447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
26680 /* 78450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4pp),
26681 /* 78455 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26682 /* 78458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26683 /* 78461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26684 /* 78464 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26685 /* 78467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
26686 /* 78471 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10779:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26687 /* 78471 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26688 /* 78474 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26689 /* 78478 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26690 /* 78483 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26691 /* 78487 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26692 /* 78492 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26693 /* 78495 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26694 /* 78499 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26695 /* 78504 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26696 /* 78508 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26697 /* 78513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4PP),
26698 /* 78516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26699 /* 78518 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26700 /* 78520 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26701 /* 78523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26702 /* 78526 */ GIR_RootConstrainSelectedInstOperands,
26703 /* 78527 */ // GIR_Coverage, 3546,
26704 /* 78527 */ GIR_EraseRootFromParent_Done,
26705 /* 78528 */ // Label 1283: @78528
26706 /* 78528 */ GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(78614), // Rule ID 3548 //
26707 /* 78533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
26708 /* 78536 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2spp),
26709 /* 78541 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26710 /* 78544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26711 /* 78547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26712 /* 78550 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26713 /* 78553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
26714 /* 78557 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10775:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26715 /* 78557 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26716 /* 78560 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26717 /* 78564 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26718 /* 78569 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26719 /* 78573 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26720 /* 78578 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26721 /* 78581 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26722 /* 78585 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26723 /* 78590 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26724 /* 78594 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26725 /* 78599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SPP),
26726 /* 78602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26727 /* 78604 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26728 /* 78606 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26729 /* 78609 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26730 /* 78612 */ GIR_RootConstrainSelectedInstOperands,
26731 /* 78613 */ // GIR_Coverage, 3548,
26732 /* 78613 */ GIR_EraseRootFromParent_Done,
26733 /* 78614 */ // Label 1284: @78614
26734 /* 78614 */ GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(78700), // Rule ID 3550 //
26735 /* 78619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26736 /* 78622 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8pp),
26737 /* 78627 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26738 /* 78630 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26739 /* 78633 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26740 /* 78636 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26741 /* 78639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
26742 /* 78643 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10777:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26743 /* 78643 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26744 /* 78646 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26745 /* 78650 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26746 /* 78655 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26747 /* 78659 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26748 /* 78664 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26749 /* 78667 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26750 /* 78671 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26751 /* 78676 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26752 /* 78680 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26753 /* 78685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8WPP),
26754 /* 78688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26755 /* 78690 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26756 /* 78692 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26757 /* 78695 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26758 /* 78698 */ GIR_RootConstrainSelectedInstOperands,
26759 /* 78699 */ // GIR_Coverage, 3550,
26760 /* 78699 */ GIR_EraseRootFromParent_Done,
26761 /* 78700 */ // Label 1285: @78700
26762 /* 78700 */ GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(78786), // Rule ID 3552 //
26763 /* 78705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26764 /* 78708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4pp),
26765 /* 78713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26766 /* 78716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26767 /* 78719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26768 /* 78722 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26769 /* 78725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
26770 /* 78729 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10779:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26771 /* 78729 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26772 /* 78732 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26773 /* 78736 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26774 /* 78741 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26775 /* 78745 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26776 /* 78750 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26777 /* 78753 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26778 /* 78757 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26779 /* 78762 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26780 /* 78766 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26781 /* 78771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4WPP),
26782 /* 78774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26783 /* 78776 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26784 /* 78778 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26785 /* 78781 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26786 /* 78784 */ GIR_RootConstrainSelectedInstOperands,
26787 /* 78785 */ // GIR_Coverage, 3552,
26788 /* 78785 */ GIR_EraseRootFromParent_Done,
26789 /* 78786 */ // Label 1286: @78786
26790 /* 78786 */ GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(78872), // Rule ID 3554 //
26791 /* 78791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26792 /* 78794 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2spp),
26793 /* 78799 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26794 /* 78802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26795 /* 78805 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26796 /* 78808 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26797 /* 78811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
26798 /* 78815 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10775:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26799 /* 78815 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26800 /* 78818 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26801 /* 78822 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26802 /* 78827 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26803 /* 78831 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26804 /* 78836 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26805 /* 78839 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26806 /* 78843 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26807 /* 78848 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26808 /* 78852 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26809 /* 78857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SWPP),
26810 /* 78860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26811 /* 78862 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26812 /* 78864 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26813 /* 78867 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26814 /* 78870 */ GIR_RootConstrainSelectedInstOperands,
26815 /* 78871 */ // GIR_Coverage, 3554,
26816 /* 78871 */ GIR_EraseRootFromParent_Done,
26817 /* 78872 */ // Label 1287: @78872
26818 /* 78872 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(78958), // Rule ID 3556 //
26819 /* 78877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
26820 /* 78880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pp),
26821 /* 78885 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26822 /* 78888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26823 /* 78891 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26824 /* 78894 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26825 /* 78897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
26826 /* 78901 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10761:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26827 /* 78901 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26828 /* 78904 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26829 /* 78908 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26830 /* 78913 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26831 /* 78917 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26832 /* 78922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26833 /* 78925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26834 /* 78929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26835 /* 78934 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26836 /* 78938 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26837 /* 78943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2PP),
26838 /* 78946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26839 /* 78948 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26840 /* 78950 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26841 /* 78953 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26842 /* 78956 */ GIR_RootConstrainSelectedInstOperands,
26843 /* 78957 */ // GIR_Coverage, 3556,
26844 /* 78957 */ GIR_EraseRootFromParent_Done,
26845 /* 78958 */ // Label 1288: @78958
26846 /* 78958 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(79044), // Rule ID 3557 //
26847 /* 78963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
26848 /* 78966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pn),
26849 /* 78971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26850 /* 78974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26851 /* 78977 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26852 /* 78980 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26853 /* 78983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
26854 /* 78987 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10760:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26855 /* 78987 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26856 /* 78990 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26857 /* 78994 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26858 /* 78999 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26859 /* 79003 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26860 /* 79008 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26861 /* 79011 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26862 /* 79015 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26863 /* 79020 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26864 /* 79024 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26865 /* 79029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2PN),
26866 /* 79032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26867 /* 79034 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26868 /* 79036 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26869 /* 79039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26870 /* 79042 */ GIR_RootConstrainSelectedInstOperands,
26871 /* 79043 */ // GIR_Coverage, 3557,
26872 /* 79043 */ GIR_EraseRootFromParent_Done,
26873 /* 79044 */ // Label 1289: @79044
26874 /* 79044 */ GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(79130), // Rule ID 3558 //
26875 /* 79049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
26876 /* 79052 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2np),
26877 /* 79057 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26878 /* 79060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26879 /* 79063 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26880 /* 79066 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26881 /* 79069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
26882 /* 79073 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10759:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26883 /* 79073 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26884 /* 79076 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26885 /* 79080 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26886 /* 79085 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26887 /* 79089 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26888 /* 79094 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26889 /* 79097 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26890 /* 79101 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26891 /* 79106 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26892 /* 79110 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26893 /* 79115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2NP),
26894 /* 79118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26895 /* 79120 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26896 /* 79122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26897 /* 79125 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26898 /* 79128 */ GIR_RootConstrainSelectedInstOperands,
26899 /* 79129 */ // GIR_Coverage, 3558,
26900 /* 79129 */ GIR_EraseRootFromParent_Done,
26901 /* 79130 */ // Label 1290: @79130
26902 /* 79130 */ GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(79216), // Rule ID 3559 //
26903 /* 79135 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
26904 /* 79138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2nn),
26905 /* 79143 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26906 /* 79146 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26907 /* 79149 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26908 /* 79152 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26909 /* 79155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
26910 /* 79159 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10758:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26911 /* 79159 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26912 /* 79162 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26913 /* 79166 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26914 /* 79171 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26915 /* 79175 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26916 /* 79180 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26917 /* 79183 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26918 /* 79187 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26919 /* 79192 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26920 /* 79196 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26921 /* 79201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2NN),
26922 /* 79204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26923 /* 79206 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26924 /* 79208 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26925 /* 79211 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26926 /* 79214 */ GIR_RootConstrainSelectedInstOperands,
26927 /* 79215 */ // GIR_Coverage, 3559,
26928 /* 79215 */ GIR_EraseRootFromParent_Done,
26929 /* 79216 */ // Label 1291: @79216
26930 /* 79216 */ GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(79302), // Rule ID 3561 //
26931 /* 79221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26932 /* 79224 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pp),
26933 /* 79229 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26934 /* 79232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26935 /* 79235 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26936 /* 79238 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26937 /* 79241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
26938 /* 79245 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10761:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26939 /* 79245 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26940 /* 79248 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26941 /* 79252 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26942 /* 79257 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26943 /* 79261 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26944 /* 79266 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26945 /* 79269 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26946 /* 79273 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26947 /* 79278 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26948 /* 79282 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26949 /* 79287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WPP),
26950 /* 79290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26951 /* 79292 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26952 /* 79294 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26953 /* 79297 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26954 /* 79300 */ GIR_RootConstrainSelectedInstOperands,
26955 /* 79301 */ // GIR_Coverage, 3561,
26956 /* 79301 */ GIR_EraseRootFromParent_Done,
26957 /* 79302 */ // Label 1292: @79302
26958 /* 79302 */ GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(79388), // Rule ID 3562 //
26959 /* 79307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26960 /* 79310 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pn),
26961 /* 79315 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26962 /* 79318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26963 /* 79321 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26964 /* 79324 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26965 /* 79327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
26966 /* 79331 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10760:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26967 /* 79331 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26968 /* 79334 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26969 /* 79338 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26970 /* 79343 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26971 /* 79347 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26972 /* 79352 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26973 /* 79355 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26974 /* 79359 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26975 /* 79364 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
26976 /* 79368 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
26977 /* 79373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WPN),
26978 /* 79376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
26979 /* 79378 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
26980 /* 79380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26981 /* 79383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
26982 /* 79386 */ GIR_RootConstrainSelectedInstOperands,
26983 /* 79387 */ // GIR_Coverage, 3562,
26984 /* 79387 */ GIR_EraseRootFromParent_Done,
26985 /* 79388 */ // Label 1293: @79388
26986 /* 79388 */ GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(79474), // Rule ID 3563 //
26987 /* 79393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
26988 /* 79396 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2np),
26989 /* 79401 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
26990 /* 79404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
26991 /* 79407 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26992 /* 79410 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
26993 /* 79413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
26994 /* 79417 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10759:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
26995 /* 79417 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26996 /* 79420 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26997 /* 79424 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26998 /* 79429 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
26999 /* 79433 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27000 /* 79438 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27001 /* 79441 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27002 /* 79445 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27003 /* 79450 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27004 /* 79454 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27005 /* 79459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WNP),
27006 /* 79462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27007 /* 79464 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27008 /* 79466 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27009 /* 79469 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27010 /* 79472 */ GIR_RootConstrainSelectedInstOperands,
27011 /* 79473 */ // GIR_Coverage, 3563,
27012 /* 79473 */ GIR_EraseRootFromParent_Done,
27013 /* 79474 */ // Label 1294: @79474
27014 /* 79474 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(79560), // Rule ID 3564 //
27015 /* 79479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27016 /* 79482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2nn),
27017 /* 79487 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27018 /* 79490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27019 /* 79493 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27020 /* 79496 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27021 /* 79499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27022 /* 79503 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10758:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27023 /* 79503 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27024 /* 79506 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27025 /* 79510 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27026 /* 79515 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27027 /* 79519 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27028 /* 79524 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27029 /* 79527 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27030 /* 79531 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27031 /* 79536 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27032 /* 79540 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27033 /* 79545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WNN),
27034 /* 79548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27035 /* 79550 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27036 /* 79552 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27037 /* 79555 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27038 /* 79558 */ GIR_RootConstrainSelectedInstOperands,
27039 /* 79559 */ // GIR_Coverage, 3564,
27040 /* 79559 */ GIR_EraseRootFromParent_Done,
27041 /* 79560 */ // Label 1295: @79560
27042 /* 79560 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(79646), // Rule ID 3566 //
27043 /* 79565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27044 /* 79568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpp),
27045 /* 79573 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27046 /* 79576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27047 /* 79579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27048 /* 79582 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27049 /* 79585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27050 /* 79589 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10766:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27051 /* 79589 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27052 /* 79592 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27053 /* 79596 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27054 /* 79601 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27055 /* 79605 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27056 /* 79610 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27057 /* 79613 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27058 /* 79617 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27059 /* 79622 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27060 /* 79626 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27061 /* 79631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERPP),
27062 /* 79634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27063 /* 79636 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27064 /* 79638 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27065 /* 79641 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27066 /* 79644 */ GIR_RootConstrainSelectedInstOperands,
27067 /* 79645 */ // GIR_Coverage, 3566,
27068 /* 79645 */ GIR_EraseRootFromParent_Done,
27069 /* 79646 */ // Label 1296: @79646
27070 /* 79646 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(79732), // Rule ID 3567 //
27071 /* 79651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27072 /* 79654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpn),
27073 /* 79659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27074 /* 79662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27075 /* 79665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27076 /* 79668 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27077 /* 79671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27078 /* 79675 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10765:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27079 /* 79675 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27080 /* 79678 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27081 /* 79682 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27082 /* 79687 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27083 /* 79691 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27084 /* 79696 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27085 /* 79699 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27086 /* 79703 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27087 /* 79708 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27088 /* 79712 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27089 /* 79717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERPN),
27090 /* 79720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27091 /* 79722 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27092 /* 79724 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27093 /* 79727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27094 /* 79730 */ GIR_RootConstrainSelectedInstOperands,
27095 /* 79731 */ // GIR_Coverage, 3567,
27096 /* 79731 */ GIR_EraseRootFromParent_Done,
27097 /* 79732 */ // Label 1297: @79732
27098 /* 79732 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(79818), // Rule ID 3568 //
27099 /* 79737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27100 /* 79740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernp),
27101 /* 79745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27102 /* 79748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27103 /* 79751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27104 /* 79754 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27105 /* 79757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27106 /* 79761 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10764:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27107 /* 79761 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27108 /* 79764 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27109 /* 79768 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27110 /* 79773 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27111 /* 79777 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27112 /* 79782 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27113 /* 79785 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27114 /* 79789 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27115 /* 79794 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27116 /* 79798 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27117 /* 79803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERNP),
27118 /* 79806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27119 /* 79808 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27120 /* 79810 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27121 /* 79813 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27122 /* 79816 */ GIR_RootConstrainSelectedInstOperands,
27123 /* 79817 */ // GIR_Coverage, 3568,
27124 /* 79817 */ GIR_EraseRootFromParent_Done,
27125 /* 79818 */ // Label 1298: @79818
27126 /* 79818 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(79904), // Rule ID 3569 //
27127 /* 79823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27128 /* 79826 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernn),
27129 /* 79831 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27130 /* 79834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27131 /* 79837 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27132 /* 79840 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27133 /* 79843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27134 /* 79847 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10763:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27135 /* 79847 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27136 /* 79850 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27137 /* 79854 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27138 /* 79859 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27139 /* 79863 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27140 /* 79868 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27141 /* 79871 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27142 /* 79875 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27143 /* 79880 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27144 /* 79884 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27145 /* 79889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERNN),
27146 /* 79892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27147 /* 79894 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27148 /* 79896 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27149 /* 79899 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27150 /* 79902 */ GIR_RootConstrainSelectedInstOperands,
27151 /* 79903 */ // GIR_Coverage, 3569,
27152 /* 79903 */ GIR_EraseRootFromParent_Done,
27153 /* 79904 */ // Label 1299: @79904
27154 /* 79904 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(79968), // Rule ID 3571 //
27155 /* 79909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27156 /* 79912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpp),
27157 /* 79917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27158 /* 79920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27159 /* 79923 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
27160 /* 79926 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27161 /* 79929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27162 /* 79933 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10771:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27163 /* 79933 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27164 /* 79936 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27165 /* 79940 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27166 /* 79945 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
27167 /* 79949 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27168 /* 79954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERPP),
27169 /* 79957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27170 /* 79959 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27171 /* 79961 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
27172 /* 79963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27173 /* 79966 */ GIR_RootConstrainSelectedInstOperands,
27174 /* 79967 */ // GIR_Coverage, 3571,
27175 /* 79967 */ GIR_EraseRootFromParent_Done,
27176 /* 79968 */ // Label 1300: @79968
27177 /* 79968 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(80032), // Rule ID 3572 //
27178 /* 79973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27179 /* 79976 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpn),
27180 /* 79981 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27181 /* 79984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27182 /* 79987 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
27183 /* 79990 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27184 /* 79993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27185 /* 79997 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10770:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27186 /* 79997 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27187 /* 80000 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27188 /* 80004 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27189 /* 80009 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
27190 /* 80013 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27191 /* 80018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERPN),
27192 /* 80021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27193 /* 80023 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27194 /* 80025 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
27195 /* 80027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27196 /* 80030 */ GIR_RootConstrainSelectedInstOperands,
27197 /* 80031 */ // GIR_Coverage, 3572,
27198 /* 80031 */ GIR_EraseRootFromParent_Done,
27199 /* 80032 */ // Label 1301: @80032
27200 /* 80032 */ GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(80096), // Rule ID 3573 //
27201 /* 80037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27202 /* 80040 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernp),
27203 /* 80045 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27204 /* 80048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27205 /* 80051 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
27206 /* 80054 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27207 /* 80057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27208 /* 80061 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10769:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27209 /* 80061 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27210 /* 80064 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27211 /* 80068 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27212 /* 80073 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
27213 /* 80077 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27214 /* 80082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNP),
27215 /* 80085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27216 /* 80087 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27217 /* 80089 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
27218 /* 80091 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27219 /* 80094 */ GIR_RootConstrainSelectedInstOperands,
27220 /* 80095 */ // GIR_Coverage, 3573,
27221 /* 80095 */ GIR_EraseRootFromParent_Done,
27222 /* 80096 */ // Label 1302: @80096
27223 /* 80096 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(80160), // Rule ID 3574 //
27224 /* 80101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27225 /* 80104 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernn),
27226 /* 80109 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27227 /* 80112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27228 /* 80115 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
27229 /* 80118 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27230 /* 80121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27231 /* 80125 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10768:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27232 /* 80125 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27233 /* 80128 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27234 /* 80132 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27235 /* 80137 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
27236 /* 80141 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27237 /* 80146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNN),
27238 /* 80149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27239 /* 80151 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27240 /* 80153 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
27241 /* 80155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27242 /* 80158 */ GIR_RootConstrainSelectedInstOperands,
27243 /* 80159 */ // GIR_Coverage, 3574,
27244 /* 80159 */ GIR_EraseRootFromParent_Done,
27245 /* 80160 */ // Label 1303: @80160
27246 /* 80160 */ GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(80246), // Rule ID 3576 //
27247 /* 80165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27248 /* 80168 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pp),
27249 /* 80173 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27250 /* 80176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27251 /* 80179 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27252 /* 80182 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27253 /* 80185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27254 /* 80189 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10756:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27255 /* 80189 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27256 /* 80192 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27257 /* 80196 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27258 /* 80201 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27259 /* 80205 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27260 /* 80210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27261 /* 80213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27262 /* 80217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27263 /* 80222 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27264 /* 80226 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27265 /* 80231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2PP),
27266 /* 80234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27267 /* 80236 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27268 /* 80238 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27269 /* 80241 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27270 /* 80244 */ GIR_RootConstrainSelectedInstOperands,
27271 /* 80245 */ // GIR_Coverage, 3576,
27272 /* 80245 */ GIR_EraseRootFromParent_Done,
27273 /* 80246 */ // Label 1304: @80246
27274 /* 80246 */ GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(80332), // Rule ID 3577 //
27275 /* 80251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27276 /* 80254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pn),
27277 /* 80259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27278 /* 80262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27279 /* 80265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27280 /* 80268 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27281 /* 80271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27282 /* 80275 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10755:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27283 /* 80275 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27284 /* 80278 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27285 /* 80282 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27286 /* 80287 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27287 /* 80291 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27288 /* 80296 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27289 /* 80299 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27290 /* 80303 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27291 /* 80308 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27292 /* 80312 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27293 /* 80317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2PN),
27294 /* 80320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27295 /* 80322 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27296 /* 80324 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27297 /* 80327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27298 /* 80330 */ GIR_RootConstrainSelectedInstOperands,
27299 /* 80331 */ // GIR_Coverage, 3577,
27300 /* 80331 */ GIR_EraseRootFromParent_Done,
27301 /* 80332 */ // Label 1305: @80332
27302 /* 80332 */ GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(80418), // Rule ID 3578 //
27303 /* 80337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27304 /* 80340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2np),
27305 /* 80345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27306 /* 80348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27307 /* 80351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27308 /* 80354 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27309 /* 80357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27310 /* 80361 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10754:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27311 /* 80361 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27312 /* 80364 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27313 /* 80368 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27314 /* 80373 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27315 /* 80377 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27316 /* 80382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27317 /* 80385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27318 /* 80389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27319 /* 80394 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27320 /* 80398 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27321 /* 80403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2NP),
27322 /* 80406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27323 /* 80408 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27324 /* 80410 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27325 /* 80413 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27326 /* 80416 */ GIR_RootConstrainSelectedInstOperands,
27327 /* 80417 */ // GIR_Coverage, 3578,
27328 /* 80417 */ GIR_EraseRootFromParent_Done,
27329 /* 80418 */ // Label 1306: @80418
27330 /* 80418 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(80504), // Rule ID 3579 //
27331 /* 80423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27332 /* 80426 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2nn),
27333 /* 80431 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27334 /* 80434 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27335 /* 80437 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27336 /* 80440 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27337 /* 80443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27338 /* 80447 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10753:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27339 /* 80447 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27340 /* 80450 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27341 /* 80454 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27342 /* 80459 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27343 /* 80463 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27344 /* 80468 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27345 /* 80471 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27346 /* 80475 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27347 /* 80480 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27348 /* 80484 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27349 /* 80489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2NN),
27350 /* 80492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27351 /* 80494 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27352 /* 80496 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27353 /* 80499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27354 /* 80502 */ GIR_RootConstrainSelectedInstOperands,
27355 /* 80503 */ // GIR_Coverage, 3579,
27356 /* 80503 */ GIR_EraseRootFromParent_Done,
27357 /* 80504 */ // Label 1307: @80504
27358 /* 80504 */ GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(80590), // Rule ID 3581 //
27359 /* 80509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27360 /* 80512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2pp),
27361 /* 80517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27362 /* 80520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27363 /* 80523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27364 /* 80526 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27365 /* 80529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27366 /* 80533 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10773:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27367 /* 80533 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27368 /* 80536 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27369 /* 80540 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27370 /* 80545 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27371 /* 80549 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27372 /* 80554 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27373 /* 80557 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27374 /* 80561 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27375 /* 80566 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27376 /* 80570 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27377 /* 80575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2PP),
27378 /* 80578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27379 /* 80580 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27380 /* 80582 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27381 /* 80585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27382 /* 80588 */ GIR_RootConstrainSelectedInstOperands,
27383 /* 80589 */ // GIR_Coverage, 3581,
27384 /* 80589 */ GIR_EraseRootFromParent_Done,
27385 /* 80590 */ // Label 1308: @80590
27386 /* 80590 */ GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(80676), // Rule ID 3582 //
27387 /* 80595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA),
27388 /* 80598 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4spp),
27389 /* 80603 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27390 /* 80606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27391 /* 80609 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27392 /* 80612 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27393 /* 80615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27394 /* 80619 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10780:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27395 /* 80619 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27396 /* 80622 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27397 /* 80626 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27398 /* 80631 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27399 /* 80635 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27400 /* 80640 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27401 /* 80643 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27402 /* 80647 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27403 /* 80652 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27404 /* 80656 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27405 /* 80661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4SPP),
27406 /* 80664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27407 /* 80666 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27408 /* 80668 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27409 /* 80671 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27410 /* 80674 */ GIR_RootConstrainSelectedInstOperands,
27411 /* 80675 */ // GIR_Coverage, 3582,
27412 /* 80675 */ GIR_EraseRootFromParent_Done,
27413 /* 80676 */ // Label 1309: @80676
27414 /* 80676 */ GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(80762), // Rule ID 3584 //
27415 /* 80681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27416 /* 80684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpp),
27417 /* 80689 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27418 /* 80692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27419 /* 80695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27420 /* 80698 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27421 /* 80701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27422 /* 80705 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10766:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27423 /* 80705 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27424 /* 80708 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27425 /* 80712 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27426 /* 80717 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27427 /* 80721 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27428 /* 80726 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27429 /* 80729 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27430 /* 80733 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27431 /* 80738 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27432 /* 80742 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27433 /* 80747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWPP),
27434 /* 80750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27435 /* 80752 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27436 /* 80754 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27437 /* 80757 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27438 /* 80760 */ GIR_RootConstrainSelectedInstOperands,
27439 /* 80761 */ // GIR_Coverage, 3584,
27440 /* 80761 */ GIR_EraseRootFromParent_Done,
27441 /* 80762 */ // Label 1310: @80762
27442 /* 80762 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(80848), // Rule ID 3585 //
27443 /* 80767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27444 /* 80770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpn),
27445 /* 80775 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27446 /* 80778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27447 /* 80781 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27448 /* 80784 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27449 /* 80787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27450 /* 80791 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10765:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27451 /* 80791 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27452 /* 80794 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27453 /* 80798 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27454 /* 80803 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27455 /* 80807 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27456 /* 80812 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27457 /* 80815 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27458 /* 80819 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27459 /* 80824 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27460 /* 80828 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27461 /* 80833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWPN),
27462 /* 80836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27463 /* 80838 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27464 /* 80840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27465 /* 80843 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27466 /* 80846 */ GIR_RootConstrainSelectedInstOperands,
27467 /* 80847 */ // GIR_Coverage, 3585,
27468 /* 80847 */ GIR_EraseRootFromParent_Done,
27469 /* 80848 */ // Label 1311: @80848
27470 /* 80848 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(80934), // Rule ID 3586 //
27471 /* 80853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27472 /* 80856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernp),
27473 /* 80861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27474 /* 80864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27475 /* 80867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27476 /* 80870 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27477 /* 80873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27478 /* 80877 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10764:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27479 /* 80877 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27480 /* 80880 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27481 /* 80884 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27482 /* 80889 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27483 /* 80893 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27484 /* 80898 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27485 /* 80901 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27486 /* 80905 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27487 /* 80910 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27488 /* 80914 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27489 /* 80919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWNP),
27490 /* 80922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27491 /* 80924 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27492 /* 80926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27493 /* 80929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27494 /* 80932 */ GIR_RootConstrainSelectedInstOperands,
27495 /* 80933 */ // GIR_Coverage, 3586,
27496 /* 80933 */ GIR_EraseRootFromParent_Done,
27497 /* 80934 */ // Label 1312: @80934
27498 /* 80934 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(81020), // Rule ID 3587 //
27499 /* 80939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27500 /* 80942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernn),
27501 /* 80947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27502 /* 80950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27503 /* 80953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27504 /* 80956 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27505 /* 80959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27506 /* 80963 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10763:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27507 /* 80963 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27508 /* 80966 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27509 /* 80970 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27510 /* 80975 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27511 /* 80979 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27512 /* 80984 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27513 /* 80987 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27514 /* 80991 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27515 /* 80996 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27516 /* 81000 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27517 /* 81005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWNN),
27518 /* 81008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27519 /* 81010 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27520 /* 81012 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27521 /* 81015 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27522 /* 81018 */ GIR_RootConstrainSelectedInstOperands,
27523 /* 81019 */ // GIR_Coverage, 3587,
27524 /* 81019 */ GIR_EraseRootFromParent_Done,
27525 /* 81020 */ // Label 1313: @81020
27526 /* 81020 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(81084), // Rule ID 3589 //
27527 /* 81025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27528 /* 81028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpp),
27529 /* 81033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27530 /* 81036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27531 /* 81039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
27532 /* 81042 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27533 /* 81045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27534 /* 81049 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10771:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27535 /* 81049 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27536 /* 81052 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27537 /* 81056 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27538 /* 81061 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
27539 /* 81065 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27540 /* 81070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWPP),
27541 /* 81073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27542 /* 81075 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27543 /* 81077 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
27544 /* 81079 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27545 /* 81082 */ GIR_RootConstrainSelectedInstOperands,
27546 /* 81083 */ // GIR_Coverage, 3589,
27547 /* 81083 */ GIR_EraseRootFromParent_Done,
27548 /* 81084 */ // Label 1314: @81084
27549 /* 81084 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(81148), // Rule ID 3590 //
27550 /* 81089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27551 /* 81092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpn),
27552 /* 81097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27553 /* 81100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27554 /* 81103 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
27555 /* 81106 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27556 /* 81109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27557 /* 81113 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10770:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27558 /* 81113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27559 /* 81116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27560 /* 81120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27561 /* 81125 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
27562 /* 81129 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27563 /* 81134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWPN),
27564 /* 81137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27565 /* 81139 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27566 /* 81141 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
27567 /* 81143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27568 /* 81146 */ GIR_RootConstrainSelectedInstOperands,
27569 /* 81147 */ // GIR_Coverage, 3590,
27570 /* 81147 */ GIR_EraseRootFromParent_Done,
27571 /* 81148 */ // Label 1315: @81148
27572 /* 81148 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(81212), // Rule ID 3591 //
27573 /* 81153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27574 /* 81156 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernp),
27575 /* 81161 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27576 /* 81164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27577 /* 81167 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
27578 /* 81170 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27579 /* 81173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27580 /* 81177 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10769:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27581 /* 81177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27582 /* 81180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27583 /* 81184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27584 /* 81189 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
27585 /* 81193 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27586 /* 81198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNP),
27587 /* 81201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27588 /* 81203 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27589 /* 81205 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
27590 /* 81207 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27591 /* 81210 */ GIR_RootConstrainSelectedInstOperands,
27592 /* 81211 */ // GIR_Coverage, 3591,
27593 /* 81211 */ GIR_EraseRootFromParent_Done,
27594 /* 81212 */ // Label 1316: @81212
27595 /* 81212 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(81276), // Rule ID 3592 //
27596 /* 81217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27597 /* 81220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernn),
27598 /* 81225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27599 /* 81228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27600 /* 81231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
27601 /* 81234 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27602 /* 81237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27603 /* 81241 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10768:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27604 /* 81241 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27605 /* 81244 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27606 /* 81248 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27607 /* 81253 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
27608 /* 81257 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27609 /* 81262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWNN),
27610 /* 81265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27611 /* 81267 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27612 /* 81269 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
27613 /* 81271 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27614 /* 81274 */ GIR_RootConstrainSelectedInstOperands,
27615 /* 81275 */ // GIR_Coverage, 3592,
27616 /* 81275 */ GIR_EraseRootFromParent_Done,
27617 /* 81276 */ // Label 1317: @81276
27618 /* 81276 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(81362), // Rule ID 3594 //
27619 /* 81281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27620 /* 81284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pp),
27621 /* 81289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27622 /* 81292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27623 /* 81295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27624 /* 81298 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27625 /* 81301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27626 /* 81305 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10756:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27627 /* 81305 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27628 /* 81308 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27629 /* 81312 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27630 /* 81317 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27631 /* 81321 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27632 /* 81326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27633 /* 81329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27634 /* 81333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27635 /* 81338 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27636 /* 81342 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27637 /* 81347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WPP),
27638 /* 81350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27639 /* 81352 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27640 /* 81354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27641 /* 81357 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27642 /* 81360 */ GIR_RootConstrainSelectedInstOperands,
27643 /* 81361 */ // GIR_Coverage, 3594,
27644 /* 81361 */ GIR_EraseRootFromParent_Done,
27645 /* 81362 */ // Label 1318: @81362
27646 /* 81362 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(81448), // Rule ID 3595 //
27647 /* 81367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27648 /* 81370 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pn),
27649 /* 81375 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27650 /* 81378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27651 /* 81381 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27652 /* 81384 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27653 /* 81387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27654 /* 81391 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10755:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27655 /* 81391 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27656 /* 81394 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27657 /* 81398 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27658 /* 81403 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27659 /* 81407 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27660 /* 81412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27661 /* 81415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27662 /* 81419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27663 /* 81424 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27664 /* 81428 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27665 /* 81433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WPN),
27666 /* 81436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27667 /* 81438 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27668 /* 81440 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27669 /* 81443 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27670 /* 81446 */ GIR_RootConstrainSelectedInstOperands,
27671 /* 81447 */ // GIR_Coverage, 3595,
27672 /* 81447 */ GIR_EraseRootFromParent_Done,
27673 /* 81448 */ // Label 1319: @81448
27674 /* 81448 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(81534), // Rule ID 3596 //
27675 /* 81453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27676 /* 81456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2np),
27677 /* 81461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27678 /* 81464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27679 /* 81467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27680 /* 81470 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27681 /* 81473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27682 /* 81477 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10754:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27683 /* 81477 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27684 /* 81480 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27685 /* 81484 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27686 /* 81489 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27687 /* 81493 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27688 /* 81498 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27689 /* 81501 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27690 /* 81505 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27691 /* 81510 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27692 /* 81514 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27693 /* 81519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WNP),
27694 /* 81522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27695 /* 81524 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27696 /* 81526 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27697 /* 81529 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27698 /* 81532 */ GIR_RootConstrainSelectedInstOperands,
27699 /* 81533 */ // GIR_Coverage, 3596,
27700 /* 81533 */ GIR_EraseRootFromParent_Done,
27701 /* 81534 */ // Label 1320: @81534
27702 /* 81534 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(81620), // Rule ID 3597 //
27703 /* 81539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27704 /* 81542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2nn),
27705 /* 81547 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27706 /* 81550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27707 /* 81553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27708 /* 81556 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27709 /* 81559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27710 /* 81563 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10753:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27711 /* 81563 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27712 /* 81566 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27713 /* 81570 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27714 /* 81575 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27715 /* 81579 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27716 /* 81584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27717 /* 81587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27718 /* 81591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27719 /* 81596 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27720 /* 81600 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27721 /* 81605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WNN),
27722 /* 81608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27723 /* 81610 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27724 /* 81612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27725 /* 81615 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27726 /* 81618 */ GIR_RootConstrainSelectedInstOperands,
27727 /* 81619 */ // GIR_Coverage, 3597,
27728 /* 81619 */ GIR_EraseRootFromParent_Done,
27729 /* 81620 */ // Label 1321: @81620
27730 /* 81620 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(81706), // Rule ID 3599 //
27731 /* 81625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27732 /* 81628 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2pp),
27733 /* 81633 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27734 /* 81636 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27735 /* 81639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27736 /* 81642 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27737 /* 81645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27738 /* 81649 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10773:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27739 /* 81649 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27740 /* 81652 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27741 /* 81656 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27742 /* 81661 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27743 /* 81665 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27744 /* 81670 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27745 /* 81673 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27746 /* 81677 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27747 /* 81682 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27748 /* 81686 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27749 /* 81691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2WPP),
27750 /* 81694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27751 /* 81696 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27752 /* 81698 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27753 /* 81701 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27754 /* 81704 */ GIR_RootConstrainSelectedInstOperands,
27755 /* 81705 */ // GIR_Coverage, 3599,
27756 /* 81705 */ GIR_EraseRootFromParent_Done,
27757 /* 81706 */ // Label 1322: @81706
27758 /* 81706 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(81792), // Rule ID 3600 //
27759 /* 81711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA),
27760 /* 81714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4spp),
27761 /* 81719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27762 /* 81722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
27763 /* 81725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27764 /* 81728 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27765 /* 81731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27766 /* 81735 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10780:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4WSPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }))
27767 /* 81735 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27768 /* 81738 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27769 /* 81742 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27770 /* 81747 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
27771 /* 81751 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27772 /* 81756 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27773 /* 81759 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27774 /* 81763 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27775 /* 81768 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
27776 /* 81772 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27777 /* 81777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4WSPP),
27778 /* 81780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27779 /* 81782 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
27780 /* 81784 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27781 /* 81787 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27782 /* 81790 */ GIR_RootConstrainSelectedInstOperands,
27783 /* 81791 */ // GIR_Coverage, 3600,
27784 /* 81791 */ GIR_EraseRootFromParent_Done,
27785 /* 81792 */ // Label 1323: @81792
27786 /* 81792 */ GIM_Reject,
27787 /* 81793 */ // Label 1200: @81793
27788 /* 81793 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(82417),
27789 /* 81798 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
27790 /* 81801 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(81920), // Rule ID 3612 //
27791 /* 81806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
27792 /* 81809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32ger),
27793 /* 81814 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27794 /* 81817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27795 /* 81820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27796 /* 81823 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27797 /* 81826 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
27798 /* 81829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27799 /* 81833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27800 /* 81837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27801 /* 81841 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
27802 /* 81845 */ // MIs[1] Operand 1
27803 /* 81845 */ // No operand predicates
27804 /* 81845 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
27805 /* 81849 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27806 /* 81853 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
27807 /* 81857 */ // MIs[2] Operand 1
27808 /* 81857 */ // No operand predicates
27809 /* 81857 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
27810 /* 81859 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10733:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GER:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
27811 /* 81859 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27812 /* 81862 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27813 /* 81866 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27814 /* 81871 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
27815 /* 81875 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27816 /* 81880 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27817 /* 81883 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27818 /* 81887 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27819 /* 81892 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
27820 /* 81896 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27821 /* 81901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GER),
27822 /* 81904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27823 /* 81906 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27824 /* 81909 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27825 /* 81912 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
27826 /* 81915 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
27827 /* 81918 */ GIR_RootConstrainSelectedInstOperands,
27828 /* 81919 */ // GIR_Coverage, 3612,
27829 /* 81919 */ GIR_EraseRootFromParent_Done,
27830 /* 81920 */ // Label 1325: @81920
27831 /* 81920 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(82017), // Rule ID 3617 //
27832 /* 81925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
27833 /* 81928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64ger),
27834 /* 81933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27835 /* 81936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
27836 /* 81939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27837 /* 81942 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27838 /* 81945 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
27839 /* 81948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
27840 /* 81952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27841 /* 81956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27842 /* 81960 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
27843 /* 81964 */ // MIs[1] Operand 1
27844 /* 81964 */ // No operand predicates
27845 /* 81964 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
27846 /* 81968 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27847 /* 81972 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
27848 /* 81976 */ // MIs[2] Operand 1
27849 /* 81976 */ // No operand predicates
27850 /* 81976 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
27851 /* 81978 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10738:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GER:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
27852 /* 81978 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27853 /* 81981 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27854 /* 81985 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27855 /* 81990 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
27856 /* 81994 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27857 /* 81999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GER),
27858 /* 82002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27859 /* 82004 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
27860 /* 82006 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27861 /* 82009 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
27862 /* 82012 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
27863 /* 82015 */ GIR_RootConstrainSelectedInstOperands,
27864 /* 82016 */ // GIR_Coverage, 3617,
27865 /* 82016 */ GIR_EraseRootFromParent_Done,
27866 /* 82017 */ // Label 1326: @82017
27867 /* 82017 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(82136), // Rule ID 3641 //
27868 /* 82022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
27869 /* 82025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32ger),
27870 /* 82030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27871 /* 82033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27872 /* 82036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27873 /* 82039 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27874 /* 82042 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
27875 /* 82045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27876 /* 82049 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27877 /* 82053 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27878 /* 82057 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
27879 /* 82061 */ // MIs[1] Operand 1
27880 /* 82061 */ // No operand predicates
27881 /* 82061 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
27882 /* 82065 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27883 /* 82069 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
27884 /* 82073 */ // MIs[2] Operand 1
27885 /* 82073 */ // No operand predicates
27886 /* 82073 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
27887 /* 82075 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10733:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
27888 /* 82075 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27889 /* 82078 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27890 /* 82082 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27891 /* 82087 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
27892 /* 82091 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27893 /* 82096 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27894 /* 82099 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27895 /* 82103 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27896 /* 82108 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
27897 /* 82112 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27898 /* 82117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERW),
27899 /* 82120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27900 /* 82122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27901 /* 82125 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
27902 /* 82128 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
27903 /* 82131 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
27904 /* 82134 */ GIR_RootConstrainSelectedInstOperands,
27905 /* 82135 */ // GIR_Coverage, 3641,
27906 /* 82135 */ GIR_EraseRootFromParent_Done,
27907 /* 82136 */ // Label 1327: @82136
27908 /* 82136 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(82233), // Rule ID 3646 //
27909 /* 82141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
27910 /* 82144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64ger),
27911 /* 82149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
27912 /* 82152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
27913 /* 82155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27914 /* 82158 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27915 /* 82161 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
27916 /* 82164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
27917 /* 82168 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27918 /* 82172 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27919 /* 82176 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
27920 /* 82180 */ // MIs[1] Operand 1
27921 /* 82180 */ // No operand predicates
27922 /* 82180 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
27923 /* 82184 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27924 /* 82188 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
27925 /* 82192 */ // MIs[2] Operand 1
27926 /* 82192 */ // No operand predicates
27927 /* 82192 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
27928 /* 82194 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10738:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERW:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
27929 /* 82194 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27930 /* 82197 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27931 /* 82201 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27932 /* 82206 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
27933 /* 82210 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27934 /* 82215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERW),
27935 /* 82218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
27936 /* 82220 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
27937 /* 82222 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27938 /* 82225 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
27939 /* 82228 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
27940 /* 82231 */ GIR_RootConstrainSelectedInstOperands,
27941 /* 82232 */ // GIR_Coverage, 3646,
27942 /* 82232 */ GIR_EraseRootFromParent_Done,
27943 /* 82233 */ // Label 1328: @82233
27944 /* 82233 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(82280), // Rule ID 1117 //
27945 /* 82238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
27946 /* 82241 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxeval),
27947 /* 82246 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
27948 /* 82249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
27949 /* 82252 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
27950 /* 82255 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
27951 /* 82258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
27952 /* 82262 */ // MIs[0] IMM
27953 /* 82262 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
27954 /* 82265 */ // (intrinsic_wo_chain:{ *:[v2i64] } 10921:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB, v2i64:{ *:[v2i64] }:$XC, (timm:{ *:[i32] }):$IMM) => (XXEVAL:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB, v2i64:{ *:[v2i64] }:$XC, (timm:{ *:[i32] }):$IMM)
27955 /* 82265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL),
27956 /* 82268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
27957 /* 82270 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
27958 /* 82272 */ GIR_RootToRootCopy, /*OpIdx*/3, // XB
27959 /* 82274 */ GIR_RootToRootCopy, /*OpIdx*/4, // XC
27960 /* 82276 */ GIR_RootToRootCopy, /*OpIdx*/5, // IMM
27961 /* 82278 */ GIR_RootConstrainSelectedInstOperands,
27962 /* 82279 */ // GIR_Coverage, 1117,
27963 /* 82279 */ GIR_EraseRootFromParent_Done,
27964 /* 82280 */ // Label 1329: @82280
27965 /* 82280 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(82416), // Rule ID 3431 //
27966 /* 82285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs),
27967 /* 82288 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxpermx),
27968 /* 82293 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27969 /* 82296 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27970 /* 82299 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27971 /* 82302 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27972 /* 82305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
27973 /* 82309 */ // MIs[0] D
27974 /* 82309 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
27975 /* 82312 */ // (intrinsic_wo_chain:{ *:[v16i8] } 10929:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$A, v16i8:{ *:[v16i8] }:$B, v16i8:{ *:[v16i8] }:$C, (timm:{ *:[i32] }):$D) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXPERMX:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$C, VSRC:{ *:[i32] }), ?:{ *:[i32] }:$D), VSRC:{ *:[i32] })
27976 /* 82312 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
27977 /* 82315 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27978 /* 82319 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27979 /* 82324 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C
27980 /* 82328 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27981 /* 82333 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
27982 /* 82336 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27983 /* 82340 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27984 /* 82345 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B
27985 /* 82349 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27986 /* 82354 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27987 /* 82357 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27988 /* 82361 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27989 /* 82366 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A
27990 /* 82370 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
27991 /* 82375 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27992 /* 82378 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMX),
27993 /* 82382 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27994 /* 82387 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
27995 /* 82390 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
27996 /* 82393 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
27997 /* 82396 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // D
27998 /* 82400 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27999 /* 82402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28000 /* 82405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28001 /* 82407 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28002 /* 82410 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28003 /* 82415 */ // GIR_Coverage, 3431,
28004 /* 82415 */ GIR_EraseRootFromParent_Done,
28005 /* 82416 */ // Label 1330: @82416
28006 /* 82416 */ GIM_Reject,
28007 /* 82417 */ // Label 1324: @82417
28008 /* 82417 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(86297),
28009 /* 82422 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
28010 /* 82425 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(82540), // Rule ID 3529 //
28011 /* 82430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28012 /* 82433 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvi8gerx4),
28013 /* 82438 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
28014 /* 82441 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
28015 /* 82444 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28016 /* 82447 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28017 /* 82450 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28018 /* 82453 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28019 /* 82456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
28020 /* 82460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28021 /* 82464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28022 /* 82468 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
28023 /* 82472 */ // MIs[1] Operand 1
28024 /* 82472 */ // No operand predicates
28025 /* 82472 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28026 /* 82476 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28027 /* 82480 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28028 /* 82484 */ // MIs[2] Operand 1
28029 /* 82484 */ // No operand predicates
28030 /* 82484 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28031 /* 82488 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28032 /* 82492 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28033 /* 82496 */ // MIs[3] Operand 1
28034 /* 82496 */ // No operand predicates
28035 /* 82496 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28036 /* 82498 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10720:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMDMXVI8GERX4:{ *:[v1024i1] } ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK)
28037 /* 82498 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28038 /* 82501 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28039 /* 82505 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28040 /* 82510 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
28041 /* 82514 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28042 /* 82519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVI8GERX4),
28043 /* 82522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28044 /* 82524 */ GIR_RootToRootCopy, /*OpIdx*/2, // XAp
28045 /* 82526 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28046 /* 82529 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28047 /* 82532 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28048 /* 82535 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28049 /* 82538 */ GIR_RootConstrainSelectedInstOperands,
28050 /* 82539 */ // GIR_Coverage, 3529,
28051 /* 82539 */ GIR_EraseRootFromParent_Done,
28052 /* 82540 */ // Label 1332: @82540
28053 /* 82540 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(82655), // Rule ID 3532 //
28054 /* 82545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28055 /* 82548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvbf16gerx2),
28056 /* 82553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
28057 /* 82556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
28058 /* 82559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28059 /* 82562 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28060 /* 82565 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28061 /* 82568 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28062 /* 82571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
28063 /* 82575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28064 /* 82579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28065 /* 82583 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
28066 /* 82587 */ // MIs[1] Operand 1
28067 /* 82587 */ // No operand predicates
28068 /* 82587 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28069 /* 82591 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28070 /* 82595 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28071 /* 82599 */ // MIs[2] Operand 1
28072 /* 82599 */ // No operand predicates
28073 /* 82599 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28074 /* 82603 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28075 /* 82607 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28076 /* 82611 */ // MIs[3] Operand 1
28077 /* 82611 */ // No operand predicates
28078 /* 82611 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28079 /* 82613 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10710:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVBF16GERX2:{ *:[v1024i1] } ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28080 /* 82613 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28081 /* 82616 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28082 /* 82620 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28083 /* 82625 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
28084 /* 82629 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28085 /* 82634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVBF16GERX2),
28086 /* 82637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28087 /* 82639 */ GIR_RootToRootCopy, /*OpIdx*/2, // XAp
28088 /* 82641 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28089 /* 82644 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28090 /* 82647 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28091 /* 82650 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28092 /* 82653 */ GIR_RootConstrainSelectedInstOperands,
28093 /* 82654 */ // GIR_Coverage, 3532,
28094 /* 82654 */ GIR_EraseRootFromParent_Done,
28095 /* 82655 */ // Label 1333: @82655
28096 /* 82655 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(82770), // Rule ID 3537 //
28097 /* 82660 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28098 /* 82663 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvf16gerx2),
28099 /* 82668 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
28100 /* 82671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1,
28101 /* 82674 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28102 /* 82677 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28103 /* 82680 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28104 /* 82683 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28105 /* 82686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
28106 /* 82690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28107 /* 82694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28108 /* 82698 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
28109 /* 82702 */ // MIs[1] Operand 1
28110 /* 82702 */ // No operand predicates
28111 /* 82702 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28112 /* 82706 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28113 /* 82710 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28114 /* 82714 */ // MIs[2] Operand 1
28115 /* 82714 */ // No operand predicates
28116 /* 82714 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28117 /* 82718 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28118 /* 82722 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28119 /* 82726 */ // MIs[3] Operand 1
28120 /* 82726 */ // No operand predicates
28121 /* 82726 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28122 /* 82728 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10715:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVF16GERX2:{ *:[v1024i1] } ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28123 /* 82728 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28124 /* 82731 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28125 /* 82735 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28126 /* 82740 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
28127 /* 82744 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28128 /* 82749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVF16GERX2),
28129 /* 82752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28130 /* 82754 */ GIR_RootToRootCopy, /*OpIdx*/2, // XAp
28131 /* 82756 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28132 /* 82759 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28133 /* 82762 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28134 /* 82765 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28135 /* 82768 */ GIR_RootConstrainSelectedInstOperands,
28136 /* 82769 */ // GIR_Coverage, 3537,
28137 /* 82769 */ GIR_EraseRootFromParent_Done,
28138 /* 82770 */ // Label 1334: @82770
28139 /* 82770 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(82907), // Rule ID 3601 //
28140 /* 82775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28141 /* 82778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8),
28142 /* 82783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28143 /* 82786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28144 /* 82789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28145 /* 82792 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28146 /* 82795 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28147 /* 82798 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28148 /* 82801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28149 /* 82805 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28150 /* 82809 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28151 /* 82813 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28152 /* 82817 */ // MIs[1] Operand 1
28153 /* 82817 */ // No operand predicates
28154 /* 82817 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28155 /* 82821 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28156 /* 82825 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28157 /* 82829 */ // MIs[2] Operand 1
28158 /* 82829 */ // No operand predicates
28159 /* 82829 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28160 /* 82833 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28161 /* 82837 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
28162 /* 82841 */ // MIs[3] Operand 1
28163 /* 82841 */ // No operand predicates
28164 /* 82841 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28165 /* 82843 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10747:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK)
28166 /* 82843 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28167 /* 82846 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28168 /* 82850 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28169 /* 82855 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28170 /* 82859 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28171 /* 82864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28172 /* 82867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28173 /* 82871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28174 /* 82876 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28175 /* 82880 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28176 /* 82885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8),
28177 /* 82888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28178 /* 82890 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28179 /* 82893 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28180 /* 82896 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28181 /* 82899 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28182 /* 82902 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28183 /* 82905 */ GIR_RootConstrainSelectedInstOperands,
28184 /* 82906 */ // GIR_Coverage, 3601,
28185 /* 82906 */ GIR_EraseRootFromParent_Done,
28186 /* 82907 */ // Label 1335: @82907
28187 /* 82907 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(83044), // Rule ID 3603 //
28188 /* 82912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28189 /* 82915 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4),
28190 /* 82920 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28191 /* 82923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28192 /* 82926 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28193 /* 82929 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28194 /* 82932 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28195 /* 82935 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28196 /* 82938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28197 /* 82942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28198 /* 82946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28199 /* 82950 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28200 /* 82954 */ // MIs[1] Operand 1
28201 /* 82954 */ // No operand predicates
28202 /* 82954 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28203 /* 82958 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28204 /* 82962 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28205 /* 82966 */ // MIs[2] Operand 1
28206 /* 82966 */ // No operand predicates
28207 /* 82966 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28208 /* 82970 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28209 /* 82974 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28210 /* 82978 */ // MIs[3] Operand 1
28211 /* 82978 */ // No operand predicates
28212 /* 82978 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28213 /* 82980 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10749:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK)
28214 /* 82980 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28215 /* 82983 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28216 /* 82987 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28217 /* 82992 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28218 /* 82996 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28219 /* 83001 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28220 /* 83004 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28221 /* 83008 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28222 /* 83013 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28223 /* 83017 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28224 /* 83022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4),
28225 /* 83025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28226 /* 83027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28227 /* 83030 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28228 /* 83033 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28229 /* 83036 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28230 /* 83039 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28231 /* 83042 */ GIR_RootConstrainSelectedInstOperands,
28232 /* 83043 */ // GIR_Coverage, 3603,
28233 /* 83043 */ GIR_EraseRootFromParent_Done,
28234 /* 83044 */ // Label 1336: @83044
28235 /* 83044 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(83181), // Rule ID 3605 //
28236 /* 83049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28237 /* 83052 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2s),
28238 /* 83057 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28239 /* 83060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28240 /* 83063 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28241 /* 83066 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28242 /* 83069 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28243 /* 83072 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28244 /* 83075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28245 /* 83079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28246 /* 83083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28247 /* 83087 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28248 /* 83091 */ // MIs[1] Operand 1
28249 /* 83091 */ // No operand predicates
28250 /* 83091 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28251 /* 83095 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28252 /* 83099 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28253 /* 83103 */ // MIs[2] Operand 1
28254 /* 83103 */ // No operand predicates
28255 /* 83103 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28256 /* 83107 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28257 /* 83111 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28258 /* 83115 */ // MIs[3] Operand 1
28259 /* 83115 */ // No operand predicates
28260 /* 83115 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28261 /* 83117 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10745:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2S:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28262 /* 83117 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28263 /* 83120 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28264 /* 83124 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28265 /* 83129 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28266 /* 83133 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28267 /* 83138 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28268 /* 83141 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28269 /* 83145 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28270 /* 83150 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28271 /* 83154 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28272 /* 83159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2S),
28273 /* 83162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28274 /* 83164 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28275 /* 83167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28276 /* 83170 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28277 /* 83173 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28278 /* 83176 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28279 /* 83179 */ GIR_RootConstrainSelectedInstOperands,
28280 /* 83180 */ // GIR_Coverage, 3605,
28281 /* 83180 */ GIR_EraseRootFromParent_Done,
28282 /* 83181 */ // Label 1337: @83181
28283 /* 83181 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(83318), // Rule ID 3607 //
28284 /* 83186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28285 /* 83189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2),
28286 /* 83194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28287 /* 83197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28288 /* 83200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28289 /* 83203 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28290 /* 83206 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28291 /* 83209 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28292 /* 83212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28293 /* 83216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28294 /* 83220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28295 /* 83224 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28296 /* 83228 */ // MIs[1] Operand 1
28297 /* 83228 */ // No operand predicates
28298 /* 83228 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28299 /* 83232 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28300 /* 83236 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28301 /* 83240 */ // MIs[2] Operand 1
28302 /* 83240 */ // No operand predicates
28303 /* 83240 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28304 /* 83244 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28305 /* 83248 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28306 /* 83252 */ // MIs[3] Operand 1
28307 /* 83252 */ // No operand predicates
28308 /* 83252 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28309 /* 83254 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10728:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28310 /* 83254 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28311 /* 83257 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28312 /* 83261 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28313 /* 83266 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28314 /* 83270 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28315 /* 83275 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28316 /* 83278 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28317 /* 83282 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28318 /* 83287 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28319 /* 83291 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28320 /* 83296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2),
28321 /* 83299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28322 /* 83301 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28323 /* 83304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28324 /* 83307 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28325 /* 83310 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28326 /* 83313 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28327 /* 83316 */ GIR_RootConstrainSelectedInstOperands,
28328 /* 83317 */ // GIR_Coverage, 3607,
28329 /* 83317 */ GIR_EraseRootFromParent_Done,
28330 /* 83318 */ // Label 1338: @83318
28331 /* 83318 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(83455), // Rule ID 3622 //
28332 /* 83323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28333 /* 83326 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2),
28334 /* 83331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28335 /* 83334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28336 /* 83337 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28337 /* 83340 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28338 /* 83343 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28339 /* 83346 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28340 /* 83349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28341 /* 83353 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28342 /* 83357 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28343 /* 83361 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28344 /* 83365 */ // MIs[1] Operand 1
28345 /* 83365 */ // No operand predicates
28346 /* 83365 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28347 /* 83369 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28348 /* 83373 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28349 /* 83377 */ // MIs[2] Operand 1
28350 /* 83377 */ // No operand predicates
28351 /* 83377 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28352 /* 83381 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28353 /* 83385 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28354 /* 83389 */ // MIs[3] Operand 1
28355 /* 83389 */ // No operand predicates
28356 /* 83389 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28357 /* 83391 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10723:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28358 /* 83391 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28359 /* 83394 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28360 /* 83398 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28361 /* 83403 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28362 /* 83407 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28363 /* 83412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28364 /* 83415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28365 /* 83419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28366 /* 83424 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28367 /* 83428 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28368 /* 83433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2),
28369 /* 83436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28370 /* 83438 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28371 /* 83441 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28372 /* 83444 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28373 /* 83447 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28374 /* 83450 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28375 /* 83453 */ GIR_RootConstrainSelectedInstOperands,
28376 /* 83454 */ // GIR_Coverage, 3622,
28377 /* 83454 */ GIR_EraseRootFromParent_Done,
28378 /* 83455 */ // Label 1339: @83455
28379 /* 83455 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(83592), // Rule ID 3627 //
28380 /* 83460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28381 /* 83463 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2),
28382 /* 83468 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28383 /* 83471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28384 /* 83474 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28385 /* 83477 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28386 /* 83480 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28387 /* 83483 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28388 /* 83486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28389 /* 83490 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28390 /* 83494 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28391 /* 83498 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28392 /* 83502 */ // MIs[1] Operand 1
28393 /* 83502 */ // No operand predicates
28394 /* 83502 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28395 /* 83506 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28396 /* 83510 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28397 /* 83514 */ // MIs[2] Operand 1
28398 /* 83514 */ // No operand predicates
28399 /* 83514 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28400 /* 83518 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28401 /* 83522 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28402 /* 83526 */ // MIs[3] Operand 1
28403 /* 83526 */ // No operand predicates
28404 /* 83526 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28405 /* 83528 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10743:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28406 /* 83528 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28407 /* 83531 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28408 /* 83535 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28409 /* 83540 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28410 /* 83544 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28411 /* 83549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28412 /* 83552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28413 /* 83556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28414 /* 83561 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28415 /* 83565 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28416 /* 83570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2),
28417 /* 83573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28418 /* 83575 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28419 /* 83578 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28420 /* 83581 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28421 /* 83584 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28422 /* 83587 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28423 /* 83590 */ GIR_RootConstrainSelectedInstOperands,
28424 /* 83591 */ // GIR_Coverage, 3627,
28425 /* 83591 */ GIR_EraseRootFromParent_Done,
28426 /* 83592 */ // Label 1340: @83592
28427 /* 83592 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(83729), // Rule ID 3630 //
28428 /* 83597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28429 /* 83600 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8),
28430 /* 83605 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28431 /* 83608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28432 /* 83611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28433 /* 83614 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28434 /* 83617 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28435 /* 83620 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28436 /* 83623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
28437 /* 83627 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28438 /* 83631 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28439 /* 83635 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28440 /* 83639 */ // MIs[1] Operand 1
28441 /* 83639 */ // No operand predicates
28442 /* 83639 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28443 /* 83643 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28444 /* 83647 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28445 /* 83651 */ // MIs[2] Operand 1
28446 /* 83651 */ // No operand predicates
28447 /* 83651 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28448 /* 83655 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28449 /* 83659 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
28450 /* 83663 */ // MIs[3] Operand 1
28451 /* 83663 */ // No operand predicates
28452 /* 83663 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28453 /* 83665 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10747:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK)
28454 /* 83665 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28455 /* 83668 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28456 /* 83672 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28457 /* 83677 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28458 /* 83681 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28459 /* 83686 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28460 /* 83689 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28461 /* 83693 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28462 /* 83698 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28463 /* 83702 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28464 /* 83707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8W),
28465 /* 83710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28466 /* 83712 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28467 /* 83715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28468 /* 83718 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28469 /* 83721 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28470 /* 83724 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28471 /* 83727 */ GIR_RootConstrainSelectedInstOperands,
28472 /* 83728 */ // GIR_Coverage, 3630,
28473 /* 83728 */ GIR_EraseRootFromParent_Done,
28474 /* 83729 */ // Label 1341: @83729
28475 /* 83729 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(83866), // Rule ID 3632 //
28476 /* 83734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28477 /* 83737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4),
28478 /* 83742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28479 /* 83745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28480 /* 83748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28481 /* 83751 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28482 /* 83754 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28483 /* 83757 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28484 /* 83760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
28485 /* 83764 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28486 /* 83768 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28487 /* 83772 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28488 /* 83776 */ // MIs[1] Operand 1
28489 /* 83776 */ // No operand predicates
28490 /* 83776 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28491 /* 83780 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28492 /* 83784 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28493 /* 83788 */ // MIs[2] Operand 1
28494 /* 83788 */ // No operand predicates
28495 /* 83788 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28496 /* 83792 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28497 /* 83796 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28498 /* 83800 */ // MIs[3] Operand 1
28499 /* 83800 */ // No operand predicates
28500 /* 83800 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28501 /* 83802 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10749:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK)
28502 /* 83802 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28503 /* 83805 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28504 /* 83809 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28505 /* 83814 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28506 /* 83818 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28507 /* 83823 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28508 /* 83826 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28509 /* 83830 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28510 /* 83835 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28511 /* 83839 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28512 /* 83844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4W),
28513 /* 83847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28514 /* 83849 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28515 /* 83852 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28516 /* 83855 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28517 /* 83858 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28518 /* 83861 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28519 /* 83864 */ GIR_RootConstrainSelectedInstOperands,
28520 /* 83865 */ // GIR_Coverage, 3632,
28521 /* 83865 */ GIR_EraseRootFromParent_Done,
28522 /* 83866 */ // Label 1342: @83866
28523 /* 83866 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(84003), // Rule ID 3634 //
28524 /* 83871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28525 /* 83874 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2s),
28526 /* 83879 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28527 /* 83882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28528 /* 83885 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28529 /* 83888 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28530 /* 83891 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28531 /* 83894 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28532 /* 83897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
28533 /* 83901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28534 /* 83905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28535 /* 83909 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28536 /* 83913 */ // MIs[1] Operand 1
28537 /* 83913 */ // No operand predicates
28538 /* 83913 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28539 /* 83917 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28540 /* 83921 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28541 /* 83925 */ // MIs[2] Operand 1
28542 /* 83925 */ // No operand predicates
28543 /* 83925 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28544 /* 83929 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28545 /* 83933 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28546 /* 83937 */ // MIs[3] Operand 1
28547 /* 83937 */ // No operand predicates
28548 /* 83937 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28549 /* 83939 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10745:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28550 /* 83939 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28551 /* 83942 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28552 /* 83946 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28553 /* 83951 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28554 /* 83955 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28555 /* 83960 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28556 /* 83963 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28557 /* 83967 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28558 /* 83972 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28559 /* 83976 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28560 /* 83981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SW),
28561 /* 83984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28562 /* 83986 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28563 /* 83989 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28564 /* 83992 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28565 /* 83995 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28566 /* 83998 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28567 /* 84001 */ GIR_RootConstrainSelectedInstOperands,
28568 /* 84002 */ // GIR_Coverage, 3634,
28569 /* 84002 */ GIR_EraseRootFromParent_Done,
28570 /* 84003 */ // Label 1343: @84003
28571 /* 84003 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(84140), // Rule ID 3636 //
28572 /* 84008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28573 /* 84011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2),
28574 /* 84016 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28575 /* 84019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28576 /* 84022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28577 /* 84025 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28578 /* 84028 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28579 /* 84031 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28580 /* 84034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
28581 /* 84038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28582 /* 84042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28583 /* 84046 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28584 /* 84050 */ // MIs[1] Operand 1
28585 /* 84050 */ // No operand predicates
28586 /* 84050 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28587 /* 84054 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28588 /* 84058 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28589 /* 84062 */ // MIs[2] Operand 1
28590 /* 84062 */ // No operand predicates
28591 /* 84062 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28592 /* 84066 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28593 /* 84070 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28594 /* 84074 */ // MIs[3] Operand 1
28595 /* 84074 */ // No operand predicates
28596 /* 84074 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28597 /* 84076 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10728:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28598 /* 84076 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28599 /* 84079 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28600 /* 84083 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28601 /* 84088 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28602 /* 84092 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28603 /* 84097 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28604 /* 84100 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28605 /* 84104 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28606 /* 84109 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28607 /* 84113 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28608 /* 84118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2W),
28609 /* 84121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28610 /* 84123 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28611 /* 84126 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28612 /* 84129 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28613 /* 84132 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28614 /* 84135 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28615 /* 84138 */ GIR_RootConstrainSelectedInstOperands,
28616 /* 84139 */ // GIR_Coverage, 3636,
28617 /* 84139 */ GIR_EraseRootFromParent_Done,
28618 /* 84140 */ // Label 1344: @84140
28619 /* 84140 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(84277), // Rule ID 3651 //
28620 /* 84145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28621 /* 84148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2),
28622 /* 84153 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28623 /* 84156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28624 /* 84159 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28625 /* 84162 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28626 /* 84165 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28627 /* 84168 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28628 /* 84171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
28629 /* 84175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28630 /* 84179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28631 /* 84183 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28632 /* 84187 */ // MIs[1] Operand 1
28633 /* 84187 */ // No operand predicates
28634 /* 84187 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28635 /* 84191 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28636 /* 84195 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28637 /* 84199 */ // MIs[2] Operand 1
28638 /* 84199 */ // No operand predicates
28639 /* 84199 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28640 /* 84203 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28641 /* 84207 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28642 /* 84211 */ // MIs[3] Operand 1
28643 /* 84211 */ // No operand predicates
28644 /* 84211 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28645 /* 84213 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10723:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28646 /* 84213 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28647 /* 84216 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28648 /* 84220 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28649 /* 84225 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28650 /* 84229 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28651 /* 84234 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28652 /* 84237 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28653 /* 84241 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28654 /* 84246 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28655 /* 84250 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28656 /* 84255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2W),
28657 /* 84258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28658 /* 84260 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28659 /* 84263 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28660 /* 84266 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28661 /* 84269 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28662 /* 84272 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28663 /* 84275 */ GIR_RootConstrainSelectedInstOperands,
28664 /* 84276 */ // GIR_Coverage, 3651,
28665 /* 84276 */ GIR_EraseRootFromParent_Done,
28666 /* 84277 */ // Label 1345: @84277
28667 /* 84277 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(84414), // Rule ID 3656 //
28668 /* 84282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
28669 /* 84285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2),
28670 /* 84290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28671 /* 84293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28672 /* 84296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28673 /* 84299 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28674 /* 84302 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28675 /* 84305 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28676 /* 84308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
28677 /* 84312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
28678 /* 84316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28679 /* 84320 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28680 /* 84324 */ // MIs[1] Operand 1
28681 /* 84324 */ // No operand predicates
28682 /* 84324 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
28683 /* 84328 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28684 /* 84332 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28685 /* 84336 */ // MIs[2] Operand 1
28686 /* 84336 */ // No operand predicates
28687 /* 84336 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3]
28688 /* 84340 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28689 /* 84344 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28690 /* 84348 */ // MIs[3] Operand 1
28691 /* 84348 */ // No operand predicates
28692 /* 84348 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
28693 /* 84350 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10743:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
28694 /* 84350 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28695 /* 84353 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28696 /* 84357 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28697 /* 84362 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB
28698 /* 84366 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28699 /* 84371 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28700 /* 84374 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28701 /* 84378 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28702 /* 84383 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA
28703 /* 84387 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28704 /* 84392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2W),
28705 /* 84395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28706 /* 84397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28707 /* 84400 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28708 /* 84403 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28709 /* 84406 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28710 /* 84409 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
28711 /* 84412 */ GIR_RootConstrainSelectedInstOperands,
28712 /* 84413 */ // GIR_Coverage, 3656,
28713 /* 84413 */ GIR_EraseRootFromParent_Done,
28714 /* 84414 */ // Label 1346: @84414
28715 /* 84414 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(84488), // Rule ID 3542 //
28716 /* 84419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture),
28717 /* 84422 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_dmxxshapad),
28718 /* 84427 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
28719 /* 84430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
28720 /* 84433 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28721 /* 84436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
28722 /* 84440 */ // MIs[0] ID
28723 /* 84440 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
28724 /* 84443 */ // MIs[0] E
28725 /* 84443 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
28726 /* 84446 */ // MIs[0] BL
28727 /* 84446 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
28728 /* 84449 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10709:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v16i8:{ *:[v16i8] }:$XB, (timm:{ *:[i32] }):$ID, (timm:{ *:[i32] }):$E, (timm:{ *:[i32] }):$BL) => (DMXXSHAPAD:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), ?:{ *:[i32] }:$ID, ?:{ *:[i32] }:$E, ?:{ *:[i32] }:$BL)
28729 /* 84449 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28730 /* 84452 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28731 /* 84456 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28732 /* 84461 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB
28733 /* 84465 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28734 /* 84470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DMXXSHAPAD),
28735 /* 84473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28736 /* 84475 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
28737 /* 84477 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28738 /* 84480 */ GIR_RootToRootCopy, /*OpIdx*/4, // ID
28739 /* 84482 */ GIR_RootToRootCopy, /*OpIdx*/5, // E
28740 /* 84484 */ GIR_RootToRootCopy, /*OpIdx*/6, // BL
28741 /* 84486 */ GIR_RootConstrainSelectedInstOperands,
28742 /* 84487 */ // GIR_Coverage, 3542,
28743 /* 84487 */ GIR_EraseRootFromParent_Done,
28744 /* 84488 */ // Label 1347: @84488
28745 /* 84488 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(84612), // Rule ID 3613 //
28746 /* 84493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28747 /* 84496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpp),
28748 /* 84501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28749 /* 84504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
28750 /* 84507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28751 /* 84510 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28752 /* 84513 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28753 /* 84516 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28754 /* 84519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28755 /* 84523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
28756 /* 84527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28757 /* 84531 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28758 /* 84535 */ // MIs[1] Operand 1
28759 /* 84535 */ // No operand predicates
28760 /* 84535 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
28761 /* 84539 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28762 /* 84543 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28763 /* 84547 */ // MIs[2] Operand 1
28764 /* 84547 */ // No operand predicates
28765 /* 84547 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
28766 /* 84549 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10737:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
28767 /* 84549 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28768 /* 84552 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28769 /* 84556 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28770 /* 84561 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
28771 /* 84565 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28772 /* 84570 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28773 /* 84573 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28774 /* 84577 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28775 /* 84582 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
28776 /* 84586 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28777 /* 84591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERPP),
28778 /* 84594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28779 /* 84596 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
28780 /* 84598 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28781 /* 84601 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28782 /* 84604 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28783 /* 84607 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28784 /* 84610 */ GIR_RootConstrainSelectedInstOperands,
28785 /* 84611 */ // GIR_Coverage, 3613,
28786 /* 84611 */ GIR_EraseRootFromParent_Done,
28787 /* 84612 */ // Label 1348: @84612
28788 /* 84612 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(84736), // Rule ID 3614 //
28789 /* 84617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28790 /* 84620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpn),
28791 /* 84625 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28792 /* 84628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
28793 /* 84631 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28794 /* 84634 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28795 /* 84637 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28796 /* 84640 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28797 /* 84643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28798 /* 84647 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
28799 /* 84651 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28800 /* 84655 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28801 /* 84659 */ // MIs[1] Operand 1
28802 /* 84659 */ // No operand predicates
28803 /* 84659 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
28804 /* 84663 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28805 /* 84667 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28806 /* 84671 */ // MIs[2] Operand 1
28807 /* 84671 */ // No operand predicates
28808 /* 84671 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
28809 /* 84673 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10736:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
28810 /* 84673 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28811 /* 84676 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28812 /* 84680 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28813 /* 84685 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
28814 /* 84689 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28815 /* 84694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28816 /* 84697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28817 /* 84701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28818 /* 84706 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
28819 /* 84710 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28820 /* 84715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERPN),
28821 /* 84718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28822 /* 84720 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
28823 /* 84722 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28824 /* 84725 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28825 /* 84728 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28826 /* 84731 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28827 /* 84734 */ GIR_RootConstrainSelectedInstOperands,
28828 /* 84735 */ // GIR_Coverage, 3614,
28829 /* 84735 */ GIR_EraseRootFromParent_Done,
28830 /* 84736 */ // Label 1349: @84736
28831 /* 84736 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(84860), // Rule ID 3615 //
28832 /* 84741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28833 /* 84744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernp),
28834 /* 84749 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28835 /* 84752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
28836 /* 84755 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28837 /* 84758 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28838 /* 84761 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28839 /* 84764 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28840 /* 84767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28841 /* 84771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
28842 /* 84775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28843 /* 84779 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28844 /* 84783 */ // MIs[1] Operand 1
28845 /* 84783 */ // No operand predicates
28846 /* 84783 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
28847 /* 84787 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28848 /* 84791 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28849 /* 84795 */ // MIs[2] Operand 1
28850 /* 84795 */ // No operand predicates
28851 /* 84795 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
28852 /* 84797 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10735:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
28853 /* 84797 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28854 /* 84800 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28855 /* 84804 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28856 /* 84809 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
28857 /* 84813 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28858 /* 84818 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28859 /* 84821 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28860 /* 84825 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28861 /* 84830 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
28862 /* 84834 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28863 /* 84839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERNP),
28864 /* 84842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28865 /* 84844 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
28866 /* 84846 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28867 /* 84849 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28868 /* 84852 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28869 /* 84855 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28870 /* 84858 */ GIR_RootConstrainSelectedInstOperands,
28871 /* 84859 */ // GIR_Coverage, 3615,
28872 /* 84859 */ GIR_EraseRootFromParent_Done,
28873 /* 84860 */ // Label 1350: @84860
28874 /* 84860 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(84984), // Rule ID 3616 //
28875 /* 84865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28876 /* 84868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernn),
28877 /* 84873 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28878 /* 84876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
28879 /* 84879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28880 /* 84882 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28881 /* 84885 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28882 /* 84888 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28883 /* 84891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28884 /* 84895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
28885 /* 84899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28886 /* 84903 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28887 /* 84907 */ // MIs[1] Operand 1
28888 /* 84907 */ // No operand predicates
28889 /* 84907 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
28890 /* 84911 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28891 /* 84915 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28892 /* 84919 */ // MIs[2] Operand 1
28893 /* 84919 */ // No operand predicates
28894 /* 84919 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
28895 /* 84921 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10734:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
28896 /* 84921 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
28897 /* 84924 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28898 /* 84928 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28899 /* 84933 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
28900 /* 84937 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28901 /* 84942 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28902 /* 84945 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28903 /* 84949 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28904 /* 84954 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
28905 /* 84958 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28906 /* 84963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERNN),
28907 /* 84966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28908 /* 84968 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
28909 /* 84970 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28910 /* 84973 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
28911 /* 84976 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28912 /* 84979 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28913 /* 84982 */ GIR_RootConstrainSelectedInstOperands,
28914 /* 84983 */ // GIR_Coverage, 3616,
28915 /* 84983 */ GIR_EraseRootFromParent_Done,
28916 /* 84984 */ // Label 1351: @84984
28917 /* 84984 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(85086), // Rule ID 3618 //
28918 /* 84989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28919 /* 84992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpp),
28920 /* 84997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28921 /* 85000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
28922 /* 85003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
28923 /* 85006 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28924 /* 85009 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28925 /* 85012 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28926 /* 85015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28927 /* 85019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
28928 /* 85023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28929 /* 85027 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28930 /* 85031 */ // MIs[1] Operand 1
28931 /* 85031 */ // No operand predicates
28932 /* 85031 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
28933 /* 85035 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28934 /* 85039 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28935 /* 85043 */ // MIs[2] Operand 1
28936 /* 85043 */ // No operand predicates
28937 /* 85043 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
28938 /* 85045 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10742:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
28939 /* 85045 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28940 /* 85048 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28941 /* 85052 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28942 /* 85057 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
28943 /* 85061 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28944 /* 85066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERPP),
28945 /* 85069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28946 /* 85071 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
28947 /* 85073 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
28948 /* 85075 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28949 /* 85078 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28950 /* 85081 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28951 /* 85084 */ GIR_RootConstrainSelectedInstOperands,
28952 /* 85085 */ // GIR_Coverage, 3618,
28953 /* 85085 */ GIR_EraseRootFromParent_Done,
28954 /* 85086 */ // Label 1352: @85086
28955 /* 85086 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(85188), // Rule ID 3619 //
28956 /* 85091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28957 /* 85094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpn),
28958 /* 85099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28959 /* 85102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
28960 /* 85105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
28961 /* 85108 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28962 /* 85111 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28963 /* 85114 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
28964 /* 85117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
28965 /* 85121 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
28966 /* 85125 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28967 /* 85129 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
28968 /* 85133 */ // MIs[1] Operand 1
28969 /* 85133 */ // No operand predicates
28970 /* 85133 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
28971 /* 85137 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28972 /* 85141 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
28973 /* 85145 */ // MIs[2] Operand 1
28974 /* 85145 */ // No operand predicates
28975 /* 85145 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
28976 /* 85147 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10741:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
28977 /* 85147 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28978 /* 85150 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28979 /* 85154 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28980 /* 85159 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
28981 /* 85163 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
28982 /* 85168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERPN),
28983 /* 85171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
28984 /* 85173 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
28985 /* 85175 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
28986 /* 85177 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28987 /* 85180 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
28988 /* 85183 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
28989 /* 85186 */ GIR_RootConstrainSelectedInstOperands,
28990 /* 85187 */ // GIR_Coverage, 3619,
28991 /* 85187 */ GIR_EraseRootFromParent_Done,
28992 /* 85188 */ // Label 1353: @85188
28993 /* 85188 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(85290), // Rule ID 3620 //
28994 /* 85193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
28995 /* 85196 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernp),
28996 /* 85201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
28997 /* 85204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
28998 /* 85207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
28999 /* 85210 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29000 /* 85213 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29001 /* 85216 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29002 /* 85219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
29003 /* 85223 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29004 /* 85227 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29005 /* 85231 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29006 /* 85235 */ // MIs[1] Operand 1
29007 /* 85235 */ // No operand predicates
29008 /* 85235 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29009 /* 85239 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29010 /* 85243 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29011 /* 85247 */ // MIs[2] Operand 1
29012 /* 85247 */ // No operand predicates
29013 /* 85247 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29014 /* 85249 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10740:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
29015 /* 85249 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29016 /* 85252 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29017 /* 85256 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29018 /* 85261 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29019 /* 85265 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29020 /* 85270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERNP),
29021 /* 85273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29022 /* 85275 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29023 /* 85277 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
29024 /* 85279 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29025 /* 85282 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29026 /* 85285 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29027 /* 85288 */ GIR_RootConstrainSelectedInstOperands,
29028 /* 85289 */ // GIR_Coverage, 3620,
29029 /* 85289 */ GIR_EraseRootFromParent_Done,
29030 /* 85290 */ // Label 1354: @85290
29031 /* 85290 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(85392), // Rule ID 3621 //
29032 /* 85295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
29033 /* 85298 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernn),
29034 /* 85303 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29035 /* 85306 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29036 /* 85309 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29037 /* 85312 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29038 /* 85315 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29039 /* 85318 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29040 /* 85321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
29041 /* 85325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29042 /* 85329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29043 /* 85333 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29044 /* 85337 */ // MIs[1] Operand 1
29045 /* 85337 */ // No operand predicates
29046 /* 85337 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29047 /* 85341 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29048 /* 85345 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29049 /* 85349 */ // MIs[2] Operand 1
29050 /* 85349 */ // No operand predicates
29051 /* 85349 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29052 /* 85351 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10739:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
29053 /* 85351 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29054 /* 85354 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29055 /* 85358 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29056 /* 85363 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29057 /* 85367 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29058 /* 85372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERNN),
29059 /* 85375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29060 /* 85377 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29061 /* 85379 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
29062 /* 85381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29063 /* 85384 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29064 /* 85387 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29065 /* 85390 */ GIR_RootConstrainSelectedInstOperands,
29066 /* 85391 */ // GIR_Coverage, 3621,
29067 /* 85391 */ GIR_EraseRootFromParent_Done,
29068 /* 85392 */ // Label 1355: @85392
29069 /* 85392 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(85516), // Rule ID 3642 //
29070 /* 85397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29071 /* 85400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpp),
29072 /* 85405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29073 /* 85408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29074 /* 85411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29075 /* 85414 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29076 /* 85417 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29077 /* 85420 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29078 /* 85423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
29079 /* 85427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29080 /* 85431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29081 /* 85435 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29082 /* 85439 */ // MIs[1] Operand 1
29083 /* 85439 */ // No operand predicates
29084 /* 85439 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29085 /* 85443 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29086 /* 85447 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29087 /* 85451 */ // MIs[2] Operand 1
29088 /* 85451 */ // No operand predicates
29089 /* 85451 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29090 /* 85453 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10737:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
29091 /* 85453 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
29092 /* 85456 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29093 /* 85460 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29094 /* 85465 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
29095 /* 85469 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29096 /* 85474 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29097 /* 85477 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29098 /* 85481 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29099 /* 85486 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
29100 /* 85490 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29101 /* 85495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWPP),
29102 /* 85498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29103 /* 85500 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29104 /* 85502 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29105 /* 85505 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
29106 /* 85508 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29107 /* 85511 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29108 /* 85514 */ GIR_RootConstrainSelectedInstOperands,
29109 /* 85515 */ // GIR_Coverage, 3642,
29110 /* 85515 */ GIR_EraseRootFromParent_Done,
29111 /* 85516 */ // Label 1356: @85516
29112 /* 85516 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(85640), // Rule ID 3643 //
29113 /* 85521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29114 /* 85524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpn),
29115 /* 85529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29116 /* 85532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29117 /* 85535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29118 /* 85538 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29119 /* 85541 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29120 /* 85544 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29121 /* 85547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
29122 /* 85551 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29123 /* 85555 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29124 /* 85559 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29125 /* 85563 */ // MIs[1] Operand 1
29126 /* 85563 */ // No operand predicates
29127 /* 85563 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29128 /* 85567 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29129 /* 85571 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29130 /* 85575 */ // MIs[2] Operand 1
29131 /* 85575 */ // No operand predicates
29132 /* 85575 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29133 /* 85577 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10736:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
29134 /* 85577 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
29135 /* 85580 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29136 /* 85584 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29137 /* 85589 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
29138 /* 85593 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29139 /* 85598 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29140 /* 85601 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29141 /* 85605 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29142 /* 85610 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
29143 /* 85614 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29144 /* 85619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWPN),
29145 /* 85622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29146 /* 85624 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29147 /* 85626 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29148 /* 85629 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
29149 /* 85632 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29150 /* 85635 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29151 /* 85638 */ GIR_RootConstrainSelectedInstOperands,
29152 /* 85639 */ // GIR_Coverage, 3643,
29153 /* 85639 */ GIR_EraseRootFromParent_Done,
29154 /* 85640 */ // Label 1357: @85640
29155 /* 85640 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(85764), // Rule ID 3644 //
29156 /* 85645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29157 /* 85648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernp),
29158 /* 85653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29159 /* 85656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29160 /* 85659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29161 /* 85662 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29162 /* 85665 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29163 /* 85668 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29164 /* 85671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
29165 /* 85675 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29166 /* 85679 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29167 /* 85683 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29168 /* 85687 */ // MIs[1] Operand 1
29169 /* 85687 */ // No operand predicates
29170 /* 85687 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29171 /* 85691 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29172 /* 85695 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29173 /* 85699 */ // MIs[2] Operand 1
29174 /* 85699 */ // No operand predicates
29175 /* 85699 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29176 /* 85701 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10735:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
29177 /* 85701 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
29178 /* 85704 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29179 /* 85708 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29180 /* 85713 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
29181 /* 85717 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29182 /* 85722 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29183 /* 85725 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29184 /* 85729 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29185 /* 85734 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
29186 /* 85738 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29187 /* 85743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWNP),
29188 /* 85746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29189 /* 85748 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29190 /* 85750 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29191 /* 85753 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
29192 /* 85756 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29193 /* 85759 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29194 /* 85762 */ GIR_RootConstrainSelectedInstOperands,
29195 /* 85763 */ // GIR_Coverage, 3644,
29196 /* 85763 */ GIR_EraseRootFromParent_Done,
29197 /* 85764 */ // Label 1358: @85764
29198 /* 85764 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(85888), // Rule ID 3645 //
29199 /* 85769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29200 /* 85772 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernn),
29201 /* 85777 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29202 /* 85780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29203 /* 85783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29204 /* 85786 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29205 /* 85789 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29206 /* 85792 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29207 /* 85795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
29208 /* 85799 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29209 /* 85803 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29210 /* 85807 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29211 /* 85811 */ // MIs[1] Operand 1
29212 /* 85811 */ // No operand predicates
29213 /* 85811 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29214 /* 85815 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29215 /* 85819 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29216 /* 85823 */ // MIs[2] Operand 1
29217 /* 85823 */ // No operand predicates
29218 /* 85823 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29219 /* 85825 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10734:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK)
29220 /* 85825 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
29221 /* 85828 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29222 /* 85832 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29223 /* 85837 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
29224 /* 85841 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29225 /* 85846 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29226 /* 85849 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29227 /* 85853 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29228 /* 85858 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
29229 /* 85862 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29230 /* 85867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWNN),
29231 /* 85870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29232 /* 85872 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29233 /* 85874 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29234 /* 85877 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
29235 /* 85880 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29236 /* 85883 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29237 /* 85886 */ GIR_RootConstrainSelectedInstOperands,
29238 /* 85887 */ // GIR_Coverage, 3645,
29239 /* 85887 */ GIR_EraseRootFromParent_Done,
29240 /* 85888 */ // Label 1359: @85888
29241 /* 85888 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(85990), // Rule ID 3647 //
29242 /* 85893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29243 /* 85896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpp),
29244 /* 85901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29245 /* 85904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29246 /* 85907 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29247 /* 85910 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29248 /* 85913 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29249 /* 85916 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29250 /* 85919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
29251 /* 85923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29252 /* 85927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29253 /* 85931 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29254 /* 85935 */ // MIs[1] Operand 1
29255 /* 85935 */ // No operand predicates
29256 /* 85935 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29257 /* 85939 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29258 /* 85943 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29259 /* 85947 */ // MIs[2] Operand 1
29260 /* 85947 */ // No operand predicates
29261 /* 85947 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29262 /* 85949 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10742:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
29263 /* 85949 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29264 /* 85952 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29265 /* 85956 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29266 /* 85961 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29267 /* 85965 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29268 /* 85970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWPP),
29269 /* 85973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29270 /* 85975 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29271 /* 85977 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
29272 /* 85979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29273 /* 85982 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29274 /* 85985 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29275 /* 85988 */ GIR_RootConstrainSelectedInstOperands,
29276 /* 85989 */ // GIR_Coverage, 3647,
29277 /* 85989 */ GIR_EraseRootFromParent_Done,
29278 /* 85990 */ // Label 1360: @85990
29279 /* 85990 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(86092), // Rule ID 3648 //
29280 /* 85995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29281 /* 85998 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpn),
29282 /* 86003 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29283 /* 86006 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29284 /* 86009 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29285 /* 86012 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29286 /* 86015 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29287 /* 86018 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29288 /* 86021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
29289 /* 86025 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29290 /* 86029 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29291 /* 86033 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29292 /* 86037 */ // MIs[1] Operand 1
29293 /* 86037 */ // No operand predicates
29294 /* 86037 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29295 /* 86041 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29296 /* 86045 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29297 /* 86049 */ // MIs[2] Operand 1
29298 /* 86049 */ // No operand predicates
29299 /* 86049 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29300 /* 86051 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10741:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
29301 /* 86051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29302 /* 86054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29303 /* 86058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29304 /* 86063 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29305 /* 86067 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29306 /* 86072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWPN),
29307 /* 86075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29308 /* 86077 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29309 /* 86079 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
29310 /* 86081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29311 /* 86084 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29312 /* 86087 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29313 /* 86090 */ GIR_RootConstrainSelectedInstOperands,
29314 /* 86091 */ // GIR_Coverage, 3648,
29315 /* 86091 */ GIR_EraseRootFromParent_Done,
29316 /* 86092 */ // Label 1361: @86092
29317 /* 86092 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(86194), // Rule ID 3649 //
29318 /* 86097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29319 /* 86100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernp),
29320 /* 86105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29321 /* 86108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29322 /* 86111 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29323 /* 86114 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29324 /* 86117 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29325 /* 86120 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29326 /* 86123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
29327 /* 86127 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29328 /* 86131 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29329 /* 86135 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29330 /* 86139 */ // MIs[1] Operand 1
29331 /* 86139 */ // No operand predicates
29332 /* 86139 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29333 /* 86143 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29334 /* 86147 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29335 /* 86151 */ // MIs[2] Operand 1
29336 /* 86151 */ // No operand predicates
29337 /* 86151 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29338 /* 86153 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10740:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
29339 /* 86153 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29340 /* 86156 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29341 /* 86160 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29342 /* 86165 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29343 /* 86169 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29344 /* 86174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWNP),
29345 /* 86177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29346 /* 86179 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29347 /* 86181 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
29348 /* 86183 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29349 /* 86186 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29350 /* 86189 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29351 /* 86192 */ GIR_RootConstrainSelectedInstOperands,
29352 /* 86193 */ // GIR_Coverage, 3649,
29353 /* 86193 */ GIR_EraseRootFromParent_Done,
29354 /* 86194 */ // Label 1362: @86194
29355 /* 86194 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(86296), // Rule ID 3650 //
29356 /* 86199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29357 /* 86202 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernn),
29358 /* 86207 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29359 /* 86210 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29360 /* 86213 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29361 /* 86216 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29362 /* 86219 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29363 /* 86222 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29364 /* 86225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
29365 /* 86229 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29366 /* 86233 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29367 /* 86237 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29368 /* 86241 */ // MIs[1] Operand 1
29369 /* 86241 */ // No operand predicates
29370 /* 86241 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29371 /* 86245 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29372 /* 86249 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29373 /* 86253 */ // MIs[2] Operand 1
29374 /* 86253 */ // No operand predicates
29375 /* 86253 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
29376 /* 86255 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10739:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK)
29377 /* 86255 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29378 /* 86258 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29379 /* 86262 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29380 /* 86267 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29381 /* 86271 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29382 /* 86276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWNN),
29383 /* 86279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29384 /* 86281 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29385 /* 86283 */ GIR_RootToRootCopy, /*OpIdx*/3, // XA
29386 /* 86285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29387 /* 86288 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29388 /* 86291 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29389 /* 86294 */ GIR_RootConstrainSelectedInstOperands,
29390 /* 86295 */ // GIR_Coverage, 3650,
29391 /* 86295 */ GIR_EraseRootFromParent_Done,
29392 /* 86296 */ // Label 1363: @86296
29393 /* 86296 */ GIM_Reject,
29394 /* 86297 */ // Label 1331: @86297
29395 /* 86297 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(91198),
29396 /* 86302 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
29397 /* 86305 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(86425), // Rule ID 3530 //
29398 /* 86310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29399 /* 86313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvi8gerx4pp),
29400 /* 86318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29401 /* 86321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29402 /* 86324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29403 /* 86327 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29404 /* 86330 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29405 /* 86333 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29406 /* 86336 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29407 /* 86339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29408 /* 86343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29409 /* 86347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29410 /* 86351 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29411 /* 86355 */ // MIs[1] Operand 1
29412 /* 86355 */ // No operand predicates
29413 /* 86355 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29414 /* 86359 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29415 /* 86363 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29416 /* 86367 */ // MIs[2] Operand 1
29417 /* 86367 */ // No operand predicates
29418 /* 86367 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29419 /* 86371 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29420 /* 86375 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29421 /* 86379 */ // MIs[3] Operand 1
29422 /* 86379 */ // No operand predicates
29423 /* 86379 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29424 /* 86381 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10721:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMDMXVI8GERX4PP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK)
29425 /* 86381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29426 /* 86384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29427 /* 86388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29428 /* 86393 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29429 /* 86397 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29430 /* 86402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVI8GERX4PP),
29431 /* 86405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29432 /* 86407 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29433 /* 86409 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29434 /* 86411 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29435 /* 86414 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29436 /* 86417 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29437 /* 86420 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29438 /* 86423 */ GIR_RootConstrainSelectedInstOperands,
29439 /* 86424 */ // GIR_Coverage, 3530,
29440 /* 86424 */ GIR_EraseRootFromParent_Done,
29441 /* 86425 */ // Label 1365: @86425
29442 /* 86425 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(86545), // Rule ID 3531 //
29443 /* 86430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29444 /* 86433 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvi8gerx4spp),
29445 /* 86438 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29446 /* 86441 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29447 /* 86444 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29448 /* 86447 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29449 /* 86450 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29450 /* 86453 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29451 /* 86456 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29452 /* 86459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29453 /* 86463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29454 /* 86467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29455 /* 86471 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29456 /* 86475 */ // MIs[1] Operand 1
29457 /* 86475 */ // No operand predicates
29458 /* 86475 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29459 /* 86479 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29460 /* 86483 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29461 /* 86487 */ // MIs[2] Operand 1
29462 /* 86487 */ // No operand predicates
29463 /* 86487 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29464 /* 86491 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29465 /* 86495 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29466 /* 86499 */ // MIs[3] Operand 1
29467 /* 86499 */ // No operand predicates
29468 /* 86499 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29469 /* 86501 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10722:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMDMXVI8GERX4SPP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK)
29470 /* 86501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29471 /* 86504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29472 /* 86508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29473 /* 86513 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29474 /* 86517 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29475 /* 86522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVI8GERX4SPP),
29476 /* 86525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29477 /* 86527 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29478 /* 86529 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29479 /* 86531 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29480 /* 86534 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29481 /* 86537 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29482 /* 86540 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29483 /* 86543 */ GIR_RootConstrainSelectedInstOperands,
29484 /* 86544 */ // GIR_Coverage, 3531,
29485 /* 86544 */ GIR_EraseRootFromParent_Done,
29486 /* 86545 */ // Label 1366: @86545
29487 /* 86545 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(86665), // Rule ID 3533 //
29488 /* 86550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29489 /* 86553 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvbf16gerx2pp),
29490 /* 86558 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29491 /* 86561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29492 /* 86564 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29493 /* 86567 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29494 /* 86570 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29495 /* 86573 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29496 /* 86576 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29497 /* 86579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29498 /* 86583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29499 /* 86587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29500 /* 86591 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29501 /* 86595 */ // MIs[1] Operand 1
29502 /* 86595 */ // No operand predicates
29503 /* 86595 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29504 /* 86599 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29505 /* 86603 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29506 /* 86607 */ // MIs[2] Operand 1
29507 /* 86607 */ // No operand predicates
29508 /* 86607 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29509 /* 86611 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29510 /* 86615 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29511 /* 86619 */ // MIs[3] Operand 1
29512 /* 86619 */ // No operand predicates
29513 /* 86619 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29514 /* 86621 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10714:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVBF16GERX2PP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29515 /* 86621 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29516 /* 86624 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29517 /* 86628 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29518 /* 86633 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29519 /* 86637 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29520 /* 86642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVBF16GERX2PP),
29521 /* 86645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29522 /* 86647 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29523 /* 86649 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29524 /* 86651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29525 /* 86654 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29526 /* 86657 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29527 /* 86660 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29528 /* 86663 */ GIR_RootConstrainSelectedInstOperands,
29529 /* 86664 */ // GIR_Coverage, 3533,
29530 /* 86664 */ GIR_EraseRootFromParent_Done,
29531 /* 86665 */ // Label 1367: @86665
29532 /* 86665 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(86785), // Rule ID 3534 //
29533 /* 86670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29534 /* 86673 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvbf16gerx2pn),
29535 /* 86678 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29536 /* 86681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29537 /* 86684 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29538 /* 86687 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29539 /* 86690 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29540 /* 86693 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29541 /* 86696 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29542 /* 86699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29543 /* 86703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29544 /* 86707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29545 /* 86711 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29546 /* 86715 */ // MIs[1] Operand 1
29547 /* 86715 */ // No operand predicates
29548 /* 86715 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29549 /* 86719 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29550 /* 86723 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29551 /* 86727 */ // MIs[2] Operand 1
29552 /* 86727 */ // No operand predicates
29553 /* 86727 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29554 /* 86731 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29555 /* 86735 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29556 /* 86739 */ // MIs[3] Operand 1
29557 /* 86739 */ // No operand predicates
29558 /* 86739 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29559 /* 86741 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10713:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVBF16GERX2PN:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29560 /* 86741 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29561 /* 86744 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29562 /* 86748 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29563 /* 86753 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29564 /* 86757 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29565 /* 86762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVBF16GERX2PN),
29566 /* 86765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29567 /* 86767 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29568 /* 86769 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29569 /* 86771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29570 /* 86774 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29571 /* 86777 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29572 /* 86780 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29573 /* 86783 */ GIR_RootConstrainSelectedInstOperands,
29574 /* 86784 */ // GIR_Coverage, 3534,
29575 /* 86784 */ GIR_EraseRootFromParent_Done,
29576 /* 86785 */ // Label 1368: @86785
29577 /* 86785 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(86905), // Rule ID 3535 //
29578 /* 86790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29579 /* 86793 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvbf16gerx2np),
29580 /* 86798 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29581 /* 86801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29582 /* 86804 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29583 /* 86807 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29584 /* 86810 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29585 /* 86813 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29586 /* 86816 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29587 /* 86819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29588 /* 86823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29589 /* 86827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29590 /* 86831 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29591 /* 86835 */ // MIs[1] Operand 1
29592 /* 86835 */ // No operand predicates
29593 /* 86835 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29594 /* 86839 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29595 /* 86843 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29596 /* 86847 */ // MIs[2] Operand 1
29597 /* 86847 */ // No operand predicates
29598 /* 86847 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29599 /* 86851 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29600 /* 86855 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29601 /* 86859 */ // MIs[3] Operand 1
29602 /* 86859 */ // No operand predicates
29603 /* 86859 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29604 /* 86861 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10712:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVBF16GERX2NP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29605 /* 86861 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29606 /* 86864 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29607 /* 86868 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29608 /* 86873 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29609 /* 86877 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29610 /* 86882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVBF16GERX2NP),
29611 /* 86885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29612 /* 86887 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29613 /* 86889 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29614 /* 86891 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29615 /* 86894 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29616 /* 86897 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29617 /* 86900 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29618 /* 86903 */ GIR_RootConstrainSelectedInstOperands,
29619 /* 86904 */ // GIR_Coverage, 3535,
29620 /* 86904 */ GIR_EraseRootFromParent_Done,
29621 /* 86905 */ // Label 1369: @86905
29622 /* 86905 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(87025), // Rule ID 3536 //
29623 /* 86910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29624 /* 86913 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvbf16gerx2nn),
29625 /* 86918 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29626 /* 86921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29627 /* 86924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29628 /* 86927 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29629 /* 86930 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29630 /* 86933 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29631 /* 86936 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29632 /* 86939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29633 /* 86943 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29634 /* 86947 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29635 /* 86951 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29636 /* 86955 */ // MIs[1] Operand 1
29637 /* 86955 */ // No operand predicates
29638 /* 86955 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29639 /* 86959 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29640 /* 86963 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29641 /* 86967 */ // MIs[2] Operand 1
29642 /* 86967 */ // No operand predicates
29643 /* 86967 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29644 /* 86971 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29645 /* 86975 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29646 /* 86979 */ // MIs[3] Operand 1
29647 /* 86979 */ // No operand predicates
29648 /* 86979 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29649 /* 86981 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10711:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVBF16GERX2NN:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29650 /* 86981 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29651 /* 86984 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29652 /* 86988 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29653 /* 86993 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29654 /* 86997 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29655 /* 87002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVBF16GERX2NN),
29656 /* 87005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29657 /* 87007 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29658 /* 87009 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29659 /* 87011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29660 /* 87014 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29661 /* 87017 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29662 /* 87020 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29663 /* 87023 */ GIR_RootConstrainSelectedInstOperands,
29664 /* 87024 */ // GIR_Coverage, 3536,
29665 /* 87024 */ GIR_EraseRootFromParent_Done,
29666 /* 87025 */ // Label 1370: @87025
29667 /* 87025 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(87145), // Rule ID 3538 //
29668 /* 87030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29669 /* 87033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvf16gerx2pp),
29670 /* 87038 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29671 /* 87041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29672 /* 87044 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29673 /* 87047 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29674 /* 87050 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29675 /* 87053 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29676 /* 87056 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29677 /* 87059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29678 /* 87063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29679 /* 87067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29680 /* 87071 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29681 /* 87075 */ // MIs[1] Operand 1
29682 /* 87075 */ // No operand predicates
29683 /* 87075 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29684 /* 87079 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29685 /* 87083 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29686 /* 87087 */ // MIs[2] Operand 1
29687 /* 87087 */ // No operand predicates
29688 /* 87087 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29689 /* 87091 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29690 /* 87095 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29691 /* 87099 */ // MIs[3] Operand 1
29692 /* 87099 */ // No operand predicates
29693 /* 87099 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29694 /* 87101 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10719:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVF16GERX2PP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29695 /* 87101 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29696 /* 87104 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29697 /* 87108 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29698 /* 87113 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29699 /* 87117 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29700 /* 87122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVF16GERX2PP),
29701 /* 87125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29702 /* 87127 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29703 /* 87129 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29704 /* 87131 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29705 /* 87134 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29706 /* 87137 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29707 /* 87140 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29708 /* 87143 */ GIR_RootConstrainSelectedInstOperands,
29709 /* 87144 */ // GIR_Coverage, 3538,
29710 /* 87144 */ GIR_EraseRootFromParent_Done,
29711 /* 87145 */ // Label 1371: @87145
29712 /* 87145 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(87265), // Rule ID 3539 //
29713 /* 87150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29714 /* 87153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvf16gerx2pn),
29715 /* 87158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29716 /* 87161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29717 /* 87164 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29718 /* 87167 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29719 /* 87170 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29720 /* 87173 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29721 /* 87176 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29722 /* 87179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29723 /* 87183 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29724 /* 87187 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29725 /* 87191 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29726 /* 87195 */ // MIs[1] Operand 1
29727 /* 87195 */ // No operand predicates
29728 /* 87195 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29729 /* 87199 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29730 /* 87203 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29731 /* 87207 */ // MIs[2] Operand 1
29732 /* 87207 */ // No operand predicates
29733 /* 87207 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29734 /* 87211 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29735 /* 87215 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29736 /* 87219 */ // MIs[3] Operand 1
29737 /* 87219 */ // No operand predicates
29738 /* 87219 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29739 /* 87221 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10718:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVF16GERX2PN:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29740 /* 87221 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29741 /* 87224 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29742 /* 87228 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29743 /* 87233 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29744 /* 87237 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29745 /* 87242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVF16GERX2PN),
29746 /* 87245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29747 /* 87247 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29748 /* 87249 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29749 /* 87251 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29750 /* 87254 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29751 /* 87257 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29752 /* 87260 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29753 /* 87263 */ GIR_RootConstrainSelectedInstOperands,
29754 /* 87264 */ // GIR_Coverage, 3539,
29755 /* 87264 */ GIR_EraseRootFromParent_Done,
29756 /* 87265 */ // Label 1372: @87265
29757 /* 87265 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(87385), // Rule ID 3540 //
29758 /* 87270 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29759 /* 87273 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvf16gerx2np),
29760 /* 87278 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29761 /* 87281 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29762 /* 87284 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29763 /* 87287 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29764 /* 87290 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29765 /* 87293 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29766 /* 87296 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29767 /* 87299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29768 /* 87303 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29769 /* 87307 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29770 /* 87311 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29771 /* 87315 */ // MIs[1] Operand 1
29772 /* 87315 */ // No operand predicates
29773 /* 87315 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29774 /* 87319 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29775 /* 87323 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29776 /* 87327 */ // MIs[2] Operand 1
29777 /* 87327 */ // No operand predicates
29778 /* 87327 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29779 /* 87331 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29780 /* 87335 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29781 /* 87339 */ // MIs[3] Operand 1
29782 /* 87339 */ // No operand predicates
29783 /* 87339 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29784 /* 87341 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10717:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVF16GERX2NP:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29785 /* 87341 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29786 /* 87344 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29787 /* 87348 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29788 /* 87353 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29789 /* 87357 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29790 /* 87362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVF16GERX2NP),
29791 /* 87365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29792 /* 87367 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29793 /* 87369 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29794 /* 87371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29795 /* 87374 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29796 /* 87377 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29797 /* 87380 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29798 /* 87383 */ GIR_RootConstrainSelectedInstOperands,
29799 /* 87384 */ // GIR_Coverage, 3540,
29800 /* 87384 */ GIR_EraseRootFromParent_Done,
29801 /* 87385 */ // Label 1373: @87385
29802 /* 87385 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(87505), // Rule ID 3541 //
29803 /* 87390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
29804 /* 87393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmdmxvf16gerx2nn),
29805 /* 87398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v1024s1,
29806 /* 87401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v1024s1,
29807 /* 87404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1,
29808 /* 87407 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29809 /* 87410 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29810 /* 87413 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29811 /* 87416 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29812 /* 87419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::DMRRCRegClassID),
29813 /* 87423 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29814 /* 87427 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29815 /* 87431 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29816 /* 87435 */ // MIs[1] Operand 1
29817 /* 87435 */ // No operand predicates
29818 /* 87435 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29819 /* 87439 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29820 /* 87443 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29821 /* 87447 */ // MIs[2] Operand 1
29822 /* 87447 */ // No operand predicates
29823 /* 87447 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29824 /* 87451 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29825 /* 87455 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29826 /* 87459 */ // MIs[3] Operand 1
29827 /* 87459 */ // No operand predicates
29828 /* 87459 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29829 /* 87461 */ // (intrinsic_wo_chain:{ *:[v1024i1] } 10716:{ *:[iPTR] }, v1024i1:{ *:[v1024i1] }:$ATi, v256i1:{ *:[v256i1] }:$XAp, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMDMXVF16GERX2NN:{ *:[v1024i1] } ?:{ *:[v1024i1] }:$ATi, ?:{ *:[v256i1] }:$XAp, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29830 /* 87461 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29831 /* 87464 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29832 /* 87468 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29833 /* 87473 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB
29834 /* 87477 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29835 /* 87482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMDMXVF16GERX2NN),
29836 /* 87485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29837 /* 87487 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29838 /* 87489 */ GIR_RootToRootCopy, /*OpIdx*/3, // XAp
29839 /* 87491 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29840 /* 87494 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29841 /* 87497 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29842 /* 87500 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29843 /* 87503 */ GIR_RootConstrainSelectedInstOperands,
29844 /* 87504 */ // GIR_Coverage, 3541,
29845 /* 87504 */ GIR_EraseRootFromParent_Done,
29846 /* 87505 */ // Label 1374: @87505
29847 /* 87505 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(87647), // Rule ID 3602 //
29848 /* 87510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
29849 /* 87513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8pp),
29850 /* 87518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29851 /* 87521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29852 /* 87524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29853 /* 87527 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29854 /* 87530 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29855 /* 87533 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29856 /* 87536 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29857 /* 87539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
29858 /* 87543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29859 /* 87547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29860 /* 87551 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29861 /* 87555 */ // MIs[1] Operand 1
29862 /* 87555 */ // No operand predicates
29863 /* 87555 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29864 /* 87559 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29865 /* 87563 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29866 /* 87567 */ // MIs[2] Operand 1
29867 /* 87567 */ // No operand predicates
29868 /* 87567 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29869 /* 87571 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29870 /* 87575 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
29871 /* 87579 */ // MIs[3] Operand 1
29872 /* 87579 */ // No operand predicates
29873 /* 87579 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29874 /* 87581 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10748:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK)
29875 /* 87581 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
29876 /* 87584 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29877 /* 87588 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29878 /* 87593 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
29879 /* 87597 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29880 /* 87602 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29881 /* 87605 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29882 /* 87609 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29883 /* 87614 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
29884 /* 87618 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29885 /* 87623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8PP),
29886 /* 87626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29887 /* 87628 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29888 /* 87630 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29889 /* 87633 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
29890 /* 87636 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29891 /* 87639 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29892 /* 87642 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29893 /* 87645 */ GIR_RootConstrainSelectedInstOperands,
29894 /* 87646 */ // GIR_Coverage, 3602,
29895 /* 87646 */ GIR_EraseRootFromParent_Done,
29896 /* 87647 */ // Label 1375: @87647
29897 /* 87647 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(87789), // Rule ID 3604 //
29898 /* 87652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
29899 /* 87655 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4pp),
29900 /* 87660 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29901 /* 87663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29902 /* 87666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29903 /* 87669 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29904 /* 87672 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29905 /* 87675 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29906 /* 87678 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29907 /* 87681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
29908 /* 87685 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29909 /* 87689 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29910 /* 87693 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29911 /* 87697 */ // MIs[1] Operand 1
29912 /* 87697 */ // No operand predicates
29913 /* 87697 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29914 /* 87701 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29915 /* 87705 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29916 /* 87709 */ // MIs[2] Operand 1
29917 /* 87709 */ // No operand predicates
29918 /* 87709 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29919 /* 87713 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29920 /* 87717 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29921 /* 87721 */ // MIs[3] Operand 1
29922 /* 87721 */ // No operand predicates
29923 /* 87721 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29924 /* 87723 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10750:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK)
29925 /* 87723 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
29926 /* 87726 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29927 /* 87730 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29928 /* 87735 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
29929 /* 87739 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29930 /* 87744 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29931 /* 87747 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29932 /* 87751 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29933 /* 87756 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
29934 /* 87760 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29935 /* 87765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4PP),
29936 /* 87768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29937 /* 87770 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29938 /* 87772 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29939 /* 87775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
29940 /* 87778 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29941 /* 87781 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29942 /* 87784 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29943 /* 87787 */ GIR_RootConstrainSelectedInstOperands,
29944 /* 87788 */ // GIR_Coverage, 3604,
29945 /* 87788 */ GIR_EraseRootFromParent_Done,
29946 /* 87789 */ // Label 1376: @87789
29947 /* 87789 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(87931), // Rule ID 3606 //
29948 /* 87794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
29949 /* 87797 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2spp),
29950 /* 87802 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
29951 /* 87805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
29952 /* 87808 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29953 /* 87811 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29954 /* 87814 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29955 /* 87817 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29956 /* 87820 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
29957 /* 87823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
29958 /* 87827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
29959 /* 87831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29960 /* 87835 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29961 /* 87839 */ // MIs[1] Operand 1
29962 /* 87839 */ // No operand predicates
29963 /* 87839 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
29964 /* 87843 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29965 /* 87847 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
29966 /* 87851 */ // MIs[2] Operand 1
29967 /* 87851 */ // No operand predicates
29968 /* 87851 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
29969 /* 87855 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29970 /* 87859 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
29971 /* 87863 */ // MIs[3] Operand 1
29972 /* 87863 */ // No operand predicates
29973 /* 87863 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
29974 /* 87865 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10746:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
29975 /* 87865 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
29976 /* 87868 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29977 /* 87872 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29978 /* 87877 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
29979 /* 87881 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29980 /* 87886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29981 /* 87889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29982 /* 87893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29983 /* 87898 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
29984 /* 87902 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
29985 /* 87907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SPP),
29986 /* 87910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
29987 /* 87912 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
29988 /* 87914 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29989 /* 87917 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
29990 /* 87920 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
29991 /* 87923 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
29992 /* 87926 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
29993 /* 87929 */ GIR_RootConstrainSelectedInstOperands,
29994 /* 87930 */ // GIR_Coverage, 3606,
29995 /* 87930 */ GIR_EraseRootFromParent_Done,
29996 /* 87931 */ // Label 1377: @87931
29997 /* 87931 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(88073), // Rule ID 3608 //
29998 /* 87936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
29999 /* 87939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pp),
30000 /* 87944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30001 /* 87947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30002 /* 87950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30003 /* 87953 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30004 /* 87956 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30005 /* 87959 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30006 /* 87962 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30007 /* 87965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30008 /* 87969 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30009 /* 87973 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30010 /* 87977 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30011 /* 87981 */ // MIs[1] Operand 1
30012 /* 87981 */ // No operand predicates
30013 /* 87981 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30014 /* 87985 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30015 /* 87989 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30016 /* 87993 */ // MIs[2] Operand 1
30017 /* 87993 */ // No operand predicates
30018 /* 87993 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30019 /* 87997 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30020 /* 88001 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30021 /* 88005 */ // MIs[3] Operand 1
30022 /* 88005 */ // No operand predicates
30023 /* 88005 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30024 /* 88007 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10732:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30025 /* 88007 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30026 /* 88010 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30027 /* 88014 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30028 /* 88019 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30029 /* 88023 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30030 /* 88028 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30031 /* 88031 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30032 /* 88035 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30033 /* 88040 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30034 /* 88044 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30035 /* 88049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2PP),
30036 /* 88052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30037 /* 88054 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30038 /* 88056 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30039 /* 88059 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30040 /* 88062 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30041 /* 88065 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30042 /* 88068 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30043 /* 88071 */ GIR_RootConstrainSelectedInstOperands,
30044 /* 88072 */ // GIR_Coverage, 3608,
30045 /* 88072 */ GIR_EraseRootFromParent_Done,
30046 /* 88073 */ // Label 1378: @88073
30047 /* 88073 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(88215), // Rule ID 3609 //
30048 /* 88078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30049 /* 88081 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pn),
30050 /* 88086 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30051 /* 88089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30052 /* 88092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30053 /* 88095 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30054 /* 88098 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30055 /* 88101 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30056 /* 88104 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30057 /* 88107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30058 /* 88111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30059 /* 88115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30060 /* 88119 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30061 /* 88123 */ // MIs[1] Operand 1
30062 /* 88123 */ // No operand predicates
30063 /* 88123 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30064 /* 88127 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30065 /* 88131 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30066 /* 88135 */ // MIs[2] Operand 1
30067 /* 88135 */ // No operand predicates
30068 /* 88135 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30069 /* 88139 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30070 /* 88143 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30071 /* 88147 */ // MIs[3] Operand 1
30072 /* 88147 */ // No operand predicates
30073 /* 88147 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30074 /* 88149 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10731:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30075 /* 88149 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30076 /* 88152 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30077 /* 88156 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30078 /* 88161 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30079 /* 88165 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30080 /* 88170 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30081 /* 88173 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30082 /* 88177 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30083 /* 88182 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30084 /* 88186 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30085 /* 88191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2PN),
30086 /* 88194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30087 /* 88196 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30088 /* 88198 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30089 /* 88201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30090 /* 88204 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30091 /* 88207 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30092 /* 88210 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30093 /* 88213 */ GIR_RootConstrainSelectedInstOperands,
30094 /* 88214 */ // GIR_Coverage, 3609,
30095 /* 88214 */ GIR_EraseRootFromParent_Done,
30096 /* 88215 */ // Label 1379: @88215
30097 /* 88215 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(88357), // Rule ID 3610 //
30098 /* 88220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30099 /* 88223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2np),
30100 /* 88228 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30101 /* 88231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30102 /* 88234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30103 /* 88237 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30104 /* 88240 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30105 /* 88243 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30106 /* 88246 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30107 /* 88249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30108 /* 88253 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30109 /* 88257 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30110 /* 88261 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30111 /* 88265 */ // MIs[1] Operand 1
30112 /* 88265 */ // No operand predicates
30113 /* 88265 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30114 /* 88269 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30115 /* 88273 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30116 /* 88277 */ // MIs[2] Operand 1
30117 /* 88277 */ // No operand predicates
30118 /* 88277 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30119 /* 88281 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30120 /* 88285 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30121 /* 88289 */ // MIs[3] Operand 1
30122 /* 88289 */ // No operand predicates
30123 /* 88289 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30124 /* 88291 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10730:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30125 /* 88291 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30126 /* 88294 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30127 /* 88298 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30128 /* 88303 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30129 /* 88307 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30130 /* 88312 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30131 /* 88315 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30132 /* 88319 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30133 /* 88324 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30134 /* 88328 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30135 /* 88333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2NP),
30136 /* 88336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30137 /* 88338 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30138 /* 88340 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30139 /* 88343 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30140 /* 88346 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30141 /* 88349 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30142 /* 88352 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30143 /* 88355 */ GIR_RootConstrainSelectedInstOperands,
30144 /* 88356 */ // GIR_Coverage, 3610,
30145 /* 88356 */ GIR_EraseRootFromParent_Done,
30146 /* 88357 */ // Label 1380: @88357
30147 /* 88357 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(88499), // Rule ID 3611 //
30148 /* 88362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30149 /* 88365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2nn),
30150 /* 88370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30151 /* 88373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30152 /* 88376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30153 /* 88379 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30154 /* 88382 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30155 /* 88385 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30156 /* 88388 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30157 /* 88391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30158 /* 88395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30159 /* 88399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30160 /* 88403 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30161 /* 88407 */ // MIs[1] Operand 1
30162 /* 88407 */ // No operand predicates
30163 /* 88407 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30164 /* 88411 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30165 /* 88415 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30166 /* 88419 */ // MIs[2] Operand 1
30167 /* 88419 */ // No operand predicates
30168 /* 88419 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30169 /* 88423 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30170 /* 88427 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30171 /* 88431 */ // MIs[3] Operand 1
30172 /* 88431 */ // No operand predicates
30173 /* 88431 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30174 /* 88433 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10729:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30175 /* 88433 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30176 /* 88436 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30177 /* 88440 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30178 /* 88445 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30179 /* 88449 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30180 /* 88454 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30181 /* 88457 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30182 /* 88461 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30183 /* 88466 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30184 /* 88470 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30185 /* 88475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2NN),
30186 /* 88478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30187 /* 88480 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30188 /* 88482 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30189 /* 88485 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30190 /* 88488 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30191 /* 88491 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30192 /* 88494 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30193 /* 88497 */ GIR_RootConstrainSelectedInstOperands,
30194 /* 88498 */ // GIR_Coverage, 3611,
30195 /* 88498 */ GIR_EraseRootFromParent_Done,
30196 /* 88499 */ // Label 1381: @88499
30197 /* 88499 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(88641), // Rule ID 3623 //
30198 /* 88504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30199 /* 88507 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pp),
30200 /* 88512 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30201 /* 88515 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30202 /* 88518 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30203 /* 88521 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30204 /* 88524 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30205 /* 88527 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30206 /* 88530 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30207 /* 88533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30208 /* 88537 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30209 /* 88541 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30210 /* 88545 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30211 /* 88549 */ // MIs[1] Operand 1
30212 /* 88549 */ // No operand predicates
30213 /* 88549 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30214 /* 88553 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30215 /* 88557 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30216 /* 88561 */ // MIs[2] Operand 1
30217 /* 88561 */ // No operand predicates
30218 /* 88561 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30219 /* 88565 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30220 /* 88569 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30221 /* 88573 */ // MIs[3] Operand 1
30222 /* 88573 */ // No operand predicates
30223 /* 88573 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30224 /* 88575 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10727:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30225 /* 88575 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30226 /* 88578 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30227 /* 88582 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30228 /* 88587 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30229 /* 88591 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30230 /* 88596 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30231 /* 88599 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30232 /* 88603 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30233 /* 88608 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30234 /* 88612 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30235 /* 88617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2PP),
30236 /* 88620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30237 /* 88622 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30238 /* 88624 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30239 /* 88627 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30240 /* 88630 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30241 /* 88633 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30242 /* 88636 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30243 /* 88639 */ GIR_RootConstrainSelectedInstOperands,
30244 /* 88640 */ // GIR_Coverage, 3623,
30245 /* 88640 */ GIR_EraseRootFromParent_Done,
30246 /* 88641 */ // Label 1382: @88641
30247 /* 88641 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(88783), // Rule ID 3624 //
30248 /* 88646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30249 /* 88649 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pn),
30250 /* 88654 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30251 /* 88657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30252 /* 88660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30253 /* 88663 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30254 /* 88666 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30255 /* 88669 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30256 /* 88672 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30257 /* 88675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30258 /* 88679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30259 /* 88683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30260 /* 88687 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30261 /* 88691 */ // MIs[1] Operand 1
30262 /* 88691 */ // No operand predicates
30263 /* 88691 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30264 /* 88695 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30265 /* 88699 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30266 /* 88703 */ // MIs[2] Operand 1
30267 /* 88703 */ // No operand predicates
30268 /* 88703 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30269 /* 88707 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30270 /* 88711 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30271 /* 88715 */ // MIs[3] Operand 1
30272 /* 88715 */ // No operand predicates
30273 /* 88715 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30274 /* 88717 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10726:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30275 /* 88717 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30276 /* 88720 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30277 /* 88724 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30278 /* 88729 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30279 /* 88733 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30280 /* 88738 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30281 /* 88741 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30282 /* 88745 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30283 /* 88750 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30284 /* 88754 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30285 /* 88759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2PN),
30286 /* 88762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30287 /* 88764 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30288 /* 88766 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30289 /* 88769 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30290 /* 88772 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30291 /* 88775 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30292 /* 88778 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30293 /* 88781 */ GIR_RootConstrainSelectedInstOperands,
30294 /* 88782 */ // GIR_Coverage, 3624,
30295 /* 88782 */ GIR_EraseRootFromParent_Done,
30296 /* 88783 */ // Label 1383: @88783
30297 /* 88783 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(88925), // Rule ID 3625 //
30298 /* 88788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30299 /* 88791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2np),
30300 /* 88796 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30301 /* 88799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30302 /* 88802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30303 /* 88805 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30304 /* 88808 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30305 /* 88811 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30306 /* 88814 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30307 /* 88817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30308 /* 88821 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30309 /* 88825 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30310 /* 88829 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30311 /* 88833 */ // MIs[1] Operand 1
30312 /* 88833 */ // No operand predicates
30313 /* 88833 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30314 /* 88837 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30315 /* 88841 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30316 /* 88845 */ // MIs[2] Operand 1
30317 /* 88845 */ // No operand predicates
30318 /* 88845 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30319 /* 88849 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30320 /* 88853 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30321 /* 88857 */ // MIs[3] Operand 1
30322 /* 88857 */ // No operand predicates
30323 /* 88857 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30324 /* 88859 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10725:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30325 /* 88859 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30326 /* 88862 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30327 /* 88866 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30328 /* 88871 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30329 /* 88875 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30330 /* 88880 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30331 /* 88883 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30332 /* 88887 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30333 /* 88892 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30334 /* 88896 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30335 /* 88901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2NP),
30336 /* 88904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30337 /* 88906 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30338 /* 88908 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30339 /* 88911 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30340 /* 88914 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30341 /* 88917 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30342 /* 88920 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30343 /* 88923 */ GIR_RootConstrainSelectedInstOperands,
30344 /* 88924 */ // GIR_Coverage, 3625,
30345 /* 88924 */ GIR_EraseRootFromParent_Done,
30346 /* 88925 */ // Label 1384: @88925
30347 /* 88925 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(89067), // Rule ID 3626 //
30348 /* 88930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30349 /* 88933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2nn),
30350 /* 88938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30351 /* 88941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30352 /* 88944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30353 /* 88947 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30354 /* 88950 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30355 /* 88953 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30356 /* 88956 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30357 /* 88959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30358 /* 88963 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30359 /* 88967 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30360 /* 88971 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30361 /* 88975 */ // MIs[1] Operand 1
30362 /* 88975 */ // No operand predicates
30363 /* 88975 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30364 /* 88979 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30365 /* 88983 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30366 /* 88987 */ // MIs[2] Operand 1
30367 /* 88987 */ // No operand predicates
30368 /* 88987 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30369 /* 88991 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30370 /* 88995 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30371 /* 88999 */ // MIs[3] Operand 1
30372 /* 88999 */ // No operand predicates
30373 /* 88999 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30374 /* 89001 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10724:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30375 /* 89001 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30376 /* 89004 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30377 /* 89008 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30378 /* 89013 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30379 /* 89017 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30380 /* 89022 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30381 /* 89025 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30382 /* 89029 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30383 /* 89034 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30384 /* 89038 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30385 /* 89043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2NN),
30386 /* 89046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30387 /* 89048 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30388 /* 89050 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30389 /* 89053 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30390 /* 89056 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30391 /* 89059 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30392 /* 89062 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30393 /* 89065 */ GIR_RootConstrainSelectedInstOperands,
30394 /* 89066 */ // GIR_Coverage, 3626,
30395 /* 89066 */ GIR_EraseRootFromParent_Done,
30396 /* 89067 */ // Label 1385: @89067
30397 /* 89067 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(89209), // Rule ID 3628 //
30398 /* 89072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30399 /* 89075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4spp),
30400 /* 89080 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30401 /* 89083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30402 /* 89086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30403 /* 89089 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30404 /* 89092 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30405 /* 89095 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30406 /* 89098 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30407 /* 89101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30408 /* 89105 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30409 /* 89109 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30410 /* 89113 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30411 /* 89117 */ // MIs[1] Operand 1
30412 /* 89117 */ // No operand predicates
30413 /* 89117 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30414 /* 89121 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30415 /* 89125 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30416 /* 89129 */ // MIs[2] Operand 1
30417 /* 89129 */ // No operand predicates
30418 /* 89129 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30419 /* 89133 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30420 /* 89137 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30421 /* 89141 */ // MIs[3] Operand 1
30422 /* 89141 */ // No operand predicates
30423 /* 89141 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30424 /* 89143 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10751:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI8GER4SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30425 /* 89143 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30426 /* 89146 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30427 /* 89150 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30428 /* 89155 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30429 /* 89159 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30430 /* 89164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30431 /* 89167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30432 /* 89171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30433 /* 89176 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30434 /* 89180 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30435 /* 89185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4SPP),
30436 /* 89188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30437 /* 89190 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30438 /* 89192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30439 /* 89195 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30440 /* 89198 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30441 /* 89201 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30442 /* 89204 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30443 /* 89207 */ GIR_RootConstrainSelectedInstOperands,
30444 /* 89208 */ // GIR_Coverage, 3628,
30445 /* 89208 */ GIR_EraseRootFromParent_Done,
30446 /* 89209 */ // Label 1386: @89209
30447 /* 89209 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(89351), // Rule ID 3629 //
30448 /* 89214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs),
30449 /* 89217 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2pp),
30450 /* 89222 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30451 /* 89225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30452 /* 89228 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30453 /* 89231 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30454 /* 89234 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30455 /* 89237 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30456 /* 89240 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30457 /* 89243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
30458 /* 89247 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30459 /* 89251 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30460 /* 89255 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30461 /* 89259 */ // MIs[1] Operand 1
30462 /* 89259 */ // No operand predicates
30463 /* 89259 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30464 /* 89263 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30465 /* 89267 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30466 /* 89271 */ // MIs[2] Operand 1
30467 /* 89271 */ // No operand predicates
30468 /* 89271 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30469 /* 89275 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30470 /* 89279 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30471 /* 89283 */ // MIs[3] Operand 1
30472 /* 89283 */ // No operand predicates
30473 /* 89283 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30474 /* 89285 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10744:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30475 /* 89285 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30476 /* 89288 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30477 /* 89292 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30478 /* 89297 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30479 /* 89301 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30480 /* 89306 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30481 /* 89309 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30482 /* 89313 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30483 /* 89318 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30484 /* 89322 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30485 /* 89327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2PP),
30486 /* 89330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30487 /* 89332 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30488 /* 89334 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30489 /* 89337 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30490 /* 89340 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30491 /* 89343 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30492 /* 89346 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30493 /* 89349 */ GIR_RootConstrainSelectedInstOperands,
30494 /* 89350 */ // GIR_Coverage, 3629,
30495 /* 89350 */ GIR_EraseRootFromParent_Done,
30496 /* 89351 */ // Label 1387: @89351
30497 /* 89351 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(89493), // Rule ID 3631 //
30498 /* 89356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30499 /* 89359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8pp),
30500 /* 89364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30501 /* 89367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30502 /* 89370 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30503 /* 89373 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30504 /* 89376 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30505 /* 89379 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30506 /* 89382 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30507 /* 89385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30508 /* 89389 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30509 /* 89393 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30510 /* 89397 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30511 /* 89401 */ // MIs[1] Operand 1
30512 /* 89401 */ // No operand predicates
30513 /* 89401 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30514 /* 89405 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30515 /* 89409 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30516 /* 89413 */ // MIs[2] Operand 1
30517 /* 89413 */ // No operand predicates
30518 /* 89413 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30519 /* 89417 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30520 /* 89421 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm),
30521 /* 89425 */ // MIs[3] Operand 1
30522 /* 89425 */ // No operand predicates
30523 /* 89425 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30524 /* 89427 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10748:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK)
30525 /* 89427 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30526 /* 89430 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30527 /* 89434 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30528 /* 89439 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30529 /* 89443 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30530 /* 89448 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30531 /* 89451 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30532 /* 89455 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30533 /* 89460 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30534 /* 89464 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30535 /* 89469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8WPP),
30536 /* 89472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30537 /* 89474 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30538 /* 89476 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30539 /* 89479 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30540 /* 89482 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30541 /* 89485 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30542 /* 89488 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30543 /* 89491 */ GIR_RootConstrainSelectedInstOperands,
30544 /* 89492 */ // GIR_Coverage, 3631,
30545 /* 89492 */ GIR_EraseRootFromParent_Done,
30546 /* 89493 */ // Label 1388: @89493
30547 /* 89493 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(89635), // Rule ID 3633 //
30548 /* 89498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30549 /* 89501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4pp),
30550 /* 89506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30551 /* 89509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30552 /* 89512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30553 /* 89515 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30554 /* 89518 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30555 /* 89521 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30556 /* 89524 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30557 /* 89527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30558 /* 89531 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30559 /* 89535 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30560 /* 89539 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30561 /* 89543 */ // MIs[1] Operand 1
30562 /* 89543 */ // No operand predicates
30563 /* 89543 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30564 /* 89547 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30565 /* 89551 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30566 /* 89555 */ // MIs[2] Operand 1
30567 /* 89555 */ // No operand predicates
30568 /* 89555 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30569 /* 89559 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30570 /* 89563 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30571 /* 89567 */ // MIs[3] Operand 1
30572 /* 89567 */ // No operand predicates
30573 /* 89567 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30574 /* 89569 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10750:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK)
30575 /* 89569 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30576 /* 89572 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30577 /* 89576 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30578 /* 89581 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30579 /* 89585 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30580 /* 89590 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30581 /* 89593 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30582 /* 89597 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30583 /* 89602 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30584 /* 89606 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30585 /* 89611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4WPP),
30586 /* 89614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30587 /* 89616 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30588 /* 89618 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30589 /* 89621 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30590 /* 89624 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30591 /* 89627 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30592 /* 89630 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30593 /* 89633 */ GIR_RootConstrainSelectedInstOperands,
30594 /* 89634 */ // GIR_Coverage, 3633,
30595 /* 89634 */ GIR_EraseRootFromParent_Done,
30596 /* 89635 */ // Label 1389: @89635
30597 /* 89635 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(89777), // Rule ID 3635 //
30598 /* 89640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30599 /* 89643 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2spp),
30600 /* 89648 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30601 /* 89651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30602 /* 89654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30603 /* 89657 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30604 /* 89660 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30605 /* 89663 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30606 /* 89666 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30607 /* 89669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30608 /* 89673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30609 /* 89677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30610 /* 89681 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30611 /* 89685 */ // MIs[1] Operand 1
30612 /* 89685 */ // No operand predicates
30613 /* 89685 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30614 /* 89689 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30615 /* 89693 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30616 /* 89697 */ // MIs[2] Operand 1
30617 /* 89697 */ // No operand predicates
30618 /* 89697 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30619 /* 89701 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30620 /* 89705 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30621 /* 89709 */ // MIs[3] Operand 1
30622 /* 89709 */ // No operand predicates
30623 /* 89709 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30624 /* 89711 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10746:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30625 /* 89711 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30626 /* 89714 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30627 /* 89718 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30628 /* 89723 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30629 /* 89727 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30630 /* 89732 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30631 /* 89735 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30632 /* 89739 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30633 /* 89744 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30634 /* 89748 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30635 /* 89753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SWPP),
30636 /* 89756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30637 /* 89758 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30638 /* 89760 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30639 /* 89763 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30640 /* 89766 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30641 /* 89769 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30642 /* 89772 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30643 /* 89775 */ GIR_RootConstrainSelectedInstOperands,
30644 /* 89776 */ // GIR_Coverage, 3635,
30645 /* 89776 */ GIR_EraseRootFromParent_Done,
30646 /* 89777 */ // Label 1390: @89777
30647 /* 89777 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(89919), // Rule ID 3637 //
30648 /* 89782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30649 /* 89785 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pp),
30650 /* 89790 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30651 /* 89793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30652 /* 89796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30653 /* 89799 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30654 /* 89802 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30655 /* 89805 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30656 /* 89808 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30657 /* 89811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30658 /* 89815 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30659 /* 89819 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30660 /* 89823 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30661 /* 89827 */ // MIs[1] Operand 1
30662 /* 89827 */ // No operand predicates
30663 /* 89827 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30664 /* 89831 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30665 /* 89835 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30666 /* 89839 */ // MIs[2] Operand 1
30667 /* 89839 */ // No operand predicates
30668 /* 89839 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30669 /* 89843 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30670 /* 89847 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30671 /* 89851 */ // MIs[3] Operand 1
30672 /* 89851 */ // No operand predicates
30673 /* 89851 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30674 /* 89853 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10732:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30675 /* 89853 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30676 /* 89856 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30677 /* 89860 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30678 /* 89865 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30679 /* 89869 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30680 /* 89874 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30681 /* 89877 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30682 /* 89881 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30683 /* 89886 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30684 /* 89890 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30685 /* 89895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WPP),
30686 /* 89898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30687 /* 89900 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30688 /* 89902 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30689 /* 89905 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30690 /* 89908 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30691 /* 89911 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30692 /* 89914 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30693 /* 89917 */ GIR_RootConstrainSelectedInstOperands,
30694 /* 89918 */ // GIR_Coverage, 3637,
30695 /* 89918 */ GIR_EraseRootFromParent_Done,
30696 /* 89919 */ // Label 1391: @89919
30697 /* 89919 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(90061), // Rule ID 3638 //
30698 /* 89924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30699 /* 89927 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pn),
30700 /* 89932 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30701 /* 89935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30702 /* 89938 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30703 /* 89941 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30704 /* 89944 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30705 /* 89947 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30706 /* 89950 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30707 /* 89953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30708 /* 89957 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30709 /* 89961 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30710 /* 89965 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30711 /* 89969 */ // MIs[1] Operand 1
30712 /* 89969 */ // No operand predicates
30713 /* 89969 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30714 /* 89973 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30715 /* 89977 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30716 /* 89981 */ // MIs[2] Operand 1
30717 /* 89981 */ // No operand predicates
30718 /* 89981 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30719 /* 89985 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30720 /* 89989 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30721 /* 89993 */ // MIs[3] Operand 1
30722 /* 89993 */ // No operand predicates
30723 /* 89993 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30724 /* 89995 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10731:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30725 /* 89995 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30726 /* 89998 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30727 /* 90002 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30728 /* 90007 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30729 /* 90011 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30730 /* 90016 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30731 /* 90019 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30732 /* 90023 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30733 /* 90028 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30734 /* 90032 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30735 /* 90037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WPN),
30736 /* 90040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30737 /* 90042 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30738 /* 90044 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30739 /* 90047 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30740 /* 90050 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30741 /* 90053 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30742 /* 90056 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30743 /* 90059 */ GIR_RootConstrainSelectedInstOperands,
30744 /* 90060 */ // GIR_Coverage, 3638,
30745 /* 90060 */ GIR_EraseRootFromParent_Done,
30746 /* 90061 */ // Label 1392: @90061
30747 /* 90061 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(90203), // Rule ID 3639 //
30748 /* 90066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30749 /* 90069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2np),
30750 /* 90074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30751 /* 90077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30752 /* 90080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30753 /* 90083 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30754 /* 90086 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30755 /* 90089 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30756 /* 90092 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30757 /* 90095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30758 /* 90099 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30759 /* 90103 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30760 /* 90107 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30761 /* 90111 */ // MIs[1] Operand 1
30762 /* 90111 */ // No operand predicates
30763 /* 90111 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30764 /* 90115 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30765 /* 90119 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30766 /* 90123 */ // MIs[2] Operand 1
30767 /* 90123 */ // No operand predicates
30768 /* 90123 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30769 /* 90127 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30770 /* 90131 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30771 /* 90135 */ // MIs[3] Operand 1
30772 /* 90135 */ // No operand predicates
30773 /* 90135 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30774 /* 90137 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10730:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30775 /* 90137 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30776 /* 90140 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30777 /* 90144 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30778 /* 90149 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30779 /* 90153 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30780 /* 90158 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30781 /* 90161 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30782 /* 90165 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30783 /* 90170 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30784 /* 90174 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30785 /* 90179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WNP),
30786 /* 90182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30787 /* 90184 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30788 /* 90186 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30789 /* 90189 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30790 /* 90192 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30791 /* 90195 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30792 /* 90198 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30793 /* 90201 */ GIR_RootConstrainSelectedInstOperands,
30794 /* 90202 */ // GIR_Coverage, 3639,
30795 /* 90202 */ GIR_EraseRootFromParent_Done,
30796 /* 90203 */ // Label 1393: @90203
30797 /* 90203 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(90345), // Rule ID 3640 //
30798 /* 90208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30799 /* 90211 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2nn),
30800 /* 90216 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30801 /* 90219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30802 /* 90222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30803 /* 90225 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30804 /* 90228 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30805 /* 90231 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30806 /* 90234 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30807 /* 90237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30808 /* 90241 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30809 /* 90245 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30810 /* 90249 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30811 /* 90253 */ // MIs[1] Operand 1
30812 /* 90253 */ // No operand predicates
30813 /* 90253 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30814 /* 90257 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30815 /* 90261 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30816 /* 90265 */ // MIs[2] Operand 1
30817 /* 90265 */ // No operand predicates
30818 /* 90265 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30819 /* 90269 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30820 /* 90273 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30821 /* 90277 */ // MIs[3] Operand 1
30822 /* 90277 */ // No operand predicates
30823 /* 90277 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30824 /* 90279 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10729:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30825 /* 90279 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30826 /* 90282 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30827 /* 90286 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30828 /* 90291 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30829 /* 90295 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30830 /* 90300 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30831 /* 90303 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30832 /* 90307 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30833 /* 90312 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30834 /* 90316 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30835 /* 90321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WNN),
30836 /* 90324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30837 /* 90326 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30838 /* 90328 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30839 /* 90331 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30840 /* 90334 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30841 /* 90337 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30842 /* 90340 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30843 /* 90343 */ GIR_RootConstrainSelectedInstOperands,
30844 /* 90344 */ // GIR_Coverage, 3640,
30845 /* 90344 */ GIR_EraseRootFromParent_Done,
30846 /* 90345 */ // Label 1394: @90345
30847 /* 90345 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(90487), // Rule ID 3652 //
30848 /* 90350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30849 /* 90353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pp),
30850 /* 90358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30851 /* 90361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30852 /* 90364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30853 /* 90367 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30854 /* 90370 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30855 /* 90373 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30856 /* 90376 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30857 /* 90379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30858 /* 90383 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30859 /* 90387 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30860 /* 90391 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30861 /* 90395 */ // MIs[1] Operand 1
30862 /* 90395 */ // No operand predicates
30863 /* 90395 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30864 /* 90399 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30865 /* 90403 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30866 /* 90407 */ // MIs[2] Operand 1
30867 /* 90407 */ // No operand predicates
30868 /* 90407 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30869 /* 90411 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30870 /* 90415 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30871 /* 90419 */ // MIs[3] Operand 1
30872 /* 90419 */ // No operand predicates
30873 /* 90419 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30874 /* 90421 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10727:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30875 /* 90421 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30876 /* 90424 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30877 /* 90428 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30878 /* 90433 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30879 /* 90437 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30880 /* 90442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30881 /* 90445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30882 /* 90449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30883 /* 90454 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30884 /* 90458 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30885 /* 90463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2WPP),
30886 /* 90466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30887 /* 90468 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30888 /* 90470 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30889 /* 90473 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30890 /* 90476 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30891 /* 90479 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30892 /* 90482 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30893 /* 90485 */ GIR_RootConstrainSelectedInstOperands,
30894 /* 90486 */ // GIR_Coverage, 3652,
30895 /* 90486 */ GIR_EraseRootFromParent_Done,
30896 /* 90487 */ // Label 1395: @90487
30897 /* 90487 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(90629), // Rule ID 3653 //
30898 /* 90492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30899 /* 90495 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pn),
30900 /* 90500 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30901 /* 90503 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30902 /* 90506 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30903 /* 90509 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30904 /* 90512 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30905 /* 90515 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30906 /* 90518 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30907 /* 90521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30908 /* 90525 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30909 /* 90529 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30910 /* 90533 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30911 /* 90537 */ // MIs[1] Operand 1
30912 /* 90537 */ // No operand predicates
30913 /* 90537 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30914 /* 90541 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30915 /* 90545 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30916 /* 90549 */ // MIs[2] Operand 1
30917 /* 90549 */ // No operand predicates
30918 /* 90549 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30919 /* 90553 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30920 /* 90557 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30921 /* 90561 */ // MIs[3] Operand 1
30922 /* 90561 */ // No operand predicates
30923 /* 90561 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30924 /* 90563 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10726:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30925 /* 90563 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30926 /* 90566 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30927 /* 90570 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30928 /* 90575 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30929 /* 90579 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30930 /* 90584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30931 /* 90587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30932 /* 90591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30933 /* 90596 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30934 /* 90600 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30935 /* 90605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2WPN),
30936 /* 90608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30937 /* 90610 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30938 /* 90612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30939 /* 90615 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30940 /* 90618 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30941 /* 90621 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30942 /* 90624 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30943 /* 90627 */ GIR_RootConstrainSelectedInstOperands,
30944 /* 90628 */ // GIR_Coverage, 3653,
30945 /* 90628 */ GIR_EraseRootFromParent_Done,
30946 /* 90629 */ // Label 1396: @90629
30947 /* 90629 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(90771), // Rule ID 3654 //
30948 /* 90634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30949 /* 90637 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2np),
30950 /* 90642 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
30951 /* 90645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
30952 /* 90648 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30953 /* 90651 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30954 /* 90654 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30955 /* 90657 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30956 /* 90660 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
30957 /* 90663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
30958 /* 90667 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
30959 /* 90671 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30960 /* 90675 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30961 /* 90679 */ // MIs[1] Operand 1
30962 /* 90679 */ // No operand predicates
30963 /* 90679 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
30964 /* 90683 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30965 /* 90687 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
30966 /* 90691 */ // MIs[2] Operand 1
30967 /* 90691 */ // No operand predicates
30968 /* 90691 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
30969 /* 90695 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30970 /* 90699 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
30971 /* 90703 */ // MIs[3] Operand 1
30972 /* 90703 */ // No operand predicates
30973 /* 90703 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
30974 /* 90705 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10725:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
30975 /* 90705 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
30976 /* 90708 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30977 /* 90712 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30978 /* 90717 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
30979 /* 90721 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30980 /* 90726 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30981 /* 90729 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
30982 /* 90733 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30983 /* 90738 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
30984 /* 90742 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
30985 /* 90747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2WNP),
30986 /* 90750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
30987 /* 90752 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
30988 /* 90754 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30989 /* 90757 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
30990 /* 90760 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
30991 /* 90763 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
30992 /* 90766 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
30993 /* 90769 */ GIR_RootConstrainSelectedInstOperands,
30994 /* 90770 */ // GIR_Coverage, 3654,
30995 /* 90770 */ GIR_EraseRootFromParent_Done,
30996 /* 90771 */ // Label 1397: @90771
30997 /* 90771 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(90913), // Rule ID 3655 //
30998 /* 90776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
30999 /* 90779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2nn),
31000 /* 90784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
31001 /* 90787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
31002 /* 90790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
31003 /* 90793 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
31004 /* 90796 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31005 /* 90799 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31006 /* 90802 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31007 /* 90805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
31008 /* 90809 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
31009 /* 90813 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31010 /* 90817 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
31011 /* 90821 */ // MIs[1] Operand 1
31012 /* 90821 */ // No operand predicates
31013 /* 90821 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
31014 /* 90825 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31015 /* 90829 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
31016 /* 90833 */ // MIs[2] Operand 1
31017 /* 90833 */ // No operand predicates
31018 /* 90833 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
31019 /* 90837 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31020 /* 90841 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
31021 /* 90845 */ // MIs[3] Operand 1
31022 /* 90845 */ // No operand predicates
31023 /* 90845 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
31024 /* 90847 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10724:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
31025 /* 90847 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
31026 /* 90850 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
31027 /* 90854 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31028 /* 90859 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
31029 /* 90863 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
31030 /* 90868 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31031 /* 90871 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
31032 /* 90875 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31033 /* 90880 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
31034 /* 90884 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
31035 /* 90889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2WNN),
31036 /* 90892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
31037 /* 90894 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
31038 /* 90896 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31039 /* 90899 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
31040 /* 90902 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
31041 /* 90905 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
31042 /* 90908 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
31043 /* 90911 */ GIR_RootConstrainSelectedInstOperands,
31044 /* 90912 */ // GIR_Coverage, 3655,
31045 /* 90912 */ GIR_EraseRootFromParent_Done,
31046 /* 90913 */ // Label 1398: @90913
31047 /* 90913 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(91055), // Rule ID 3657 //
31048 /* 90918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
31049 /* 90921 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4spp),
31050 /* 90926 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
31051 /* 90929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
31052 /* 90932 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
31053 /* 90935 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
31054 /* 90938 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31055 /* 90941 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31056 /* 90944 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31057 /* 90947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID),
31058 /* 90951 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
31059 /* 90955 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31060 /* 90959 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
31061 /* 90963 */ // MIs[1] Operand 1
31062 /* 90963 */ // No operand predicates
31063 /* 90963 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
31064 /* 90967 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31065 /* 90971 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
31066 /* 90975 */ // MIs[2] Operand 1
31067 /* 90975 */ // No operand predicates
31068 /* 90975 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
31069 /* 90979 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31070 /* 90983 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
31071 /* 90987 */ // MIs[3] Operand 1
31072 /* 90987 */ // No operand predicates
31073 /* 90987 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
31074 /* 90989 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10751:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI8GER4WSPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
31075 /* 90989 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
31076 /* 90992 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
31077 /* 90996 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31078 /* 91001 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
31079 /* 91005 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
31080 /* 91010 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31081 /* 91013 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
31082 /* 91017 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31083 /* 91022 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
31084 /* 91026 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
31085 /* 91031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4WSPP),
31086 /* 91034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
31087 /* 91036 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
31088 /* 91038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31089 /* 91041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
31090 /* 91044 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
31091 /* 91047 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
31092 /* 91050 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
31093 /* 91053 */ GIR_RootConstrainSelectedInstOperands,
31094 /* 91054 */ // GIR_Coverage, 3657,
31095 /* 91054 */ GIR_EraseRootFromParent_Done,
31096 /* 91055 */ // Label 1399: @91055
31097 /* 91055 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(91197), // Rule ID 3658 //
31098 /* 91060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs),
31099 /* 91063 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2pp),
31100 /* 91068 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1,
31101 /* 91071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1,
31102 /* 91074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
31103 /* 91077 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
31104 /* 91080 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31105 /* 91083 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31106 /* 91086 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31107 /* 91089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID),
31108 /* 91093 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1]
31109 /* 91097 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31110 /* 91101 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
31111 /* 91105 */ // MIs[1] Operand 1
31112 /* 91105 */ // No operand predicates
31113 /* 91105 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2]
31114 /* 91109 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31115 /* 91113 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm),
31116 /* 91117 */ // MIs[2] Operand 1
31117 /* 91117 */ // No operand predicates
31118 /* 91117 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3]
31119 /* 91121 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31120 /* 91125 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm),
31121 /* 91129 */ // MIs[3] Operand 1
31122 /* 91129 */ // No operand predicates
31123 /* 91129 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
31124 /* 91131 */ // (intrinsic_wo_chain:{ *:[v512i1] } 10744:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK)
31125 /* 91131 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
31126 /* 91134 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
31127 /* 91138 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31128 /* 91143 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB
31129 /* 91147 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
31130 /* 91152 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31131 /* 91155 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
31132 /* 91159 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31133 /* 91164 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA
31134 /* 91168 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
31135 /* 91173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2WPP),
31136 /* 91176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT]
31137 /* 91178 */ GIR_RootToRootCopy, /*OpIdx*/2, // ATi
31138 /* 91180 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31139 /* 91183 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
31140 /* 91186 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK
31141 /* 91189 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK
31142 /* 91192 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK
31143 /* 91195 */ GIR_RootConstrainSelectedInstOperands,
31144 /* 91196 */ // GIR_Coverage, 3658,
31145 /* 91196 */ GIR_EraseRootFromParent_Done,
31146 /* 91197 */ // Label 1400: @91197
31147 /* 91197 */ GIM_Reject,
31148 /* 91198 */ // Label 1364: @91198
31149 /* 91198 */ GIM_Reject,
31150 /* 91199 */ // Label 20: @91199
31151 /* 91199 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(91538),
31152 /* 91204 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
31153 /* 91207 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(91226), // Rule ID 106 //
31154 /* 91212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_eieio),
31155 /* 91217 */ // (intrinsic_void 10627:{ *:[iPTR] }) => (PseudoEIEIO)
31156 /* 91217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PseudoEIEIO),
31157 /* 91220 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31158 /* 91224 */ GIR_RootConstrainSelectedInstOperands,
31159 /* 91225 */ // GIR_Coverage, 106,
31160 /* 91225 */ GIR_EraseRootFromParent_Done,
31161 /* 91226 */ // Label 1402: @91226
31162 /* 91226 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(91251), // Rule ID 1201 //
31163 /* 91231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC),
31164 /* 91234 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_sync),
31165 /* 91239 */ // (intrinsic_void 10825:{ *:[iPTR] }) => (SYNC 0:{ *:[i32] })
31166 /* 91239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC),
31167 /* 91242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31168 /* 91245 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31169 /* 91249 */ GIR_RootConstrainSelectedInstOperands,
31170 /* 91250 */ // GIR_Coverage, 1201,
31171 /* 91250 */ GIR_EraseRootFromParent_Done,
31172 /* 91251 */ // Label 1403: @91251
31173 /* 91251 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(91276), // Rule ID 1202 //
31174 /* 91256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC),
31175 /* 91259 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_sync),
31176 /* 91264 */ // (intrinsic_void 10662:{ *:[iPTR] }) => (SYNC 0:{ *:[i32] })
31177 /* 91264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC),
31178 /* 91267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31179 /* 91270 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31180 /* 91274 */ GIR_RootConstrainSelectedInstOperands,
31181 /* 91275 */ // GIR_Coverage, 1202,
31182 /* 91275 */ GIR_EraseRootFromParent_Done,
31183 /* 91276 */ // Label 1404: @91276
31184 /* 91276 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(91301), // Rule ID 1203 //
31185 /* 91281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC),
31186 /* 91284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_lwsync),
31187 /* 91289 */ // (intrinsic_void 10671:{ *:[iPTR] }) => (SYNC 1:{ *:[i32] })
31188 /* 91289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC),
31189 /* 91292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
31190 /* 91295 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31191 /* 91299 */ GIR_RootConstrainSelectedInstOperands,
31192 /* 91300 */ // GIR_Coverage, 1203,
31193 /* 91300 */ GIR_EraseRootFromParent_Done,
31194 /* 91301 */ // Label 1405: @91301
31195 /* 91301 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(91326), // Rule ID 1204 //
31196 /* 91306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC),
31197 /* 91309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_lwsync),
31198 /* 91314 */ // (intrinsic_void 10661:{ *:[iPTR] }) => (SYNC 1:{ *:[i32] })
31199 /* 91314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC),
31200 /* 91317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
31201 /* 91320 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31202 /* 91324 */ GIR_RootConstrainSelectedInstOperands,
31203 /* 91325 */ // GIR_Coverage, 1204,
31204 /* 91325 */ GIR_EraseRootFromParent_Done,
31205 /* 91326 */ // Label 1406: @91326
31206 /* 91326 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(91348), // Rule ID 1205 //
31207 /* 91331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC),
31208 /* 91334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_sync),
31209 /* 91339 */ // (intrinsic_void 10825:{ *:[iPTR] }) => (MSYNC)
31210 /* 91339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC),
31211 /* 91342 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31212 /* 91346 */ GIR_RootConstrainSelectedInstOperands,
31213 /* 91347 */ // GIR_Coverage, 1205,
31214 /* 91347 */ GIR_EraseRootFromParent_Done,
31215 /* 91348 */ // Label 1407: @91348
31216 /* 91348 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(91370), // Rule ID 1206 //
31217 /* 91353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC),
31218 /* 91356 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_sync),
31219 /* 91361 */ // (intrinsic_void 10662:{ *:[iPTR] }) => (MSYNC)
31220 /* 91361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC),
31221 /* 91364 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31222 /* 91368 */ GIR_RootConstrainSelectedInstOperands,
31223 /* 91369 */ // GIR_Coverage, 1206,
31224 /* 91369 */ GIR_EraseRootFromParent_Done,
31225 /* 91370 */ // Label 1408: @91370
31226 /* 91370 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(91392), // Rule ID 1207 //
31227 /* 91375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC),
31228 /* 91378 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_lwsync),
31229 /* 91383 */ // (intrinsic_void 10671:{ *:[iPTR] }) => (MSYNC)
31230 /* 91383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC),
31231 /* 91386 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31232 /* 91390 */ GIR_RootConstrainSelectedInstOperands,
31233 /* 91391 */ // GIR_Coverage, 1207,
31234 /* 91391 */ GIR_EraseRootFromParent_Done,
31235 /* 91392 */ // Label 1409: @91392
31236 /* 91392 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(91414), // Rule ID 1208 //
31237 /* 91397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC),
31238 /* 91400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_lwsync),
31239 /* 91405 */ // (intrinsic_void 10661:{ *:[iPTR] }) => (MSYNC)
31240 /* 91405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC),
31241 /* 91408 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31242 /* 91412 */ GIR_RootConstrainSelectedInstOperands,
31243 /* 91413 */ // GIR_Coverage, 1208,
31244 /* 91413 */ GIR_EraseRootFromParent_Done,
31245 /* 91414 */ // Label 1410: @91414
31246 /* 91414 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(91433), // Rule ID 1209 //
31247 /* 91419 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_eieio),
31248 /* 91424 */ // (intrinsic_void 10627:{ *:[iPTR] }) => (PseudoEIEIO)
31249 /* 91424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PseudoEIEIO),
31250 /* 91427 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31251 /* 91431 */ GIR_RootConstrainSelectedInstOperands,
31252 /* 91432 */ // GIR_Coverage, 1209,
31253 /* 91432 */ GIR_EraseRootFromParent_Done,
31254 /* 91433 */ // Label 1411: @91433
31255 /* 91433 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(91452), // Rule ID 1210 //
31256 /* 91438 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_eieio),
31257 /* 91443 */ // (intrinsic_void 10660:{ *:[iPTR] }) => (PseudoEIEIO)
31258 /* 91443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PseudoEIEIO),
31259 /* 91446 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31260 /* 91450 */ GIR_RootConstrainSelectedInstOperands,
31261 /* 91451 */ // GIR_Coverage, 1210,
31262 /* 91451 */ GIR_EraseRootFromParent_Done,
31263 /* 91452 */ // Label 1412: @91452
31264 /* 91452 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(91474), // Rule ID 1236 //
31265 /* 91457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_fence),
31266 /* 91462 */ // (intrinsic_void 10638:{ *:[iPTR] }) => (FENCE)
31267 /* 91462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FENCE),
31268 /* 91465 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0,
31269 /* 91468 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31270 /* 91472 */ GIR_RootConstrainSelectedInstOperands,
31271 /* 91473 */ // GIR_Coverage, 1236,
31272 /* 91473 */ GIR_EraseRootFromParent_Done,
31273 /* 91474 */ // Label 1413: @91474
31274 /* 91474 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(91496), // Rule ID 1290 //
31275 /* 91479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsAIX),
31276 /* 91482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dssall),
31277 /* 91487 */ // (intrinsic_void 10279:{ *:[iPTR] }) => (NOP)
31278 /* 91487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOP),
31279 /* 91490 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31280 /* 91494 */ GIR_RootConstrainSelectedInstOperands,
31281 /* 91495 */ // GIR_Coverage, 1290,
31282 /* 91495 */ GIR_EraseRootFromParent_Done,
31283 /* 91496 */ // Label 1414: @91496
31284 /* 91496 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(91518), // Rule ID 1291 //
31285 /* 91501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotAIX),
31286 /* 91504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dssall),
31287 /* 91509 */ // (intrinsic_void 10279:{ *:[iPTR] }) => (DSSALL)
31288 /* 91509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSSALL),
31289 /* 91512 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31290 /* 91516 */ GIR_RootConstrainSelectedInstOperands,
31291 /* 91517 */ // GIR_Coverage, 1291,
31292 /* 91517 */ GIR_EraseRootFromParent_Done,
31293 /* 91518 */ // Label 1415: @91518
31294 /* 91518 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(91537), // Rule ID 4860 //
31295 /* 91523 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_isync),
31296 /* 91528 */ // (intrinsic_void 10663:{ *:[iPTR] }) => (ISYNC)
31297 /* 91528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ISYNC),
31298 /* 91531 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31299 /* 91535 */ GIR_RootConstrainSelectedInstOperands,
31300 /* 91536 */ // GIR_Coverage, 4860,
31301 /* 91536 */ GIR_EraseRootFromParent_Done,
31302 /* 91537 */ // Label 1416: @91537
31303 /* 91537 */ GIM_Reject,
31304 /* 91538 */ // Label 1401: @91538
31305 /* 91538 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(92421),
31306 /* 91543 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
31307 /* 91546 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(91585), // Rule ID 269 //
31308 /* 91551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31309 /* 91554 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dss),
31310 /* 91559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
31311 /* 91562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
31312 /* 91566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31313 /* 91570 */ // MIs[1] Operand 1
31314 /* 91570 */ // No operand predicates
31315 /* 91570 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31316 /* 91572 */ // (intrinsic_void 10278:{ *:[iPTR] }, (imm:{ *:[i32] }):$STRM) => (DSS (imm:{ *:[i32] }):$STRM)
31317 /* 91572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSS),
31318 /* 91575 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
31319 /* 91578 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31320 /* 91583 */ GIR_RootConstrainSelectedInstOperands,
31321 /* 91584 */ // GIR_Coverage, 269,
31322 /* 91584 */ GIR_EraseRootFromParent_Done,
31323 /* 91585 */ // Label 1418: @91585
31324 /* 91585 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(91611), // Rule ID 193 //
31325 /* 91590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
31326 /* 91593 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtfsb0),
31327 /* 91598 */ // MIs[0] FM
31328 /* 91598 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31329 /* 91601 */ // (intrinsic_void 10784:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM) => (MTFSB0 (timm:{ *:[i32] }):$FM)
31330 /* 91601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTFSB0),
31331 /* 91604 */ GIR_RootToRootCopy, /*OpIdx*/1, // FM
31332 /* 91606 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0,
31333 /* 91609 */ GIR_RootConstrainSelectedInstOperands,
31334 /* 91610 */ // GIR_Coverage, 193,
31335 /* 91610 */ GIR_EraseRootFromParent_Done,
31336 /* 91611 */ // Label 1419: @91611
31337 /* 91611 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(91637), // Rule ID 194 //
31338 /* 91616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
31339 /* 91619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtfsb1),
31340 /* 91624 */ // MIs[0] FM
31341 /* 91624 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31342 /* 91627 */ // (intrinsic_void 10785:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM) => (MTFSB1 (timm:{ *:[i32] }):$FM)
31343 /* 91627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTFSB1),
31344 /* 91630 */ GIR_RootToRootCopy, /*OpIdx*/1, // FM
31345 /* 91632 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0,
31346 /* 91635 */ GIR_RootConstrainSelectedInstOperands,
31347 /* 91636 */ // GIR_Coverage, 194,
31348 /* 91636 */ GIR_EraseRootFromParent_Done,
31349 /* 91637 */ // Label 1420: @91637
31350 /* 91637 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(91664), // Rule ID 278 //
31351 /* 91642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31352 /* 91645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mfvscr),
31353 /* 91650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31354 /* 91653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
31355 /* 91657 */ // (intrinsic_w_chain:{ *:[v8i16] } 10291:{ *:[iPTR] }) => (MFVSCR:{ *:[v8i16] })
31356 /* 91657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSCR),
31357 /* 91660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
31358 /* 91662 */ GIR_RootConstrainSelectedInstOperands,
31359 /* 91663 */ // GIR_Coverage, 278,
31360 /* 91663 */ GIR_EraseRootFromParent_Done,
31361 /* 91664 */ // Label 1421: @91664
31362 /* 91664 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(91688), // Rule ID 1237 //
31363 /* 91669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_readflm),
31364 /* 91674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31365 /* 91677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
31366 /* 91681 */ // (intrinsic_w_chain:{ *:[f64] } 10802:{ *:[iPTR] }) => (MFFS:{ *:[f64] })
31367 /* 91681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFFS),
31368 /* 91684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
31369 /* 91686 */ GIR_RootConstrainSelectedInstOperands,
31370 /* 91687 */ // GIR_Coverage, 1237,
31371 /* 91687 */ GIR_EraseRootFromParent_Done,
31372 /* 91688 */ // Label 1422: @91688
31373 /* 91688 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(91716), // Rule ID 1238 //
31374 /* 91693 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mffsl),
31375 /* 91698 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31376 /* 91701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
31377 /* 91705 */ // (intrinsic_w_chain:{ *:[f64] } 10678:{ *:[iPTR] }) => (MFFSL:{ *:[f64] })
31378 /* 91705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFFSL),
31379 /* 91708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
31380 /* 91710 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31381 /* 91714 */ GIR_RootConstrainSelectedInstOperands,
31382 /* 91715 */ // GIR_Coverage, 1238,
31383 /* 91715 */ GIR_EraseRootFromParent_Done,
31384 /* 91716 */ // Label 1423: @91716
31385 /* 91716 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(91780), // Rule ID 1574 //
31386 /* 91721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
31387 /* 91724 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_darn32),
31388 /* 91729 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31389 /* 91732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
31390 /* 91736 */ // (intrinsic_w_chain:{ *:[i32] } 10604:{ *:[iPTR] }) => (EXTRACT_SUBREG:{ *:[i32] } (DARN:{ *:[i64] } 0:{ *:[i32] }), sub_32:{ *:[i32] })
31391 /* 91736 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
31392 /* 91739 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::DARN),
31393 /* 91743 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31394 /* 91748 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
31395 /* 91751 */ GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31396 /* 91755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31397 /* 91757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
31398 /* 91760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31399 /* 91762 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
31400 /* 91769 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
31401 /* 91774 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
31402 /* 91779 */ // GIR_Coverage, 1574,
31403 /* 91779 */ GIR_EraseRootFromParent_Done,
31404 /* 91780 */ // Label 1424: @91780
31405 /* 91780 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(91814), // Rule ID 1575 //
31406 /* 91785 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
31407 /* 91788 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_darn),
31408 /* 91793 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31409 /* 91796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
31410 /* 91800 */ // (intrinsic_w_chain:{ *:[i64] } 10603:{ *:[iPTR] }) => (DARN:{ *:[i64] } 1:{ *:[i32] })
31411 /* 91800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DARN),
31412 /* 91803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
31413 /* 91805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
31414 /* 91808 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31415 /* 91812 */ GIR_RootConstrainSelectedInstOperands,
31416 /* 91813 */ // GIR_Coverage, 1575,
31417 /* 91813 */ GIR_EraseRootFromParent_Done,
31418 /* 91814 */ // Label 1425: @91814
31419 /* 91814 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(91848), // Rule ID 1576 //
31420 /* 91819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
31421 /* 91822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_darnraw),
31422 /* 91827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31423 /* 91830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
31424 /* 91834 */ // (intrinsic_w_chain:{ *:[i64] } 10605:{ *:[iPTR] }) => (DARN:{ *:[i64] } 2:{ *:[i32] })
31425 /* 91834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DARN),
31426 /* 91837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
31427 /* 91839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
31428 /* 91842 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31429 /* 91846 */ GIR_RootConstrainSelectedInstOperands,
31430 /* 91847 */ // GIR_Coverage, 1576,
31431 /* 91847 */ GIR_EraseRootFromParent_Done,
31432 /* 91848 */ // Label 1426: @91848
31433 /* 91848 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(91879), // Rule ID 2893 //
31434 /* 91853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31435 /* 91856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_tcheck),
31436 /* 91861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31437 /* 91864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
31438 /* 91868 */ // (intrinsic_w_chain:{ *:[i32] } 10832:{ *:[iPTR] }) => (TCHECK_RET:{ *:[i32] })
31439 /* 91868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::TCHECK_RET),
31440 /* 91871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
31441 /* 91873 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31442 /* 91877 */ GIR_RootConstrainSelectedInstOperands,
31443 /* 91878 */ // GIR_Coverage, 2893,
31444 /* 91878 */ GIR_EraseRootFromParent_Done,
31445 /* 91879 */ // Label 1427: @91879
31446 /* 91879 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(91920), // Rule ID 2897 //
31447 /* 91884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31448 /* 91887 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_get_texasr),
31449 /* 91892 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31450 /* 91895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
31451 /* 91899 */ // (intrinsic_w_chain:{ *:[i64] } 10654:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 130:{ *:[i32] })
31452 /* 91899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8),
31453 /* 91902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
31454 /* 91904 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(130),
31455 /* 91914 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31456 /* 91918 */ GIR_RootConstrainSelectedInstOperands,
31457 /* 91919 */ // GIR_Coverage, 2897,
31458 /* 91919 */ GIR_EraseRootFromParent_Done,
31459 /* 91920 */ // Label 1428: @91920
31460 /* 91920 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(91961), // Rule ID 2898 //
31461 /* 91925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31462 /* 91928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_get_texasru),
31463 /* 91933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31464 /* 91936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
31465 /* 91940 */ // (intrinsic_w_chain:{ *:[i64] } 10655:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 131:{ *:[i32] })
31466 /* 91940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8),
31467 /* 91943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
31468 /* 91945 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(131),
31469 /* 91955 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31470 /* 91959 */ GIR_RootConstrainSelectedInstOperands,
31471 /* 91960 */ // GIR_Coverage, 2898,
31472 /* 91960 */ GIR_EraseRootFromParent_Done,
31473 /* 91961 */ // Label 1429: @91961
31474 /* 91961 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(92002), // Rule ID 2899 //
31475 /* 91966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31476 /* 91969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_get_tfhar),
31477 /* 91974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31478 /* 91977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
31479 /* 91981 */ // (intrinsic_w_chain:{ *:[i64] } 10656:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 128:{ *:[i32] })
31480 /* 91981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8),
31481 /* 91984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
31482 /* 91986 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
31483 /* 91996 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31484 /* 92000 */ GIR_RootConstrainSelectedInstOperands,
31485 /* 92001 */ // GIR_Coverage, 2899,
31486 /* 92001 */ GIR_EraseRootFromParent_Done,
31487 /* 92002 */ // Label 1430: @92002
31488 /* 92002 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(92043), // Rule ID 2900 //
31489 /* 92007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31490 /* 92010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_get_tfiar),
31491 /* 92015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31492 /* 92018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
31493 /* 92022 */ // (intrinsic_w_chain:{ *:[i64] } 10657:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 129:{ *:[i32] })
31494 /* 92022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8),
31495 /* 92025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
31496 /* 92027 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(129),
31497 /* 92037 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31498 /* 92041 */ GIR_RootConstrainSelectedInstOperands,
31499 /* 92042 */ // GIR_Coverage, 2900,
31500 /* 92042 */ GIR_EraseRootFromParent_Done,
31501 /* 92043 */ // Label 1431: @92043
31502 /* 92043 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(92074), // Rule ID 4910 //
31503 /* 92048 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtmsr),
31504 /* 92053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
31505 /* 92056 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
31506 /* 92060 */ // (intrinsic_void 10788:{ *:[iPTR] }, gprc:{ *:[i32] }:$RS) => (MTMSR ?:{ *:[i32] }:$RS, 0:{ *:[i32] })
31507 /* 92060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTMSR),
31508 /* 92063 */ GIR_RootToRootCopy, /*OpIdx*/1, // RS
31509 /* 92065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31510 /* 92068 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31511 /* 92072 */ GIR_RootConstrainSelectedInstOperands,
31512 /* 92073 */ // GIR_Coverage, 4910,
31513 /* 92073 */ GIR_EraseRootFromParent_Done,
31514 /* 92074 */ // Label 1432: @92074
31515 /* 92074 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(92101), // Rule ID 189 //
31516 /* 92079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::set_loop_iterations),
31517 /* 92084 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
31518 /* 92087 */ // (intrinsic_void 326:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (MTCTRloop:{ *:[i32] } i32:{ *:[i32] }:$RST)
31519 /* 92087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTCTRloop),
31520 /* 92090 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
31521 /* 92092 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CTR*/0,
31522 /* 92095 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31523 /* 92099 */ GIR_RootConstrainSelectedInstOperands,
31524 /* 92100 */ // GIR_Coverage, 189,
31525 /* 92100 */ GIR_EraseRootFromParent_Done,
31526 /* 92101 */ // Label 1433: @92101
31527 /* 92101 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(92124), // Rule ID 279 //
31528 /* 92106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31529 /* 92109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_mtvscr),
31530 /* 92114 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
31531 /* 92117 */ // (intrinsic_void 10292:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (MTVSCR v4i32:{ *:[v4i32] }:$VB)
31532 /* 92117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSCR),
31533 /* 92120 */ GIR_RootToRootCopy, /*OpIdx*/1, // VB
31534 /* 92122 */ GIR_RootConstrainSelectedInstOperands,
31535 /* 92123 */ // GIR_Coverage, 279,
31536 /* 92123 */ GIR_EraseRootFromParent_Done,
31537 /* 92124 */ // Label 1434: @92124
31538 /* 92124 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(92151), // Rule ID 637 //
31539 /* 92129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::set_loop_iterations),
31540 /* 92134 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
31541 /* 92137 */ // (intrinsic_void 326:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (MTCTR8loop:{ *:[i64] } i64:{ *:[i64] }:$RST)
31542 /* 92137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTCTR8loop),
31543 /* 92140 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
31544 /* 92142 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CTR8*/0,
31545 /* 92145 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31546 /* 92149 */ GIR_RootConstrainSelectedInstOperands,
31547 /* 92150 */ // GIR_Coverage, 637,
31548 /* 92150 */ GIR_EraseRootFromParent_Done,
31549 /* 92151 */ // Label 1435: @92151
31550 /* 92151 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(92188), // Rule ID 2901 //
31551 /* 92156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31552 /* 92159 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_set_texasr),
31553 /* 92164 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
31554 /* 92167 */ // (intrinsic_void 10808:{ *:[iPTR] }, i64:{ *:[i64] }:$V) => (MTSPR8 130:{ *:[i32] }, ?:{ *:[i64] }:$V)
31555 /* 92167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8),
31556 /* 92170 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(130),
31557 /* 92180 */ GIR_RootToRootCopy, /*OpIdx*/1, // V
31558 /* 92182 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31559 /* 92186 */ GIR_RootConstrainSelectedInstOperands,
31560 /* 92187 */ // GIR_Coverage, 2901,
31561 /* 92187 */ GIR_EraseRootFromParent_Done,
31562 /* 92188 */ // Label 1436: @92188
31563 /* 92188 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(92225), // Rule ID 2902 //
31564 /* 92193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31565 /* 92196 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_set_texasru),
31566 /* 92201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
31567 /* 92204 */ // (intrinsic_void 10809:{ *:[iPTR] }, i64:{ *:[i64] }:$V) => (MTSPR8 131:{ *:[i32] }, ?:{ *:[i64] }:$V)
31568 /* 92204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8),
31569 /* 92207 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(131),
31570 /* 92217 */ GIR_RootToRootCopy, /*OpIdx*/1, // V
31571 /* 92219 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31572 /* 92223 */ GIR_RootConstrainSelectedInstOperands,
31573 /* 92224 */ // GIR_Coverage, 2902,
31574 /* 92224 */ GIR_EraseRootFromParent_Done,
31575 /* 92225 */ // Label 1437: @92225
31576 /* 92225 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(92262), // Rule ID 2903 //
31577 /* 92230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31578 /* 92233 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_set_tfhar),
31579 /* 92238 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
31580 /* 92241 */ // (intrinsic_void 10810:{ *:[iPTR] }, i64:{ *:[i64] }:$V) => (MTSPR8 128:{ *:[i32] }, ?:{ *:[i64] }:$V)
31581 /* 92241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8),
31582 /* 92244 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
31583 /* 92254 */ GIR_RootToRootCopy, /*OpIdx*/1, // V
31584 /* 92256 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31585 /* 92260 */ GIR_RootConstrainSelectedInstOperands,
31586 /* 92261 */ // GIR_Coverage, 2903,
31587 /* 92261 */ GIR_EraseRootFromParent_Done,
31588 /* 92262 */ // Label 1438: @92262
31589 /* 92262 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(92299), // Rule ID 2904 //
31590 /* 92267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31591 /* 92270 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_set_tfiar),
31592 /* 92275 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
31593 /* 92278 */ // (intrinsic_void 10811:{ *:[iPTR] }, i64:{ *:[i64] }:$V) => (MTSPR8 129:{ *:[i32] }, ?:{ *:[i64] }:$V)
31594 /* 92278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8),
31595 /* 92281 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(129),
31596 /* 92291 */ GIR_RootToRootCopy, /*OpIdx*/1, // V
31597 /* 92293 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31598 /* 92297 */ GIR_RootConstrainSelectedInstOperands,
31599 /* 92298 */ // GIR_Coverage, 2904,
31600 /* 92298 */ GIR_EraseRootFromParent_Done,
31601 /* 92299 */ // Label 1439: @92299
31602 /* 92299 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(92327), // Rule ID 2895 //
31603 /* 92304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31604 /* 92307 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_trechkpt),
31605 /* 92312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31606 /* 92315 */ // (intrinsic_w_chain:{ *:[i32] } 10839:{ *:[iPTR] }) => (TRECHKPT:{ *:[i32] })
31607 /* 92315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::TRECHKPT),
31608 /* 92318 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
31609 /* 92321 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31610 /* 92325 */ GIR_RootConstrainSelectedInstOperands,
31611 /* 92326 */ // GIR_Coverage, 2895,
31612 /* 92326 */ GIR_EraseRootFromParent_Done,
31613 /* 92327 */ // Label 1440: @92327
31614 /* 92327 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(92358), // Rule ID 2905 //
31615 /* 92332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31616 /* 92335 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_tendall),
31617 /* 92340 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31618 /* 92343 */ // (intrinsic_w_chain:{ *:[i32] } 10835:{ *:[iPTR] }) => (TEND:{ *:[i32] } 1:{ *:[i32] })
31619 /* 92343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::TEND),
31620 /* 92346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
31621 /* 92349 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
31622 /* 92352 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31623 /* 92356 */ GIR_RootConstrainSelectedInstOperands,
31624 /* 92357 */ // GIR_Coverage, 2905,
31625 /* 92357 */ GIR_EraseRootFromParent_Done,
31626 /* 92358 */ // Label 1441: @92358
31627 /* 92358 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(92389), // Rule ID 2906 //
31628 /* 92363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31629 /* 92366 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_tresume),
31630 /* 92371 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31631 /* 92374 */ // (intrinsic_w_chain:{ *:[i32] } 10841:{ *:[iPTR] }) => (TSR:{ *:[i32] } 1:{ *:[i32] })
31632 /* 92374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::TSR),
31633 /* 92377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
31634 /* 92380 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
31635 /* 92383 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31636 /* 92387 */ GIR_RootConstrainSelectedInstOperands,
31637 /* 92388 */ // GIR_Coverage, 2906,
31638 /* 92388 */ GIR_EraseRootFromParent_Done,
31639 /* 92389 */ // Label 1442: @92389
31640 /* 92389 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(92420), // Rule ID 2907 //
31641 /* 92394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31642 /* 92397 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_tsuspend),
31643 /* 92402 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31644 /* 92405 */ // (intrinsic_w_chain:{ *:[i32] } 10844:{ *:[iPTR] }) => (TSR:{ *:[i32] } 0:{ *:[i32] })
31645 /* 92405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::TSR),
31646 /* 92408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31647 /* 92411 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
31648 /* 92414 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31649 /* 92418 */ GIR_RootConstrainSelectedInstOperands,
31650 /* 92419 */ // GIR_Coverage, 2907,
31651 /* 92419 */ GIR_EraseRootFromParent_Done,
31652 /* 92420 */ // Label 1443: @92420
31653 /* 92420 */ GIM_Reject,
31654 /* 92421 */ // Label 1417: @92421
31655 /* 92421 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(92947),
31656 /* 92426 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
31657 /* 92429 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(92460), // Rule ID 1178 //
31658 /* 92434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
31659 /* 92437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtfsfi),
31660 /* 92442 */ // MIs[0] BF
31661 /* 92442 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31662 /* 92445 */ // MIs[0] U
31663 /* 92445 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
31664 /* 92448 */ // (intrinsic_void 10787:{ *:[iPTR] }, (timm:{ *:[i32] }):$BF, (timm:{ *:[i32] }):$U) => (MTFSFIb (timm:{ *:[i32] }):$BF, (timm:{ *:[i32] }):$U)
31665 /* 92448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTFSFIb),
31666 /* 92451 */ GIR_RootToRootCopy, /*OpIdx*/1, // BF
31667 /* 92453 */ GIR_RootToRootCopy, /*OpIdx*/2, // U
31668 /* 92455 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0,
31669 /* 92458 */ GIR_RootConstrainSelectedInstOperands,
31670 /* 92459 */ // GIR_Coverage, 1178,
31671 /* 92459 */ GIR_EraseRootFromParent_Done,
31672 /* 92460 */ // Label 1445: @92460
31673 /* 92460 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(92508), // Rule ID 12 //
31674 /* 92465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setrnd),
31675 /* 92470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31676 /* 92473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31677 /* 92476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
31678 /* 92480 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
31679 /* 92484 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31680 /* 92488 */ // MIs[1] Operand 1
31681 /* 92488 */ // No operand predicates
31682 /* 92488 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31683 /* 92490 */ // (intrinsic_w_chain:{ *:[f64] } 10814:{ *:[iPTR] }, (imm:{ *:[i32] }):$RND) => (SETRNDi:{ *:[f64] } (imm:{ *:[i32] }):$RND)
31684 /* 92490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETRNDi),
31685 /* 92493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
31686 /* 92495 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // RND
31687 /* 92498 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0,
31688 /* 92501 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31689 /* 92506 */ GIR_RootConstrainSelectedInstOperands,
31690 /* 92507 */ // GIR_Coverage, 12,
31691 /* 92507 */ GIR_EraseRootFromParent_Done,
31692 /* 92508 */ // Label 1446: @92508
31693 /* 92508 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(92556), // Rule ID 190 //
31694 /* 92513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::loop_decrement),
31695 /* 92518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
31696 /* 92521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31697 /* 92524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
31698 /* 92528 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
31699 /* 92532 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31700 /* 92536 */ // MIs[1] Operand 1
31701 /* 92536 */ // No operand predicates
31702 /* 92536 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31703 /* 92538 */ // (intrinsic_w_chain:{ *:[i1] } 224:{ *:[iPTR] }, (imm:{ *:[i32] }):$stride) => (DecreaseCTRloop:{ *:[i1] }:{ *:[i32] } (imm:{ *:[i32] }):$stride)
31704 /* 92538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DecreaseCTRloop),
31705 /* 92541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rT]
31706 /* 92543 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // stride
31707 /* 92546 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CTR*/0,
31708 /* 92549 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31709 /* 92554 */ GIR_RootConstrainSelectedInstOperands,
31710 /* 92555 */ // GIR_Coverage, 190,
31711 /* 92555 */ GIR_EraseRootFromParent_Done,
31712 /* 92556 */ // Label 1447: @92556
31713 /* 92556 */ GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(92604), // Rule ID 638 //
31714 /* 92561 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::loop_decrement),
31715 /* 92566 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
31716 /* 92569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
31717 /* 92572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
31718 /* 92576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
31719 /* 92580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31720 /* 92584 */ // MIs[1] Operand 1
31721 /* 92584 */ // No operand predicates
31722 /* 92584 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31723 /* 92586 */ // (intrinsic_w_chain:{ *:[i1] } 224:{ *:[iPTR] }, (imm:{ *:[i64] }):$stride) => (DecreaseCTR8loop:{ *:[i1] }:{ *:[i64] } (imm:{ *:[i64] }):$stride)
31724 /* 92586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DecreaseCTR8loop),
31725 /* 92589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rT]
31726 /* 92591 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // stride
31727 /* 92594 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CTR8*/0,
31728 /* 92597 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31729 /* 92602 */ GIR_RootConstrainSelectedInstOperands,
31730 /* 92603 */ // GIR_Coverage, 638,
31731 /* 92603 */ GIR_EraseRootFromParent_Done,
31732 /* 92604 */ // Label 1448: @92604
31733 /* 92604 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(92637), // Rule ID 1179 //
31734 /* 92609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fixed_addr_ld),
31735 /* 92614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31736 /* 92617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
31737 /* 92621 */ // MIs[0] imm
31738 /* 92621 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
31739 /* 92624 */ // (intrinsic_w_chain:{ *:[i32] } 10639:{ *:[iPTR] }, (timm:{ *:[i32] }):$imm) => (PPCLdFixedAddr:{ *:[i32] } (timm:{ *:[i32] }):$imm)
31740 /* 92624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PPCLdFixedAddr),
31741 /* 92627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rT]
31742 /* 92629 */ GIR_RootToRootCopy, /*OpIdx*/2, // imm
31743 /* 92631 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31744 /* 92635 */ GIR_RootConstrainSelectedInstOperands,
31745 /* 92636 */ // GIR_Coverage, 1179,
31746 /* 92636 */ GIR_EraseRootFromParent_Done,
31747 /* 92637 */ // Label 1449: @92637
31748 /* 92637 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(92670), // Rule ID 1580 //
31749 /* 92642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mfspr),
31750 /* 92647 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31751 /* 92650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
31752 /* 92654 */ // MIs[0] SPR
31753 /* 92654 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
31754 /* 92657 */ // (intrinsic_w_chain:{ *:[i64] } 10680:{ *:[iPTR] }, (timm:{ *:[i32] }):$SPR) => (MFSPR8:{ *:[i64] } ?:{ *:[i32] }:$SPR)
31755 /* 92657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8),
31756 /* 92660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
31757 /* 92662 */ GIR_RootToRootCopy, /*OpIdx*/2, // SPR
31758 /* 92664 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31759 /* 92668 */ GIR_RootConstrainSelectedInstOperands,
31760 /* 92669 */ // GIR_Coverage, 1580,
31761 /* 92669 */ GIR_EraseRootFromParent_Done,
31762 /* 92670 */ // Label 1450: @92670
31763 /* 92670 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(92703), // Rule ID 4908 //
31764 /* 92675 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mfspr),
31765 /* 92680 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31766 /* 92683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
31767 /* 92687 */ // MIs[0] SPR
31768 /* 92687 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
31769 /* 92690 */ // (intrinsic_w_chain:{ *:[i32] } 10680:{ *:[iPTR] }, (timm:{ *:[i32] }):$SPR) => (MFSPR:{ *:[i32] } ?:{ *:[i32] }:$SPR)
31770 /* 92690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR),
31771 /* 92693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
31772 /* 92695 */ GIR_RootToRootCopy, /*OpIdx*/2, // SPR
31773 /* 92697 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31774 /* 92701 */ GIR_RootConstrainSelectedInstOperands,
31775 /* 92702 */ // GIR_Coverage, 4908,
31776 /* 92702 */ GIR_EraseRootFromParent_Done,
31777 /* 92703 */ // Label 1451: @92703
31778 /* 92703 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(92736), // Rule ID 1581 //
31779 /* 92708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtspr),
31780 /* 92713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
31781 /* 92716 */ // MIs[0] SPR
31782 /* 92716 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31783 /* 92719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
31784 /* 92723 */ // (intrinsic_void 10789:{ *:[iPTR] }, (timm:{ *:[i32] }):$SPR, g8rc:{ *:[i64] }:$RT) => (MTSPR8 ?:{ *:[i32] }:$SPR, ?:{ *:[i64] }:$RT)
31785 /* 92723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8),
31786 /* 92726 */ GIR_RootToRootCopy, /*OpIdx*/1, // SPR
31787 /* 92728 */ GIR_RootToRootCopy, /*OpIdx*/2, // RT
31788 /* 92730 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31789 /* 92734 */ GIR_RootConstrainSelectedInstOperands,
31790 /* 92735 */ // GIR_Coverage, 1581,
31791 /* 92735 */ GIR_EraseRootFromParent_Done,
31792 /* 92736 */ // Label 1452: @92736
31793 /* 92736 */ GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(92769), // Rule ID 4909 //
31794 /* 92741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtspr),
31795 /* 92746 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31796 /* 92749 */ // MIs[0] SPR
31797 /* 92749 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31798 /* 92752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
31799 /* 92756 */ // (intrinsic_void 10789:{ *:[iPTR] }, (timm:{ *:[i32] }):$SPR, gprc:{ *:[i32] }:$RT) => (MTSPR ?:{ *:[i32] }:$SPR, ?:{ *:[i32] }:$RT)
31800 /* 92756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR),
31801 /* 92759 */ GIR_RootToRootCopy, /*OpIdx*/1, // SPR
31802 /* 92761 */ GIR_RootToRootCopy, /*OpIdx*/2, // RT
31803 /* 92763 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31804 /* 92767 */ GIR_RootConstrainSelectedInstOperands,
31805 /* 92768 */ // GIR_Coverage, 4909,
31806 /* 92768 */ GIR_EraseRootFromParent_Done,
31807 /* 92769 */ // Label 1453: @92769
31808 /* 92769 */ GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(92800), // Rule ID 195 //
31809 /* 92774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
31810 /* 92777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtfsf),
31811 /* 92782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
31812 /* 92785 */ // MIs[0] FM
31813 /* 92785 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
31814 /* 92788 */ // (intrinsic_void 10786:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM, f64:{ *:[f64] }:$RT) => (MTFSFb (timm:{ *:[i32] }):$FM, f64:{ *:[f64] }:$RT)
31815 /* 92788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTFSFb),
31816 /* 92791 */ GIR_RootToRootCopy, /*OpIdx*/1, // FM
31817 /* 92793 */ GIR_RootToRootCopy, /*OpIdx*/2, // RT
31818 /* 92795 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0,
31819 /* 92798 */ GIR_RootConstrainSelectedInstOperands,
31820 /* 92799 */ // GIR_Coverage, 195,
31821 /* 92799 */ GIR_EraseRootFromParent_Done,
31822 /* 92800 */ // Label 1454: @92800
31823 /* 92800 */ GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(92840), // Rule ID 13 //
31824 /* 92805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setrnd),
31825 /* 92810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31826 /* 92813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31827 /* 92816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
31828 /* 92820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
31829 /* 92824 */ // (intrinsic_w_chain:{ *:[f64] } 10814:{ *:[iPTR] }, gprc:{ *:[i32] }:$in) => (SETRND:{ *:[f64] } gprc:{ *:[i32] }:$in)
31830 /* 92824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETRND),
31831 /* 92827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
31832 /* 92829 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31833 /* 92831 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0,
31834 /* 92834 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31835 /* 92838 */ GIR_RootConstrainSelectedInstOperands,
31836 /* 92839 */ // GIR_Coverage, 13,
31837 /* 92839 */ GIR_EraseRootFromParent_Done,
31838 /* 92840 */ // Label 1455: @92840
31839 /* 92840 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(92880), // Rule ID 14 //
31840 /* 92845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setflm),
31841 /* 92850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
31842 /* 92853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
31843 /* 92856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
31844 /* 92860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
31845 /* 92864 */ // (intrinsic_w_chain:{ *:[f64] } 10813:{ *:[iPTR] }, f8rc:{ *:[f64] }:$FLM) => (SETFLM:{ *:[f64] } f8rc:{ *:[f64] }:$FLM)
31846 /* 92864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETFLM),
31847 /* 92867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
31848 /* 92869 */ GIR_RootToRootCopy, /*OpIdx*/2, // FLM
31849 /* 92871 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0,
31850 /* 92874 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31851 /* 92878 */ GIR_RootConstrainSelectedInstOperands,
31852 /* 92879 */ // GIR_Coverage, 14,
31853 /* 92879 */ GIR_EraseRootFromParent_Done,
31854 /* 92880 */ // Label 1456: @92880
31855 /* 92880 */ GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(92913), // Rule ID 2888 //
31856 /* 92885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31857 /* 92888 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_tabort),
31858 /* 92893 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31859 /* 92896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31860 /* 92899 */ // (intrinsic_w_chain:{ *:[i32] } 10826:{ *:[iPTR] }, i32:{ *:[i32] }:$R) => (TABORT:{ *:[i32] } ?:{ *:[i32] }:$R)
31861 /* 92899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::TABORT),
31862 /* 92902 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
31863 /* 92904 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
31864 /* 92907 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31865 /* 92911 */ GIR_RootConstrainSelectedInstOperands,
31866 /* 92912 */ // GIR_Coverage, 2888,
31867 /* 92912 */ GIR_EraseRootFromParent_Done,
31868 /* 92913 */ // Label 1457: @92913
31869 /* 92913 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(92946), // Rule ID 2894 //
31870 /* 92918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM),
31871 /* 92921 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_treclaim),
31872 /* 92926 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31873 /* 92929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31874 /* 92932 */ // (intrinsic_w_chain:{ *:[i32] } 10840:{ *:[iPTR] }, i32:{ *:[i32] }:$RA) => (TRECLAIM:{ *:[i32] } ?:{ *:[i32] }:$RA)
31875 /* 92932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::TRECLAIM),
31876 /* 92935 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
31877 /* 92937 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
31878 /* 92940 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31879 /* 92944 */ GIR_RootConstrainSelectedInstOperands,
31880 /* 92945 */ // GIR_Coverage, 2894,
31881 /* 92945 */ GIR_EraseRootFromParent_Done,
31882 /* 92946 */ // Label 1458: @92946
31883 /* 92946 */ GIM_Reject,
31884 /* 92947 */ // Label 1444: @92947
31885 /* 92947 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(93874),
31886 /* 92952 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
31887 /* 92955 */ GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(93005), // Rule ID 270 //
31888 /* 92960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31889 /* 92963 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dst),
31890 /* 92968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31891 /* 92971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31892 /* 92974 */ // MIs[0] RA
31893 /* 92974 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
31894 /* 92978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
31895 /* 92982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31896 /* 92986 */ // MIs[1] Operand 1
31897 /* 92986 */ // No operand predicates
31898 /* 92986 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31899 /* 92988 */ // (intrinsic_void 10280:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DST (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
31900 /* 92988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DST),
31901 /* 92991 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
31902 /* 92994 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
31903 /* 92996 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
31904 /* 92998 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31905 /* 93003 */ GIR_RootConstrainSelectedInstOperands,
31906 /* 93004 */ // GIR_Coverage, 270,
31907 /* 93004 */ GIR_EraseRootFromParent_Done,
31908 /* 93005 */ // Label 1460: @93005
31909 /* 93005 */ GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(93055), // Rule ID 271 //
31910 /* 93010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31911 /* 93013 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dstt),
31912 /* 93018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31913 /* 93021 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31914 /* 93024 */ // MIs[0] RA
31915 /* 93024 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
31916 /* 93028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
31917 /* 93032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31918 /* 93036 */ // MIs[1] Operand 1
31919 /* 93036 */ // No operand predicates
31920 /* 93036 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31921 /* 93038 */ // (intrinsic_void 10283:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTT (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
31922 /* 93038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTT),
31923 /* 93041 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
31924 /* 93044 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
31925 /* 93046 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
31926 /* 93048 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31927 /* 93053 */ GIR_RootConstrainSelectedInstOperands,
31928 /* 93054 */ // GIR_Coverage, 271,
31929 /* 93054 */ GIR_EraseRootFromParent_Done,
31930 /* 93055 */ // Label 1461: @93055
31931 /* 93055 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(93105), // Rule ID 272 //
31932 /* 93060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31933 /* 93063 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dstst),
31934 /* 93068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31935 /* 93071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31936 /* 93074 */ // MIs[0] RA
31937 /* 93074 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
31938 /* 93078 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
31939 /* 93082 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31940 /* 93086 */ // MIs[1] Operand 1
31941 /* 93086 */ // No operand predicates
31942 /* 93086 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31943 /* 93088 */ // (intrinsic_void 10281:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTST (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
31944 /* 93088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTST),
31945 /* 93091 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
31946 /* 93094 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
31947 /* 93096 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
31948 /* 93098 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31949 /* 93103 */ GIR_RootConstrainSelectedInstOperands,
31950 /* 93104 */ // GIR_Coverage, 272,
31951 /* 93104 */ GIR_EraseRootFromParent_Done,
31952 /* 93105 */ // Label 1462: @93105
31953 /* 93105 */ GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(93155), // Rule ID 273 //
31954 /* 93110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31955 /* 93113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dststt),
31956 /* 93118 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31957 /* 93121 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31958 /* 93124 */ // MIs[0] RA
31959 /* 93124 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
31960 /* 93128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
31961 /* 93132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31962 /* 93136 */ // MIs[1] Operand 1
31963 /* 93136 */ // No operand predicates
31964 /* 93136 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31965 /* 93138 */ // (intrinsic_void 10282:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTSTT (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
31966 /* 93138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTSTT),
31967 /* 93141 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
31968 /* 93144 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
31969 /* 93146 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
31970 /* 93148 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31971 /* 93153 */ GIR_RootConstrainSelectedInstOperands,
31972 /* 93154 */ // GIR_Coverage, 273,
31973 /* 93154 */ GIR_EraseRootFromParent_Done,
31974 /* 93155 */ // Label 1463: @93155
31975 /* 93155 */ GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(93205), // Rule ID 274 //
31976 /* 93160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31977 /* 93163 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dst),
31978 /* 93168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31979 /* 93171 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31980 /* 93174 */ // MIs[0] RA
31981 /* 93174 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
31982 /* 93178 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
31983 /* 93182 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31984 /* 93186 */ // MIs[1] Operand 1
31985 /* 93186 */ // No operand predicates
31986 /* 93186 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31987 /* 93188 */ // (intrinsic_void 10280:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DST64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB)
31988 /* 93188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DST64),
31989 /* 93191 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
31990 /* 93194 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
31991 /* 93196 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
31992 /* 93198 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
31993 /* 93203 */ GIR_RootConstrainSelectedInstOperands,
31994 /* 93204 */ // GIR_Coverage, 274,
31995 /* 93204 */ GIR_EraseRootFromParent_Done,
31996 /* 93205 */ // Label 1464: @93205
31997 /* 93205 */ GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(93255), // Rule ID 275 //
31998 /* 93210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
31999 /* 93213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dstt),
32000 /* 93218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32001 /* 93221 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32002 /* 93224 */ // MIs[0] RA
32003 /* 93224 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32004 /* 93228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
32005 /* 93232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32006 /* 93236 */ // MIs[1] Operand 1
32007 /* 93236 */ // No operand predicates
32008 /* 93236 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32009 /* 93238 */ // (intrinsic_void 10283:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTT64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB)
32010 /* 93238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTT64),
32011 /* 93241 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
32012 /* 93244 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
32013 /* 93246 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
32014 /* 93248 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32015 /* 93253 */ GIR_RootConstrainSelectedInstOperands,
32016 /* 93254 */ // GIR_Coverage, 275,
32017 /* 93254 */ GIR_EraseRootFromParent_Done,
32018 /* 93255 */ // Label 1465: @93255
32019 /* 93255 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(93305), // Rule ID 276 //
32020 /* 93260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32021 /* 93263 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dstst),
32022 /* 93268 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32023 /* 93271 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32024 /* 93274 */ // MIs[0] RA
32025 /* 93274 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32026 /* 93278 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
32027 /* 93282 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32028 /* 93286 */ // MIs[1] Operand 1
32029 /* 93286 */ // No operand predicates
32030 /* 93286 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32031 /* 93288 */ // (intrinsic_void 10281:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTST64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB)
32032 /* 93288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTST64),
32033 /* 93291 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
32034 /* 93294 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
32035 /* 93296 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
32036 /* 93298 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32037 /* 93303 */ GIR_RootConstrainSelectedInstOperands,
32038 /* 93304 */ // GIR_Coverage, 276,
32039 /* 93304 */ GIR_EraseRootFromParent_Done,
32040 /* 93305 */ // Label 1466: @93305
32041 /* 93305 */ GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(93355), // Rule ID 277 //
32042 /* 93310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32043 /* 93313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dststt),
32044 /* 93318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32045 /* 93321 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32046 /* 93324 */ // MIs[0] RA
32047 /* 93324 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32048 /* 93328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
32049 /* 93332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32050 /* 93336 */ // MIs[1] Operand 1
32051 /* 93336 */ // No operand predicates
32052 /* 93336 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32053 /* 93338 */ // (intrinsic_void 10282:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTSTT64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB)
32054 /* 93338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTSTT64),
32055 /* 93341 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM
32056 /* 93344 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
32057 /* 93346 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
32058 /* 93348 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32059 /* 93353 */ GIR_RootConstrainSelectedInstOperands,
32060 /* 93354 */ // GIR_Coverage, 277,
32061 /* 93354 */ GIR_EraseRootFromParent_Done,
32062 /* 93355 */ // Label 1467: @93355
32063 /* 93355 */ GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(93392), // Rule ID 380 //
32064 /* 93360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32065 /* 93363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsumsws),
32066 /* 93368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32067 /* 93371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32068 /* 93374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32069 /* 93377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32070 /* 93381 */ // (intrinsic_w_chain:{ *:[v4i32] } 10562:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUMSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
32071 /* 93381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUMSWS),
32072 /* 93384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32073 /* 93386 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32074 /* 93388 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32075 /* 93390 */ GIR_RootConstrainSelectedInstOperands,
32076 /* 93391 */ // GIR_Coverage, 380,
32077 /* 93391 */ GIR_EraseRootFromParent_Done,
32078 /* 93392 */ // Label 1468: @93392
32079 /* 93392 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(93429), // Rule ID 381 //
32080 /* 93397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32081 /* 93400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsum2sws),
32082 /* 93405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32083 /* 93408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32084 /* 93411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32085 /* 93414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32086 /* 93418 */ // (intrinsic_w_chain:{ *:[v4i32] } 10558:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUM2SWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
32087 /* 93418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUM2SWS),
32088 /* 93421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32089 /* 93423 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32090 /* 93425 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32091 /* 93427 */ GIR_RootConstrainSelectedInstOperands,
32092 /* 93428 */ // GIR_Coverage, 381,
32093 /* 93428 */ GIR_EraseRootFromParent_Done,
32094 /* 93429 */ // Label 1469: @93429
32095 /* 93429 */ GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(93466), // Rule ID 382 //
32096 /* 93434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32097 /* 93437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsum4sbs),
32098 /* 93442 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32099 /* 93445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
32100 /* 93448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32101 /* 93451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32102 /* 93455 */ // (intrinsic_w_chain:{ *:[v4i32] } 10559:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUM4SBS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$VA, v4i32:{ *:[v4i32] }:$VB)
32103 /* 93455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUM4SBS),
32104 /* 93458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32105 /* 93460 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32106 /* 93462 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32107 /* 93464 */ GIR_RootConstrainSelectedInstOperands,
32108 /* 93465 */ // GIR_Coverage, 382,
32109 /* 93465 */ GIR_EraseRootFromParent_Done,
32110 /* 93466 */ // Label 1470: @93466
32111 /* 93466 */ GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(93503), // Rule ID 383 //
32112 /* 93471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32113 /* 93474 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsum4shs),
32114 /* 93479 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32115 /* 93482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32116 /* 93485 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32117 /* 93488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32118 /* 93492 */ // (intrinsic_w_chain:{ *:[v4i32] } 10560:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUM4SHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v4i32:{ *:[v4i32] }:$VB)
32119 /* 93492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUM4SHS),
32120 /* 93495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32121 /* 93497 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32122 /* 93499 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32123 /* 93501 */ GIR_RootConstrainSelectedInstOperands,
32124 /* 93502 */ // GIR_Coverage, 383,
32125 /* 93502 */ GIR_EraseRootFromParent_Done,
32126 /* 93503 */ // Label 1471: @93503
32127 /* 93503 */ GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(93540), // Rule ID 384 //
32128 /* 93508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32129 /* 93511 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsum4ubs),
32130 /* 93516 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32131 /* 93519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
32132 /* 93522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32133 /* 93525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32134 /* 93529 */ // (intrinsic_w_chain:{ *:[v4i32] } 10561:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUM4UBS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$VA, v4i32:{ *:[v4i32] }:$VB)
32135 /* 93529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUM4UBS),
32136 /* 93532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32137 /* 93534 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32138 /* 93536 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32139 /* 93538 */ GIR_RootConstrainSelectedInstOperands,
32140 /* 93539 */ // GIR_Coverage, 384,
32141 /* 93539 */ GIR_EraseRootFromParent_Done,
32142 /* 93540 */ // Label 1472: @93540
32143 /* 93540 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(93577), // Rule ID 411 //
32144 /* 93545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32145 /* 93548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkshss),
32146 /* 93553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
32147 /* 93556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32148 /* 93559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32149 /* 93562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32150 /* 93566 */ // (intrinsic_w_chain:{ *:[v16i8] } 10496:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPKSHSS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
32151 /* 93566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSHSS),
32152 /* 93569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32153 /* 93571 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32154 /* 93573 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32155 /* 93575 */ GIR_RootConstrainSelectedInstOperands,
32156 /* 93576 */ // GIR_Coverage, 411,
32157 /* 93576 */ GIR_EraseRootFromParent_Done,
32158 /* 93577 */ // Label 1473: @93577
32159 /* 93577 */ GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(93614), // Rule ID 412 //
32160 /* 93582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32161 /* 93585 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkshus),
32162 /* 93590 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
32163 /* 93593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32164 /* 93596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32165 /* 93599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32166 /* 93603 */ // (intrinsic_w_chain:{ *:[v16i8] } 10497:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPKSHUS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
32167 /* 93603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSHUS),
32168 /* 93606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32169 /* 93608 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32170 /* 93610 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32171 /* 93612 */ GIR_RootConstrainSelectedInstOperands,
32172 /* 93613 */ // GIR_Coverage, 412,
32173 /* 93613 */ GIR_EraseRootFromParent_Done,
32174 /* 93614 */ // Label 1474: @93614
32175 /* 93614 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(93651), // Rule ID 413 //
32176 /* 93619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32177 /* 93622 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkswss),
32178 /* 93627 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32179 /* 93630 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32180 /* 93633 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32181 /* 93636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32182 /* 93640 */ // (intrinsic_w_chain:{ *:[v8i16] } 10498:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKSWSS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
32183 /* 93640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSWSS),
32184 /* 93643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32185 /* 93645 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32186 /* 93647 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32187 /* 93649 */ GIR_RootConstrainSelectedInstOperands,
32188 /* 93650 */ // GIR_Coverage, 413,
32189 /* 93650 */ GIR_EraseRootFromParent_Done,
32190 /* 93651 */ // Label 1475: @93651
32191 /* 93651 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(93688), // Rule ID 414 //
32192 /* 93656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32193 /* 93659 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkswus),
32194 /* 93664 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32195 /* 93667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32196 /* 93670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32197 /* 93673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32198 /* 93677 */ // (intrinsic_w_chain:{ *:[v8i16] } 10499:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKSWUS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
32199 /* 93677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSWUS),
32200 /* 93680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32201 /* 93682 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32202 /* 93684 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32203 /* 93686 */ GIR_RootConstrainSelectedInstOperands,
32204 /* 93687 */ // GIR_Coverage, 414,
32205 /* 93687 */ GIR_EraseRootFromParent_Done,
32206 /* 93688 */ // Label 1476: @93688
32207 /* 93688 */ GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(93725), // Rule ID 415 //
32208 /* 93693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32209 /* 93696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkuhus),
32210 /* 93701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
32211 /* 93704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32212 /* 93707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32213 /* 93710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32214 /* 93714 */ // (intrinsic_w_chain:{ *:[v16i8] } 10501:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPKUHUS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB)
32215 /* 93714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKUHUS),
32216 /* 93717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32217 /* 93719 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32218 /* 93721 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32219 /* 93723 */ GIR_RootConstrainSelectedInstOperands,
32220 /* 93724 */ // GIR_Coverage, 415,
32221 /* 93724 */ GIR_EraseRootFromParent_Done,
32222 /* 93725 */ // Label 1477: @93725
32223 /* 93725 */ GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(93762), // Rule ID 416 //
32224 /* 93730 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32225 /* 93733 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkuwus),
32226 /* 93738 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32227 /* 93741 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32228 /* 93744 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32229 /* 93747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32230 /* 93751 */ // (intrinsic_w_chain:{ *:[v8i16] } 10502:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKUWUS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
32231 /* 93751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKUWUS),
32232 /* 93754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32233 /* 93756 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32234 /* 93758 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32235 /* 93760 */ GIR_RootConstrainSelectedInstOperands,
32236 /* 93761 */ // GIR_Coverage, 416,
32237 /* 93761 */ GIR_EraseRootFromParent_Done,
32238 /* 93762 */ // Label 1478: @93762
32239 /* 93762 */ GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(93799), // Rule ID 500 //
32240 /* 93767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
32241 /* 93770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpksdss),
32242 /* 93775 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32243 /* 93778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
32244 /* 93781 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
32245 /* 93784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32246 /* 93788 */ // (intrinsic_w_chain:{ *:[v4i32] } 10494:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPKSDSS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
32247 /* 93788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSDSS),
32248 /* 93791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32249 /* 93793 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32250 /* 93795 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32251 /* 93797 */ GIR_RootConstrainSelectedInstOperands,
32252 /* 93798 */ // GIR_Coverage, 500,
32253 /* 93798 */ GIR_EraseRootFromParent_Done,
32254 /* 93799 */ // Label 1479: @93799
32255 /* 93799 */ GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(93836), // Rule ID 501 //
32256 /* 93804 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
32257 /* 93807 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpksdus),
32258 /* 93812 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32259 /* 93815 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
32260 /* 93818 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
32261 /* 93821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32262 /* 93825 */ // (intrinsic_w_chain:{ *:[v4i32] } 10495:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPKSDUS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
32263 /* 93825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSDUS),
32264 /* 93828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32265 /* 93830 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32266 /* 93832 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32267 /* 93834 */ GIR_RootConstrainSelectedInstOperands,
32268 /* 93835 */ // GIR_Coverage, 501,
32269 /* 93835 */ GIR_EraseRootFromParent_Done,
32270 /* 93836 */ // Label 1480: @93836
32271 /* 93836 */ GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(93873), // Rule ID 502 //
32272 /* 93841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
32273 /* 93844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkudus),
32274 /* 93849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32275 /* 93852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
32276 /* 93855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
32277 /* 93858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32278 /* 93862 */ // (intrinsic_w_chain:{ *:[v4i32] } 10500:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPKUDUS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
32279 /* 93862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKUDUS),
32280 /* 93865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
32281 /* 93867 */ GIR_RootToRootCopy, /*OpIdx*/2, // VA
32282 /* 93869 */ GIR_RootToRootCopy, /*OpIdx*/3, // VB
32283 /* 93871 */ GIR_RootConstrainSelectedInstOperands,
32284 /* 93872 */ // GIR_Coverage, 502,
32285 /* 93872 */ GIR_EraseRootFromParent_Done,
32286 /* 93873 */ // Label 1481: @93873
32287 /* 93873 */ GIM_Reject,
32288 /* 93874 */ // Label 1459: @93874
32289 /* 93874 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(94090),
32290 /* 93879 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
32291 /* 93882 */ GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(93921), // Rule ID 766 //
32292 /* 93887 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addex),
32293 /* 93892 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
32294 /* 93895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
32295 /* 93898 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
32296 /* 93901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
32297 /* 93905 */ // MIs[0] CY
32298 /* 93905 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
32299 /* 93908 */ // (intrinsic_w_chain:{ *:[i64] } 10261:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB, (timm:{ *:[i32] }):$CY) => (ADDEX8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB, (timm:{ *:[i32] }):$CY)
32300 /* 93908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDEX8),
32301 /* 93911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
32302 /* 93913 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
32303 /* 93915 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
32304 /* 93917 */ GIR_RootToRootCopy, /*OpIdx*/4, // CY
32305 /* 93919 */ GIR_RootConstrainSelectedInstOperands,
32306 /* 93920 */ // GIR_Coverage, 766,
32307 /* 93920 */ GIR_EraseRootFromParent_Done,
32308 /* 93921 */ // Label 1483: @93921
32309 /* 93921 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(93963), // Rule ID 294 //
32310 /* 93926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32311 /* 93929 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmhaddshs),
32312 /* 93934 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32313 /* 93937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32314 /* 93940 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32315 /* 93943 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
32316 /* 93946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32317 /* 93950 */ // (intrinsic_w_chain:{ *:[v8i16] } 10449:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) => (VMHADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC)
32318 /* 93950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMHADDSHS),
32319 /* 93953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
32320 /* 93955 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
32321 /* 93957 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
32322 /* 93959 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
32323 /* 93961 */ GIR_RootConstrainSelectedInstOperands,
32324 /* 93962 */ // GIR_Coverage, 294,
32325 /* 93962 */ GIR_EraseRootFromParent_Done,
32326 /* 93963 */ // Label 1484: @93963
32327 /* 93963 */ GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(94005), // Rule ID 295 //
32328 /* 93968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32329 /* 93971 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmhraddshs),
32330 /* 93976 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32331 /* 93979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32332 /* 93982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32333 /* 93985 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
32334 /* 93988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32335 /* 93992 */ // (intrinsic_w_chain:{ *:[v8i16] } 10450:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) => (VMHRADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC)
32336 /* 93992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMHRADDSHS),
32337 /* 93995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
32338 /* 93997 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
32339 /* 93999 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
32340 /* 94001 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
32341 /* 94003 */ GIR_RootConstrainSelectedInstOperands,
32342 /* 94004 */ // GIR_Coverage, 295,
32343 /* 94004 */ GIR_EraseRootFromParent_Done,
32344 /* 94005 */ // Label 1485: @94005
32345 /* 94005 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(94047), // Rule ID 353 //
32346 /* 94010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32347 /* 94013 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumshs),
32348 /* 94018 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32349 /* 94021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32350 /* 94024 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32351 /* 94027 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
32352 /* 94030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32353 /* 94034 */ // (intrinsic_w_chain:{ *:[v4i32] } 10464:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMSHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC)
32354 /* 94034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMSHS),
32355 /* 94037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
32356 /* 94039 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
32357 /* 94041 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
32358 /* 94043 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
32359 /* 94045 */ GIR_RootConstrainSelectedInstOperands,
32360 /* 94046 */ // GIR_Coverage, 353,
32361 /* 94046 */ GIR_EraseRootFromParent_Done,
32362 /* 94047 */ // Label 1486: @94047
32363 /* 94047 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(94089), // Rule ID 354 //
32364 /* 94052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
32365 /* 94055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumuhs),
32366 /* 94060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32367 /* 94063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32368 /* 94066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32369 /* 94069 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
32370 /* 94072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
32371 /* 94076 */ // (intrinsic_w_chain:{ *:[v4i32] } 10468:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMUHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC)
32372 /* 94076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUHS),
32373 /* 94079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
32374 /* 94081 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
32375 /* 94083 */ GIR_RootToRootCopy, /*OpIdx*/3, // RB
32376 /* 94085 */ GIR_RootToRootCopy, /*OpIdx*/4, // RC
32377 /* 94087 */ GIR_RootConstrainSelectedInstOperands,
32378 /* 94088 */ // GIR_Coverage, 354,
32379 /* 94088 */ GIR_EraseRootFromParent_Done,
32380 /* 94089 */ // Label 1487: @94089
32381 /* 94089 */ GIM_Reject,
32382 /* 94090 */ // Label 1482: @94090
32383 /* 94090 */ GIM_Reject,
32384 /* 94091 */ // Label 21: @94091
32385 /* 94091 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1490*/ GIMT_Encode4(114846),
32386 /* 94102 */ /*GILLT_s32*//*Label 1488*/ GIMT_Encode4(94110),
32387 /* 94106 */ /*GILLT_s64*//*Label 1489*/ GIMT_Encode4(104331),
32388 /* 94110 */ // Label 1488: @94110
32389 /* 94110 */ GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(104330),
32390 /* 94115 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
32391 /* 94118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
32392 /* 94122 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(94234), // Rule ID 5303 //
32393 /* 94127 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32394 /* 94131 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32395 /* 94135 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32396 /* 94139 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32397 /* 94143 */ // MIs[1] Operand 1
32398 /* 94143 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
32399 /* 94148 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32400 /* 94152 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
32401 /* 94156 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
32402 /* 94160 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
32403 /* 94164 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
32404 /* 94168 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
32405 /* 94172 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
32406 /* 94176 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
32407 /* 94180 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
32408 /* 94184 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32409 /* 94188 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
32410 /* 94190 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa), i32:{ *:[i32] }:$s1), 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] })
32411 /* 94190 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32412 /* 94193 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
32413 /* 94197 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32414 /* 94202 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/2, // sa
32415 /* 94206 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
32416 /* 94209 */ GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for PPC::CARRY*/0,
32417 /* 94212 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32418 /* 94214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
32419 /* 94217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32420 /* 94219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // s1
32421 /* 94223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32422 /* 94226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32423 /* 94229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32424 /* 94232 */ GIR_RootConstrainSelectedInstOperands,
32425 /* 94233 */ // GIR_Coverage, 5303,
32426 /* 94233 */ GIR_EraseRootFromParent_Done,
32427 /* 94234 */ // Label 1492: @94234
32428 /* 94234 */ GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(94373), // Rule ID 5306 //
32429 /* 94239 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32430 /* 94243 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32431 /* 94247 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32432 /* 94251 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32433 /* 94255 */ // MIs[1] Operand 1
32434 /* 94255 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
32435 /* 94260 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32436 /* 94264 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
32437 /* 94268 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
32438 /* 94272 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
32439 /* 94276 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
32440 /* 94280 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
32441 /* 94284 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
32442 /* 94288 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
32443 /* 94292 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
32444 /* 94296 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32445 /* 94300 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
32446 /* 94302 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa), i64:{ *:[i64] }:$s1), 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] }), sub_32:{ *:[i32] })
32447 /* 94302 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
32448 /* 94305 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
32449 /* 94309 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32450 /* 94314 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
32451 /* 94318 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/64,
32452 /* 94321 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
32453 /* 94324 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32454 /* 94326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
32455 /* 94329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
32456 /* 94333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32457 /* 94338 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
32458 /* 94342 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32459 /* 94345 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
32460 /* 94348 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32461 /* 94350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32462 /* 94353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32463 /* 94355 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
32464 /* 94362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
32465 /* 94367 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
32466 /* 94372 */ // GIR_Coverage, 5306,
32467 /* 94372 */ GIR_EraseRootFromParent_Done,
32468 /* 94373 */ // Label 1493: @94373
32469 /* 94373 */ GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(94506), // Rule ID 5311 //
32470 /* 94378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32471 /* 94382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32472 /* 94386 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32473 /* 94390 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32474 /* 94394 */ // MIs[1] Operand 1
32475 /* 94394 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
32476 /* 94399 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32477 /* 94403 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
32478 /* 94407 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
32479 /* 94411 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
32480 /* 94415 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
32481 /* 94419 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
32482 /* 94423 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
32483 /* 94427 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
32484 /* 94431 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
32485 /* 94435 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32486 /* 94439 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
32487 /* 94441 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa), i32:{ *:[i32] }:$s1), 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (RLWNM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] })
32488 /* 94441 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
32489 /* 94444 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
32490 /* 94448 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32491 /* 94453 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
32492 /* 94457 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/32,
32493 /* 94460 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
32494 /* 94463 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32495 /* 94465 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32496 /* 94468 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
32497 /* 94472 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32498 /* 94477 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
32499 /* 94481 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
32500 /* 94485 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32501 /* 94487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
32502 /* 94490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32503 /* 94492 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32504 /* 94495 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
32505 /* 94498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32506 /* 94501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32507 /* 94504 */ GIR_RootConstrainSelectedInstOperands,
32508 /* 94505 */ // GIR_Coverage, 5311,
32509 /* 94505 */ GIR_EraseRootFromParent_Done,
32510 /* 94506 */ // Label 1494: @94506
32511 /* 94506 */ GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(94666), // Rule ID 5314 //
32512 /* 94511 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32513 /* 94515 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32514 /* 94519 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32515 /* 94523 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32516 /* 94527 */ // MIs[1] Operand 1
32517 /* 94527 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
32518 /* 94532 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32519 /* 94536 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
32520 /* 94540 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
32521 /* 94544 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
32522 /* 94548 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
32523 /* 94552 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
32524 /* 94556 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
32525 /* 94560 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
32526 /* 94564 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
32527 /* 94568 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32528 /* 94572 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
32529 /* 94574 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa), i64:{ *:[i64] }:$s1), 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDCL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] }), sub_32:{ *:[i32] })
32530 /* 94574 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
32531 /* 94577 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
32532 /* 94581 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32533 /* 94586 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, // sa
32534 /* 94590 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/64,
32535 /* 94593 */ GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for PPC::CARRY*/0,
32536 /* 94596 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
32537 /* 94598 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
32538 /* 94601 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
32539 /* 94605 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32540 /* 94610 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // s1
32541 /* 94614 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // s1
32542 /* 94618 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32543 /* 94620 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
32544 /* 94623 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
32545 /* 94627 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32546 /* 94632 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32547 /* 94635 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
32548 /* 94638 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
32549 /* 94641 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32550 /* 94643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32551 /* 94646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32552 /* 94648 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
32553 /* 94655 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
32554 /* 94660 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
32555 /* 94665 */ // GIR_Coverage, 5314,
32556 /* 94665 */ GIR_EraseRootFromParent_Done,
32557 /* 94666 */ // Label 1495: @94666
32558 /* 94666 */ GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(94778), // Rule ID 3781 //
32559 /* 94671 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32560 /* 94675 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32561 /* 94679 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32562 /* 94683 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32563 /* 94687 */ // MIs[1] Operand 1
32564 /* 94687 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
32565 /* 94692 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32566 /* 94696 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
32567 /* 94700 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
32568 /* 94704 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
32569 /* 94708 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
32570 /* 94712 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
32571 /* 94716 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
32572 /* 94720 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
32573 /* 94724 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
32574 /* 94728 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32575 /* 94732 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
32576 /* 94734 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i32] } i32:{ *:[i32] }:$s1, (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] })
32577 /* 94734 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32578 /* 94737 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
32579 /* 94741 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32580 /* 94746 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/2, // sa
32581 /* 94750 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
32582 /* 94753 */ GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for PPC::CARRY*/0,
32583 /* 94756 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32584 /* 94758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
32585 /* 94761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32586 /* 94763 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // s1
32587 /* 94767 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32588 /* 94770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32589 /* 94773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32590 /* 94776 */ GIR_RootConstrainSelectedInstOperands,
32591 /* 94777 */ // GIR_Coverage, 3781,
32592 /* 94777 */ GIR_EraseRootFromParent_Done,
32593 /* 94778 */ // Label 1496: @94778
32594 /* 94778 */ GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(94917), // Rule ID 3784 //
32595 /* 94783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32596 /* 94787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32597 /* 94791 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32598 /* 94795 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32599 /* 94799 */ // MIs[1] Operand 1
32600 /* 94799 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
32601 /* 94804 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32602 /* 94808 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
32603 /* 94812 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
32604 /* 94816 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
32605 /* 94820 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
32606 /* 94824 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
32607 /* 94828 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
32608 /* 94832 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
32609 /* 94836 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
32610 /* 94840 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32611 /* 94844 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
32612 /* 94846 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i64] } i64:{ *:[i64] }:$s1, (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] }), sub_32:{ *:[i32] })
32613 /* 94846 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
32614 /* 94849 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
32615 /* 94853 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32616 /* 94858 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
32617 /* 94862 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/64,
32618 /* 94865 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
32619 /* 94868 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32620 /* 94870 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
32621 /* 94873 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
32622 /* 94877 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32623 /* 94882 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
32624 /* 94886 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32625 /* 94889 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
32626 /* 94892 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32627 /* 94894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32628 /* 94897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32629 /* 94899 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
32630 /* 94906 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
32631 /* 94911 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
32632 /* 94916 */ // GIR_Coverage, 3784,
32633 /* 94916 */ GIR_EraseRootFromParent_Done,
32634 /* 94917 */ // Label 1497: @94917
32635 /* 94917 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(95050), // Rule ID 3789 //
32636 /* 94922 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32637 /* 94926 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32638 /* 94930 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32639 /* 94934 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32640 /* 94938 */ // MIs[1] Operand 1
32641 /* 94938 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
32642 /* 94943 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32643 /* 94947 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
32644 /* 94951 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
32645 /* 94955 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
32646 /* 94959 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
32647 /* 94963 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
32648 /* 94967 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
32649 /* 94971 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
32650 /* 94975 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
32651 /* 94979 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32652 /* 94983 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
32653 /* 94985 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i32] } i32:{ *:[i32] }:$s1, (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (RLWNM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] })
32654 /* 94985 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
32655 /* 94988 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
32656 /* 94992 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32657 /* 94997 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
32658 /* 95001 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/32,
32659 /* 95004 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
32660 /* 95007 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32661 /* 95009 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32662 /* 95012 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
32663 /* 95016 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32664 /* 95021 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
32665 /* 95025 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
32666 /* 95029 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32667 /* 95031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
32668 /* 95034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32669 /* 95036 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32670 /* 95039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
32671 /* 95042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32672 /* 95045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32673 /* 95048 */ GIR_RootConstrainSelectedInstOperands,
32674 /* 95049 */ // GIR_Coverage, 3789,
32675 /* 95049 */ GIR_EraseRootFromParent_Done,
32676 /* 95050 */ // Label 1498: @95050
32677 /* 95050 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(95210), // Rule ID 3792 //
32678 /* 95055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32679 /* 95059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32680 /* 95063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32681 /* 95067 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32682 /* 95071 */ // MIs[1] Operand 1
32683 /* 95071 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
32684 /* 95076 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32685 /* 95080 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
32686 /* 95084 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
32687 /* 95088 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
32688 /* 95092 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
32689 /* 95096 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
32690 /* 95100 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
32691 /* 95104 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
32692 /* 95108 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
32693 /* 95112 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32694 /* 95116 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
32695 /* 95118 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i64] } i64:{ *:[i64] }:$s1, (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDCL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] }), sub_32:{ *:[i32] })
32696 /* 95118 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
32697 /* 95121 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
32698 /* 95125 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32699 /* 95130 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, // sa
32700 /* 95134 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/64,
32701 /* 95137 */ GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for PPC::CARRY*/0,
32702 /* 95140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
32703 /* 95142 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
32704 /* 95145 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
32705 /* 95149 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32706 /* 95154 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // s1
32707 /* 95158 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // s1
32708 /* 95162 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32709 /* 95164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
32710 /* 95167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
32711 /* 95171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32712 /* 95176 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32713 /* 95179 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
32714 /* 95182 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
32715 /* 95185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32716 /* 95187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32717 /* 95190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32718 /* 95192 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
32719 /* 95199 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
32720 /* 95204 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
32721 /* 95209 */ // GIR_Coverage, 3792,
32722 /* 95209 */ GIR_EraseRootFromParent_Done,
32723 /* 95210 */ // Label 1499: @95210
32724 /* 95210 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(95279), // Rule ID 3701 //
32725 /* 95215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32726 /* 95219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32727 /* 95223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32728 /* 95227 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32729 /* 95231 */ // MIs[1] Operand 1
32730 /* 95231 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
32731 /* 95236 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32732 /* 95240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32733 /* 95242 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (RLWINM:{ *:[i32] } (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1), 27:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
32734 /* 95242 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32735 /* 95245 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
32736 /* 95249 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32737 /* 95254 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
32738 /* 95258 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32739 /* 95260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
32740 /* 95263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32741 /* 95265 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32742 /* 95268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/27,
32743 /* 95271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32744 /* 95274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32745 /* 95277 */ GIR_RootConstrainSelectedInstOperands,
32746 /* 95278 */ // GIR_Coverage, 3701,
32747 /* 95278 */ GIR_EraseRootFromParent_Done,
32748 /* 95279 */ // Label 1500: @95279
32749 /* 95279 */ GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(95375), // Rule ID 3704 //
32750 /* 95284 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32751 /* 95288 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32752 /* 95292 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32753 /* 95296 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32754 /* 95300 */ // MIs[1] Operand 1
32755 /* 95300 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
32756 /* 95305 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32757 /* 95309 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32758 /* 95311 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1), 58:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
32759 /* 95311 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
32760 /* 95314 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
32761 /* 95318 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32762 /* 95323 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
32763 /* 95327 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32764 /* 95329 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
32765 /* 95332 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
32766 /* 95336 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32767 /* 95341 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32768 /* 95344 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/58,
32769 /* 95347 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
32770 /* 95350 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32771 /* 95352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32772 /* 95355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32773 /* 95357 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
32774 /* 95364 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
32775 /* 95369 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
32776 /* 95374 */ // GIR_Coverage, 3704,
32777 /* 95374 */ GIR_EraseRootFromParent_Done,
32778 /* 95375 */ // Label 1501: @95375
32779 /* 95375 */ GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(95482), // Rule ID 3709 //
32780 /* 95380 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32781 /* 95384 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32782 /* 95388 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32783 /* 95392 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32784 /* 95396 */ // MIs[1] Operand 1
32785 /* 95396 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
32786 /* 95401 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32787 /* 95405 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32788 /* 95407 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1), (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1)), 27:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
32789 /* 95407 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
32790 /* 95410 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
32791 /* 95414 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32792 /* 95419 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
32793 /* 95423 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
32794 /* 95425 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
32795 /* 95428 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
32796 /* 95432 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32797 /* 95437 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
32798 /* 95441 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32799 /* 95443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32800 /* 95446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
32801 /* 95450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32802 /* 95455 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32803 /* 95458 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
32804 /* 95461 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32805 /* 95463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
32806 /* 95466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32807 /* 95468 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32808 /* 95471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/27,
32809 /* 95474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32810 /* 95477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32811 /* 95480 */ GIR_RootConstrainSelectedInstOperands,
32812 /* 95481 */ // GIR_Coverage, 3709,
32813 /* 95481 */ GIR_EraseRootFromParent_Done,
32814 /* 95482 */ // Label 1502: @95482
32815 /* 95482 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(95616), // Rule ID 3712 //
32816 /* 95487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32817 /* 95491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32818 /* 95495 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32819 /* 95499 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32820 /* 95503 */ // MIs[1] Operand 1
32821 /* 95503 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
32822 /* 95508 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32823 /* 95512 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32824 /* 95514 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1), (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1)), 58:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
32825 /* 95514 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
32826 /* 95517 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
32827 /* 95521 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32828 /* 95526 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
32829 /* 95530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
32830 /* 95532 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
32831 /* 95535 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
32832 /* 95539 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32833 /* 95544 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
32834 /* 95548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
32835 /* 95550 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
32836 /* 95553 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
32837 /* 95557 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32838 /* 95562 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
32839 /* 95565 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
32840 /* 95568 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32841 /* 95570 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
32842 /* 95573 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
32843 /* 95577 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32844 /* 95582 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32845 /* 95585 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/58,
32846 /* 95588 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
32847 /* 95591 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32848 /* 95593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32849 /* 95596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32850 /* 95598 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
32851 /* 95605 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
32852 /* 95610 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
32853 /* 95615 */ // GIR_Coverage, 3712,
32854 /* 95615 */ GIR_EraseRootFromParent_Done,
32855 /* 95616 */ // Label 1503: @95616
32856 /* 95616 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(95668), // Rule ID 3717 //
32857 /* 95621 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32858 /* 95625 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32859 /* 95629 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32860 /* 95633 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32861 /* 95637 */ // MIs[1] Operand 1
32862 /* 95637 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
32863 /* 95642 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32864 /* 95646 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32865 /* 95648 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETLT:{ *:[Other] })) => (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
32866 /* 95648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
32867 /* 95651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32868 /* 95653 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // s1
32869 /* 95657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
32870 /* 95660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32871 /* 95663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32872 /* 95666 */ GIR_RootConstrainSelectedInstOperands,
32873 /* 95667 */ // GIR_Coverage, 3717,
32874 /* 95667 */ GIR_EraseRootFromParent_Done,
32875 /* 95668 */ // Label 1504: @95668
32876 /* 95668 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(95747), // Rule ID 3720 //
32877 /* 95673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32878 /* 95677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32879 /* 95681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32880 /* 95685 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32881 /* 95689 */ // MIs[1] Operand 1
32882 /* 95689 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
32883 /* 95694 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32884 /* 95698 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32885 /* 95700 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETLT:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
32886 /* 95700 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
32887 /* 95703 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
32888 /* 95707 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32889 /* 95712 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
32890 /* 95716 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
32891 /* 95719 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
32892 /* 95722 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32893 /* 95724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32894 /* 95727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32895 /* 95729 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
32896 /* 95736 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
32897 /* 95741 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
32898 /* 95746 */ // GIR_Coverage, 3720,
32899 /* 95746 */ GIR_EraseRootFromParent_Done,
32900 /* 95747 */ // Label 1505: @95747
32901 /* 95747 */ GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(95820), // Rule ID 3725 //
32902 /* 95752 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32903 /* 95756 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32904 /* 95760 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32905 /* 95764 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32906 /* 95768 */ // MIs[1] Operand 1
32907 /* 95768 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
32908 /* 95773 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32909 /* 95777 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32910 /* 95779 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETGE:{ *:[Other] })) => (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
32911 /* 95779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32912 /* 95782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
32913 /* 95786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32914 /* 95791 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
32915 /* 95795 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
32916 /* 95799 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32917 /* 95801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
32918 /* 95804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32919 /* 95806 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32920 /* 95809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
32921 /* 95812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32922 /* 95815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32923 /* 95818 */ GIR_RootConstrainSelectedInstOperands,
32924 /* 95819 */ // GIR_Coverage, 3725,
32925 /* 95819 */ GIR_EraseRootFromParent_Done,
32926 /* 95820 */ // Label 1506: @95820
32927 /* 95820 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(95920), // Rule ID 3728 //
32928 /* 95825 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32929 /* 95829 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32930 /* 95833 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32931 /* 95837 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32932 /* 95841 */ // MIs[1] Operand 1
32933 /* 95841 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
32934 /* 95846 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32935 /* 95850 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32936 /* 95852 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETGE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
32937 /* 95852 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
32938 /* 95855 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
32939 /* 95859 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32940 /* 95864 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
32941 /* 95868 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
32942 /* 95872 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32943 /* 95874 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
32944 /* 95877 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
32945 /* 95881 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32946 /* 95886 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32947 /* 95889 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
32948 /* 95892 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
32949 /* 95895 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32950 /* 95897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32951 /* 95900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32952 /* 95902 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
32953 /* 95909 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
32954 /* 95914 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
32955 /* 95919 */ // GIR_Coverage, 3728,
32956 /* 95919 */ GIR_EraseRootFromParent_Done,
32957 /* 95920 */ // Label 1507: @95920
32958 /* 95920 */ GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(96010), // Rule ID 3733 //
32959 /* 95925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32960 /* 95929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32961 /* 95933 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
32962 /* 95937 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
32963 /* 95941 */ // MIs[1] Operand 1
32964 /* 95941 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
32965 /* 95946 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32966 /* 95950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32967 /* 95952 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETGT:{ *:[Other] })) => (RLWINM:{ *:[i32] } (ANDC:{ *:[i32] } (NEG:{ *:[i32] } ?:{ *:[i32] }:$s1), ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
32968 /* 95952 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
32969 /* 95955 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NEG),
32970 /* 95959 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32971 /* 95964 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
32972 /* 95968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32973 /* 95970 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32974 /* 95973 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::ANDC),
32975 /* 95977 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32976 /* 95982 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32977 /* 95985 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
32978 /* 95989 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
32979 /* 95991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
32980 /* 95994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
32981 /* 95996 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32982 /* 95999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
32983 /* 96002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32984 /* 96005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
32985 /* 96008 */ GIR_RootConstrainSelectedInstOperands,
32986 /* 96009 */ // GIR_Coverage, 3733,
32987 /* 96009 */ GIR_EraseRootFromParent_Done,
32988 /* 96010 */ // Label 1508: @96010
32989 /* 96010 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(96127), // Rule ID 3736 //
32990 /* 96015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32991 /* 96019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
32992 /* 96023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32993 /* 96027 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
32994 /* 96031 */ // MIs[1] Operand 1
32995 /* 96031 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
32996 /* 96036 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
32997 /* 96040 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32998 /* 96042 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETGT:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (ANDC8:{ *:[i64] } (NEG8:{ *:[i64] } ?:{ *:[i64] }:$s1), ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
32999 /* 96042 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
33000 /* 96045 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NEG8),
33001 /* 96049 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33002 /* 96054 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
33003 /* 96058 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33004 /* 96060 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
33005 /* 96063 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ANDC8),
33006 /* 96067 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33007 /* 96072 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
33008 /* 96075 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33009 /* 96079 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33010 /* 96081 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33011 /* 96084 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
33012 /* 96088 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33013 /* 96093 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
33014 /* 96096 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
33015 /* 96099 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
33016 /* 96102 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33017 /* 96104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33018 /* 96107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33019 /* 96109 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
33020 /* 96116 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
33021 /* 96121 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
33022 /* 96126 */ // GIR_Coverage, 3736,
33023 /* 96126 */ GIR_EraseRootFromParent_Done,
33024 /* 96127 */ // Label 1509: @96127
33025 /* 96127 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(96217), // Rule ID 3741 //
33026 /* 96132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33027 /* 96136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33028 /* 96140 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33029 /* 96144 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33030 /* 96148 */ // MIs[1] Operand 1
33031 /* 96148 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
33032 /* 96153 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
33033 /* 96157 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33034 /* 96159 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETLE:{ *:[Other] })) => (RLWINM:{ *:[i32] } (ORC:{ *:[i32] } ?:{ *:[i32] }:$s1, (NEG:{ *:[i32] } ?:{ *:[i32] }:$s1)), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
33035 /* 96159 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33036 /* 96162 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NEG),
33037 /* 96166 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33038 /* 96171 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33039 /* 96175 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33040 /* 96177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
33041 /* 96180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::ORC),
33042 /* 96184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33043 /* 96189 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
33044 /* 96193 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
33045 /* 96196 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33046 /* 96198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
33047 /* 96201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
33048 /* 96203 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33049 /* 96206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
33050 /* 96209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33051 /* 96212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33052 /* 96215 */ GIR_RootConstrainSelectedInstOperands,
33053 /* 96216 */ // GIR_Coverage, 3741,
33054 /* 96216 */ GIR_EraseRootFromParent_Done,
33055 /* 96217 */ // Label 1510: @96217
33056 /* 96217 */ GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(96334), // Rule ID 3744 //
33057 /* 96222 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33058 /* 96226 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33059 /* 96230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33060 /* 96234 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33061 /* 96238 */ // MIs[1] Operand 1
33062 /* 96238 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
33063 /* 96243 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
33064 /* 96247 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33065 /* 96249 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETLE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (ORC8:{ *:[i64] } ?:{ *:[i64] }:$s1, (NEG8:{ *:[i64] } ?:{ *:[i64] }:$s1)), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
33066 /* 96249 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
33067 /* 96252 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NEG8),
33068 /* 96256 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33069 /* 96261 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
33070 /* 96265 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33071 /* 96267 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
33072 /* 96270 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ORC8),
33073 /* 96274 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33074 /* 96279 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33075 /* 96283 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
33076 /* 96286 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33077 /* 96288 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33078 /* 96291 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
33079 /* 96295 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33080 /* 96300 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
33081 /* 96303 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
33082 /* 96306 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
33083 /* 96309 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33084 /* 96311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33085 /* 96314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33086 /* 96316 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
33087 /* 96323 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
33088 /* 96328 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
33089 /* 96333 */ // GIR_Coverage, 3744,
33090 /* 96333 */ GIR_EraseRootFromParent_Done,
33091 /* 96334 */ // Label 1511: @96334
33092 /* 96334 */ GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(96427), // Rule ID 3749 //
33093 /* 96339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33094 /* 96343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33095 /* 96347 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33096 /* 96351 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33097 /* 96355 */ // MIs[1] Operand 1
33098 /* 96355 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
33099 /* 96360 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
33100 /* 96364 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33101 /* 96366 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETLT:{ *:[Other] })) => (RLWINM:{ *:[i32] } (AND:{ *:[i32] } ?:{ *:[i32] }:$s1, (ADDI:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] })), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
33102 /* 96366 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33103 /* 96369 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ADDI),
33104 /* 96373 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33105 /* 96378 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33106 /* 96382 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
33107 /* 96385 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33108 /* 96387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
33109 /* 96390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::AND),
33110 /* 96394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33111 /* 96399 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
33112 /* 96403 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
33113 /* 96406 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33114 /* 96408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
33115 /* 96411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
33116 /* 96413 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33117 /* 96416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
33118 /* 96419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33119 /* 96422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33120 /* 96425 */ GIR_RootConstrainSelectedInstOperands,
33121 /* 96426 */ // GIR_Coverage, 3749,
33122 /* 96426 */ GIR_EraseRootFromParent_Done,
33123 /* 96427 */ // Label 1512: @96427
33124 /* 96427 */ GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(96547), // Rule ID 3752 //
33125 /* 96432 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33126 /* 96436 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33127 /* 96440 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33128 /* 96444 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33129 /* 96448 */ // MIs[1] Operand 1
33130 /* 96448 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
33131 /* 96453 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
33132 /* 96457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33133 /* 96459 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETLT:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (AND8:{ *:[i64] } ?:{ *:[i64] }:$s1, (ADDI8:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i64] })), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
33134 /* 96459 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
33135 /* 96462 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
33136 /* 96466 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33137 /* 96471 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
33138 /* 96475 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
33139 /* 96478 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33140 /* 96480 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
33141 /* 96483 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::AND8),
33142 /* 96487 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33143 /* 96492 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33144 /* 96496 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
33145 /* 96499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33146 /* 96501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33147 /* 96504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
33148 /* 96508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33149 /* 96513 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
33150 /* 96516 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
33151 /* 96519 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
33152 /* 96522 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33153 /* 96524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33154 /* 96527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33155 /* 96529 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
33156 /* 96536 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
33157 /* 96541 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
33158 /* 96546 */ // GIR_Coverage, 3752,
33159 /* 96546 */ GIR_EraseRootFromParent_Done,
33160 /* 96547 */ // Label 1513: @96547
33161 /* 96547 */ GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(96640), // Rule ID 3757 //
33162 /* 96552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33163 /* 96556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33164 /* 96560 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33165 /* 96564 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33166 /* 96568 */ // MIs[1] Operand 1
33167 /* 96568 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
33168 /* 96573 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
33169 /* 96577 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33170 /* 96579 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETGE:{ *:[Other] })) => (RLWINM:{ *:[i32] } (NAND:{ *:[i32] } ?:{ *:[i32] }:$s1, (ADDI:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] })), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
33171 /* 96579 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33172 /* 96582 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ADDI),
33173 /* 96586 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33174 /* 96591 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33175 /* 96595 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
33176 /* 96598 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33177 /* 96600 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
33178 /* 96603 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NAND),
33179 /* 96607 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33180 /* 96612 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
33181 /* 96616 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
33182 /* 96619 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33183 /* 96621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
33184 /* 96624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
33185 /* 96626 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33186 /* 96629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
33187 /* 96632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33188 /* 96635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33189 /* 96638 */ GIR_RootConstrainSelectedInstOperands,
33190 /* 96639 */ // GIR_Coverage, 3757,
33191 /* 96639 */ GIR_EraseRootFromParent_Done,
33192 /* 96640 */ // Label 1514: @96640
33193 /* 96640 */ GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(96760), // Rule ID 3760 //
33194 /* 96645 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33195 /* 96649 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33196 /* 96653 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33197 /* 96657 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33198 /* 96661 */ // MIs[1] Operand 1
33199 /* 96661 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
33200 /* 96666 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
33201 /* 96670 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33202 /* 96672 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETGE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (NAND8:{ *:[i64] } ?:{ *:[i64] }:$s1, (ADDI8:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i64] })), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
33203 /* 96672 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
33204 /* 96675 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
33205 /* 96679 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33206 /* 96684 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
33207 /* 96688 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
33208 /* 96691 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33209 /* 96693 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
33210 /* 96696 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NAND8),
33211 /* 96700 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33212 /* 96705 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33213 /* 96709 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
33214 /* 96712 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33215 /* 96714 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33216 /* 96717 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
33217 /* 96721 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33218 /* 96726 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
33219 /* 96729 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
33220 /* 96732 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
33221 /* 96735 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33222 /* 96737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33223 /* 96740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33224 /* 96742 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
33225 /* 96749 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
33226 /* 96754 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
33227 /* 96759 */ // GIR_Coverage, 3760,
33228 /* 96759 */ GIR_EraseRootFromParent_Done,
33229 /* 96760 */ // Label 1515: @96760
33230 /* 96760 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(96833), // Rule ID 3765 //
33231 /* 96765 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33232 /* 96769 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33233 /* 96773 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33234 /* 96777 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33235 /* 96781 */ // MIs[1] Operand 1
33236 /* 96781 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
33237 /* 96786 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
33238 /* 96790 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33239 /* 96792 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETGT:{ *:[Other] })) => (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
33240 /* 96792 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
33241 /* 96795 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
33242 /* 96799 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33243 /* 96804 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
33244 /* 96808 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
33245 /* 96812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33246 /* 96814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
33247 /* 96817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
33248 /* 96819 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33249 /* 96822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
33250 /* 96825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33251 /* 96828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33252 /* 96831 */ GIR_RootConstrainSelectedInstOperands,
33253 /* 96832 */ // GIR_Coverage, 3765,
33254 /* 96832 */ GIR_EraseRootFromParent_Done,
33255 /* 96833 */ // Label 1516: @96833
33256 /* 96833 */ GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(96933), // Rule ID 3768 //
33257 /* 96838 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33258 /* 96842 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33259 /* 96846 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33260 /* 96850 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33261 /* 96854 */ // MIs[1] Operand 1
33262 /* 96854 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
33263 /* 96859 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
33264 /* 96863 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33265 /* 96865 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETGT:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
33266 /* 96865 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
33267 /* 96868 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
33268 /* 96872 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33269 /* 96877 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33270 /* 96881 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33271 /* 96885 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33272 /* 96887 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33273 /* 96890 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
33274 /* 96894 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33275 /* 96899 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
33276 /* 96902 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
33277 /* 96905 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
33278 /* 96908 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33279 /* 96910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33280 /* 96913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33281 /* 96915 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
33282 /* 96922 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
33283 /* 96927 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
33284 /* 96932 */ // GIR_Coverage, 3768,
33285 /* 96932 */ GIR_EraseRootFromParent_Done,
33286 /* 96933 */ // Label 1517: @96933
33287 /* 96933 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(96985), // Rule ID 3773 //
33288 /* 96938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33289 /* 96942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33290 /* 96946 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33291 /* 96950 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33292 /* 96954 */ // MIs[1] Operand 1
33293 /* 96954 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
33294 /* 96959 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
33295 /* 96963 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33296 /* 96965 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETLE:{ *:[Other] })) => (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
33297 /* 96965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
33298 /* 96968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
33299 /* 96970 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // s1
33300 /* 96974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
33301 /* 96977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33302 /* 96980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
33303 /* 96983 */ GIR_RootConstrainSelectedInstOperands,
33304 /* 96984 */ // GIR_Coverage, 3773,
33305 /* 96984 */ GIR_EraseRootFromParent_Done,
33306 /* 96985 */ // Label 1518: @96985
33307 /* 96985 */ GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(97064), // Rule ID 3776 //
33308 /* 96990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33309 /* 96994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33310 /* 96998 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33311 /* 97002 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33312 /* 97006 */ // MIs[1] Operand 1
33313 /* 97006 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
33314 /* 97011 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
33315 /* 97015 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33316 /* 97017 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETLE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
33317 /* 97017 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33318 /* 97020 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
33319 /* 97024 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33320 /* 97029 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
33321 /* 97033 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
33322 /* 97036 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
33323 /* 97039 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
33324 /* 97041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33325 /* 97044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33326 /* 97046 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
33327 /* 97053 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
33328 /* 97058 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
33329 /* 97063 */ // GIR_Coverage, 3776,
33330 /* 97063 */ GIR_EraseRootFromParent_Done,
33331 /* 97064 */ // Label 1519: @97064
33332 /* 97064 */ GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(97167), // Rule ID 3040 //
33333 /* 97069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
33334 /* 97072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33335 /* 97076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33336 /* 97080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33337 /* 97084 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33338 /* 97088 */ // MIs[1] Operand 1
33339 /* 97088 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
33340 /* 97093 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33341 /* 97097 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33342 /* 97101 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
33343 /* 97105 */ // MIs[2] Operand 1
33344 /* 97105 */ // No operand predicates
33345 /* 97105 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33346 /* 97107 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }))
33347 /* 97107 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33348 /* 97110 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
33349 /* 97114 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33350 /* 97119 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33351 /* 97123 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33352 /* 97126 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33353 /* 97128 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33354 /* 97131 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33355 /* 97135 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33356 /* 97140 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
33357 /* 97147 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33358 /* 97152 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33359 /* 97157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33360 /* 97160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33361 /* 97162 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33362 /* 97165 */ GIR_RootConstrainSelectedInstOperands,
33363 /* 97166 */ // GIR_Coverage, 3040,
33364 /* 97166 */ GIR_EraseRootFromParent_Done,
33365 /* 97167 */ // Label 1520: @97167
33366 /* 97167 */ GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(97270), // Rule ID 3056 //
33367 /* 97172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
33368 /* 97175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33369 /* 97179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33370 /* 97183 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33371 /* 97187 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33372 /* 97191 */ // MIs[1] Operand 1
33373 /* 97191 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
33374 /* 97196 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33375 /* 97200 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33376 /* 97204 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
33377 /* 97208 */ // MIs[2] Operand 1
33378 /* 97208 */ // No operand predicates
33379 /* 97208 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33380 /* 97210 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }))
33381 /* 97210 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33382 /* 97213 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
33383 /* 97217 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33384 /* 97222 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33385 /* 97226 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33386 /* 97229 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33387 /* 97231 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33388 /* 97234 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33389 /* 97238 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33390 /* 97243 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
33391 /* 97250 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33392 /* 97255 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33393 /* 97260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33394 /* 97263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33395 /* 97265 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33396 /* 97268 */ GIR_RootConstrainSelectedInstOperands,
33397 /* 97269 */ // GIR_Coverage, 3056,
33398 /* 97269 */ GIR_EraseRootFromParent_Done,
33399 /* 97270 */ // Label 1521: @97270
33400 /* 97270 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(97373), // Rule ID 3064 //
33401 /* 97275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
33402 /* 97278 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33403 /* 97282 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33404 /* 97286 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33405 /* 97290 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33406 /* 97294 */ // MIs[1] Operand 1
33407 /* 97294 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
33408 /* 97299 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33409 /* 97303 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33410 /* 97307 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
33411 /* 97311 */ // MIs[2] Operand 1
33412 /* 97311 */ // No operand predicates
33413 /* 97311 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33414 /* 97313 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }))
33415 /* 97313 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33416 /* 97316 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
33417 /* 97320 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33418 /* 97325 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33419 /* 97329 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33420 /* 97332 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33421 /* 97334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33422 /* 97337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33423 /* 97341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33424 /* 97346 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
33425 /* 97353 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33426 /* 97358 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33427 /* 97363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33428 /* 97366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33429 /* 97368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33430 /* 97371 */ GIR_RootConstrainSelectedInstOperands,
33431 /* 97372 */ // GIR_Coverage, 3064,
33432 /* 97372 */ GIR_EraseRootFromParent_Done,
33433 /* 97373 */ // Label 1522: @97373
33434 /* 97373 */ GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(97476), // Rule ID 3136 //
33435 /* 97378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
33436 /* 97381 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33437 /* 97385 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33438 /* 97389 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33439 /* 97393 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33440 /* 97397 */ // MIs[1] Operand 1
33441 /* 97397 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
33442 /* 97402 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33443 /* 97406 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33444 /* 97410 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
33445 /* 97414 */ // MIs[2] Operand 1
33446 /* 97414 */ // No operand predicates
33447 /* 97414 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33448 /* 97416 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }))
33449 /* 97416 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33450 /* 97419 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
33451 /* 97423 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33452 /* 97428 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33453 /* 97432 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33454 /* 97435 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33455 /* 97437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33456 /* 97440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33457 /* 97444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33458 /* 97449 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
33459 /* 97456 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33460 /* 97461 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33461 /* 97466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33462 /* 97469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33463 /* 97471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33464 /* 97474 */ GIR_RootConstrainSelectedInstOperands,
33465 /* 97475 */ // GIR_Coverage, 3136,
33466 /* 97475 */ GIR_EraseRootFromParent_Done,
33467 /* 97476 */ // Label 1523: @97476
33468 /* 97476 */ GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(97579), // Rule ID 3152 //
33469 /* 97481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
33470 /* 97484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33471 /* 97488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33472 /* 97492 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33473 /* 97496 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33474 /* 97500 */ // MIs[1] Operand 1
33475 /* 97500 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
33476 /* 97505 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33477 /* 97509 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33478 /* 97513 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
33479 /* 97517 */ // MIs[2] Operand 1
33480 /* 97517 */ // No operand predicates
33481 /* 97517 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33482 /* 97519 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }))
33483 /* 97519 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33484 /* 97522 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
33485 /* 97526 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33486 /* 97531 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33487 /* 97535 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33488 /* 97538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33489 /* 97540 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33490 /* 97543 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33491 /* 97547 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33492 /* 97552 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
33493 /* 97559 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33494 /* 97564 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33495 /* 97569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33496 /* 97572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33497 /* 97574 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33498 /* 97577 */ GIR_RootConstrainSelectedInstOperands,
33499 /* 97578 */ // GIR_Coverage, 3152,
33500 /* 97578 */ GIR_EraseRootFromParent_Done,
33501 /* 97579 */ // Label 1524: @97579
33502 /* 97579 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(97682), // Rule ID 3160 //
33503 /* 97584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
33504 /* 97587 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33505 /* 97591 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33506 /* 97595 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33507 /* 97599 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33508 /* 97603 */ // MIs[1] Operand 1
33509 /* 97603 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
33510 /* 97608 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33511 /* 97612 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33512 /* 97616 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
33513 /* 97620 */ // MIs[2] Operand 1
33514 /* 97620 */ // No operand predicates
33515 /* 97620 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33516 /* 97622 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }))
33517 /* 97622 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33518 /* 97625 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
33519 /* 97629 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33520 /* 97634 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33521 /* 97638 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33522 /* 97641 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33523 /* 97643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33524 /* 97646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33525 /* 97650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33526 /* 97655 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
33527 /* 97662 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33528 /* 97667 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33529 /* 97672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33530 /* 97675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33531 /* 97677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33532 /* 97680 */ GIR_RootConstrainSelectedInstOperands,
33533 /* 97681 */ // GIR_Coverage, 3160,
33534 /* 97681 */ GIR_EraseRootFromParent_Done,
33535 /* 97682 */ // Label 1525: @97682
33536 /* 97682 */ GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(97825), // Rule ID 3823 //
33537 /* 97687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
33538 /* 97690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33539 /* 97694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33540 /* 97698 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33541 /* 97702 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33542 /* 97706 */ // MIs[1] Operand 1
33543 /* 97706 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
33544 /* 97711 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33545 /* 97715 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33546 /* 97719 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
33547 /* 97723 */ // MIs[2] Operand 1
33548 /* 97723 */ // No operand predicates
33549 /* 97723 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33550 /* 97725 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
33551 /* 97725 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33552 /* 97728 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
33553 /* 97732 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33554 /* 97737 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33555 /* 97741 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33556 /* 97744 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33557 /* 97746 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
33558 /* 97749 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
33559 /* 97753 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33560 /* 97758 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
33561 /* 97761 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
33562 /* 97763 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
33563 /* 97766 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
33564 /* 97770 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33565 /* 97775 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
33566 /* 97778 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33567 /* 97780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33568 /* 97783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33569 /* 97787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33570 /* 97792 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
33571 /* 97799 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33572 /* 97804 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33573 /* 97809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
33574 /* 97812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33575 /* 97814 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33576 /* 97817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
33577 /* 97820 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
33578 /* 97823 */ GIR_RootConstrainSelectedInstOperands,
33579 /* 97824 */ // GIR_Coverage, 3823,
33580 /* 97824 */ GIR_EraseRootFromParent_Done,
33581 /* 97825 */ // Label 1526: @97825
33582 /* 97825 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(97968), // Rule ID 3839 //
33583 /* 97830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
33584 /* 97833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33585 /* 97837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33586 /* 97841 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33587 /* 97845 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33588 /* 97849 */ // MIs[1] Operand 1
33589 /* 97849 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
33590 /* 97854 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33591 /* 97858 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33592 /* 97862 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
33593 /* 97866 */ // MIs[2] Operand 1
33594 /* 97866 */ // No operand predicates
33595 /* 97866 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33596 /* 97868 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
33597 /* 97868 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33598 /* 97871 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
33599 /* 97875 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33600 /* 97880 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33601 /* 97884 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33602 /* 97887 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33603 /* 97889 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
33604 /* 97892 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
33605 /* 97896 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33606 /* 97901 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
33607 /* 97904 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
33608 /* 97906 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
33609 /* 97909 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
33610 /* 97913 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33611 /* 97918 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
33612 /* 97921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33613 /* 97923 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33614 /* 97926 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33615 /* 97930 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33616 /* 97935 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
33617 /* 97942 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33618 /* 97947 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33619 /* 97952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
33620 /* 97955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33621 /* 97957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33622 /* 97960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
33623 /* 97963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
33624 /* 97966 */ GIR_RootConstrainSelectedInstOperands,
33625 /* 97967 */ // GIR_Coverage, 3839,
33626 /* 97967 */ GIR_EraseRootFromParent_Done,
33627 /* 97968 */ // Label 1527: @97968
33628 /* 97968 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(98111), // Rule ID 3847 //
33629 /* 97973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
33630 /* 97976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33631 /* 97980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33632 /* 97984 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33633 /* 97988 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33634 /* 97992 */ // MIs[1] Operand 1
33635 /* 97992 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
33636 /* 97997 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33637 /* 98001 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33638 /* 98005 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
33639 /* 98009 */ // MIs[2] Operand 1
33640 /* 98009 */ // No operand predicates
33641 /* 98009 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33642 /* 98011 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
33643 /* 98011 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33644 /* 98014 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
33645 /* 98018 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33646 /* 98023 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33647 /* 98027 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33648 /* 98030 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33649 /* 98032 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
33650 /* 98035 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
33651 /* 98039 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33652 /* 98044 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
33653 /* 98047 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
33654 /* 98049 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
33655 /* 98052 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
33656 /* 98056 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33657 /* 98061 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
33658 /* 98064 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33659 /* 98066 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33660 /* 98069 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33661 /* 98073 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33662 /* 98078 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
33663 /* 98085 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33664 /* 98090 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33665 /* 98095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
33666 /* 98098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33667 /* 98100 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33668 /* 98103 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
33669 /* 98106 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
33670 /* 98109 */ GIR_RootConstrainSelectedInstOperands,
33671 /* 98110 */ // GIR_Coverage, 3847,
33672 /* 98110 */ GIR_EraseRootFromParent_Done,
33673 /* 98111 */ // Label 1528: @98111
33674 /* 98111 */ GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(98254), // Rule ID 3919 //
33675 /* 98116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
33676 /* 98119 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33677 /* 98123 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33678 /* 98127 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33679 /* 98131 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33680 /* 98135 */ // MIs[1] Operand 1
33681 /* 98135 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
33682 /* 98140 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33683 /* 98144 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33684 /* 98148 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
33685 /* 98152 */ // MIs[2] Operand 1
33686 /* 98152 */ // No operand predicates
33687 /* 98152 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33688 /* 98154 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
33689 /* 98154 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33690 /* 98157 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
33691 /* 98161 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33692 /* 98166 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33693 /* 98170 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33694 /* 98173 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33695 /* 98175 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
33696 /* 98178 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
33697 /* 98182 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33698 /* 98187 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
33699 /* 98190 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
33700 /* 98192 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
33701 /* 98195 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
33702 /* 98199 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33703 /* 98204 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
33704 /* 98207 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33705 /* 98209 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33706 /* 98212 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33707 /* 98216 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33708 /* 98221 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
33709 /* 98228 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33710 /* 98233 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33711 /* 98238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
33712 /* 98241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33713 /* 98243 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33714 /* 98246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
33715 /* 98249 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
33716 /* 98252 */ GIR_RootConstrainSelectedInstOperands,
33717 /* 98253 */ // GIR_Coverage, 3919,
33718 /* 98253 */ GIR_EraseRootFromParent_Done,
33719 /* 98254 */ // Label 1529: @98254
33720 /* 98254 */ GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(98397), // Rule ID 3935 //
33721 /* 98259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
33722 /* 98262 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33723 /* 98266 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33724 /* 98270 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33725 /* 98274 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33726 /* 98278 */ // MIs[1] Operand 1
33727 /* 98278 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
33728 /* 98283 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33729 /* 98287 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33730 /* 98291 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
33731 /* 98295 */ // MIs[2] Operand 1
33732 /* 98295 */ // No operand predicates
33733 /* 98295 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33734 /* 98297 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
33735 /* 98297 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33736 /* 98300 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
33737 /* 98304 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33738 /* 98309 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33739 /* 98313 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33740 /* 98316 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33741 /* 98318 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
33742 /* 98321 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
33743 /* 98325 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33744 /* 98330 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
33745 /* 98333 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
33746 /* 98335 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
33747 /* 98338 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
33748 /* 98342 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33749 /* 98347 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
33750 /* 98350 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33751 /* 98352 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33752 /* 98355 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33753 /* 98359 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33754 /* 98364 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
33755 /* 98371 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33756 /* 98376 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33757 /* 98381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
33758 /* 98384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33759 /* 98386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33760 /* 98389 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
33761 /* 98392 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
33762 /* 98395 */ GIR_RootConstrainSelectedInstOperands,
33763 /* 98396 */ // GIR_Coverage, 3935,
33764 /* 98396 */ GIR_EraseRootFromParent_Done,
33765 /* 98397 */ // Label 1530: @98397
33766 /* 98397 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(98540), // Rule ID 3943 //
33767 /* 98402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
33768 /* 98405 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33769 /* 98409 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
33770 /* 98413 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33771 /* 98417 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33772 /* 98421 */ // MIs[1] Operand 1
33773 /* 98421 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
33774 /* 98426 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
33775 /* 98430 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33776 /* 98434 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
33777 /* 98438 */ // MIs[2] Operand 1
33778 /* 98438 */ // No operand predicates
33779 /* 98438 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
33780 /* 98440 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
33781 /* 98440 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33782 /* 98443 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
33783 /* 98447 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33784 /* 98452 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33785 /* 98456 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
33786 /* 98459 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33787 /* 98461 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
33788 /* 98464 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
33789 /* 98468 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33790 /* 98473 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
33791 /* 98476 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
33792 /* 98478 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
33793 /* 98481 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
33794 /* 98485 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33795 /* 98490 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
33796 /* 98493 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
33797 /* 98495 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33798 /* 98498 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33799 /* 98502 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33800 /* 98507 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
33801 /* 98514 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33802 /* 98519 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33803 /* 98524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
33804 /* 98527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33805 /* 98529 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33806 /* 98532 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
33807 /* 98535 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
33808 /* 98538 */ GIR_RootConstrainSelectedInstOperands,
33809 /* 98539 */ // GIR_Coverage, 3943,
33810 /* 98539 */ GIR_EraseRootFromParent_Done,
33811 /* 98540 */ // Label 1531: @98540
33812 /* 98540 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(98632), // Rule ID 3184 //
33813 /* 98545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
33814 /* 98548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33815 /* 98552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
33816 /* 98556 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33817 /* 98560 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33818 /* 98564 */ // MIs[1] Operand 1
33819 /* 98564 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
33820 /* 98569 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33821 /* 98571 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }))
33822 /* 98571 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33823 /* 98574 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
33824 /* 98578 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33825 /* 98583 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33826 /* 98587 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
33827 /* 98591 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33828 /* 98593 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33829 /* 98596 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33830 /* 98600 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33831 /* 98605 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
33832 /* 98612 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33833 /* 98617 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33834 /* 98622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33835 /* 98625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33836 /* 98627 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33837 /* 98630 */ GIR_RootConstrainSelectedInstOperands,
33838 /* 98631 */ // GIR_Coverage, 3184,
33839 /* 98631 */ GIR_EraseRootFromParent_Done,
33840 /* 98632 */ // Label 1532: @98632
33841 /* 98632 */ GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(98724), // Rule ID 3200 //
33842 /* 98637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
33843 /* 98640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33844 /* 98644 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
33845 /* 98648 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33846 /* 98652 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33847 /* 98656 */ // MIs[1] Operand 1
33848 /* 98656 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
33849 /* 98661 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33850 /* 98663 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
33851 /* 98663 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33852 /* 98666 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
33853 /* 98670 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33854 /* 98675 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33855 /* 98679 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
33856 /* 98683 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33857 /* 98685 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33858 /* 98688 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33859 /* 98692 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33860 /* 98697 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
33861 /* 98704 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33862 /* 98709 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33863 /* 98714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33864 /* 98717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33865 /* 98719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33866 /* 98722 */ GIR_RootConstrainSelectedInstOperands,
33867 /* 98723 */ // GIR_Coverage, 3200,
33868 /* 98723 */ GIR_EraseRootFromParent_Done,
33869 /* 98724 */ // Label 1533: @98724
33870 /* 98724 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(98816), // Rule ID 3216 //
33871 /* 98729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
33872 /* 98732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33873 /* 98736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
33874 /* 98740 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33875 /* 98744 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33876 /* 98748 */ // MIs[1] Operand 1
33877 /* 98748 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
33878 /* 98753 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33879 /* 98755 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }))
33880 /* 98755 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33881 /* 98758 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
33882 /* 98762 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33883 /* 98767 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33884 /* 98771 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
33885 /* 98775 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33886 /* 98777 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33887 /* 98780 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33888 /* 98784 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33889 /* 98789 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
33890 /* 98796 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33891 /* 98801 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33892 /* 98806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33893 /* 98809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33894 /* 98811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33895 /* 98814 */ GIR_RootConstrainSelectedInstOperands,
33896 /* 98815 */ // GIR_Coverage, 3216,
33897 /* 98815 */ GIR_EraseRootFromParent_Done,
33898 /* 98816 */ // Label 1534: @98816
33899 /* 98816 */ GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(98908), // Rule ID 3232 //
33900 /* 98821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
33901 /* 98824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33902 /* 98828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
33903 /* 98832 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
33904 /* 98836 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
33905 /* 98840 */ // MIs[1] Operand 1
33906 /* 98840 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
33907 /* 98845 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33908 /* 98847 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }))
33909 /* 98847 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33910 /* 98850 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
33911 /* 98854 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33912 /* 98859 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33913 /* 98863 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
33914 /* 98867 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33915 /* 98869 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33916 /* 98872 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33917 /* 98876 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33918 /* 98881 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
33919 /* 98888 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33920 /* 98893 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33921 /* 98898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33922 /* 98901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33923 /* 98903 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33924 /* 98906 */ GIR_RootConstrainSelectedInstOperands,
33925 /* 98907 */ // GIR_Coverage, 3232,
33926 /* 98907 */ GIR_EraseRootFromParent_Done,
33927 /* 98908 */ // Label 1535: @98908
33928 /* 98908 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(99000), // Rule ID 3240 //
33929 /* 98913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
33930 /* 98916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33931 /* 98920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
33932 /* 98924 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33933 /* 98928 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33934 /* 98932 */ // MIs[1] Operand 1
33935 /* 98932 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
33936 /* 98937 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33937 /* 98939 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }))
33938 /* 98939 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33939 /* 98942 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
33940 /* 98946 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33941 /* 98951 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33942 /* 98955 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
33943 /* 98959 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33944 /* 98961 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33945 /* 98964 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33946 /* 98968 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33947 /* 98973 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
33948 /* 98980 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33949 /* 98985 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33950 /* 98990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33951 /* 98993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33952 /* 98995 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33953 /* 98998 */ GIR_RootConstrainSelectedInstOperands,
33954 /* 98999 */ // GIR_Coverage, 3240,
33955 /* 98999 */ GIR_EraseRootFromParent_Done,
33956 /* 99000 */ // Label 1536: @99000
33957 /* 99000 */ GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(99092), // Rule ID 3256 //
33958 /* 99005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
33959 /* 99008 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33960 /* 99012 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
33961 /* 99016 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33962 /* 99020 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33963 /* 99024 */ // MIs[1] Operand 1
33964 /* 99024 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
33965 /* 99029 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33966 /* 99031 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
33967 /* 99031 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33968 /* 99034 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
33969 /* 99038 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33970 /* 99043 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
33971 /* 99047 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
33972 /* 99051 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
33973 /* 99053 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
33974 /* 99056 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33975 /* 99060 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33976 /* 99065 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
33977 /* 99072 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
33978 /* 99077 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
33979 /* 99082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
33980 /* 99085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
33981 /* 99087 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33982 /* 99090 */ GIR_RootConstrainSelectedInstOperands,
33983 /* 99091 */ // GIR_Coverage, 3256,
33984 /* 99091 */ GIR_EraseRootFromParent_Done,
33985 /* 99092 */ // Label 1537: @99092
33986 /* 99092 */ GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(99184), // Rule ID 3272 //
33987 /* 99097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
33988 /* 99100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33989 /* 99104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
33990 /* 99108 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33991 /* 99112 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
33992 /* 99116 */ // MIs[1] Operand 1
33993 /* 99116 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
33994 /* 99121 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33995 /* 99123 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }))
33996 /* 99123 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
33997 /* 99126 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
33998 /* 99130 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33999 /* 99135 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34000 /* 99139 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34001 /* 99143 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34002 /* 99145 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34003 /* 99148 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34004 /* 99152 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34005 /* 99157 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
34006 /* 99164 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34007 /* 99169 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34008 /* 99174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34009 /* 99177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34010 /* 99179 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34011 /* 99182 */ GIR_RootConstrainSelectedInstOperands,
34012 /* 99183 */ // GIR_Coverage, 3272,
34013 /* 99183 */ GIR_EraseRootFromParent_Done,
34014 /* 99184 */ // Label 1538: @99184
34015 /* 99184 */ GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(99276), // Rule ID 3288 //
34016 /* 99189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
34017 /* 99192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34018 /* 99196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34019 /* 99200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34020 /* 99204 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34021 /* 99208 */ // MIs[1] Operand 1
34022 /* 99208 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
34023 /* 99213 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34024 /* 99215 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }))
34025 /* 99215 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34026 /* 99218 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
34027 /* 99222 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34028 /* 99227 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34029 /* 99231 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34030 /* 99235 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34031 /* 99237 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34032 /* 99240 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34033 /* 99244 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34034 /* 99249 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
34035 /* 99256 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34036 /* 99261 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34037 /* 99266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34038 /* 99269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34039 /* 99271 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34040 /* 99274 */ GIR_RootConstrainSelectedInstOperands,
34041 /* 99275 */ // GIR_Coverage, 3288,
34042 /* 99275 */ GIR_EraseRootFromParent_Done,
34043 /* 99276 */ // Label 1539: @99276
34044 /* 99276 */ GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(99368), // Rule ID 3296 //
34045 /* 99281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
34046 /* 99284 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34047 /* 99288 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34048 /* 99292 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
34049 /* 99296 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
34050 /* 99300 */ // MIs[1] Operand 1
34051 /* 99300 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
34052 /* 99305 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34053 /* 99307 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }))
34054 /* 99307 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34055 /* 99310 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
34056 /* 99314 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34057 /* 99319 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34058 /* 99323 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34059 /* 99327 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34060 /* 99329 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34061 /* 99332 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34062 /* 99336 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34063 /* 99341 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
34064 /* 99348 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34065 /* 99353 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34066 /* 99358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34067 /* 99361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34068 /* 99363 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34069 /* 99366 */ GIR_RootConstrainSelectedInstOperands,
34070 /* 99367 */ // GIR_Coverage, 3296,
34071 /* 99367 */ GIR_EraseRootFromParent_Done,
34072 /* 99368 */ // Label 1540: @99368
34073 /* 99368 */ GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(99460), // Rule ID 3312 //
34074 /* 99373 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
34075 /* 99376 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34076 /* 99380 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34077 /* 99384 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
34078 /* 99388 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
34079 /* 99392 */ // MIs[1] Operand 1
34080 /* 99392 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
34081 /* 99397 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34082 /* 99399 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }))
34083 /* 99399 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34084 /* 99402 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
34085 /* 99406 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34086 /* 99411 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34087 /* 99415 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34088 /* 99419 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34089 /* 99421 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34090 /* 99424 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34091 /* 99428 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34092 /* 99433 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34093 /* 99440 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34094 /* 99445 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34095 /* 99450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34096 /* 99453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34097 /* 99455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34098 /* 99458 */ GIR_RootConstrainSelectedInstOperands,
34099 /* 99459 */ // GIR_Coverage, 3312,
34100 /* 99459 */ GIR_EraseRootFromParent_Done,
34101 /* 99460 */ // Label 1541: @99460
34102 /* 99460 */ GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(99552), // Rule ID 3328 //
34103 /* 99465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
34104 /* 99468 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34105 /* 99472 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34106 /* 99476 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
34107 /* 99480 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
34108 /* 99484 */ // MIs[1] Operand 1
34109 /* 99484 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
34110 /* 99489 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34111 /* 99491 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }))
34112 /* 99491 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34113 /* 99494 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
34114 /* 99498 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34115 /* 99503 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34116 /* 99507 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34117 /* 99511 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34118 /* 99513 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34119 /* 99516 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34120 /* 99520 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34121 /* 99525 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
34122 /* 99532 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34123 /* 99537 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34124 /* 99542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34125 /* 99545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34126 /* 99547 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34127 /* 99550 */ GIR_RootConstrainSelectedInstOperands,
34128 /* 99551 */ // GIR_Coverage, 3328,
34129 /* 99551 */ GIR_EraseRootFromParent_Done,
34130 /* 99552 */ // Label 1542: @99552
34131 /* 99552 */ GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(99644), // Rule ID 3344 //
34132 /* 99557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
34133 /* 99560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34134 /* 99564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34135 /* 99568 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
34136 /* 99572 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
34137 /* 99576 */ // MIs[1] Operand 1
34138 /* 99576 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
34139 /* 99581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34140 /* 99583 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }))
34141 /* 99583 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34142 /* 99586 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
34143 /* 99590 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34144 /* 99595 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34145 /* 99599 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34146 /* 99603 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34147 /* 99605 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34148 /* 99608 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34149 /* 99612 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34150 /* 99617 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
34151 /* 99624 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34152 /* 99629 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34153 /* 99634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34154 /* 99637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34155 /* 99639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34156 /* 99642 */ GIR_RootConstrainSelectedInstOperands,
34157 /* 99643 */ // GIR_Coverage, 3344,
34158 /* 99643 */ GIR_EraseRootFromParent_Done,
34159 /* 99644 */ // Label 1543: @99644
34160 /* 99644 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(99776), // Rule ID 4028 //
34161 /* 99649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34162 /* 99652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34163 /* 99656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34164 /* 99660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34165 /* 99664 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34166 /* 99668 */ // MIs[1] Operand 1
34167 /* 99668 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
34168 /* 99673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34169 /* 99675 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34170 /* 99675 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34171 /* 99678 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
34172 /* 99682 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34173 /* 99687 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34174 /* 99691 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34175 /* 99695 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34176 /* 99697 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34177 /* 99700 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34178 /* 99704 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34179 /* 99709 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34180 /* 99712 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34181 /* 99714 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34182 /* 99717 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34183 /* 99721 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34184 /* 99726 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34185 /* 99729 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34186 /* 99731 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34187 /* 99734 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34188 /* 99738 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34189 /* 99743 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
34190 /* 99750 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34191 /* 99755 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34192 /* 99760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34193 /* 99763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34194 /* 99765 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34195 /* 99768 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34196 /* 99771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34197 /* 99774 */ GIR_RootConstrainSelectedInstOperands,
34198 /* 99775 */ // GIR_Coverage, 4028,
34199 /* 99775 */ GIR_EraseRootFromParent_Done,
34200 /* 99776 */ // Label 1544: @99776
34201 /* 99776 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(99908), // Rule ID 4060 //
34202 /* 99781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34203 /* 99784 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34204 /* 99788 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34205 /* 99792 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34206 /* 99796 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34207 /* 99800 */ // MIs[1] Operand 1
34208 /* 99800 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
34209 /* 99805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34210 /* 99807 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34211 /* 99807 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34212 /* 99810 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
34213 /* 99814 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34214 /* 99819 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34215 /* 99823 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34216 /* 99827 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34217 /* 99829 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34218 /* 99832 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34219 /* 99836 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34220 /* 99841 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34221 /* 99844 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34222 /* 99846 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34223 /* 99849 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34224 /* 99853 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34225 /* 99858 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34226 /* 99861 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34227 /* 99863 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34228 /* 99866 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34229 /* 99870 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34230 /* 99875 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34231 /* 99882 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34232 /* 99887 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34233 /* 99892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34234 /* 99895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34235 /* 99897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34236 /* 99900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34237 /* 99903 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34238 /* 99906 */ GIR_RootConstrainSelectedInstOperands,
34239 /* 99907 */ // GIR_Coverage, 4060,
34240 /* 99907 */ GIR_EraseRootFromParent_Done,
34241 /* 99908 */ // Label 1545: @99908
34242 /* 99908 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(100040), // Rule ID 4092 //
34243 /* 99913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34244 /* 99916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34245 /* 99920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34246 /* 99924 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34247 /* 99928 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34248 /* 99932 */ // MIs[1] Operand 1
34249 /* 99932 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
34250 /* 99937 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34251 /* 99939 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34252 /* 99939 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34253 /* 99942 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
34254 /* 99946 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34255 /* 99951 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34256 /* 99955 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34257 /* 99959 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34258 /* 99961 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34259 /* 99964 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34260 /* 99968 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34261 /* 99973 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34262 /* 99976 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34263 /* 99978 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34264 /* 99981 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34265 /* 99985 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34266 /* 99990 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34267 /* 99993 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34268 /* 99995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34269 /* 99998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34270 /* 100002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34271 /* 100007 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
34272 /* 100014 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34273 /* 100019 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34274 /* 100024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34275 /* 100027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34276 /* 100029 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34277 /* 100032 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34278 /* 100035 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34279 /* 100038 */ GIR_RootConstrainSelectedInstOperands,
34280 /* 100039 */ // GIR_Coverage, 4092,
34281 /* 100039 */ GIR_EraseRootFromParent_Done,
34282 /* 100040 */ // Label 1546: @100040
34283 /* 100040 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(100172), // Rule ID 4124 //
34284 /* 100045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34285 /* 100048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34286 /* 100052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34287 /* 100056 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34288 /* 100060 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34289 /* 100064 */ // MIs[1] Operand 1
34290 /* 100064 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
34291 /* 100069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34292 /* 100071 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34293 /* 100071 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34294 /* 100074 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
34295 /* 100078 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34296 /* 100083 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34297 /* 100087 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34298 /* 100091 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34299 /* 100093 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34300 /* 100096 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34301 /* 100100 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34302 /* 100105 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34303 /* 100108 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34304 /* 100110 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34305 /* 100113 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34306 /* 100117 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34307 /* 100122 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34308 /* 100125 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34309 /* 100127 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34310 /* 100130 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34311 /* 100134 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34312 /* 100139 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
34313 /* 100146 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34314 /* 100151 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34315 /* 100156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34316 /* 100159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34317 /* 100161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34318 /* 100164 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34319 /* 100167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34320 /* 100170 */ GIR_RootConstrainSelectedInstOperands,
34321 /* 100171 */ // GIR_Coverage, 4124,
34322 /* 100171 */ GIR_EraseRootFromParent_Done,
34323 /* 100172 */ // Label 1547: @100172
34324 /* 100172 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(100304), // Rule ID 4140 //
34325 /* 100177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34326 /* 100180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34327 /* 100184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34328 /* 100188 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34329 /* 100192 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34330 /* 100196 */ // MIs[1] Operand 1
34331 /* 100196 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
34332 /* 100201 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34333 /* 100203 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34334 /* 100203 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34335 /* 100206 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
34336 /* 100210 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34337 /* 100215 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34338 /* 100219 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34339 /* 100223 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34340 /* 100225 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34341 /* 100228 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34342 /* 100232 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34343 /* 100237 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34344 /* 100240 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34345 /* 100242 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34346 /* 100245 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34347 /* 100249 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34348 /* 100254 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34349 /* 100257 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34350 /* 100259 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34351 /* 100262 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34352 /* 100266 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34353 /* 100271 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
34354 /* 100278 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34355 /* 100283 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34356 /* 100288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34357 /* 100291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34358 /* 100293 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34359 /* 100296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34360 /* 100299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34361 /* 100302 */ GIR_RootConstrainSelectedInstOperands,
34362 /* 100303 */ // GIR_Coverage, 4140,
34363 /* 100303 */ GIR_EraseRootFromParent_Done,
34364 /* 100304 */ // Label 1548: @100304
34365 /* 100304 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(100436), // Rule ID 4172 //
34366 /* 100309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34367 /* 100312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34368 /* 100316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34369 /* 100320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34370 /* 100324 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34371 /* 100328 */ // MIs[1] Operand 1
34372 /* 100328 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
34373 /* 100333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34374 /* 100335 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34375 /* 100335 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34376 /* 100338 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
34377 /* 100342 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34378 /* 100347 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34379 /* 100351 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34380 /* 100355 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34381 /* 100357 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34382 /* 100360 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34383 /* 100364 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34384 /* 100369 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34385 /* 100372 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34386 /* 100374 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34387 /* 100377 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34388 /* 100381 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34389 /* 100386 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34390 /* 100389 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34391 /* 100391 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34392 /* 100394 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34393 /* 100398 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34394 /* 100403 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34395 /* 100410 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34396 /* 100415 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34397 /* 100420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34398 /* 100423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34399 /* 100425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34400 /* 100428 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34401 /* 100431 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34402 /* 100434 */ GIR_RootConstrainSelectedInstOperands,
34403 /* 100435 */ // GIR_Coverage, 4172,
34404 /* 100435 */ GIR_EraseRootFromParent_Done,
34405 /* 100436 */ // Label 1549: @100436
34406 /* 100436 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(100568), // Rule ID 4204 //
34407 /* 100441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34408 /* 100444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34409 /* 100448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34410 /* 100452 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34411 /* 100456 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34412 /* 100460 */ // MIs[1] Operand 1
34413 /* 100460 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
34414 /* 100465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34415 /* 100467 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34416 /* 100467 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34417 /* 100470 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
34418 /* 100474 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34419 /* 100479 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34420 /* 100483 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34421 /* 100487 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34422 /* 100489 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34423 /* 100492 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34424 /* 100496 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34425 /* 100501 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34426 /* 100504 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34427 /* 100506 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34428 /* 100509 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34429 /* 100513 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34430 /* 100518 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34431 /* 100521 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34432 /* 100523 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34433 /* 100526 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34434 /* 100530 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34435 /* 100535 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
34436 /* 100542 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34437 /* 100547 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34438 /* 100552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34439 /* 100555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34440 /* 100557 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34441 /* 100560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34442 /* 100563 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34443 /* 100566 */ GIR_RootConstrainSelectedInstOperands,
34444 /* 100567 */ // GIR_Coverage, 4204,
34445 /* 100567 */ GIR_EraseRootFromParent_Done,
34446 /* 100568 */ // Label 1550: @100568
34447 /* 100568 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(100700), // Rule ID 4236 //
34448 /* 100573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34449 /* 100576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34450 /* 100580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34451 /* 100584 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34452 /* 100588 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34453 /* 100592 */ // MIs[1] Operand 1
34454 /* 100592 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
34455 /* 100597 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34456 /* 100599 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34457 /* 100599 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34458 /* 100602 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
34459 /* 100606 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34460 /* 100611 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34461 /* 100615 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34462 /* 100619 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34463 /* 100621 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34464 /* 100624 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34465 /* 100628 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34466 /* 100633 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34467 /* 100636 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34468 /* 100638 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34469 /* 100641 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34470 /* 100645 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34471 /* 100650 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34472 /* 100653 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34473 /* 100655 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34474 /* 100658 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34475 /* 100662 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34476 /* 100667 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
34477 /* 100674 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34478 /* 100679 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34479 /* 100684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34480 /* 100687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34481 /* 100689 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34482 /* 100692 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34483 /* 100695 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34484 /* 100698 */ GIR_RootConstrainSelectedInstOperands,
34485 /* 100699 */ // GIR_Coverage, 4236,
34486 /* 100699 */ GIR_EraseRootFromParent_Done,
34487 /* 100700 */ // Label 1551: @100700
34488 /* 100700 */ GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(100832), // Rule ID 4266 //
34489 /* 100705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34490 /* 100708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34491 /* 100712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34492 /* 100716 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
34493 /* 100720 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
34494 /* 100724 */ // MIs[1] Operand 1
34495 /* 100724 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
34496 /* 100729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34497 /* 100731 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34498 /* 100731 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34499 /* 100734 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
34500 /* 100738 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34501 /* 100743 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34502 /* 100747 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34503 /* 100751 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34504 /* 100753 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34505 /* 100756 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34506 /* 100760 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34507 /* 100765 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34508 /* 100768 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34509 /* 100770 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34510 /* 100773 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34511 /* 100777 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34512 /* 100782 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34513 /* 100785 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34514 /* 100787 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34515 /* 100790 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34516 /* 100794 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34517 /* 100799 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
34518 /* 100806 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34519 /* 100811 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34520 /* 100816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34521 /* 100819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34522 /* 100821 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34523 /* 100824 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34524 /* 100827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34525 /* 100830 */ GIR_RootConstrainSelectedInstOperands,
34526 /* 100831 */ // GIR_Coverage, 4266,
34527 /* 100831 */ GIR_EraseRootFromParent_Done,
34528 /* 100832 */ // Label 1552: @100832
34529 /* 100832 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(100964), // Rule ID 4298 //
34530 /* 100837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34531 /* 100840 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34532 /* 100844 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34533 /* 100848 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
34534 /* 100852 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
34535 /* 100856 */ // MIs[1] Operand 1
34536 /* 100856 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
34537 /* 100861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34538 /* 100863 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34539 /* 100863 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34540 /* 100866 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
34541 /* 100870 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34542 /* 100875 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34543 /* 100879 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34544 /* 100883 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34545 /* 100885 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34546 /* 100888 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34547 /* 100892 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34548 /* 100897 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34549 /* 100900 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34550 /* 100902 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34551 /* 100905 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34552 /* 100909 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34553 /* 100914 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34554 /* 100917 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34555 /* 100919 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34556 /* 100922 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34557 /* 100926 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34558 /* 100931 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34559 /* 100938 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34560 /* 100943 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34561 /* 100948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34562 /* 100951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34563 /* 100953 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34564 /* 100956 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34565 /* 100959 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34566 /* 100962 */ GIR_RootConstrainSelectedInstOperands,
34567 /* 100963 */ // GIR_Coverage, 4298,
34568 /* 100963 */ GIR_EraseRootFromParent_Done,
34569 /* 100964 */ // Label 1553: @100964
34570 /* 100964 */ GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(101096), // Rule ID 4330 //
34571 /* 100969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34572 /* 100972 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34573 /* 100976 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34574 /* 100980 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
34575 /* 100984 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
34576 /* 100988 */ // MIs[1] Operand 1
34577 /* 100988 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
34578 /* 100993 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34579 /* 100995 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34580 /* 100995 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34581 /* 100998 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
34582 /* 101002 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34583 /* 101007 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34584 /* 101011 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34585 /* 101015 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34586 /* 101017 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34587 /* 101020 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34588 /* 101024 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34589 /* 101029 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34590 /* 101032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34591 /* 101034 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34592 /* 101037 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34593 /* 101041 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34594 /* 101046 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34595 /* 101049 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34596 /* 101051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34597 /* 101054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34598 /* 101058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34599 /* 101063 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
34600 /* 101070 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34601 /* 101075 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34602 /* 101080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34603 /* 101083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34604 /* 101085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34605 /* 101088 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34606 /* 101091 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34607 /* 101094 */ GIR_RootConstrainSelectedInstOperands,
34608 /* 101095 */ // GIR_Coverage, 4330,
34609 /* 101095 */ GIR_EraseRootFromParent_Done,
34610 /* 101096 */ // Label 1554: @101096
34611 /* 101096 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(101228), // Rule ID 4362 //
34612 /* 101101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
34613 /* 101104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34614 /* 101108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34615 /* 101112 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
34616 /* 101116 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
34617 /* 101120 */ // MIs[1] Operand 1
34618 /* 101120 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
34619 /* 101125 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34620 /* 101127 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34621 /* 101127 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34622 /* 101130 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
34623 /* 101134 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34624 /* 101139 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34625 /* 101143 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34626 /* 101147 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34627 /* 101149 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34628 /* 101152 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34629 /* 101156 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34630 /* 101161 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34631 /* 101164 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34632 /* 101166 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34633 /* 101169 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34634 /* 101173 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34635 /* 101178 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34636 /* 101181 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34637 /* 101183 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34638 /* 101186 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34639 /* 101190 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34640 /* 101195 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
34641 /* 101202 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34642 /* 101207 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34643 /* 101212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34644 /* 101215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34645 /* 101217 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34646 /* 101220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34647 /* 101223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34648 /* 101226 */ GIR_RootConstrainSelectedInstOperands,
34649 /* 101227 */ // GIR_Coverage, 4362,
34650 /* 101227 */ GIR_EraseRootFromParent_Done,
34651 /* 101228 */ // Label 1555: @101228
34652 /* 101228 */ GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(101360), // Rule ID 4593 //
34653 /* 101233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
34654 /* 101236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34655 /* 101240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34656 /* 101244 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34657 /* 101248 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34658 /* 101252 */ // MIs[1] Operand 1
34659 /* 101252 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
34660 /* 101257 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34661 /* 101259 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34662 /* 101259 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34663 /* 101262 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
34664 /* 101266 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34665 /* 101271 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34666 /* 101275 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34667 /* 101279 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34668 /* 101281 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34669 /* 101284 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34670 /* 101288 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34671 /* 101293 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34672 /* 101296 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34673 /* 101298 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34674 /* 101301 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34675 /* 101305 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34676 /* 101310 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34677 /* 101313 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34678 /* 101315 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34679 /* 101318 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34680 /* 101322 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34681 /* 101327 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34682 /* 101334 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34683 /* 101339 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34684 /* 101344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34685 /* 101347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34686 /* 101349 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34687 /* 101352 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34688 /* 101355 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34689 /* 101358 */ GIR_RootConstrainSelectedInstOperands,
34690 /* 101359 */ // GIR_Coverage, 4593,
34691 /* 101359 */ GIR_EraseRootFromParent_Done,
34692 /* 101360 */ // Label 1556: @101360
34693 /* 101360 */ GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(101492), // Rule ID 4625 //
34694 /* 101365 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
34695 /* 101368 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34696 /* 101372 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34697 /* 101376 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34698 /* 101380 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34699 /* 101384 */ // MIs[1] Operand 1
34700 /* 101384 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
34701 /* 101389 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34702 /* 101391 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34703 /* 101391 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34704 /* 101394 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
34705 /* 101398 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34706 /* 101403 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34707 /* 101407 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34708 /* 101411 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34709 /* 101413 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34710 /* 101416 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34711 /* 101420 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34712 /* 101425 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34713 /* 101428 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34714 /* 101430 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34715 /* 101433 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34716 /* 101437 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34717 /* 101442 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34718 /* 101445 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34719 /* 101447 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34720 /* 101450 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34721 /* 101454 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34722 /* 101459 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34723 /* 101466 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34724 /* 101471 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34725 /* 101476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34726 /* 101479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34727 /* 101481 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34728 /* 101484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34729 /* 101487 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34730 /* 101490 */ GIR_RootConstrainSelectedInstOperands,
34731 /* 101491 */ // GIR_Coverage, 4625,
34732 /* 101491 */ GIR_EraseRootFromParent_Done,
34733 /* 101492 */ // Label 1557: @101492
34734 /* 101492 */ GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(101624), // Rule ID 4657 //
34735 /* 101497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
34736 /* 101500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34737 /* 101504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34738 /* 101508 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34739 /* 101512 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34740 /* 101516 */ // MIs[1] Operand 1
34741 /* 101516 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
34742 /* 101521 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34743 /* 101523 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34744 /* 101523 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34745 /* 101526 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
34746 /* 101530 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34747 /* 101535 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34748 /* 101539 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34749 /* 101543 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34750 /* 101545 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34751 /* 101548 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34752 /* 101552 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34753 /* 101557 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34754 /* 101560 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34755 /* 101562 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34756 /* 101565 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34757 /* 101569 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34758 /* 101574 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34759 /* 101577 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34760 /* 101579 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34761 /* 101582 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34762 /* 101586 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34763 /* 101591 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34764 /* 101598 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34765 /* 101603 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34766 /* 101608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34767 /* 101611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34768 /* 101613 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34769 /* 101616 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34770 /* 101619 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34771 /* 101622 */ GIR_RootConstrainSelectedInstOperands,
34772 /* 101623 */ // GIR_Coverage, 4657,
34773 /* 101623 */ GIR_EraseRootFromParent_Done,
34774 /* 101624 */ // Label 1558: @101624
34775 /* 101624 */ GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(101756), // Rule ID 4701 //
34776 /* 101629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
34777 /* 101632 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34778 /* 101636 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34779 /* 101640 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34780 /* 101644 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34781 /* 101648 */ // MIs[1] Operand 1
34782 /* 101648 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
34783 /* 101653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34784 /* 101655 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34785 /* 101655 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34786 /* 101658 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
34787 /* 101662 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34788 /* 101667 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34789 /* 101671 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34790 /* 101675 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34791 /* 101677 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34792 /* 101680 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34793 /* 101684 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34794 /* 101689 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34795 /* 101692 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34796 /* 101694 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34797 /* 101697 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34798 /* 101701 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34799 /* 101706 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34800 /* 101709 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34801 /* 101711 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34802 /* 101714 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34803 /* 101718 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34804 /* 101723 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34805 /* 101730 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34806 /* 101735 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34807 /* 101740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34808 /* 101743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34809 /* 101745 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34810 /* 101748 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34811 /* 101751 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34812 /* 101754 */ GIR_RootConstrainSelectedInstOperands,
34813 /* 101755 */ // GIR_Coverage, 4701,
34814 /* 101755 */ GIR_EraseRootFromParent_Done,
34815 /* 101756 */ // Label 1559: @101756
34816 /* 101756 */ GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(101888), // Rule ID 4733 //
34817 /* 101761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
34818 /* 101764 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34819 /* 101768 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34820 /* 101772 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34821 /* 101776 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34822 /* 101780 */ // MIs[1] Operand 1
34823 /* 101780 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
34824 /* 101785 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34825 /* 101787 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34826 /* 101787 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34827 /* 101790 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
34828 /* 101794 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34829 /* 101799 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34830 /* 101803 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34831 /* 101807 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34832 /* 101809 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34833 /* 101812 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34834 /* 101816 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34835 /* 101821 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34836 /* 101824 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34837 /* 101826 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34838 /* 101829 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34839 /* 101833 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34840 /* 101838 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34841 /* 101841 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34842 /* 101843 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34843 /* 101846 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34844 /* 101850 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34845 /* 101855 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34846 /* 101862 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34847 /* 101867 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34848 /* 101872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34849 /* 101875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34850 /* 101877 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34851 /* 101880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34852 /* 101883 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34853 /* 101886 */ GIR_RootConstrainSelectedInstOperands,
34854 /* 101887 */ // GIR_Coverage, 4733,
34855 /* 101887 */ GIR_EraseRootFromParent_Done,
34856 /* 101888 */ // Label 1560: @101888
34857 /* 101888 */ GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(102020), // Rule ID 4765 //
34858 /* 101893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
34859 /* 101896 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34860 /* 101900 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
34861 /* 101904 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34862 /* 101908 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
34863 /* 101912 */ // MIs[1] Operand 1
34864 /* 101912 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
34865 /* 101917 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34866 /* 101919 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
34867 /* 101919 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34868 /* 101922 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
34869 /* 101926 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34870 /* 101931 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34871 /* 101935 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34872 /* 101939 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34873 /* 101941 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
34874 /* 101944 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
34875 /* 101948 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34876 /* 101953 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
34877 /* 101956 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
34878 /* 101958 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
34879 /* 101961 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
34880 /* 101965 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34881 /* 101970 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
34882 /* 101973 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
34883 /* 101975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34884 /* 101978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34885 /* 101982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34886 /* 101987 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34887 /* 101994 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34888 /* 101999 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34889 /* 102004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
34890 /* 102007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
34891 /* 102009 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34892 /* 102012 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
34893 /* 102015 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
34894 /* 102018 */ GIR_RootConstrainSelectedInstOperands,
34895 /* 102019 */ // GIR_Coverage, 4765,
34896 /* 102019 */ GIR_EraseRootFromParent_Done,
34897 /* 102020 */ // Label 1561: @102020
34898 /* 102020 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(102112), // Rule ID 2986 //
34899 /* 102025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
34900 /* 102028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34901 /* 102032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
34902 /* 102036 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34903 /* 102040 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34904 /* 102044 */ // MIs[1] Operand 1
34905 /* 102044 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
34906 /* 102049 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34907 /* 102051 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
34908 /* 102051 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34909 /* 102054 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
34910 /* 102058 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34911 /* 102063 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34912 /* 102067 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34913 /* 102071 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34914 /* 102073 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34915 /* 102076 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34916 /* 102080 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34917 /* 102085 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
34918 /* 102092 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34919 /* 102097 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34920 /* 102102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34921 /* 102105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34922 /* 102107 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34923 /* 102110 */ GIR_RootConstrainSelectedInstOperands,
34924 /* 102111 */ // GIR_Coverage, 2986,
34925 /* 102111 */ GIR_EraseRootFromParent_Done,
34926 /* 102112 */ // Label 1562: @102112
34927 /* 102112 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(102204), // Rule ID 3000 //
34928 /* 102117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
34929 /* 102120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34930 /* 102124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
34931 /* 102128 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34932 /* 102132 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34933 /* 102136 */ // MIs[1] Operand 1
34934 /* 102136 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
34935 /* 102141 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34936 /* 102143 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
34937 /* 102143 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34938 /* 102146 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
34939 /* 102150 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34940 /* 102155 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34941 /* 102159 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34942 /* 102163 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34943 /* 102165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34944 /* 102168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34945 /* 102172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34946 /* 102177 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
34947 /* 102184 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34948 /* 102189 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34949 /* 102194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34950 /* 102197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34951 /* 102199 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34952 /* 102202 */ GIR_RootConstrainSelectedInstOperands,
34953 /* 102203 */ // GIR_Coverage, 3000,
34954 /* 102203 */ GIR_EraseRootFromParent_Done,
34955 /* 102204 */ // Label 1563: @102204
34956 /* 102204 */ GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(102296), // Rule ID 3008 //
34957 /* 102209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
34958 /* 102212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34959 /* 102216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
34960 /* 102220 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34961 /* 102224 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34962 /* 102228 */ // MIs[1] Operand 1
34963 /* 102228 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
34964 /* 102233 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34965 /* 102235 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
34966 /* 102235 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34967 /* 102238 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
34968 /* 102242 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34969 /* 102247 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34970 /* 102251 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
34971 /* 102255 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
34972 /* 102257 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
34973 /* 102260 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34974 /* 102264 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34975 /* 102269 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
34976 /* 102276 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
34977 /* 102281 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
34978 /* 102286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
34979 /* 102289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
34980 /* 102291 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34981 /* 102294 */ GIR_RootConstrainSelectedInstOperands,
34982 /* 102295 */ // GIR_Coverage, 3008,
34983 /* 102295 */ GIR_EraseRootFromParent_Done,
34984 /* 102296 */ // Label 1564: @102296
34985 /* 102296 */ GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(102388), // Rule ID 3016 //
34986 /* 102301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
34987 /* 102304 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34988 /* 102308 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
34989 /* 102312 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
34990 /* 102316 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
34991 /* 102320 */ // MIs[1] Operand 1
34992 /* 102320 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
34993 /* 102325 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34994 /* 102327 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
34995 /* 102327 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
34996 /* 102330 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
34997 /* 102334 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34998 /* 102339 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
34999 /* 102343 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35000 /* 102347 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35001 /* 102349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35002 /* 102352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35003 /* 102356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35004 /* 102361 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
35005 /* 102368 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35006 /* 102373 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35007 /* 102378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
35008 /* 102381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
35009 /* 102383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35010 /* 102386 */ GIR_RootConstrainSelectedInstOperands,
35011 /* 102387 */ // GIR_Coverage, 3016,
35012 /* 102387 */ GIR_EraseRootFromParent_Done,
35013 /* 102388 */ // Label 1565: @102388
35014 /* 102388 */ GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(102480), // Rule ID 3024 //
35015 /* 102393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
35016 /* 102396 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35017 /* 102400 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35018 /* 102404 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35019 /* 102408 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35020 /* 102412 */ // MIs[1] Operand 1
35021 /* 102412 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
35022 /* 102417 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35023 /* 102419 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }))
35024 /* 102419 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35025 /* 102422 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
35026 /* 102426 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35027 /* 102431 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35028 /* 102435 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35029 /* 102439 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35030 /* 102441 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35031 /* 102444 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35032 /* 102448 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35033 /* 102453 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
35034 /* 102460 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35035 /* 102465 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35036 /* 102470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
35037 /* 102473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
35038 /* 102475 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35039 /* 102478 */ GIR_RootConstrainSelectedInstOperands,
35040 /* 102479 */ // GIR_Coverage, 3024,
35041 /* 102479 */ GIR_EraseRootFromParent_Done,
35042 /* 102480 */ // Label 1566: @102480
35043 /* 102480 */ GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(102572), // Rule ID 3088 //
35044 /* 102485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
35045 /* 102488 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35046 /* 102492 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35047 /* 102496 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35048 /* 102500 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35049 /* 102504 */ // MIs[1] Operand 1
35050 /* 102504 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
35051 /* 102509 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35052 /* 102511 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
35053 /* 102511 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35054 /* 102514 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
35055 /* 102518 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35056 /* 102523 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35057 /* 102527 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35058 /* 102531 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35059 /* 102533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35060 /* 102536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35061 /* 102540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35062 /* 102545 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
35063 /* 102552 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35064 /* 102557 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35065 /* 102562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
35066 /* 102565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
35067 /* 102567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35068 /* 102570 */ GIR_RootConstrainSelectedInstOperands,
35069 /* 102571 */ // GIR_Coverage, 3088,
35070 /* 102571 */ GIR_EraseRootFromParent_Done,
35071 /* 102572 */ // Label 1567: @102572
35072 /* 102572 */ GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(102664), // Rule ID 3096 //
35073 /* 102577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
35074 /* 102580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35075 /* 102584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35076 /* 102588 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35077 /* 102592 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35078 /* 102596 */ // MIs[1] Operand 1
35079 /* 102596 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
35080 /* 102601 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35081 /* 102603 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
35082 /* 102603 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35083 /* 102606 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
35084 /* 102610 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35085 /* 102615 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35086 /* 102619 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35087 /* 102623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35088 /* 102625 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35089 /* 102628 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35090 /* 102632 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35091 /* 102637 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
35092 /* 102644 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35093 /* 102649 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35094 /* 102654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
35095 /* 102657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
35096 /* 102659 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35097 /* 102662 */ GIR_RootConstrainSelectedInstOperands,
35098 /* 102663 */ // GIR_Coverage, 3096,
35099 /* 102663 */ GIR_EraseRootFromParent_Done,
35100 /* 102664 */ // Label 1568: @102664
35101 /* 102664 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(102756), // Rule ID 3104 //
35102 /* 102669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
35103 /* 102672 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35104 /* 102676 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35105 /* 102680 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35106 /* 102684 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35107 /* 102688 */ // MIs[1] Operand 1
35108 /* 102688 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
35109 /* 102693 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35110 /* 102695 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
35111 /* 102695 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35112 /* 102698 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
35113 /* 102702 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35114 /* 102707 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35115 /* 102711 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35116 /* 102715 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35117 /* 102717 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35118 /* 102720 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35119 /* 102724 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35120 /* 102729 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
35121 /* 102736 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35122 /* 102741 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35123 /* 102746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
35124 /* 102749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
35125 /* 102751 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35126 /* 102754 */ GIR_RootConstrainSelectedInstOperands,
35127 /* 102755 */ // GIR_Coverage, 3104,
35128 /* 102755 */ GIR_EraseRootFromParent_Done,
35129 /* 102756 */ // Label 1569: @102756
35130 /* 102756 */ GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(102848), // Rule ID 3112 //
35131 /* 102761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
35132 /* 102764 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35133 /* 102768 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35134 /* 102772 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35135 /* 102776 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35136 /* 102780 */ // MIs[1] Operand 1
35137 /* 102780 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
35138 /* 102785 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35139 /* 102787 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
35140 /* 102787 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35141 /* 102790 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
35142 /* 102794 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35143 /* 102799 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35144 /* 102803 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35145 /* 102807 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35146 /* 102809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35147 /* 102812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35148 /* 102816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35149 /* 102821 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
35150 /* 102828 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35151 /* 102833 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35152 /* 102838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
35153 /* 102841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
35154 /* 102843 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35155 /* 102846 */ GIR_RootConstrainSelectedInstOperands,
35156 /* 102847 */ // GIR_Coverage, 3112,
35157 /* 102847 */ GIR_EraseRootFromParent_Done,
35158 /* 102848 */ // Label 1570: @102848
35159 /* 102848 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(102940), // Rule ID 3120 //
35160 /* 102853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
35161 /* 102856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35162 /* 102860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35163 /* 102864 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35164 /* 102868 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35165 /* 102872 */ // MIs[1] Operand 1
35166 /* 102872 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
35167 /* 102877 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35168 /* 102879 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }))
35169 /* 102879 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35170 /* 102882 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
35171 /* 102886 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35172 /* 102891 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35173 /* 102895 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35174 /* 102899 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35175 /* 102901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35176 /* 102904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35177 /* 102908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35178 /* 102913 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
35179 /* 102920 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35180 /* 102925 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35181 /* 102930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
35182 /* 102933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
35183 /* 102935 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35184 /* 102938 */ GIR_RootConstrainSelectedInstOperands,
35185 /* 102939 */ // GIR_Coverage, 3120,
35186 /* 102939 */ GIR_EraseRootFromParent_Done,
35187 /* 102940 */ // Label 1571: @102940
35188 /* 102940 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(103072), // Rule ID 3871 //
35189 /* 102945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35190 /* 102948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35191 /* 102952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35192 /* 102956 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35193 /* 102960 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35194 /* 102964 */ // MIs[1] Operand 1
35195 /* 102964 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
35196 /* 102969 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35197 /* 102971 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35198 /* 102971 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35199 /* 102974 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
35200 /* 102978 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35201 /* 102983 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35202 /* 102987 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35203 /* 102991 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35204 /* 102993 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35205 /* 102996 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35206 /* 103000 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35207 /* 103005 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35208 /* 103008 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35209 /* 103010 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35210 /* 103013 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35211 /* 103017 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35212 /* 103022 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35213 /* 103025 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35214 /* 103027 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35215 /* 103030 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35216 /* 103034 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35217 /* 103039 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
35218 /* 103046 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35219 /* 103051 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35220 /* 103056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35221 /* 103059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35222 /* 103061 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35223 /* 103064 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35224 /* 103067 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35225 /* 103070 */ GIR_RootConstrainSelectedInstOperands,
35226 /* 103071 */ // GIR_Coverage, 3871,
35227 /* 103071 */ GIR_EraseRootFromParent_Done,
35228 /* 103072 */ // Label 1572: @103072
35229 /* 103072 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(103204), // Rule ID 3879 //
35230 /* 103077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35231 /* 103080 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35232 /* 103084 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35233 /* 103088 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35234 /* 103092 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35235 /* 103096 */ // MIs[1] Operand 1
35236 /* 103096 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
35237 /* 103101 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35238 /* 103103 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35239 /* 103103 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35240 /* 103106 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
35241 /* 103110 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35242 /* 103115 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35243 /* 103119 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35244 /* 103123 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35245 /* 103125 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35246 /* 103128 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35247 /* 103132 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35248 /* 103137 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35249 /* 103140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35250 /* 103142 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35251 /* 103145 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35252 /* 103149 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35253 /* 103154 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35254 /* 103157 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35255 /* 103159 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35256 /* 103162 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35257 /* 103166 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35258 /* 103171 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
35259 /* 103178 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35260 /* 103183 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35261 /* 103188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35262 /* 103191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35263 /* 103193 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35264 /* 103196 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35265 /* 103199 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35266 /* 103202 */ GIR_RootConstrainSelectedInstOperands,
35267 /* 103203 */ // GIR_Coverage, 3879,
35268 /* 103203 */ GIR_EraseRootFromParent_Done,
35269 /* 103204 */ // Label 1573: @103204
35270 /* 103204 */ GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(103336), // Rule ID 3887 //
35271 /* 103209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35272 /* 103212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35273 /* 103216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35274 /* 103220 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35275 /* 103224 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35276 /* 103228 */ // MIs[1] Operand 1
35277 /* 103228 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
35278 /* 103233 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35279 /* 103235 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35280 /* 103235 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35281 /* 103238 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
35282 /* 103242 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35283 /* 103247 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35284 /* 103251 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35285 /* 103255 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35286 /* 103257 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35287 /* 103260 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35288 /* 103264 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35289 /* 103269 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35290 /* 103272 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35291 /* 103274 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35292 /* 103277 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35293 /* 103281 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35294 /* 103286 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35295 /* 103289 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35296 /* 103291 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35297 /* 103294 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35298 /* 103298 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35299 /* 103303 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
35300 /* 103310 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35301 /* 103315 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35302 /* 103320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35303 /* 103323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35304 /* 103325 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35305 /* 103328 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35306 /* 103331 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35307 /* 103334 */ GIR_RootConstrainSelectedInstOperands,
35308 /* 103335 */ // GIR_Coverage, 3887,
35309 /* 103335 */ GIR_EraseRootFromParent_Done,
35310 /* 103336 */ // Label 1574: @103336
35311 /* 103336 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(103468), // Rule ID 3895 //
35312 /* 103341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35313 /* 103344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35314 /* 103348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35315 /* 103352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35316 /* 103356 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35317 /* 103360 */ // MIs[1] Operand 1
35318 /* 103360 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
35319 /* 103365 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35320 /* 103367 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35321 /* 103367 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35322 /* 103370 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
35323 /* 103374 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35324 /* 103379 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35325 /* 103383 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35326 /* 103387 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35327 /* 103389 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35328 /* 103392 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35329 /* 103396 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35330 /* 103401 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35331 /* 103404 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35332 /* 103406 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35333 /* 103409 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35334 /* 103413 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35335 /* 103418 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35336 /* 103421 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35337 /* 103423 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35338 /* 103426 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35339 /* 103430 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35340 /* 103435 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
35341 /* 103442 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35342 /* 103447 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35343 /* 103452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35344 /* 103455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35345 /* 103457 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35346 /* 103460 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35347 /* 103463 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35348 /* 103466 */ GIR_RootConstrainSelectedInstOperands,
35349 /* 103467 */ // GIR_Coverage, 3895,
35350 /* 103467 */ GIR_EraseRootFromParent_Done,
35351 /* 103468 */ // Label 1575: @103468
35352 /* 103468 */ GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(103600), // Rule ID 3903 //
35353 /* 103473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35354 /* 103476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35355 /* 103480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35356 /* 103484 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35357 /* 103488 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35358 /* 103492 */ // MIs[1] Operand 1
35359 /* 103492 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
35360 /* 103497 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35361 /* 103499 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35362 /* 103499 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35363 /* 103502 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
35364 /* 103506 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35365 /* 103511 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35366 /* 103515 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35367 /* 103519 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35368 /* 103521 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35369 /* 103524 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35370 /* 103528 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35371 /* 103533 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35372 /* 103536 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35373 /* 103538 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35374 /* 103541 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35375 /* 103545 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35376 /* 103550 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35377 /* 103553 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35378 /* 103555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35379 /* 103558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35380 /* 103562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35381 /* 103567 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
35382 /* 103574 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35383 /* 103579 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35384 /* 103584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35385 /* 103587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35386 /* 103589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35387 /* 103592 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35388 /* 103595 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35389 /* 103598 */ GIR_RootConstrainSelectedInstOperands,
35390 /* 103599 */ // GIR_Coverage, 3903,
35391 /* 103599 */ GIR_EraseRootFromParent_Done,
35392 /* 103600 */ // Label 1576: @103600
35393 /* 103600 */ GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(103732), // Rule ID 3967 //
35394 /* 103605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35395 /* 103608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35396 /* 103612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35397 /* 103616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35398 /* 103620 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35399 /* 103624 */ // MIs[1] Operand 1
35400 /* 103624 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
35401 /* 103629 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35402 /* 103631 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35403 /* 103631 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35404 /* 103634 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
35405 /* 103638 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35406 /* 103643 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35407 /* 103647 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35408 /* 103651 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35409 /* 103653 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35410 /* 103656 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35411 /* 103660 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35412 /* 103665 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35413 /* 103668 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35414 /* 103670 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35415 /* 103673 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35416 /* 103677 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35417 /* 103682 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35418 /* 103685 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35419 /* 103687 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35420 /* 103690 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35421 /* 103694 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35422 /* 103699 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
35423 /* 103706 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35424 /* 103711 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35425 /* 103716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35426 /* 103719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35427 /* 103721 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35428 /* 103724 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35429 /* 103727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35430 /* 103730 */ GIR_RootConstrainSelectedInstOperands,
35431 /* 103731 */ // GIR_Coverage, 3967,
35432 /* 103731 */ GIR_EraseRootFromParent_Done,
35433 /* 103732 */ // Label 1577: @103732
35434 /* 103732 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(103864), // Rule ID 3975 //
35435 /* 103737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35436 /* 103740 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35437 /* 103744 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35438 /* 103748 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35439 /* 103752 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35440 /* 103756 */ // MIs[1] Operand 1
35441 /* 103756 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
35442 /* 103761 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35443 /* 103763 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35444 /* 103763 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35445 /* 103766 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
35446 /* 103770 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35447 /* 103775 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35448 /* 103779 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35449 /* 103783 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35450 /* 103785 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35451 /* 103788 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35452 /* 103792 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35453 /* 103797 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35454 /* 103800 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35455 /* 103802 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35456 /* 103805 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35457 /* 103809 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35458 /* 103814 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35459 /* 103817 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35460 /* 103819 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35461 /* 103822 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35462 /* 103826 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35463 /* 103831 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
35464 /* 103838 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35465 /* 103843 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35466 /* 103848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35467 /* 103851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35468 /* 103853 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35469 /* 103856 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35470 /* 103859 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35471 /* 103862 */ GIR_RootConstrainSelectedInstOperands,
35472 /* 103863 */ // GIR_Coverage, 3975,
35473 /* 103863 */ GIR_EraseRootFromParent_Done,
35474 /* 103864 */ // Label 1578: @103864
35475 /* 103864 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(103996), // Rule ID 3983 //
35476 /* 103869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35477 /* 103872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35478 /* 103876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35479 /* 103880 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35480 /* 103884 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35481 /* 103888 */ // MIs[1] Operand 1
35482 /* 103888 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
35483 /* 103893 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35484 /* 103895 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35485 /* 103895 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35486 /* 103898 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
35487 /* 103902 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35488 /* 103907 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35489 /* 103911 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35490 /* 103915 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35491 /* 103917 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35492 /* 103920 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35493 /* 103924 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35494 /* 103929 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35495 /* 103932 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35496 /* 103934 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35497 /* 103937 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35498 /* 103941 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35499 /* 103946 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35500 /* 103949 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35501 /* 103951 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35502 /* 103954 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35503 /* 103958 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35504 /* 103963 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
35505 /* 103970 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35506 /* 103975 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35507 /* 103980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35508 /* 103983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35509 /* 103985 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35510 /* 103988 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35511 /* 103991 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35512 /* 103994 */ GIR_RootConstrainSelectedInstOperands,
35513 /* 103995 */ // GIR_Coverage, 3983,
35514 /* 103995 */ GIR_EraseRootFromParent_Done,
35515 /* 103996 */ // Label 1579: @103996
35516 /* 103996 */ GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(104128), // Rule ID 3991 //
35517 /* 104001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35518 /* 104004 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35519 /* 104008 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35520 /* 104012 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35521 /* 104016 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35522 /* 104020 */ // MIs[1] Operand 1
35523 /* 104020 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
35524 /* 104025 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35525 /* 104027 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35526 /* 104027 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35527 /* 104030 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
35528 /* 104034 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35529 /* 104039 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35530 /* 104043 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35531 /* 104047 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35532 /* 104049 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35533 /* 104052 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35534 /* 104056 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35535 /* 104061 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35536 /* 104064 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35537 /* 104066 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35538 /* 104069 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35539 /* 104073 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35540 /* 104078 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35541 /* 104081 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35542 /* 104083 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35543 /* 104086 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35544 /* 104090 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35545 /* 104095 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
35546 /* 104102 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35547 /* 104107 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35548 /* 104112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35549 /* 104115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35550 /* 104117 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35551 /* 104120 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35552 /* 104123 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35553 /* 104126 */ GIR_RootConstrainSelectedInstOperands,
35554 /* 104127 */ // GIR_Coverage, 3991,
35555 /* 104127 */ GIR_EraseRootFromParent_Done,
35556 /* 104128 */ // Label 1580: @104128
35557 /* 104128 */ GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(104260), // Rule ID 3999 //
35558 /* 104133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
35559 /* 104136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35560 /* 104140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35561 /* 104144 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35562 /* 104148 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35563 /* 104152 */ // MIs[1] Operand 1
35564 /* 104152 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
35565 /* 104157 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35566 /* 104159 */ // (anyext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
35567 /* 104159 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35568 /* 104162 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
35569 /* 104166 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35570 /* 104171 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
35571 /* 104175 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
35572 /* 104179 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35573 /* 104181 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35574 /* 104184 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
35575 /* 104188 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35576 /* 104193 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
35577 /* 104196 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35578 /* 104198 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35579 /* 104201 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
35580 /* 104205 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35581 /* 104210 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
35582 /* 104213 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35583 /* 104215 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
35584 /* 104218 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
35585 /* 104222 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35586 /* 104227 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
35587 /* 104234 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
35588 /* 104239 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
35589 /* 104244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35590 /* 104247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35591 /* 104249 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35592 /* 104252 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35593 /* 104255 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
35594 /* 104258 */ GIR_RootConstrainSelectedInstOperands,
35595 /* 104259 */ // GIR_Coverage, 3999,
35596 /* 104259 */ GIR_EraseRootFromParent_Done,
35597 /* 104260 */ // Label 1581: @104260
35598 /* 104260 */ GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(104275), // Rule ID 2992 //
35599 /* 104265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
35600 /* 104268 */ // (anyext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SETBC:{ *:[i32] } ?:{ *:[i1] }:$in)
35601 /* 104268 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETBC),
35602 /* 104273 */ GIR_RootConstrainSelectedInstOperands,
35603 /* 104274 */ // GIR_Coverage, 2992,
35604 /* 104274 */ GIR_Done,
35605 /* 104275 */ // Label 1582: @104275
35606 /* 104275 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(104329), // Rule ID 3677 //
35607 /* 104280 */ // (anyext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SELECT_I4:{ *:[i32] } ?:{ *:[i1] }:$in, (LI:{ *:[i32] } 1:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }))
35608 /* 104280 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35609 /* 104283 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI),
35610 /* 104287 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35611 /* 104292 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
35612 /* 104295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35613 /* 104297 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35614 /* 104300 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI),
35615 /* 104304 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35616 /* 104309 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
35617 /* 104312 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35618 /* 104314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
35619 /* 104317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35620 /* 104319 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
35621 /* 104321 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35622 /* 104324 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
35623 /* 104327 */ GIR_RootConstrainSelectedInstOperands,
35624 /* 104328 */ // GIR_Coverage, 3677,
35625 /* 104328 */ GIR_EraseRootFromParent_Done,
35626 /* 104329 */ // Label 1583: @104329
35627 /* 104329 */ GIM_Reject,
35628 /* 104330 */ // Label 1491: @104330
35629 /* 104330 */ GIM_Reject,
35630 /* 104331 */ // Label 1489: @104331
35631 /* 104331 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(114845),
35632 /* 104336 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
35633 /* 104339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
35634 /* 104343 */ GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(104452), // Rule ID 5304 //
35635 /* 104348 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35636 /* 104352 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35637 /* 104356 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35638 /* 104360 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35639 /* 104364 */ // MIs[1] Operand 1
35640 /* 104364 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
35641 /* 104369 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
35642 /* 104373 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
35643 /* 104377 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
35644 /* 104381 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
35645 /* 104385 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
35646 /* 104389 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
35647 /* 104393 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
35648 /* 104397 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
35649 /* 104401 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
35650 /* 104405 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
35651 /* 104409 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
35652 /* 104411 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa), i64:{ *:[i64] }:$s1), 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] })
35653 /* 104411 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35654 /* 104414 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
35655 /* 104418 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35656 /* 104423 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/2, // sa
35657 /* 104427 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/64,
35658 /* 104430 */ GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for PPC::CARRY*/0,
35659 /* 104433 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35660 /* 104435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
35661 /* 104438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
35662 /* 104440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // s1
35663 /* 104444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35664 /* 104447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
35665 /* 104450 */ GIR_RootConstrainSelectedInstOperands,
35666 /* 104451 */ // GIR_Coverage, 5304,
35667 /* 104451 */ GIR_EraseRootFromParent_Done,
35668 /* 104452 */ // Label 1585: @104452
35669 /* 104452 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(104615), // Rule ID 5305 //
35670 /* 104457 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35671 /* 104461 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35672 /* 104465 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35673 /* 104469 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35674 /* 104473 */ // MIs[1] Operand 1
35675 /* 104473 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
35676 /* 104478 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
35677 /* 104482 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
35678 /* 104486 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
35679 /* 104490 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
35680 /* 104494 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
35681 /* 104498 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
35682 /* 104502 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
35683 /* 104506 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
35684 /* 104510 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
35685 /* 104514 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
35686 /* 104518 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
35687 /* 104520 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa), i32:{ *:[i32] }:$s1), 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
35688 /* 104520 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35689 /* 104523 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
35690 /* 104527 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35691 /* 104532 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, // sa
35692 /* 104536 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/32,
35693 /* 104539 */ GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for PPC::CARRY*/0,
35694 /* 104542 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35695 /* 104544 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35696 /* 104547 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
35697 /* 104551 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35698 /* 104556 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // s1
35699 /* 104560 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
35700 /* 104563 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
35701 /* 104566 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
35702 /* 104569 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35703 /* 104571 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
35704 /* 104574 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35705 /* 104578 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35706 /* 104583 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35707 /* 104585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
35708 /* 104588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35709 /* 104590 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35710 /* 104593 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
35711 /* 104596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
35712 /* 104599 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
35713 /* 104604 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
35714 /* 104609 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
35715 /* 104614 */ // GIR_Coverage, 5305,
35716 /* 104614 */ GIR_EraseRootFromParent_Done,
35717 /* 104615 */ // Label 1586: @104615
35718 /* 104615 */ GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(104745), // Rule ID 5312 //
35719 /* 104620 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35720 /* 104624 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35721 /* 104628 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35722 /* 104632 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35723 /* 104636 */ // MIs[1] Operand 1
35724 /* 104636 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
35725 /* 104641 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
35726 /* 104645 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
35727 /* 104649 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
35728 /* 104653 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
35729 /* 104657 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
35730 /* 104661 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
35731 /* 104665 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
35732 /* 104669 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
35733 /* 104673 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
35734 /* 104677 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
35735 /* 104681 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
35736 /* 104683 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa), i64:{ *:[i64] }:$s1), 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (RLDCL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] })
35737 /* 104683 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35738 /* 104686 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
35739 /* 104690 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35740 /* 104695 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
35741 /* 104699 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/64,
35742 /* 104702 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
35743 /* 104705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35744 /* 104707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
35745 /* 104710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
35746 /* 104714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35747 /* 104719 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
35748 /* 104723 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
35749 /* 104727 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35750 /* 104729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
35751 /* 104732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
35752 /* 104734 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35753 /* 104737 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
35754 /* 104740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
35755 /* 104743 */ GIR_RootConstrainSelectedInstOperands,
35756 /* 104744 */ // GIR_Coverage, 5312,
35757 /* 104744 */ GIR_EraseRootFromParent_Done,
35758 /* 104745 */ // Label 1587: @104745
35759 /* 104745 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(104929), // Rule ID 5313 //
35760 /* 104750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35761 /* 104754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35762 /* 104758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35763 /* 104762 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35764 /* 104766 */ // MIs[1] Operand 1
35765 /* 104766 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
35766 /* 104771 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
35767 /* 104775 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
35768 /* 104779 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
35769 /* 104783 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
35770 /* 104787 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
35771 /* 104791 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
35772 /* 104795 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
35773 /* 104799 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
35774 /* 104803 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
35775 /* 104807 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
35776 /* 104811 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
35777 /* 104813 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa), i32:{ *:[i32] }:$s1), 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWNM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
35778 /* 104813 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35779 /* 104816 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
35780 /* 104820 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35781 /* 104825 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/3, /*OpIdx*/2, // sa
35782 /* 104829 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/32,
35783 /* 104832 */ GIR_SetImplicitDefDead, /*InsnID*/4, /*OpIdx for PPC::CARRY*/0,
35784 /* 104835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35785 /* 104837 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35786 /* 104840 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
35787 /* 104844 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35788 /* 104849 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // s1
35789 /* 104853 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // s1
35790 /* 104857 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35791 /* 104859 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35792 /* 104862 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
35793 /* 104866 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35794 /* 104871 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
35795 /* 104874 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
35796 /* 104877 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
35797 /* 104880 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
35798 /* 104883 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35799 /* 104885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
35800 /* 104888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35801 /* 104892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35802 /* 104897 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35803 /* 104899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
35804 /* 104902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35805 /* 104904 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35806 /* 104907 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
35807 /* 104910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
35808 /* 104913 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
35809 /* 104918 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
35810 /* 104923 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
35811 /* 104928 */ // GIR_Coverage, 5313,
35812 /* 104928 */ GIR_EraseRootFromParent_Done,
35813 /* 104929 */ // Label 1588: @104929
35814 /* 104929 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(105038), // Rule ID 3782 //
35815 /* 104934 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35816 /* 104938 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35817 /* 104942 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35818 /* 104946 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35819 /* 104950 */ // MIs[1] Operand 1
35820 /* 104950 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
35821 /* 104955 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
35822 /* 104959 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
35823 /* 104963 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
35824 /* 104967 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
35825 /* 104971 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
35826 /* 104975 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
35827 /* 104979 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
35828 /* 104983 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
35829 /* 104987 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
35830 /* 104991 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
35831 /* 104995 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
35832 /* 104997 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i64] } i64:{ *:[i64] }:$s1, (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] })
35833 /* 104997 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
35834 /* 105000 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
35835 /* 105004 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35836 /* 105009 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/2, // sa
35837 /* 105013 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/64,
35838 /* 105016 */ GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for PPC::CARRY*/0,
35839 /* 105019 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35840 /* 105021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
35841 /* 105024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
35842 /* 105026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // s1
35843 /* 105030 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35844 /* 105033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
35845 /* 105036 */ GIR_RootConstrainSelectedInstOperands,
35846 /* 105037 */ // GIR_Coverage, 3782,
35847 /* 105037 */ GIR_EraseRootFromParent_Done,
35848 /* 105038 */ // Label 1589: @105038
35849 /* 105038 */ GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(105201), // Rule ID 3783 //
35850 /* 105043 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35851 /* 105047 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35852 /* 105051 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35853 /* 105055 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35854 /* 105059 */ // MIs[1] Operand 1
35855 /* 105059 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
35856 /* 105064 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
35857 /* 105068 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
35858 /* 105072 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
35859 /* 105076 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
35860 /* 105080 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
35861 /* 105084 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
35862 /* 105088 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
35863 /* 105092 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
35864 /* 105096 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
35865 /* 105100 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
35866 /* 105104 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
35867 /* 105106 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i32] } i32:{ *:[i32] }:$s1, (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
35868 /* 105106 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35869 /* 105109 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
35870 /* 105113 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35871 /* 105118 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, // sa
35872 /* 105122 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/32,
35873 /* 105125 */ GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for PPC::CARRY*/0,
35874 /* 105128 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35875 /* 105130 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35876 /* 105133 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
35877 /* 105137 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35878 /* 105142 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // s1
35879 /* 105146 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
35880 /* 105149 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
35881 /* 105152 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
35882 /* 105155 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35883 /* 105157 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
35884 /* 105160 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35885 /* 105164 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35886 /* 105169 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35887 /* 105171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
35888 /* 105174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35889 /* 105176 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35890 /* 105179 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
35891 /* 105182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
35892 /* 105185 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
35893 /* 105190 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
35894 /* 105195 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
35895 /* 105200 */ // GIR_Coverage, 3783,
35896 /* 105200 */ GIR_EraseRootFromParent_Done,
35897 /* 105201 */ // Label 1590: @105201
35898 /* 105201 */ GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(105331), // Rule ID 3790 //
35899 /* 105206 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35900 /* 105210 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35901 /* 105214 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35902 /* 105218 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35903 /* 105222 */ // MIs[1] Operand 1
35904 /* 105222 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
35905 /* 105227 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
35906 /* 105231 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
35907 /* 105235 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
35908 /* 105239 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
35909 /* 105243 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
35910 /* 105247 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
35911 /* 105251 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
35912 /* 105255 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
35913 /* 105259 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
35914 /* 105263 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
35915 /* 105267 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
35916 /* 105269 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i64] } i64:{ *:[i64] }:$s1, (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (RLDCL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] })
35917 /* 105269 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35918 /* 105272 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
35919 /* 105276 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35920 /* 105281 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
35921 /* 105285 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/64,
35922 /* 105288 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
35923 /* 105291 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35924 /* 105293 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
35925 /* 105296 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
35926 /* 105300 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35927 /* 105305 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
35928 /* 105309 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
35929 /* 105313 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35930 /* 105315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
35931 /* 105318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
35932 /* 105320 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35933 /* 105323 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
35934 /* 105326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
35935 /* 105329 */ GIR_RootConstrainSelectedInstOperands,
35936 /* 105330 */ // GIR_Coverage, 3790,
35937 /* 105330 */ GIR_EraseRootFromParent_Done,
35938 /* 105331 */ // Label 1591: @105331
35939 /* 105331 */ GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(105515), // Rule ID 3791 //
35940 /* 105336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35941 /* 105340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35942 /* 105344 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
35943 /* 105348 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
35944 /* 105352 */ // MIs[1] Operand 1
35945 /* 105352 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
35946 /* 105357 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
35947 /* 105361 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
35948 /* 105365 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
35949 /* 105369 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
35950 /* 105373 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
35951 /* 105377 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
35952 /* 105381 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
35953 /* 105385 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
35954 /* 105389 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
35955 /* 105393 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
35956 /* 105397 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
35957 /* 105399 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i32] } i32:{ *:[i32] }:$s1, (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWNM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
35958 /* 105399 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
35959 /* 105402 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
35960 /* 105406 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35961 /* 105411 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/3, /*OpIdx*/2, // sa
35962 /* 105415 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/32,
35963 /* 105418 */ GIR_SetImplicitDefDead, /*InsnID*/4, /*OpIdx for PPC::CARRY*/0,
35964 /* 105421 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
35965 /* 105423 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
35966 /* 105426 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
35967 /* 105430 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35968 /* 105435 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // s1
35969 /* 105439 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // s1
35970 /* 105443 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
35971 /* 105445 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
35972 /* 105448 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
35973 /* 105452 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35974 /* 105457 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
35975 /* 105460 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
35976 /* 105463 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
35977 /* 105466 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
35978 /* 105469 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
35979 /* 105471 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
35980 /* 105474 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35981 /* 105478 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
35982 /* 105483 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35983 /* 105485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
35984 /* 105488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35985 /* 105490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35986 /* 105493 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
35987 /* 105496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
35988 /* 105499 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
35989 /* 105504 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
35990 /* 105509 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
35991 /* 105514 */ // GIR_Coverage, 3791,
35992 /* 105514 */ GIR_EraseRootFromParent_Done,
35993 /* 105515 */ // Label 1592: @105515
35994 /* 105515 */ GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(105581), // Rule ID 3702 //
35995 /* 105520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35996 /* 105524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
35997 /* 105528 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
35998 /* 105532 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
35999 /* 105536 */ // MIs[1] Operand 1
36000 /* 105536 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
36001 /* 105541 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36002 /* 105545 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36003 /* 105547 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (RLDICL:{ *:[i64] } (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1), 58:{ *:[i32] }, 63:{ *:[i32] })
36004 /* 105547 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36005 /* 105550 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
36006 /* 105554 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36007 /* 105559 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36008 /* 105563 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36009 /* 105565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36010 /* 105568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36011 /* 105570 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36012 /* 105573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/58,
36013 /* 105576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36014 /* 105579 */ GIR_RootConstrainSelectedInstOperands,
36015 /* 105580 */ // GIR_Coverage, 3702,
36016 /* 105580 */ GIR_EraseRootFromParent_Done,
36017 /* 105581 */ // Label 1593: @105581
36018 /* 105581 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(105701), // Rule ID 3703 //
36019 /* 105586 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36020 /* 105590 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36021 /* 105594 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36022 /* 105598 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36023 /* 105602 */ // MIs[1] Operand 1
36024 /* 105602 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
36025 /* 105607 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36026 /* 105611 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36027 /* 105613 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1), 27:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36028 /* 105613 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
36029 /* 105616 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
36030 /* 105620 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36031 /* 105625 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36032 /* 105629 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36033 /* 105631 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36034 /* 105634 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36035 /* 105638 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36036 /* 105643 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
36037 /* 105646 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/27,
36038 /* 105649 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36039 /* 105652 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36040 /* 105655 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36041 /* 105657 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36042 /* 105660 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36043 /* 105664 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36044 /* 105669 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36045 /* 105671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36046 /* 105674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36047 /* 105676 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36048 /* 105679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36049 /* 105682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36050 /* 105685 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36051 /* 105690 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36052 /* 105695 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36053 /* 105700 */ // GIR_Coverage, 3703,
36054 /* 105700 */ GIR_EraseRootFromParent_Done,
36055 /* 105701 */ // Label 1594: @105701
36056 /* 105701 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(105805), // Rule ID 3710 //
36057 /* 105706 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36058 /* 105710 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36059 /* 105714 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36060 /* 105718 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36061 /* 105722 */ // MIs[1] Operand 1
36062 /* 105722 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
36063 /* 105727 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36064 /* 105731 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36065 /* 105733 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1), (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1)), 58:{ *:[i32] }, 63:{ *:[i32] })
36066 /* 105733 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
36067 /* 105736 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
36068 /* 105740 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36069 /* 105745 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36070 /* 105749 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36071 /* 105751 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
36072 /* 105754 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
36073 /* 105758 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36074 /* 105763 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36075 /* 105767 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36076 /* 105769 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36077 /* 105772 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
36078 /* 105776 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36079 /* 105781 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
36080 /* 105784 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
36081 /* 105787 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36082 /* 105789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36083 /* 105792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36084 /* 105794 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36085 /* 105797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/58,
36086 /* 105800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36087 /* 105803 */ GIR_RootConstrainSelectedInstOperands,
36088 /* 105804 */ // GIR_Coverage, 3710,
36089 /* 105804 */ GIR_EraseRootFromParent_Done,
36090 /* 105805 */ // Label 1595: @105805
36091 /* 105805 */ GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(105963), // Rule ID 3711 //
36092 /* 105810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36093 /* 105814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36094 /* 105818 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36095 /* 105822 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36096 /* 105826 */ // MIs[1] Operand 1
36097 /* 105826 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
36098 /* 105831 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36099 /* 105835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36100 /* 105837 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1), (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1)), 27:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36101 /* 105837 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
36102 /* 105840 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
36103 /* 105844 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36104 /* 105849 */ GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // s1
36105 /* 105853 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
36106 /* 105855 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
36107 /* 105858 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
36108 /* 105862 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36109 /* 105867 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
36110 /* 105871 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
36111 /* 105873 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
36112 /* 105876 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
36113 /* 105880 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36114 /* 105885 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
36115 /* 105888 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
36116 /* 105891 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36117 /* 105893 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36118 /* 105896 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36119 /* 105900 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36120 /* 105905 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
36121 /* 105908 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/27,
36122 /* 105911 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36123 /* 105914 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36124 /* 105917 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36125 /* 105919 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36126 /* 105922 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36127 /* 105926 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36128 /* 105931 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36129 /* 105933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36130 /* 105936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36131 /* 105938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36132 /* 105941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36133 /* 105944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36134 /* 105947 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36135 /* 105952 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36136 /* 105957 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36137 /* 105962 */ // GIR_Coverage, 3711,
36138 /* 105962 */ GIR_EraseRootFromParent_Done,
36139 /* 105963 */ // Label 1596: @105963
36140 /* 105963 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(106012), // Rule ID 3718 //
36141 /* 105968 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36142 /* 105972 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36143 /* 105976 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36144 /* 105980 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36145 /* 105984 */ // MIs[1] Operand 1
36146 /* 105984 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
36147 /* 105989 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36148 /* 105993 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36149 /* 105995 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETLT:{ *:[Other] })) => (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i32] }, 63:{ *:[i32] })
36150 /* 105995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36151 /* 105998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36152 /* 106000 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // s1
36153 /* 106004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36154 /* 106007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36155 /* 106010 */ GIR_RootConstrainSelectedInstOperands,
36156 /* 106011 */ // GIR_Coverage, 3718,
36157 /* 106011 */ GIR_EraseRootFromParent_Done,
36158 /* 106012 */ // Label 1597: @106012
36159 /* 106012 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(106115), // Rule ID 3719 //
36160 /* 106017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36161 /* 106021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36162 /* 106025 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36163 /* 106029 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36164 /* 106033 */ // MIs[1] Operand 1
36165 /* 106033 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
36166 /* 106038 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36167 /* 106042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36168 /* 106044 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETLT:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36169 /* 106044 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36170 /* 106047 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36171 /* 106051 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36172 /* 106056 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36173 /* 106060 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36174 /* 106063 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36175 /* 106066 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36176 /* 106069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36177 /* 106071 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36178 /* 106074 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36179 /* 106078 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36180 /* 106083 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36181 /* 106085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36182 /* 106088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36183 /* 106090 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36184 /* 106093 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36185 /* 106096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36186 /* 106099 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36187 /* 106104 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36188 /* 106109 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36189 /* 106114 */ // GIR_Coverage, 3719,
36190 /* 106114 */ GIR_EraseRootFromParent_Done,
36191 /* 106115 */ // Label 1598: @106115
36192 /* 106115 */ GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(106185), // Rule ID 3726 //
36193 /* 106120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36194 /* 106124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36195 /* 106128 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36196 /* 106132 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36197 /* 106136 */ // MIs[1] Operand 1
36198 /* 106136 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
36199 /* 106141 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36200 /* 106145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36201 /* 106147 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETGE:{ *:[Other] })) => (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] })
36202 /* 106147 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36203 /* 106150 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
36204 /* 106154 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36205 /* 106159 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36206 /* 106163 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36207 /* 106167 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36208 /* 106169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36209 /* 106172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36210 /* 106174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36211 /* 106177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36212 /* 106180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36213 /* 106183 */ GIR_RootConstrainSelectedInstOperands,
36214 /* 106184 */ // GIR_Coverage, 3726,
36215 /* 106184 */ GIR_EraseRootFromParent_Done,
36216 /* 106185 */ // Label 1599: @106185
36217 /* 106185 */ GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(106309), // Rule ID 3727 //
36218 /* 106190 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36219 /* 106194 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36220 /* 106198 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36221 /* 106202 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36222 /* 106206 */ // MIs[1] Operand 1
36223 /* 106206 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
36224 /* 106211 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36225 /* 106215 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36226 /* 106217 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETGE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36227 /* 106217 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
36228 /* 106220 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
36229 /* 106224 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36230 /* 106229 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36231 /* 106233 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36232 /* 106237 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36233 /* 106239 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36234 /* 106242 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36235 /* 106246 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36236 /* 106251 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
36237 /* 106254 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36238 /* 106257 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36239 /* 106260 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36240 /* 106263 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36241 /* 106265 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36242 /* 106268 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36243 /* 106272 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36244 /* 106277 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36245 /* 106279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36246 /* 106282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36247 /* 106284 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36248 /* 106287 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36249 /* 106290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36250 /* 106293 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36251 /* 106298 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36252 /* 106303 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36253 /* 106308 */ // GIR_Coverage, 3727,
36254 /* 106308 */ GIR_EraseRootFromParent_Done,
36255 /* 106309 */ // Label 1600: @106309
36256 /* 106309 */ GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(106396), // Rule ID 3734 //
36257 /* 106314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36258 /* 106318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36259 /* 106322 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36260 /* 106326 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36261 /* 106330 */ // MIs[1] Operand 1
36262 /* 106330 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
36263 /* 106335 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36264 /* 106339 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36265 /* 106341 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETGT:{ *:[Other] })) => (RLDICL:{ *:[i64] } (ANDC8:{ *:[i64] } (NEG8:{ *:[i64] } ?:{ *:[i64] }:$s1), ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] })
36266 /* 106341 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
36267 /* 106344 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NEG8),
36268 /* 106348 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36269 /* 106353 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36270 /* 106357 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36271 /* 106359 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36272 /* 106362 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::ANDC8),
36273 /* 106366 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36274 /* 106371 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
36275 /* 106374 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36276 /* 106378 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36277 /* 106380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36278 /* 106383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36279 /* 106385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36280 /* 106388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36281 /* 106391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36282 /* 106394 */ GIR_RootConstrainSelectedInstOperands,
36283 /* 106395 */ // GIR_Coverage, 3734,
36284 /* 106395 */ GIR_EraseRootFromParent_Done,
36285 /* 106396 */ // Label 1601: @106396
36286 /* 106396 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(106537), // Rule ID 3735 //
36287 /* 106401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36288 /* 106405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36289 /* 106409 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36290 /* 106413 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36291 /* 106417 */ // MIs[1] Operand 1
36292 /* 106417 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
36293 /* 106422 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36294 /* 106426 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36295 /* 106428 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETGT:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (ANDC:{ *:[i32] } (NEG:{ *:[i32] } ?:{ *:[i32] }:$s1), ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36296 /* 106428 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
36297 /* 106431 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::NEG),
36298 /* 106435 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36299 /* 106440 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
36300 /* 106444 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
36301 /* 106446 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
36302 /* 106449 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::ANDC),
36303 /* 106453 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36304 /* 106458 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
36305 /* 106461 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36306 /* 106465 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36307 /* 106467 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36308 /* 106470 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36309 /* 106474 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36310 /* 106479 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
36311 /* 106482 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36312 /* 106485 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36313 /* 106488 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36314 /* 106491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36315 /* 106493 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36316 /* 106496 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36317 /* 106500 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36318 /* 106505 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36319 /* 106507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36320 /* 106510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36321 /* 106512 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36322 /* 106515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36323 /* 106518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36324 /* 106521 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36325 /* 106526 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36326 /* 106531 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36327 /* 106536 */ // GIR_Coverage, 3735,
36328 /* 106536 */ GIR_EraseRootFromParent_Done,
36329 /* 106537 */ // Label 1602: @106537
36330 /* 106537 */ GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(106624), // Rule ID 3742 //
36331 /* 106542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36332 /* 106546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36333 /* 106550 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36334 /* 106554 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36335 /* 106558 */ // MIs[1] Operand 1
36336 /* 106558 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
36337 /* 106563 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36338 /* 106567 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36339 /* 106569 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETLE:{ *:[Other] })) => (RLDICL:{ *:[i64] } (ORC8:{ *:[i64] } ?:{ *:[i64] }:$s1, (NEG8:{ *:[i64] } ?:{ *:[i64] }:$s1)), 1:{ *:[i32] }, 63:{ *:[i32] })
36340 /* 106569 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
36341 /* 106572 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NEG8),
36342 /* 106576 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36343 /* 106581 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36344 /* 106585 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36345 /* 106587 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36346 /* 106590 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::ORC8),
36347 /* 106594 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36348 /* 106599 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36349 /* 106603 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
36350 /* 106606 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36351 /* 106608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36352 /* 106611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36353 /* 106613 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36354 /* 106616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36355 /* 106619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36356 /* 106622 */ GIR_RootConstrainSelectedInstOperands,
36357 /* 106623 */ // GIR_Coverage, 3742,
36358 /* 106623 */ GIR_EraseRootFromParent_Done,
36359 /* 106624 */ // Label 1603: @106624
36360 /* 106624 */ GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(106765), // Rule ID 3743 //
36361 /* 106629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36362 /* 106633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36363 /* 106637 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36364 /* 106641 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36365 /* 106645 */ // MIs[1] Operand 1
36366 /* 106645 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
36367 /* 106650 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
36368 /* 106654 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36369 /* 106656 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETLE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (ORC:{ *:[i32] } ?:{ *:[i32] }:$s1, (NEG:{ *:[i32] } ?:{ *:[i32] }:$s1)), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36370 /* 106656 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
36371 /* 106659 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::NEG),
36372 /* 106663 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36373 /* 106668 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
36374 /* 106672 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
36375 /* 106674 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
36376 /* 106677 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::ORC),
36377 /* 106681 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36378 /* 106686 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36379 /* 106690 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
36380 /* 106693 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36381 /* 106695 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36382 /* 106698 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36383 /* 106702 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36384 /* 106707 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
36385 /* 106710 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36386 /* 106713 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36387 /* 106716 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36388 /* 106719 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36389 /* 106721 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36390 /* 106724 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36391 /* 106728 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36392 /* 106733 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36393 /* 106735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36394 /* 106738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36395 /* 106740 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36396 /* 106743 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36397 /* 106746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36398 /* 106749 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36399 /* 106754 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36400 /* 106759 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36401 /* 106764 */ // GIR_Coverage, 3743,
36402 /* 106764 */ GIR_EraseRootFromParent_Done,
36403 /* 106765 */ // Label 1604: @106765
36404 /* 106765 */ GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(106855), // Rule ID 3750 //
36405 /* 106770 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36406 /* 106774 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36407 /* 106778 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36408 /* 106782 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36409 /* 106786 */ // MIs[1] Operand 1
36410 /* 106786 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
36411 /* 106791 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
36412 /* 106795 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36413 /* 106797 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETLT:{ *:[Other] })) => (RLDICL:{ *:[i64] } (AND8:{ *:[i64] } ?:{ *:[i64] }:$s1, (ADDI8:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i64] })), 1:{ *:[i32] }, 63:{ *:[i32] })
36414 /* 106797 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
36415 /* 106800 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
36416 /* 106804 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36417 /* 106809 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36418 /* 106813 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36419 /* 106816 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36420 /* 106818 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36421 /* 106821 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::AND8),
36422 /* 106825 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36423 /* 106830 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36424 /* 106834 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
36425 /* 106837 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36426 /* 106839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36427 /* 106842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36428 /* 106844 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36429 /* 106847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36430 /* 106850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36431 /* 106853 */ GIR_RootConstrainSelectedInstOperands,
36432 /* 106854 */ // GIR_Coverage, 3750,
36433 /* 106854 */ GIR_EraseRootFromParent_Done,
36434 /* 106855 */ // Label 1605: @106855
36435 /* 106855 */ GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(106999), // Rule ID 3751 //
36436 /* 106860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36437 /* 106864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36438 /* 106868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36439 /* 106872 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36440 /* 106876 */ // MIs[1] Operand 1
36441 /* 106876 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
36442 /* 106881 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
36443 /* 106885 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36444 /* 106887 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETLT:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (AND:{ *:[i32] } ?:{ *:[i32] }:$s1, (ADDI:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] })), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36445 /* 106887 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
36446 /* 106890 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::ADDI),
36447 /* 106894 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36448 /* 106899 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
36449 /* 106903 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
36450 /* 106906 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
36451 /* 106908 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
36452 /* 106911 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::AND),
36453 /* 106915 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36454 /* 106920 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36455 /* 106924 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
36456 /* 106927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36457 /* 106929 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36458 /* 106932 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36459 /* 106936 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36460 /* 106941 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
36461 /* 106944 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36462 /* 106947 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36463 /* 106950 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36464 /* 106953 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36465 /* 106955 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36466 /* 106958 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36467 /* 106962 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36468 /* 106967 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36469 /* 106969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36470 /* 106972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36471 /* 106974 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36472 /* 106977 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36473 /* 106980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36474 /* 106983 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36475 /* 106988 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36476 /* 106993 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36477 /* 106998 */ // GIR_Coverage, 3751,
36478 /* 106998 */ GIR_EraseRootFromParent_Done,
36479 /* 106999 */ // Label 1606: @106999
36480 /* 106999 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(107089), // Rule ID 3758 //
36481 /* 107004 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36482 /* 107008 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36483 /* 107012 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36484 /* 107016 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36485 /* 107020 */ // MIs[1] Operand 1
36486 /* 107020 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
36487 /* 107025 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
36488 /* 107029 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36489 /* 107031 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETGE:{ *:[Other] })) => (RLDICL:{ *:[i64] } (NAND8:{ *:[i64] } ?:{ *:[i64] }:$s1, (ADDI8:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i64] })), 1:{ *:[i32] }, 63:{ *:[i32] })
36490 /* 107031 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
36491 /* 107034 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
36492 /* 107038 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36493 /* 107043 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36494 /* 107047 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36495 /* 107050 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36496 /* 107052 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36497 /* 107055 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NAND8),
36498 /* 107059 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36499 /* 107064 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36500 /* 107068 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
36501 /* 107071 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36502 /* 107073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36503 /* 107076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36504 /* 107078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36505 /* 107081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36506 /* 107084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36507 /* 107087 */ GIR_RootConstrainSelectedInstOperands,
36508 /* 107088 */ // GIR_Coverage, 3758,
36509 /* 107088 */ GIR_EraseRootFromParent_Done,
36510 /* 107089 */ // Label 1607: @107089
36511 /* 107089 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(107233), // Rule ID 3759 //
36512 /* 107094 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36513 /* 107098 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36514 /* 107102 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36515 /* 107106 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36516 /* 107110 */ // MIs[1] Operand 1
36517 /* 107110 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
36518 /* 107115 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
36519 /* 107119 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36520 /* 107121 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETGE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (NAND:{ *:[i32] } ?:{ *:[i32] }:$s1, (ADDI:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] })), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36521 /* 107121 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
36522 /* 107124 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::ADDI),
36523 /* 107128 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36524 /* 107133 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
36525 /* 107137 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
36526 /* 107140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
36527 /* 107142 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
36528 /* 107145 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NAND),
36529 /* 107149 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36530 /* 107154 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36531 /* 107158 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
36532 /* 107161 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36533 /* 107163 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36534 /* 107166 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36535 /* 107170 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36536 /* 107175 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
36537 /* 107178 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36538 /* 107181 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36539 /* 107184 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36540 /* 107187 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36541 /* 107189 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36542 /* 107192 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36543 /* 107196 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36544 /* 107201 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36545 /* 107203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36546 /* 107206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36547 /* 107208 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36548 /* 107211 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36549 /* 107214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36550 /* 107217 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36551 /* 107222 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36552 /* 107227 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36553 /* 107232 */ // GIR_Coverage, 3759,
36554 /* 107232 */ GIR_EraseRootFromParent_Done,
36555 /* 107233 */ // Label 1608: @107233
36556 /* 107233 */ GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(107303), // Rule ID 3766 //
36557 /* 107238 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36558 /* 107242 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36559 /* 107246 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36560 /* 107250 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36561 /* 107254 */ // MIs[1] Operand 1
36562 /* 107254 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
36563 /* 107259 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
36564 /* 107263 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36565 /* 107265 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETGT:{ *:[Other] })) => (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] })
36566 /* 107265 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36567 /* 107268 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
36568 /* 107272 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36569 /* 107277 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36570 /* 107281 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
36571 /* 107285 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36572 /* 107287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36573 /* 107290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36574 /* 107292 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36575 /* 107295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36576 /* 107298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36577 /* 107301 */ GIR_RootConstrainSelectedInstOperands,
36578 /* 107302 */ // GIR_Coverage, 3766,
36579 /* 107302 */ GIR_EraseRootFromParent_Done,
36580 /* 107303 */ // Label 1609: @107303
36581 /* 107303 */ GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(107427), // Rule ID 3767 //
36582 /* 107308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36583 /* 107312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36584 /* 107316 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36585 /* 107320 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36586 /* 107324 */ // MIs[1] Operand 1
36587 /* 107324 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
36588 /* 107329 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
36589 /* 107333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36590 /* 107335 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETGT:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36591 /* 107335 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
36592 /* 107338 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
36593 /* 107342 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36594 /* 107347 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36595 /* 107351 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
36596 /* 107355 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36597 /* 107357 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36598 /* 107360 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36599 /* 107364 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36600 /* 107369 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
36601 /* 107372 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36602 /* 107375 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36603 /* 107378 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36604 /* 107381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36605 /* 107383 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36606 /* 107386 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36607 /* 107390 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36608 /* 107395 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36609 /* 107397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36610 /* 107400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36611 /* 107402 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36612 /* 107405 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36613 /* 107408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36614 /* 107411 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36615 /* 107416 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36616 /* 107421 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36617 /* 107426 */ // GIR_Coverage, 3767,
36618 /* 107426 */ GIR_EraseRootFromParent_Done,
36619 /* 107427 */ // Label 1610: @107427
36620 /* 107427 */ GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(107476), // Rule ID 3774 //
36621 /* 107432 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36622 /* 107436 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36623 /* 107440 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36624 /* 107444 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36625 /* 107448 */ // MIs[1] Operand 1
36626 /* 107448 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
36627 /* 107453 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
36628 /* 107457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36629 /* 107459 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETLE:{ *:[Other] })) => (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i32] }, 63:{ *:[i32] })
36630 /* 107459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
36631 /* 107462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
36632 /* 107464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // s1
36633 /* 107468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36634 /* 107471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
36635 /* 107474 */ GIR_RootConstrainSelectedInstOperands,
36636 /* 107475 */ // GIR_Coverage, 3774,
36637 /* 107475 */ GIR_EraseRootFromParent_Done,
36638 /* 107476 */ // Label 1611: @107476
36639 /* 107476 */ GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(107579), // Rule ID 3775 //
36640 /* 107481 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36641 /* 107485 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36642 /* 107489 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36643 /* 107493 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36644 /* 107497 */ // MIs[1] Operand 1
36645 /* 107497 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
36646 /* 107502 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
36647 /* 107506 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36648 /* 107508 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETLE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
36649 /* 107508 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36650 /* 107511 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
36651 /* 107515 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36652 /* 107520 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36653 /* 107524 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
36654 /* 107527 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36655 /* 107530 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
36656 /* 107533 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36657 /* 107535 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
36658 /* 107538 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36659 /* 107542 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36660 /* 107547 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36661 /* 107549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
36662 /* 107552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36663 /* 107554 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36664 /* 107557 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
36665 /* 107560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
36666 /* 107563 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
36667 /* 107568 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
36668 /* 107573 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
36669 /* 107578 */ // GIR_Coverage, 3775,
36670 /* 107578 */ GIR_EraseRootFromParent_Done,
36671 /* 107579 */ // Label 1612: @107579
36672 /* 107579 */ GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(107682), // Rule ID 3041 //
36673 /* 107584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
36674 /* 107587 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36675 /* 107591 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36676 /* 107595 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36677 /* 107599 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36678 /* 107603 */ // MIs[1] Operand 1
36679 /* 107603 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
36680 /* 107608 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36681 /* 107612 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36682 /* 107616 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
36683 /* 107620 */ // MIs[2] Operand 1
36684 /* 107620 */ // No operand predicates
36685 /* 107620 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36686 /* 107622 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }))
36687 /* 107622 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36688 /* 107625 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
36689 /* 107629 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36690 /* 107634 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36691 /* 107638 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36692 /* 107641 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36693 /* 107643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
36694 /* 107646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
36695 /* 107650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36696 /* 107655 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
36697 /* 107662 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
36698 /* 107667 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
36699 /* 107672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
36700 /* 107675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
36701 /* 107677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36702 /* 107680 */ GIR_RootConstrainSelectedInstOperands,
36703 /* 107681 */ // GIR_Coverage, 3041,
36704 /* 107681 */ GIR_EraseRootFromParent_Done,
36705 /* 107682 */ // Label 1613: @107682
36706 /* 107682 */ GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(107785), // Rule ID 3057 //
36707 /* 107687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
36708 /* 107690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36709 /* 107694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36710 /* 107698 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36711 /* 107702 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36712 /* 107706 */ // MIs[1] Operand 1
36713 /* 107706 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
36714 /* 107711 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36715 /* 107715 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36716 /* 107719 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
36717 /* 107723 */ // MIs[2] Operand 1
36718 /* 107723 */ // No operand predicates
36719 /* 107723 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36720 /* 107725 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }))
36721 /* 107725 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36722 /* 107728 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
36723 /* 107732 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36724 /* 107737 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36725 /* 107741 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36726 /* 107744 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36727 /* 107746 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
36728 /* 107749 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
36729 /* 107753 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36730 /* 107758 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
36731 /* 107765 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
36732 /* 107770 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
36733 /* 107775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
36734 /* 107778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
36735 /* 107780 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36736 /* 107783 */ GIR_RootConstrainSelectedInstOperands,
36737 /* 107784 */ // GIR_Coverage, 3057,
36738 /* 107784 */ GIR_EraseRootFromParent_Done,
36739 /* 107785 */ // Label 1614: @107785
36740 /* 107785 */ GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(107888), // Rule ID 3065 //
36741 /* 107790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
36742 /* 107793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36743 /* 107797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36744 /* 107801 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36745 /* 107805 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36746 /* 107809 */ // MIs[1] Operand 1
36747 /* 107809 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
36748 /* 107814 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36749 /* 107818 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36750 /* 107822 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
36751 /* 107826 */ // MIs[2] Operand 1
36752 /* 107826 */ // No operand predicates
36753 /* 107826 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36754 /* 107828 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }))
36755 /* 107828 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36756 /* 107831 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
36757 /* 107835 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36758 /* 107840 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36759 /* 107844 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36760 /* 107847 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36761 /* 107849 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
36762 /* 107852 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
36763 /* 107856 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36764 /* 107861 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
36765 /* 107868 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
36766 /* 107873 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
36767 /* 107878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
36768 /* 107881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
36769 /* 107883 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36770 /* 107886 */ GIR_RootConstrainSelectedInstOperands,
36771 /* 107887 */ // GIR_Coverage, 3065,
36772 /* 107887 */ GIR_EraseRootFromParent_Done,
36773 /* 107888 */ // Label 1615: @107888
36774 /* 107888 */ GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(107991), // Rule ID 3137 //
36775 /* 107893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
36776 /* 107896 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36777 /* 107900 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36778 /* 107904 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36779 /* 107908 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36780 /* 107912 */ // MIs[1] Operand 1
36781 /* 107912 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
36782 /* 107917 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36783 /* 107921 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36784 /* 107925 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
36785 /* 107929 */ // MIs[2] Operand 1
36786 /* 107929 */ // No operand predicates
36787 /* 107929 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36788 /* 107931 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }))
36789 /* 107931 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36790 /* 107934 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
36791 /* 107938 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36792 /* 107943 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36793 /* 107947 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36794 /* 107950 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36795 /* 107952 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
36796 /* 107955 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
36797 /* 107959 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36798 /* 107964 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
36799 /* 107971 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
36800 /* 107976 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
36801 /* 107981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
36802 /* 107984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
36803 /* 107986 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36804 /* 107989 */ GIR_RootConstrainSelectedInstOperands,
36805 /* 107990 */ // GIR_Coverage, 3137,
36806 /* 107990 */ GIR_EraseRootFromParent_Done,
36807 /* 107991 */ // Label 1616: @107991
36808 /* 107991 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(108094), // Rule ID 3153 //
36809 /* 107996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
36810 /* 107999 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36811 /* 108003 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36812 /* 108007 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36813 /* 108011 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36814 /* 108015 */ // MIs[1] Operand 1
36815 /* 108015 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
36816 /* 108020 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36817 /* 108024 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36818 /* 108028 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
36819 /* 108032 */ // MIs[2] Operand 1
36820 /* 108032 */ // No operand predicates
36821 /* 108032 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36822 /* 108034 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }))
36823 /* 108034 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36824 /* 108037 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
36825 /* 108041 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36826 /* 108046 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36827 /* 108050 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36828 /* 108053 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36829 /* 108055 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
36830 /* 108058 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
36831 /* 108062 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36832 /* 108067 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
36833 /* 108074 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
36834 /* 108079 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
36835 /* 108084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
36836 /* 108087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
36837 /* 108089 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36838 /* 108092 */ GIR_RootConstrainSelectedInstOperands,
36839 /* 108093 */ // GIR_Coverage, 3153,
36840 /* 108093 */ GIR_EraseRootFromParent_Done,
36841 /* 108094 */ // Label 1617: @108094
36842 /* 108094 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(108197), // Rule ID 3161 //
36843 /* 108099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
36844 /* 108102 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36845 /* 108106 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36846 /* 108110 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
36847 /* 108114 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
36848 /* 108118 */ // MIs[1] Operand 1
36849 /* 108118 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
36850 /* 108123 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36851 /* 108127 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36852 /* 108131 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
36853 /* 108135 */ // MIs[2] Operand 1
36854 /* 108135 */ // No operand predicates
36855 /* 108135 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36856 /* 108137 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }))
36857 /* 108137 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36858 /* 108140 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
36859 /* 108144 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36860 /* 108149 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36861 /* 108153 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36862 /* 108156 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36863 /* 108158 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
36864 /* 108161 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
36865 /* 108165 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36866 /* 108170 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
36867 /* 108177 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
36868 /* 108182 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
36869 /* 108187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
36870 /* 108190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
36871 /* 108192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36872 /* 108195 */ GIR_RootConstrainSelectedInstOperands,
36873 /* 108196 */ // GIR_Coverage, 3161,
36874 /* 108196 */ GIR_EraseRootFromParent_Done,
36875 /* 108197 */ // Label 1618: @108197
36876 /* 108197 */ GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(108340), // Rule ID 3824 //
36877 /* 108202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
36878 /* 108205 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36879 /* 108209 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36880 /* 108213 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36881 /* 108217 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36882 /* 108221 */ // MIs[1] Operand 1
36883 /* 108221 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
36884 /* 108226 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36885 /* 108230 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36886 /* 108234 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
36887 /* 108238 */ // MIs[2] Operand 1
36888 /* 108238 */ // No operand predicates
36889 /* 108238 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36890 /* 108240 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
36891 /* 108240 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36892 /* 108243 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
36893 /* 108247 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36894 /* 108252 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36895 /* 108256 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36896 /* 108259 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36897 /* 108261 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
36898 /* 108264 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
36899 /* 108268 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36900 /* 108273 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
36901 /* 108276 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
36902 /* 108278 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
36903 /* 108281 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
36904 /* 108285 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36905 /* 108290 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
36906 /* 108293 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36907 /* 108295 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
36908 /* 108298 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
36909 /* 108302 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36910 /* 108307 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
36911 /* 108314 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
36912 /* 108319 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
36913 /* 108324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
36914 /* 108327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36915 /* 108329 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36916 /* 108332 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
36917 /* 108335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
36918 /* 108338 */ GIR_RootConstrainSelectedInstOperands,
36919 /* 108339 */ // GIR_Coverage, 3824,
36920 /* 108339 */ GIR_EraseRootFromParent_Done,
36921 /* 108340 */ // Label 1619: @108340
36922 /* 108340 */ GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(108483), // Rule ID 3840 //
36923 /* 108345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
36924 /* 108348 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36925 /* 108352 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36926 /* 108356 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36927 /* 108360 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36928 /* 108364 */ // MIs[1] Operand 1
36929 /* 108364 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
36930 /* 108369 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36931 /* 108373 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36932 /* 108377 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
36933 /* 108381 */ // MIs[2] Operand 1
36934 /* 108381 */ // No operand predicates
36935 /* 108381 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36936 /* 108383 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
36937 /* 108383 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36938 /* 108386 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
36939 /* 108390 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36940 /* 108395 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36941 /* 108399 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36942 /* 108402 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36943 /* 108404 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
36944 /* 108407 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
36945 /* 108411 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36946 /* 108416 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
36947 /* 108419 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
36948 /* 108421 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
36949 /* 108424 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
36950 /* 108428 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36951 /* 108433 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
36952 /* 108436 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36953 /* 108438 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
36954 /* 108441 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
36955 /* 108445 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36956 /* 108450 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
36957 /* 108457 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
36958 /* 108462 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
36959 /* 108467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
36960 /* 108470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
36961 /* 108472 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36962 /* 108475 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
36963 /* 108478 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
36964 /* 108481 */ GIR_RootConstrainSelectedInstOperands,
36965 /* 108482 */ // GIR_Coverage, 3840,
36966 /* 108482 */ GIR_EraseRootFromParent_Done,
36967 /* 108483 */ // Label 1620: @108483
36968 /* 108483 */ GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(108626), // Rule ID 3848 //
36969 /* 108488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
36970 /* 108491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36971 /* 108495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
36972 /* 108499 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
36973 /* 108503 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
36974 /* 108507 */ // MIs[1] Operand 1
36975 /* 108507 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
36976 /* 108512 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
36977 /* 108516 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36978 /* 108520 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
36979 /* 108524 */ // MIs[2] Operand 1
36980 /* 108524 */ // No operand predicates
36981 /* 108524 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
36982 /* 108526 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
36983 /* 108526 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
36984 /* 108529 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
36985 /* 108533 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36986 /* 108538 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
36987 /* 108542 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
36988 /* 108545 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
36989 /* 108547 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
36990 /* 108550 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
36991 /* 108554 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36992 /* 108559 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
36993 /* 108562 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
36994 /* 108564 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
36995 /* 108567 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
36996 /* 108571 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36997 /* 108576 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
36998 /* 108579 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
36999 /* 108581 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37000 /* 108584 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37001 /* 108588 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37002 /* 108593 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
37003 /* 108600 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37004 /* 108605 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37005 /* 108610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37006 /* 108613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37007 /* 108615 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37008 /* 108618 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37009 /* 108621 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37010 /* 108624 */ GIR_RootConstrainSelectedInstOperands,
37011 /* 108625 */ // GIR_Coverage, 3848,
37012 /* 108625 */ GIR_EraseRootFromParent_Done,
37013 /* 108626 */ // Label 1621: @108626
37014 /* 108626 */ GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(108769), // Rule ID 3920 //
37015 /* 108631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
37016 /* 108634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37017 /* 108638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
37018 /* 108642 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37019 /* 108646 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37020 /* 108650 */ // MIs[1] Operand 1
37021 /* 108650 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
37022 /* 108655 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
37023 /* 108659 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
37024 /* 108663 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
37025 /* 108667 */ // MIs[2] Operand 1
37026 /* 108667 */ // No operand predicates
37027 /* 108667 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
37028 /* 108669 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37029 /* 108669 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37030 /* 108672 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
37031 /* 108676 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37032 /* 108681 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37033 /* 108685 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
37034 /* 108688 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37035 /* 108690 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37036 /* 108693 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37037 /* 108697 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37038 /* 108702 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37039 /* 108705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37040 /* 108707 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37041 /* 108710 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37042 /* 108714 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37043 /* 108719 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37044 /* 108722 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37045 /* 108724 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37046 /* 108727 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37047 /* 108731 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37048 /* 108736 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
37049 /* 108743 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37050 /* 108748 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37051 /* 108753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37052 /* 108756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37053 /* 108758 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37054 /* 108761 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37055 /* 108764 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37056 /* 108767 */ GIR_RootConstrainSelectedInstOperands,
37057 /* 108768 */ // GIR_Coverage, 3920,
37058 /* 108768 */ GIR_EraseRootFromParent_Done,
37059 /* 108769 */ // Label 1622: @108769
37060 /* 108769 */ GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(108912), // Rule ID 3936 //
37061 /* 108774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
37062 /* 108777 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37063 /* 108781 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
37064 /* 108785 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37065 /* 108789 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37066 /* 108793 */ // MIs[1] Operand 1
37067 /* 108793 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
37068 /* 108798 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
37069 /* 108802 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
37070 /* 108806 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
37071 /* 108810 */ // MIs[2] Operand 1
37072 /* 108810 */ // No operand predicates
37073 /* 108810 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
37074 /* 108812 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37075 /* 108812 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37076 /* 108815 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
37077 /* 108819 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37078 /* 108824 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37079 /* 108828 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
37080 /* 108831 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37081 /* 108833 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37082 /* 108836 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37083 /* 108840 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37084 /* 108845 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37085 /* 108848 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37086 /* 108850 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37087 /* 108853 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37088 /* 108857 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37089 /* 108862 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37090 /* 108865 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37091 /* 108867 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37092 /* 108870 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37093 /* 108874 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37094 /* 108879 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
37095 /* 108886 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37096 /* 108891 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37097 /* 108896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37098 /* 108899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37099 /* 108901 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37100 /* 108904 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37101 /* 108907 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37102 /* 108910 */ GIR_RootConstrainSelectedInstOperands,
37103 /* 108911 */ // GIR_Coverage, 3936,
37104 /* 108911 */ GIR_EraseRootFromParent_Done,
37105 /* 108912 */ // Label 1623: @108912
37106 /* 108912 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(109055), // Rule ID 3944 //
37107 /* 108917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
37108 /* 108920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37109 /* 108924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
37110 /* 108928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37111 /* 108932 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37112 /* 108936 */ // MIs[1] Operand 1
37113 /* 108936 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
37114 /* 108941 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
37115 /* 108945 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
37116 /* 108949 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
37117 /* 108953 */ // MIs[2] Operand 1
37118 /* 108953 */ // No operand predicates
37119 /* 108953 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
37120 /* 108955 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37121 /* 108955 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37122 /* 108958 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
37123 /* 108962 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37124 /* 108967 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37125 /* 108971 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
37126 /* 108974 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37127 /* 108976 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37128 /* 108979 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37129 /* 108983 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37130 /* 108988 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37131 /* 108991 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37132 /* 108993 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37133 /* 108996 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37134 /* 109000 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37135 /* 109005 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37136 /* 109008 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37137 /* 109010 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37138 /* 109013 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37139 /* 109017 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37140 /* 109022 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
37141 /* 109029 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37142 /* 109034 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37143 /* 109039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37144 /* 109042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37145 /* 109044 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37146 /* 109047 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37147 /* 109050 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37148 /* 109053 */ GIR_RootConstrainSelectedInstOperands,
37149 /* 109054 */ // GIR_Coverage, 3944,
37150 /* 109054 */ GIR_EraseRootFromParent_Done,
37151 /* 109055 */ // Label 1624: @109055
37152 /* 109055 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(109147), // Rule ID 3185 //
37153 /* 109060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37154 /* 109063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37155 /* 109067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37156 /* 109071 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37157 /* 109075 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37158 /* 109079 */ // MIs[1] Operand 1
37159 /* 109079 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
37160 /* 109084 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37161 /* 109086 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }))
37162 /* 109086 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37163 /* 109089 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
37164 /* 109093 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37165 /* 109098 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37166 /* 109102 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37167 /* 109106 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37168 /* 109108 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37169 /* 109111 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37170 /* 109115 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37171 /* 109120 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
37172 /* 109127 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37173 /* 109132 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37174 /* 109137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37175 /* 109140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37176 /* 109142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37177 /* 109145 */ GIR_RootConstrainSelectedInstOperands,
37178 /* 109146 */ // GIR_Coverage, 3185,
37179 /* 109146 */ GIR_EraseRootFromParent_Done,
37180 /* 109147 */ // Label 1625: @109147
37181 /* 109147 */ GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(109239), // Rule ID 3201 //
37182 /* 109152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37183 /* 109155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37184 /* 109159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37185 /* 109163 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37186 /* 109167 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37187 /* 109171 */ // MIs[1] Operand 1
37188 /* 109171 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
37189 /* 109176 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37190 /* 109178 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
37191 /* 109178 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37192 /* 109181 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
37193 /* 109185 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37194 /* 109190 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37195 /* 109194 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37196 /* 109198 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37197 /* 109200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37198 /* 109203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37199 /* 109207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37200 /* 109212 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
37201 /* 109219 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37202 /* 109224 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37203 /* 109229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37204 /* 109232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37205 /* 109234 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37206 /* 109237 */ GIR_RootConstrainSelectedInstOperands,
37207 /* 109238 */ // GIR_Coverage, 3201,
37208 /* 109238 */ GIR_EraseRootFromParent_Done,
37209 /* 109239 */ // Label 1626: @109239
37210 /* 109239 */ GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(109331), // Rule ID 3217 //
37211 /* 109244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37212 /* 109247 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37213 /* 109251 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37214 /* 109255 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37215 /* 109259 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37216 /* 109263 */ // MIs[1] Operand 1
37217 /* 109263 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
37218 /* 109268 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37219 /* 109270 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }))
37220 /* 109270 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37221 /* 109273 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
37222 /* 109277 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37223 /* 109282 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37224 /* 109286 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37225 /* 109290 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37226 /* 109292 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37227 /* 109295 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37228 /* 109299 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37229 /* 109304 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
37230 /* 109311 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37231 /* 109316 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37232 /* 109321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37233 /* 109324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37234 /* 109326 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37235 /* 109329 */ GIR_RootConstrainSelectedInstOperands,
37236 /* 109330 */ // GIR_Coverage, 3217,
37237 /* 109330 */ GIR_EraseRootFromParent_Done,
37238 /* 109331 */ // Label 1627: @109331
37239 /* 109331 */ GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(109423), // Rule ID 3233 //
37240 /* 109336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37241 /* 109339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37242 /* 109343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37243 /* 109347 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37244 /* 109351 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37245 /* 109355 */ // MIs[1] Operand 1
37246 /* 109355 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
37247 /* 109360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37248 /* 109362 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }))
37249 /* 109362 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37250 /* 109365 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
37251 /* 109369 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37252 /* 109374 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37253 /* 109378 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37254 /* 109382 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37255 /* 109384 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37256 /* 109387 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37257 /* 109391 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37258 /* 109396 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
37259 /* 109403 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37260 /* 109408 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37261 /* 109413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37262 /* 109416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37263 /* 109418 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37264 /* 109421 */ GIR_RootConstrainSelectedInstOperands,
37265 /* 109422 */ // GIR_Coverage, 3233,
37266 /* 109422 */ GIR_EraseRootFromParent_Done,
37267 /* 109423 */ // Label 1628: @109423
37268 /* 109423 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(109515), // Rule ID 3241 //
37269 /* 109428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37270 /* 109431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37271 /* 109435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37272 /* 109439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37273 /* 109443 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37274 /* 109447 */ // MIs[1] Operand 1
37275 /* 109447 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
37276 /* 109452 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37277 /* 109454 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }))
37278 /* 109454 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37279 /* 109457 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
37280 /* 109461 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37281 /* 109466 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37282 /* 109470 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37283 /* 109474 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37284 /* 109476 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37285 /* 109479 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37286 /* 109483 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37287 /* 109488 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
37288 /* 109495 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37289 /* 109500 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37290 /* 109505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37291 /* 109508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37292 /* 109510 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37293 /* 109513 */ GIR_RootConstrainSelectedInstOperands,
37294 /* 109514 */ // GIR_Coverage, 3241,
37295 /* 109514 */ GIR_EraseRootFromParent_Done,
37296 /* 109515 */ // Label 1629: @109515
37297 /* 109515 */ GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(109607), // Rule ID 3257 //
37298 /* 109520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37299 /* 109523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37300 /* 109527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37301 /* 109531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37302 /* 109535 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37303 /* 109539 */ // MIs[1] Operand 1
37304 /* 109539 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
37305 /* 109544 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37306 /* 109546 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
37307 /* 109546 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37308 /* 109549 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
37309 /* 109553 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37310 /* 109558 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37311 /* 109562 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37312 /* 109566 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37313 /* 109568 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37314 /* 109571 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37315 /* 109575 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37316 /* 109580 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
37317 /* 109587 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37318 /* 109592 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37319 /* 109597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37320 /* 109600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37321 /* 109602 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37322 /* 109605 */ GIR_RootConstrainSelectedInstOperands,
37323 /* 109606 */ // GIR_Coverage, 3257,
37324 /* 109606 */ GIR_EraseRootFromParent_Done,
37325 /* 109607 */ // Label 1630: @109607
37326 /* 109607 */ GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(109699), // Rule ID 3273 //
37327 /* 109612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37328 /* 109615 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37329 /* 109619 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37330 /* 109623 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37331 /* 109627 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37332 /* 109631 */ // MIs[1] Operand 1
37333 /* 109631 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
37334 /* 109636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37335 /* 109638 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }))
37336 /* 109638 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37337 /* 109641 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
37338 /* 109645 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37339 /* 109650 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37340 /* 109654 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37341 /* 109658 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37342 /* 109660 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37343 /* 109663 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37344 /* 109667 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37345 /* 109672 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
37346 /* 109679 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37347 /* 109684 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37348 /* 109689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37349 /* 109692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37350 /* 109694 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37351 /* 109697 */ GIR_RootConstrainSelectedInstOperands,
37352 /* 109698 */ // GIR_Coverage, 3273,
37353 /* 109698 */ GIR_EraseRootFromParent_Done,
37354 /* 109699 */ // Label 1631: @109699
37355 /* 109699 */ GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(109791), // Rule ID 3289 //
37356 /* 109704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37357 /* 109707 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37358 /* 109711 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37359 /* 109715 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37360 /* 109719 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37361 /* 109723 */ // MIs[1] Operand 1
37362 /* 109723 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
37363 /* 109728 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37364 /* 109730 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }))
37365 /* 109730 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37366 /* 109733 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
37367 /* 109737 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37368 /* 109742 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37369 /* 109746 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37370 /* 109750 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37371 /* 109752 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37372 /* 109755 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37373 /* 109759 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37374 /* 109764 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
37375 /* 109771 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37376 /* 109776 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37377 /* 109781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37378 /* 109784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37379 /* 109786 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37380 /* 109789 */ GIR_RootConstrainSelectedInstOperands,
37381 /* 109790 */ // GIR_Coverage, 3289,
37382 /* 109790 */ GIR_EraseRootFromParent_Done,
37383 /* 109791 */ // Label 1632: @109791
37384 /* 109791 */ GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(109883), // Rule ID 3297 //
37385 /* 109796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37386 /* 109799 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37387 /* 109803 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37388 /* 109807 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
37389 /* 109811 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
37390 /* 109815 */ // MIs[1] Operand 1
37391 /* 109815 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
37392 /* 109820 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37393 /* 109822 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }))
37394 /* 109822 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37395 /* 109825 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
37396 /* 109829 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37397 /* 109834 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37398 /* 109838 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37399 /* 109842 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37400 /* 109844 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37401 /* 109847 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37402 /* 109851 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37403 /* 109856 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
37404 /* 109863 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37405 /* 109868 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37406 /* 109873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37407 /* 109876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37408 /* 109878 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37409 /* 109881 */ GIR_RootConstrainSelectedInstOperands,
37410 /* 109882 */ // GIR_Coverage, 3297,
37411 /* 109882 */ GIR_EraseRootFromParent_Done,
37412 /* 109883 */ // Label 1633: @109883
37413 /* 109883 */ GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(109975), // Rule ID 3313 //
37414 /* 109888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37415 /* 109891 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37416 /* 109895 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37417 /* 109899 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
37418 /* 109903 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
37419 /* 109907 */ // MIs[1] Operand 1
37420 /* 109907 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
37421 /* 109912 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37422 /* 109914 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }))
37423 /* 109914 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37424 /* 109917 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
37425 /* 109921 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37426 /* 109926 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37427 /* 109930 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37428 /* 109934 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37429 /* 109936 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37430 /* 109939 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37431 /* 109943 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37432 /* 109948 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
37433 /* 109955 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37434 /* 109960 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37435 /* 109965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37436 /* 109968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37437 /* 109970 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37438 /* 109973 */ GIR_RootConstrainSelectedInstOperands,
37439 /* 109974 */ // GIR_Coverage, 3313,
37440 /* 109974 */ GIR_EraseRootFromParent_Done,
37441 /* 109975 */ // Label 1634: @109975
37442 /* 109975 */ GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(110067), // Rule ID 3329 //
37443 /* 109980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37444 /* 109983 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37445 /* 109987 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37446 /* 109991 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
37447 /* 109995 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
37448 /* 109999 */ // MIs[1] Operand 1
37449 /* 109999 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
37450 /* 110004 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37451 /* 110006 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }))
37452 /* 110006 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37453 /* 110009 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
37454 /* 110013 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37455 /* 110018 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37456 /* 110022 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37457 /* 110026 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37458 /* 110028 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37459 /* 110031 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37460 /* 110035 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37461 /* 110040 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
37462 /* 110047 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37463 /* 110052 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37464 /* 110057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37465 /* 110060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37466 /* 110062 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37467 /* 110065 */ GIR_RootConstrainSelectedInstOperands,
37468 /* 110066 */ // GIR_Coverage, 3329,
37469 /* 110066 */ GIR_EraseRootFromParent_Done,
37470 /* 110067 */ // Label 1635: @110067
37471 /* 110067 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(110159), // Rule ID 3345 //
37472 /* 110072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
37473 /* 110075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37474 /* 110079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37475 /* 110083 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
37476 /* 110087 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
37477 /* 110091 */ // MIs[1] Operand 1
37478 /* 110091 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
37479 /* 110096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37480 /* 110098 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }))
37481 /* 110098 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37482 /* 110101 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
37483 /* 110105 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37484 /* 110110 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37485 /* 110114 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37486 /* 110118 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37487 /* 110120 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37488 /* 110123 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37489 /* 110127 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37490 /* 110132 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
37491 /* 110139 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37492 /* 110144 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37493 /* 110149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
37494 /* 110152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
37495 /* 110154 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37496 /* 110157 */ GIR_RootConstrainSelectedInstOperands,
37497 /* 110158 */ // GIR_Coverage, 3345,
37498 /* 110158 */ GIR_EraseRootFromParent_Done,
37499 /* 110159 */ // Label 1636: @110159
37500 /* 110159 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(110291), // Rule ID 4030 //
37501 /* 110164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37502 /* 110167 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37503 /* 110171 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37504 /* 110175 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37505 /* 110179 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37506 /* 110183 */ // MIs[1] Operand 1
37507 /* 110183 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
37508 /* 110188 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37509 /* 110190 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37510 /* 110190 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37511 /* 110193 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
37512 /* 110197 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37513 /* 110202 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37514 /* 110206 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37515 /* 110210 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37516 /* 110212 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37517 /* 110215 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37518 /* 110219 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37519 /* 110224 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37520 /* 110227 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37521 /* 110229 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37522 /* 110232 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37523 /* 110236 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37524 /* 110241 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37525 /* 110244 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37526 /* 110246 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37527 /* 110249 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37528 /* 110253 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37529 /* 110258 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
37530 /* 110265 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37531 /* 110270 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37532 /* 110275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37533 /* 110278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37534 /* 110280 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37535 /* 110283 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37536 /* 110286 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37537 /* 110289 */ GIR_RootConstrainSelectedInstOperands,
37538 /* 110290 */ // GIR_Coverage, 4030,
37539 /* 110290 */ GIR_EraseRootFromParent_Done,
37540 /* 110291 */ // Label 1637: @110291
37541 /* 110291 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(110423), // Rule ID 4062 //
37542 /* 110296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37543 /* 110299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37544 /* 110303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37545 /* 110307 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37546 /* 110311 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37547 /* 110315 */ // MIs[1] Operand 1
37548 /* 110315 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
37549 /* 110320 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37550 /* 110322 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37551 /* 110322 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37552 /* 110325 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
37553 /* 110329 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37554 /* 110334 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37555 /* 110338 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37556 /* 110342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37557 /* 110344 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37558 /* 110347 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37559 /* 110351 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37560 /* 110356 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37561 /* 110359 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37562 /* 110361 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37563 /* 110364 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37564 /* 110368 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37565 /* 110373 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37566 /* 110376 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37567 /* 110378 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37568 /* 110381 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37569 /* 110385 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37570 /* 110390 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
37571 /* 110397 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37572 /* 110402 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37573 /* 110407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37574 /* 110410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37575 /* 110412 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37576 /* 110415 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37577 /* 110418 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37578 /* 110421 */ GIR_RootConstrainSelectedInstOperands,
37579 /* 110422 */ // GIR_Coverage, 4062,
37580 /* 110422 */ GIR_EraseRootFromParent_Done,
37581 /* 110423 */ // Label 1638: @110423
37582 /* 110423 */ GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(110555), // Rule ID 4094 //
37583 /* 110428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37584 /* 110431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37585 /* 110435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37586 /* 110439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37587 /* 110443 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37588 /* 110447 */ // MIs[1] Operand 1
37589 /* 110447 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
37590 /* 110452 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37591 /* 110454 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37592 /* 110454 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37593 /* 110457 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
37594 /* 110461 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37595 /* 110466 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37596 /* 110470 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37597 /* 110474 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37598 /* 110476 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37599 /* 110479 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37600 /* 110483 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37601 /* 110488 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37602 /* 110491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37603 /* 110493 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37604 /* 110496 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37605 /* 110500 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37606 /* 110505 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37607 /* 110508 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37608 /* 110510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37609 /* 110513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37610 /* 110517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37611 /* 110522 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
37612 /* 110529 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37613 /* 110534 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37614 /* 110539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37615 /* 110542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37616 /* 110544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37617 /* 110547 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37618 /* 110550 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37619 /* 110553 */ GIR_RootConstrainSelectedInstOperands,
37620 /* 110554 */ // GIR_Coverage, 4094,
37621 /* 110554 */ GIR_EraseRootFromParent_Done,
37622 /* 110555 */ // Label 1639: @110555
37623 /* 110555 */ GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(110687), // Rule ID 4126 //
37624 /* 110560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37625 /* 110563 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37626 /* 110567 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37627 /* 110571 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37628 /* 110575 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37629 /* 110579 */ // MIs[1] Operand 1
37630 /* 110579 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
37631 /* 110584 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37632 /* 110586 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37633 /* 110586 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37634 /* 110589 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
37635 /* 110593 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37636 /* 110598 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37637 /* 110602 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37638 /* 110606 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37639 /* 110608 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37640 /* 110611 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37641 /* 110615 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37642 /* 110620 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37643 /* 110623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37644 /* 110625 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37645 /* 110628 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37646 /* 110632 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37647 /* 110637 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37648 /* 110640 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37649 /* 110642 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37650 /* 110645 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37651 /* 110649 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37652 /* 110654 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
37653 /* 110661 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37654 /* 110666 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37655 /* 110671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37656 /* 110674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37657 /* 110676 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37658 /* 110679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37659 /* 110682 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37660 /* 110685 */ GIR_RootConstrainSelectedInstOperands,
37661 /* 110686 */ // GIR_Coverage, 4126,
37662 /* 110686 */ GIR_EraseRootFromParent_Done,
37663 /* 110687 */ // Label 1640: @110687
37664 /* 110687 */ GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(110819), // Rule ID 4142 //
37665 /* 110692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37666 /* 110695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37667 /* 110699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37668 /* 110703 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37669 /* 110707 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37670 /* 110711 */ // MIs[1] Operand 1
37671 /* 110711 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
37672 /* 110716 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37673 /* 110718 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37674 /* 110718 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37675 /* 110721 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
37676 /* 110725 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37677 /* 110730 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37678 /* 110734 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37679 /* 110738 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37680 /* 110740 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37681 /* 110743 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37682 /* 110747 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37683 /* 110752 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37684 /* 110755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37685 /* 110757 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37686 /* 110760 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37687 /* 110764 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37688 /* 110769 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37689 /* 110772 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37690 /* 110774 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37691 /* 110777 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37692 /* 110781 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37693 /* 110786 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
37694 /* 110793 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37695 /* 110798 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37696 /* 110803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37697 /* 110806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37698 /* 110808 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37699 /* 110811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37700 /* 110814 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37701 /* 110817 */ GIR_RootConstrainSelectedInstOperands,
37702 /* 110818 */ // GIR_Coverage, 4142,
37703 /* 110818 */ GIR_EraseRootFromParent_Done,
37704 /* 110819 */ // Label 1641: @110819
37705 /* 110819 */ GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(110951), // Rule ID 4174 //
37706 /* 110824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37707 /* 110827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37708 /* 110831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37709 /* 110835 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37710 /* 110839 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37711 /* 110843 */ // MIs[1] Operand 1
37712 /* 110843 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
37713 /* 110848 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37714 /* 110850 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37715 /* 110850 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37716 /* 110853 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
37717 /* 110857 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37718 /* 110862 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37719 /* 110866 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37720 /* 110870 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37721 /* 110872 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37722 /* 110875 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37723 /* 110879 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37724 /* 110884 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37725 /* 110887 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37726 /* 110889 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37727 /* 110892 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37728 /* 110896 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37729 /* 110901 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37730 /* 110904 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37731 /* 110906 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37732 /* 110909 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37733 /* 110913 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37734 /* 110918 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
37735 /* 110925 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37736 /* 110930 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37737 /* 110935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37738 /* 110938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37739 /* 110940 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37740 /* 110943 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37741 /* 110946 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37742 /* 110949 */ GIR_RootConstrainSelectedInstOperands,
37743 /* 110950 */ // GIR_Coverage, 4174,
37744 /* 110950 */ GIR_EraseRootFromParent_Done,
37745 /* 110951 */ // Label 1642: @110951
37746 /* 110951 */ GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(111083), // Rule ID 4206 //
37747 /* 110956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37748 /* 110959 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37749 /* 110963 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37750 /* 110967 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37751 /* 110971 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37752 /* 110975 */ // MIs[1] Operand 1
37753 /* 110975 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
37754 /* 110980 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37755 /* 110982 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37756 /* 110982 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37757 /* 110985 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
37758 /* 110989 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37759 /* 110994 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37760 /* 110998 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37761 /* 111002 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37762 /* 111004 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37763 /* 111007 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37764 /* 111011 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37765 /* 111016 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37766 /* 111019 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37767 /* 111021 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37768 /* 111024 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37769 /* 111028 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37770 /* 111033 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37771 /* 111036 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37772 /* 111038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37773 /* 111041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37774 /* 111045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37775 /* 111050 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
37776 /* 111057 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37777 /* 111062 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37778 /* 111067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37779 /* 111070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37780 /* 111072 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37781 /* 111075 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37782 /* 111078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37783 /* 111081 */ GIR_RootConstrainSelectedInstOperands,
37784 /* 111082 */ // GIR_Coverage, 4206,
37785 /* 111082 */ GIR_EraseRootFromParent_Done,
37786 /* 111083 */ // Label 1643: @111083
37787 /* 111083 */ GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(111215), // Rule ID 4238 //
37788 /* 111088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37789 /* 111091 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37790 /* 111095 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37791 /* 111099 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
37792 /* 111103 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
37793 /* 111107 */ // MIs[1] Operand 1
37794 /* 111107 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
37795 /* 111112 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37796 /* 111114 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37797 /* 111114 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37798 /* 111117 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
37799 /* 111121 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37800 /* 111126 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37801 /* 111130 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37802 /* 111134 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37803 /* 111136 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37804 /* 111139 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37805 /* 111143 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37806 /* 111148 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37807 /* 111151 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37808 /* 111153 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37809 /* 111156 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37810 /* 111160 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37811 /* 111165 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37812 /* 111168 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37813 /* 111170 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37814 /* 111173 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37815 /* 111177 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37816 /* 111182 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
37817 /* 111189 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37818 /* 111194 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37819 /* 111199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37820 /* 111202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37821 /* 111204 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37822 /* 111207 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37823 /* 111210 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37824 /* 111213 */ GIR_RootConstrainSelectedInstOperands,
37825 /* 111214 */ // GIR_Coverage, 4238,
37826 /* 111214 */ GIR_EraseRootFromParent_Done,
37827 /* 111215 */ // Label 1644: @111215
37828 /* 111215 */ GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(111347), // Rule ID 4268 //
37829 /* 111220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37830 /* 111223 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37831 /* 111227 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37832 /* 111231 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
37833 /* 111235 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
37834 /* 111239 */ // MIs[1] Operand 1
37835 /* 111239 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
37836 /* 111244 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37837 /* 111246 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37838 /* 111246 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37839 /* 111249 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
37840 /* 111253 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37841 /* 111258 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37842 /* 111262 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37843 /* 111266 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37844 /* 111268 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37845 /* 111271 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37846 /* 111275 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37847 /* 111280 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37848 /* 111283 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37849 /* 111285 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37850 /* 111288 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37851 /* 111292 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37852 /* 111297 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37853 /* 111300 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37854 /* 111302 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37855 /* 111305 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37856 /* 111309 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37857 /* 111314 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
37858 /* 111321 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37859 /* 111326 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37860 /* 111331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37861 /* 111334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37862 /* 111336 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37863 /* 111339 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37864 /* 111342 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37865 /* 111345 */ GIR_RootConstrainSelectedInstOperands,
37866 /* 111346 */ // GIR_Coverage, 4268,
37867 /* 111346 */ GIR_EraseRootFromParent_Done,
37868 /* 111347 */ // Label 1645: @111347
37869 /* 111347 */ GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(111479), // Rule ID 4300 //
37870 /* 111352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37871 /* 111355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37872 /* 111359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37873 /* 111363 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
37874 /* 111367 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
37875 /* 111371 */ // MIs[1] Operand 1
37876 /* 111371 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
37877 /* 111376 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37878 /* 111378 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37879 /* 111378 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37880 /* 111381 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
37881 /* 111385 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37882 /* 111390 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37883 /* 111394 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37884 /* 111398 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37885 /* 111400 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37886 /* 111403 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37887 /* 111407 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37888 /* 111412 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37889 /* 111415 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37890 /* 111417 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37891 /* 111420 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37892 /* 111424 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37893 /* 111429 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37894 /* 111432 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37895 /* 111434 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37896 /* 111437 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37897 /* 111441 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37898 /* 111446 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
37899 /* 111453 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37900 /* 111458 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37901 /* 111463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37902 /* 111466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37903 /* 111468 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37904 /* 111471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37905 /* 111474 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37906 /* 111477 */ GIR_RootConstrainSelectedInstOperands,
37907 /* 111478 */ // GIR_Coverage, 4300,
37908 /* 111478 */ GIR_EraseRootFromParent_Done,
37909 /* 111479 */ // Label 1646: @111479
37910 /* 111479 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(111611), // Rule ID 4332 //
37911 /* 111484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37912 /* 111487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37913 /* 111491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37914 /* 111495 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
37915 /* 111499 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
37916 /* 111503 */ // MIs[1] Operand 1
37917 /* 111503 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
37918 /* 111508 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37919 /* 111510 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37920 /* 111510 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37921 /* 111513 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
37922 /* 111517 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37923 /* 111522 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37924 /* 111526 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37925 /* 111530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37926 /* 111532 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37927 /* 111535 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37928 /* 111539 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37929 /* 111544 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37930 /* 111547 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37931 /* 111549 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37932 /* 111552 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37933 /* 111556 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37934 /* 111561 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37935 /* 111564 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37936 /* 111566 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37937 /* 111569 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37938 /* 111573 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37939 /* 111578 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
37940 /* 111585 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37941 /* 111590 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37942 /* 111595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37943 /* 111598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37944 /* 111600 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37945 /* 111603 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37946 /* 111606 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37947 /* 111609 */ GIR_RootConstrainSelectedInstOperands,
37948 /* 111610 */ // GIR_Coverage, 4332,
37949 /* 111610 */ GIR_EraseRootFromParent_Done,
37950 /* 111611 */ // Label 1647: @111611
37951 /* 111611 */ GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(111743), // Rule ID 4364 //
37952 /* 111616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
37953 /* 111619 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37954 /* 111623 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37955 /* 111627 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
37956 /* 111631 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
37957 /* 111635 */ // MIs[1] Operand 1
37958 /* 111635 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
37959 /* 111640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37960 /* 111642 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
37961 /* 111642 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
37962 /* 111645 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
37963 /* 111649 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37964 /* 111654 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
37965 /* 111658 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
37966 /* 111662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37967 /* 111664 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
37968 /* 111667 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
37969 /* 111671 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37970 /* 111676 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
37971 /* 111679 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
37972 /* 111681 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
37973 /* 111684 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
37974 /* 111688 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37975 /* 111693 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
37976 /* 111696 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
37977 /* 111698 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
37978 /* 111701 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37979 /* 111705 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37980 /* 111710 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
37981 /* 111717 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
37982 /* 111722 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
37983 /* 111727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
37984 /* 111730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37985 /* 111732 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37986 /* 111735 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
37987 /* 111738 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
37988 /* 111741 */ GIR_RootConstrainSelectedInstOperands,
37989 /* 111742 */ // GIR_Coverage, 4364,
37990 /* 111742 */ GIR_EraseRootFromParent_Done,
37991 /* 111743 */ // Label 1648: @111743
37992 /* 111743 */ GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(111875), // Rule ID 4595 //
37993 /* 111748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
37994 /* 111751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37995 /* 111755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
37996 /* 111759 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37997 /* 111763 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
37998 /* 111767 */ // MIs[1] Operand 1
37999 /* 111767 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
38000 /* 111772 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38001 /* 111774 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38002 /* 111774 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38003 /* 111777 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
38004 /* 111781 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38005 /* 111786 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38006 /* 111790 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38007 /* 111794 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38008 /* 111796 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38009 /* 111799 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38010 /* 111803 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38011 /* 111808 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38012 /* 111811 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38013 /* 111813 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38014 /* 111816 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38015 /* 111820 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38016 /* 111825 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38017 /* 111828 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38018 /* 111830 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38019 /* 111833 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38020 /* 111837 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38021 /* 111842 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38022 /* 111849 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38023 /* 111854 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38024 /* 111859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38025 /* 111862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38026 /* 111864 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38027 /* 111867 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38028 /* 111870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38029 /* 111873 */ GIR_RootConstrainSelectedInstOperands,
38030 /* 111874 */ // GIR_Coverage, 4595,
38031 /* 111874 */ GIR_EraseRootFromParent_Done,
38032 /* 111875 */ // Label 1649: @111875
38033 /* 111875 */ GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(112007), // Rule ID 4627 //
38034 /* 111880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
38035 /* 111883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38036 /* 111887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
38037 /* 111891 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38038 /* 111895 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38039 /* 111899 */ // MIs[1] Operand 1
38040 /* 111899 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
38041 /* 111904 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38042 /* 111906 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38043 /* 111906 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38044 /* 111909 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
38045 /* 111913 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38046 /* 111918 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38047 /* 111922 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38048 /* 111926 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38049 /* 111928 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38050 /* 111931 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38051 /* 111935 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38052 /* 111940 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38053 /* 111943 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38054 /* 111945 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38055 /* 111948 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38056 /* 111952 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38057 /* 111957 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38058 /* 111960 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38059 /* 111962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38060 /* 111965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38061 /* 111969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38062 /* 111974 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38063 /* 111981 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38064 /* 111986 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38065 /* 111991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38066 /* 111994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38067 /* 111996 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38068 /* 111999 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38069 /* 112002 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38070 /* 112005 */ GIR_RootConstrainSelectedInstOperands,
38071 /* 112006 */ // GIR_Coverage, 4627,
38072 /* 112006 */ GIR_EraseRootFromParent_Done,
38073 /* 112007 */ // Label 1650: @112007
38074 /* 112007 */ GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(112139), // Rule ID 4659 //
38075 /* 112012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
38076 /* 112015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38077 /* 112019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
38078 /* 112023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38079 /* 112027 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38080 /* 112031 */ // MIs[1] Operand 1
38081 /* 112031 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
38082 /* 112036 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38083 /* 112038 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38084 /* 112038 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38085 /* 112041 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
38086 /* 112045 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38087 /* 112050 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38088 /* 112054 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38089 /* 112058 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38090 /* 112060 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38091 /* 112063 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38092 /* 112067 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38093 /* 112072 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38094 /* 112075 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38095 /* 112077 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38096 /* 112080 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38097 /* 112084 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38098 /* 112089 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38099 /* 112092 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38100 /* 112094 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38101 /* 112097 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38102 /* 112101 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38103 /* 112106 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38104 /* 112113 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38105 /* 112118 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38106 /* 112123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38107 /* 112126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38108 /* 112128 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38109 /* 112131 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38110 /* 112134 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38111 /* 112137 */ GIR_RootConstrainSelectedInstOperands,
38112 /* 112138 */ // GIR_Coverage, 4659,
38113 /* 112138 */ GIR_EraseRootFromParent_Done,
38114 /* 112139 */ // Label 1651: @112139
38115 /* 112139 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(112271), // Rule ID 4703 //
38116 /* 112144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
38117 /* 112147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38118 /* 112151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
38119 /* 112155 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38120 /* 112159 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38121 /* 112163 */ // MIs[1] Operand 1
38122 /* 112163 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
38123 /* 112168 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38124 /* 112170 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38125 /* 112170 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38126 /* 112173 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
38127 /* 112177 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38128 /* 112182 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38129 /* 112186 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38130 /* 112190 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38131 /* 112192 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38132 /* 112195 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38133 /* 112199 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38134 /* 112204 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38135 /* 112207 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38136 /* 112209 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38137 /* 112212 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38138 /* 112216 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38139 /* 112221 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38140 /* 112224 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38141 /* 112226 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38142 /* 112229 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38143 /* 112233 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38144 /* 112238 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38145 /* 112245 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38146 /* 112250 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38147 /* 112255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38148 /* 112258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38149 /* 112260 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38150 /* 112263 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38151 /* 112266 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38152 /* 112269 */ GIR_RootConstrainSelectedInstOperands,
38153 /* 112270 */ // GIR_Coverage, 4703,
38154 /* 112270 */ GIR_EraseRootFromParent_Done,
38155 /* 112271 */ // Label 1652: @112271
38156 /* 112271 */ GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(112403), // Rule ID 4735 //
38157 /* 112276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
38158 /* 112279 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38159 /* 112283 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
38160 /* 112287 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38161 /* 112291 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38162 /* 112295 */ // MIs[1] Operand 1
38163 /* 112295 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
38164 /* 112300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38165 /* 112302 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38166 /* 112302 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38167 /* 112305 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
38168 /* 112309 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38169 /* 112314 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38170 /* 112318 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38171 /* 112322 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38172 /* 112324 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38173 /* 112327 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38174 /* 112331 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38175 /* 112336 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38176 /* 112339 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38177 /* 112341 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38178 /* 112344 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38179 /* 112348 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38180 /* 112353 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38181 /* 112356 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38182 /* 112358 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38183 /* 112361 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38184 /* 112365 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38185 /* 112370 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38186 /* 112377 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38187 /* 112382 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38188 /* 112387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38189 /* 112390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38190 /* 112392 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38191 /* 112395 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38192 /* 112398 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38193 /* 112401 */ GIR_RootConstrainSelectedInstOperands,
38194 /* 112402 */ // GIR_Coverage, 4735,
38195 /* 112402 */ GIR_EraseRootFromParent_Done,
38196 /* 112403 */ // Label 1653: @112403
38197 /* 112403 */ GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(112535), // Rule ID 4767 //
38198 /* 112408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
38199 /* 112411 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38200 /* 112415 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
38201 /* 112419 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38202 /* 112423 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38203 /* 112427 */ // MIs[1] Operand 1
38204 /* 112427 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
38205 /* 112432 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38206 /* 112434 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38207 /* 112434 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38208 /* 112437 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
38209 /* 112441 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38210 /* 112446 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38211 /* 112450 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38212 /* 112454 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38213 /* 112456 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38214 /* 112459 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38215 /* 112463 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38216 /* 112468 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38217 /* 112471 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38218 /* 112473 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38219 /* 112476 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38220 /* 112480 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38221 /* 112485 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38222 /* 112488 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38223 /* 112490 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38224 /* 112493 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38225 /* 112497 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38226 /* 112502 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38227 /* 112509 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38228 /* 112514 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38229 /* 112519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38230 /* 112522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38231 /* 112524 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38232 /* 112527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38233 /* 112530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38234 /* 112533 */ GIR_RootConstrainSelectedInstOperands,
38235 /* 112534 */ // GIR_Coverage, 4767,
38236 /* 112534 */ GIR_EraseRootFromParent_Done,
38237 /* 112535 */ // Label 1654: @112535
38238 /* 112535 */ GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(112627), // Rule ID 2987 //
38239 /* 112540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38240 /* 112543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38241 /* 112547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38242 /* 112551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38243 /* 112555 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38244 /* 112559 */ // MIs[1] Operand 1
38245 /* 112559 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
38246 /* 112564 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38247 /* 112566 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
38248 /* 112566 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38249 /* 112569 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
38250 /* 112573 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38251 /* 112578 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38252 /* 112582 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38253 /* 112586 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38254 /* 112588 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38255 /* 112591 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38256 /* 112595 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38257 /* 112600 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
38258 /* 112607 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38259 /* 112612 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38260 /* 112617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38261 /* 112620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38262 /* 112622 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38263 /* 112625 */ GIR_RootConstrainSelectedInstOperands,
38264 /* 112626 */ // GIR_Coverage, 2987,
38265 /* 112626 */ GIR_EraseRootFromParent_Done,
38266 /* 112627 */ // Label 1655: @112627
38267 /* 112627 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(112719), // Rule ID 3001 //
38268 /* 112632 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38269 /* 112635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38270 /* 112639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38271 /* 112643 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38272 /* 112647 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38273 /* 112651 */ // MIs[1] Operand 1
38274 /* 112651 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
38275 /* 112656 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38276 /* 112658 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
38277 /* 112658 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38278 /* 112661 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
38279 /* 112665 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38280 /* 112670 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38281 /* 112674 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38282 /* 112678 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38283 /* 112680 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38284 /* 112683 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38285 /* 112687 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38286 /* 112692 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
38287 /* 112699 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38288 /* 112704 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38289 /* 112709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38290 /* 112712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38291 /* 112714 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38292 /* 112717 */ GIR_RootConstrainSelectedInstOperands,
38293 /* 112718 */ // GIR_Coverage, 3001,
38294 /* 112718 */ GIR_EraseRootFromParent_Done,
38295 /* 112719 */ // Label 1656: @112719
38296 /* 112719 */ GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(112811), // Rule ID 3009 //
38297 /* 112724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38298 /* 112727 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38299 /* 112731 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38300 /* 112735 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38301 /* 112739 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38302 /* 112743 */ // MIs[1] Operand 1
38303 /* 112743 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
38304 /* 112748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38305 /* 112750 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
38306 /* 112750 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38307 /* 112753 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
38308 /* 112757 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38309 /* 112762 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38310 /* 112766 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38311 /* 112770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38312 /* 112772 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38313 /* 112775 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38314 /* 112779 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38315 /* 112784 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38316 /* 112791 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38317 /* 112796 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38318 /* 112801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38319 /* 112804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38320 /* 112806 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38321 /* 112809 */ GIR_RootConstrainSelectedInstOperands,
38322 /* 112810 */ // GIR_Coverage, 3009,
38323 /* 112810 */ GIR_EraseRootFromParent_Done,
38324 /* 112811 */ // Label 1657: @112811
38325 /* 112811 */ GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(112903), // Rule ID 3017 //
38326 /* 112816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38327 /* 112819 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38328 /* 112823 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38329 /* 112827 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38330 /* 112831 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38331 /* 112835 */ // MIs[1] Operand 1
38332 /* 112835 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
38333 /* 112840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38334 /* 112842 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
38335 /* 112842 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38336 /* 112845 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
38337 /* 112849 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38338 /* 112854 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38339 /* 112858 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38340 /* 112862 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38341 /* 112864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38342 /* 112867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38343 /* 112871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38344 /* 112876 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38345 /* 112883 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38346 /* 112888 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38347 /* 112893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38348 /* 112896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38349 /* 112898 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38350 /* 112901 */ GIR_RootConstrainSelectedInstOperands,
38351 /* 112902 */ // GIR_Coverage, 3017,
38352 /* 112902 */ GIR_EraseRootFromParent_Done,
38353 /* 112903 */ // Label 1658: @112903
38354 /* 112903 */ GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(112995), // Rule ID 3025 //
38355 /* 112908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38356 /* 112911 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38357 /* 112915 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38358 /* 112919 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38359 /* 112923 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38360 /* 112927 */ // MIs[1] Operand 1
38361 /* 112927 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
38362 /* 112932 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38363 /* 112934 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }))
38364 /* 112934 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38365 /* 112937 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
38366 /* 112941 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38367 /* 112946 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38368 /* 112950 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38369 /* 112954 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38370 /* 112956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38371 /* 112959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38372 /* 112963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38373 /* 112968 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
38374 /* 112975 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38375 /* 112980 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38376 /* 112985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38377 /* 112988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38378 /* 112990 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38379 /* 112993 */ GIR_RootConstrainSelectedInstOperands,
38380 /* 112994 */ // GIR_Coverage, 3025,
38381 /* 112994 */ GIR_EraseRootFromParent_Done,
38382 /* 112995 */ // Label 1659: @112995
38383 /* 112995 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(113087), // Rule ID 3089 //
38384 /* 113000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38385 /* 113003 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38386 /* 113007 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38387 /* 113011 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38388 /* 113015 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38389 /* 113019 */ // MIs[1] Operand 1
38390 /* 113019 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
38391 /* 113024 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38392 /* 113026 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
38393 /* 113026 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38394 /* 113029 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
38395 /* 113033 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38396 /* 113038 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38397 /* 113042 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38398 /* 113046 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38399 /* 113048 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38400 /* 113051 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38401 /* 113055 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38402 /* 113060 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
38403 /* 113067 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38404 /* 113072 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38405 /* 113077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38406 /* 113080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38407 /* 113082 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38408 /* 113085 */ GIR_RootConstrainSelectedInstOperands,
38409 /* 113086 */ // GIR_Coverage, 3089,
38410 /* 113086 */ GIR_EraseRootFromParent_Done,
38411 /* 113087 */ // Label 1660: @113087
38412 /* 113087 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(113179), // Rule ID 3097 //
38413 /* 113092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38414 /* 113095 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38415 /* 113099 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38416 /* 113103 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38417 /* 113107 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38418 /* 113111 */ // MIs[1] Operand 1
38419 /* 113111 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
38420 /* 113116 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38421 /* 113118 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
38422 /* 113118 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38423 /* 113121 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
38424 /* 113125 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38425 /* 113130 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38426 /* 113134 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38427 /* 113138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38428 /* 113140 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38429 /* 113143 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38430 /* 113147 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38431 /* 113152 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
38432 /* 113159 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38433 /* 113164 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38434 /* 113169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38435 /* 113172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38436 /* 113174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38437 /* 113177 */ GIR_RootConstrainSelectedInstOperands,
38438 /* 113178 */ // GIR_Coverage, 3097,
38439 /* 113178 */ GIR_EraseRootFromParent_Done,
38440 /* 113179 */ // Label 1661: @113179
38441 /* 113179 */ GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(113271), // Rule ID 3105 //
38442 /* 113184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38443 /* 113187 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38444 /* 113191 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38445 /* 113195 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38446 /* 113199 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38447 /* 113203 */ // MIs[1] Operand 1
38448 /* 113203 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
38449 /* 113208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38450 /* 113210 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
38451 /* 113210 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38452 /* 113213 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
38453 /* 113217 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38454 /* 113222 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38455 /* 113226 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38456 /* 113230 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38457 /* 113232 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38458 /* 113235 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38459 /* 113239 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38460 /* 113244 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38461 /* 113251 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38462 /* 113256 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38463 /* 113261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38464 /* 113264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38465 /* 113266 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38466 /* 113269 */ GIR_RootConstrainSelectedInstOperands,
38467 /* 113270 */ // GIR_Coverage, 3105,
38468 /* 113270 */ GIR_EraseRootFromParent_Done,
38469 /* 113271 */ // Label 1662: @113271
38470 /* 113271 */ GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(113363), // Rule ID 3113 //
38471 /* 113276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38472 /* 113279 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38473 /* 113283 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38474 /* 113287 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38475 /* 113291 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38476 /* 113295 */ // MIs[1] Operand 1
38477 /* 113295 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
38478 /* 113300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38479 /* 113302 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
38480 /* 113302 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38481 /* 113305 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
38482 /* 113309 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38483 /* 113314 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38484 /* 113318 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38485 /* 113322 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38486 /* 113324 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38487 /* 113327 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38488 /* 113331 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38489 /* 113336 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38490 /* 113343 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38491 /* 113348 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38492 /* 113353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38493 /* 113356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38494 /* 113358 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38495 /* 113361 */ GIR_RootConstrainSelectedInstOperands,
38496 /* 113362 */ // GIR_Coverage, 3113,
38497 /* 113362 */ GIR_EraseRootFromParent_Done,
38498 /* 113363 */ // Label 1663: @113363
38499 /* 113363 */ GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(113455), // Rule ID 3121 //
38500 /* 113368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38501 /* 113371 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38502 /* 113375 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38503 /* 113379 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38504 /* 113383 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38505 /* 113387 */ // MIs[1] Operand 1
38506 /* 113387 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
38507 /* 113392 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38508 /* 113394 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }))
38509 /* 113394 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38510 /* 113397 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
38511 /* 113401 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38512 /* 113406 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38513 /* 113410 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38514 /* 113414 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38515 /* 113416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38516 /* 113419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38517 /* 113423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38518 /* 113428 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
38519 /* 113435 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38520 /* 113440 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38521 /* 113445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
38522 /* 113448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
38523 /* 113450 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38524 /* 113453 */ GIR_RootConstrainSelectedInstOperands,
38525 /* 113454 */ // GIR_Coverage, 3121,
38526 /* 113454 */ GIR_EraseRootFromParent_Done,
38527 /* 113455 */ // Label 1664: @113455
38528 /* 113455 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(113587), // Rule ID 3872 //
38529 /* 113460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38530 /* 113463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38531 /* 113467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38532 /* 113471 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38533 /* 113475 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38534 /* 113479 */ // MIs[1] Operand 1
38535 /* 113479 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
38536 /* 113484 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38537 /* 113486 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38538 /* 113486 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38539 /* 113489 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
38540 /* 113493 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38541 /* 113498 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38542 /* 113502 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38543 /* 113506 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38544 /* 113508 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38545 /* 113511 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38546 /* 113515 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38547 /* 113520 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38548 /* 113523 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38549 /* 113525 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38550 /* 113528 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38551 /* 113532 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38552 /* 113537 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38553 /* 113540 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38554 /* 113542 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38555 /* 113545 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38556 /* 113549 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38557 /* 113554 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
38558 /* 113561 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38559 /* 113566 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38560 /* 113571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38561 /* 113574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38562 /* 113576 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38563 /* 113579 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38564 /* 113582 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38565 /* 113585 */ GIR_RootConstrainSelectedInstOperands,
38566 /* 113586 */ // GIR_Coverage, 3872,
38567 /* 113586 */ GIR_EraseRootFromParent_Done,
38568 /* 113587 */ // Label 1665: @113587
38569 /* 113587 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(113719), // Rule ID 3880 //
38570 /* 113592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38571 /* 113595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38572 /* 113599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38573 /* 113603 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38574 /* 113607 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38575 /* 113611 */ // MIs[1] Operand 1
38576 /* 113611 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
38577 /* 113616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38578 /* 113618 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38579 /* 113618 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38580 /* 113621 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
38581 /* 113625 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38582 /* 113630 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38583 /* 113634 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38584 /* 113638 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38585 /* 113640 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38586 /* 113643 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38587 /* 113647 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38588 /* 113652 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38589 /* 113655 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38590 /* 113657 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38591 /* 113660 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38592 /* 113664 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38593 /* 113669 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38594 /* 113672 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38595 /* 113674 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38596 /* 113677 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38597 /* 113681 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38598 /* 113686 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
38599 /* 113693 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38600 /* 113698 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38601 /* 113703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38602 /* 113706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38603 /* 113708 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38604 /* 113711 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38605 /* 113714 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38606 /* 113717 */ GIR_RootConstrainSelectedInstOperands,
38607 /* 113718 */ // GIR_Coverage, 3880,
38608 /* 113718 */ GIR_EraseRootFromParent_Done,
38609 /* 113719 */ // Label 1666: @113719
38610 /* 113719 */ GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(113851), // Rule ID 3888 //
38611 /* 113724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38612 /* 113727 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38613 /* 113731 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38614 /* 113735 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38615 /* 113739 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38616 /* 113743 */ // MIs[1] Operand 1
38617 /* 113743 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
38618 /* 113748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38619 /* 113750 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38620 /* 113750 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38621 /* 113753 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
38622 /* 113757 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38623 /* 113762 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38624 /* 113766 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38625 /* 113770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38626 /* 113772 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38627 /* 113775 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38628 /* 113779 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38629 /* 113784 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38630 /* 113787 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38631 /* 113789 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38632 /* 113792 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38633 /* 113796 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38634 /* 113801 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38635 /* 113804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38636 /* 113806 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38637 /* 113809 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38638 /* 113813 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38639 /* 113818 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38640 /* 113825 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38641 /* 113830 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38642 /* 113835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38643 /* 113838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38644 /* 113840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38645 /* 113843 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38646 /* 113846 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38647 /* 113849 */ GIR_RootConstrainSelectedInstOperands,
38648 /* 113850 */ // GIR_Coverage, 3888,
38649 /* 113850 */ GIR_EraseRootFromParent_Done,
38650 /* 113851 */ // Label 1667: @113851
38651 /* 113851 */ GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(113983), // Rule ID 3896 //
38652 /* 113856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38653 /* 113859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38654 /* 113863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38655 /* 113867 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38656 /* 113871 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38657 /* 113875 */ // MIs[1] Operand 1
38658 /* 113875 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
38659 /* 113880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38660 /* 113882 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38661 /* 113882 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38662 /* 113885 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
38663 /* 113889 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38664 /* 113894 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38665 /* 113898 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38666 /* 113902 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38667 /* 113904 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38668 /* 113907 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38669 /* 113911 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38670 /* 113916 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38671 /* 113919 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38672 /* 113921 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38673 /* 113924 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38674 /* 113928 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38675 /* 113933 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38676 /* 113936 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38677 /* 113938 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38678 /* 113941 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38679 /* 113945 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38680 /* 113950 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38681 /* 113957 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38682 /* 113962 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38683 /* 113967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38684 /* 113970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38685 /* 113972 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38686 /* 113975 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38687 /* 113978 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38688 /* 113981 */ GIR_RootConstrainSelectedInstOperands,
38689 /* 113982 */ // GIR_Coverage, 3896,
38690 /* 113982 */ GIR_EraseRootFromParent_Done,
38691 /* 113983 */ // Label 1668: @113983
38692 /* 113983 */ GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(114115), // Rule ID 3904 //
38693 /* 113988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38694 /* 113991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38695 /* 113995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38696 /* 113999 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38697 /* 114003 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
38698 /* 114007 */ // MIs[1] Operand 1
38699 /* 114007 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
38700 /* 114012 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38701 /* 114014 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38702 /* 114014 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38703 /* 114017 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
38704 /* 114021 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38705 /* 114026 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38706 /* 114030 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38707 /* 114034 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38708 /* 114036 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38709 /* 114039 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38710 /* 114043 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38711 /* 114048 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38712 /* 114051 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38713 /* 114053 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38714 /* 114056 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38715 /* 114060 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38716 /* 114065 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38717 /* 114068 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38718 /* 114070 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38719 /* 114073 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38720 /* 114077 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38721 /* 114082 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
38722 /* 114089 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38723 /* 114094 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38724 /* 114099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38725 /* 114102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38726 /* 114104 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38727 /* 114107 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38728 /* 114110 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38729 /* 114113 */ GIR_RootConstrainSelectedInstOperands,
38730 /* 114114 */ // GIR_Coverage, 3904,
38731 /* 114114 */ GIR_EraseRootFromParent_Done,
38732 /* 114115 */ // Label 1669: @114115
38733 /* 114115 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(114247), // Rule ID 3968 //
38734 /* 114120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38735 /* 114123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38736 /* 114127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38737 /* 114131 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38738 /* 114135 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38739 /* 114139 */ // MIs[1] Operand 1
38740 /* 114139 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
38741 /* 114144 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38742 /* 114146 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38743 /* 114146 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38744 /* 114149 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
38745 /* 114153 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38746 /* 114158 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38747 /* 114162 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38748 /* 114166 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38749 /* 114168 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38750 /* 114171 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38751 /* 114175 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38752 /* 114180 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38753 /* 114183 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38754 /* 114185 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38755 /* 114188 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38756 /* 114192 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38757 /* 114197 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38758 /* 114200 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38759 /* 114202 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38760 /* 114205 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38761 /* 114209 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38762 /* 114214 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
38763 /* 114221 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38764 /* 114226 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38765 /* 114231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38766 /* 114234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38767 /* 114236 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38768 /* 114239 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38769 /* 114242 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38770 /* 114245 */ GIR_RootConstrainSelectedInstOperands,
38771 /* 114246 */ // GIR_Coverage, 3968,
38772 /* 114246 */ GIR_EraseRootFromParent_Done,
38773 /* 114247 */ // Label 1670: @114247
38774 /* 114247 */ GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(114379), // Rule ID 3976 //
38775 /* 114252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38776 /* 114255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38777 /* 114259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38778 /* 114263 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38779 /* 114267 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38780 /* 114271 */ // MIs[1] Operand 1
38781 /* 114271 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
38782 /* 114276 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38783 /* 114278 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38784 /* 114278 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38785 /* 114281 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
38786 /* 114285 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38787 /* 114290 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38788 /* 114294 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38789 /* 114298 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38790 /* 114300 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38791 /* 114303 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38792 /* 114307 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38793 /* 114312 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38794 /* 114315 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38795 /* 114317 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38796 /* 114320 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38797 /* 114324 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38798 /* 114329 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38799 /* 114332 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38800 /* 114334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38801 /* 114337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38802 /* 114341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38803 /* 114346 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
38804 /* 114353 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38805 /* 114358 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38806 /* 114363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38807 /* 114366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38808 /* 114368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38809 /* 114371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38810 /* 114374 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38811 /* 114377 */ GIR_RootConstrainSelectedInstOperands,
38812 /* 114378 */ // GIR_Coverage, 3976,
38813 /* 114378 */ GIR_EraseRootFromParent_Done,
38814 /* 114379 */ // Label 1671: @114379
38815 /* 114379 */ GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(114511), // Rule ID 3984 //
38816 /* 114384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38817 /* 114387 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38818 /* 114391 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38819 /* 114395 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38820 /* 114399 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38821 /* 114403 */ // MIs[1] Operand 1
38822 /* 114403 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
38823 /* 114408 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38824 /* 114410 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38825 /* 114410 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38826 /* 114413 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
38827 /* 114417 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38828 /* 114422 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38829 /* 114426 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38830 /* 114430 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38831 /* 114432 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38832 /* 114435 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38833 /* 114439 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38834 /* 114444 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38835 /* 114447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38836 /* 114449 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38837 /* 114452 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38838 /* 114456 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38839 /* 114461 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38840 /* 114464 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38841 /* 114466 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38842 /* 114469 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38843 /* 114473 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38844 /* 114478 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38845 /* 114485 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38846 /* 114490 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38847 /* 114495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38848 /* 114498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38849 /* 114500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38850 /* 114503 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38851 /* 114506 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38852 /* 114509 */ GIR_RootConstrainSelectedInstOperands,
38853 /* 114510 */ // GIR_Coverage, 3984,
38854 /* 114510 */ GIR_EraseRootFromParent_Done,
38855 /* 114511 */ // Label 1672: @114511
38856 /* 114511 */ GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(114643), // Rule ID 3992 //
38857 /* 114516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38858 /* 114519 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38859 /* 114523 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38860 /* 114527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38861 /* 114531 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38862 /* 114535 */ // MIs[1] Operand 1
38863 /* 114535 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
38864 /* 114540 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38865 /* 114542 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38866 /* 114542 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38867 /* 114545 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
38868 /* 114549 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38869 /* 114554 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38870 /* 114558 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38871 /* 114562 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38872 /* 114564 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38873 /* 114567 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38874 /* 114571 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38875 /* 114576 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38876 /* 114579 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38877 /* 114581 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38878 /* 114584 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38879 /* 114588 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38880 /* 114593 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38881 /* 114596 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38882 /* 114598 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38883 /* 114601 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38884 /* 114605 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38885 /* 114610 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
38886 /* 114617 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38887 /* 114622 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38888 /* 114627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38889 /* 114630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38890 /* 114632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38891 /* 114635 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38892 /* 114638 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38893 /* 114641 */ GIR_RootConstrainSelectedInstOperands,
38894 /* 114642 */ // GIR_Coverage, 3992,
38895 /* 114642 */ GIR_EraseRootFromParent_Done,
38896 /* 114643 */ // Label 1673: @114643
38897 /* 114643 */ GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(114775), // Rule ID 4000 //
38898 /* 114648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
38899 /* 114651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38900 /* 114655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
38901 /* 114659 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
38902 /* 114663 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
38903 /* 114667 */ // MIs[1] Operand 1
38904 /* 114667 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
38905 /* 114672 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38906 /* 114674 */ // (anyext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
38907 /* 114674 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
38908 /* 114677 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
38909 /* 114681 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38910 /* 114686 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
38911 /* 114690 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
38912 /* 114694 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38913 /* 114696 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
38914 /* 114699 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
38915 /* 114703 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38916 /* 114708 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
38917 /* 114711 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
38918 /* 114713 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
38919 /* 114716 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
38920 /* 114720 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38921 /* 114725 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
38922 /* 114728 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
38923 /* 114730 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
38924 /* 114733 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38925 /* 114737 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38926 /* 114742 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
38927 /* 114749 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
38928 /* 114754 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
38929 /* 114759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38930 /* 114762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38931 /* 114764 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38932 /* 114767 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38933 /* 114770 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
38934 /* 114773 */ GIR_RootConstrainSelectedInstOperands,
38935 /* 114774 */ // GIR_Coverage, 4000,
38936 /* 114774 */ GIR_EraseRootFromParent_Done,
38937 /* 114775 */ // Label 1674: @114775
38938 /* 114775 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(114790), // Rule ID 2993 //
38939 /* 114780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
38940 /* 114783 */ // (anyext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SETBC8:{ *:[i64] } ?:{ *:[i1] }:$in)
38941 /* 114783 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETBC8),
38942 /* 114788 */ GIR_RootConstrainSelectedInstOperands,
38943 /* 114789 */ // GIR_Coverage, 2993,
38944 /* 114789 */ GIR_Done,
38945 /* 114790 */ // Label 1675: @114790
38946 /* 114790 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(114844), // Rule ID 3678 //
38947 /* 114795 */ // (anyext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SELECT_I8:{ *:[i64] } ?:{ *:[i1] }:$in, (LI8:{ *:[i64] } 1:{ *:[i64] }), (LI8:{ *:[i64] } 0:{ *:[i64] }))
38948 /* 114795 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38949 /* 114798 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI8),
38950 /* 114802 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38951 /* 114807 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
38952 /* 114810 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38953 /* 114812 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38954 /* 114815 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI8),
38955 /* 114819 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38956 /* 114824 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
38957 /* 114827 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38958 /* 114829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
38959 /* 114832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38960 /* 114834 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
38961 /* 114836 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38962 /* 114839 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
38963 /* 114842 */ GIR_RootConstrainSelectedInstOperands,
38964 /* 114843 */ // GIR_Coverage, 3678,
38965 /* 114843 */ GIR_EraseRootFromParent_Done,
38966 /* 114844 */ // Label 1676: @114844
38967 /* 114844 */ GIM_Reject,
38968 /* 114845 */ // Label 1584: @114845
38969 /* 114845 */ GIM_Reject,
38970 /* 114846 */ // Label 1490: @114846
38971 /* 114846 */ GIM_Reject,
38972 /* 114847 */ // Label 22: @114847
38973 /* 114847 */ GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(115032),
38974 /* 114852 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
38975 /* 114855 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1680*/ GIMT_Encode4(114966),
38976 /* 114866 */ /*GILLT_s32*//*Label 1678*/ GIMT_Encode4(114874),
38977 /* 114870 */ /*GILLT_s64*//*Label 1679*/ GIMT_Encode4(114920),
38978 /* 114874 */ // Label 1678: @114874
38979 /* 114874 */ GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(114919), // Rule ID 1174 //
38980 /* 114879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
38981 /* 114883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38982 /* 114887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
38983 /* 114891 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38984 /* 114895 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38985 /* 114899 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
38986 /* 114903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38987 /* 114905 */ // (trunc:{ *:[i1] } (xor:{ *:[i32] } i32:{ *:[i32] }:$in, -1:{ *:[i32] })) => (ANDI_rec_1_EQ_BIT:{ *:[i1] }:{ *:[i32] } i32:{ *:[i32] }:$in)
38988 /* 114905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_EQ_BIT),
38989 /* 114908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38990 /* 114910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // in
38991 /* 114914 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
38992 /* 114917 */ GIR_RootConstrainSelectedInstOperands,
38993 /* 114918 */ // GIR_Coverage, 1174,
38994 /* 114918 */ GIR_EraseRootFromParent_Done,
38995 /* 114919 */ // Label 1681: @114919
38996 /* 114919 */ GIM_Reject,
38997 /* 114920 */ // Label 1679: @114920
38998 /* 114920 */ GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(114965), // Rule ID 1176 //
38999 /* 114925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
39000 /* 114929 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39001 /* 114933 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
39002 /* 114937 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39003 /* 114941 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39004 /* 114945 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
39005 /* 114949 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39006 /* 114951 */ // (trunc:{ *:[i1] } (xor:{ *:[i64] } i64:{ *:[i64] }:$in, -1:{ *:[i64] })) => (ANDI_rec_1_EQ_BIT8:{ *:[i1] }:{ *:[i32] } i64:{ *:[i64] }:$in)
39007 /* 114951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_EQ_BIT8),
39008 /* 114954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39009 /* 114956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // in
39010 /* 114960 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0,
39011 /* 114963 */ GIR_RootConstrainSelectedInstOperands,
39012 /* 114964 */ // GIR_Coverage, 1176,
39013 /* 114964 */ GIR_EraseRootFromParent_Done,
39014 /* 114965 */ // Label 1682: @114965
39015 /* 114965 */ GIM_Reject,
39016 /* 114966 */ // Label 1680: @114966
39017 /* 114966 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1685*/ GIMT_Encode4(115031),
39018 /* 114977 */ /*GILLT_s32*//*Label 1683*/ GIMT_Encode4(114985),
39019 /* 114981 */ /*GILLT_s64*//*Label 1684*/ GIMT_Encode4(115008),
39020 /* 114985 */ // Label 1683: @114985
39021 /* 114985 */ GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(115007), // Rule ID 1175 //
39022 /* 114990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
39023 /* 114994 */ // (trunc:{ *:[i1] } i32:{ *:[i32] }:$in) => (ANDI_rec_1_GT_BIT:{ *:[i1] }:{ *:[i32] } i32:{ *:[i32] }:$in)
39024 /* 114994 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_GT_BIT),
39025 /* 114999 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(PPC::CR0), GIMT_Encode2(RegState::Dead),
39026 /* 115005 */ GIR_RootConstrainSelectedInstOperands,
39027 /* 115006 */ // GIR_Coverage, 1175,
39028 /* 115006 */ GIR_Done,
39029 /* 115007 */ // Label 1686: @115007
39030 /* 115007 */ GIM_Reject,
39031 /* 115008 */ // Label 1684: @115008
39032 /* 115008 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(115030), // Rule ID 1177 //
39033 /* 115013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
39034 /* 115017 */ // (trunc:{ *:[i1] } i64:{ *:[i64] }:$in) => (ANDI_rec_1_GT_BIT8:{ *:[i1] }:{ *:[i32] } i64:{ *:[i64] }:$in)
39035 /* 115017 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_GT_BIT8),
39036 /* 115022 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(PPC::CR0), GIMT_Encode2(RegState::Dead),
39037 /* 115028 */ GIR_RootConstrainSelectedInstOperands,
39038 /* 115029 */ // GIR_Coverage, 1177,
39039 /* 115029 */ GIR_Done,
39040 /* 115030 */ // Label 1687: @115030
39041 /* 115030 */ GIM_Reject,
39042 /* 115031 */ // Label 1685: @115031
39043 /* 115031 */ GIM_Reject,
39044 /* 115032 */ // Label 1677: @115032
39045 /* 115032 */ GIM_Reject,
39046 /* 115033 */ // Label 23: @115033
39047 /* 115033 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 1691*/ GIMT_Encode4(115184),
39048 /* 115044 */ /*GILLT_s1*//*Label 1688*/ GIMT_Encode4(115056),
39049 /* 115048 */ /*GILLT_s32*//*Label 1689*/ GIMT_Encode4(115136),
39050 /* 115052 */ /*GILLT_s64*//*Label 1690*/ GIMT_Encode4(115160),
39051 /* 115056 */ // Label 1688: @115056
39052 /* 115056 */ GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(115135),
39053 /* 115061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
39054 /* 115065 */ GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(115088), // Rule ID 184 //
39055 /* 115070 */ // MIs[0] Operand 1
39056 /* 115070 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(1),
39057 /* 115081 */ // 1:{ *:[i1] } => (CRSET:{ *:[i1] })
39058 /* 115081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRSET),
39059 /* 115084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
39060 /* 115086 */ GIR_RootConstrainSelectedInstOperands,
39061 /* 115087 */ // GIR_Coverage, 184,
39062 /* 115087 */ GIR_EraseRootFromParent_Done,
39063 /* 115088 */ // Label 1693: @115088
39064 /* 115088 */ GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(115111), // Rule ID 185 //
39065 /* 115093 */ // MIs[0] Operand 1
39066 /* 115093 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0),
39067 /* 115104 */ // 0:{ *:[i1] } => (CRUNSET:{ *:[i1] })
39068 /* 115104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRUNSET),
39069 /* 115107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
39070 /* 115109 */ GIR_RootConstrainSelectedInstOperands,
39071 /* 115110 */ // GIR_Coverage, 185,
39072 /* 115110 */ GIR_EraseRootFromParent_Done,
39073 /* 115111 */ // Label 1694: @115111
39074 /* 115111 */ GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(115134), // Rule ID 3672 //
39075 /* 115116 */ // MIs[0] Operand 1
39076 /* 115116 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(-1),
39077 /* 115127 */ // -1:{ *:[i1] } => (CRSET:{ *:[i1] })
39078 /* 115127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRSET),
39079 /* 115130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
39080 /* 115132 */ GIR_RootConstrainSelectedInstOperands,
39081 /* 115133 */ // GIR_Coverage, 3672,
39082 /* 115133 */ GIR_EraseRootFromParent_Done,
39083 /* 115134 */ // Label 1695: @115134
39084 /* 115134 */ GIM_Reject,
39085 /* 115135 */ // Label 1692: @115135
39086 /* 115135 */ GIM_Reject,
39087 /* 115136 */ // Label 1689: @115136
39088 /* 115136 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(115159), // Rule ID 113 //
39089 /* 115141 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
39090 /* 115145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
39091 /* 115149 */ // MIs[0] Operand 1
39092 /* 115149 */ // No operand predicates
39093 /* 115149 */ // (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$D => (LI:{ *:[i32] } (imm:{ *:[i32] }):$D)
39094 /* 115149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::LI),
39095 /* 115152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39096 /* 115154 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // D
39097 /* 115157 */ GIR_RootConstrainSelectedInstOperands,
39098 /* 115158 */ // GIR_Coverage, 113,
39099 /* 115158 */ GIR_EraseRootFromParent_Done,
39100 /* 115159 */ // Label 1696: @115159
39101 /* 115159 */ GIM_Reject,
39102 /* 115160 */ // Label 1690: @115160
39103 /* 115160 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(115183), // Rule ID 643 //
39104 /* 115165 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
39105 /* 115169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
39106 /* 115173 */ // MIs[0] Operand 1
39107 /* 115173 */ // No operand predicates
39108 /* 115173 */ // (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$D => (LI8:{ *:[i64] } (imm:{ *:[i64] }):$D)
39109 /* 115173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::LI8),
39110 /* 115176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39111 /* 115178 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // D
39112 /* 115181 */ GIR_RootConstrainSelectedInstOperands,
39113 /* 115182 */ // GIR_Coverage, 643,
39114 /* 115182 */ GIR_EraseRootFromParent_Done,
39115 /* 115183 */ // Label 1697: @115183
39116 /* 115183 */ GIM_Reject,
39117 /* 115184 */ // Label 1691: @115184
39118 /* 115184 */ GIM_Reject,
39119 /* 115185 */ // Label 24: @115185
39120 /* 115185 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1700*/ GIMT_Encode4(130216),
39121 /* 115196 */ /*GILLT_s32*//*Label 1698*/ GIMT_Encode4(115204),
39122 /* 115200 */ /*GILLT_s64*//*Label 1699*/ GIMT_Encode4(122483),
39123 /* 115204 */ // Label 1698: @115204
39124 /* 115204 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(122482),
39125 /* 115209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
39126 /* 115212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
39127 /* 115216 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(115319), // Rule ID 3038 //
39128 /* 115221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
39129 /* 115224 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39130 /* 115228 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39131 /* 115232 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39132 /* 115236 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39133 /* 115240 */ // MIs[1] Operand 1
39134 /* 115240 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
39135 /* 115245 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39136 /* 115249 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39137 /* 115253 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
39138 /* 115257 */ // MIs[2] Operand 1
39139 /* 115257 */ // No operand predicates
39140 /* 115257 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39141 /* 115259 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }))
39142 /* 115259 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39143 /* 115262 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
39144 /* 115266 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39145 /* 115271 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39146 /* 115275 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39147 /* 115278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39148 /* 115280 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39149 /* 115283 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39150 /* 115287 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39151 /* 115292 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
39152 /* 115299 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39153 /* 115304 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39154 /* 115309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39155 /* 115312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39156 /* 115314 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39157 /* 115317 */ GIR_RootConstrainSelectedInstOperands,
39158 /* 115318 */ // GIR_Coverage, 3038,
39159 /* 115318 */ GIR_EraseRootFromParent_Done,
39160 /* 115319 */ // Label 1702: @115319
39161 /* 115319 */ GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(115422), // Rule ID 3054 //
39162 /* 115324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
39163 /* 115327 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39164 /* 115331 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39165 /* 115335 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39166 /* 115339 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39167 /* 115343 */ // MIs[1] Operand 1
39168 /* 115343 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
39169 /* 115348 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39170 /* 115352 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39171 /* 115356 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
39172 /* 115360 */ // MIs[2] Operand 1
39173 /* 115360 */ // No operand predicates
39174 /* 115360 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39175 /* 115362 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }))
39176 /* 115362 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39177 /* 115365 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
39178 /* 115369 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39179 /* 115374 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39180 /* 115378 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39181 /* 115381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39182 /* 115383 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39183 /* 115386 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39184 /* 115390 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39185 /* 115395 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
39186 /* 115402 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39187 /* 115407 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39188 /* 115412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39189 /* 115415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39190 /* 115417 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39191 /* 115420 */ GIR_RootConstrainSelectedInstOperands,
39192 /* 115421 */ // GIR_Coverage, 3054,
39193 /* 115421 */ GIR_EraseRootFromParent_Done,
39194 /* 115422 */ // Label 1703: @115422
39195 /* 115422 */ GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(115525), // Rule ID 3062 //
39196 /* 115427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
39197 /* 115430 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39198 /* 115434 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39199 /* 115438 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39200 /* 115442 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39201 /* 115446 */ // MIs[1] Operand 1
39202 /* 115446 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
39203 /* 115451 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39204 /* 115455 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39205 /* 115459 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
39206 /* 115463 */ // MIs[2] Operand 1
39207 /* 115463 */ // No operand predicates
39208 /* 115463 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39209 /* 115465 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }))
39210 /* 115465 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39211 /* 115468 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
39212 /* 115472 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39213 /* 115477 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39214 /* 115481 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39215 /* 115484 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39216 /* 115486 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39217 /* 115489 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39218 /* 115493 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39219 /* 115498 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
39220 /* 115505 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39221 /* 115510 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39222 /* 115515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39223 /* 115518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39224 /* 115520 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39225 /* 115523 */ GIR_RootConstrainSelectedInstOperands,
39226 /* 115524 */ // GIR_Coverage, 3062,
39227 /* 115524 */ GIR_EraseRootFromParent_Done,
39228 /* 115525 */ // Label 1704: @115525
39229 /* 115525 */ GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(115628), // Rule ID 3134 //
39230 /* 115530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
39231 /* 115533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39232 /* 115537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39233 /* 115541 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39234 /* 115545 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39235 /* 115549 */ // MIs[1] Operand 1
39236 /* 115549 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
39237 /* 115554 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39238 /* 115558 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39239 /* 115562 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
39240 /* 115566 */ // MIs[2] Operand 1
39241 /* 115566 */ // No operand predicates
39242 /* 115566 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39243 /* 115568 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }))
39244 /* 115568 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39245 /* 115571 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
39246 /* 115575 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39247 /* 115580 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39248 /* 115584 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39249 /* 115587 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39250 /* 115589 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39251 /* 115592 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39252 /* 115596 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39253 /* 115601 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
39254 /* 115608 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39255 /* 115613 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39256 /* 115618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39257 /* 115621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39258 /* 115623 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39259 /* 115626 */ GIR_RootConstrainSelectedInstOperands,
39260 /* 115627 */ // GIR_Coverage, 3134,
39261 /* 115627 */ GIR_EraseRootFromParent_Done,
39262 /* 115628 */ // Label 1705: @115628
39263 /* 115628 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(115731), // Rule ID 3150 //
39264 /* 115633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
39265 /* 115636 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39266 /* 115640 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39267 /* 115644 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39268 /* 115648 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39269 /* 115652 */ // MIs[1] Operand 1
39270 /* 115652 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
39271 /* 115657 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39272 /* 115661 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39273 /* 115665 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
39274 /* 115669 */ // MIs[2] Operand 1
39275 /* 115669 */ // No operand predicates
39276 /* 115669 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39277 /* 115671 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }))
39278 /* 115671 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39279 /* 115674 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
39280 /* 115678 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39281 /* 115683 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39282 /* 115687 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39283 /* 115690 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39284 /* 115692 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39285 /* 115695 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39286 /* 115699 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39287 /* 115704 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
39288 /* 115711 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39289 /* 115716 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39290 /* 115721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39291 /* 115724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39292 /* 115726 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39293 /* 115729 */ GIR_RootConstrainSelectedInstOperands,
39294 /* 115730 */ // GIR_Coverage, 3150,
39295 /* 115730 */ GIR_EraseRootFromParent_Done,
39296 /* 115731 */ // Label 1706: @115731
39297 /* 115731 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(115834), // Rule ID 3158 //
39298 /* 115736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
39299 /* 115739 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39300 /* 115743 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39301 /* 115747 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39302 /* 115751 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39303 /* 115755 */ // MIs[1] Operand 1
39304 /* 115755 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
39305 /* 115760 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39306 /* 115764 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39307 /* 115768 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
39308 /* 115772 */ // MIs[2] Operand 1
39309 /* 115772 */ // No operand predicates
39310 /* 115772 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39311 /* 115774 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }))
39312 /* 115774 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39313 /* 115777 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
39314 /* 115781 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39315 /* 115786 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39316 /* 115790 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39317 /* 115793 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39318 /* 115795 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39319 /* 115798 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39320 /* 115802 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39321 /* 115807 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
39322 /* 115814 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39323 /* 115819 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39324 /* 115824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39325 /* 115827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39326 /* 115829 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39327 /* 115832 */ GIR_RootConstrainSelectedInstOperands,
39328 /* 115833 */ // GIR_Coverage, 3158,
39329 /* 115833 */ GIR_EraseRootFromParent_Done,
39330 /* 115834 */ // Label 1707: @115834
39331 /* 115834 */ GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(115977), // Rule ID 3820 //
39332 /* 115839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
39333 /* 115842 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39334 /* 115846 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39335 /* 115850 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39336 /* 115854 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39337 /* 115858 */ // MIs[1] Operand 1
39338 /* 115858 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
39339 /* 115863 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39340 /* 115867 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39341 /* 115871 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
39342 /* 115875 */ // MIs[2] Operand 1
39343 /* 115875 */ // No operand predicates
39344 /* 115875 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39345 /* 115877 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
39346 /* 115877 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39347 /* 115880 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
39348 /* 115884 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39349 /* 115889 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39350 /* 115893 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39351 /* 115896 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39352 /* 115898 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
39353 /* 115901 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
39354 /* 115905 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39355 /* 115910 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
39356 /* 115913 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39357 /* 115915 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
39358 /* 115918 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
39359 /* 115922 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39360 /* 115927 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
39361 /* 115930 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
39362 /* 115932 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39363 /* 115935 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39364 /* 115939 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39365 /* 115944 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
39366 /* 115951 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39367 /* 115956 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39368 /* 115961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
39369 /* 115964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39370 /* 115966 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39371 /* 115969 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
39372 /* 115972 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
39373 /* 115975 */ GIR_RootConstrainSelectedInstOperands,
39374 /* 115976 */ // GIR_Coverage, 3820,
39375 /* 115976 */ GIR_EraseRootFromParent_Done,
39376 /* 115977 */ // Label 1708: @115977
39377 /* 115977 */ GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(116120), // Rule ID 3836 //
39378 /* 115982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
39379 /* 115985 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39380 /* 115989 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39381 /* 115993 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39382 /* 115997 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39383 /* 116001 */ // MIs[1] Operand 1
39384 /* 116001 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
39385 /* 116006 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39386 /* 116010 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39387 /* 116014 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
39388 /* 116018 */ // MIs[2] Operand 1
39389 /* 116018 */ // No operand predicates
39390 /* 116018 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39391 /* 116020 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
39392 /* 116020 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39393 /* 116023 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
39394 /* 116027 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39395 /* 116032 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39396 /* 116036 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39397 /* 116039 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39398 /* 116041 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
39399 /* 116044 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
39400 /* 116048 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39401 /* 116053 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
39402 /* 116056 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39403 /* 116058 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
39404 /* 116061 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
39405 /* 116065 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39406 /* 116070 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
39407 /* 116073 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
39408 /* 116075 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39409 /* 116078 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39410 /* 116082 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39411 /* 116087 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
39412 /* 116094 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39413 /* 116099 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39414 /* 116104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
39415 /* 116107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39416 /* 116109 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39417 /* 116112 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
39418 /* 116115 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
39419 /* 116118 */ GIR_RootConstrainSelectedInstOperands,
39420 /* 116119 */ // GIR_Coverage, 3836,
39421 /* 116119 */ GIR_EraseRootFromParent_Done,
39422 /* 116120 */ // Label 1709: @116120
39423 /* 116120 */ GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(116263), // Rule ID 3844 //
39424 /* 116125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
39425 /* 116128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39426 /* 116132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39427 /* 116136 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39428 /* 116140 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39429 /* 116144 */ // MIs[1] Operand 1
39430 /* 116144 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
39431 /* 116149 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39432 /* 116153 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39433 /* 116157 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
39434 /* 116161 */ // MIs[2] Operand 1
39435 /* 116161 */ // No operand predicates
39436 /* 116161 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39437 /* 116163 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
39438 /* 116163 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39439 /* 116166 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
39440 /* 116170 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39441 /* 116175 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39442 /* 116179 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39443 /* 116182 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39444 /* 116184 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
39445 /* 116187 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
39446 /* 116191 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39447 /* 116196 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
39448 /* 116199 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39449 /* 116201 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
39450 /* 116204 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
39451 /* 116208 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39452 /* 116213 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
39453 /* 116216 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
39454 /* 116218 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39455 /* 116221 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39456 /* 116225 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39457 /* 116230 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
39458 /* 116237 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39459 /* 116242 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39460 /* 116247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
39461 /* 116250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39462 /* 116252 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39463 /* 116255 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
39464 /* 116258 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
39465 /* 116261 */ GIR_RootConstrainSelectedInstOperands,
39466 /* 116262 */ // GIR_Coverage, 3844,
39467 /* 116262 */ GIR_EraseRootFromParent_Done,
39468 /* 116263 */ // Label 1710: @116263
39469 /* 116263 */ GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(116406), // Rule ID 3916 //
39470 /* 116268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
39471 /* 116271 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39472 /* 116275 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39473 /* 116279 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39474 /* 116283 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39475 /* 116287 */ // MIs[1] Operand 1
39476 /* 116287 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
39477 /* 116292 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39478 /* 116296 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39479 /* 116300 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
39480 /* 116304 */ // MIs[2] Operand 1
39481 /* 116304 */ // No operand predicates
39482 /* 116304 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39483 /* 116306 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
39484 /* 116306 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39485 /* 116309 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
39486 /* 116313 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39487 /* 116318 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39488 /* 116322 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39489 /* 116325 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39490 /* 116327 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
39491 /* 116330 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
39492 /* 116334 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39493 /* 116339 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
39494 /* 116342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39495 /* 116344 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
39496 /* 116347 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
39497 /* 116351 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39498 /* 116356 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
39499 /* 116359 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
39500 /* 116361 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39501 /* 116364 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39502 /* 116368 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39503 /* 116373 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
39504 /* 116380 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39505 /* 116385 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39506 /* 116390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
39507 /* 116393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39508 /* 116395 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39509 /* 116398 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
39510 /* 116401 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
39511 /* 116404 */ GIR_RootConstrainSelectedInstOperands,
39512 /* 116405 */ // GIR_Coverage, 3916,
39513 /* 116405 */ GIR_EraseRootFromParent_Done,
39514 /* 116406 */ // Label 1711: @116406
39515 /* 116406 */ GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(116549), // Rule ID 3932 //
39516 /* 116411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
39517 /* 116414 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39518 /* 116418 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39519 /* 116422 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39520 /* 116426 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39521 /* 116430 */ // MIs[1] Operand 1
39522 /* 116430 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
39523 /* 116435 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39524 /* 116439 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39525 /* 116443 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
39526 /* 116447 */ // MIs[2] Operand 1
39527 /* 116447 */ // No operand predicates
39528 /* 116447 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39529 /* 116449 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
39530 /* 116449 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39531 /* 116452 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
39532 /* 116456 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39533 /* 116461 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39534 /* 116465 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39535 /* 116468 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39536 /* 116470 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
39537 /* 116473 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
39538 /* 116477 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39539 /* 116482 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
39540 /* 116485 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39541 /* 116487 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
39542 /* 116490 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
39543 /* 116494 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39544 /* 116499 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
39545 /* 116502 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
39546 /* 116504 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39547 /* 116507 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39548 /* 116511 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39549 /* 116516 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
39550 /* 116523 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39551 /* 116528 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39552 /* 116533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
39553 /* 116536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39554 /* 116538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39555 /* 116541 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
39556 /* 116544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
39557 /* 116547 */ GIR_RootConstrainSelectedInstOperands,
39558 /* 116548 */ // GIR_Coverage, 3932,
39559 /* 116548 */ GIR_EraseRootFromParent_Done,
39560 /* 116549 */ // Label 1712: @116549
39561 /* 116549 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(116692), // Rule ID 3940 //
39562 /* 116554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
39563 /* 116557 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39564 /* 116561 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
39565 /* 116565 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39566 /* 116569 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39567 /* 116573 */ // MIs[1] Operand 1
39568 /* 116573 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
39569 /* 116578 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
39570 /* 116582 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39571 /* 116586 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
39572 /* 116590 */ // MIs[2] Operand 1
39573 /* 116590 */ // No operand predicates
39574 /* 116590 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39575 /* 116592 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
39576 /* 116592 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39577 /* 116595 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
39578 /* 116599 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39579 /* 116604 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39580 /* 116608 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
39581 /* 116611 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39582 /* 116613 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
39583 /* 116616 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
39584 /* 116620 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39585 /* 116625 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
39586 /* 116628 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39587 /* 116630 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
39588 /* 116633 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
39589 /* 116637 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39590 /* 116642 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
39591 /* 116645 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
39592 /* 116647 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39593 /* 116650 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39594 /* 116654 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39595 /* 116659 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
39596 /* 116666 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39597 /* 116671 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39598 /* 116676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
39599 /* 116679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39600 /* 116681 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39601 /* 116684 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
39602 /* 116687 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
39603 /* 116690 */ GIR_RootConstrainSelectedInstOperands,
39604 /* 116691 */ // GIR_Coverage, 3940,
39605 /* 116691 */ GIR_EraseRootFromParent_Done,
39606 /* 116692 */ // Label 1713: @116692
39607 /* 116692 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(116784), // Rule ID 3182 //
39608 /* 116697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39609 /* 116700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39610 /* 116704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39611 /* 116708 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39612 /* 116712 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39613 /* 116716 */ // MIs[1] Operand 1
39614 /* 116716 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
39615 /* 116721 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39616 /* 116723 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }))
39617 /* 116723 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39618 /* 116726 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
39619 /* 116730 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39620 /* 116735 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39621 /* 116739 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39622 /* 116743 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39623 /* 116745 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39624 /* 116748 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39625 /* 116752 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39626 /* 116757 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
39627 /* 116764 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39628 /* 116769 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39629 /* 116774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39630 /* 116777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39631 /* 116779 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39632 /* 116782 */ GIR_RootConstrainSelectedInstOperands,
39633 /* 116783 */ // GIR_Coverage, 3182,
39634 /* 116783 */ GIR_EraseRootFromParent_Done,
39635 /* 116784 */ // Label 1714: @116784
39636 /* 116784 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(116876), // Rule ID 3198 //
39637 /* 116789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39638 /* 116792 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39639 /* 116796 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39640 /* 116800 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39641 /* 116804 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39642 /* 116808 */ // MIs[1] Operand 1
39643 /* 116808 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
39644 /* 116813 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39645 /* 116815 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
39646 /* 116815 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39647 /* 116818 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
39648 /* 116822 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39649 /* 116827 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39650 /* 116831 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39651 /* 116835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39652 /* 116837 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39653 /* 116840 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39654 /* 116844 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39655 /* 116849 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
39656 /* 116856 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39657 /* 116861 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39658 /* 116866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39659 /* 116869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39660 /* 116871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39661 /* 116874 */ GIR_RootConstrainSelectedInstOperands,
39662 /* 116875 */ // GIR_Coverage, 3198,
39663 /* 116875 */ GIR_EraseRootFromParent_Done,
39664 /* 116876 */ // Label 1715: @116876
39665 /* 116876 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(116968), // Rule ID 3214 //
39666 /* 116881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39667 /* 116884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39668 /* 116888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39669 /* 116892 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39670 /* 116896 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39671 /* 116900 */ // MIs[1] Operand 1
39672 /* 116900 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
39673 /* 116905 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39674 /* 116907 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }))
39675 /* 116907 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39676 /* 116910 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
39677 /* 116914 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39678 /* 116919 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39679 /* 116923 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39680 /* 116927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39681 /* 116929 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39682 /* 116932 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39683 /* 116936 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39684 /* 116941 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
39685 /* 116948 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39686 /* 116953 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39687 /* 116958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39688 /* 116961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39689 /* 116963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39690 /* 116966 */ GIR_RootConstrainSelectedInstOperands,
39691 /* 116967 */ // GIR_Coverage, 3214,
39692 /* 116967 */ GIR_EraseRootFromParent_Done,
39693 /* 116968 */ // Label 1716: @116968
39694 /* 116968 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(117060), // Rule ID 3230 //
39695 /* 116973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39696 /* 116976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39697 /* 116980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39698 /* 116984 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39699 /* 116988 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39700 /* 116992 */ // MIs[1] Operand 1
39701 /* 116992 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
39702 /* 116997 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39703 /* 116999 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }))
39704 /* 116999 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39705 /* 117002 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
39706 /* 117006 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39707 /* 117011 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39708 /* 117015 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39709 /* 117019 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39710 /* 117021 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39711 /* 117024 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39712 /* 117028 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39713 /* 117033 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
39714 /* 117040 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39715 /* 117045 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39716 /* 117050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39717 /* 117053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39718 /* 117055 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39719 /* 117058 */ GIR_RootConstrainSelectedInstOperands,
39720 /* 117059 */ // GIR_Coverage, 3230,
39721 /* 117059 */ GIR_EraseRootFromParent_Done,
39722 /* 117060 */ // Label 1717: @117060
39723 /* 117060 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(117152), // Rule ID 3238 //
39724 /* 117065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39725 /* 117068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39726 /* 117072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39727 /* 117076 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39728 /* 117080 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39729 /* 117084 */ // MIs[1] Operand 1
39730 /* 117084 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
39731 /* 117089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39732 /* 117091 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }))
39733 /* 117091 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39734 /* 117094 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
39735 /* 117098 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39736 /* 117103 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39737 /* 117107 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39738 /* 117111 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39739 /* 117113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39740 /* 117116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39741 /* 117120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39742 /* 117125 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
39743 /* 117132 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39744 /* 117137 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39745 /* 117142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39746 /* 117145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39747 /* 117147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39748 /* 117150 */ GIR_RootConstrainSelectedInstOperands,
39749 /* 117151 */ // GIR_Coverage, 3238,
39750 /* 117151 */ GIR_EraseRootFromParent_Done,
39751 /* 117152 */ // Label 1718: @117152
39752 /* 117152 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(117244), // Rule ID 3254 //
39753 /* 117157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39754 /* 117160 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39755 /* 117164 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39756 /* 117168 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39757 /* 117172 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39758 /* 117176 */ // MIs[1] Operand 1
39759 /* 117176 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
39760 /* 117181 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39761 /* 117183 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
39762 /* 117183 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39763 /* 117186 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
39764 /* 117190 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39765 /* 117195 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39766 /* 117199 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39767 /* 117203 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39768 /* 117205 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39769 /* 117208 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39770 /* 117212 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39771 /* 117217 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
39772 /* 117224 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39773 /* 117229 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39774 /* 117234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39775 /* 117237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39776 /* 117239 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39777 /* 117242 */ GIR_RootConstrainSelectedInstOperands,
39778 /* 117243 */ // GIR_Coverage, 3254,
39779 /* 117243 */ GIR_EraseRootFromParent_Done,
39780 /* 117244 */ // Label 1719: @117244
39781 /* 117244 */ GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(117336), // Rule ID 3270 //
39782 /* 117249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39783 /* 117252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39784 /* 117256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39785 /* 117260 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39786 /* 117264 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39787 /* 117268 */ // MIs[1] Operand 1
39788 /* 117268 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
39789 /* 117273 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39790 /* 117275 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }))
39791 /* 117275 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39792 /* 117278 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
39793 /* 117282 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39794 /* 117287 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39795 /* 117291 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39796 /* 117295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39797 /* 117297 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39798 /* 117300 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39799 /* 117304 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39800 /* 117309 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
39801 /* 117316 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39802 /* 117321 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39803 /* 117326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39804 /* 117329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39805 /* 117331 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39806 /* 117334 */ GIR_RootConstrainSelectedInstOperands,
39807 /* 117335 */ // GIR_Coverage, 3270,
39808 /* 117335 */ GIR_EraseRootFromParent_Done,
39809 /* 117336 */ // Label 1720: @117336
39810 /* 117336 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(117428), // Rule ID 3286 //
39811 /* 117341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39812 /* 117344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39813 /* 117348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39814 /* 117352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
39815 /* 117356 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
39816 /* 117360 */ // MIs[1] Operand 1
39817 /* 117360 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
39818 /* 117365 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39819 /* 117367 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }))
39820 /* 117367 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39821 /* 117370 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
39822 /* 117374 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39823 /* 117379 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39824 /* 117383 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39825 /* 117387 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39826 /* 117389 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39827 /* 117392 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39828 /* 117396 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39829 /* 117401 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
39830 /* 117408 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39831 /* 117413 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39832 /* 117418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39833 /* 117421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39834 /* 117423 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39835 /* 117426 */ GIR_RootConstrainSelectedInstOperands,
39836 /* 117427 */ // GIR_Coverage, 3286,
39837 /* 117427 */ GIR_EraseRootFromParent_Done,
39838 /* 117428 */ // Label 1721: @117428
39839 /* 117428 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(117520), // Rule ID 3294 //
39840 /* 117433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39841 /* 117436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39842 /* 117440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39843 /* 117444 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
39844 /* 117448 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
39845 /* 117452 */ // MIs[1] Operand 1
39846 /* 117452 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
39847 /* 117457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39848 /* 117459 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }))
39849 /* 117459 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39850 /* 117462 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
39851 /* 117466 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39852 /* 117471 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39853 /* 117475 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39854 /* 117479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39855 /* 117481 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39856 /* 117484 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39857 /* 117488 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39858 /* 117493 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
39859 /* 117500 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39860 /* 117505 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39861 /* 117510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39862 /* 117513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39863 /* 117515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39864 /* 117518 */ GIR_RootConstrainSelectedInstOperands,
39865 /* 117519 */ // GIR_Coverage, 3294,
39866 /* 117519 */ GIR_EraseRootFromParent_Done,
39867 /* 117520 */ // Label 1722: @117520
39868 /* 117520 */ GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(117612), // Rule ID 3310 //
39869 /* 117525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39870 /* 117528 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39871 /* 117532 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39872 /* 117536 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
39873 /* 117540 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
39874 /* 117544 */ // MIs[1] Operand 1
39875 /* 117544 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
39876 /* 117549 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39877 /* 117551 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }))
39878 /* 117551 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39879 /* 117554 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
39880 /* 117558 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39881 /* 117563 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39882 /* 117567 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39883 /* 117571 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39884 /* 117573 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39885 /* 117576 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39886 /* 117580 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39887 /* 117585 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
39888 /* 117592 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39889 /* 117597 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39890 /* 117602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39891 /* 117605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39892 /* 117607 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39893 /* 117610 */ GIR_RootConstrainSelectedInstOperands,
39894 /* 117611 */ // GIR_Coverage, 3310,
39895 /* 117611 */ GIR_EraseRootFromParent_Done,
39896 /* 117612 */ // Label 1723: @117612
39897 /* 117612 */ GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(117704), // Rule ID 3326 //
39898 /* 117617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39899 /* 117620 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39900 /* 117624 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39901 /* 117628 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
39902 /* 117632 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
39903 /* 117636 */ // MIs[1] Operand 1
39904 /* 117636 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
39905 /* 117641 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39906 /* 117643 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }))
39907 /* 117643 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39908 /* 117646 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
39909 /* 117650 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39910 /* 117655 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39911 /* 117659 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39912 /* 117663 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39913 /* 117665 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39914 /* 117668 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39915 /* 117672 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39916 /* 117677 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
39917 /* 117684 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39918 /* 117689 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39919 /* 117694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39920 /* 117697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39921 /* 117699 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39922 /* 117702 */ GIR_RootConstrainSelectedInstOperands,
39923 /* 117703 */ // GIR_Coverage, 3326,
39924 /* 117703 */ GIR_EraseRootFromParent_Done,
39925 /* 117704 */ // Label 1724: @117704
39926 /* 117704 */ GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(117796), // Rule ID 3342 //
39927 /* 117709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
39928 /* 117712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39929 /* 117716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39930 /* 117720 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
39931 /* 117724 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
39932 /* 117728 */ // MIs[1] Operand 1
39933 /* 117728 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
39934 /* 117733 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39935 /* 117735 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }))
39936 /* 117735 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39937 /* 117738 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
39938 /* 117742 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39939 /* 117747 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39940 /* 117751 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39941 /* 117755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39942 /* 117757 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39943 /* 117760 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39944 /* 117764 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39945 /* 117769 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
39946 /* 117776 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39947 /* 117781 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39948 /* 117786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
39949 /* 117789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
39950 /* 117791 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39951 /* 117794 */ GIR_RootConstrainSelectedInstOperands,
39952 /* 117795 */ // GIR_Coverage, 3342,
39953 /* 117795 */ GIR_EraseRootFromParent_Done,
39954 /* 117796 */ // Label 1725: @117796
39955 /* 117796 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(117928), // Rule ID 4022 //
39956 /* 117801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
39957 /* 117804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39958 /* 117808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
39959 /* 117812 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39960 /* 117816 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
39961 /* 117820 */ // MIs[1] Operand 1
39962 /* 117820 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
39963 /* 117825 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39964 /* 117827 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
39965 /* 117827 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
39966 /* 117830 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
39967 /* 117834 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39968 /* 117839 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
39969 /* 117843 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
39970 /* 117847 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39971 /* 117849 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
39972 /* 117852 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
39973 /* 117856 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39974 /* 117861 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
39975 /* 117864 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39976 /* 117866 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
39977 /* 117869 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
39978 /* 117873 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39979 /* 117878 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
39980 /* 117881 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
39981 /* 117883 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
39982 /* 117886 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39983 /* 117890 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
39984 /* 117895 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
39985 /* 117902 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
39986 /* 117907 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
39987 /* 117912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
39988 /* 117915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39989 /* 117917 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39990 /* 117920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
39991 /* 117923 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
39992 /* 117926 */ GIR_RootConstrainSelectedInstOperands,
39993 /* 117927 */ // GIR_Coverage, 4022,
39994 /* 117927 */ GIR_EraseRootFromParent_Done,
39995 /* 117928 */ // Label 1726: @117928
39996 /* 117928 */ GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(118060), // Rule ID 4054 //
39997 /* 117933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
39998 /* 117936 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39999 /* 117940 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40000 /* 117944 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40001 /* 117948 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40002 /* 117952 */ // MIs[1] Operand 1
40003 /* 117952 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
40004 /* 117957 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40005 /* 117959 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40006 /* 117959 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40007 /* 117962 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
40008 /* 117966 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40009 /* 117971 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40010 /* 117975 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40011 /* 117979 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40012 /* 117981 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40013 /* 117984 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40014 /* 117988 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40015 /* 117993 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40016 /* 117996 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40017 /* 117998 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40018 /* 118001 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40019 /* 118005 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40020 /* 118010 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40021 /* 118013 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40022 /* 118015 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40023 /* 118018 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40024 /* 118022 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40025 /* 118027 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40026 /* 118034 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40027 /* 118039 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40028 /* 118044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40029 /* 118047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40030 /* 118049 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40031 /* 118052 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40032 /* 118055 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40033 /* 118058 */ GIR_RootConstrainSelectedInstOperands,
40034 /* 118059 */ // GIR_Coverage, 4054,
40035 /* 118059 */ GIR_EraseRootFromParent_Done,
40036 /* 118060 */ // Label 1727: @118060
40037 /* 118060 */ GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(118192), // Rule ID 4086 //
40038 /* 118065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40039 /* 118068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40040 /* 118072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40041 /* 118076 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40042 /* 118080 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40043 /* 118084 */ // MIs[1] Operand 1
40044 /* 118084 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
40045 /* 118089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40046 /* 118091 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40047 /* 118091 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40048 /* 118094 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
40049 /* 118098 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40050 /* 118103 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40051 /* 118107 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40052 /* 118111 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40053 /* 118113 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40054 /* 118116 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40055 /* 118120 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40056 /* 118125 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40057 /* 118128 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40058 /* 118130 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40059 /* 118133 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40060 /* 118137 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40061 /* 118142 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40062 /* 118145 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40063 /* 118147 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40064 /* 118150 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40065 /* 118154 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40066 /* 118159 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
40067 /* 118166 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40068 /* 118171 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40069 /* 118176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40070 /* 118179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40071 /* 118181 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40072 /* 118184 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40073 /* 118187 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40074 /* 118190 */ GIR_RootConstrainSelectedInstOperands,
40075 /* 118191 */ // GIR_Coverage, 4086,
40076 /* 118191 */ GIR_EraseRootFromParent_Done,
40077 /* 118192 */ // Label 1728: @118192
40078 /* 118192 */ GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(118324), // Rule ID 4118 //
40079 /* 118197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40080 /* 118200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40081 /* 118204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40082 /* 118208 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40083 /* 118212 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40084 /* 118216 */ // MIs[1] Operand 1
40085 /* 118216 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
40086 /* 118221 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40087 /* 118223 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40088 /* 118223 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40089 /* 118226 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
40090 /* 118230 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40091 /* 118235 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40092 /* 118239 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40093 /* 118243 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40094 /* 118245 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40095 /* 118248 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40096 /* 118252 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40097 /* 118257 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40098 /* 118260 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40099 /* 118262 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40100 /* 118265 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40101 /* 118269 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40102 /* 118274 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40103 /* 118277 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40104 /* 118279 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40105 /* 118282 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40106 /* 118286 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40107 /* 118291 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
40108 /* 118298 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40109 /* 118303 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40110 /* 118308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40111 /* 118311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40112 /* 118313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40113 /* 118316 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40114 /* 118319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40115 /* 118322 */ GIR_RootConstrainSelectedInstOperands,
40116 /* 118323 */ // GIR_Coverage, 4118,
40117 /* 118323 */ GIR_EraseRootFromParent_Done,
40118 /* 118324 */ // Label 1729: @118324
40119 /* 118324 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(118456), // Rule ID 4134 //
40120 /* 118329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40121 /* 118332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40122 /* 118336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40123 /* 118340 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40124 /* 118344 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40125 /* 118348 */ // MIs[1] Operand 1
40126 /* 118348 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
40127 /* 118353 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40128 /* 118355 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40129 /* 118355 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40130 /* 118358 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
40131 /* 118362 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40132 /* 118367 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40133 /* 118371 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40134 /* 118375 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40135 /* 118377 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40136 /* 118380 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40137 /* 118384 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40138 /* 118389 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40139 /* 118392 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40140 /* 118394 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40141 /* 118397 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40142 /* 118401 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40143 /* 118406 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40144 /* 118409 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40145 /* 118411 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40146 /* 118414 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40147 /* 118418 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40148 /* 118423 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
40149 /* 118430 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40150 /* 118435 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40151 /* 118440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40152 /* 118443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40153 /* 118445 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40154 /* 118448 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40155 /* 118451 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40156 /* 118454 */ GIR_RootConstrainSelectedInstOperands,
40157 /* 118455 */ // GIR_Coverage, 4134,
40158 /* 118455 */ GIR_EraseRootFromParent_Done,
40159 /* 118456 */ // Label 1730: @118456
40160 /* 118456 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(118588), // Rule ID 4166 //
40161 /* 118461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40162 /* 118464 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40163 /* 118468 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40164 /* 118472 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40165 /* 118476 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40166 /* 118480 */ // MIs[1] Operand 1
40167 /* 118480 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
40168 /* 118485 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40169 /* 118487 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40170 /* 118487 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40171 /* 118490 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
40172 /* 118494 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40173 /* 118499 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40174 /* 118503 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40175 /* 118507 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40176 /* 118509 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40177 /* 118512 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40178 /* 118516 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40179 /* 118521 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40180 /* 118524 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40181 /* 118526 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40182 /* 118529 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40183 /* 118533 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40184 /* 118538 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40185 /* 118541 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40186 /* 118543 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40187 /* 118546 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40188 /* 118550 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40189 /* 118555 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40190 /* 118562 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40191 /* 118567 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40192 /* 118572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40193 /* 118575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40194 /* 118577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40195 /* 118580 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40196 /* 118583 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40197 /* 118586 */ GIR_RootConstrainSelectedInstOperands,
40198 /* 118587 */ // GIR_Coverage, 4166,
40199 /* 118587 */ GIR_EraseRootFromParent_Done,
40200 /* 118588 */ // Label 1731: @118588
40201 /* 118588 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(118720), // Rule ID 4198 //
40202 /* 118593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40203 /* 118596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40204 /* 118600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40205 /* 118604 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40206 /* 118608 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40207 /* 118612 */ // MIs[1] Operand 1
40208 /* 118612 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
40209 /* 118617 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40210 /* 118619 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40211 /* 118619 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40212 /* 118622 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
40213 /* 118626 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40214 /* 118631 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40215 /* 118635 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40216 /* 118639 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40217 /* 118641 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40218 /* 118644 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40219 /* 118648 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40220 /* 118653 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40221 /* 118656 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40222 /* 118658 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40223 /* 118661 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40224 /* 118665 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40225 /* 118670 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40226 /* 118673 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40227 /* 118675 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40228 /* 118678 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40229 /* 118682 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40230 /* 118687 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
40231 /* 118694 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40232 /* 118699 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40233 /* 118704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40234 /* 118707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40235 /* 118709 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40236 /* 118712 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40237 /* 118715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40238 /* 118718 */ GIR_RootConstrainSelectedInstOperands,
40239 /* 118719 */ // GIR_Coverage, 4198,
40240 /* 118719 */ GIR_EraseRootFromParent_Done,
40241 /* 118720 */ // Label 1732: @118720
40242 /* 118720 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(118852), // Rule ID 4230 //
40243 /* 118725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40244 /* 118728 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40245 /* 118732 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40246 /* 118736 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40247 /* 118740 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40248 /* 118744 */ // MIs[1] Operand 1
40249 /* 118744 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
40250 /* 118749 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40251 /* 118751 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40252 /* 118751 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40253 /* 118754 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
40254 /* 118758 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40255 /* 118763 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40256 /* 118767 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40257 /* 118771 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40258 /* 118773 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40259 /* 118776 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40260 /* 118780 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40261 /* 118785 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40262 /* 118788 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40263 /* 118790 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40264 /* 118793 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40265 /* 118797 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40266 /* 118802 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40267 /* 118805 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40268 /* 118807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40269 /* 118810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40270 /* 118814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40271 /* 118819 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
40272 /* 118826 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40273 /* 118831 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40274 /* 118836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40275 /* 118839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40276 /* 118841 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40277 /* 118844 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40278 /* 118847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40279 /* 118850 */ GIR_RootConstrainSelectedInstOperands,
40280 /* 118851 */ // GIR_Coverage, 4230,
40281 /* 118851 */ GIR_EraseRootFromParent_Done,
40282 /* 118852 */ // Label 1733: @118852
40283 /* 118852 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(118984), // Rule ID 4260 //
40284 /* 118857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40285 /* 118860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40286 /* 118864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40287 /* 118868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
40288 /* 118872 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
40289 /* 118876 */ // MIs[1] Operand 1
40290 /* 118876 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
40291 /* 118881 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40292 /* 118883 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40293 /* 118883 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40294 /* 118886 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
40295 /* 118890 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40296 /* 118895 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40297 /* 118899 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40298 /* 118903 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40299 /* 118905 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40300 /* 118908 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40301 /* 118912 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40302 /* 118917 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40303 /* 118920 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40304 /* 118922 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40305 /* 118925 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40306 /* 118929 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40307 /* 118934 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40308 /* 118937 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40309 /* 118939 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40310 /* 118942 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40311 /* 118946 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40312 /* 118951 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
40313 /* 118958 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40314 /* 118963 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40315 /* 118968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40316 /* 118971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40317 /* 118973 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40318 /* 118976 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40319 /* 118979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40320 /* 118982 */ GIR_RootConstrainSelectedInstOperands,
40321 /* 118983 */ // GIR_Coverage, 4260,
40322 /* 118983 */ GIR_EraseRootFromParent_Done,
40323 /* 118984 */ // Label 1734: @118984
40324 /* 118984 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(119116), // Rule ID 4292 //
40325 /* 118989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40326 /* 118992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40327 /* 118996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40328 /* 119000 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
40329 /* 119004 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
40330 /* 119008 */ // MIs[1] Operand 1
40331 /* 119008 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
40332 /* 119013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40333 /* 119015 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40334 /* 119015 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40335 /* 119018 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
40336 /* 119022 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40337 /* 119027 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40338 /* 119031 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40339 /* 119035 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40340 /* 119037 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40341 /* 119040 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40342 /* 119044 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40343 /* 119049 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40344 /* 119052 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40345 /* 119054 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40346 /* 119057 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40347 /* 119061 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40348 /* 119066 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40349 /* 119069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40350 /* 119071 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40351 /* 119074 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40352 /* 119078 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40353 /* 119083 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40354 /* 119090 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40355 /* 119095 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40356 /* 119100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40357 /* 119103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40358 /* 119105 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40359 /* 119108 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40360 /* 119111 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40361 /* 119114 */ GIR_RootConstrainSelectedInstOperands,
40362 /* 119115 */ // GIR_Coverage, 4292,
40363 /* 119115 */ GIR_EraseRootFromParent_Done,
40364 /* 119116 */ // Label 1735: @119116
40365 /* 119116 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(119248), // Rule ID 4324 //
40366 /* 119121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40367 /* 119124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40368 /* 119128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40369 /* 119132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
40370 /* 119136 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
40371 /* 119140 */ // MIs[1] Operand 1
40372 /* 119140 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
40373 /* 119145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40374 /* 119147 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40375 /* 119147 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40376 /* 119150 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
40377 /* 119154 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40378 /* 119159 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40379 /* 119163 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40380 /* 119167 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40381 /* 119169 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40382 /* 119172 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40383 /* 119176 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40384 /* 119181 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40385 /* 119184 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40386 /* 119186 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40387 /* 119189 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40388 /* 119193 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40389 /* 119198 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40390 /* 119201 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40391 /* 119203 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40392 /* 119206 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40393 /* 119210 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40394 /* 119215 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
40395 /* 119222 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40396 /* 119227 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40397 /* 119232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40398 /* 119235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40399 /* 119237 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40400 /* 119240 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40401 /* 119243 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40402 /* 119246 */ GIR_RootConstrainSelectedInstOperands,
40403 /* 119247 */ // GIR_Coverage, 4324,
40404 /* 119247 */ GIR_EraseRootFromParent_Done,
40405 /* 119248 */ // Label 1736: @119248
40406 /* 119248 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(119380), // Rule ID 4356 //
40407 /* 119253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
40408 /* 119256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40409 /* 119260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40410 /* 119264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
40411 /* 119268 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
40412 /* 119272 */ // MIs[1] Operand 1
40413 /* 119272 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
40414 /* 119277 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40415 /* 119279 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40416 /* 119279 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40417 /* 119282 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
40418 /* 119286 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40419 /* 119291 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40420 /* 119295 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40421 /* 119299 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40422 /* 119301 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40423 /* 119304 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40424 /* 119308 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40425 /* 119313 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40426 /* 119316 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40427 /* 119318 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40428 /* 119321 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40429 /* 119325 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40430 /* 119330 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40431 /* 119333 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40432 /* 119335 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40433 /* 119338 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40434 /* 119342 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40435 /* 119347 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
40436 /* 119354 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40437 /* 119359 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40438 /* 119364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40439 /* 119367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40440 /* 119369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40441 /* 119372 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40442 /* 119375 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40443 /* 119378 */ GIR_RootConstrainSelectedInstOperands,
40444 /* 119379 */ // GIR_Coverage, 4356,
40445 /* 119379 */ GIR_EraseRootFromParent_Done,
40446 /* 119380 */ // Label 1737: @119380
40447 /* 119380 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(119512), // Rule ID 4587 //
40448 /* 119385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
40449 /* 119388 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40450 /* 119392 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40451 /* 119396 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40452 /* 119400 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40453 /* 119404 */ // MIs[1] Operand 1
40454 /* 119404 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
40455 /* 119409 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40456 /* 119411 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40457 /* 119411 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40458 /* 119414 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
40459 /* 119418 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40460 /* 119423 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40461 /* 119427 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40462 /* 119431 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40463 /* 119433 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40464 /* 119436 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40465 /* 119440 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40466 /* 119445 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40467 /* 119448 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40468 /* 119450 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40469 /* 119453 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40470 /* 119457 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40471 /* 119462 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40472 /* 119465 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40473 /* 119467 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40474 /* 119470 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40475 /* 119474 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40476 /* 119479 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40477 /* 119486 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40478 /* 119491 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40479 /* 119496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40480 /* 119499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40481 /* 119501 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40482 /* 119504 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40483 /* 119507 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40484 /* 119510 */ GIR_RootConstrainSelectedInstOperands,
40485 /* 119511 */ // GIR_Coverage, 4587,
40486 /* 119511 */ GIR_EraseRootFromParent_Done,
40487 /* 119512 */ // Label 1738: @119512
40488 /* 119512 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(119644), // Rule ID 4619 //
40489 /* 119517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
40490 /* 119520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40491 /* 119524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40492 /* 119528 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40493 /* 119532 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40494 /* 119536 */ // MIs[1] Operand 1
40495 /* 119536 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
40496 /* 119541 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40497 /* 119543 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40498 /* 119543 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40499 /* 119546 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
40500 /* 119550 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40501 /* 119555 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40502 /* 119559 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40503 /* 119563 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40504 /* 119565 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40505 /* 119568 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40506 /* 119572 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40507 /* 119577 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40508 /* 119580 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40509 /* 119582 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40510 /* 119585 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40511 /* 119589 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40512 /* 119594 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40513 /* 119597 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40514 /* 119599 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40515 /* 119602 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40516 /* 119606 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40517 /* 119611 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40518 /* 119618 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40519 /* 119623 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40520 /* 119628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40521 /* 119631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40522 /* 119633 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40523 /* 119636 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40524 /* 119639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40525 /* 119642 */ GIR_RootConstrainSelectedInstOperands,
40526 /* 119643 */ // GIR_Coverage, 4619,
40527 /* 119643 */ GIR_EraseRootFromParent_Done,
40528 /* 119644 */ // Label 1739: @119644
40529 /* 119644 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(119776), // Rule ID 4651 //
40530 /* 119649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
40531 /* 119652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40532 /* 119656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40533 /* 119660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40534 /* 119664 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40535 /* 119668 */ // MIs[1] Operand 1
40536 /* 119668 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
40537 /* 119673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40538 /* 119675 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40539 /* 119675 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40540 /* 119678 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
40541 /* 119682 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40542 /* 119687 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40543 /* 119691 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40544 /* 119695 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40545 /* 119697 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40546 /* 119700 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40547 /* 119704 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40548 /* 119709 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40549 /* 119712 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40550 /* 119714 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40551 /* 119717 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40552 /* 119721 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40553 /* 119726 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40554 /* 119729 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40555 /* 119731 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40556 /* 119734 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40557 /* 119738 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40558 /* 119743 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40559 /* 119750 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40560 /* 119755 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40561 /* 119760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40562 /* 119763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40563 /* 119765 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40564 /* 119768 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40565 /* 119771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40566 /* 119774 */ GIR_RootConstrainSelectedInstOperands,
40567 /* 119775 */ // GIR_Coverage, 4651,
40568 /* 119775 */ GIR_EraseRootFromParent_Done,
40569 /* 119776 */ // Label 1740: @119776
40570 /* 119776 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(119908), // Rule ID 4695 //
40571 /* 119781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
40572 /* 119784 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40573 /* 119788 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40574 /* 119792 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40575 /* 119796 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40576 /* 119800 */ // MIs[1] Operand 1
40577 /* 119800 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
40578 /* 119805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40579 /* 119807 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40580 /* 119807 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40581 /* 119810 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
40582 /* 119814 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40583 /* 119819 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40584 /* 119823 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40585 /* 119827 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40586 /* 119829 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40587 /* 119832 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40588 /* 119836 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40589 /* 119841 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40590 /* 119844 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40591 /* 119846 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40592 /* 119849 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40593 /* 119853 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40594 /* 119858 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40595 /* 119861 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40596 /* 119863 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40597 /* 119866 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40598 /* 119870 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40599 /* 119875 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40600 /* 119882 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40601 /* 119887 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40602 /* 119892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40603 /* 119895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40604 /* 119897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40605 /* 119900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40606 /* 119903 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40607 /* 119906 */ GIR_RootConstrainSelectedInstOperands,
40608 /* 119907 */ // GIR_Coverage, 4695,
40609 /* 119907 */ GIR_EraseRootFromParent_Done,
40610 /* 119908 */ // Label 1741: @119908
40611 /* 119908 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(120040), // Rule ID 4727 //
40612 /* 119913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
40613 /* 119916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40614 /* 119920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40615 /* 119924 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40616 /* 119928 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40617 /* 119932 */ // MIs[1] Operand 1
40618 /* 119932 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
40619 /* 119937 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40620 /* 119939 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40621 /* 119939 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40622 /* 119942 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
40623 /* 119946 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40624 /* 119951 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40625 /* 119955 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40626 /* 119959 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40627 /* 119961 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40628 /* 119964 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40629 /* 119968 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40630 /* 119973 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40631 /* 119976 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40632 /* 119978 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40633 /* 119981 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40634 /* 119985 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40635 /* 119990 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40636 /* 119993 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40637 /* 119995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40638 /* 119998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40639 /* 120002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40640 /* 120007 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40641 /* 120014 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40642 /* 120019 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40643 /* 120024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40644 /* 120027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40645 /* 120029 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40646 /* 120032 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40647 /* 120035 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40648 /* 120038 */ GIR_RootConstrainSelectedInstOperands,
40649 /* 120039 */ // GIR_Coverage, 4727,
40650 /* 120039 */ GIR_EraseRootFromParent_Done,
40651 /* 120040 */ // Label 1742: @120040
40652 /* 120040 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(120172), // Rule ID 4759 //
40653 /* 120045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
40654 /* 120048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40655 /* 120052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
40656 /* 120056 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40657 /* 120060 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40658 /* 120064 */ // MIs[1] Operand 1
40659 /* 120064 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
40660 /* 120069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40661 /* 120071 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40662 /* 120071 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40663 /* 120074 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
40664 /* 120078 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40665 /* 120083 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40666 /* 120087 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40667 /* 120091 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40668 /* 120093 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
40669 /* 120096 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
40670 /* 120100 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40671 /* 120105 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
40672 /* 120108 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40673 /* 120110 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
40674 /* 120113 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
40675 /* 120117 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40676 /* 120122 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
40677 /* 120125 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
40678 /* 120127 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40679 /* 120130 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40680 /* 120134 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40681 /* 120139 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40682 /* 120146 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40683 /* 120151 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40684 /* 120156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
40685 /* 120159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40686 /* 120161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40687 /* 120164 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
40688 /* 120167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
40689 /* 120170 */ GIR_RootConstrainSelectedInstOperands,
40690 /* 120171 */ // GIR_Coverage, 4759,
40691 /* 120171 */ GIR_EraseRootFromParent_Done,
40692 /* 120172 */ // Label 1743: @120172
40693 /* 120172 */ GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(120264), // Rule ID 2984 //
40694 /* 120177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40695 /* 120180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40696 /* 120184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40697 /* 120188 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40698 /* 120192 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40699 /* 120196 */ // MIs[1] Operand 1
40700 /* 120196 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
40701 /* 120201 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40702 /* 120203 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
40703 /* 120203 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40704 /* 120206 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
40705 /* 120210 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40706 /* 120215 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40707 /* 120219 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40708 /* 120223 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40709 /* 120225 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40710 /* 120228 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40711 /* 120232 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40712 /* 120237 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
40713 /* 120244 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40714 /* 120249 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40715 /* 120254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40716 /* 120257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40717 /* 120259 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40718 /* 120262 */ GIR_RootConstrainSelectedInstOperands,
40719 /* 120263 */ // GIR_Coverage, 2984,
40720 /* 120263 */ GIR_EraseRootFromParent_Done,
40721 /* 120264 */ // Label 1744: @120264
40722 /* 120264 */ GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(120356), // Rule ID 2998 //
40723 /* 120269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40724 /* 120272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40725 /* 120276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40726 /* 120280 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40727 /* 120284 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40728 /* 120288 */ // MIs[1] Operand 1
40729 /* 120288 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
40730 /* 120293 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40731 /* 120295 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
40732 /* 120295 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40733 /* 120298 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
40734 /* 120302 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40735 /* 120307 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40736 /* 120311 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40737 /* 120315 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40738 /* 120317 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40739 /* 120320 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40740 /* 120324 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40741 /* 120329 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
40742 /* 120336 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40743 /* 120341 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40744 /* 120346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40745 /* 120349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40746 /* 120351 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40747 /* 120354 */ GIR_RootConstrainSelectedInstOperands,
40748 /* 120355 */ // GIR_Coverage, 2998,
40749 /* 120355 */ GIR_EraseRootFromParent_Done,
40750 /* 120356 */ // Label 1745: @120356
40751 /* 120356 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(120448), // Rule ID 3006 //
40752 /* 120361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40753 /* 120364 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40754 /* 120368 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40755 /* 120372 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40756 /* 120376 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40757 /* 120380 */ // MIs[1] Operand 1
40758 /* 120380 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
40759 /* 120385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40760 /* 120387 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
40761 /* 120387 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40762 /* 120390 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
40763 /* 120394 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40764 /* 120399 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40765 /* 120403 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40766 /* 120407 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40767 /* 120409 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40768 /* 120412 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40769 /* 120416 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40770 /* 120421 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40771 /* 120428 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40772 /* 120433 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40773 /* 120438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40774 /* 120441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40775 /* 120443 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40776 /* 120446 */ GIR_RootConstrainSelectedInstOperands,
40777 /* 120447 */ // GIR_Coverage, 3006,
40778 /* 120447 */ GIR_EraseRootFromParent_Done,
40779 /* 120448 */ // Label 1746: @120448
40780 /* 120448 */ GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(120540), // Rule ID 3014 //
40781 /* 120453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40782 /* 120456 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40783 /* 120460 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40784 /* 120464 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40785 /* 120468 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40786 /* 120472 */ // MIs[1] Operand 1
40787 /* 120472 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
40788 /* 120477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40789 /* 120479 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
40790 /* 120479 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40791 /* 120482 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
40792 /* 120486 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40793 /* 120491 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40794 /* 120495 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40795 /* 120499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40796 /* 120501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40797 /* 120504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40798 /* 120508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40799 /* 120513 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40800 /* 120520 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40801 /* 120525 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40802 /* 120530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40803 /* 120533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40804 /* 120535 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40805 /* 120538 */ GIR_RootConstrainSelectedInstOperands,
40806 /* 120539 */ // GIR_Coverage, 3014,
40807 /* 120539 */ GIR_EraseRootFromParent_Done,
40808 /* 120540 */ // Label 1747: @120540
40809 /* 120540 */ GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(120632), // Rule ID 3022 //
40810 /* 120545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40811 /* 120548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40812 /* 120552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40813 /* 120556 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40814 /* 120560 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40815 /* 120564 */ // MIs[1] Operand 1
40816 /* 120564 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
40817 /* 120569 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40818 /* 120571 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }))
40819 /* 120571 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40820 /* 120574 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
40821 /* 120578 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40822 /* 120583 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40823 /* 120587 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40824 /* 120591 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40825 /* 120593 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40826 /* 120596 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40827 /* 120600 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40828 /* 120605 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
40829 /* 120612 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40830 /* 120617 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40831 /* 120622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40832 /* 120625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40833 /* 120627 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40834 /* 120630 */ GIR_RootConstrainSelectedInstOperands,
40835 /* 120631 */ // GIR_Coverage, 3022,
40836 /* 120631 */ GIR_EraseRootFromParent_Done,
40837 /* 120632 */ // Label 1748: @120632
40838 /* 120632 */ GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(120724), // Rule ID 3086 //
40839 /* 120637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40840 /* 120640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40841 /* 120644 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40842 /* 120648 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40843 /* 120652 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40844 /* 120656 */ // MIs[1] Operand 1
40845 /* 120656 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
40846 /* 120661 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40847 /* 120663 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
40848 /* 120663 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40849 /* 120666 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
40850 /* 120670 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40851 /* 120675 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40852 /* 120679 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40853 /* 120683 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40854 /* 120685 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40855 /* 120688 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40856 /* 120692 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40857 /* 120697 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
40858 /* 120704 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40859 /* 120709 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40860 /* 120714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40861 /* 120717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40862 /* 120719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40863 /* 120722 */ GIR_RootConstrainSelectedInstOperands,
40864 /* 120723 */ // GIR_Coverage, 3086,
40865 /* 120723 */ GIR_EraseRootFromParent_Done,
40866 /* 120724 */ // Label 1749: @120724
40867 /* 120724 */ GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(120816), // Rule ID 3094 //
40868 /* 120729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40869 /* 120732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40870 /* 120736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40871 /* 120740 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40872 /* 120744 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40873 /* 120748 */ // MIs[1] Operand 1
40874 /* 120748 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
40875 /* 120753 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40876 /* 120755 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
40877 /* 120755 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40878 /* 120758 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
40879 /* 120762 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40880 /* 120767 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40881 /* 120771 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40882 /* 120775 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40883 /* 120777 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40884 /* 120780 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40885 /* 120784 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40886 /* 120789 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
40887 /* 120796 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40888 /* 120801 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40889 /* 120806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40890 /* 120809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40891 /* 120811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40892 /* 120814 */ GIR_RootConstrainSelectedInstOperands,
40893 /* 120815 */ // GIR_Coverage, 3094,
40894 /* 120815 */ GIR_EraseRootFromParent_Done,
40895 /* 120816 */ // Label 1750: @120816
40896 /* 120816 */ GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(120908), // Rule ID 3102 //
40897 /* 120821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40898 /* 120824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40899 /* 120828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40900 /* 120832 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40901 /* 120836 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40902 /* 120840 */ // MIs[1] Operand 1
40903 /* 120840 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
40904 /* 120845 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40905 /* 120847 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
40906 /* 120847 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40907 /* 120850 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
40908 /* 120854 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40909 /* 120859 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40910 /* 120863 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40911 /* 120867 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40912 /* 120869 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40913 /* 120872 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40914 /* 120876 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40915 /* 120881 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40916 /* 120888 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40917 /* 120893 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40918 /* 120898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40919 /* 120901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40920 /* 120903 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40921 /* 120906 */ GIR_RootConstrainSelectedInstOperands,
40922 /* 120907 */ // GIR_Coverage, 3102,
40923 /* 120907 */ GIR_EraseRootFromParent_Done,
40924 /* 120908 */ // Label 1751: @120908
40925 /* 120908 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(121000), // Rule ID 3110 //
40926 /* 120913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40927 /* 120916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40928 /* 120920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40929 /* 120924 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40930 /* 120928 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40931 /* 120932 */ // MIs[1] Operand 1
40932 /* 120932 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
40933 /* 120937 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40934 /* 120939 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
40935 /* 120939 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40936 /* 120942 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
40937 /* 120946 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40938 /* 120951 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40939 /* 120955 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40940 /* 120959 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40941 /* 120961 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40942 /* 120964 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40943 /* 120968 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40944 /* 120973 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
40945 /* 120980 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40946 /* 120985 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40947 /* 120990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40948 /* 120993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40949 /* 120995 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40950 /* 120998 */ GIR_RootConstrainSelectedInstOperands,
40951 /* 120999 */ // GIR_Coverage, 3110,
40952 /* 120999 */ GIR_EraseRootFromParent_Done,
40953 /* 121000 */ // Label 1752: @121000
40954 /* 121000 */ GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(121092), // Rule ID 3118 //
40955 /* 121005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
40956 /* 121008 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40957 /* 121012 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40958 /* 121016 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40959 /* 121020 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40960 /* 121024 */ // MIs[1] Operand 1
40961 /* 121024 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
40962 /* 121029 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40963 /* 121031 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SETNBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }))
40964 /* 121031 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40965 /* 121034 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
40966 /* 121038 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40967 /* 121043 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40968 /* 121047 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40969 /* 121051 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40970 /* 121053 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
40971 /* 121056 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40972 /* 121060 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40973 /* 121065 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
40974 /* 121072 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
40975 /* 121077 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
40976 /* 121082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR),
40977 /* 121085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
40978 /* 121087 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40979 /* 121090 */ GIR_RootConstrainSelectedInstOperands,
40980 /* 121091 */ // GIR_Coverage, 3118,
40981 /* 121091 */ GIR_EraseRootFromParent_Done,
40982 /* 121092 */ // Label 1753: @121092
40983 /* 121092 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(121224), // Rule ID 3868 //
40984 /* 121097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
40985 /* 121100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40986 /* 121104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
40987 /* 121108 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40988 /* 121112 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40989 /* 121116 */ // MIs[1] Operand 1
40990 /* 121116 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
40991 /* 121121 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40992 /* 121123 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
40993 /* 121123 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40994 /* 121126 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
40995 /* 121130 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
40996 /* 121135 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
40997 /* 121139 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
40998 /* 121143 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40999 /* 121145 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41000 /* 121148 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41001 /* 121152 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41002 /* 121157 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41003 /* 121160 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41004 /* 121162 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41005 /* 121165 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41006 /* 121169 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41007 /* 121174 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41008 /* 121177 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41009 /* 121179 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41010 /* 121182 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41011 /* 121186 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41012 /* 121191 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41013 /* 121198 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41014 /* 121203 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41015 /* 121208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41016 /* 121211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41017 /* 121213 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41018 /* 121216 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41019 /* 121219 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41020 /* 121222 */ GIR_RootConstrainSelectedInstOperands,
41021 /* 121223 */ // GIR_Coverage, 3868,
41022 /* 121223 */ GIR_EraseRootFromParent_Done,
41023 /* 121224 */ // Label 1754: @121224
41024 /* 121224 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(121356), // Rule ID 3876 //
41025 /* 121229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41026 /* 121232 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41027 /* 121236 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41028 /* 121240 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41029 /* 121244 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41030 /* 121248 */ // MIs[1] Operand 1
41031 /* 121248 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
41032 /* 121253 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41033 /* 121255 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41034 /* 121255 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41035 /* 121258 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
41036 /* 121262 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41037 /* 121267 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41038 /* 121271 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41039 /* 121275 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41040 /* 121277 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41041 /* 121280 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41042 /* 121284 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41043 /* 121289 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41044 /* 121292 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41045 /* 121294 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41046 /* 121297 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41047 /* 121301 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41048 /* 121306 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41049 /* 121309 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41050 /* 121311 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41051 /* 121314 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41052 /* 121318 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41053 /* 121323 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41054 /* 121330 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41055 /* 121335 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41056 /* 121340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41057 /* 121343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41058 /* 121345 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41059 /* 121348 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41060 /* 121351 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41061 /* 121354 */ GIR_RootConstrainSelectedInstOperands,
41062 /* 121355 */ // GIR_Coverage, 3876,
41063 /* 121355 */ GIR_EraseRootFromParent_Done,
41064 /* 121356 */ // Label 1755: @121356
41065 /* 121356 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(121488), // Rule ID 3884 //
41066 /* 121361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41067 /* 121364 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41068 /* 121368 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41069 /* 121372 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41070 /* 121376 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41071 /* 121380 */ // MIs[1] Operand 1
41072 /* 121380 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
41073 /* 121385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41074 /* 121387 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41075 /* 121387 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41076 /* 121390 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
41077 /* 121394 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41078 /* 121399 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41079 /* 121403 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41080 /* 121407 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41081 /* 121409 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41082 /* 121412 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41083 /* 121416 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41084 /* 121421 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41085 /* 121424 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41086 /* 121426 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41087 /* 121429 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41088 /* 121433 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41089 /* 121438 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41090 /* 121441 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41091 /* 121443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41092 /* 121446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41093 /* 121450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41094 /* 121455 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41095 /* 121462 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41096 /* 121467 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41097 /* 121472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41098 /* 121475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41099 /* 121477 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41100 /* 121480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41101 /* 121483 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41102 /* 121486 */ GIR_RootConstrainSelectedInstOperands,
41103 /* 121487 */ // GIR_Coverage, 3884,
41104 /* 121487 */ GIR_EraseRootFromParent_Done,
41105 /* 121488 */ // Label 1756: @121488
41106 /* 121488 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(121620), // Rule ID 3892 //
41107 /* 121493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41108 /* 121496 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41109 /* 121500 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41110 /* 121504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41111 /* 121508 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41112 /* 121512 */ // MIs[1] Operand 1
41113 /* 121512 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
41114 /* 121517 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41115 /* 121519 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41116 /* 121519 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41117 /* 121522 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
41118 /* 121526 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41119 /* 121531 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41120 /* 121535 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41121 /* 121539 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41122 /* 121541 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41123 /* 121544 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41124 /* 121548 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41125 /* 121553 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41126 /* 121556 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41127 /* 121558 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41128 /* 121561 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41129 /* 121565 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41130 /* 121570 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41131 /* 121573 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41132 /* 121575 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41133 /* 121578 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41134 /* 121582 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41135 /* 121587 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41136 /* 121594 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41137 /* 121599 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41138 /* 121604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41139 /* 121607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41140 /* 121609 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41141 /* 121612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41142 /* 121615 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41143 /* 121618 */ GIR_RootConstrainSelectedInstOperands,
41144 /* 121619 */ // GIR_Coverage, 3892,
41145 /* 121619 */ GIR_EraseRootFromParent_Done,
41146 /* 121620 */ // Label 1757: @121620
41147 /* 121620 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(121752), // Rule ID 3900 //
41148 /* 121625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41149 /* 121628 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41150 /* 121632 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41151 /* 121636 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41152 /* 121640 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41153 /* 121644 */ // MIs[1] Operand 1
41154 /* 121644 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
41155 /* 121649 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41156 /* 121651 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41157 /* 121651 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41158 /* 121654 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
41159 /* 121658 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41160 /* 121663 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41161 /* 121667 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41162 /* 121671 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41163 /* 121673 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41164 /* 121676 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41165 /* 121680 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41166 /* 121685 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41167 /* 121688 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41168 /* 121690 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41169 /* 121693 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41170 /* 121697 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41171 /* 121702 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41172 /* 121705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41173 /* 121707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41174 /* 121710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41175 /* 121714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41176 /* 121719 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
41177 /* 121726 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41178 /* 121731 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41179 /* 121736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41180 /* 121739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41181 /* 121741 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41182 /* 121744 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41183 /* 121747 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41184 /* 121750 */ GIR_RootConstrainSelectedInstOperands,
41185 /* 121751 */ // GIR_Coverage, 3900,
41186 /* 121751 */ GIR_EraseRootFromParent_Done,
41187 /* 121752 */ // Label 1758: @121752
41188 /* 121752 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(121884), // Rule ID 3964 //
41189 /* 121757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41190 /* 121760 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41191 /* 121764 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41192 /* 121768 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41193 /* 121772 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41194 /* 121776 */ // MIs[1] Operand 1
41195 /* 121776 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
41196 /* 121781 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41197 /* 121783 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41198 /* 121783 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41199 /* 121786 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
41200 /* 121790 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41201 /* 121795 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41202 /* 121799 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41203 /* 121803 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41204 /* 121805 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41205 /* 121808 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41206 /* 121812 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41207 /* 121817 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41208 /* 121820 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41209 /* 121822 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41210 /* 121825 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41211 /* 121829 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41212 /* 121834 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41213 /* 121837 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41214 /* 121839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41215 /* 121842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41216 /* 121846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41217 /* 121851 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41218 /* 121858 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41219 /* 121863 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41220 /* 121868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41221 /* 121871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41222 /* 121873 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41223 /* 121876 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41224 /* 121879 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41225 /* 121882 */ GIR_RootConstrainSelectedInstOperands,
41226 /* 121883 */ // GIR_Coverage, 3964,
41227 /* 121883 */ GIR_EraseRootFromParent_Done,
41228 /* 121884 */ // Label 1759: @121884
41229 /* 121884 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(122016), // Rule ID 3972 //
41230 /* 121889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41231 /* 121892 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41232 /* 121896 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41233 /* 121900 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41234 /* 121904 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41235 /* 121908 */ // MIs[1] Operand 1
41236 /* 121908 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
41237 /* 121913 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41238 /* 121915 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41239 /* 121915 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41240 /* 121918 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
41241 /* 121922 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41242 /* 121927 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41243 /* 121931 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41244 /* 121935 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41245 /* 121937 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41246 /* 121940 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41247 /* 121944 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41248 /* 121949 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41249 /* 121952 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41250 /* 121954 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41251 /* 121957 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41252 /* 121961 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41253 /* 121966 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41254 /* 121969 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41255 /* 121971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41256 /* 121974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41257 /* 121978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41258 /* 121983 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41259 /* 121990 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41260 /* 121995 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41261 /* 122000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41262 /* 122003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41263 /* 122005 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41264 /* 122008 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41265 /* 122011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41266 /* 122014 */ GIR_RootConstrainSelectedInstOperands,
41267 /* 122015 */ // GIR_Coverage, 3972,
41268 /* 122015 */ GIR_EraseRootFromParent_Done,
41269 /* 122016 */ // Label 1760: @122016
41270 /* 122016 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(122148), // Rule ID 3980 //
41271 /* 122021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41272 /* 122024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41273 /* 122028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41274 /* 122032 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41275 /* 122036 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41276 /* 122040 */ // MIs[1] Operand 1
41277 /* 122040 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
41278 /* 122045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41279 /* 122047 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41280 /* 122047 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41281 /* 122050 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
41282 /* 122054 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41283 /* 122059 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41284 /* 122063 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41285 /* 122067 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41286 /* 122069 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41287 /* 122072 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41288 /* 122076 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41289 /* 122081 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41290 /* 122084 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41291 /* 122086 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41292 /* 122089 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41293 /* 122093 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41294 /* 122098 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41295 /* 122101 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41296 /* 122103 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41297 /* 122106 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41298 /* 122110 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41299 /* 122115 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41300 /* 122122 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41301 /* 122127 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41302 /* 122132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41303 /* 122135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41304 /* 122137 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41305 /* 122140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41306 /* 122143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41307 /* 122146 */ GIR_RootConstrainSelectedInstOperands,
41308 /* 122147 */ // GIR_Coverage, 3980,
41309 /* 122147 */ GIR_EraseRootFromParent_Done,
41310 /* 122148 */ // Label 1761: @122148
41311 /* 122148 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(122280), // Rule ID 3988 //
41312 /* 122153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41313 /* 122156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41314 /* 122160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41315 /* 122164 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41316 /* 122168 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41317 /* 122172 */ // MIs[1] Operand 1
41318 /* 122172 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
41319 /* 122177 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41320 /* 122179 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41321 /* 122179 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41322 /* 122182 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
41323 /* 122186 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41324 /* 122191 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41325 /* 122195 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41326 /* 122199 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41327 /* 122201 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41328 /* 122204 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41329 /* 122208 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41330 /* 122213 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41331 /* 122216 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41332 /* 122218 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41333 /* 122221 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41334 /* 122225 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41335 /* 122230 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41336 /* 122233 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41337 /* 122235 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41338 /* 122238 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41339 /* 122242 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41340 /* 122247 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41341 /* 122254 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41342 /* 122259 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41343 /* 122264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41344 /* 122267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41345 /* 122269 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41346 /* 122272 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41347 /* 122275 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41348 /* 122278 */ GIR_RootConstrainSelectedInstOperands,
41349 /* 122279 */ // GIR_Coverage, 3988,
41350 /* 122279 */ GIR_EraseRootFromParent_Done,
41351 /* 122280 */ // Label 1762: @122280
41352 /* 122280 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(122412), // Rule ID 3996 //
41353 /* 122285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41354 /* 122288 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41355 /* 122292 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41356 /* 122296 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41357 /* 122300 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41358 /* 122304 */ // MIs[1] Operand 1
41359 /* 122304 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
41360 /* 122309 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41361 /* 122311 */ // (sext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } -1:{ *:[i32] }))
41362 /* 122311 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41363 /* 122314 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
41364 /* 122318 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41365 /* 122323 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41366 /* 122327 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41367 /* 122331 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41368 /* 122333 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41369 /* 122336 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
41370 /* 122340 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41371 /* 122345 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41372 /* 122348 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41373 /* 122350 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
41374 /* 122353 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
41375 /* 122357 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41376 /* 122362 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41377 /* 122365 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41378 /* 122367 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41379 /* 122370 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41380 /* 122374 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41381 /* 122379 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
41382 /* 122386 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41383 /* 122391 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41384 /* 122396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41385 /* 122399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41386 /* 122401 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41387 /* 122404 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41388 /* 122407 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41389 /* 122410 */ GIR_RootConstrainSelectedInstOperands,
41390 /* 122411 */ // GIR_Coverage, 3996,
41391 /* 122411 */ GIR_EraseRootFromParent_Done,
41392 /* 122412 */ // Label 1763: @122412
41393 /* 122412 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(122427), // Rule ID 2990 //
41394 /* 122417 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
41395 /* 122420 */ // (sext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SETNBC:{ *:[i32] } ?:{ *:[i1] }:$in)
41396 /* 122420 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETNBC),
41397 /* 122425 */ GIR_RootConstrainSelectedInstOperands,
41398 /* 122426 */ // GIR_Coverage, 2990,
41399 /* 122426 */ GIR_Done,
41400 /* 122427 */ // Label 1764: @122427
41401 /* 122427 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(122481), // Rule ID 3674 //
41402 /* 122432 */ // (sext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SELECT_I4:{ *:[i32] } ?:{ *:[i1] }:$in, (LI:{ *:[i32] } -1:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }))
41403 /* 122432 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41404 /* 122435 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI),
41405 /* 122439 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41406 /* 122444 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
41407 /* 122447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41408 /* 122449 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41409 /* 122452 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI),
41410 /* 122456 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41411 /* 122461 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/uint8_t(-1),
41412 /* 122464 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41413 /* 122466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
41414 /* 122469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41415 /* 122471 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
41416 /* 122473 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41417 /* 122476 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
41418 /* 122479 */ GIR_RootConstrainSelectedInstOperands,
41419 /* 122480 */ // GIR_Coverage, 3674,
41420 /* 122480 */ GIR_EraseRootFromParent_Done,
41421 /* 122481 */ // Label 1765: @122481
41422 /* 122481 */ GIM_Reject,
41423 /* 122482 */ // Label 1701: @122482
41424 /* 122482 */ GIM_Reject,
41425 /* 122483 */ // Label 1699: @122483
41426 /* 122483 */ GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(122593), // Rule ID 3039 //
41427 /* 122488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
41428 /* 122491 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41429 /* 122494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41430 /* 122498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41431 /* 122502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41432 /* 122506 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41433 /* 122510 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41434 /* 122514 */ // MIs[1] Operand 1
41435 /* 122514 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
41436 /* 122519 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41437 /* 122523 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41438 /* 122527 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
41439 /* 122531 */ // MIs[2] Operand 1
41440 /* 122531 */ // No operand predicates
41441 /* 122531 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41442 /* 122533 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }))
41443 /* 122533 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41444 /* 122536 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
41445 /* 122540 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41446 /* 122545 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41447 /* 122549 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41448 /* 122552 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41449 /* 122554 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41450 /* 122557 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41451 /* 122561 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41452 /* 122566 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41453 /* 122573 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41454 /* 122578 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41455 /* 122583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
41456 /* 122586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
41457 /* 122588 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41458 /* 122591 */ GIR_RootConstrainSelectedInstOperands,
41459 /* 122592 */ // GIR_Coverage, 3039,
41460 /* 122592 */ GIR_EraseRootFromParent_Done,
41461 /* 122593 */ // Label 1766: @122593
41462 /* 122593 */ GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(122703), // Rule ID 3055 //
41463 /* 122598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
41464 /* 122601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41465 /* 122604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41466 /* 122608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41467 /* 122612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41468 /* 122616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41469 /* 122620 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41470 /* 122624 */ // MIs[1] Operand 1
41471 /* 122624 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
41472 /* 122629 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41473 /* 122633 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41474 /* 122637 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
41475 /* 122641 */ // MIs[2] Operand 1
41476 /* 122641 */ // No operand predicates
41477 /* 122641 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41478 /* 122643 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }))
41479 /* 122643 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41480 /* 122646 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
41481 /* 122650 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41482 /* 122655 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41483 /* 122659 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41484 /* 122662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41485 /* 122664 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41486 /* 122667 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41487 /* 122671 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41488 /* 122676 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41489 /* 122683 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41490 /* 122688 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41491 /* 122693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
41492 /* 122696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
41493 /* 122698 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41494 /* 122701 */ GIR_RootConstrainSelectedInstOperands,
41495 /* 122702 */ // GIR_Coverage, 3055,
41496 /* 122702 */ GIR_EraseRootFromParent_Done,
41497 /* 122703 */ // Label 1767: @122703
41498 /* 122703 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(122813), // Rule ID 3063 //
41499 /* 122708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
41500 /* 122711 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41501 /* 122714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41502 /* 122718 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41503 /* 122722 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41504 /* 122726 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41505 /* 122730 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41506 /* 122734 */ // MIs[1] Operand 1
41507 /* 122734 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
41508 /* 122739 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41509 /* 122743 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41510 /* 122747 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
41511 /* 122751 */ // MIs[2] Operand 1
41512 /* 122751 */ // No operand predicates
41513 /* 122751 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41514 /* 122753 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }))
41515 /* 122753 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41516 /* 122756 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
41517 /* 122760 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41518 /* 122765 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41519 /* 122769 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41520 /* 122772 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41521 /* 122774 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41522 /* 122777 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41523 /* 122781 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41524 /* 122786 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
41525 /* 122793 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41526 /* 122798 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41527 /* 122803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
41528 /* 122806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
41529 /* 122808 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41530 /* 122811 */ GIR_RootConstrainSelectedInstOperands,
41531 /* 122812 */ // GIR_Coverage, 3063,
41532 /* 122812 */ GIR_EraseRootFromParent_Done,
41533 /* 122813 */ // Label 1768: @122813
41534 /* 122813 */ GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(122923), // Rule ID 3135 //
41535 /* 122818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
41536 /* 122821 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41537 /* 122824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41538 /* 122828 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41539 /* 122832 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41540 /* 122836 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41541 /* 122840 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41542 /* 122844 */ // MIs[1] Operand 1
41543 /* 122844 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
41544 /* 122849 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41545 /* 122853 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41546 /* 122857 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
41547 /* 122861 */ // MIs[2] Operand 1
41548 /* 122861 */ // No operand predicates
41549 /* 122861 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41550 /* 122863 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }))
41551 /* 122863 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41552 /* 122866 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
41553 /* 122870 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41554 /* 122875 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41555 /* 122879 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41556 /* 122882 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41557 /* 122884 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41558 /* 122887 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41559 /* 122891 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41560 /* 122896 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41561 /* 122903 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41562 /* 122908 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41563 /* 122913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
41564 /* 122916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
41565 /* 122918 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41566 /* 122921 */ GIR_RootConstrainSelectedInstOperands,
41567 /* 122922 */ // GIR_Coverage, 3135,
41568 /* 122922 */ GIR_EraseRootFromParent_Done,
41569 /* 122923 */ // Label 1769: @122923
41570 /* 122923 */ GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(123033), // Rule ID 3151 //
41571 /* 122928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
41572 /* 122931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41573 /* 122934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41574 /* 122938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41575 /* 122942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41576 /* 122946 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41577 /* 122950 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41578 /* 122954 */ // MIs[1] Operand 1
41579 /* 122954 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
41580 /* 122959 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41581 /* 122963 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41582 /* 122967 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
41583 /* 122971 */ // MIs[2] Operand 1
41584 /* 122971 */ // No operand predicates
41585 /* 122971 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41586 /* 122973 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }))
41587 /* 122973 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41588 /* 122976 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
41589 /* 122980 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41590 /* 122985 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41591 /* 122989 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41592 /* 122992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41593 /* 122994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41594 /* 122997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41595 /* 123001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41596 /* 123006 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41597 /* 123013 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41598 /* 123018 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41599 /* 123023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
41600 /* 123026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
41601 /* 123028 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41602 /* 123031 */ GIR_RootConstrainSelectedInstOperands,
41603 /* 123032 */ // GIR_Coverage, 3151,
41604 /* 123032 */ GIR_EraseRootFromParent_Done,
41605 /* 123033 */ // Label 1770: @123033
41606 /* 123033 */ GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(123143), // Rule ID 3159 //
41607 /* 123038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
41608 /* 123041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41609 /* 123044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41610 /* 123048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41611 /* 123052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41612 /* 123056 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41613 /* 123060 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41614 /* 123064 */ // MIs[1] Operand 1
41615 /* 123064 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
41616 /* 123069 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41617 /* 123073 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41618 /* 123077 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
41619 /* 123081 */ // MIs[2] Operand 1
41620 /* 123081 */ // No operand predicates
41621 /* 123081 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41622 /* 123083 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }))
41623 /* 123083 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41624 /* 123086 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
41625 /* 123090 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41626 /* 123095 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41627 /* 123099 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41628 /* 123102 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41629 /* 123104 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41630 /* 123107 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41631 /* 123111 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41632 /* 123116 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
41633 /* 123123 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41634 /* 123128 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41635 /* 123133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
41636 /* 123136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
41637 /* 123138 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41638 /* 123141 */ GIR_RootConstrainSelectedInstOperands,
41639 /* 123142 */ // GIR_Coverage, 3159,
41640 /* 123142 */ GIR_EraseRootFromParent_Done,
41641 /* 123143 */ // Label 1771: @123143
41642 /* 123143 */ GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(123293), // Rule ID 3822 //
41643 /* 123148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41644 /* 123151 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41645 /* 123154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41646 /* 123158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41647 /* 123162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41648 /* 123166 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41649 /* 123170 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41650 /* 123174 */ // MIs[1] Operand 1
41651 /* 123174 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
41652 /* 123179 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41653 /* 123183 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41654 /* 123187 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
41655 /* 123191 */ // MIs[2] Operand 1
41656 /* 123191 */ // No operand predicates
41657 /* 123191 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41658 /* 123193 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
41659 /* 123193 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41660 /* 123196 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
41661 /* 123200 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41662 /* 123205 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41663 /* 123209 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41664 /* 123212 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41665 /* 123214 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
41666 /* 123217 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
41667 /* 123221 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41668 /* 123226 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41669 /* 123229 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41670 /* 123231 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
41671 /* 123234 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
41672 /* 123238 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41673 /* 123243 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41674 /* 123246 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41675 /* 123248 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41676 /* 123251 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41677 /* 123255 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41678 /* 123260 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41679 /* 123267 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41680 /* 123272 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41681 /* 123277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
41682 /* 123280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41683 /* 123282 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41684 /* 123285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41685 /* 123288 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41686 /* 123291 */ GIR_RootConstrainSelectedInstOperands,
41687 /* 123292 */ // GIR_Coverage, 3822,
41688 /* 123292 */ GIR_EraseRootFromParent_Done,
41689 /* 123293 */ // Label 1772: @123293
41690 /* 123293 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(123443), // Rule ID 3838 //
41691 /* 123298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41692 /* 123301 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41693 /* 123304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41694 /* 123308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41695 /* 123312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41696 /* 123316 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41697 /* 123320 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41698 /* 123324 */ // MIs[1] Operand 1
41699 /* 123324 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
41700 /* 123329 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41701 /* 123333 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41702 /* 123337 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
41703 /* 123341 */ // MIs[2] Operand 1
41704 /* 123341 */ // No operand predicates
41705 /* 123341 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41706 /* 123343 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
41707 /* 123343 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41708 /* 123346 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
41709 /* 123350 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41710 /* 123355 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41711 /* 123359 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41712 /* 123362 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41713 /* 123364 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
41714 /* 123367 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
41715 /* 123371 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41716 /* 123376 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41717 /* 123379 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41718 /* 123381 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
41719 /* 123384 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
41720 /* 123388 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41721 /* 123393 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41722 /* 123396 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41723 /* 123398 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41724 /* 123401 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41725 /* 123405 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41726 /* 123410 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41727 /* 123417 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41728 /* 123422 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41729 /* 123427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
41730 /* 123430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41731 /* 123432 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41732 /* 123435 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41733 /* 123438 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41734 /* 123441 */ GIR_RootConstrainSelectedInstOperands,
41735 /* 123442 */ // GIR_Coverage, 3838,
41736 /* 123442 */ GIR_EraseRootFromParent_Done,
41737 /* 123443 */ // Label 1773: @123443
41738 /* 123443 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(123593), // Rule ID 3846 //
41739 /* 123448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41740 /* 123451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41741 /* 123454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41742 /* 123458 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41743 /* 123462 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41744 /* 123466 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41745 /* 123470 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41746 /* 123474 */ // MIs[1] Operand 1
41747 /* 123474 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
41748 /* 123479 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41749 /* 123483 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41750 /* 123487 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
41751 /* 123491 */ // MIs[2] Operand 1
41752 /* 123491 */ // No operand predicates
41753 /* 123491 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41754 /* 123493 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
41755 /* 123493 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41756 /* 123496 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
41757 /* 123500 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41758 /* 123505 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41759 /* 123509 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41760 /* 123512 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41761 /* 123514 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
41762 /* 123517 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
41763 /* 123521 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41764 /* 123526 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41765 /* 123529 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41766 /* 123531 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
41767 /* 123534 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
41768 /* 123538 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41769 /* 123543 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41770 /* 123546 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41771 /* 123548 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41772 /* 123551 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41773 /* 123555 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41774 /* 123560 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
41775 /* 123567 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41776 /* 123572 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41777 /* 123577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
41778 /* 123580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41779 /* 123582 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41780 /* 123585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41781 /* 123588 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41782 /* 123591 */ GIR_RootConstrainSelectedInstOperands,
41783 /* 123592 */ // GIR_Coverage, 3846,
41784 /* 123592 */ GIR_EraseRootFromParent_Done,
41785 /* 123593 */ // Label 1774: @123593
41786 /* 123593 */ GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(123743), // Rule ID 3918 //
41787 /* 123598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41788 /* 123601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41789 /* 123604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41790 /* 123608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41791 /* 123612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41792 /* 123616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41793 /* 123620 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41794 /* 123624 */ // MIs[1] Operand 1
41795 /* 123624 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
41796 /* 123629 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41797 /* 123633 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41798 /* 123637 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
41799 /* 123641 */ // MIs[2] Operand 1
41800 /* 123641 */ // No operand predicates
41801 /* 123641 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41802 /* 123643 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
41803 /* 123643 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41804 /* 123646 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
41805 /* 123650 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41806 /* 123655 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41807 /* 123659 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41808 /* 123662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41809 /* 123664 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
41810 /* 123667 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
41811 /* 123671 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41812 /* 123676 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41813 /* 123679 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41814 /* 123681 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
41815 /* 123684 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
41816 /* 123688 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41817 /* 123693 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41818 /* 123696 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41819 /* 123698 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41820 /* 123701 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41821 /* 123705 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41822 /* 123710 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41823 /* 123717 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41824 /* 123722 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41825 /* 123727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
41826 /* 123730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41827 /* 123732 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41828 /* 123735 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41829 /* 123738 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41830 /* 123741 */ GIR_RootConstrainSelectedInstOperands,
41831 /* 123742 */ // GIR_Coverage, 3918,
41832 /* 123742 */ GIR_EraseRootFromParent_Done,
41833 /* 123743 */ // Label 1775: @123743
41834 /* 123743 */ GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(123893), // Rule ID 3934 //
41835 /* 123748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41836 /* 123751 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41837 /* 123754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41838 /* 123758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41839 /* 123762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41840 /* 123766 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41841 /* 123770 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41842 /* 123774 */ // MIs[1] Operand 1
41843 /* 123774 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
41844 /* 123779 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41845 /* 123783 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41846 /* 123787 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
41847 /* 123791 */ // MIs[2] Operand 1
41848 /* 123791 */ // No operand predicates
41849 /* 123791 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41850 /* 123793 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
41851 /* 123793 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41852 /* 123796 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
41853 /* 123800 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41854 /* 123805 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41855 /* 123809 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41856 /* 123812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41857 /* 123814 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
41858 /* 123817 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
41859 /* 123821 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41860 /* 123826 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41861 /* 123829 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41862 /* 123831 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
41863 /* 123834 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
41864 /* 123838 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41865 /* 123843 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41866 /* 123846 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41867 /* 123848 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41868 /* 123851 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41869 /* 123855 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41870 /* 123860 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41871 /* 123867 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41872 /* 123872 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41873 /* 123877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
41874 /* 123880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41875 /* 123882 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41876 /* 123885 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41877 /* 123888 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41878 /* 123891 */ GIR_RootConstrainSelectedInstOperands,
41879 /* 123892 */ // GIR_Coverage, 3934,
41880 /* 123892 */ GIR_EraseRootFromParent_Done,
41881 /* 123893 */ // Label 1776: @123893
41882 /* 123893 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(124043), // Rule ID 3942 //
41883 /* 123898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
41884 /* 123901 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41885 /* 123904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41886 /* 123908 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41887 /* 123912 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
41888 /* 123916 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41889 /* 123920 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41890 /* 123924 */ // MIs[1] Operand 1
41891 /* 123924 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
41892 /* 123929 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
41893 /* 123933 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
41894 /* 123937 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
41895 /* 123941 */ // MIs[2] Operand 1
41896 /* 123941 */ // No operand predicates
41897 /* 123941 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
41898 /* 123943 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
41899 /* 123943 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41900 /* 123946 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
41901 /* 123950 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41902 /* 123955 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41903 /* 123959 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
41904 /* 123962 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41905 /* 123964 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
41906 /* 123967 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
41907 /* 123971 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41908 /* 123976 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
41909 /* 123979 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41910 /* 123981 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
41911 /* 123984 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
41912 /* 123988 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41913 /* 123993 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
41914 /* 123996 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41915 /* 123998 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41916 /* 124001 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41917 /* 124005 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41918 /* 124010 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
41919 /* 124017 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41920 /* 124022 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41921 /* 124027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
41922 /* 124030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41923 /* 124032 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41924 /* 124035 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
41925 /* 124038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
41926 /* 124041 */ GIR_RootConstrainSelectedInstOperands,
41927 /* 124042 */ // GIR_Coverage, 3942,
41928 /* 124042 */ GIR_EraseRootFromParent_Done,
41929 /* 124043 */ // Label 1777: @124043
41930 /* 124043 */ GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(124142), // Rule ID 3183 //
41931 /* 124048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
41932 /* 124051 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41933 /* 124054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41934 /* 124058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41935 /* 124062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
41936 /* 124066 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41937 /* 124070 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41938 /* 124074 */ // MIs[1] Operand 1
41939 /* 124074 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
41940 /* 124079 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41941 /* 124081 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }))
41942 /* 124081 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41943 /* 124084 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
41944 /* 124088 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41945 /* 124093 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41946 /* 124097 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41947 /* 124101 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41948 /* 124103 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41949 /* 124106 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41950 /* 124110 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41951 /* 124115 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
41952 /* 124122 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41953 /* 124127 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41954 /* 124132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
41955 /* 124135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
41956 /* 124137 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41957 /* 124140 */ GIR_RootConstrainSelectedInstOperands,
41958 /* 124141 */ // GIR_Coverage, 3183,
41959 /* 124141 */ GIR_EraseRootFromParent_Done,
41960 /* 124142 */ // Label 1778: @124142
41961 /* 124142 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(124241), // Rule ID 3199 //
41962 /* 124147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
41963 /* 124150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41964 /* 124153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41965 /* 124157 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41966 /* 124161 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
41967 /* 124165 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41968 /* 124169 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41969 /* 124173 */ // MIs[1] Operand 1
41970 /* 124173 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
41971 /* 124178 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41972 /* 124180 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
41973 /* 124180 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
41974 /* 124183 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
41975 /* 124187 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41976 /* 124192 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
41977 /* 124196 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
41978 /* 124200 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41979 /* 124202 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
41980 /* 124205 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41981 /* 124209 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41982 /* 124214 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
41983 /* 124221 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
41984 /* 124226 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
41985 /* 124231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
41986 /* 124234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
41987 /* 124236 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41988 /* 124239 */ GIR_RootConstrainSelectedInstOperands,
41989 /* 124240 */ // GIR_Coverage, 3199,
41990 /* 124240 */ GIR_EraseRootFromParent_Done,
41991 /* 124241 */ // Label 1779: @124241
41992 /* 124241 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(124340), // Rule ID 3215 //
41993 /* 124246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
41994 /* 124249 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
41995 /* 124252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
41996 /* 124256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41997 /* 124260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
41998 /* 124264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41999 /* 124268 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42000 /* 124272 */ // MIs[1] Operand 1
42001 /* 124272 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
42002 /* 124277 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42003 /* 124279 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }))
42004 /* 124279 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42005 /* 124282 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
42006 /* 124286 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42007 /* 124291 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42008 /* 124295 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42009 /* 124299 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42010 /* 124301 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42011 /* 124304 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42012 /* 124308 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42013 /* 124313 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
42014 /* 124320 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42015 /* 124325 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42016 /* 124330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42017 /* 124333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42018 /* 124335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42019 /* 124338 */ GIR_RootConstrainSelectedInstOperands,
42020 /* 124339 */ // GIR_Coverage, 3215,
42021 /* 124339 */ GIR_EraseRootFromParent_Done,
42022 /* 124340 */ // Label 1780: @124340
42023 /* 124340 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(124439), // Rule ID 3231 //
42024 /* 124345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42025 /* 124348 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42026 /* 124351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42027 /* 124355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42028 /* 124359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42029 /* 124363 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42030 /* 124367 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42031 /* 124371 */ // MIs[1] Operand 1
42032 /* 124371 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
42033 /* 124376 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42034 /* 124378 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }))
42035 /* 124378 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42036 /* 124381 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
42037 /* 124385 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42038 /* 124390 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42039 /* 124394 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42040 /* 124398 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42041 /* 124400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42042 /* 124403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42043 /* 124407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42044 /* 124412 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
42045 /* 124419 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42046 /* 124424 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42047 /* 124429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42048 /* 124432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42049 /* 124434 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42050 /* 124437 */ GIR_RootConstrainSelectedInstOperands,
42051 /* 124438 */ // GIR_Coverage, 3231,
42052 /* 124438 */ GIR_EraseRootFromParent_Done,
42053 /* 124439 */ // Label 1781: @124439
42054 /* 124439 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(124538), // Rule ID 3239 //
42055 /* 124444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42056 /* 124447 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42057 /* 124450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42058 /* 124454 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42059 /* 124458 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42060 /* 124462 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42061 /* 124466 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42062 /* 124470 */ // MIs[1] Operand 1
42063 /* 124470 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
42064 /* 124475 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42065 /* 124477 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }))
42066 /* 124477 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42067 /* 124480 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
42068 /* 124484 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42069 /* 124489 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42070 /* 124493 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42071 /* 124497 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42072 /* 124499 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42073 /* 124502 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42074 /* 124506 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42075 /* 124511 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
42076 /* 124518 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42077 /* 124523 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42078 /* 124528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42079 /* 124531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42080 /* 124533 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42081 /* 124536 */ GIR_RootConstrainSelectedInstOperands,
42082 /* 124537 */ // GIR_Coverage, 3239,
42083 /* 124537 */ GIR_EraseRootFromParent_Done,
42084 /* 124538 */ // Label 1782: @124538
42085 /* 124538 */ GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(124637), // Rule ID 3255 //
42086 /* 124543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42087 /* 124546 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42088 /* 124549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42089 /* 124553 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42090 /* 124557 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42091 /* 124561 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42092 /* 124565 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42093 /* 124569 */ // MIs[1] Operand 1
42094 /* 124569 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
42095 /* 124574 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42096 /* 124576 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
42097 /* 124576 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42098 /* 124579 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
42099 /* 124583 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42100 /* 124588 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42101 /* 124592 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42102 /* 124596 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42103 /* 124598 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42104 /* 124601 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42105 /* 124605 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42106 /* 124610 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42107 /* 124617 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42108 /* 124622 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42109 /* 124627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42110 /* 124630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42111 /* 124632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42112 /* 124635 */ GIR_RootConstrainSelectedInstOperands,
42113 /* 124636 */ // GIR_Coverage, 3255,
42114 /* 124636 */ GIR_EraseRootFromParent_Done,
42115 /* 124637 */ // Label 1783: @124637
42116 /* 124637 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(124736), // Rule ID 3271 //
42117 /* 124642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42118 /* 124645 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42119 /* 124648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42120 /* 124652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42121 /* 124656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42122 /* 124660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42123 /* 124664 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42124 /* 124668 */ // MIs[1] Operand 1
42125 /* 124668 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
42126 /* 124673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42127 /* 124675 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }))
42128 /* 124675 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42129 /* 124678 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
42130 /* 124682 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42131 /* 124687 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42132 /* 124691 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42133 /* 124695 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42134 /* 124697 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42135 /* 124700 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42136 /* 124704 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42137 /* 124709 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
42138 /* 124716 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42139 /* 124721 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42140 /* 124726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42141 /* 124729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42142 /* 124731 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42143 /* 124734 */ GIR_RootConstrainSelectedInstOperands,
42144 /* 124735 */ // GIR_Coverage, 3271,
42145 /* 124735 */ GIR_EraseRootFromParent_Done,
42146 /* 124736 */ // Label 1784: @124736
42147 /* 124736 */ GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(124835), // Rule ID 3287 //
42148 /* 124741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42149 /* 124744 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42150 /* 124747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42151 /* 124751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42152 /* 124755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42153 /* 124759 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42154 /* 124763 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42155 /* 124767 */ // MIs[1] Operand 1
42156 /* 124767 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
42157 /* 124772 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42158 /* 124774 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }))
42159 /* 124774 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42160 /* 124777 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
42161 /* 124781 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42162 /* 124786 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42163 /* 124790 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42164 /* 124794 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42165 /* 124796 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42166 /* 124799 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42167 /* 124803 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42168 /* 124808 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
42169 /* 124815 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42170 /* 124820 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42171 /* 124825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42172 /* 124828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42173 /* 124830 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42174 /* 124833 */ GIR_RootConstrainSelectedInstOperands,
42175 /* 124834 */ // GIR_Coverage, 3287,
42176 /* 124834 */ GIR_EraseRootFromParent_Done,
42177 /* 124835 */ // Label 1785: @124835
42178 /* 124835 */ GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(124934), // Rule ID 3295 //
42179 /* 124840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42180 /* 124843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42181 /* 124846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42182 /* 124850 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42183 /* 124854 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42184 /* 124858 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
42185 /* 124862 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
42186 /* 124866 */ // MIs[1] Operand 1
42187 /* 124866 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
42188 /* 124871 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42189 /* 124873 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }))
42190 /* 124873 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42191 /* 124876 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
42192 /* 124880 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42193 /* 124885 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42194 /* 124889 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42195 /* 124893 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42196 /* 124895 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42197 /* 124898 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42198 /* 124902 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42199 /* 124907 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
42200 /* 124914 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42201 /* 124919 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42202 /* 124924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42203 /* 124927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42204 /* 124929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42205 /* 124932 */ GIR_RootConstrainSelectedInstOperands,
42206 /* 124933 */ // GIR_Coverage, 3295,
42207 /* 124933 */ GIR_EraseRootFromParent_Done,
42208 /* 124934 */ // Label 1786: @124934
42209 /* 124934 */ GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(125033), // Rule ID 3311 //
42210 /* 124939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42211 /* 124942 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42212 /* 124945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42213 /* 124949 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42214 /* 124953 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42215 /* 124957 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
42216 /* 124961 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
42217 /* 124965 */ // MIs[1] Operand 1
42218 /* 124965 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
42219 /* 124970 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42220 /* 124972 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }))
42221 /* 124972 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42222 /* 124975 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
42223 /* 124979 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42224 /* 124984 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42225 /* 124988 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42226 /* 124992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42227 /* 124994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42228 /* 124997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42229 /* 125001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42230 /* 125006 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42231 /* 125013 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42232 /* 125018 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42233 /* 125023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42234 /* 125026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42235 /* 125028 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42236 /* 125031 */ GIR_RootConstrainSelectedInstOperands,
42237 /* 125032 */ // GIR_Coverage, 3311,
42238 /* 125032 */ GIR_EraseRootFromParent_Done,
42239 /* 125033 */ // Label 1787: @125033
42240 /* 125033 */ GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(125132), // Rule ID 3327 //
42241 /* 125038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42242 /* 125041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42243 /* 125044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42244 /* 125048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42245 /* 125052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42246 /* 125056 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
42247 /* 125060 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
42248 /* 125064 */ // MIs[1] Operand 1
42249 /* 125064 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
42250 /* 125069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42251 /* 125071 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }))
42252 /* 125071 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42253 /* 125074 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
42254 /* 125078 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42255 /* 125083 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42256 /* 125087 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42257 /* 125091 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42258 /* 125093 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42259 /* 125096 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42260 /* 125100 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42261 /* 125105 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
42262 /* 125112 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42263 /* 125117 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42264 /* 125122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42265 /* 125125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42266 /* 125127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42267 /* 125130 */ GIR_RootConstrainSelectedInstOperands,
42268 /* 125131 */ // GIR_Coverage, 3327,
42269 /* 125131 */ GIR_EraseRootFromParent_Done,
42270 /* 125132 */ // Label 1788: @125132
42271 /* 125132 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(125231), // Rule ID 3343 //
42272 /* 125137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
42273 /* 125140 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42274 /* 125143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42275 /* 125147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42276 /* 125151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42277 /* 125155 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
42278 /* 125159 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
42279 /* 125163 */ // MIs[1] Operand 1
42280 /* 125163 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
42281 /* 125168 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42282 /* 125170 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }))
42283 /* 125170 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42284 /* 125173 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
42285 /* 125177 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42286 /* 125182 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42287 /* 125186 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42288 /* 125190 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42289 /* 125192 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42290 /* 125195 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42291 /* 125199 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42292 /* 125204 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
42293 /* 125211 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42294 /* 125216 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42295 /* 125221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
42296 /* 125224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
42297 /* 125226 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42298 /* 125229 */ GIR_RootConstrainSelectedInstOperands,
42299 /* 125230 */ // GIR_Coverage, 3343,
42300 /* 125230 */ GIR_EraseRootFromParent_Done,
42301 /* 125231 */ // Label 1789: @125231
42302 /* 125231 */ GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(125370), // Rule ID 4026 //
42303 /* 125236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42304 /* 125239 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42305 /* 125242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42306 /* 125246 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42307 /* 125250 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42308 /* 125254 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42309 /* 125258 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42310 /* 125262 */ // MIs[1] Operand 1
42311 /* 125262 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
42312 /* 125267 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42313 /* 125269 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42314 /* 125269 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42315 /* 125272 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
42316 /* 125276 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42317 /* 125281 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42318 /* 125285 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42319 /* 125289 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42320 /* 125291 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42321 /* 125294 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42322 /* 125298 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42323 /* 125303 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42324 /* 125306 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42325 /* 125308 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42326 /* 125311 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42327 /* 125315 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42328 /* 125320 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42329 /* 125323 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42330 /* 125325 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42331 /* 125328 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42332 /* 125332 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42333 /* 125337 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
42334 /* 125344 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42335 /* 125349 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42336 /* 125354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42337 /* 125357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42338 /* 125359 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42339 /* 125362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42340 /* 125365 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42341 /* 125368 */ GIR_RootConstrainSelectedInstOperands,
42342 /* 125369 */ // GIR_Coverage, 4026,
42343 /* 125369 */ GIR_EraseRootFromParent_Done,
42344 /* 125370 */ // Label 1790: @125370
42345 /* 125370 */ GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(125509), // Rule ID 4058 //
42346 /* 125375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42347 /* 125378 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42348 /* 125381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42349 /* 125385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42350 /* 125389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42351 /* 125393 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42352 /* 125397 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42353 /* 125401 */ // MIs[1] Operand 1
42354 /* 125401 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
42355 /* 125406 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42356 /* 125408 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42357 /* 125408 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42358 /* 125411 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
42359 /* 125415 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42360 /* 125420 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42361 /* 125424 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42362 /* 125428 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42363 /* 125430 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42364 /* 125433 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42365 /* 125437 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42366 /* 125442 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42367 /* 125445 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42368 /* 125447 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42369 /* 125450 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42370 /* 125454 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42371 /* 125459 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42372 /* 125462 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42373 /* 125464 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42374 /* 125467 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42375 /* 125471 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42376 /* 125476 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42377 /* 125483 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42378 /* 125488 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42379 /* 125493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42380 /* 125496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42381 /* 125498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42382 /* 125501 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42383 /* 125504 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42384 /* 125507 */ GIR_RootConstrainSelectedInstOperands,
42385 /* 125508 */ // GIR_Coverage, 4058,
42386 /* 125508 */ GIR_EraseRootFromParent_Done,
42387 /* 125509 */ // Label 1791: @125509
42388 /* 125509 */ GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(125648), // Rule ID 4090 //
42389 /* 125514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42390 /* 125517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42391 /* 125520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42392 /* 125524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42393 /* 125528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42394 /* 125532 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42395 /* 125536 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42396 /* 125540 */ // MIs[1] Operand 1
42397 /* 125540 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
42398 /* 125545 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42399 /* 125547 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42400 /* 125547 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42401 /* 125550 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
42402 /* 125554 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42403 /* 125559 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42404 /* 125563 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42405 /* 125567 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42406 /* 125569 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42407 /* 125572 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42408 /* 125576 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42409 /* 125581 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42410 /* 125584 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42411 /* 125586 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42412 /* 125589 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42413 /* 125593 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42414 /* 125598 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42415 /* 125601 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42416 /* 125603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42417 /* 125606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42418 /* 125610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42419 /* 125615 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
42420 /* 125622 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42421 /* 125627 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42422 /* 125632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42423 /* 125635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42424 /* 125637 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42425 /* 125640 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42426 /* 125643 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42427 /* 125646 */ GIR_RootConstrainSelectedInstOperands,
42428 /* 125647 */ // GIR_Coverage, 4090,
42429 /* 125647 */ GIR_EraseRootFromParent_Done,
42430 /* 125648 */ // Label 1792: @125648
42431 /* 125648 */ GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(125787), // Rule ID 4122 //
42432 /* 125653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42433 /* 125656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42434 /* 125659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42435 /* 125663 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42436 /* 125667 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42437 /* 125671 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42438 /* 125675 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42439 /* 125679 */ // MIs[1] Operand 1
42440 /* 125679 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
42441 /* 125684 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42442 /* 125686 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42443 /* 125686 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42444 /* 125689 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
42445 /* 125693 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42446 /* 125698 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42447 /* 125702 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42448 /* 125706 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42449 /* 125708 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42450 /* 125711 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42451 /* 125715 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42452 /* 125720 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42453 /* 125723 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42454 /* 125725 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42455 /* 125728 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42456 /* 125732 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42457 /* 125737 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42458 /* 125740 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42459 /* 125742 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42460 /* 125745 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42461 /* 125749 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42462 /* 125754 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
42463 /* 125761 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42464 /* 125766 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42465 /* 125771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42466 /* 125774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42467 /* 125776 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42468 /* 125779 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42469 /* 125782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42470 /* 125785 */ GIR_RootConstrainSelectedInstOperands,
42471 /* 125786 */ // GIR_Coverage, 4122,
42472 /* 125786 */ GIR_EraseRootFromParent_Done,
42473 /* 125787 */ // Label 1793: @125787
42474 /* 125787 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(125926), // Rule ID 4138 //
42475 /* 125792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42476 /* 125795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42477 /* 125798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42478 /* 125802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42479 /* 125806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42480 /* 125810 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42481 /* 125814 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42482 /* 125818 */ // MIs[1] Operand 1
42483 /* 125818 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
42484 /* 125823 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42485 /* 125825 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42486 /* 125825 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42487 /* 125828 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
42488 /* 125832 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42489 /* 125837 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42490 /* 125841 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42491 /* 125845 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42492 /* 125847 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42493 /* 125850 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42494 /* 125854 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42495 /* 125859 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42496 /* 125862 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42497 /* 125864 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42498 /* 125867 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42499 /* 125871 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42500 /* 125876 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42501 /* 125879 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42502 /* 125881 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42503 /* 125884 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42504 /* 125888 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42505 /* 125893 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
42506 /* 125900 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42507 /* 125905 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42508 /* 125910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42509 /* 125913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42510 /* 125915 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42511 /* 125918 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42512 /* 125921 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42513 /* 125924 */ GIR_RootConstrainSelectedInstOperands,
42514 /* 125925 */ // GIR_Coverage, 4138,
42515 /* 125925 */ GIR_EraseRootFromParent_Done,
42516 /* 125926 */ // Label 1794: @125926
42517 /* 125926 */ GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(126065), // Rule ID 4170 //
42518 /* 125931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42519 /* 125934 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42520 /* 125937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42521 /* 125941 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42522 /* 125945 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42523 /* 125949 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42524 /* 125953 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42525 /* 125957 */ // MIs[1] Operand 1
42526 /* 125957 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
42527 /* 125962 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42528 /* 125964 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42529 /* 125964 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42530 /* 125967 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
42531 /* 125971 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42532 /* 125976 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42533 /* 125980 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42534 /* 125984 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42535 /* 125986 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42536 /* 125989 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42537 /* 125993 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42538 /* 125998 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42539 /* 126001 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42540 /* 126003 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42541 /* 126006 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42542 /* 126010 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42543 /* 126015 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42544 /* 126018 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42545 /* 126020 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42546 /* 126023 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42547 /* 126027 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42548 /* 126032 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42549 /* 126039 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42550 /* 126044 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42551 /* 126049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42552 /* 126052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42553 /* 126054 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42554 /* 126057 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42555 /* 126060 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42556 /* 126063 */ GIR_RootConstrainSelectedInstOperands,
42557 /* 126064 */ // GIR_Coverage, 4170,
42558 /* 126064 */ GIR_EraseRootFromParent_Done,
42559 /* 126065 */ // Label 1795: @126065
42560 /* 126065 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(126204), // Rule ID 4202 //
42561 /* 126070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42562 /* 126073 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42563 /* 126076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42564 /* 126080 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42565 /* 126084 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42566 /* 126088 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42567 /* 126092 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42568 /* 126096 */ // MIs[1] Operand 1
42569 /* 126096 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
42570 /* 126101 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42571 /* 126103 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42572 /* 126103 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42573 /* 126106 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
42574 /* 126110 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42575 /* 126115 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42576 /* 126119 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42577 /* 126123 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42578 /* 126125 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42579 /* 126128 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42580 /* 126132 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42581 /* 126137 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42582 /* 126140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42583 /* 126142 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42584 /* 126145 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42585 /* 126149 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42586 /* 126154 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42587 /* 126157 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42588 /* 126159 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42589 /* 126162 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42590 /* 126166 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42591 /* 126171 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
42592 /* 126178 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42593 /* 126183 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42594 /* 126188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42595 /* 126191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42596 /* 126193 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42597 /* 126196 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42598 /* 126199 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42599 /* 126202 */ GIR_RootConstrainSelectedInstOperands,
42600 /* 126203 */ // GIR_Coverage, 4202,
42601 /* 126203 */ GIR_EraseRootFromParent_Done,
42602 /* 126204 */ // Label 1796: @126204
42603 /* 126204 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(126343), // Rule ID 4234 //
42604 /* 126209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42605 /* 126212 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42606 /* 126215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42607 /* 126219 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42608 /* 126223 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42609 /* 126227 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42610 /* 126231 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42611 /* 126235 */ // MIs[1] Operand 1
42612 /* 126235 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
42613 /* 126240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42614 /* 126242 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42615 /* 126242 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42616 /* 126245 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
42617 /* 126249 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42618 /* 126254 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42619 /* 126258 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42620 /* 126262 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42621 /* 126264 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42622 /* 126267 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42623 /* 126271 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42624 /* 126276 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42625 /* 126279 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42626 /* 126281 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42627 /* 126284 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42628 /* 126288 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42629 /* 126293 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42630 /* 126296 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42631 /* 126298 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42632 /* 126301 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42633 /* 126305 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42634 /* 126310 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
42635 /* 126317 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42636 /* 126322 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42637 /* 126327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42638 /* 126330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42639 /* 126332 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42640 /* 126335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42641 /* 126338 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42642 /* 126341 */ GIR_RootConstrainSelectedInstOperands,
42643 /* 126342 */ // GIR_Coverage, 4234,
42644 /* 126342 */ GIR_EraseRootFromParent_Done,
42645 /* 126343 */ // Label 1797: @126343
42646 /* 126343 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(126482), // Rule ID 4264 //
42647 /* 126348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42648 /* 126351 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42649 /* 126354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42650 /* 126358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42651 /* 126362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42652 /* 126366 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
42653 /* 126370 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
42654 /* 126374 */ // MIs[1] Operand 1
42655 /* 126374 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
42656 /* 126379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42657 /* 126381 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42658 /* 126381 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42659 /* 126384 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
42660 /* 126388 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42661 /* 126393 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42662 /* 126397 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42663 /* 126401 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42664 /* 126403 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42665 /* 126406 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42666 /* 126410 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42667 /* 126415 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42668 /* 126418 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42669 /* 126420 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42670 /* 126423 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42671 /* 126427 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42672 /* 126432 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42673 /* 126435 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42674 /* 126437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42675 /* 126440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42676 /* 126444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42677 /* 126449 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
42678 /* 126456 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42679 /* 126461 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42680 /* 126466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42681 /* 126469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42682 /* 126471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42683 /* 126474 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42684 /* 126477 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42685 /* 126480 */ GIR_RootConstrainSelectedInstOperands,
42686 /* 126481 */ // GIR_Coverage, 4264,
42687 /* 126481 */ GIR_EraseRootFromParent_Done,
42688 /* 126482 */ // Label 1798: @126482
42689 /* 126482 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(126621), // Rule ID 4296 //
42690 /* 126487 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42691 /* 126490 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42692 /* 126493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42693 /* 126497 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42694 /* 126501 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42695 /* 126505 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
42696 /* 126509 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
42697 /* 126513 */ // MIs[1] Operand 1
42698 /* 126513 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
42699 /* 126518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42700 /* 126520 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42701 /* 126520 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42702 /* 126523 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
42703 /* 126527 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42704 /* 126532 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42705 /* 126536 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42706 /* 126540 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42707 /* 126542 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42708 /* 126545 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42709 /* 126549 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42710 /* 126554 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42711 /* 126557 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42712 /* 126559 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42713 /* 126562 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42714 /* 126566 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42715 /* 126571 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42716 /* 126574 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42717 /* 126576 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42718 /* 126579 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42719 /* 126583 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42720 /* 126588 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42721 /* 126595 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42722 /* 126600 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42723 /* 126605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42724 /* 126608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42725 /* 126610 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42726 /* 126613 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42727 /* 126616 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42728 /* 126619 */ GIR_RootConstrainSelectedInstOperands,
42729 /* 126620 */ // GIR_Coverage, 4296,
42730 /* 126620 */ GIR_EraseRootFromParent_Done,
42731 /* 126621 */ // Label 1799: @126621
42732 /* 126621 */ GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(126760), // Rule ID 4328 //
42733 /* 126626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42734 /* 126629 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42735 /* 126632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42736 /* 126636 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42737 /* 126640 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42738 /* 126644 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
42739 /* 126648 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
42740 /* 126652 */ // MIs[1] Operand 1
42741 /* 126652 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
42742 /* 126657 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42743 /* 126659 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42744 /* 126659 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42745 /* 126662 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
42746 /* 126666 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42747 /* 126671 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42748 /* 126675 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42749 /* 126679 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42750 /* 126681 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42751 /* 126684 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42752 /* 126688 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42753 /* 126693 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42754 /* 126696 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42755 /* 126698 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42756 /* 126701 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42757 /* 126705 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42758 /* 126710 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42759 /* 126713 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42760 /* 126715 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42761 /* 126718 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42762 /* 126722 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42763 /* 126727 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
42764 /* 126734 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42765 /* 126739 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42766 /* 126744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42767 /* 126747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42768 /* 126749 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42769 /* 126752 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42770 /* 126755 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42771 /* 126758 */ GIR_RootConstrainSelectedInstOperands,
42772 /* 126759 */ // GIR_Coverage, 4328,
42773 /* 126759 */ GIR_EraseRootFromParent_Done,
42774 /* 126760 */ // Label 1800: @126760
42775 /* 126760 */ GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(126899), // Rule ID 4360 //
42776 /* 126765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
42777 /* 126768 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42778 /* 126771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42779 /* 126775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42780 /* 126779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42781 /* 126783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
42782 /* 126787 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
42783 /* 126791 */ // MIs[1] Operand 1
42784 /* 126791 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
42785 /* 126796 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42786 /* 126798 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42787 /* 126798 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42788 /* 126801 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
42789 /* 126805 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42790 /* 126810 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42791 /* 126814 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42792 /* 126818 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42793 /* 126820 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42794 /* 126823 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42795 /* 126827 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42796 /* 126832 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42797 /* 126835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42798 /* 126837 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42799 /* 126840 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42800 /* 126844 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42801 /* 126849 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42802 /* 126852 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42803 /* 126854 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42804 /* 126857 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42805 /* 126861 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42806 /* 126866 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
42807 /* 126873 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42808 /* 126878 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42809 /* 126883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42810 /* 126886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42811 /* 126888 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42812 /* 126891 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42813 /* 126894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42814 /* 126897 */ GIR_RootConstrainSelectedInstOperands,
42815 /* 126898 */ // GIR_Coverage, 4360,
42816 /* 126898 */ GIR_EraseRootFromParent_Done,
42817 /* 126899 */ // Label 1801: @126899
42818 /* 126899 */ GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(127038), // Rule ID 4591 //
42819 /* 126904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
42820 /* 126907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42821 /* 126910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42822 /* 126914 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42823 /* 126918 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42824 /* 126922 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42825 /* 126926 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42826 /* 126930 */ // MIs[1] Operand 1
42827 /* 126930 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
42828 /* 126935 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42829 /* 126937 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42830 /* 126937 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42831 /* 126940 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
42832 /* 126944 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42833 /* 126949 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42834 /* 126953 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42835 /* 126957 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42836 /* 126959 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42837 /* 126962 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42838 /* 126966 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42839 /* 126971 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42840 /* 126974 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42841 /* 126976 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42842 /* 126979 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42843 /* 126983 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42844 /* 126988 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42845 /* 126991 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42846 /* 126993 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42847 /* 126996 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42848 /* 127000 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42849 /* 127005 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42850 /* 127012 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42851 /* 127017 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42852 /* 127022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42853 /* 127025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42854 /* 127027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42855 /* 127030 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42856 /* 127033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42857 /* 127036 */ GIR_RootConstrainSelectedInstOperands,
42858 /* 127037 */ // GIR_Coverage, 4591,
42859 /* 127037 */ GIR_EraseRootFromParent_Done,
42860 /* 127038 */ // Label 1802: @127038
42861 /* 127038 */ GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(127177), // Rule ID 4623 //
42862 /* 127043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
42863 /* 127046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42864 /* 127049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42865 /* 127053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42866 /* 127057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42867 /* 127061 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42868 /* 127065 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42869 /* 127069 */ // MIs[1] Operand 1
42870 /* 127069 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
42871 /* 127074 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42872 /* 127076 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42873 /* 127076 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42874 /* 127079 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
42875 /* 127083 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42876 /* 127088 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42877 /* 127092 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42878 /* 127096 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42879 /* 127098 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42880 /* 127101 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42881 /* 127105 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42882 /* 127110 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42883 /* 127113 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42884 /* 127115 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42885 /* 127118 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42886 /* 127122 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42887 /* 127127 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42888 /* 127130 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42889 /* 127132 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42890 /* 127135 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42891 /* 127139 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42892 /* 127144 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42893 /* 127151 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42894 /* 127156 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42895 /* 127161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42896 /* 127164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42897 /* 127166 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42898 /* 127169 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42899 /* 127172 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42900 /* 127175 */ GIR_RootConstrainSelectedInstOperands,
42901 /* 127176 */ // GIR_Coverage, 4623,
42902 /* 127176 */ GIR_EraseRootFromParent_Done,
42903 /* 127177 */ // Label 1803: @127177
42904 /* 127177 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(127316), // Rule ID 4655 //
42905 /* 127182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
42906 /* 127185 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42907 /* 127188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42908 /* 127192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42909 /* 127196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42910 /* 127200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
42911 /* 127204 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
42912 /* 127208 */ // MIs[1] Operand 1
42913 /* 127208 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
42914 /* 127213 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42915 /* 127215 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42916 /* 127215 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42917 /* 127218 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
42918 /* 127222 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42919 /* 127227 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42920 /* 127231 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42921 /* 127235 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42922 /* 127237 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42923 /* 127240 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42924 /* 127244 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42925 /* 127249 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42926 /* 127252 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42927 /* 127254 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42928 /* 127257 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42929 /* 127261 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42930 /* 127266 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42931 /* 127269 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42932 /* 127271 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42933 /* 127274 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42934 /* 127278 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42935 /* 127283 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42936 /* 127290 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42937 /* 127295 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42938 /* 127300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42939 /* 127303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42940 /* 127305 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42941 /* 127308 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42942 /* 127311 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42943 /* 127314 */ GIR_RootConstrainSelectedInstOperands,
42944 /* 127315 */ // GIR_Coverage, 4655,
42945 /* 127315 */ GIR_EraseRootFromParent_Done,
42946 /* 127316 */ // Label 1804: @127316
42947 /* 127316 */ GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(127455), // Rule ID 4699 //
42948 /* 127321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
42949 /* 127324 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42950 /* 127327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42951 /* 127331 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42952 /* 127335 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42953 /* 127339 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42954 /* 127343 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42955 /* 127347 */ // MIs[1] Operand 1
42956 /* 127347 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
42957 /* 127352 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42958 /* 127354 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
42959 /* 127354 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
42960 /* 127357 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
42961 /* 127361 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42962 /* 127366 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
42963 /* 127370 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
42964 /* 127374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42965 /* 127376 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
42966 /* 127379 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
42967 /* 127383 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42968 /* 127388 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
42969 /* 127391 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
42970 /* 127393 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
42971 /* 127396 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
42972 /* 127400 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42973 /* 127405 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
42974 /* 127408 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42975 /* 127410 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
42976 /* 127413 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42977 /* 127417 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
42978 /* 127422 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
42979 /* 127429 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
42980 /* 127434 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
42981 /* 127439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
42982 /* 127442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42983 /* 127444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42984 /* 127447 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
42985 /* 127450 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
42986 /* 127453 */ GIR_RootConstrainSelectedInstOperands,
42987 /* 127454 */ // GIR_Coverage, 4699,
42988 /* 127454 */ GIR_EraseRootFromParent_Done,
42989 /* 127455 */ // Label 1805: @127455
42990 /* 127455 */ GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(127594), // Rule ID 4731 //
42991 /* 127460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
42992 /* 127463 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
42993 /* 127466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
42994 /* 127470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42995 /* 127474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
42996 /* 127478 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42997 /* 127482 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
42998 /* 127486 */ // MIs[1] Operand 1
42999 /* 127486 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
43000 /* 127491 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43001 /* 127493 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43002 /* 127493 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43003 /* 127496 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
43004 /* 127500 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43005 /* 127505 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43006 /* 127509 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43007 /* 127513 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43008 /* 127515 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43009 /* 127518 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43010 /* 127522 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43011 /* 127527 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43012 /* 127530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43013 /* 127532 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43014 /* 127535 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43015 /* 127539 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43016 /* 127544 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43017 /* 127547 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43018 /* 127549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43019 /* 127552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43020 /* 127556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43021 /* 127561 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43022 /* 127568 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43023 /* 127573 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43024 /* 127578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43025 /* 127581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43026 /* 127583 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43027 /* 127586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43028 /* 127589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43029 /* 127592 */ GIR_RootConstrainSelectedInstOperands,
43030 /* 127593 */ // GIR_Coverage, 4731,
43031 /* 127593 */ GIR_EraseRootFromParent_Done,
43032 /* 127594 */ // Label 1806: @127594
43033 /* 127594 */ GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(127733), // Rule ID 4763 //
43034 /* 127599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
43035 /* 127602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43036 /* 127605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43037 /* 127609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43038 /* 127613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
43039 /* 127617 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43040 /* 127621 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43041 /* 127625 */ // MIs[1] Operand 1
43042 /* 127625 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
43043 /* 127630 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43044 /* 127632 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43045 /* 127632 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43046 /* 127635 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
43047 /* 127639 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43048 /* 127644 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43049 /* 127648 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43050 /* 127652 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43051 /* 127654 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43052 /* 127657 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43053 /* 127661 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43054 /* 127666 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43055 /* 127669 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43056 /* 127671 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43057 /* 127674 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43058 /* 127678 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43059 /* 127683 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43060 /* 127686 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43061 /* 127688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43062 /* 127691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43063 /* 127695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43064 /* 127700 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43065 /* 127707 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43066 /* 127712 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43067 /* 127717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43068 /* 127720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43069 /* 127722 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43070 /* 127725 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43071 /* 127728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43072 /* 127731 */ GIR_RootConstrainSelectedInstOperands,
43073 /* 127732 */ // GIR_Coverage, 4763,
43074 /* 127732 */ GIR_EraseRootFromParent_Done,
43075 /* 127733 */ // Label 1807: @127733
43076 /* 127733 */ GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(127832), // Rule ID 2985 //
43077 /* 127738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43078 /* 127741 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43079 /* 127744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43080 /* 127748 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43081 /* 127752 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43082 /* 127756 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43083 /* 127760 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43084 /* 127764 */ // MIs[1] Operand 1
43085 /* 127764 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
43086 /* 127769 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43087 /* 127771 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
43088 /* 127771 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43089 /* 127774 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
43090 /* 127778 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43091 /* 127783 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43092 /* 127787 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43093 /* 127791 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43094 /* 127793 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43095 /* 127796 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43096 /* 127800 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43097 /* 127805 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
43098 /* 127812 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43099 /* 127817 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43100 /* 127822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43101 /* 127825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43102 /* 127827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43103 /* 127830 */ GIR_RootConstrainSelectedInstOperands,
43104 /* 127831 */ // GIR_Coverage, 2985,
43105 /* 127831 */ GIR_EraseRootFromParent_Done,
43106 /* 127832 */ // Label 1808: @127832
43107 /* 127832 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(127931), // Rule ID 2999 //
43108 /* 127837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43109 /* 127840 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43110 /* 127843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43111 /* 127847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43112 /* 127851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43113 /* 127855 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43114 /* 127859 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43115 /* 127863 */ // MIs[1] Operand 1
43116 /* 127863 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
43117 /* 127868 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43118 /* 127870 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
43119 /* 127870 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43120 /* 127873 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
43121 /* 127877 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43122 /* 127882 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43123 /* 127886 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43124 /* 127890 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43125 /* 127892 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43126 /* 127895 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43127 /* 127899 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43128 /* 127904 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
43129 /* 127911 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43130 /* 127916 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43131 /* 127921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43132 /* 127924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43133 /* 127926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43134 /* 127929 */ GIR_RootConstrainSelectedInstOperands,
43135 /* 127930 */ // GIR_Coverage, 2999,
43136 /* 127930 */ GIR_EraseRootFromParent_Done,
43137 /* 127931 */ // Label 1809: @127931
43138 /* 127931 */ GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(128030), // Rule ID 3007 //
43139 /* 127936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43140 /* 127939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43141 /* 127942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43142 /* 127946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43143 /* 127950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43144 /* 127954 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43145 /* 127958 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43146 /* 127962 */ // MIs[1] Operand 1
43147 /* 127962 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
43148 /* 127967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43149 /* 127969 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
43150 /* 127969 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43151 /* 127972 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
43152 /* 127976 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43153 /* 127981 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43154 /* 127985 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43155 /* 127989 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43156 /* 127991 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43157 /* 127994 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43158 /* 127998 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43159 /* 128003 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43160 /* 128010 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43161 /* 128015 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43162 /* 128020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43163 /* 128023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43164 /* 128025 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43165 /* 128028 */ GIR_RootConstrainSelectedInstOperands,
43166 /* 128029 */ // GIR_Coverage, 3007,
43167 /* 128029 */ GIR_EraseRootFromParent_Done,
43168 /* 128030 */ // Label 1810: @128030
43169 /* 128030 */ GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(128129), // Rule ID 3015 //
43170 /* 128035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43171 /* 128038 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43172 /* 128041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43173 /* 128045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43174 /* 128049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43175 /* 128053 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43176 /* 128057 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43177 /* 128061 */ // MIs[1] Operand 1
43178 /* 128061 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
43179 /* 128066 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43180 /* 128068 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
43181 /* 128068 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43182 /* 128071 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
43183 /* 128075 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43184 /* 128080 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43185 /* 128084 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43186 /* 128088 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43187 /* 128090 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43188 /* 128093 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43189 /* 128097 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43190 /* 128102 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43191 /* 128109 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43192 /* 128114 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43193 /* 128119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43194 /* 128122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43195 /* 128124 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43196 /* 128127 */ GIR_RootConstrainSelectedInstOperands,
43197 /* 128128 */ // GIR_Coverage, 3015,
43198 /* 128128 */ GIR_EraseRootFromParent_Done,
43199 /* 128129 */ // Label 1811: @128129
43200 /* 128129 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(128228), // Rule ID 3023 //
43201 /* 128134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43202 /* 128137 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43203 /* 128140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43204 /* 128144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43205 /* 128148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43206 /* 128152 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43207 /* 128156 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43208 /* 128160 */ // MIs[1] Operand 1
43209 /* 128160 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
43210 /* 128165 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43211 /* 128167 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }))
43212 /* 128167 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43213 /* 128170 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
43214 /* 128174 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43215 /* 128179 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43216 /* 128183 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43217 /* 128187 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43218 /* 128189 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43219 /* 128192 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43220 /* 128196 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43221 /* 128201 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
43222 /* 128208 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43223 /* 128213 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43224 /* 128218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43225 /* 128221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43226 /* 128223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43227 /* 128226 */ GIR_RootConstrainSelectedInstOperands,
43228 /* 128227 */ // GIR_Coverage, 3023,
43229 /* 128227 */ GIR_EraseRootFromParent_Done,
43230 /* 128228 */ // Label 1812: @128228
43231 /* 128228 */ GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(128327), // Rule ID 3087 //
43232 /* 128233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43233 /* 128236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43234 /* 128239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43235 /* 128243 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43236 /* 128247 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43237 /* 128251 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43238 /* 128255 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43239 /* 128259 */ // MIs[1] Operand 1
43240 /* 128259 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
43241 /* 128264 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43242 /* 128266 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
43243 /* 128266 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43244 /* 128269 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
43245 /* 128273 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43246 /* 128278 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43247 /* 128282 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43248 /* 128286 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43249 /* 128288 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43250 /* 128291 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43251 /* 128295 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43252 /* 128300 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
43253 /* 128307 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43254 /* 128312 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43255 /* 128317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43256 /* 128320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43257 /* 128322 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43258 /* 128325 */ GIR_RootConstrainSelectedInstOperands,
43259 /* 128326 */ // GIR_Coverage, 3087,
43260 /* 128326 */ GIR_EraseRootFromParent_Done,
43261 /* 128327 */ // Label 1813: @128327
43262 /* 128327 */ GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(128426), // Rule ID 3095 //
43263 /* 128332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43264 /* 128335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43265 /* 128338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43266 /* 128342 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43267 /* 128346 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43268 /* 128350 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43269 /* 128354 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43270 /* 128358 */ // MIs[1] Operand 1
43271 /* 128358 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
43272 /* 128363 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43273 /* 128365 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
43274 /* 128365 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43275 /* 128368 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
43276 /* 128372 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43277 /* 128377 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43278 /* 128381 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43279 /* 128385 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43280 /* 128387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43281 /* 128390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43282 /* 128394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43283 /* 128399 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
43284 /* 128406 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43285 /* 128411 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43286 /* 128416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43287 /* 128419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43288 /* 128421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43289 /* 128424 */ GIR_RootConstrainSelectedInstOperands,
43290 /* 128425 */ // GIR_Coverage, 3095,
43291 /* 128425 */ GIR_EraseRootFromParent_Done,
43292 /* 128426 */ // Label 1814: @128426
43293 /* 128426 */ GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(128525), // Rule ID 3103 //
43294 /* 128431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43295 /* 128434 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43296 /* 128437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43297 /* 128441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43298 /* 128445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43299 /* 128449 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43300 /* 128453 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43301 /* 128457 */ // MIs[1] Operand 1
43302 /* 128457 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
43303 /* 128462 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43304 /* 128464 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
43305 /* 128464 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43306 /* 128467 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
43307 /* 128471 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43308 /* 128476 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43309 /* 128480 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43310 /* 128484 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43311 /* 128486 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43312 /* 128489 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43313 /* 128493 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43314 /* 128498 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43315 /* 128505 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43316 /* 128510 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43317 /* 128515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43318 /* 128518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43319 /* 128520 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43320 /* 128523 */ GIR_RootConstrainSelectedInstOperands,
43321 /* 128524 */ // GIR_Coverage, 3103,
43322 /* 128524 */ GIR_EraseRootFromParent_Done,
43323 /* 128525 */ // Label 1815: @128525
43324 /* 128525 */ GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(128624), // Rule ID 3111 //
43325 /* 128530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43326 /* 128533 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43327 /* 128536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43328 /* 128540 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43329 /* 128544 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43330 /* 128548 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43331 /* 128552 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43332 /* 128556 */ // MIs[1] Operand 1
43333 /* 128556 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
43334 /* 128561 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43335 /* 128563 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
43336 /* 128563 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43337 /* 128566 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
43338 /* 128570 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43339 /* 128575 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43340 /* 128579 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43341 /* 128583 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43342 /* 128585 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43343 /* 128588 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43344 /* 128592 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43345 /* 128597 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43346 /* 128604 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43347 /* 128609 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43348 /* 128614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43349 /* 128617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43350 /* 128619 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43351 /* 128622 */ GIR_RootConstrainSelectedInstOperands,
43352 /* 128623 */ // GIR_Coverage, 3111,
43353 /* 128623 */ GIR_EraseRootFromParent_Done,
43354 /* 128624 */ // Label 1816: @128624
43355 /* 128624 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(128723), // Rule ID 3119 //
43356 /* 128629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43357 /* 128632 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43358 /* 128635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43359 /* 128639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43360 /* 128643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43361 /* 128647 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43362 /* 128651 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43363 /* 128655 */ // MIs[1] Operand 1
43364 /* 128655 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
43365 /* 128660 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43366 /* 128662 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SETNBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }))
43367 /* 128662 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43368 /* 128665 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
43369 /* 128669 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43370 /* 128674 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43371 /* 128678 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43372 /* 128682 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43373 /* 128684 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43374 /* 128687 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43375 /* 128691 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43376 /* 128696 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
43377 /* 128703 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43378 /* 128708 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43379 /* 128713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETNBCR8),
43380 /* 128716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
43381 /* 128718 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43382 /* 128721 */ GIR_RootConstrainSelectedInstOperands,
43383 /* 128722 */ // GIR_Coverage, 3119,
43384 /* 128722 */ GIR_EraseRootFromParent_Done,
43385 /* 128723 */ // Label 1817: @128723
43386 /* 128723 */ GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(128862), // Rule ID 3870 //
43387 /* 128728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43388 /* 128731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43389 /* 128734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43390 /* 128738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43391 /* 128742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43392 /* 128746 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43393 /* 128750 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43394 /* 128754 */ // MIs[1] Operand 1
43395 /* 128754 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
43396 /* 128759 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43397 /* 128761 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43398 /* 128761 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43399 /* 128764 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
43400 /* 128768 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43401 /* 128773 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43402 /* 128777 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43403 /* 128781 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43404 /* 128783 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43405 /* 128786 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43406 /* 128790 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43407 /* 128795 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43408 /* 128798 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43409 /* 128800 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43410 /* 128803 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43411 /* 128807 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43412 /* 128812 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43413 /* 128815 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43414 /* 128817 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43415 /* 128820 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43416 /* 128824 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43417 /* 128829 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
43418 /* 128836 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43419 /* 128841 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43420 /* 128846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43421 /* 128849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43422 /* 128851 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43423 /* 128854 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43424 /* 128857 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43425 /* 128860 */ GIR_RootConstrainSelectedInstOperands,
43426 /* 128861 */ // GIR_Coverage, 3870,
43427 /* 128861 */ GIR_EraseRootFromParent_Done,
43428 /* 128862 */ // Label 1818: @128862
43429 /* 128862 */ GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(129001), // Rule ID 3878 //
43430 /* 128867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43431 /* 128870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43432 /* 128873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43433 /* 128877 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43434 /* 128881 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43435 /* 128885 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43436 /* 128889 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43437 /* 128893 */ // MIs[1] Operand 1
43438 /* 128893 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
43439 /* 128898 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43440 /* 128900 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43441 /* 128900 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43442 /* 128903 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
43443 /* 128907 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43444 /* 128912 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43445 /* 128916 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43446 /* 128920 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43447 /* 128922 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43448 /* 128925 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43449 /* 128929 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43450 /* 128934 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43451 /* 128937 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43452 /* 128939 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43453 /* 128942 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43454 /* 128946 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43455 /* 128951 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43456 /* 128954 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43457 /* 128956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43458 /* 128959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43459 /* 128963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43460 /* 128968 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
43461 /* 128975 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43462 /* 128980 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43463 /* 128985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43464 /* 128988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43465 /* 128990 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43466 /* 128993 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43467 /* 128996 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43468 /* 128999 */ GIR_RootConstrainSelectedInstOperands,
43469 /* 129000 */ // GIR_Coverage, 3878,
43470 /* 129000 */ GIR_EraseRootFromParent_Done,
43471 /* 129001 */ // Label 1819: @129001
43472 /* 129001 */ GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(129140), // Rule ID 3886 //
43473 /* 129006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43474 /* 129009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43475 /* 129012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43476 /* 129016 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43477 /* 129020 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43478 /* 129024 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43479 /* 129028 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43480 /* 129032 */ // MIs[1] Operand 1
43481 /* 129032 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
43482 /* 129037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43483 /* 129039 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43484 /* 129039 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43485 /* 129042 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
43486 /* 129046 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43487 /* 129051 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43488 /* 129055 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43489 /* 129059 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43490 /* 129061 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43491 /* 129064 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43492 /* 129068 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43493 /* 129073 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43494 /* 129076 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43495 /* 129078 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43496 /* 129081 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43497 /* 129085 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43498 /* 129090 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43499 /* 129093 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43500 /* 129095 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43501 /* 129098 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43502 /* 129102 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43503 /* 129107 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43504 /* 129114 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43505 /* 129119 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43506 /* 129124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43507 /* 129127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43508 /* 129129 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43509 /* 129132 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43510 /* 129135 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43511 /* 129138 */ GIR_RootConstrainSelectedInstOperands,
43512 /* 129139 */ // GIR_Coverage, 3886,
43513 /* 129139 */ GIR_EraseRootFromParent_Done,
43514 /* 129140 */ // Label 1820: @129140
43515 /* 129140 */ GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(129279), // Rule ID 3894 //
43516 /* 129145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43517 /* 129148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43518 /* 129151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43519 /* 129155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43520 /* 129159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43521 /* 129163 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43522 /* 129167 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43523 /* 129171 */ // MIs[1] Operand 1
43524 /* 129171 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
43525 /* 129176 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43526 /* 129178 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43527 /* 129178 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43528 /* 129181 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
43529 /* 129185 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43530 /* 129190 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43531 /* 129194 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43532 /* 129198 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43533 /* 129200 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43534 /* 129203 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43535 /* 129207 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43536 /* 129212 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43537 /* 129215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43538 /* 129217 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43539 /* 129220 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43540 /* 129224 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43541 /* 129229 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43542 /* 129232 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43543 /* 129234 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43544 /* 129237 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43545 /* 129241 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43546 /* 129246 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43547 /* 129253 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43548 /* 129258 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43549 /* 129263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43550 /* 129266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43551 /* 129268 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43552 /* 129271 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43553 /* 129274 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43554 /* 129277 */ GIR_RootConstrainSelectedInstOperands,
43555 /* 129278 */ // GIR_Coverage, 3894,
43556 /* 129278 */ GIR_EraseRootFromParent_Done,
43557 /* 129279 */ // Label 1821: @129279
43558 /* 129279 */ GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(129418), // Rule ID 3902 //
43559 /* 129284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43560 /* 129287 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43561 /* 129290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43562 /* 129294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43563 /* 129298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43564 /* 129302 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43565 /* 129306 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43566 /* 129310 */ // MIs[1] Operand 1
43567 /* 129310 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
43568 /* 129315 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43569 /* 129317 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43570 /* 129317 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43571 /* 129320 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
43572 /* 129324 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43573 /* 129329 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43574 /* 129333 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43575 /* 129337 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43576 /* 129339 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43577 /* 129342 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43578 /* 129346 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43579 /* 129351 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43580 /* 129354 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43581 /* 129356 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43582 /* 129359 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43583 /* 129363 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43584 /* 129368 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43585 /* 129371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43586 /* 129373 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43587 /* 129376 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43588 /* 129380 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43589 /* 129385 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
43590 /* 129392 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43591 /* 129397 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43592 /* 129402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43593 /* 129405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43594 /* 129407 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43595 /* 129410 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43596 /* 129413 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43597 /* 129416 */ GIR_RootConstrainSelectedInstOperands,
43598 /* 129417 */ // GIR_Coverage, 3902,
43599 /* 129417 */ GIR_EraseRootFromParent_Done,
43600 /* 129418 */ // Label 1822: @129418
43601 /* 129418 */ GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(129557), // Rule ID 3966 //
43602 /* 129423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43603 /* 129426 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43604 /* 129429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43605 /* 129433 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43606 /* 129437 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43607 /* 129441 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43608 /* 129445 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43609 /* 129449 */ // MIs[1] Operand 1
43610 /* 129449 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
43611 /* 129454 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43612 /* 129456 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43613 /* 129456 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43614 /* 129459 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
43615 /* 129463 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43616 /* 129468 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43617 /* 129472 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43618 /* 129476 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43619 /* 129478 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43620 /* 129481 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43621 /* 129485 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43622 /* 129490 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43623 /* 129493 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43624 /* 129495 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43625 /* 129498 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43626 /* 129502 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43627 /* 129507 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43628 /* 129510 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43629 /* 129512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43630 /* 129515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43631 /* 129519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43632 /* 129524 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
43633 /* 129531 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43634 /* 129536 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43635 /* 129541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43636 /* 129544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43637 /* 129546 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43638 /* 129549 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43639 /* 129552 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43640 /* 129555 */ GIR_RootConstrainSelectedInstOperands,
43641 /* 129556 */ // GIR_Coverage, 3966,
43642 /* 129556 */ GIR_EraseRootFromParent_Done,
43643 /* 129557 */ // Label 1823: @129557
43644 /* 129557 */ GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(129696), // Rule ID 3974 //
43645 /* 129562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43646 /* 129565 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43647 /* 129568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43648 /* 129572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43649 /* 129576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43650 /* 129580 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43651 /* 129584 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43652 /* 129588 */ // MIs[1] Operand 1
43653 /* 129588 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
43654 /* 129593 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43655 /* 129595 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43656 /* 129595 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43657 /* 129598 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
43658 /* 129602 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43659 /* 129607 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43660 /* 129611 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43661 /* 129615 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43662 /* 129617 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43663 /* 129620 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43664 /* 129624 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43665 /* 129629 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43666 /* 129632 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43667 /* 129634 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43668 /* 129637 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43669 /* 129641 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43670 /* 129646 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43671 /* 129649 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43672 /* 129651 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43673 /* 129654 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43674 /* 129658 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43675 /* 129663 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
43676 /* 129670 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43677 /* 129675 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43678 /* 129680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43679 /* 129683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43680 /* 129685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43681 /* 129688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43682 /* 129691 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43683 /* 129694 */ GIR_RootConstrainSelectedInstOperands,
43684 /* 129695 */ // GIR_Coverage, 3974,
43685 /* 129695 */ GIR_EraseRootFromParent_Done,
43686 /* 129696 */ // Label 1824: @129696
43687 /* 129696 */ GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(129835), // Rule ID 3982 //
43688 /* 129701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43689 /* 129704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43690 /* 129707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43691 /* 129711 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43692 /* 129715 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43693 /* 129719 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43694 /* 129723 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43695 /* 129727 */ // MIs[1] Operand 1
43696 /* 129727 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
43697 /* 129732 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43698 /* 129734 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43699 /* 129734 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43700 /* 129737 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
43701 /* 129741 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43702 /* 129746 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43703 /* 129750 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43704 /* 129754 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43705 /* 129756 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43706 /* 129759 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43707 /* 129763 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43708 /* 129768 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43709 /* 129771 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43710 /* 129773 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43711 /* 129776 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43712 /* 129780 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43713 /* 129785 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43714 /* 129788 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43715 /* 129790 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43716 /* 129793 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43717 /* 129797 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43718 /* 129802 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43719 /* 129809 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43720 /* 129814 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43721 /* 129819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43722 /* 129822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43723 /* 129824 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43724 /* 129827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43725 /* 129830 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43726 /* 129833 */ GIR_RootConstrainSelectedInstOperands,
43727 /* 129834 */ // GIR_Coverage, 3982,
43728 /* 129834 */ GIR_EraseRootFromParent_Done,
43729 /* 129835 */ // Label 1825: @129835
43730 /* 129835 */ GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(129974), // Rule ID 3990 //
43731 /* 129840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43732 /* 129843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43733 /* 129846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43734 /* 129850 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43735 /* 129854 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43736 /* 129858 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43737 /* 129862 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43738 /* 129866 */ // MIs[1] Operand 1
43739 /* 129866 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
43740 /* 129871 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43741 /* 129873 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43742 /* 129873 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43743 /* 129876 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
43744 /* 129880 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43745 /* 129885 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43746 /* 129889 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43747 /* 129893 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43748 /* 129895 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43749 /* 129898 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43750 /* 129902 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43751 /* 129907 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43752 /* 129910 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43753 /* 129912 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43754 /* 129915 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43755 /* 129919 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43756 /* 129924 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43757 /* 129927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43758 /* 129929 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43759 /* 129932 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43760 /* 129936 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43761 /* 129941 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
43762 /* 129948 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43763 /* 129953 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43764 /* 129958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43765 /* 129961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43766 /* 129963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43767 /* 129966 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43768 /* 129969 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43769 /* 129972 */ GIR_RootConstrainSelectedInstOperands,
43770 /* 129973 */ // GIR_Coverage, 3990,
43771 /* 129973 */ GIR_EraseRootFromParent_Done,
43772 /* 129974 */ // Label 1826: @129974
43773 /* 129974 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(130113), // Rule ID 3998 //
43774 /* 129979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
43775 /* 129982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43776 /* 129985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43777 /* 129989 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43778 /* 129993 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
43779 /* 129997 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43780 /* 130001 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43781 /* 130005 */ // MIs[1] Operand 1
43782 /* 130005 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
43783 /* 130010 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43784 /* 130012 */ // (sext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } -1:{ *:[i64] }))
43785 /* 130012 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
43786 /* 130015 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
43787 /* 130019 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43788 /* 130024 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
43789 /* 130028 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
43790 /* 130032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43791 /* 130034 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
43792 /* 130037 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
43793 /* 130041 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43794 /* 130046 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/uint8_t(-1),
43795 /* 130049 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43796 /* 130051 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
43797 /* 130054 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
43798 /* 130058 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43799 /* 130063 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
43800 /* 130066 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43801 /* 130068 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
43802 /* 130071 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43803 /* 130075 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43804 /* 130080 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
43805 /* 130087 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
43806 /* 130092 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
43807 /* 130097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43808 /* 130100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43809 /* 130102 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43810 /* 130105 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
43811 /* 130108 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
43812 /* 130111 */ GIR_RootConstrainSelectedInstOperands,
43813 /* 130112 */ // GIR_Coverage, 3998,
43814 /* 130112 */ GIR_EraseRootFromParent_Done,
43815 /* 130113 */ // Label 1827: @130113
43816 /* 130113 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(130132), // Rule ID 684 //
43817 /* 130118 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43818 /* 130121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43819 /* 130125 */ // (sext:{ *:[i64] } i32:{ *:[i32] }:$RST) => (EXTSW_32_64:{ *:[i64] } i32:{ *:[i32] }:$RST)
43820 /* 130125 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EXTSW_32_64),
43821 /* 130130 */ GIR_RootConstrainSelectedInstOperands,
43822 /* 130131 */ // GIR_Coverage, 684,
43823 /* 130131 */ GIR_Done,
43824 /* 130132 */ // Label 1828: @130132
43825 /* 130132 */ GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(130154), // Rule ID 2991 //
43826 /* 130137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
43827 /* 130140 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43828 /* 130143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43829 /* 130147 */ // (sext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SETNBC8:{ *:[i64] } ?:{ *:[i1] }:$in)
43830 /* 130147 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETNBC8),
43831 /* 130152 */ GIR_RootConstrainSelectedInstOperands,
43832 /* 130153 */ // GIR_Coverage, 2991,
43833 /* 130153 */ GIR_Done,
43834 /* 130154 */ // Label 1829: @130154
43835 /* 130154 */ GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(130215), // Rule ID 3676 //
43836 /* 130159 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
43837 /* 130162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43838 /* 130166 */ // (sext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SELECT_I8:{ *:[i64] } ?:{ *:[i1] }:$in, (LI8:{ *:[i64] } -1:{ *:[i64] }), (LI8:{ *:[i64] } 0:{ *:[i64] }))
43839 /* 130166 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43840 /* 130169 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI8),
43841 /* 130173 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43842 /* 130178 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
43843 /* 130181 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43844 /* 130183 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
43845 /* 130186 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI8),
43846 /* 130190 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
43847 /* 130195 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/uint8_t(-1),
43848 /* 130198 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43849 /* 130200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
43850 /* 130203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43851 /* 130205 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
43852 /* 130207 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43853 /* 130210 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
43854 /* 130213 */ GIR_RootConstrainSelectedInstOperands,
43855 /* 130214 */ // GIR_Coverage, 3676,
43856 /* 130214 */ GIR_EraseRootFromParent_Done,
43857 /* 130215 */ // Label 1830: @130215
43858 /* 130215 */ GIM_Reject,
43859 /* 130216 */ // Label 1700: @130216
43860 /* 130216 */ GIM_Reject,
43861 /* 130217 */ // Label 25: @130217
43862 /* 130217 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1835*/ GIMT_Encode4(130569),
43863 /* 130228 */ /*GILLT_s32*//*Label 1831*/ GIMT_Encode4(130248),
43864 /* 130232 */ /*GILLT_s64*//*Label 1832*/ GIMT_Encode4(130312), GIMT_Encode4(0),
43865 /* 130240 */ /*GILLT_v2s64*//*Label 1833*/ GIMT_Encode4(130401),
43866 /* 130244 */ /*GILLT_v4s32*//*Label 1834*/ GIMT_Encode4(130499),
43867 /* 130248 */ // Label 1831: @130248
43868 /* 130248 */ GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(130311),
43869 /* 130253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43870 /* 130256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
43871 /* 130260 */ GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(130285), // Rule ID 135 //
43872 /* 130265 */ // MIs[0] Operand 2
43873 /* 130265 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
43874 /* 130276 */ // (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$RST, i8:{ *:[Other] }) => (EXTSB:{ *:[i32] } i32:{ *:[i32] }:$RST)
43875 /* 130276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EXTSB),
43876 /* 130279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
43877 /* 130281 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
43878 /* 130283 */ GIR_RootConstrainSelectedInstOperands,
43879 /* 130284 */ // GIR_Coverage, 135,
43880 /* 130284 */ GIR_EraseRootFromParent_Done,
43881 /* 130285 */ // Label 1837: @130285
43882 /* 130285 */ GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(130310), // Rule ID 136 //
43883 /* 130290 */ // MIs[0] Operand 2
43884 /* 130290 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
43885 /* 130301 */ // (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$RST, i16:{ *:[Other] }) => (EXTSH:{ *:[i32] } i32:{ *:[i32] }:$RST)
43886 /* 130301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EXTSH),
43887 /* 130304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
43888 /* 130306 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
43889 /* 130308 */ GIR_RootConstrainSelectedInstOperands,
43890 /* 130309 */ // GIR_Coverage, 136,
43891 /* 130309 */ GIR_EraseRootFromParent_Done,
43892 /* 130310 */ // Label 1838: @130310
43893 /* 130310 */ GIM_Reject,
43894 /* 130311 */ // Label 1836: @130311
43895 /* 130311 */ GIM_Reject,
43896 /* 130312 */ // Label 1832: @130312
43897 /* 130312 */ GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(130400),
43898 /* 130317 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
43899 /* 130320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
43900 /* 130324 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(130349), // Rule ID 681 //
43901 /* 130329 */ // MIs[0] Operand 2
43902 /* 130329 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
43903 /* 130340 */ // (sext_inreg:{ *:[i64] } i64:{ *:[i64] }:$RST, i8:{ *:[Other] }) => (EXTSB8:{ *:[i64] } i64:{ *:[i64] }:$RST)
43904 /* 130340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EXTSB8),
43905 /* 130343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
43906 /* 130345 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
43907 /* 130347 */ GIR_RootConstrainSelectedInstOperands,
43908 /* 130348 */ // GIR_Coverage, 681,
43909 /* 130348 */ GIR_EraseRootFromParent_Done,
43910 /* 130349 */ // Label 1840: @130349
43911 /* 130349 */ GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(130374), // Rule ID 682 //
43912 /* 130354 */ // MIs[0] Operand 2
43913 /* 130354 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
43914 /* 130365 */ // (sext_inreg:{ *:[i64] } i64:{ *:[i64] }:$RST, i16:{ *:[Other] }) => (EXTSH8:{ *:[i64] } i64:{ *:[i64] }:$RST)
43915 /* 130365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EXTSH8),
43916 /* 130368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
43917 /* 130370 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
43918 /* 130372 */ GIR_RootConstrainSelectedInstOperands,
43919 /* 130373 */ // GIR_Coverage, 682,
43920 /* 130373 */ GIR_EraseRootFromParent_Done,
43921 /* 130374 */ // Label 1841: @130374
43922 /* 130374 */ GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(130399), // Rule ID 683 //
43923 /* 130379 */ // MIs[0] Operand 2
43924 /* 130379 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
43925 /* 130390 */ // (sext_inreg:{ *:[i64] } i64:{ *:[i64] }:$RST, i32:{ *:[Other] }) => (EXTSW:{ *:[i64] } i64:{ *:[i64] }:$RST)
43926 /* 130390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EXTSW),
43927 /* 130393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
43928 /* 130395 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
43929 /* 130397 */ GIR_RootConstrainSelectedInstOperands,
43930 /* 130398 */ // GIR_Coverage, 683,
43931 /* 130398 */ GIR_EraseRootFromParent_Done,
43932 /* 130399 */ // Label 1842: @130399
43933 /* 130399 */ GIM_Reject,
43934 /* 130400 */ // Label 1839: @130400
43935 /* 130400 */ GIM_Reject,
43936 /* 130401 */ // Label 1833: @130401
43937 /* 130401 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(130498),
43938 /* 130406 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
43939 /* 130409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
43940 /* 130413 */ GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(130441), // Rule ID 1456 //
43941 /* 130418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
43942 /* 130421 */ // MIs[0] Operand 2
43943 /* 130421 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
43944 /* 130432 */ // (sext_inreg:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VRB, v2i8:{ *:[Other] }) => (VEXTSB2D:{ *:[v2i64] } ?:{ *:[v2i64] }:$VRB)
43945 /* 130432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSB2D),
43946 /* 130435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
43947 /* 130437 */ GIR_RootToRootCopy, /*OpIdx*/1, // VRB
43948 /* 130439 */ GIR_RootConstrainSelectedInstOperands,
43949 /* 130440 */ // GIR_Coverage, 1456,
43950 /* 130440 */ GIR_EraseRootFromParent_Done,
43951 /* 130441 */ // Label 1844: @130441
43952 /* 130441 */ GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(130469), // Rule ID 1457 //
43953 /* 130446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
43954 /* 130449 */ // MIs[0] Operand 2
43955 /* 130449 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
43956 /* 130460 */ // (sext_inreg:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VRB, v2i16:{ *:[Other] }) => (VEXTSH2D:{ *:[v2i64] } ?:{ *:[v2i64] }:$VRB)
43957 /* 130460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSH2D),
43958 /* 130463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
43959 /* 130465 */ GIR_RootToRootCopy, /*OpIdx*/1, // VRB
43960 /* 130467 */ GIR_RootConstrainSelectedInstOperands,
43961 /* 130468 */ // GIR_Coverage, 1457,
43962 /* 130468 */ GIR_EraseRootFromParent_Done,
43963 /* 130469 */ // Label 1845: @130469
43964 /* 130469 */ GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(130497), // Rule ID 1458 //
43965 /* 130474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
43966 /* 130477 */ // MIs[0] Operand 2
43967 /* 130477 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
43968 /* 130488 */ // (sext_inreg:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VRB, v2i32:{ *:[Other] }) => (VEXTSW2D:{ *:[v2i64] } ?:{ *:[v2i64] }:$VRB)
43969 /* 130488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSW2D),
43970 /* 130491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
43971 /* 130493 */ GIR_RootToRootCopy, /*OpIdx*/1, // VRB
43972 /* 130495 */ GIR_RootConstrainSelectedInstOperands,
43973 /* 130496 */ // GIR_Coverage, 1458,
43974 /* 130496 */ GIR_EraseRootFromParent_Done,
43975 /* 130497 */ // Label 1846: @130497
43976 /* 130497 */ GIM_Reject,
43977 /* 130498 */ // Label 1843: @130498
43978 /* 130498 */ GIM_Reject,
43979 /* 130499 */ // Label 1834: @130499
43980 /* 130499 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(130568),
43981 /* 130504 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43982 /* 130507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
43983 /* 130511 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(130539), // Rule ID 1454 //
43984 /* 130516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
43985 /* 130519 */ // MIs[0] Operand 2
43986 /* 130519 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
43987 /* 130530 */ // (sext_inreg:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VRB, v4i8:{ *:[Other] }) => (VEXTSB2W:{ *:[v4i32] } ?:{ *:[v4i32] }:$VRB)
43988 /* 130530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSB2W),
43989 /* 130533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
43990 /* 130535 */ GIR_RootToRootCopy, /*OpIdx*/1, // VRB
43991 /* 130537 */ GIR_RootConstrainSelectedInstOperands,
43992 /* 130538 */ // GIR_Coverage, 1454,
43993 /* 130538 */ GIR_EraseRootFromParent_Done,
43994 /* 130539 */ // Label 1848: @130539
43995 /* 130539 */ GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(130567), // Rule ID 1455 //
43996 /* 130544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
43997 /* 130547 */ // MIs[0] Operand 2
43998 /* 130547 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
43999 /* 130558 */ // (sext_inreg:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VRB, v4i16:{ *:[Other] }) => (VEXTSH2W:{ *:[v4i32] } ?:{ *:[v4i32] }:$VRB)
44000 /* 130558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSH2W),
44001 /* 130561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
44002 /* 130563 */ GIR_RootToRootCopy, /*OpIdx*/1, // VRB
44003 /* 130565 */ GIR_RootConstrainSelectedInstOperands,
44004 /* 130566 */ // GIR_Coverage, 1455,
44005 /* 130566 */ GIR_EraseRootFromParent_Done,
44006 /* 130567 */ // Label 1849: @130567
44007 /* 130567 */ GIM_Reject,
44008 /* 130568 */ // Label 1847: @130568
44009 /* 130568 */ GIM_Reject,
44010 /* 130569 */ // Label 1835: @130569
44011 /* 130569 */ GIM_Reject,
44012 /* 130570 */ // Label 26: @130570
44013 /* 130570 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1852*/ GIMT_Encode4(152039),
44014 /* 130581 */ /*GILLT_s32*//*Label 1850*/ GIMT_Encode4(130589),
44015 /* 130585 */ /*GILLT_s64*//*Label 1851*/ GIMT_Encode4(140810),
44016 /* 130589 */ // Label 1850: @130589
44017 /* 130589 */ GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(140809),
44018 /* 130594 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
44019 /* 130597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
44020 /* 130601 */ GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(130713), // Rule ID 5299 //
44021 /* 130606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44022 /* 130610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44023 /* 130614 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44024 /* 130618 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44025 /* 130622 */ // MIs[1] Operand 1
44026 /* 130622 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
44027 /* 130627 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
44028 /* 130631 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
44029 /* 130635 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
44030 /* 130639 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
44031 /* 130643 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
44032 /* 130647 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
44033 /* 130651 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
44034 /* 130655 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
44035 /* 130659 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
44036 /* 130663 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44037 /* 130667 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
44038 /* 130669 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa), i32:{ *:[i32] }:$s1), 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] })
44039 /* 130669 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44040 /* 130672 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
44041 /* 130676 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44042 /* 130681 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/2, // sa
44043 /* 130685 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
44044 /* 130688 */ GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for PPC::CARRY*/0,
44045 /* 130691 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44046 /* 130693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
44047 /* 130696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44048 /* 130698 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // s1
44049 /* 130702 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44050 /* 130705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44051 /* 130708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44052 /* 130711 */ GIR_RootConstrainSelectedInstOperands,
44053 /* 130712 */ // GIR_Coverage, 5299,
44054 /* 130712 */ GIR_EraseRootFromParent_Done,
44055 /* 130713 */ // Label 1854: @130713
44056 /* 130713 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(130852), // Rule ID 5302 //
44057 /* 130718 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44058 /* 130722 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44059 /* 130726 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44060 /* 130730 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44061 /* 130734 */ // MIs[1] Operand 1
44062 /* 130734 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
44063 /* 130739 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
44064 /* 130743 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
44065 /* 130747 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
44066 /* 130751 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
44067 /* 130755 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
44068 /* 130759 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
44069 /* 130763 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
44070 /* 130767 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
44071 /* 130771 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
44072 /* 130775 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44073 /* 130779 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
44074 /* 130781 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa), i64:{ *:[i64] }:$s1), 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] }), sub_32:{ *:[i32] })
44075 /* 130781 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44076 /* 130784 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
44077 /* 130788 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44078 /* 130793 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
44079 /* 130797 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/64,
44080 /* 130800 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
44081 /* 130803 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44082 /* 130805 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44083 /* 130808 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
44084 /* 130812 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44085 /* 130817 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
44086 /* 130821 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44087 /* 130824 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44088 /* 130827 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44089 /* 130829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44090 /* 130832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44091 /* 130834 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44092 /* 130841 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44093 /* 130846 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44094 /* 130851 */ // GIR_Coverage, 5302,
44095 /* 130851 */ GIR_EraseRootFromParent_Done,
44096 /* 130852 */ // Label 1855: @130852
44097 /* 130852 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(130985), // Rule ID 5307 //
44098 /* 130857 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44099 /* 130861 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44100 /* 130865 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44101 /* 130869 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44102 /* 130873 */ // MIs[1] Operand 1
44103 /* 130873 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
44104 /* 130878 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
44105 /* 130882 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
44106 /* 130886 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
44107 /* 130890 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
44108 /* 130894 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
44109 /* 130898 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
44110 /* 130902 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
44111 /* 130906 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
44112 /* 130910 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
44113 /* 130914 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44114 /* 130918 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
44115 /* 130920 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa), i32:{ *:[i32] }:$s1), 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (RLWNM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] })
44116 /* 130920 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44117 /* 130923 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
44118 /* 130927 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44119 /* 130932 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
44120 /* 130936 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/32,
44121 /* 130939 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
44122 /* 130942 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44123 /* 130944 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44124 /* 130947 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
44125 /* 130951 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44126 /* 130956 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
44127 /* 130960 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
44128 /* 130964 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44129 /* 130966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
44130 /* 130969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44131 /* 130971 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44132 /* 130974 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
44133 /* 130977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44134 /* 130980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44135 /* 130983 */ GIR_RootConstrainSelectedInstOperands,
44136 /* 130984 */ // GIR_Coverage, 5307,
44137 /* 130984 */ GIR_EraseRootFromParent_Done,
44138 /* 130985 */ // Label 1856: @130985
44139 /* 130985 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(131145), // Rule ID 5310 //
44140 /* 130990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44141 /* 130994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44142 /* 130998 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44143 /* 131002 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44144 /* 131006 */ // MIs[1] Operand 1
44145 /* 131006 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
44146 /* 131011 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
44147 /* 131015 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
44148 /* 131019 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
44149 /* 131023 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
44150 /* 131027 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
44151 /* 131031 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
44152 /* 131035 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
44153 /* 131039 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
44154 /* 131043 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
44155 /* 131047 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44156 /* 131051 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
44157 /* 131053 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa), i64:{ *:[i64] }:$s1), 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDCL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] }), sub_32:{ *:[i32] })
44158 /* 131053 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
44159 /* 131056 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
44160 /* 131060 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44161 /* 131065 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, // sa
44162 /* 131069 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/64,
44163 /* 131072 */ GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for PPC::CARRY*/0,
44164 /* 131075 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44165 /* 131077 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44166 /* 131080 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
44167 /* 131084 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44168 /* 131089 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // s1
44169 /* 131093 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // s1
44170 /* 131097 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44171 /* 131099 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44172 /* 131102 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
44173 /* 131106 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44174 /* 131111 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44175 /* 131114 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
44176 /* 131117 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44177 /* 131120 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44178 /* 131122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44179 /* 131125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44180 /* 131127 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44181 /* 131134 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44182 /* 131139 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44183 /* 131144 */ // GIR_Coverage, 5310,
44184 /* 131144 */ GIR_EraseRootFromParent_Done,
44185 /* 131145 */ // Label 1857: @131145
44186 /* 131145 */ GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(131257), // Rule ID 3777 //
44187 /* 131150 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44188 /* 131154 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44189 /* 131158 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44190 /* 131162 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44191 /* 131166 */ // MIs[1] Operand 1
44192 /* 131166 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
44193 /* 131171 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
44194 /* 131175 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
44195 /* 131179 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
44196 /* 131183 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
44197 /* 131187 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
44198 /* 131191 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
44199 /* 131195 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
44200 /* 131199 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
44201 /* 131203 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
44202 /* 131207 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44203 /* 131211 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
44204 /* 131213 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i32] } i32:{ *:[i32] }:$s1, (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] })
44205 /* 131213 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44206 /* 131216 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
44207 /* 131220 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44208 /* 131225 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/2, // sa
44209 /* 131229 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
44210 /* 131232 */ GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for PPC::CARRY*/0,
44211 /* 131235 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44212 /* 131237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
44213 /* 131240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44214 /* 131242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // s1
44215 /* 131246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44216 /* 131249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44217 /* 131252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44218 /* 131255 */ GIR_RootConstrainSelectedInstOperands,
44219 /* 131256 */ // GIR_Coverage, 3777,
44220 /* 131256 */ GIR_EraseRootFromParent_Done,
44221 /* 131257 */ // Label 1858: @131257
44222 /* 131257 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(131396), // Rule ID 3780 //
44223 /* 131262 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44224 /* 131266 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44225 /* 131270 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44226 /* 131274 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44227 /* 131278 */ // MIs[1] Operand 1
44228 /* 131278 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
44229 /* 131283 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
44230 /* 131287 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
44231 /* 131291 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
44232 /* 131295 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
44233 /* 131299 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
44234 /* 131303 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
44235 /* 131307 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
44236 /* 131311 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
44237 /* 131315 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
44238 /* 131319 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44239 /* 131323 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
44240 /* 131325 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i64] } i64:{ *:[i64] }:$s1, (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] }), sub_32:{ *:[i32] })
44241 /* 131325 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44242 /* 131328 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
44243 /* 131332 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44244 /* 131337 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
44245 /* 131341 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/64,
44246 /* 131344 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
44247 /* 131347 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44248 /* 131349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44249 /* 131352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
44250 /* 131356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44251 /* 131361 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
44252 /* 131365 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44253 /* 131368 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44254 /* 131371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44255 /* 131373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44256 /* 131376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44257 /* 131378 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44258 /* 131385 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44259 /* 131390 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44260 /* 131395 */ // GIR_Coverage, 3780,
44261 /* 131395 */ GIR_EraseRootFromParent_Done,
44262 /* 131396 */ // Label 1859: @131396
44263 /* 131396 */ GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(131529), // Rule ID 3785 //
44264 /* 131401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44265 /* 131405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44266 /* 131409 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44267 /* 131413 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44268 /* 131417 */ // MIs[1] Operand 1
44269 /* 131417 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
44270 /* 131422 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
44271 /* 131426 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
44272 /* 131430 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
44273 /* 131434 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
44274 /* 131438 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
44275 /* 131442 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
44276 /* 131446 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
44277 /* 131450 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
44278 /* 131454 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
44279 /* 131458 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44280 /* 131462 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
44281 /* 131464 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i32] } i32:{ *:[i32] }:$s1, (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (RLWNM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] })
44282 /* 131464 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44283 /* 131467 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
44284 /* 131471 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44285 /* 131476 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
44286 /* 131480 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/32,
44287 /* 131483 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
44288 /* 131486 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44289 /* 131488 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44290 /* 131491 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
44291 /* 131495 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44292 /* 131500 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
44293 /* 131504 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
44294 /* 131508 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44295 /* 131510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
44296 /* 131513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44297 /* 131515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44298 /* 131518 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
44299 /* 131521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44300 /* 131524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44301 /* 131527 */ GIR_RootConstrainSelectedInstOperands,
44302 /* 131528 */ // GIR_Coverage, 3785,
44303 /* 131528 */ GIR_EraseRootFromParent_Done,
44304 /* 131529 */ // Label 1860: @131529
44305 /* 131529 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(131689), // Rule ID 3788 //
44306 /* 131534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44307 /* 131538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44308 /* 131542 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44309 /* 131546 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44310 /* 131550 */ // MIs[1] Operand 1
44311 /* 131550 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
44312 /* 131555 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
44313 /* 131559 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
44314 /* 131563 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
44315 /* 131567 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
44316 /* 131571 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
44317 /* 131575 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
44318 /* 131579 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
44319 /* 131583 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
44320 /* 131587 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
44321 /* 131591 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44322 /* 131595 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
44323 /* 131597 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } (and:{ *:[i64] } i64:{ *:[i64] }:$s1, (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDCL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] }), sub_32:{ *:[i32] })
44324 /* 131597 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
44325 /* 131600 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
44326 /* 131604 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44327 /* 131609 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, // sa
44328 /* 131613 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/64,
44329 /* 131616 */ GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for PPC::CARRY*/0,
44330 /* 131619 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44331 /* 131621 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44332 /* 131624 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
44333 /* 131628 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44334 /* 131633 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // s1
44335 /* 131637 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // s1
44336 /* 131641 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44337 /* 131643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44338 /* 131646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
44339 /* 131650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44340 /* 131655 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44341 /* 131658 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
44342 /* 131661 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44343 /* 131664 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44344 /* 131666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44345 /* 131669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44346 /* 131671 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44347 /* 131678 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44348 /* 131683 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44349 /* 131688 */ // GIR_Coverage, 3788,
44350 /* 131688 */ GIR_EraseRootFromParent_Done,
44351 /* 131689 */ // Label 1861: @131689
44352 /* 131689 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(131758), // Rule ID 3697 //
44353 /* 131694 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44354 /* 131698 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44355 /* 131702 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44356 /* 131706 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44357 /* 131710 */ // MIs[1] Operand 1
44358 /* 131710 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
44359 /* 131715 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44360 /* 131719 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44361 /* 131721 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (RLWINM:{ *:[i32] } (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1), 27:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44362 /* 131721 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44363 /* 131724 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
44364 /* 131728 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44365 /* 131733 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44366 /* 131737 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44367 /* 131739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44368 /* 131742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44369 /* 131744 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44370 /* 131747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/27,
44371 /* 131750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44372 /* 131753 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44373 /* 131756 */ GIR_RootConstrainSelectedInstOperands,
44374 /* 131757 */ // GIR_Coverage, 3697,
44375 /* 131757 */ GIR_EraseRootFromParent_Done,
44376 /* 131758 */ // Label 1862: @131758
44377 /* 131758 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(131854), // Rule ID 3700 //
44378 /* 131763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44379 /* 131767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44380 /* 131771 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44381 /* 131775 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44382 /* 131779 */ // MIs[1] Operand 1
44383 /* 131779 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
44384 /* 131784 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44385 /* 131788 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44386 /* 131790 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1), 58:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44387 /* 131790 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44388 /* 131793 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
44389 /* 131797 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44390 /* 131802 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44391 /* 131806 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44392 /* 131808 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44393 /* 131811 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44394 /* 131815 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44395 /* 131820 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44396 /* 131823 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/58,
44397 /* 131826 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44398 /* 131829 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44399 /* 131831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44400 /* 131834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44401 /* 131836 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44402 /* 131843 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44403 /* 131848 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44404 /* 131853 */ // GIR_Coverage, 3700,
44405 /* 131853 */ GIR_EraseRootFromParent_Done,
44406 /* 131854 */ // Label 1863: @131854
44407 /* 131854 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(131961), // Rule ID 3705 //
44408 /* 131859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44409 /* 131863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44410 /* 131867 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44411 /* 131871 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44412 /* 131875 */ // MIs[1] Operand 1
44413 /* 131875 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
44414 /* 131880 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44415 /* 131884 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44416 /* 131886 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1), (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1)), 27:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44417 /* 131886 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
44418 /* 131889 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
44419 /* 131893 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44420 /* 131898 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
44421 /* 131902 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44422 /* 131904 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44423 /* 131907 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
44424 /* 131911 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44425 /* 131916 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44426 /* 131920 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44427 /* 131922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44428 /* 131925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
44429 /* 131929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44430 /* 131934 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44431 /* 131937 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
44432 /* 131940 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44433 /* 131942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44434 /* 131945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44435 /* 131947 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44436 /* 131950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/27,
44437 /* 131953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44438 /* 131956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44439 /* 131959 */ GIR_RootConstrainSelectedInstOperands,
44440 /* 131960 */ // GIR_Coverage, 3705,
44441 /* 131960 */ GIR_EraseRootFromParent_Done,
44442 /* 131961 */ // Label 1864: @131961
44443 /* 131961 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(132095), // Rule ID 3708 //
44444 /* 131966 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44445 /* 131970 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44446 /* 131974 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44447 /* 131978 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44448 /* 131982 */ // MIs[1] Operand 1
44449 /* 131982 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
44450 /* 131987 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44451 /* 131991 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44452 /* 131993 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1), (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1)), 58:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44453 /* 131993 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
44454 /* 131996 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
44455 /* 132000 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44456 /* 132005 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
44457 /* 132009 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
44458 /* 132011 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
44459 /* 132014 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
44460 /* 132018 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44461 /* 132023 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
44462 /* 132027 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44463 /* 132029 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44464 /* 132032 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
44465 /* 132036 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44466 /* 132041 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44467 /* 132044 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
44468 /* 132047 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44469 /* 132049 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44470 /* 132052 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44471 /* 132056 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44472 /* 132061 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44473 /* 132064 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/58,
44474 /* 132067 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44475 /* 132070 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44476 /* 132072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44477 /* 132075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44478 /* 132077 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44479 /* 132084 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44480 /* 132089 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44481 /* 132094 */ // GIR_Coverage, 3708,
44482 /* 132094 */ GIR_EraseRootFromParent_Done,
44483 /* 132095 */ // Label 1865: @132095
44484 /* 132095 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(132147), // Rule ID 3713 //
44485 /* 132100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44486 /* 132104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44487 /* 132108 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44488 /* 132112 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44489 /* 132116 */ // MIs[1] Operand 1
44490 /* 132116 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
44491 /* 132121 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44492 /* 132125 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44493 /* 132127 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETLT:{ *:[Other] })) => (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44494 /* 132127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44495 /* 132130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44496 /* 132132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // s1
44497 /* 132136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44498 /* 132139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44499 /* 132142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44500 /* 132145 */ GIR_RootConstrainSelectedInstOperands,
44501 /* 132146 */ // GIR_Coverage, 3713,
44502 /* 132146 */ GIR_EraseRootFromParent_Done,
44503 /* 132147 */ // Label 1866: @132147
44504 /* 132147 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(132226), // Rule ID 3716 //
44505 /* 132152 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44506 /* 132156 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44507 /* 132160 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44508 /* 132164 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44509 /* 132168 */ // MIs[1] Operand 1
44510 /* 132168 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
44511 /* 132173 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44512 /* 132177 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44513 /* 132179 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETLT:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44514 /* 132179 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44515 /* 132182 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44516 /* 132186 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44517 /* 132191 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44518 /* 132195 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
44519 /* 132198 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44520 /* 132201 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44521 /* 132203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44522 /* 132206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44523 /* 132208 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44524 /* 132215 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44525 /* 132220 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44526 /* 132225 */ // GIR_Coverage, 3716,
44527 /* 132225 */ GIR_EraseRootFromParent_Done,
44528 /* 132226 */ // Label 1867: @132226
44529 /* 132226 */ GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(132299), // Rule ID 3721 //
44530 /* 132231 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44531 /* 132235 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44532 /* 132239 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44533 /* 132243 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44534 /* 132247 */ // MIs[1] Operand 1
44535 /* 132247 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
44536 /* 132252 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44537 /* 132256 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44538 /* 132258 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETGE:{ *:[Other] })) => (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44539 /* 132258 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44540 /* 132261 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
44541 /* 132265 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44542 /* 132270 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44543 /* 132274 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44544 /* 132278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44545 /* 132280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44546 /* 132283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44547 /* 132285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44548 /* 132288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44549 /* 132291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44550 /* 132294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44551 /* 132297 */ GIR_RootConstrainSelectedInstOperands,
44552 /* 132298 */ // GIR_Coverage, 3721,
44553 /* 132298 */ GIR_EraseRootFromParent_Done,
44554 /* 132299 */ // Label 1868: @132299
44555 /* 132299 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(132399), // Rule ID 3724 //
44556 /* 132304 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44557 /* 132308 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44558 /* 132312 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44559 /* 132316 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44560 /* 132320 */ // MIs[1] Operand 1
44561 /* 132320 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
44562 /* 132325 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44563 /* 132329 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44564 /* 132331 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETGE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44565 /* 132331 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44566 /* 132334 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
44567 /* 132338 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44568 /* 132343 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44569 /* 132347 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44570 /* 132351 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44571 /* 132353 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44572 /* 132356 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44573 /* 132360 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44574 /* 132365 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44575 /* 132368 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
44576 /* 132371 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44577 /* 132374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44578 /* 132376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44579 /* 132379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44580 /* 132381 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44581 /* 132388 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44582 /* 132393 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44583 /* 132398 */ // GIR_Coverage, 3724,
44584 /* 132398 */ GIR_EraseRootFromParent_Done,
44585 /* 132399 */ // Label 1869: @132399
44586 /* 132399 */ GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(132489), // Rule ID 3729 //
44587 /* 132404 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44588 /* 132408 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44589 /* 132412 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44590 /* 132416 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44591 /* 132420 */ // MIs[1] Operand 1
44592 /* 132420 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
44593 /* 132425 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44594 /* 132429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44595 /* 132431 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETGT:{ *:[Other] })) => (RLWINM:{ *:[i32] } (ANDC:{ *:[i32] } (NEG:{ *:[i32] } ?:{ *:[i32] }:$s1), ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44596 /* 132431 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44597 /* 132434 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NEG),
44598 /* 132438 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44599 /* 132443 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44600 /* 132447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44601 /* 132449 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44602 /* 132452 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::ANDC),
44603 /* 132456 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44604 /* 132461 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44605 /* 132464 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44606 /* 132468 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44607 /* 132470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44608 /* 132473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44609 /* 132475 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44610 /* 132478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44611 /* 132481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44612 /* 132484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44613 /* 132487 */ GIR_RootConstrainSelectedInstOperands,
44614 /* 132488 */ // GIR_Coverage, 3729,
44615 /* 132488 */ GIR_EraseRootFromParent_Done,
44616 /* 132489 */ // Label 1870: @132489
44617 /* 132489 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(132606), // Rule ID 3732 //
44618 /* 132494 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44619 /* 132498 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44620 /* 132502 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44621 /* 132506 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44622 /* 132510 */ // MIs[1] Operand 1
44623 /* 132510 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
44624 /* 132515 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44625 /* 132519 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44626 /* 132521 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETGT:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (ANDC8:{ *:[i64] } (NEG8:{ *:[i64] } ?:{ *:[i64] }:$s1), ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44627 /* 132521 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
44628 /* 132524 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NEG8),
44629 /* 132528 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44630 /* 132533 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
44631 /* 132537 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44632 /* 132539 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44633 /* 132542 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ANDC8),
44634 /* 132546 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44635 /* 132551 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44636 /* 132554 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44637 /* 132558 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44638 /* 132560 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44639 /* 132563 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44640 /* 132567 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44641 /* 132572 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44642 /* 132575 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
44643 /* 132578 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44644 /* 132581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44645 /* 132583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44646 /* 132586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44647 /* 132588 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44648 /* 132595 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44649 /* 132600 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44650 /* 132605 */ // GIR_Coverage, 3732,
44651 /* 132605 */ GIR_EraseRootFromParent_Done,
44652 /* 132606 */ // Label 1871: @132606
44653 /* 132606 */ GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(132696), // Rule ID 3737 //
44654 /* 132611 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44655 /* 132615 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44656 /* 132619 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44657 /* 132623 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44658 /* 132627 */ // MIs[1] Operand 1
44659 /* 132627 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
44660 /* 132632 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44661 /* 132636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44662 /* 132638 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETLE:{ *:[Other] })) => (RLWINM:{ *:[i32] } (ORC:{ *:[i32] } ?:{ *:[i32] }:$s1, (NEG:{ *:[i32] } ?:{ *:[i32] }:$s1)), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44663 /* 132638 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44664 /* 132641 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NEG),
44665 /* 132645 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44666 /* 132650 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44667 /* 132654 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44668 /* 132656 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44669 /* 132659 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::ORC),
44670 /* 132663 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44671 /* 132668 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44672 /* 132672 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44673 /* 132675 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44674 /* 132677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44675 /* 132680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44676 /* 132682 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44677 /* 132685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44678 /* 132688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44679 /* 132691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44680 /* 132694 */ GIR_RootConstrainSelectedInstOperands,
44681 /* 132695 */ // GIR_Coverage, 3737,
44682 /* 132695 */ GIR_EraseRootFromParent_Done,
44683 /* 132696 */ // Label 1872: @132696
44684 /* 132696 */ GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(132813), // Rule ID 3740 //
44685 /* 132701 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44686 /* 132705 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44687 /* 132709 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44688 /* 132713 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44689 /* 132717 */ // MIs[1] Operand 1
44690 /* 132717 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
44691 /* 132722 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
44692 /* 132726 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44693 /* 132728 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETLE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (ORC8:{ *:[i64] } ?:{ *:[i64] }:$s1, (NEG8:{ *:[i64] } ?:{ *:[i64] }:$s1)), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44694 /* 132728 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
44695 /* 132731 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NEG8),
44696 /* 132735 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44697 /* 132740 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
44698 /* 132744 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44699 /* 132746 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44700 /* 132749 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ORC8),
44701 /* 132753 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44702 /* 132758 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44703 /* 132762 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44704 /* 132765 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44705 /* 132767 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44706 /* 132770 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44707 /* 132774 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44708 /* 132779 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44709 /* 132782 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
44710 /* 132785 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44711 /* 132788 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44712 /* 132790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44713 /* 132793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44714 /* 132795 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44715 /* 132802 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44716 /* 132807 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44717 /* 132812 */ // GIR_Coverage, 3740,
44718 /* 132812 */ GIR_EraseRootFromParent_Done,
44719 /* 132813 */ // Label 1873: @132813
44720 /* 132813 */ GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(132906), // Rule ID 3745 //
44721 /* 132818 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44722 /* 132822 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44723 /* 132826 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44724 /* 132830 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44725 /* 132834 */ // MIs[1] Operand 1
44726 /* 132834 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
44727 /* 132839 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
44728 /* 132843 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44729 /* 132845 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETLT:{ *:[Other] })) => (RLWINM:{ *:[i32] } (AND:{ *:[i32] } ?:{ *:[i32] }:$s1, (ADDI:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] })), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44730 /* 132845 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44731 /* 132848 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ADDI),
44732 /* 132852 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44733 /* 132857 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44734 /* 132861 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
44735 /* 132864 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44736 /* 132866 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44737 /* 132869 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::AND),
44738 /* 132873 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44739 /* 132878 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44740 /* 132882 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44741 /* 132885 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44742 /* 132887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44743 /* 132890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44744 /* 132892 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44745 /* 132895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44746 /* 132898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44747 /* 132901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44748 /* 132904 */ GIR_RootConstrainSelectedInstOperands,
44749 /* 132905 */ // GIR_Coverage, 3745,
44750 /* 132905 */ GIR_EraseRootFromParent_Done,
44751 /* 132906 */ // Label 1874: @132906
44752 /* 132906 */ GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(133026), // Rule ID 3748 //
44753 /* 132911 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44754 /* 132915 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44755 /* 132919 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44756 /* 132923 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44757 /* 132927 */ // MIs[1] Operand 1
44758 /* 132927 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
44759 /* 132932 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
44760 /* 132936 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44761 /* 132938 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETLT:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (AND8:{ *:[i64] } ?:{ *:[i64] }:$s1, (ADDI8:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i64] })), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44762 /* 132938 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
44763 /* 132941 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
44764 /* 132945 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44765 /* 132950 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
44766 /* 132954 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
44767 /* 132957 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44768 /* 132959 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44769 /* 132962 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::AND8),
44770 /* 132966 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44771 /* 132971 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44772 /* 132975 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44773 /* 132978 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44774 /* 132980 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44775 /* 132983 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44776 /* 132987 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44777 /* 132992 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44778 /* 132995 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
44779 /* 132998 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44780 /* 133001 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44781 /* 133003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44782 /* 133006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44783 /* 133008 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44784 /* 133015 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44785 /* 133020 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44786 /* 133025 */ // GIR_Coverage, 3748,
44787 /* 133025 */ GIR_EraseRootFromParent_Done,
44788 /* 133026 */ // Label 1875: @133026
44789 /* 133026 */ GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(133119), // Rule ID 3753 //
44790 /* 133031 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44791 /* 133035 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44792 /* 133039 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44793 /* 133043 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44794 /* 133047 */ // MIs[1] Operand 1
44795 /* 133047 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
44796 /* 133052 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
44797 /* 133056 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44798 /* 133058 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETGE:{ *:[Other] })) => (RLWINM:{ *:[i32] } (NAND:{ *:[i32] } ?:{ *:[i32] }:$s1, (ADDI:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] })), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44799 /* 133058 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44800 /* 133061 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ADDI),
44801 /* 133065 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44802 /* 133070 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44803 /* 133074 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
44804 /* 133077 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44805 /* 133079 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44806 /* 133082 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NAND),
44807 /* 133086 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44808 /* 133091 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44809 /* 133095 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44810 /* 133098 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44811 /* 133100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44812 /* 133103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44813 /* 133105 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44814 /* 133108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44815 /* 133111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44816 /* 133114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44817 /* 133117 */ GIR_RootConstrainSelectedInstOperands,
44818 /* 133118 */ // GIR_Coverage, 3753,
44819 /* 133118 */ GIR_EraseRootFromParent_Done,
44820 /* 133119 */ // Label 1876: @133119
44821 /* 133119 */ GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(133239), // Rule ID 3756 //
44822 /* 133124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44823 /* 133128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44824 /* 133132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44825 /* 133136 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44826 /* 133140 */ // MIs[1] Operand 1
44827 /* 133140 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
44828 /* 133145 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
44829 /* 133149 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44830 /* 133151 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETGE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (NAND8:{ *:[i64] } ?:{ *:[i64] }:$s1, (ADDI8:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i64] })), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44831 /* 133151 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
44832 /* 133154 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
44833 /* 133158 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44834 /* 133163 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
44835 /* 133167 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
44836 /* 133170 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44837 /* 133172 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44838 /* 133175 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NAND8),
44839 /* 133179 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44840 /* 133184 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44841 /* 133188 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44842 /* 133191 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44843 /* 133193 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44844 /* 133196 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44845 /* 133200 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44846 /* 133205 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44847 /* 133208 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
44848 /* 133211 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44849 /* 133214 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44850 /* 133216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44851 /* 133219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44852 /* 133221 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44853 /* 133228 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44854 /* 133233 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44855 /* 133238 */ // GIR_Coverage, 3756,
44856 /* 133238 */ GIR_EraseRootFromParent_Done,
44857 /* 133239 */ // Label 1877: @133239
44858 /* 133239 */ GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(133312), // Rule ID 3761 //
44859 /* 133244 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44860 /* 133248 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44861 /* 133252 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44862 /* 133256 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44863 /* 133260 */ // MIs[1] Operand 1
44864 /* 133260 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
44865 /* 133265 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
44866 /* 133269 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44867 /* 133271 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETGT:{ *:[Other] })) => (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44868 /* 133271 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44869 /* 133274 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR),
44870 /* 133278 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44871 /* 133283 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44872 /* 133287 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44873 /* 133291 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44874 /* 133293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44875 /* 133296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44876 /* 133298 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44877 /* 133301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44878 /* 133304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44879 /* 133307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44880 /* 133310 */ GIR_RootConstrainSelectedInstOperands,
44881 /* 133311 */ // GIR_Coverage, 3761,
44882 /* 133311 */ GIR_EraseRootFromParent_Done,
44883 /* 133312 */ // Label 1878: @133312
44884 /* 133312 */ GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(133412), // Rule ID 3764 //
44885 /* 133317 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44886 /* 133321 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44887 /* 133325 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44888 /* 133329 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44889 /* 133333 */ // MIs[1] Operand 1
44890 /* 133333 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
44891 /* 133338 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
44892 /* 133342 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44893 /* 133344 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETGT:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44894 /* 133344 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
44895 /* 133347 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NOR8),
44896 /* 133351 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44897 /* 133356 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44898 /* 133360 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44899 /* 133364 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44900 /* 133366 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44901 /* 133369 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44902 /* 133373 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44903 /* 133378 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44904 /* 133381 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
44905 /* 133384 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44906 /* 133387 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44907 /* 133389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44908 /* 133392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44909 /* 133394 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44910 /* 133401 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44911 /* 133406 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44912 /* 133411 */ // GIR_Coverage, 3764,
44913 /* 133411 */ GIR_EraseRootFromParent_Done,
44914 /* 133412 */ // Label 1879: @133412
44915 /* 133412 */ GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(133464), // Rule ID 3769 //
44916 /* 133417 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44917 /* 133421 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44918 /* 133425 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44919 /* 133429 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44920 /* 133433 */ // MIs[1] Operand 1
44921 /* 133433 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
44922 /* 133438 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
44923 /* 133442 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44924 /* 133444 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETLE:{ *:[Other] })) => (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] })
44925 /* 133444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
44926 /* 133447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
44927 /* 133449 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // s1
44928 /* 133453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44929 /* 133456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44930 /* 133459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
44931 /* 133462 */ GIR_RootConstrainSelectedInstOperands,
44932 /* 133463 */ // GIR_Coverage, 3769,
44933 /* 133463 */ GIR_EraseRootFromParent_Done,
44934 /* 133464 */ // Label 1880: @133464
44935 /* 133464 */ GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(133543), // Rule ID 3772 //
44936 /* 133469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44937 /* 133473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44938 /* 133477 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44939 /* 133481 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44940 /* 133485 */ // MIs[1] Operand 1
44941 /* 133485 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
44942 /* 133490 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
44943 /* 133494 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44944 /* 133496 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETLE:{ *:[Other] })) => (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i32] }, 63:{ *:[i32] }), sub_32:{ *:[i32] })
44945 /* 133496 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44946 /* 133499 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
44947 /* 133503 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44948 /* 133508 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
44949 /* 133512 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
44950 /* 133515 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/63,
44951 /* 133518 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44952 /* 133520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44953 /* 133523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44954 /* 133525 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
44955 /* 133532 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
44956 /* 133537 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
44957 /* 133542 */ // GIR_Coverage, 3772,
44958 /* 133542 */ GIR_EraseRootFromParent_Done,
44959 /* 133543 */ // Label 1881: @133543
44960 /* 133543 */ GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(133646), // Rule ID 3036 //
44961 /* 133548 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
44962 /* 133551 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44963 /* 133555 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44964 /* 133559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44965 /* 133563 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
44966 /* 133567 */ // MIs[1] Operand 1
44967 /* 133567 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
44968 /* 133572 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
44969 /* 133576 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
44970 /* 133580 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
44971 /* 133584 */ // MIs[2] Operand 1
44972 /* 133584 */ // No operand predicates
44973 /* 133584 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
44974 /* 133586 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }))
44975 /* 133586 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44976 /* 133589 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
44977 /* 133593 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44978 /* 133598 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
44979 /* 133602 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
44980 /* 133605 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44981 /* 133607 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
44982 /* 133610 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44983 /* 133614 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44984 /* 133619 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
44985 /* 133626 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
44986 /* 133631 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
44987 /* 133636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
44988 /* 133639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
44989 /* 133641 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44990 /* 133644 */ GIR_RootConstrainSelectedInstOperands,
44991 /* 133645 */ // GIR_Coverage, 3036,
44992 /* 133645 */ GIR_EraseRootFromParent_Done,
44993 /* 133646 */ // Label 1882: @133646
44994 /* 133646 */ GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(133749), // Rule ID 3052 //
44995 /* 133651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
44996 /* 133654 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44997 /* 133658 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
44998 /* 133662 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
44999 /* 133666 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45000 /* 133670 */ // MIs[1] Operand 1
45001 /* 133670 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
45002 /* 133675 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45003 /* 133679 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45004 /* 133683 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
45005 /* 133687 */ // MIs[2] Operand 1
45006 /* 133687 */ // No operand predicates
45007 /* 133687 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45008 /* 133689 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }))
45009 /* 133689 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45010 /* 133692 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
45011 /* 133696 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45012 /* 133701 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45013 /* 133705 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45014 /* 133708 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45015 /* 133710 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45016 /* 133713 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45017 /* 133717 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45018 /* 133722 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
45019 /* 133729 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45020 /* 133734 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45021 /* 133739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45022 /* 133742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45023 /* 133744 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45024 /* 133747 */ GIR_RootConstrainSelectedInstOperands,
45025 /* 133748 */ // GIR_Coverage, 3052,
45026 /* 133748 */ GIR_EraseRootFromParent_Done,
45027 /* 133749 */ // Label 1883: @133749
45028 /* 133749 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(133852), // Rule ID 3060 //
45029 /* 133754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
45030 /* 133757 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45031 /* 133761 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45032 /* 133765 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45033 /* 133769 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45034 /* 133773 */ // MIs[1] Operand 1
45035 /* 133773 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
45036 /* 133778 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45037 /* 133782 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45038 /* 133786 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
45039 /* 133790 */ // MIs[2] Operand 1
45040 /* 133790 */ // No operand predicates
45041 /* 133790 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45042 /* 133792 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }))
45043 /* 133792 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45044 /* 133795 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
45045 /* 133799 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45046 /* 133804 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45047 /* 133808 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45048 /* 133811 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45049 /* 133813 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45050 /* 133816 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45051 /* 133820 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45052 /* 133825 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
45053 /* 133832 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45054 /* 133837 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45055 /* 133842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45056 /* 133845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45057 /* 133847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45058 /* 133850 */ GIR_RootConstrainSelectedInstOperands,
45059 /* 133851 */ // GIR_Coverage, 3060,
45060 /* 133851 */ GIR_EraseRootFromParent_Done,
45061 /* 133852 */ // Label 1884: @133852
45062 /* 133852 */ GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(133955), // Rule ID 3132 //
45063 /* 133857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
45064 /* 133860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45065 /* 133864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45066 /* 133868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45067 /* 133872 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45068 /* 133876 */ // MIs[1] Operand 1
45069 /* 133876 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
45070 /* 133881 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45071 /* 133885 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45072 /* 133889 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
45073 /* 133893 */ // MIs[2] Operand 1
45074 /* 133893 */ // No operand predicates
45075 /* 133893 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45076 /* 133895 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }))
45077 /* 133895 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45078 /* 133898 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
45079 /* 133902 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45080 /* 133907 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45081 /* 133911 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45082 /* 133914 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45083 /* 133916 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45084 /* 133919 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45085 /* 133923 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45086 /* 133928 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
45087 /* 133935 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45088 /* 133940 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45089 /* 133945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45090 /* 133948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45091 /* 133950 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45092 /* 133953 */ GIR_RootConstrainSelectedInstOperands,
45093 /* 133954 */ // GIR_Coverage, 3132,
45094 /* 133954 */ GIR_EraseRootFromParent_Done,
45095 /* 133955 */ // Label 1885: @133955
45096 /* 133955 */ GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(134058), // Rule ID 3148 //
45097 /* 133960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
45098 /* 133963 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45099 /* 133967 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45100 /* 133971 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45101 /* 133975 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45102 /* 133979 */ // MIs[1] Operand 1
45103 /* 133979 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
45104 /* 133984 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45105 /* 133988 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45106 /* 133992 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
45107 /* 133996 */ // MIs[2] Operand 1
45108 /* 133996 */ // No operand predicates
45109 /* 133996 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45110 /* 133998 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }))
45111 /* 133998 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45112 /* 134001 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
45113 /* 134005 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45114 /* 134010 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45115 /* 134014 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45116 /* 134017 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45117 /* 134019 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45118 /* 134022 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45119 /* 134026 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45120 /* 134031 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
45121 /* 134038 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45122 /* 134043 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45123 /* 134048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45124 /* 134051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45125 /* 134053 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45126 /* 134056 */ GIR_RootConstrainSelectedInstOperands,
45127 /* 134057 */ // GIR_Coverage, 3148,
45128 /* 134057 */ GIR_EraseRootFromParent_Done,
45129 /* 134058 */ // Label 1886: @134058
45130 /* 134058 */ GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(134161), // Rule ID 3156 //
45131 /* 134063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
45132 /* 134066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45133 /* 134070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45134 /* 134074 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45135 /* 134078 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45136 /* 134082 */ // MIs[1] Operand 1
45137 /* 134082 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
45138 /* 134087 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45139 /* 134091 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45140 /* 134095 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
45141 /* 134099 */ // MIs[2] Operand 1
45142 /* 134099 */ // No operand predicates
45143 /* 134099 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45144 /* 134101 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }))
45145 /* 134101 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45146 /* 134104 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
45147 /* 134108 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45148 /* 134113 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45149 /* 134117 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45150 /* 134120 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45151 /* 134122 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45152 /* 134125 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45153 /* 134129 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45154 /* 134134 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
45155 /* 134141 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45156 /* 134146 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45157 /* 134151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45158 /* 134154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45159 /* 134156 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45160 /* 134159 */ GIR_RootConstrainSelectedInstOperands,
45161 /* 134160 */ // GIR_Coverage, 3156,
45162 /* 134160 */ GIR_EraseRootFromParent_Done,
45163 /* 134161 */ // Label 1887: @134161
45164 /* 134161 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(134304), // Rule ID 3819 //
45165 /* 134166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
45166 /* 134169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45167 /* 134173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45168 /* 134177 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45169 /* 134181 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45170 /* 134185 */ // MIs[1] Operand 1
45171 /* 134185 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
45172 /* 134190 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45173 /* 134194 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45174 /* 134198 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
45175 /* 134202 */ // MIs[2] Operand 1
45176 /* 134202 */ // No operand predicates
45177 /* 134202 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45178 /* 134204 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45179 /* 134204 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45180 /* 134207 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
45181 /* 134211 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45182 /* 134216 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45183 /* 134220 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45184 /* 134223 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45185 /* 134225 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45186 /* 134228 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45187 /* 134232 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45188 /* 134237 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45189 /* 134240 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45190 /* 134242 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45191 /* 134245 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45192 /* 134249 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45193 /* 134254 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45194 /* 134257 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45195 /* 134259 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45196 /* 134262 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45197 /* 134266 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45198 /* 134271 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
45199 /* 134278 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45200 /* 134283 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45201 /* 134288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45202 /* 134291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45203 /* 134293 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45204 /* 134296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45205 /* 134299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45206 /* 134302 */ GIR_RootConstrainSelectedInstOperands,
45207 /* 134303 */ // GIR_Coverage, 3819,
45208 /* 134303 */ GIR_EraseRootFromParent_Done,
45209 /* 134304 */ // Label 1888: @134304
45210 /* 134304 */ GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(134447), // Rule ID 3835 //
45211 /* 134309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
45212 /* 134312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45213 /* 134316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45214 /* 134320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45215 /* 134324 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45216 /* 134328 */ // MIs[1] Operand 1
45217 /* 134328 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
45218 /* 134333 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45219 /* 134337 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45220 /* 134341 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
45221 /* 134345 */ // MIs[2] Operand 1
45222 /* 134345 */ // No operand predicates
45223 /* 134345 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45224 /* 134347 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45225 /* 134347 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45226 /* 134350 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
45227 /* 134354 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45228 /* 134359 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45229 /* 134363 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45230 /* 134366 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45231 /* 134368 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45232 /* 134371 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45233 /* 134375 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45234 /* 134380 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45235 /* 134383 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45236 /* 134385 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45237 /* 134388 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45238 /* 134392 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45239 /* 134397 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45240 /* 134400 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45241 /* 134402 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45242 /* 134405 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45243 /* 134409 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45244 /* 134414 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
45245 /* 134421 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45246 /* 134426 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45247 /* 134431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45248 /* 134434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45249 /* 134436 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45250 /* 134439 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45251 /* 134442 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45252 /* 134445 */ GIR_RootConstrainSelectedInstOperands,
45253 /* 134446 */ // GIR_Coverage, 3835,
45254 /* 134446 */ GIR_EraseRootFromParent_Done,
45255 /* 134447 */ // Label 1889: @134447
45256 /* 134447 */ GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(134590), // Rule ID 3843 //
45257 /* 134452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
45258 /* 134455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45259 /* 134459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45260 /* 134463 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45261 /* 134467 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45262 /* 134471 */ // MIs[1] Operand 1
45263 /* 134471 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
45264 /* 134476 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45265 /* 134480 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45266 /* 134484 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
45267 /* 134488 */ // MIs[2] Operand 1
45268 /* 134488 */ // No operand predicates
45269 /* 134488 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45270 /* 134490 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45271 /* 134490 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45272 /* 134493 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
45273 /* 134497 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45274 /* 134502 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45275 /* 134506 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45276 /* 134509 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45277 /* 134511 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45278 /* 134514 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45279 /* 134518 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45280 /* 134523 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45281 /* 134526 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45282 /* 134528 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45283 /* 134531 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45284 /* 134535 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45285 /* 134540 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45286 /* 134543 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45287 /* 134545 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45288 /* 134548 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45289 /* 134552 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45290 /* 134557 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
45291 /* 134564 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45292 /* 134569 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45293 /* 134574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45294 /* 134577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45295 /* 134579 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45296 /* 134582 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45297 /* 134585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45298 /* 134588 */ GIR_RootConstrainSelectedInstOperands,
45299 /* 134589 */ // GIR_Coverage, 3843,
45300 /* 134589 */ GIR_EraseRootFromParent_Done,
45301 /* 134590 */ // Label 1890: @134590
45302 /* 134590 */ GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(134733), // Rule ID 3915 //
45303 /* 134595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
45304 /* 134598 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45305 /* 134602 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45306 /* 134606 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45307 /* 134610 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45308 /* 134614 */ // MIs[1] Operand 1
45309 /* 134614 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
45310 /* 134619 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45311 /* 134623 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45312 /* 134627 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
45313 /* 134631 */ // MIs[2] Operand 1
45314 /* 134631 */ // No operand predicates
45315 /* 134631 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45316 /* 134633 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45317 /* 134633 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45318 /* 134636 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
45319 /* 134640 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45320 /* 134645 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45321 /* 134649 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45322 /* 134652 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45323 /* 134654 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45324 /* 134657 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45325 /* 134661 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45326 /* 134666 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45327 /* 134669 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45328 /* 134671 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45329 /* 134674 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45330 /* 134678 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45331 /* 134683 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45332 /* 134686 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45333 /* 134688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45334 /* 134691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45335 /* 134695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45336 /* 134700 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
45337 /* 134707 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45338 /* 134712 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45339 /* 134717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45340 /* 134720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45341 /* 134722 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45342 /* 134725 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45343 /* 134728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45344 /* 134731 */ GIR_RootConstrainSelectedInstOperands,
45345 /* 134732 */ // GIR_Coverage, 3915,
45346 /* 134732 */ GIR_EraseRootFromParent_Done,
45347 /* 134733 */ // Label 1891: @134733
45348 /* 134733 */ GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(134876), // Rule ID 3931 //
45349 /* 134738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
45350 /* 134741 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45351 /* 134745 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45352 /* 134749 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45353 /* 134753 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45354 /* 134757 */ // MIs[1] Operand 1
45355 /* 134757 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
45356 /* 134762 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45357 /* 134766 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45358 /* 134770 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
45359 /* 134774 */ // MIs[2] Operand 1
45360 /* 134774 */ // No operand predicates
45361 /* 134774 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45362 /* 134776 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45363 /* 134776 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45364 /* 134779 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
45365 /* 134783 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45366 /* 134788 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45367 /* 134792 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45368 /* 134795 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45369 /* 134797 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45370 /* 134800 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45371 /* 134804 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45372 /* 134809 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45373 /* 134812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45374 /* 134814 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45375 /* 134817 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45376 /* 134821 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45377 /* 134826 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45378 /* 134829 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45379 /* 134831 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45380 /* 134834 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45381 /* 134838 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45382 /* 134843 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
45383 /* 134850 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45384 /* 134855 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45385 /* 134860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45386 /* 134863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45387 /* 134865 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45388 /* 134868 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45389 /* 134871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45390 /* 134874 */ GIR_RootConstrainSelectedInstOperands,
45391 /* 134875 */ // GIR_Coverage, 3931,
45392 /* 134875 */ GIR_EraseRootFromParent_Done,
45393 /* 134876 */ // Label 1892: @134876
45394 /* 134876 */ GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(135019), // Rule ID 3939 //
45395 /* 134881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
45396 /* 134884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45397 /* 134888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
45398 /* 134892 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45399 /* 134896 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45400 /* 134900 */ // MIs[1] Operand 1
45401 /* 134900 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
45402 /* 134905 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
45403 /* 134909 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45404 /* 134913 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
45405 /* 134917 */ // MIs[2] Operand 1
45406 /* 134917 */ // No operand predicates
45407 /* 134917 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45408 /* 134919 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45409 /* 134919 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45410 /* 134922 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
45411 /* 134926 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45412 /* 134931 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45413 /* 134935 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
45414 /* 134938 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45415 /* 134940 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45416 /* 134943 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45417 /* 134947 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45418 /* 134952 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45419 /* 134955 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45420 /* 134957 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45421 /* 134960 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45422 /* 134964 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45423 /* 134969 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45424 /* 134972 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45425 /* 134974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45426 /* 134977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45427 /* 134981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45428 /* 134986 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
45429 /* 134993 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45430 /* 134998 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45431 /* 135003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45432 /* 135006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45433 /* 135008 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45434 /* 135011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45435 /* 135014 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45436 /* 135017 */ GIR_RootConstrainSelectedInstOperands,
45437 /* 135018 */ // GIR_Coverage, 3939,
45438 /* 135018 */ GIR_EraseRootFromParent_Done,
45439 /* 135019 */ // Label 1893: @135019
45440 /* 135019 */ GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(135111), // Rule ID 3180 //
45441 /* 135024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45442 /* 135027 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45443 /* 135031 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45444 /* 135035 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45445 /* 135039 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45446 /* 135043 */ // MIs[1] Operand 1
45447 /* 135043 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
45448 /* 135048 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45449 /* 135050 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }))
45450 /* 135050 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45451 /* 135053 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
45452 /* 135057 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45453 /* 135062 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45454 /* 135066 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45455 /* 135070 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45456 /* 135072 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45457 /* 135075 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45458 /* 135079 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45459 /* 135084 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
45460 /* 135091 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45461 /* 135096 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45462 /* 135101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45463 /* 135104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45464 /* 135106 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45465 /* 135109 */ GIR_RootConstrainSelectedInstOperands,
45466 /* 135110 */ // GIR_Coverage, 3180,
45467 /* 135110 */ GIR_EraseRootFromParent_Done,
45468 /* 135111 */ // Label 1894: @135111
45469 /* 135111 */ GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(135203), // Rule ID 3196 //
45470 /* 135116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45471 /* 135119 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45472 /* 135123 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45473 /* 135127 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45474 /* 135131 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45475 /* 135135 */ // MIs[1] Operand 1
45476 /* 135135 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
45477 /* 135140 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45478 /* 135142 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
45479 /* 135142 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45480 /* 135145 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
45481 /* 135149 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45482 /* 135154 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45483 /* 135158 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45484 /* 135162 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45485 /* 135164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45486 /* 135167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45487 /* 135171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45488 /* 135176 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
45489 /* 135183 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45490 /* 135188 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45491 /* 135193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45492 /* 135196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45493 /* 135198 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45494 /* 135201 */ GIR_RootConstrainSelectedInstOperands,
45495 /* 135202 */ // GIR_Coverage, 3196,
45496 /* 135202 */ GIR_EraseRootFromParent_Done,
45497 /* 135203 */ // Label 1895: @135203
45498 /* 135203 */ GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(135295), // Rule ID 3212 //
45499 /* 135208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45500 /* 135211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45501 /* 135215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45502 /* 135219 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45503 /* 135223 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45504 /* 135227 */ // MIs[1] Operand 1
45505 /* 135227 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
45506 /* 135232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45507 /* 135234 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }))
45508 /* 135234 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45509 /* 135237 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
45510 /* 135241 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45511 /* 135246 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45512 /* 135250 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45513 /* 135254 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45514 /* 135256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45515 /* 135259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45516 /* 135263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45517 /* 135268 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
45518 /* 135275 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45519 /* 135280 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45520 /* 135285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45521 /* 135288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45522 /* 135290 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45523 /* 135293 */ GIR_RootConstrainSelectedInstOperands,
45524 /* 135294 */ // GIR_Coverage, 3212,
45525 /* 135294 */ GIR_EraseRootFromParent_Done,
45526 /* 135295 */ // Label 1896: @135295
45527 /* 135295 */ GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(135387), // Rule ID 3228 //
45528 /* 135300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45529 /* 135303 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45530 /* 135307 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45531 /* 135311 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45532 /* 135315 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45533 /* 135319 */ // MIs[1] Operand 1
45534 /* 135319 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
45535 /* 135324 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45536 /* 135326 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }))
45537 /* 135326 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45538 /* 135329 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
45539 /* 135333 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45540 /* 135338 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45541 /* 135342 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45542 /* 135346 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45543 /* 135348 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45544 /* 135351 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45545 /* 135355 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45546 /* 135360 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
45547 /* 135367 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45548 /* 135372 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45549 /* 135377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45550 /* 135380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45551 /* 135382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45552 /* 135385 */ GIR_RootConstrainSelectedInstOperands,
45553 /* 135386 */ // GIR_Coverage, 3228,
45554 /* 135386 */ GIR_EraseRootFromParent_Done,
45555 /* 135387 */ // Label 1897: @135387
45556 /* 135387 */ GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(135479), // Rule ID 3236 //
45557 /* 135392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45558 /* 135395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45559 /* 135399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45560 /* 135403 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45561 /* 135407 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45562 /* 135411 */ // MIs[1] Operand 1
45563 /* 135411 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
45564 /* 135416 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45565 /* 135418 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }))
45566 /* 135418 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45567 /* 135421 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
45568 /* 135425 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45569 /* 135430 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45570 /* 135434 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45571 /* 135438 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45572 /* 135440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45573 /* 135443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45574 /* 135447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45575 /* 135452 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
45576 /* 135459 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45577 /* 135464 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45578 /* 135469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45579 /* 135472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45580 /* 135474 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45581 /* 135477 */ GIR_RootConstrainSelectedInstOperands,
45582 /* 135478 */ // GIR_Coverage, 3236,
45583 /* 135478 */ GIR_EraseRootFromParent_Done,
45584 /* 135479 */ // Label 1898: @135479
45585 /* 135479 */ GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(135571), // Rule ID 3252 //
45586 /* 135484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45587 /* 135487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45588 /* 135491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45589 /* 135495 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45590 /* 135499 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45591 /* 135503 */ // MIs[1] Operand 1
45592 /* 135503 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
45593 /* 135508 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45594 /* 135510 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
45595 /* 135510 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45596 /* 135513 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
45597 /* 135517 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45598 /* 135522 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45599 /* 135526 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45600 /* 135530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45601 /* 135532 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45602 /* 135535 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45603 /* 135539 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45604 /* 135544 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
45605 /* 135551 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45606 /* 135556 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45607 /* 135561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45608 /* 135564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45609 /* 135566 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45610 /* 135569 */ GIR_RootConstrainSelectedInstOperands,
45611 /* 135570 */ // GIR_Coverage, 3252,
45612 /* 135570 */ GIR_EraseRootFromParent_Done,
45613 /* 135571 */ // Label 1899: @135571
45614 /* 135571 */ GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(135663), // Rule ID 3268 //
45615 /* 135576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45616 /* 135579 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45617 /* 135583 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45618 /* 135587 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45619 /* 135591 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45620 /* 135595 */ // MIs[1] Operand 1
45621 /* 135595 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
45622 /* 135600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45623 /* 135602 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }))
45624 /* 135602 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45625 /* 135605 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
45626 /* 135609 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45627 /* 135614 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45628 /* 135618 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45629 /* 135622 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45630 /* 135624 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45631 /* 135627 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45632 /* 135631 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45633 /* 135636 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
45634 /* 135643 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45635 /* 135648 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45636 /* 135653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45637 /* 135656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45638 /* 135658 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45639 /* 135661 */ GIR_RootConstrainSelectedInstOperands,
45640 /* 135662 */ // GIR_Coverage, 3268,
45641 /* 135662 */ GIR_EraseRootFromParent_Done,
45642 /* 135663 */ // Label 1900: @135663
45643 /* 135663 */ GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(135755), // Rule ID 3284 //
45644 /* 135668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45645 /* 135671 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45646 /* 135675 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45647 /* 135679 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45648 /* 135683 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45649 /* 135687 */ // MIs[1] Operand 1
45650 /* 135687 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
45651 /* 135692 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45652 /* 135694 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }))
45653 /* 135694 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45654 /* 135697 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
45655 /* 135701 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45656 /* 135706 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45657 /* 135710 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45658 /* 135714 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45659 /* 135716 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45660 /* 135719 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45661 /* 135723 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45662 /* 135728 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
45663 /* 135735 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45664 /* 135740 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45665 /* 135745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45666 /* 135748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45667 /* 135750 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45668 /* 135753 */ GIR_RootConstrainSelectedInstOperands,
45669 /* 135754 */ // GIR_Coverage, 3284,
45670 /* 135754 */ GIR_EraseRootFromParent_Done,
45671 /* 135755 */ // Label 1901: @135755
45672 /* 135755 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(135847), // Rule ID 3292 //
45673 /* 135760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45674 /* 135763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45675 /* 135767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45676 /* 135771 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
45677 /* 135775 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
45678 /* 135779 */ // MIs[1] Operand 1
45679 /* 135779 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
45680 /* 135784 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45681 /* 135786 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }))
45682 /* 135786 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45683 /* 135789 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
45684 /* 135793 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45685 /* 135798 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45686 /* 135802 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45687 /* 135806 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45688 /* 135808 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45689 /* 135811 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45690 /* 135815 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45691 /* 135820 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
45692 /* 135827 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45693 /* 135832 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45694 /* 135837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45695 /* 135840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45696 /* 135842 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45697 /* 135845 */ GIR_RootConstrainSelectedInstOperands,
45698 /* 135846 */ // GIR_Coverage, 3292,
45699 /* 135846 */ GIR_EraseRootFromParent_Done,
45700 /* 135847 */ // Label 1902: @135847
45701 /* 135847 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(135939), // Rule ID 3308 //
45702 /* 135852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45703 /* 135855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45704 /* 135859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45705 /* 135863 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
45706 /* 135867 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
45707 /* 135871 */ // MIs[1] Operand 1
45708 /* 135871 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
45709 /* 135876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45710 /* 135878 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }))
45711 /* 135878 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45712 /* 135881 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
45713 /* 135885 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45714 /* 135890 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45715 /* 135894 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45716 /* 135898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45717 /* 135900 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45718 /* 135903 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45719 /* 135907 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45720 /* 135912 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
45721 /* 135919 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45722 /* 135924 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45723 /* 135929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45724 /* 135932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45725 /* 135934 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45726 /* 135937 */ GIR_RootConstrainSelectedInstOperands,
45727 /* 135938 */ // GIR_Coverage, 3308,
45728 /* 135938 */ GIR_EraseRootFromParent_Done,
45729 /* 135939 */ // Label 1903: @135939
45730 /* 135939 */ GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(136031), // Rule ID 3324 //
45731 /* 135944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45732 /* 135947 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45733 /* 135951 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45734 /* 135955 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
45735 /* 135959 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
45736 /* 135963 */ // MIs[1] Operand 1
45737 /* 135963 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
45738 /* 135968 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45739 /* 135970 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }))
45740 /* 135970 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45741 /* 135973 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
45742 /* 135977 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45743 /* 135982 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45744 /* 135986 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45745 /* 135990 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45746 /* 135992 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45747 /* 135995 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45748 /* 135999 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45749 /* 136004 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
45750 /* 136011 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45751 /* 136016 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45752 /* 136021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45753 /* 136024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45754 /* 136026 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45755 /* 136029 */ GIR_RootConstrainSelectedInstOperands,
45756 /* 136030 */ // GIR_Coverage, 3324,
45757 /* 136030 */ GIR_EraseRootFromParent_Done,
45758 /* 136031 */ // Label 1904: @136031
45759 /* 136031 */ GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(136123), // Rule ID 3340 //
45760 /* 136036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
45761 /* 136039 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45762 /* 136043 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45763 /* 136047 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
45764 /* 136051 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
45765 /* 136055 */ // MIs[1] Operand 1
45766 /* 136055 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
45767 /* 136060 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45768 /* 136062 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }))
45769 /* 136062 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45770 /* 136065 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
45771 /* 136069 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45772 /* 136074 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45773 /* 136078 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45774 /* 136082 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45775 /* 136084 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45776 /* 136087 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45777 /* 136091 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45778 /* 136096 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
45779 /* 136103 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45780 /* 136108 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45781 /* 136113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
45782 /* 136116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
45783 /* 136118 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45784 /* 136121 */ GIR_RootConstrainSelectedInstOperands,
45785 /* 136122 */ // GIR_Coverage, 3340,
45786 /* 136122 */ GIR_EraseRootFromParent_Done,
45787 /* 136123 */ // Label 1905: @136123
45788 /* 136123 */ GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(136255), // Rule ID 4020 //
45789 /* 136128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
45790 /* 136131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45791 /* 136135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45792 /* 136139 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45793 /* 136143 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45794 /* 136147 */ // MIs[1] Operand 1
45795 /* 136147 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
45796 /* 136152 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45797 /* 136154 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45798 /* 136154 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45799 /* 136157 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
45800 /* 136161 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45801 /* 136166 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45802 /* 136170 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45803 /* 136174 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45804 /* 136176 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45805 /* 136179 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45806 /* 136183 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45807 /* 136188 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45808 /* 136191 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45809 /* 136193 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45810 /* 136196 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45811 /* 136200 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45812 /* 136205 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45813 /* 136208 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45814 /* 136210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45815 /* 136213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45816 /* 136217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45817 /* 136222 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
45818 /* 136229 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45819 /* 136234 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45820 /* 136239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45821 /* 136242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45822 /* 136244 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45823 /* 136247 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45824 /* 136250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45825 /* 136253 */ GIR_RootConstrainSelectedInstOperands,
45826 /* 136254 */ // GIR_Coverage, 4020,
45827 /* 136254 */ GIR_EraseRootFromParent_Done,
45828 /* 136255 */ // Label 1906: @136255
45829 /* 136255 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(136387), // Rule ID 4052 //
45830 /* 136260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
45831 /* 136263 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45832 /* 136267 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45833 /* 136271 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45834 /* 136275 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45835 /* 136279 */ // MIs[1] Operand 1
45836 /* 136279 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
45837 /* 136284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45838 /* 136286 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45839 /* 136286 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45840 /* 136289 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
45841 /* 136293 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45842 /* 136298 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45843 /* 136302 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45844 /* 136306 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45845 /* 136308 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45846 /* 136311 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45847 /* 136315 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45848 /* 136320 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45849 /* 136323 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45850 /* 136325 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45851 /* 136328 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45852 /* 136332 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45853 /* 136337 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45854 /* 136340 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45855 /* 136342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45856 /* 136345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45857 /* 136349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45858 /* 136354 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
45859 /* 136361 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45860 /* 136366 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45861 /* 136371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45862 /* 136374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45863 /* 136376 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45864 /* 136379 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45865 /* 136382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45866 /* 136385 */ GIR_RootConstrainSelectedInstOperands,
45867 /* 136386 */ // GIR_Coverage, 4052,
45868 /* 136386 */ GIR_EraseRootFromParent_Done,
45869 /* 136387 */ // Label 1907: @136387
45870 /* 136387 */ GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(136519), // Rule ID 4084 //
45871 /* 136392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
45872 /* 136395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45873 /* 136399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45874 /* 136403 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45875 /* 136407 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45876 /* 136411 */ // MIs[1] Operand 1
45877 /* 136411 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
45878 /* 136416 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45879 /* 136418 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45880 /* 136418 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45881 /* 136421 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
45882 /* 136425 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45883 /* 136430 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45884 /* 136434 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45885 /* 136438 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45886 /* 136440 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45887 /* 136443 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45888 /* 136447 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45889 /* 136452 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45890 /* 136455 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45891 /* 136457 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45892 /* 136460 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45893 /* 136464 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45894 /* 136469 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45895 /* 136472 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45896 /* 136474 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45897 /* 136477 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45898 /* 136481 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45899 /* 136486 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
45900 /* 136493 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45901 /* 136498 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45902 /* 136503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45903 /* 136506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45904 /* 136508 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45905 /* 136511 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45906 /* 136514 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45907 /* 136517 */ GIR_RootConstrainSelectedInstOperands,
45908 /* 136518 */ // GIR_Coverage, 4084,
45909 /* 136518 */ GIR_EraseRootFromParent_Done,
45910 /* 136519 */ // Label 1908: @136519
45911 /* 136519 */ GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(136651), // Rule ID 4116 //
45912 /* 136524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
45913 /* 136527 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45914 /* 136531 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45915 /* 136535 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
45916 /* 136539 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
45917 /* 136543 */ // MIs[1] Operand 1
45918 /* 136543 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
45919 /* 136548 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45920 /* 136550 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45921 /* 136550 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45922 /* 136553 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
45923 /* 136557 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45924 /* 136562 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45925 /* 136566 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45926 /* 136570 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45927 /* 136572 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45928 /* 136575 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45929 /* 136579 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45930 /* 136584 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45931 /* 136587 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45932 /* 136589 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45933 /* 136592 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45934 /* 136596 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45935 /* 136601 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45936 /* 136604 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45937 /* 136606 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45938 /* 136609 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45939 /* 136613 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45940 /* 136618 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
45941 /* 136625 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45942 /* 136630 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45943 /* 136635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45944 /* 136638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45945 /* 136640 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45946 /* 136643 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45947 /* 136646 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45948 /* 136649 */ GIR_RootConstrainSelectedInstOperands,
45949 /* 136650 */ // GIR_Coverage, 4116,
45950 /* 136650 */ GIR_EraseRootFromParent_Done,
45951 /* 136651 */ // Label 1909: @136651
45952 /* 136651 */ GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(136783), // Rule ID 4132 //
45953 /* 136656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
45954 /* 136659 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45955 /* 136663 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45956 /* 136667 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45957 /* 136671 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45958 /* 136675 */ // MIs[1] Operand 1
45959 /* 136675 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
45960 /* 136680 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45961 /* 136682 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
45962 /* 136682 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
45963 /* 136685 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
45964 /* 136689 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45965 /* 136694 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
45966 /* 136698 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
45967 /* 136702 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45968 /* 136704 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45969 /* 136707 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
45970 /* 136711 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45971 /* 136716 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
45972 /* 136719 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
45973 /* 136721 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45974 /* 136724 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
45975 /* 136728 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45976 /* 136733 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
45977 /* 136736 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45978 /* 136738 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
45979 /* 136741 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45980 /* 136745 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45981 /* 136750 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
45982 /* 136757 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
45983 /* 136762 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
45984 /* 136767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
45985 /* 136770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45986 /* 136772 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45987 /* 136775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
45988 /* 136778 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
45989 /* 136781 */ GIR_RootConstrainSelectedInstOperands,
45990 /* 136782 */ // GIR_Coverage, 4132,
45991 /* 136782 */ GIR_EraseRootFromParent_Done,
45992 /* 136783 */ // Label 1910: @136783
45993 /* 136783 */ GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(136915), // Rule ID 4164 //
45994 /* 136788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
45995 /* 136791 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45996 /* 136795 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
45997 /* 136799 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
45998 /* 136803 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
45999 /* 136807 */ // MIs[1] Operand 1
46000 /* 136807 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
46001 /* 136812 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46002 /* 136814 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46003 /* 136814 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46004 /* 136817 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
46005 /* 136821 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46006 /* 136826 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46007 /* 136830 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46008 /* 136834 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46009 /* 136836 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46010 /* 136839 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46011 /* 136843 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46012 /* 136848 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46013 /* 136851 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46014 /* 136853 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46015 /* 136856 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46016 /* 136860 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46017 /* 136865 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46018 /* 136868 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46019 /* 136870 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46020 /* 136873 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46021 /* 136877 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46022 /* 136882 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46023 /* 136889 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46024 /* 136894 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46025 /* 136899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46026 /* 136902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46027 /* 136904 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46028 /* 136907 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46029 /* 136910 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46030 /* 136913 */ GIR_RootConstrainSelectedInstOperands,
46031 /* 136914 */ // GIR_Coverage, 4164,
46032 /* 136914 */ GIR_EraseRootFromParent_Done,
46033 /* 136915 */ // Label 1911: @136915
46034 /* 136915 */ GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(137047), // Rule ID 4196 //
46035 /* 136920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
46036 /* 136923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46037 /* 136927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46038 /* 136931 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46039 /* 136935 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46040 /* 136939 */ // MIs[1] Operand 1
46041 /* 136939 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
46042 /* 136944 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46043 /* 136946 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46044 /* 136946 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46045 /* 136949 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
46046 /* 136953 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46047 /* 136958 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46048 /* 136962 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46049 /* 136966 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46050 /* 136968 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46051 /* 136971 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46052 /* 136975 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46053 /* 136980 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46054 /* 136983 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46055 /* 136985 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46056 /* 136988 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46057 /* 136992 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46058 /* 136997 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46059 /* 137000 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46060 /* 137002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46061 /* 137005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46062 /* 137009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46063 /* 137014 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
46064 /* 137021 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46065 /* 137026 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46066 /* 137031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46067 /* 137034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46068 /* 137036 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46069 /* 137039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46070 /* 137042 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46071 /* 137045 */ GIR_RootConstrainSelectedInstOperands,
46072 /* 137046 */ // GIR_Coverage, 4196,
46073 /* 137046 */ GIR_EraseRootFromParent_Done,
46074 /* 137047 */ // Label 1912: @137047
46075 /* 137047 */ GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(137179), // Rule ID 4228 //
46076 /* 137052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
46077 /* 137055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46078 /* 137059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46079 /* 137063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46080 /* 137067 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46081 /* 137071 */ // MIs[1] Operand 1
46082 /* 137071 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
46083 /* 137076 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46084 /* 137078 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46085 /* 137078 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46086 /* 137081 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
46087 /* 137085 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46088 /* 137090 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46089 /* 137094 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46090 /* 137098 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46091 /* 137100 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46092 /* 137103 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46093 /* 137107 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46094 /* 137112 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46095 /* 137115 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46096 /* 137117 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46097 /* 137120 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46098 /* 137124 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46099 /* 137129 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46100 /* 137132 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46101 /* 137134 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46102 /* 137137 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46103 /* 137141 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46104 /* 137146 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
46105 /* 137153 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46106 /* 137158 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46107 /* 137163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46108 /* 137166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46109 /* 137168 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46110 /* 137171 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46111 /* 137174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46112 /* 137177 */ GIR_RootConstrainSelectedInstOperands,
46113 /* 137178 */ // GIR_Coverage, 4228,
46114 /* 137178 */ GIR_EraseRootFromParent_Done,
46115 /* 137179 */ // Label 1913: @137179
46116 /* 137179 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(137311), // Rule ID 4258 //
46117 /* 137184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
46118 /* 137187 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46119 /* 137191 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46120 /* 137195 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
46121 /* 137199 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
46122 /* 137203 */ // MIs[1] Operand 1
46123 /* 137203 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
46124 /* 137208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46125 /* 137210 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46126 /* 137210 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46127 /* 137213 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
46128 /* 137217 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46129 /* 137222 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46130 /* 137226 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46131 /* 137230 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46132 /* 137232 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46133 /* 137235 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46134 /* 137239 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46135 /* 137244 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46136 /* 137247 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46137 /* 137249 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46138 /* 137252 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46139 /* 137256 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46140 /* 137261 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46141 /* 137264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46142 /* 137266 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46143 /* 137269 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46144 /* 137273 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46145 /* 137278 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
46146 /* 137285 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46147 /* 137290 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46148 /* 137295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46149 /* 137298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46150 /* 137300 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46151 /* 137303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46152 /* 137306 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46153 /* 137309 */ GIR_RootConstrainSelectedInstOperands,
46154 /* 137310 */ // GIR_Coverage, 4258,
46155 /* 137310 */ GIR_EraseRootFromParent_Done,
46156 /* 137311 */ // Label 1914: @137311
46157 /* 137311 */ GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(137443), // Rule ID 4290 //
46158 /* 137316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
46159 /* 137319 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46160 /* 137323 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46161 /* 137327 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
46162 /* 137331 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
46163 /* 137335 */ // MIs[1] Operand 1
46164 /* 137335 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
46165 /* 137340 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46166 /* 137342 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46167 /* 137342 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46168 /* 137345 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
46169 /* 137349 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46170 /* 137354 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46171 /* 137358 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46172 /* 137362 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46173 /* 137364 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46174 /* 137367 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46175 /* 137371 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46176 /* 137376 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46177 /* 137379 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46178 /* 137381 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46179 /* 137384 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46180 /* 137388 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46181 /* 137393 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46182 /* 137396 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46183 /* 137398 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46184 /* 137401 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46185 /* 137405 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46186 /* 137410 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46187 /* 137417 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46188 /* 137422 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46189 /* 137427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46190 /* 137430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46191 /* 137432 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46192 /* 137435 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46193 /* 137438 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46194 /* 137441 */ GIR_RootConstrainSelectedInstOperands,
46195 /* 137442 */ // GIR_Coverage, 4290,
46196 /* 137442 */ GIR_EraseRootFromParent_Done,
46197 /* 137443 */ // Label 1915: @137443
46198 /* 137443 */ GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(137575), // Rule ID 4322 //
46199 /* 137448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
46200 /* 137451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46201 /* 137455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46202 /* 137459 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
46203 /* 137463 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
46204 /* 137467 */ // MIs[1] Operand 1
46205 /* 137467 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
46206 /* 137472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46207 /* 137474 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46208 /* 137474 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46209 /* 137477 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
46210 /* 137481 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46211 /* 137486 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46212 /* 137490 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46213 /* 137494 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46214 /* 137496 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46215 /* 137499 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46216 /* 137503 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46217 /* 137508 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46218 /* 137511 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46219 /* 137513 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46220 /* 137516 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46221 /* 137520 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46222 /* 137525 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46223 /* 137528 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46224 /* 137530 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46225 /* 137533 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46226 /* 137537 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46227 /* 137542 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
46228 /* 137549 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46229 /* 137554 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46230 /* 137559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46231 /* 137562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46232 /* 137564 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46233 /* 137567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46234 /* 137570 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46235 /* 137573 */ GIR_RootConstrainSelectedInstOperands,
46236 /* 137574 */ // GIR_Coverage, 4322,
46237 /* 137574 */ GIR_EraseRootFromParent_Done,
46238 /* 137575 */ // Label 1916: @137575
46239 /* 137575 */ GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(137707), // Rule ID 4354 //
46240 /* 137580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
46241 /* 137583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46242 /* 137587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46243 /* 137591 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
46244 /* 137595 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
46245 /* 137599 */ // MIs[1] Operand 1
46246 /* 137599 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
46247 /* 137604 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46248 /* 137606 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46249 /* 137606 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46250 /* 137609 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
46251 /* 137613 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46252 /* 137618 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46253 /* 137622 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46254 /* 137626 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46255 /* 137628 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46256 /* 137631 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46257 /* 137635 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46258 /* 137640 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46259 /* 137643 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46260 /* 137645 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46261 /* 137648 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46262 /* 137652 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46263 /* 137657 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46264 /* 137660 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46265 /* 137662 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46266 /* 137665 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46267 /* 137669 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46268 /* 137674 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
46269 /* 137681 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46270 /* 137686 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46271 /* 137691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46272 /* 137694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46273 /* 137696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46274 /* 137699 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46275 /* 137702 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46276 /* 137705 */ GIR_RootConstrainSelectedInstOperands,
46277 /* 137706 */ // GIR_Coverage, 4354,
46278 /* 137706 */ GIR_EraseRootFromParent_Done,
46279 /* 137707 */ // Label 1917: @137707
46280 /* 137707 */ GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(137839), // Rule ID 4585 //
46281 /* 137712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
46282 /* 137715 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46283 /* 137719 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46284 /* 137723 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46285 /* 137727 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46286 /* 137731 */ // MIs[1] Operand 1
46287 /* 137731 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
46288 /* 137736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46289 /* 137738 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46290 /* 137738 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46291 /* 137741 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
46292 /* 137745 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46293 /* 137750 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46294 /* 137754 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46295 /* 137758 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46296 /* 137760 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46297 /* 137763 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46298 /* 137767 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46299 /* 137772 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46300 /* 137775 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46301 /* 137777 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46302 /* 137780 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46303 /* 137784 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46304 /* 137789 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46305 /* 137792 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46306 /* 137794 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46307 /* 137797 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46308 /* 137801 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46309 /* 137806 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46310 /* 137813 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46311 /* 137818 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46312 /* 137823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46313 /* 137826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46314 /* 137828 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46315 /* 137831 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46316 /* 137834 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46317 /* 137837 */ GIR_RootConstrainSelectedInstOperands,
46318 /* 137838 */ // GIR_Coverage, 4585,
46319 /* 137838 */ GIR_EraseRootFromParent_Done,
46320 /* 137839 */ // Label 1918: @137839
46321 /* 137839 */ GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(137971), // Rule ID 4617 //
46322 /* 137844 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
46323 /* 137847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46324 /* 137851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46325 /* 137855 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46326 /* 137859 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46327 /* 137863 */ // MIs[1] Operand 1
46328 /* 137863 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
46329 /* 137868 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46330 /* 137870 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46331 /* 137870 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46332 /* 137873 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
46333 /* 137877 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46334 /* 137882 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46335 /* 137886 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46336 /* 137890 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46337 /* 137892 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46338 /* 137895 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46339 /* 137899 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46340 /* 137904 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46341 /* 137907 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46342 /* 137909 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46343 /* 137912 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46344 /* 137916 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46345 /* 137921 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46346 /* 137924 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46347 /* 137926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46348 /* 137929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46349 /* 137933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46350 /* 137938 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46351 /* 137945 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46352 /* 137950 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46353 /* 137955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46354 /* 137958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46355 /* 137960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46356 /* 137963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46357 /* 137966 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46358 /* 137969 */ GIR_RootConstrainSelectedInstOperands,
46359 /* 137970 */ // GIR_Coverage, 4617,
46360 /* 137970 */ GIR_EraseRootFromParent_Done,
46361 /* 137971 */ // Label 1919: @137971
46362 /* 137971 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(138103), // Rule ID 4649 //
46363 /* 137976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
46364 /* 137979 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46365 /* 137983 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46366 /* 137987 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46367 /* 137991 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46368 /* 137995 */ // MIs[1] Operand 1
46369 /* 137995 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
46370 /* 138000 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46371 /* 138002 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46372 /* 138002 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46373 /* 138005 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
46374 /* 138009 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46375 /* 138014 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46376 /* 138018 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46377 /* 138022 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46378 /* 138024 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46379 /* 138027 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46380 /* 138031 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46381 /* 138036 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46382 /* 138039 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46383 /* 138041 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46384 /* 138044 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46385 /* 138048 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46386 /* 138053 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46387 /* 138056 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46388 /* 138058 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46389 /* 138061 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46390 /* 138065 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46391 /* 138070 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46392 /* 138077 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46393 /* 138082 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46394 /* 138087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46395 /* 138090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46396 /* 138092 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46397 /* 138095 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46398 /* 138098 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46399 /* 138101 */ GIR_RootConstrainSelectedInstOperands,
46400 /* 138102 */ // GIR_Coverage, 4649,
46401 /* 138102 */ GIR_EraseRootFromParent_Done,
46402 /* 138103 */ // Label 1920: @138103
46403 /* 138103 */ GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(138235), // Rule ID 4693 //
46404 /* 138108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
46405 /* 138111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46406 /* 138115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46407 /* 138119 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46408 /* 138123 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46409 /* 138127 */ // MIs[1] Operand 1
46410 /* 138127 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
46411 /* 138132 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46412 /* 138134 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46413 /* 138134 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46414 /* 138137 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
46415 /* 138141 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46416 /* 138146 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46417 /* 138150 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46418 /* 138154 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46419 /* 138156 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46420 /* 138159 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46421 /* 138163 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46422 /* 138168 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46423 /* 138171 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46424 /* 138173 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46425 /* 138176 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46426 /* 138180 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46427 /* 138185 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46428 /* 138188 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46429 /* 138190 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46430 /* 138193 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46431 /* 138197 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46432 /* 138202 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46433 /* 138209 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46434 /* 138214 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46435 /* 138219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46436 /* 138222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46437 /* 138224 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46438 /* 138227 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46439 /* 138230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46440 /* 138233 */ GIR_RootConstrainSelectedInstOperands,
46441 /* 138234 */ // GIR_Coverage, 4693,
46442 /* 138234 */ GIR_EraseRootFromParent_Done,
46443 /* 138235 */ // Label 1921: @138235
46444 /* 138235 */ GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(138367), // Rule ID 4725 //
46445 /* 138240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
46446 /* 138243 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46447 /* 138247 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46448 /* 138251 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46449 /* 138255 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46450 /* 138259 */ // MIs[1] Operand 1
46451 /* 138259 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
46452 /* 138264 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46453 /* 138266 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46454 /* 138266 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46455 /* 138269 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
46456 /* 138273 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46457 /* 138278 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46458 /* 138282 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46459 /* 138286 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46460 /* 138288 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46461 /* 138291 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46462 /* 138295 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46463 /* 138300 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46464 /* 138303 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46465 /* 138305 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46466 /* 138308 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46467 /* 138312 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46468 /* 138317 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46469 /* 138320 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46470 /* 138322 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46471 /* 138325 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46472 /* 138329 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46473 /* 138334 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46474 /* 138341 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46475 /* 138346 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46476 /* 138351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46477 /* 138354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46478 /* 138356 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46479 /* 138359 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46480 /* 138362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46481 /* 138365 */ GIR_RootConstrainSelectedInstOperands,
46482 /* 138366 */ // GIR_Coverage, 4725,
46483 /* 138366 */ GIR_EraseRootFromParent_Done,
46484 /* 138367 */ // Label 1922: @138367
46485 /* 138367 */ GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(138499), // Rule ID 4757 //
46486 /* 138372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
46487 /* 138375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46488 /* 138379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
46489 /* 138383 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46490 /* 138387 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46491 /* 138391 */ // MIs[1] Operand 1
46492 /* 138391 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
46493 /* 138396 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46494 /* 138398 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46495 /* 138398 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46496 /* 138401 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
46497 /* 138405 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46498 /* 138410 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46499 /* 138414 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46500 /* 138418 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46501 /* 138420 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46502 /* 138423 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46503 /* 138427 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46504 /* 138432 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46505 /* 138435 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46506 /* 138437 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46507 /* 138440 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46508 /* 138444 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46509 /* 138449 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46510 /* 138452 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46511 /* 138454 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46512 /* 138457 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46513 /* 138461 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46514 /* 138466 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46515 /* 138473 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46516 /* 138478 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46517 /* 138483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46518 /* 138486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46519 /* 138488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46520 /* 138491 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46521 /* 138494 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46522 /* 138497 */ GIR_RootConstrainSelectedInstOperands,
46523 /* 138498 */ // GIR_Coverage, 4757,
46524 /* 138498 */ GIR_EraseRootFromParent_Done,
46525 /* 138499 */ // Label 1923: @138499
46526 /* 138499 */ GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(138591), // Rule ID 2982 //
46527 /* 138504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46528 /* 138507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46529 /* 138511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46530 /* 138515 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46531 /* 138519 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46532 /* 138523 */ // MIs[1] Operand 1
46533 /* 138523 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
46534 /* 138528 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46535 /* 138530 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
46536 /* 138530 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46537 /* 138533 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
46538 /* 138537 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46539 /* 138542 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46540 /* 138546 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46541 /* 138550 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46542 /* 138552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46543 /* 138555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46544 /* 138559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46545 /* 138564 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
46546 /* 138571 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46547 /* 138576 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46548 /* 138581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46549 /* 138584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46550 /* 138586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46551 /* 138589 */ GIR_RootConstrainSelectedInstOperands,
46552 /* 138590 */ // GIR_Coverage, 2982,
46553 /* 138590 */ GIR_EraseRootFromParent_Done,
46554 /* 138591 */ // Label 1924: @138591
46555 /* 138591 */ GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(138683), // Rule ID 2996 //
46556 /* 138596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46557 /* 138599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46558 /* 138603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46559 /* 138607 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46560 /* 138611 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46561 /* 138615 */ // MIs[1] Operand 1
46562 /* 138615 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
46563 /* 138620 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46564 /* 138622 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
46565 /* 138622 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46566 /* 138625 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
46567 /* 138629 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46568 /* 138634 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46569 /* 138638 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46570 /* 138642 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46571 /* 138644 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46572 /* 138647 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46573 /* 138651 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46574 /* 138656 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
46575 /* 138663 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46576 /* 138668 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46577 /* 138673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46578 /* 138676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46579 /* 138678 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46580 /* 138681 */ GIR_RootConstrainSelectedInstOperands,
46581 /* 138682 */ // GIR_Coverage, 2996,
46582 /* 138682 */ GIR_EraseRootFromParent_Done,
46583 /* 138683 */ // Label 1925: @138683
46584 /* 138683 */ GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(138775), // Rule ID 3004 //
46585 /* 138688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46586 /* 138691 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46587 /* 138695 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46588 /* 138699 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46589 /* 138703 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46590 /* 138707 */ // MIs[1] Operand 1
46591 /* 138707 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
46592 /* 138712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46593 /* 138714 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
46594 /* 138714 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46595 /* 138717 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
46596 /* 138721 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46597 /* 138726 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46598 /* 138730 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46599 /* 138734 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46600 /* 138736 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46601 /* 138739 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46602 /* 138743 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46603 /* 138748 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46604 /* 138755 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46605 /* 138760 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46606 /* 138765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46607 /* 138768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46608 /* 138770 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46609 /* 138773 */ GIR_RootConstrainSelectedInstOperands,
46610 /* 138774 */ // GIR_Coverage, 3004,
46611 /* 138774 */ GIR_EraseRootFromParent_Done,
46612 /* 138775 */ // Label 1926: @138775
46613 /* 138775 */ GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(138867), // Rule ID 3012 //
46614 /* 138780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46615 /* 138783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46616 /* 138787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46617 /* 138791 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46618 /* 138795 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46619 /* 138799 */ // MIs[1] Operand 1
46620 /* 138799 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
46621 /* 138804 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46622 /* 138806 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
46623 /* 138806 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46624 /* 138809 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
46625 /* 138813 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46626 /* 138818 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46627 /* 138822 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46628 /* 138826 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46629 /* 138828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46630 /* 138831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46631 /* 138835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46632 /* 138840 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46633 /* 138847 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46634 /* 138852 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46635 /* 138857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46636 /* 138860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46637 /* 138862 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46638 /* 138865 */ GIR_RootConstrainSelectedInstOperands,
46639 /* 138866 */ // GIR_Coverage, 3012,
46640 /* 138866 */ GIR_EraseRootFromParent_Done,
46641 /* 138867 */ // Label 1927: @138867
46642 /* 138867 */ GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(138959), // Rule ID 3020 //
46643 /* 138872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46644 /* 138875 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46645 /* 138879 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46646 /* 138883 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46647 /* 138887 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46648 /* 138891 */ // MIs[1] Operand 1
46649 /* 138891 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
46650 /* 138896 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46651 /* 138898 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }))
46652 /* 138898 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46653 /* 138901 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
46654 /* 138905 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46655 /* 138910 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46656 /* 138914 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46657 /* 138918 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46658 /* 138920 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46659 /* 138923 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46660 /* 138927 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46661 /* 138932 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
46662 /* 138939 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46663 /* 138944 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46664 /* 138949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46665 /* 138952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46666 /* 138954 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46667 /* 138957 */ GIR_RootConstrainSelectedInstOperands,
46668 /* 138958 */ // GIR_Coverage, 3020,
46669 /* 138958 */ GIR_EraseRootFromParent_Done,
46670 /* 138959 */ // Label 1928: @138959
46671 /* 138959 */ GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(139051), // Rule ID 3084 //
46672 /* 138964 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46673 /* 138967 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46674 /* 138971 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46675 /* 138975 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46676 /* 138979 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46677 /* 138983 */ // MIs[1] Operand 1
46678 /* 138983 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
46679 /* 138988 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46680 /* 138990 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
46681 /* 138990 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46682 /* 138993 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
46683 /* 138997 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46684 /* 139002 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46685 /* 139006 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46686 /* 139010 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46687 /* 139012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46688 /* 139015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46689 /* 139019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46690 /* 139024 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
46691 /* 139031 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46692 /* 139036 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46693 /* 139041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46694 /* 139044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46695 /* 139046 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46696 /* 139049 */ GIR_RootConstrainSelectedInstOperands,
46697 /* 139050 */ // GIR_Coverage, 3084,
46698 /* 139050 */ GIR_EraseRootFromParent_Done,
46699 /* 139051 */ // Label 1929: @139051
46700 /* 139051 */ GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(139143), // Rule ID 3092 //
46701 /* 139056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46702 /* 139059 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46703 /* 139063 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46704 /* 139067 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46705 /* 139071 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46706 /* 139075 */ // MIs[1] Operand 1
46707 /* 139075 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
46708 /* 139080 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46709 /* 139082 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
46710 /* 139082 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46711 /* 139085 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
46712 /* 139089 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46713 /* 139094 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46714 /* 139098 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46715 /* 139102 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46716 /* 139104 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46717 /* 139107 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46718 /* 139111 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46719 /* 139116 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
46720 /* 139123 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46721 /* 139128 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46722 /* 139133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46723 /* 139136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46724 /* 139138 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46725 /* 139141 */ GIR_RootConstrainSelectedInstOperands,
46726 /* 139142 */ // GIR_Coverage, 3092,
46727 /* 139142 */ GIR_EraseRootFromParent_Done,
46728 /* 139143 */ // Label 1930: @139143
46729 /* 139143 */ GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(139235), // Rule ID 3100 //
46730 /* 139148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46731 /* 139151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46732 /* 139155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46733 /* 139159 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46734 /* 139163 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46735 /* 139167 */ // MIs[1] Operand 1
46736 /* 139167 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
46737 /* 139172 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46738 /* 139174 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
46739 /* 139174 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46740 /* 139177 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
46741 /* 139181 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46742 /* 139186 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46743 /* 139190 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46744 /* 139194 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46745 /* 139196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46746 /* 139199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46747 /* 139203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46748 /* 139208 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46749 /* 139215 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46750 /* 139220 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46751 /* 139225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46752 /* 139228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46753 /* 139230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46754 /* 139233 */ GIR_RootConstrainSelectedInstOperands,
46755 /* 139234 */ // GIR_Coverage, 3100,
46756 /* 139234 */ GIR_EraseRootFromParent_Done,
46757 /* 139235 */ // Label 1931: @139235
46758 /* 139235 */ GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(139327), // Rule ID 3108 //
46759 /* 139240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46760 /* 139243 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46761 /* 139247 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46762 /* 139251 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46763 /* 139255 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46764 /* 139259 */ // MIs[1] Operand 1
46765 /* 139259 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
46766 /* 139264 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46767 /* 139266 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
46768 /* 139266 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46769 /* 139269 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
46770 /* 139273 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46771 /* 139278 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46772 /* 139282 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46773 /* 139286 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46774 /* 139288 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46775 /* 139291 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46776 /* 139295 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46777 /* 139300 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46778 /* 139307 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46779 /* 139312 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46780 /* 139317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46781 /* 139320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46782 /* 139322 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46783 /* 139325 */ GIR_RootConstrainSelectedInstOperands,
46784 /* 139326 */ // GIR_Coverage, 3108,
46785 /* 139326 */ GIR_EraseRootFromParent_Done,
46786 /* 139327 */ // Label 1932: @139327
46787 /* 139327 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(139419), // Rule ID 3116 //
46788 /* 139332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
46789 /* 139335 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46790 /* 139339 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46791 /* 139343 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46792 /* 139347 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
46793 /* 139351 */ // MIs[1] Operand 1
46794 /* 139351 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
46795 /* 139356 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46796 /* 139358 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SETBCR:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }))
46797 /* 139358 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46798 /* 139361 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
46799 /* 139365 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46800 /* 139370 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46801 /* 139374 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46802 /* 139378 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46803 /* 139380 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46804 /* 139383 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46805 /* 139387 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46806 /* 139392 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
46807 /* 139399 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46808 /* 139404 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46809 /* 139409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR),
46810 /* 139412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
46811 /* 139414 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46812 /* 139417 */ GIR_RootConstrainSelectedInstOperands,
46813 /* 139418 */ // GIR_Coverage, 3116,
46814 /* 139418 */ GIR_EraseRootFromParent_Done,
46815 /* 139419 */ // Label 1933: @139419
46816 /* 139419 */ GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(139551), // Rule ID 3867 //
46817 /* 139424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
46818 /* 139427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46819 /* 139431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46820 /* 139435 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46821 /* 139439 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46822 /* 139443 */ // MIs[1] Operand 1
46823 /* 139443 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
46824 /* 139448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46825 /* 139450 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46826 /* 139450 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46827 /* 139453 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
46828 /* 139457 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46829 /* 139462 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46830 /* 139466 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46831 /* 139470 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46832 /* 139472 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46833 /* 139475 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46834 /* 139479 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46835 /* 139484 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46836 /* 139487 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46837 /* 139489 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46838 /* 139492 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46839 /* 139496 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46840 /* 139501 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46841 /* 139504 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46842 /* 139506 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46843 /* 139509 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46844 /* 139513 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46845 /* 139518 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
46846 /* 139525 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46847 /* 139530 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46848 /* 139535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46849 /* 139538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46850 /* 139540 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46851 /* 139543 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46852 /* 139546 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46853 /* 139549 */ GIR_RootConstrainSelectedInstOperands,
46854 /* 139550 */ // GIR_Coverage, 3867,
46855 /* 139550 */ GIR_EraseRootFromParent_Done,
46856 /* 139551 */ // Label 1934: @139551
46857 /* 139551 */ GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(139683), // Rule ID 3875 //
46858 /* 139556 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
46859 /* 139559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46860 /* 139563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46861 /* 139567 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46862 /* 139571 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46863 /* 139575 */ // MIs[1] Operand 1
46864 /* 139575 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
46865 /* 139580 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46866 /* 139582 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46867 /* 139582 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46868 /* 139585 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
46869 /* 139589 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46870 /* 139594 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46871 /* 139598 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46872 /* 139602 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46873 /* 139604 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46874 /* 139607 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46875 /* 139611 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46876 /* 139616 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46877 /* 139619 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46878 /* 139621 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46879 /* 139624 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46880 /* 139628 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46881 /* 139633 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46882 /* 139636 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46883 /* 139638 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46884 /* 139641 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46885 /* 139645 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46886 /* 139650 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
46887 /* 139657 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46888 /* 139662 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46889 /* 139667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46890 /* 139670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46891 /* 139672 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46892 /* 139675 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46893 /* 139678 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46894 /* 139681 */ GIR_RootConstrainSelectedInstOperands,
46895 /* 139682 */ // GIR_Coverage, 3875,
46896 /* 139682 */ GIR_EraseRootFromParent_Done,
46897 /* 139683 */ // Label 1935: @139683
46898 /* 139683 */ GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(139815), // Rule ID 3883 //
46899 /* 139688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
46900 /* 139691 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46901 /* 139695 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46902 /* 139699 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46903 /* 139703 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46904 /* 139707 */ // MIs[1] Operand 1
46905 /* 139707 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
46906 /* 139712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46907 /* 139714 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46908 /* 139714 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46909 /* 139717 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
46910 /* 139721 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46911 /* 139726 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46912 /* 139730 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46913 /* 139734 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46914 /* 139736 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46915 /* 139739 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46916 /* 139743 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46917 /* 139748 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46918 /* 139751 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46919 /* 139753 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46920 /* 139756 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46921 /* 139760 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46922 /* 139765 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46923 /* 139768 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46924 /* 139770 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46925 /* 139773 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46926 /* 139777 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46927 /* 139782 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46928 /* 139789 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46929 /* 139794 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46930 /* 139799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46931 /* 139802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46932 /* 139804 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46933 /* 139807 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46934 /* 139810 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46935 /* 139813 */ GIR_RootConstrainSelectedInstOperands,
46936 /* 139814 */ // GIR_Coverage, 3883,
46937 /* 139814 */ GIR_EraseRootFromParent_Done,
46938 /* 139815 */ // Label 1936: @139815
46939 /* 139815 */ GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(139947), // Rule ID 3891 //
46940 /* 139820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
46941 /* 139823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46942 /* 139827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46943 /* 139831 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46944 /* 139835 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46945 /* 139839 */ // MIs[1] Operand 1
46946 /* 139839 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
46947 /* 139844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46948 /* 139846 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46949 /* 139846 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46950 /* 139849 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
46951 /* 139853 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46952 /* 139858 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46953 /* 139862 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46954 /* 139866 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46955 /* 139868 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46956 /* 139871 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46957 /* 139875 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46958 /* 139880 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
46959 /* 139883 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
46960 /* 139885 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46961 /* 139888 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
46962 /* 139892 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46963 /* 139897 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
46964 /* 139900 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46965 /* 139902 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
46966 /* 139905 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46967 /* 139909 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46968 /* 139914 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
46969 /* 139921 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
46970 /* 139926 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
46971 /* 139931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
46972 /* 139934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46973 /* 139936 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46974 /* 139939 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
46975 /* 139942 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
46976 /* 139945 */ GIR_RootConstrainSelectedInstOperands,
46977 /* 139946 */ // GIR_Coverage, 3891,
46978 /* 139946 */ GIR_EraseRootFromParent_Done,
46979 /* 139947 */ // Label 1937: @139947
46980 /* 139947 */ GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(140079), // Rule ID 3899 //
46981 /* 139952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
46982 /* 139955 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46983 /* 139959 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
46984 /* 139963 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
46985 /* 139967 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
46986 /* 139971 */ // MIs[1] Operand 1
46987 /* 139971 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
46988 /* 139976 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46989 /* 139978 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
46990 /* 139978 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
46991 /* 139981 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
46992 /* 139985 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46993 /* 139990 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
46994 /* 139994 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
46995 /* 139998 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46996 /* 140000 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
46997 /* 140003 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
46998 /* 140007 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46999 /* 140012 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
47000 /* 140015 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47001 /* 140017 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47002 /* 140020 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
47003 /* 140024 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47004 /* 140029 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
47005 /* 140032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47006 /* 140034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
47007 /* 140037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47008 /* 140041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47009 /* 140046 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
47010 /* 140053 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
47011 /* 140058 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
47012 /* 140063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
47013 /* 140066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47014 /* 140068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47015 /* 140071 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
47016 /* 140074 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
47017 /* 140077 */ GIR_RootConstrainSelectedInstOperands,
47018 /* 140078 */ // GIR_Coverage, 3899,
47019 /* 140078 */ GIR_EraseRootFromParent_Done,
47020 /* 140079 */ // Label 1938: @140079
47021 /* 140079 */ GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(140211), // Rule ID 3963 //
47022 /* 140084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
47023 /* 140087 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47024 /* 140091 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47025 /* 140095 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47026 /* 140099 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47027 /* 140103 */ // MIs[1] Operand 1
47028 /* 140103 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
47029 /* 140108 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47030 /* 140110 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
47031 /* 140110 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47032 /* 140113 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
47033 /* 140117 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47034 /* 140122 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
47035 /* 140126 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
47036 /* 140130 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47037 /* 140132 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47038 /* 140135 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
47039 /* 140139 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47040 /* 140144 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
47041 /* 140147 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47042 /* 140149 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47043 /* 140152 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
47044 /* 140156 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47045 /* 140161 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
47046 /* 140164 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47047 /* 140166 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
47048 /* 140169 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47049 /* 140173 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47050 /* 140178 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
47051 /* 140185 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
47052 /* 140190 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
47053 /* 140195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
47054 /* 140198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47055 /* 140200 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47056 /* 140203 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
47057 /* 140206 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
47058 /* 140209 */ GIR_RootConstrainSelectedInstOperands,
47059 /* 140210 */ // GIR_Coverage, 3963,
47060 /* 140210 */ GIR_EraseRootFromParent_Done,
47061 /* 140211 */ // Label 1939: @140211
47062 /* 140211 */ GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(140343), // Rule ID 3971 //
47063 /* 140216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
47064 /* 140219 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47065 /* 140223 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47066 /* 140227 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47067 /* 140231 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47068 /* 140235 */ // MIs[1] Operand 1
47069 /* 140235 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
47070 /* 140240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47071 /* 140242 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
47072 /* 140242 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47073 /* 140245 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
47074 /* 140249 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47075 /* 140254 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
47076 /* 140258 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
47077 /* 140262 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47078 /* 140264 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47079 /* 140267 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
47080 /* 140271 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47081 /* 140276 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
47082 /* 140279 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47083 /* 140281 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47084 /* 140284 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
47085 /* 140288 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47086 /* 140293 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
47087 /* 140296 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47088 /* 140298 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
47089 /* 140301 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47090 /* 140305 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47091 /* 140310 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
47092 /* 140317 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
47093 /* 140322 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
47094 /* 140327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
47095 /* 140330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47096 /* 140332 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47097 /* 140335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
47098 /* 140338 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
47099 /* 140341 */ GIR_RootConstrainSelectedInstOperands,
47100 /* 140342 */ // GIR_Coverage, 3971,
47101 /* 140342 */ GIR_EraseRootFromParent_Done,
47102 /* 140343 */ // Label 1940: @140343
47103 /* 140343 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(140475), // Rule ID 3979 //
47104 /* 140348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
47105 /* 140351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47106 /* 140355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47107 /* 140359 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47108 /* 140363 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47109 /* 140367 */ // MIs[1] Operand 1
47110 /* 140367 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
47111 /* 140372 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47112 /* 140374 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
47113 /* 140374 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47114 /* 140377 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
47115 /* 140381 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47116 /* 140386 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
47117 /* 140390 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
47118 /* 140394 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47119 /* 140396 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47120 /* 140399 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
47121 /* 140403 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47122 /* 140408 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
47123 /* 140411 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47124 /* 140413 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47125 /* 140416 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
47126 /* 140420 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47127 /* 140425 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
47128 /* 140428 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47129 /* 140430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
47130 /* 140433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47131 /* 140437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47132 /* 140442 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
47133 /* 140449 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
47134 /* 140454 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
47135 /* 140459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
47136 /* 140462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47137 /* 140464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47138 /* 140467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
47139 /* 140470 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
47140 /* 140473 */ GIR_RootConstrainSelectedInstOperands,
47141 /* 140474 */ // GIR_Coverage, 3979,
47142 /* 140474 */ GIR_EraseRootFromParent_Done,
47143 /* 140475 */ // Label 1941: @140475
47144 /* 140475 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(140607), // Rule ID 3987 //
47145 /* 140480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
47146 /* 140483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47147 /* 140487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47148 /* 140491 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47149 /* 140495 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47150 /* 140499 */ // MIs[1] Operand 1
47151 /* 140499 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
47152 /* 140504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47153 /* 140506 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
47154 /* 140506 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47155 /* 140509 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
47156 /* 140513 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47157 /* 140518 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
47158 /* 140522 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
47159 /* 140526 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47160 /* 140528 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47161 /* 140531 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
47162 /* 140535 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47163 /* 140540 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
47164 /* 140543 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47165 /* 140545 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47166 /* 140548 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
47167 /* 140552 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47168 /* 140557 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
47169 /* 140560 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47170 /* 140562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
47171 /* 140565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47172 /* 140569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47173 /* 140574 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
47174 /* 140581 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
47175 /* 140586 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
47176 /* 140591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
47177 /* 140594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47178 /* 140596 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47179 /* 140599 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
47180 /* 140602 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
47181 /* 140605 */ GIR_RootConstrainSelectedInstOperands,
47182 /* 140606 */ // GIR_Coverage, 3987,
47183 /* 140606 */ GIR_EraseRootFromParent_Done,
47184 /* 140607 */ // Label 1942: @140607
47185 /* 140607 */ GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(140739), // Rule ID 3995 //
47186 /* 140612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
47187 /* 140615 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47188 /* 140619 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47189 /* 140623 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47190 /* 140627 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47191 /* 140631 */ // MIs[1] Operand 1
47192 /* 140631 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
47193 /* 140636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47194 /* 140638 */ // (zext:{ *:[i32] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I4:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }), (LI:{ *:[i32] } 1:{ *:[i32] }))
47195 /* 140638 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47196 /* 140641 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
47197 /* 140645 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47198 /* 140650 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
47199 /* 140654 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
47200 /* 140658 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47201 /* 140660 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47202 /* 140663 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI),
47203 /* 140667 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47204 /* 140672 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
47205 /* 140675 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47206 /* 140677 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47207 /* 140680 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI),
47208 /* 140684 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47209 /* 140689 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
47210 /* 140692 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47211 /* 140694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
47212 /* 140697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47213 /* 140701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47214 /* 140706 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
47215 /* 140713 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
47216 /* 140718 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
47217 /* 140723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
47218 /* 140726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47219 /* 140728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47220 /* 140731 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
47221 /* 140734 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
47222 /* 140737 */ GIR_RootConstrainSelectedInstOperands,
47223 /* 140738 */ // GIR_Coverage, 3995,
47224 /* 140738 */ GIR_EraseRootFromParent_Done,
47225 /* 140739 */ // Label 1943: @140739
47226 /* 140739 */ GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(140754), // Rule ID 2988 //
47227 /* 140744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
47228 /* 140747 */ // (zext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SETBC:{ *:[i32] } ?:{ *:[i1] }:$in)
47229 /* 140747 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETBC),
47230 /* 140752 */ GIR_RootConstrainSelectedInstOperands,
47231 /* 140753 */ // GIR_Coverage, 2988,
47232 /* 140753 */ GIR_Done,
47233 /* 140754 */ // Label 1944: @140754
47234 /* 140754 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(140808), // Rule ID 3673 //
47235 /* 140759 */ // (zext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SELECT_I4:{ *:[i32] } ?:{ *:[i1] }:$in, (LI:{ *:[i32] } 1:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] }))
47236 /* 140759 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47237 /* 140762 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI),
47238 /* 140766 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47239 /* 140771 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
47240 /* 140774 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47241 /* 140776 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47242 /* 140779 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI),
47243 /* 140783 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47244 /* 140788 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
47245 /* 140791 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47246 /* 140793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
47247 /* 140796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47248 /* 140798 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
47249 /* 140800 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47250 /* 140803 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47251 /* 140806 */ GIR_RootConstrainSelectedInstOperands,
47252 /* 140807 */ // GIR_Coverage, 3673,
47253 /* 140807 */ GIR_EraseRootFromParent_Done,
47254 /* 140808 */ // Label 1945: @140808
47255 /* 140808 */ GIM_Reject,
47256 /* 140809 */ // Label 1853: @140809
47257 /* 140809 */ GIM_Reject,
47258 /* 140810 */ // Label 1851: @140810
47259 /* 140810 */ GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(140926), // Rule ID 5300 //
47260 /* 140815 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47261 /* 140818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47262 /* 140822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47263 /* 140826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47264 /* 140830 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47265 /* 140834 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47266 /* 140838 */ // MIs[1] Operand 1
47267 /* 140838 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
47268 /* 140843 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47269 /* 140847 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
47270 /* 140851 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
47271 /* 140855 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47272 /* 140859 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
47273 /* 140863 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
47274 /* 140867 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
47275 /* 140871 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
47276 /* 140875 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
47277 /* 140879 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47278 /* 140883 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
47279 /* 140885 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa), i64:{ *:[i64] }:$s1), 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] })
47280 /* 140885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47281 /* 140888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
47282 /* 140892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47283 /* 140897 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/2, // sa
47284 /* 140901 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/64,
47285 /* 140904 */ GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for PPC::CARRY*/0,
47286 /* 140907 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47287 /* 140909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
47288 /* 140912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47289 /* 140914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // s1
47290 /* 140918 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47291 /* 140921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47292 /* 140924 */ GIR_RootConstrainSelectedInstOperands,
47293 /* 140925 */ // GIR_Coverage, 5300,
47294 /* 140925 */ GIR_EraseRootFromParent_Done,
47295 /* 140926 */ // Label 1946: @140926
47296 /* 140926 */ GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(141096), // Rule ID 5301 //
47297 /* 140931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47298 /* 140934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47299 /* 140938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47300 /* 140942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47301 /* 140946 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47302 /* 140950 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47303 /* 140954 */ // MIs[1] Operand 1
47304 /* 140954 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
47305 /* 140959 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47306 /* 140963 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
47307 /* 140967 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
47308 /* 140971 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
47309 /* 140975 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
47310 /* 140979 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
47311 /* 140983 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
47312 /* 140987 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
47313 /* 140991 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
47314 /* 140995 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47315 /* 140999 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
47316 /* 141001 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa), i32:{ *:[i32] }:$s1), 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47317 /* 141001 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47318 /* 141004 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
47319 /* 141008 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47320 /* 141013 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, // sa
47321 /* 141017 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/32,
47322 /* 141020 */ GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for PPC::CARRY*/0,
47323 /* 141023 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47324 /* 141025 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47325 /* 141028 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
47326 /* 141032 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47327 /* 141037 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // s1
47328 /* 141041 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
47329 /* 141044 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47330 /* 141047 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47331 /* 141050 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47332 /* 141052 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47333 /* 141055 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47334 /* 141059 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47335 /* 141064 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47336 /* 141066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
47337 /* 141069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47338 /* 141071 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47339 /* 141074 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47340 /* 141077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47341 /* 141080 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
47342 /* 141085 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
47343 /* 141090 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
47344 /* 141095 */ // GIR_Coverage, 5301,
47345 /* 141095 */ GIR_EraseRootFromParent_Done,
47346 /* 141096 */ // Label 1947: @141096
47347 /* 141096 */ GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(141233), // Rule ID 5308 //
47348 /* 141101 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47349 /* 141104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47350 /* 141108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47351 /* 141112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47352 /* 141116 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47353 /* 141120 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47354 /* 141124 */ // MIs[1] Operand 1
47355 /* 141124 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
47356 /* 141129 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47357 /* 141133 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
47358 /* 141137 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
47359 /* 141141 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47360 /* 141145 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
47361 /* 141149 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
47362 /* 141153 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
47363 /* 141157 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
47364 /* 141161 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
47365 /* 141165 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47366 /* 141169 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
47367 /* 141171 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa), i64:{ *:[i64] }:$s1), 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (RLDCL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] })
47368 /* 141171 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47369 /* 141174 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
47370 /* 141178 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47371 /* 141183 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
47372 /* 141187 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/64,
47373 /* 141190 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
47374 /* 141193 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47375 /* 141195 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47376 /* 141198 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
47377 /* 141202 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47378 /* 141207 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
47379 /* 141211 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // s1
47380 /* 141215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47381 /* 141217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
47382 /* 141220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47383 /* 141222 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47384 /* 141225 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47385 /* 141228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47386 /* 141231 */ GIR_RootConstrainSelectedInstOperands,
47387 /* 141232 */ // GIR_Coverage, 5308,
47388 /* 141232 */ GIR_EraseRootFromParent_Done,
47389 /* 141233 */ // Label 1948: @141233
47390 /* 141233 */ GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(141424), // Rule ID 5309 //
47391 /* 141238 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47392 /* 141241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47393 /* 141245 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47394 /* 141249 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47395 /* 141253 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47396 /* 141257 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47397 /* 141261 */ // MIs[1] Operand 1
47398 /* 141261 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
47399 /* 141266 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47400 /* 141270 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
47401 /* 141274 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
47402 /* 141278 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
47403 /* 141282 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
47404 /* 141286 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
47405 /* 141290 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
47406 /* 141294 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
47407 /* 141298 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
47408 /* 141302 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47409 /* 141306 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
47410 /* 141308 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa), i32:{ *:[i32] }:$s1), 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWNM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47411 /* 141308 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47412 /* 141311 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
47413 /* 141315 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47414 /* 141320 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/3, /*OpIdx*/2, // sa
47415 /* 141324 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/32,
47416 /* 141327 */ GIR_SetImplicitDefDead, /*InsnID*/4, /*OpIdx for PPC::CARRY*/0,
47417 /* 141330 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47418 /* 141332 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47419 /* 141335 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
47420 /* 141339 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47421 /* 141344 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // s1
47422 /* 141348 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // s1
47423 /* 141352 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47424 /* 141354 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47425 /* 141357 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
47426 /* 141361 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47427 /* 141366 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
47428 /* 141369 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
47429 /* 141372 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47430 /* 141375 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47431 /* 141378 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47432 /* 141380 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47433 /* 141383 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47434 /* 141387 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47435 /* 141392 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47436 /* 141394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
47437 /* 141397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47438 /* 141399 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47439 /* 141402 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47440 /* 141405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47441 /* 141408 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
47442 /* 141413 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
47443 /* 141418 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
47444 /* 141423 */ // GIR_Coverage, 5309,
47445 /* 141423 */ GIR_EraseRootFromParent_Done,
47446 /* 141424 */ // Label 1949: @141424
47447 /* 141424 */ GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(141540), // Rule ID 3778 //
47448 /* 141429 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47449 /* 141432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47450 /* 141436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47451 /* 141440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47452 /* 141444 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47453 /* 141448 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47454 /* 141452 */ // MIs[1] Operand 1
47455 /* 141452 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
47456 /* 141457 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47457 /* 141461 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
47458 /* 141465 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
47459 /* 141469 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47460 /* 141473 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47461 /* 141477 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
47462 /* 141481 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
47463 /* 141485 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
47464 /* 141489 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
47465 /* 141493 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47466 /* 141497 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
47467 /* 141499 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i64] } i64:{ *:[i64] }:$s1, (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] })
47468 /* 141499 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47469 /* 141502 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
47470 /* 141506 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47471 /* 141511 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/2, // sa
47472 /* 141515 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/64,
47473 /* 141518 */ GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for PPC::CARRY*/0,
47474 /* 141521 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47475 /* 141523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
47476 /* 141526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47477 /* 141528 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // s1
47478 /* 141532 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47479 /* 141535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47480 /* 141538 */ GIR_RootConstrainSelectedInstOperands,
47481 /* 141539 */ // GIR_Coverage, 3778,
47482 /* 141539 */ GIR_EraseRootFromParent_Done,
47483 /* 141540 */ // Label 1950: @141540
47484 /* 141540 */ GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(141710), // Rule ID 3779 //
47485 /* 141545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47486 /* 141548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47487 /* 141552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47488 /* 141556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47489 /* 141560 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47490 /* 141564 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47491 /* 141568 */ // MIs[1] Operand 1
47492 /* 141568 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
47493 /* 141573 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47494 /* 141577 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
47495 /* 141581 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
47496 /* 141585 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
47497 /* 141589 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47498 /* 141593 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
47499 /* 141597 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
47500 /* 141601 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
47501 /* 141605 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
47502 /* 141609 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47503 /* 141613 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
47504 /* 141615 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i32] } i32:{ *:[i32] }:$s1, (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$s1, (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47505 /* 141615 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47506 /* 141618 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
47507 /* 141622 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47508 /* 141627 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, // sa
47509 /* 141631 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/32,
47510 /* 141634 */ GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for PPC::CARRY*/0,
47511 /* 141637 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47512 /* 141639 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47513 /* 141642 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
47514 /* 141646 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47515 /* 141651 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // s1
47516 /* 141655 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
47517 /* 141658 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47518 /* 141661 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47519 /* 141664 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47520 /* 141666 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47521 /* 141669 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47522 /* 141673 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47523 /* 141678 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47524 /* 141680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
47525 /* 141683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47526 /* 141685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47527 /* 141688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47528 /* 141691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47529 /* 141694 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
47530 /* 141699 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
47531 /* 141704 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
47532 /* 141709 */ // GIR_Coverage, 3779,
47533 /* 141709 */ GIR_EraseRootFromParent_Done,
47534 /* 141710 */ // Label 1951: @141710
47535 /* 141710 */ GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(141847), // Rule ID 3786 //
47536 /* 141715 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47537 /* 141718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47538 /* 141722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47539 /* 141726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47540 /* 141730 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47541 /* 141734 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47542 /* 141738 */ // MIs[1] Operand 1
47543 /* 141738 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
47544 /* 141743 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47545 /* 141747 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
47546 /* 141751 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
47547 /* 141755 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47548 /* 141759 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47549 /* 141763 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
47550 /* 141767 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
47551 /* 141771 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
47552 /* 141775 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
47553 /* 141779 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47554 /* 141783 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
47555 /* 141785 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i64] } i64:{ *:[i64] }:$s1, (shl:{ *:[i64] } 1:{ *:[i64] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (RLDCL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 64:{ *:[i32] }), 63:{ *:[i32] })
47556 /* 141785 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47557 /* 141788 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
47558 /* 141792 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47559 /* 141797 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // sa
47560 /* 141801 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/64,
47561 /* 141804 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for PPC::CARRY*/0,
47562 /* 141807 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47563 /* 141809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47564 /* 141812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
47565 /* 141816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47566 /* 141821 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
47567 /* 141825 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // s1
47568 /* 141829 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47569 /* 141831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
47570 /* 141834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47571 /* 141836 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47572 /* 141839 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47573 /* 141842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47574 /* 141845 */ GIR_RootConstrainSelectedInstOperands,
47575 /* 141846 */ // GIR_Coverage, 3786,
47576 /* 141846 */ GIR_EraseRootFromParent_Done,
47577 /* 141847 */ // Label 1952: @141847
47578 /* 141847 */ GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(142038), // Rule ID 3787 //
47579 /* 141852 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47580 /* 141855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47581 /* 141859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47582 /* 141863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47583 /* 141867 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47584 /* 141871 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47585 /* 141875 */ // MIs[1] Operand 1
47586 /* 141875 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
47587 /* 141880 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47588 /* 141884 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
47589 /* 141888 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
47590 /* 141892 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
47591 /* 141896 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47592 /* 141900 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
47593 /* 141904 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
47594 /* 141908 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
47595 /* 141912 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
47596 /* 141916 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47597 /* 141920 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
47598 /* 141922 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } (and:{ *:[i32] } i32:{ *:[i32] }:$s1, (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$sa)), 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWNM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$sa, 32:{ *:[i32] }), 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47599 /* 141922 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47600 /* 141925 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::SUBFIC),
47601 /* 141929 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47602 /* 141934 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/3, /*OpIdx*/2, // sa
47603 /* 141938 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/32,
47604 /* 141941 */ GIR_SetImplicitDefDead, /*InsnID*/4, /*OpIdx for PPC::CARRY*/0,
47605 /* 141944 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47606 /* 141946 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47607 /* 141949 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
47608 /* 141953 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47609 /* 141958 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // s1
47610 /* 141962 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // s1
47611 /* 141966 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47612 /* 141968 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47613 /* 141971 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
47614 /* 141975 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47615 /* 141980 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
47616 /* 141983 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
47617 /* 141986 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47618 /* 141989 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47619 /* 141992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47620 /* 141994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47621 /* 141997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47622 /* 142001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47623 /* 142006 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47624 /* 142008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
47625 /* 142011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47626 /* 142013 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47627 /* 142016 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47628 /* 142019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47629 /* 142022 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
47630 /* 142027 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
47631 /* 142032 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
47632 /* 142037 */ // GIR_Coverage, 3787,
47633 /* 142037 */ GIR_EraseRootFromParent_Done,
47634 /* 142038 */ // Label 1953: @142038
47635 /* 142038 */ GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(142121), // Rule ID 3357 //
47636 /* 142043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
47637 /* 142046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
47638 /* 142049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47639 /* 142053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47640 /* 142057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
47641 /* 142061 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
47642 /* 142065 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47643 /* 142069 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
47644 /* 142073 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BSWAP),
47645 /* 142077 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
47646 /* 142081 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
47647 /* 142085 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
47648 /* 142087 */ // (zext:{ *:[i64] } (srl:{ *:[i32] } (bswap:{ *:[i32] } i32:{ *:[i32] }:$RS), 16:{ *:[i32] })) => (RLDICL_32_64:{ *:[i64] } (BRH:{ *:[i32] } ?:{ *:[i32] }:$RS), 0:{ *:[i32] }, 48:{ *:[i32] })
47649 /* 142087 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47650 /* 142090 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::BRH),
47651 /* 142094 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47652 /* 142099 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // RS
47653 /* 142103 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47654 /* 142105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL_32_64),
47655 /* 142108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47656 /* 142110 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47657 /* 142113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47658 /* 142116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/48,
47659 /* 142119 */ GIR_RootConstrainSelectedInstOperands,
47660 /* 142120 */ // GIR_Coverage, 3357,
47661 /* 142120 */ GIR_EraseRootFromParent_Done,
47662 /* 142121 */ // Label 1954: @142121
47663 /* 142121 */ GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(142194), // Rule ID 3698 //
47664 /* 142126 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47665 /* 142129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47666 /* 142133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47667 /* 142137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47668 /* 142141 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47669 /* 142145 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47670 /* 142149 */ // MIs[1] Operand 1
47671 /* 142149 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
47672 /* 142154 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47673 /* 142158 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47674 /* 142160 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETEQ:{ *:[Other] })) => (RLDICL:{ *:[i64] } (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1), 58:{ *:[i32] }, 63:{ *:[i32] })
47675 /* 142160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47676 /* 142163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
47677 /* 142167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47678 /* 142172 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
47679 /* 142176 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47680 /* 142178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
47681 /* 142181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47682 /* 142183 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47683 /* 142186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/58,
47684 /* 142189 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47685 /* 142192 */ GIR_RootConstrainSelectedInstOperands,
47686 /* 142193 */ // GIR_Coverage, 3698,
47687 /* 142193 */ GIR_EraseRootFromParent_Done,
47688 /* 142194 */ // Label 1955: @142194
47689 /* 142194 */ GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(142321), // Rule ID 3699 //
47690 /* 142199 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47691 /* 142202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47692 /* 142206 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47693 /* 142210 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47694 /* 142214 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47695 /* 142218 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47696 /* 142222 */ // MIs[1] Operand 1
47697 /* 142222 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
47698 /* 142227 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47699 /* 142231 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47700 /* 142233 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETEQ:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1), 27:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47701 /* 142233 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47702 /* 142236 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
47703 /* 142240 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47704 /* 142245 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
47705 /* 142249 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47706 /* 142251 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47707 /* 142254 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
47708 /* 142258 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47709 /* 142263 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
47710 /* 142266 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/27,
47711 /* 142269 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47712 /* 142272 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47713 /* 142275 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47714 /* 142277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47715 /* 142280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47716 /* 142284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47717 /* 142289 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47718 /* 142291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
47719 /* 142294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47720 /* 142296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47721 /* 142299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47722 /* 142302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47723 /* 142305 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
47724 /* 142310 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
47725 /* 142315 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
47726 /* 142320 */ // GIR_Coverage, 3699,
47727 /* 142320 */ GIR_EraseRootFromParent_Done,
47728 /* 142321 */ // Label 1956: @142321
47729 /* 142321 */ GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(142432), // Rule ID 3706 //
47730 /* 142326 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47731 /* 142329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47732 /* 142333 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47733 /* 142337 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47734 /* 142341 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47735 /* 142345 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47736 /* 142349 */ // MIs[1] Operand 1
47737 /* 142349 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
47738 /* 142354 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47739 /* 142358 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47740 /* 142360 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETNE:{ *:[Other] })) => (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1), (CNTLZD:{ *:[i64] } ?:{ *:[i64] }:$s1)), 58:{ *:[i32] }, 63:{ *:[i32] })
47741 /* 142360 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
47742 /* 142363 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
47743 /* 142367 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47744 /* 142372 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
47745 /* 142376 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47746 /* 142378 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
47747 /* 142381 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
47748 /* 142385 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47749 /* 142390 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
47750 /* 142394 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47751 /* 142396 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47752 /* 142399 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
47753 /* 142403 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47754 /* 142408 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
47755 /* 142411 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
47756 /* 142414 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47757 /* 142416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
47758 /* 142419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47759 /* 142421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47760 /* 142424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/58,
47761 /* 142427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47762 /* 142430 */ GIR_RootConstrainSelectedInstOperands,
47763 /* 142431 */ // GIR_Coverage, 3706,
47764 /* 142431 */ GIR_EraseRootFromParent_Done,
47765 /* 142432 */ // Label 1957: @142432
47766 /* 142432 */ GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(142597), // Rule ID 3707 //
47767 /* 142437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47768 /* 142440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47769 /* 142444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47770 /* 142448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47771 /* 142452 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47772 /* 142456 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47773 /* 142460 */ // MIs[1] Operand 1
47774 /* 142460 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
47775 /* 142465 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47776 /* 142469 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47777 /* 142471 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETNE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1), (CNTLZW:{ *:[i32] } ?:{ *:[i32] }:$s1)), 27:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47778 /* 142471 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
47779 /* 142474 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
47780 /* 142478 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47781 /* 142483 */ GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // s1
47782 /* 142487 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
47783 /* 142489 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47784 /* 142492 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
47785 /* 142496 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47786 /* 142501 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
47787 /* 142505 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47788 /* 142507 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47789 /* 142510 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
47790 /* 142514 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47791 /* 142519 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
47792 /* 142522 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
47793 /* 142525 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47794 /* 142527 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47795 /* 142530 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
47796 /* 142534 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47797 /* 142539 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
47798 /* 142542 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/27,
47799 /* 142545 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47800 /* 142548 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47801 /* 142551 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47802 /* 142553 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47803 /* 142556 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47804 /* 142560 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47805 /* 142565 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47806 /* 142567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
47807 /* 142570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47808 /* 142572 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47809 /* 142575 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47810 /* 142578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47811 /* 142581 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
47812 /* 142586 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
47813 /* 142591 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
47814 /* 142596 */ // GIR_Coverage, 3707,
47815 /* 142596 */ GIR_EraseRootFromParent_Done,
47816 /* 142597 */ // Label 1958: @142597
47817 /* 142597 */ GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(142653), // Rule ID 3714 //
47818 /* 142602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47819 /* 142605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47820 /* 142609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47821 /* 142613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47822 /* 142617 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47823 /* 142621 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47824 /* 142625 */ // MIs[1] Operand 1
47825 /* 142625 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
47826 /* 142630 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47827 /* 142634 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47828 /* 142636 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETLT:{ *:[Other] })) => (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i32] }, 63:{ *:[i32] })
47829 /* 142636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
47830 /* 142639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47831 /* 142641 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // s1
47832 /* 142645 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47833 /* 142648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47834 /* 142651 */ GIR_RootConstrainSelectedInstOperands,
47835 /* 142652 */ // GIR_Coverage, 3714,
47836 /* 142652 */ GIR_EraseRootFromParent_Done,
47837 /* 142653 */ // Label 1959: @142653
47838 /* 142653 */ GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(142763), // Rule ID 3715 //
47839 /* 142658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47840 /* 142661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47841 /* 142665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47842 /* 142669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47843 /* 142673 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47844 /* 142677 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47845 /* 142681 */ // MIs[1] Operand 1
47846 /* 142681 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
47847 /* 142686 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47848 /* 142690 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47849 /* 142692 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETLT:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47850 /* 142692 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47851 /* 142695 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
47852 /* 142699 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47853 /* 142704 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
47854 /* 142708 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
47855 /* 142711 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47856 /* 142714 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47857 /* 142717 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47858 /* 142719 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47859 /* 142722 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47860 /* 142726 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47861 /* 142731 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47862 /* 142733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
47863 /* 142736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47864 /* 142738 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47865 /* 142741 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47866 /* 142744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47867 /* 142747 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
47868 /* 142752 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
47869 /* 142757 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
47870 /* 142762 */ // GIR_Coverage, 3715,
47871 /* 142762 */ GIR_EraseRootFromParent_Done,
47872 /* 142763 */ // Label 1960: @142763
47873 /* 142763 */ GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(142840), // Rule ID 3722 //
47874 /* 142768 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47875 /* 142771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47876 /* 142775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47877 /* 142779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47878 /* 142783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47879 /* 142787 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47880 /* 142791 */ // MIs[1] Operand 1
47881 /* 142791 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
47882 /* 142796 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47883 /* 142800 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47884 /* 142802 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETGE:{ *:[Other] })) => (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] })
47885 /* 142802 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47886 /* 142805 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
47887 /* 142809 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47888 /* 142814 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
47889 /* 142818 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
47890 /* 142822 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47891 /* 142824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
47892 /* 142827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47893 /* 142829 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47894 /* 142832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47895 /* 142835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47896 /* 142838 */ GIR_RootConstrainSelectedInstOperands,
47897 /* 142839 */ // GIR_Coverage, 3722,
47898 /* 142839 */ GIR_EraseRootFromParent_Done,
47899 /* 142840 */ // Label 1961: @142840
47900 /* 142840 */ GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(142971), // Rule ID 3723 //
47901 /* 142845 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47902 /* 142848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47903 /* 142852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47904 /* 142856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47905 /* 142860 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47906 /* 142864 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47907 /* 142868 */ // MIs[1] Operand 1
47908 /* 142868 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
47909 /* 142873 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47910 /* 142877 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47911 /* 142879 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETGE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47912 /* 142879 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47913 /* 142882 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
47914 /* 142886 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47915 /* 142891 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
47916 /* 142895 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
47917 /* 142899 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47918 /* 142901 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47919 /* 142904 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
47920 /* 142908 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47921 /* 142913 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
47922 /* 142916 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
47923 /* 142919 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47924 /* 142922 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
47925 /* 142925 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47926 /* 142927 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47927 /* 142930 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47928 /* 142934 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47929 /* 142939 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47930 /* 142941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
47931 /* 142944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47932 /* 142946 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47933 /* 142949 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
47934 /* 142952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47935 /* 142955 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
47936 /* 142960 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
47937 /* 142965 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
47938 /* 142970 */ // GIR_Coverage, 3723,
47939 /* 142970 */ GIR_EraseRootFromParent_Done,
47940 /* 142971 */ // Label 1962: @142971
47941 /* 142971 */ GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(143065), // Rule ID 3730 //
47942 /* 142976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47943 /* 142979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47944 /* 142983 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47945 /* 142987 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47946 /* 142991 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47947 /* 142995 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
47948 /* 142999 */ // MIs[1] Operand 1
47949 /* 142999 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
47950 /* 143004 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47951 /* 143008 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47952 /* 143010 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETGT:{ *:[Other] })) => (RLDICL:{ *:[i64] } (ANDC8:{ *:[i64] } (NEG8:{ *:[i64] } ?:{ *:[i64] }:$s1), ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] })
47953 /* 143010 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
47954 /* 143013 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NEG8),
47955 /* 143017 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47956 /* 143022 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
47957 /* 143026 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
47958 /* 143028 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47959 /* 143031 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::ANDC8),
47960 /* 143035 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47961 /* 143040 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
47962 /* 143043 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
47963 /* 143047 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47964 /* 143049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
47965 /* 143052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
47966 /* 143054 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47967 /* 143057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
47968 /* 143060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
47969 /* 143063 */ GIR_RootConstrainSelectedInstOperands,
47970 /* 143064 */ // GIR_Coverage, 3730,
47971 /* 143064 */ GIR_EraseRootFromParent_Done,
47972 /* 143065 */ // Label 1963: @143065
47973 /* 143065 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(143213), // Rule ID 3731 //
47974 /* 143070 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
47975 /* 143073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
47976 /* 143077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47977 /* 143081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
47978 /* 143085 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47979 /* 143089 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47980 /* 143093 */ // MIs[1] Operand 1
47981 /* 143093 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
47982 /* 143098 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
47983 /* 143102 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47984 /* 143104 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETGT:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (ANDC:{ *:[i32] } (NEG:{ *:[i32] } ?:{ *:[i32] }:$s1), ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
47985 /* 143104 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
47986 /* 143107 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::NEG),
47987 /* 143111 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47988 /* 143116 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
47989 /* 143120 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
47990 /* 143122 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
47991 /* 143125 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::ANDC),
47992 /* 143129 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47993 /* 143134 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
47994 /* 143137 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
47995 /* 143141 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
47996 /* 143143 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
47997 /* 143146 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
47998 /* 143150 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47999 /* 143155 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
48000 /* 143158 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
48001 /* 143161 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48002 /* 143164 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48003 /* 143167 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48004 /* 143169 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48005 /* 143172 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48006 /* 143176 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48007 /* 143181 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48008 /* 143183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
48009 /* 143186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48010 /* 143188 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48011 /* 143191 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48012 /* 143194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48013 /* 143197 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
48014 /* 143202 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
48015 /* 143207 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
48016 /* 143212 */ // GIR_Coverage, 3731,
48017 /* 143212 */ GIR_EraseRootFromParent_Done,
48018 /* 143213 */ // Label 1964: @143213
48019 /* 143213 */ GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(143307), // Rule ID 3738 //
48020 /* 143218 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48021 /* 143221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48022 /* 143225 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48023 /* 143229 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48024 /* 143233 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48025 /* 143237 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48026 /* 143241 */ // MIs[1] Operand 1
48027 /* 143241 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
48028 /* 143246 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
48029 /* 143250 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48030 /* 143252 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, 0:{ *:[i64] }, SETLE:{ *:[Other] })) => (RLDICL:{ *:[i64] } (ORC8:{ *:[i64] } ?:{ *:[i64] }:$s1, (NEG8:{ *:[i64] } ?:{ *:[i64] }:$s1)), 1:{ *:[i32] }, 63:{ *:[i32] })
48031 /* 143252 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
48032 /* 143255 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::NEG8),
48033 /* 143259 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48034 /* 143264 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48035 /* 143268 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48036 /* 143270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48037 /* 143273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::ORC8),
48038 /* 143277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48039 /* 143282 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
48040 /* 143286 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
48041 /* 143289 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48042 /* 143291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
48043 /* 143294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
48044 /* 143296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48045 /* 143299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48046 /* 143302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
48047 /* 143305 */ GIR_RootConstrainSelectedInstOperands,
48048 /* 143306 */ // GIR_Coverage, 3738,
48049 /* 143306 */ GIR_EraseRootFromParent_Done,
48050 /* 143307 */ // Label 1965: @143307
48051 /* 143307 */ GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(143455), // Rule ID 3739 //
48052 /* 143312 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48053 /* 143315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48054 /* 143319 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48055 /* 143323 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48056 /* 143327 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48057 /* 143331 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48058 /* 143335 */ // MIs[1] Operand 1
48059 /* 143335 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
48060 /* 143340 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
48061 /* 143344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48062 /* 143346 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, 0:{ *:[i32] }, SETLE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (ORC:{ *:[i32] } ?:{ *:[i32] }:$s1, (NEG:{ *:[i32] } ?:{ *:[i32] }:$s1)), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
48063 /* 143346 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
48064 /* 143349 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::NEG),
48065 /* 143353 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48066 /* 143358 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
48067 /* 143362 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48068 /* 143364 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
48069 /* 143367 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::ORC),
48070 /* 143371 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48071 /* 143376 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
48072 /* 143380 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
48073 /* 143383 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48074 /* 143385 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48075 /* 143388 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
48076 /* 143392 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48077 /* 143397 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
48078 /* 143400 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
48079 /* 143403 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48080 /* 143406 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48081 /* 143409 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48082 /* 143411 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48083 /* 143414 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48084 /* 143418 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48085 /* 143423 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48086 /* 143425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
48087 /* 143428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48088 /* 143430 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48089 /* 143433 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48090 /* 143436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48091 /* 143439 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
48092 /* 143444 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
48093 /* 143449 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
48094 /* 143454 */ // GIR_Coverage, 3739,
48095 /* 143454 */ GIR_EraseRootFromParent_Done,
48096 /* 143455 */ // Label 1966: @143455
48097 /* 143455 */ GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(143552), // Rule ID 3746 //
48098 /* 143460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48099 /* 143463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48100 /* 143467 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48101 /* 143471 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48102 /* 143475 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48103 /* 143479 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48104 /* 143483 */ // MIs[1] Operand 1
48105 /* 143483 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
48106 /* 143488 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
48107 /* 143492 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48108 /* 143494 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETLT:{ *:[Other] })) => (RLDICL:{ *:[i64] } (AND8:{ *:[i64] } ?:{ *:[i64] }:$s1, (ADDI8:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i64] })), 1:{ *:[i32] }, 63:{ *:[i32] })
48109 /* 143494 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
48110 /* 143497 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
48111 /* 143501 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48112 /* 143506 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48113 /* 143510 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
48114 /* 143513 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48115 /* 143515 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48116 /* 143518 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::AND8),
48117 /* 143522 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48118 /* 143527 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
48119 /* 143531 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
48120 /* 143534 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48121 /* 143536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
48122 /* 143539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
48123 /* 143541 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48124 /* 143544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48125 /* 143547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
48126 /* 143550 */ GIR_RootConstrainSelectedInstOperands,
48127 /* 143551 */ // GIR_Coverage, 3746,
48128 /* 143551 */ GIR_EraseRootFromParent_Done,
48129 /* 143552 */ // Label 1967: @143552
48130 /* 143552 */ GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(143703), // Rule ID 3747 //
48131 /* 143557 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48132 /* 143560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48133 /* 143564 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48134 /* 143568 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48135 /* 143572 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48136 /* 143576 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48137 /* 143580 */ // MIs[1] Operand 1
48138 /* 143580 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
48139 /* 143585 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
48140 /* 143589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48141 /* 143591 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETLT:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (AND:{ *:[i32] } ?:{ *:[i32] }:$s1, (ADDI:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] })), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
48142 /* 143591 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
48143 /* 143594 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::ADDI),
48144 /* 143598 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48145 /* 143603 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
48146 /* 143607 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
48147 /* 143610 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48148 /* 143612 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
48149 /* 143615 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::AND),
48150 /* 143619 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48151 /* 143624 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
48152 /* 143628 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
48153 /* 143631 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48154 /* 143633 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48155 /* 143636 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
48156 /* 143640 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48157 /* 143645 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
48158 /* 143648 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
48159 /* 143651 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48160 /* 143654 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48161 /* 143657 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48162 /* 143659 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48163 /* 143662 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48164 /* 143666 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48165 /* 143671 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48166 /* 143673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
48167 /* 143676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48168 /* 143678 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48169 /* 143681 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48170 /* 143684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48171 /* 143687 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
48172 /* 143692 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
48173 /* 143697 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
48174 /* 143702 */ // GIR_Coverage, 3747,
48175 /* 143702 */ GIR_EraseRootFromParent_Done,
48176 /* 143703 */ // Label 1968: @143703
48177 /* 143703 */ GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(143800), // Rule ID 3754 //
48178 /* 143708 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48179 /* 143711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48180 /* 143715 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48181 /* 143719 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48182 /* 143723 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48183 /* 143727 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48184 /* 143731 */ // MIs[1] Operand 1
48185 /* 143731 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
48186 /* 143736 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
48187 /* 143740 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48188 /* 143742 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETGE:{ *:[Other] })) => (RLDICL:{ *:[i64] } (NAND8:{ *:[i64] } ?:{ *:[i64] }:$s1, (ADDI8:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i64] })), 1:{ *:[i32] }, 63:{ *:[i32] })
48189 /* 143742 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
48190 /* 143745 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::ADDI8),
48191 /* 143749 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48192 /* 143754 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48193 /* 143758 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
48194 /* 143761 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48195 /* 143763 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48196 /* 143766 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NAND8),
48197 /* 143770 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48198 /* 143775 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
48199 /* 143779 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
48200 /* 143782 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48201 /* 143784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
48202 /* 143787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
48203 /* 143789 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48204 /* 143792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48205 /* 143795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
48206 /* 143798 */ GIR_RootConstrainSelectedInstOperands,
48207 /* 143799 */ // GIR_Coverage, 3754,
48208 /* 143799 */ GIR_EraseRootFromParent_Done,
48209 /* 143800 */ // Label 1969: @143800
48210 /* 143800 */ GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(143951), // Rule ID 3755 //
48211 /* 143805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48212 /* 143808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48213 /* 143812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48214 /* 143816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48215 /* 143820 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48216 /* 143824 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48217 /* 143828 */ // MIs[1] Operand 1
48218 /* 143828 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
48219 /* 143833 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
48220 /* 143837 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48221 /* 143839 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETGE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (NAND:{ *:[i32] } ?:{ *:[i32] }:$s1, (ADDI:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] })), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
48222 /* 143839 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
48223 /* 143842 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::ADDI),
48224 /* 143846 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48225 /* 143851 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // s1
48226 /* 143855 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
48227 /* 143858 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48228 /* 143860 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
48229 /* 143863 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NAND),
48230 /* 143867 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48231 /* 143872 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
48232 /* 143876 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
48233 /* 143879 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48234 /* 143881 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48235 /* 143884 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
48236 /* 143888 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48237 /* 143893 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
48238 /* 143896 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
48239 /* 143899 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48240 /* 143902 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48241 /* 143905 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48242 /* 143907 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48243 /* 143910 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48244 /* 143914 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48245 /* 143919 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48246 /* 143921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
48247 /* 143924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48248 /* 143926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48249 /* 143929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48250 /* 143932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48251 /* 143935 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
48252 /* 143940 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
48253 /* 143945 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
48254 /* 143950 */ // GIR_Coverage, 3755,
48255 /* 143950 */ GIR_EraseRootFromParent_Done,
48256 /* 143951 */ // Label 1970: @143951
48257 /* 143951 */ GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(144028), // Rule ID 3762 //
48258 /* 143956 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48259 /* 143959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48260 /* 143963 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48261 /* 143967 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48262 /* 143971 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48263 /* 143975 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48264 /* 143979 */ // MIs[1] Operand 1
48265 /* 143979 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
48266 /* 143984 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
48267 /* 143988 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48268 /* 143990 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETGT:{ *:[Other] })) => (RLDICL:{ *:[i64] } (NOR8:{ *:[i64] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s1), 1:{ *:[i32] }, 63:{ *:[i32] })
48269 /* 143990 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48270 /* 143993 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::NOR8),
48271 /* 143997 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48272 /* 144002 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
48273 /* 144006 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // s1
48274 /* 144010 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48275 /* 144012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
48276 /* 144015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
48277 /* 144017 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48278 /* 144020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48279 /* 144023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
48280 /* 144026 */ GIR_RootConstrainSelectedInstOperands,
48281 /* 144027 */ // GIR_Coverage, 3762,
48282 /* 144027 */ GIR_EraseRootFromParent_Done,
48283 /* 144028 */ // Label 1971: @144028
48284 /* 144028 */ GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(144159), // Rule ID 3763 //
48285 /* 144033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48286 /* 144036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48287 /* 144040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48288 /* 144044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48289 /* 144048 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48290 /* 144052 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48291 /* 144056 */ // MIs[1] Operand 1
48292 /* 144056 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
48293 /* 144061 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
48294 /* 144065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48295 /* 144067 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETGT:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } (NOR:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s1), 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
48296 /* 144067 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
48297 /* 144070 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::NOR),
48298 /* 144074 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48299 /* 144079 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
48300 /* 144083 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // s1
48301 /* 144087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48302 /* 144089 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48303 /* 144092 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
48304 /* 144096 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48305 /* 144101 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
48306 /* 144104 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
48307 /* 144107 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48308 /* 144110 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48309 /* 144113 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48310 /* 144115 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48311 /* 144118 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48312 /* 144122 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48313 /* 144127 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48314 /* 144129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
48315 /* 144132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48316 /* 144134 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48317 /* 144137 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48318 /* 144140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48319 /* 144143 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
48320 /* 144148 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
48321 /* 144153 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
48322 /* 144158 */ // GIR_Coverage, 3763,
48323 /* 144158 */ GIR_EraseRootFromParent_Done,
48324 /* 144159 */ // Label 1972: @144159
48325 /* 144159 */ GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(144215), // Rule ID 3770 //
48326 /* 144164 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48327 /* 144167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48328 /* 144171 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48329 /* 144175 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48330 /* 144179 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48331 /* 144183 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48332 /* 144187 */ // MIs[1] Operand 1
48333 /* 144187 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
48334 /* 144192 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
48335 /* 144196 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48336 /* 144198 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, -1:{ *:[i64] }, SETLE:{ *:[Other] })) => (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$s1, 1:{ *:[i32] }, 63:{ *:[i32] })
48337 /* 144198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
48338 /* 144201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
48339 /* 144203 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // s1
48340 /* 144207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48341 /* 144210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
48342 /* 144213 */ GIR_RootConstrainSelectedInstOperands,
48343 /* 144214 */ // GIR_Coverage, 3770,
48344 /* 144214 */ GIR_EraseRootFromParent_Done,
48345 /* 144215 */ // Label 1973: @144215
48346 /* 144215 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(144325), // Rule ID 3771 //
48347 /* 144220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48348 /* 144223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48349 /* 144227 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48350 /* 144231 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48351 /* 144235 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48352 /* 144239 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48353 /* 144243 */ // MIs[1] Operand 1
48354 /* 144243 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
48355 /* 144248 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
48356 /* 144252 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48357 /* 144254 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, -1:{ *:[i32] }, SETLE:{ *:[Other] })) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$s1, 1:{ *:[i32] }, 31:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })
48358 /* 144254 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48359 /* 144257 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
48360 /* 144261 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48361 /* 144266 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48362 /* 144270 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
48363 /* 144273 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48364 /* 144276 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
48365 /* 144279 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48366 /* 144281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
48367 /* 144284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48368 /* 144288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48369 /* 144293 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48370 /* 144295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
48371 /* 144298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48372 /* 144300 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48373 /* 144303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48374 /* 144306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
48375 /* 144309 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
48376 /* 144314 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
48377 /* 144319 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
48378 /* 144324 */ // GIR_Coverage, 3771,
48379 /* 144324 */ GIR_EraseRootFromParent_Done,
48380 /* 144325 */ // Label 1974: @144325
48381 /* 144325 */ GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(144435), // Rule ID 3037 //
48382 /* 144330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
48383 /* 144333 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48384 /* 144336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48385 /* 144340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48386 /* 144344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48387 /* 144348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48388 /* 144352 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48389 /* 144356 */ // MIs[1] Operand 1
48390 /* 144356 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
48391 /* 144361 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48392 /* 144365 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48393 /* 144369 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
48394 /* 144373 */ // MIs[2] Operand 1
48395 /* 144373 */ // No operand predicates
48396 /* 144373 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48397 /* 144375 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }))
48398 /* 144375 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48399 /* 144378 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
48400 /* 144382 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48401 /* 144387 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48402 /* 144391 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48403 /* 144394 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48404 /* 144396 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48405 /* 144399 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48406 /* 144403 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48407 /* 144408 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
48408 /* 144415 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48409 /* 144420 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48410 /* 144425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48411 /* 144428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48412 /* 144430 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48413 /* 144433 */ GIR_RootConstrainSelectedInstOperands,
48414 /* 144434 */ // GIR_Coverage, 3037,
48415 /* 144434 */ GIR_EraseRootFromParent_Done,
48416 /* 144435 */ // Label 1975: @144435
48417 /* 144435 */ GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(144545), // Rule ID 3053 //
48418 /* 144440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
48419 /* 144443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48420 /* 144446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48421 /* 144450 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48422 /* 144454 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48423 /* 144458 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48424 /* 144462 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48425 /* 144466 */ // MIs[1] Operand 1
48426 /* 144466 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
48427 /* 144471 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48428 /* 144475 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48429 /* 144479 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
48430 /* 144483 */ // MIs[2] Operand 1
48431 /* 144483 */ // No operand predicates
48432 /* 144483 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48433 /* 144485 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }))
48434 /* 144485 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48435 /* 144488 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
48436 /* 144492 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48437 /* 144497 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48438 /* 144501 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48439 /* 144504 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48440 /* 144506 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48441 /* 144509 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48442 /* 144513 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48443 /* 144518 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
48444 /* 144525 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48445 /* 144530 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48446 /* 144535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48447 /* 144538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48448 /* 144540 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48449 /* 144543 */ GIR_RootConstrainSelectedInstOperands,
48450 /* 144544 */ // GIR_Coverage, 3053,
48451 /* 144544 */ GIR_EraseRootFromParent_Done,
48452 /* 144545 */ // Label 1976: @144545
48453 /* 144545 */ GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(144655), // Rule ID 3061 //
48454 /* 144550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
48455 /* 144553 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48456 /* 144556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48457 /* 144560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48458 /* 144564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48459 /* 144568 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48460 /* 144572 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48461 /* 144576 */ // MIs[1] Operand 1
48462 /* 144576 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
48463 /* 144581 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48464 /* 144585 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48465 /* 144589 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
48466 /* 144593 */ // MIs[2] Operand 1
48467 /* 144593 */ // No operand predicates
48468 /* 144593 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48469 /* 144595 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }))
48470 /* 144595 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48471 /* 144598 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
48472 /* 144602 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48473 /* 144607 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48474 /* 144611 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48475 /* 144614 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48476 /* 144616 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48477 /* 144619 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48478 /* 144623 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48479 /* 144628 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
48480 /* 144635 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48481 /* 144640 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48482 /* 144645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48483 /* 144648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48484 /* 144650 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48485 /* 144653 */ GIR_RootConstrainSelectedInstOperands,
48486 /* 144654 */ // GIR_Coverage, 3061,
48487 /* 144654 */ GIR_EraseRootFromParent_Done,
48488 /* 144655 */ // Label 1977: @144655
48489 /* 144655 */ GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(144765), // Rule ID 3133 //
48490 /* 144660 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
48491 /* 144663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48492 /* 144666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48493 /* 144670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48494 /* 144674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48495 /* 144678 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48496 /* 144682 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48497 /* 144686 */ // MIs[1] Operand 1
48498 /* 144686 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
48499 /* 144691 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48500 /* 144695 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48501 /* 144699 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
48502 /* 144703 */ // MIs[2] Operand 1
48503 /* 144703 */ // No operand predicates
48504 /* 144703 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48505 /* 144705 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }))
48506 /* 144705 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48507 /* 144708 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
48508 /* 144712 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48509 /* 144717 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48510 /* 144721 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48511 /* 144724 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48512 /* 144726 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48513 /* 144729 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48514 /* 144733 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48515 /* 144738 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
48516 /* 144745 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48517 /* 144750 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48518 /* 144755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48519 /* 144758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48520 /* 144760 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48521 /* 144763 */ GIR_RootConstrainSelectedInstOperands,
48522 /* 144764 */ // GIR_Coverage, 3133,
48523 /* 144764 */ GIR_EraseRootFromParent_Done,
48524 /* 144765 */ // Label 1978: @144765
48525 /* 144765 */ GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(144875), // Rule ID 3149 //
48526 /* 144770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
48527 /* 144773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48528 /* 144776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48529 /* 144780 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48530 /* 144784 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48531 /* 144788 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48532 /* 144792 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48533 /* 144796 */ // MIs[1] Operand 1
48534 /* 144796 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
48535 /* 144801 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48536 /* 144805 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48537 /* 144809 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
48538 /* 144813 */ // MIs[2] Operand 1
48539 /* 144813 */ // No operand predicates
48540 /* 144813 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48541 /* 144815 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }))
48542 /* 144815 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48543 /* 144818 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
48544 /* 144822 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48545 /* 144827 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48546 /* 144831 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48547 /* 144834 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48548 /* 144836 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48549 /* 144839 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48550 /* 144843 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48551 /* 144848 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
48552 /* 144855 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48553 /* 144860 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48554 /* 144865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48555 /* 144868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48556 /* 144870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48557 /* 144873 */ GIR_RootConstrainSelectedInstOperands,
48558 /* 144874 */ // GIR_Coverage, 3149,
48559 /* 144874 */ GIR_EraseRootFromParent_Done,
48560 /* 144875 */ // Label 1979: @144875
48561 /* 144875 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(144985), // Rule ID 3157 //
48562 /* 144880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
48563 /* 144883 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48564 /* 144886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48565 /* 144890 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48566 /* 144894 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48567 /* 144898 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48568 /* 144902 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48569 /* 144906 */ // MIs[1] Operand 1
48570 /* 144906 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
48571 /* 144911 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48572 /* 144915 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48573 /* 144919 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
48574 /* 144923 */ // MIs[2] Operand 1
48575 /* 144923 */ // No operand predicates
48576 /* 144923 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48577 /* 144925 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }))
48578 /* 144925 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48579 /* 144928 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
48580 /* 144932 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48581 /* 144937 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48582 /* 144941 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48583 /* 144944 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48584 /* 144946 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48585 /* 144949 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48586 /* 144953 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48587 /* 144958 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
48588 /* 144965 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48589 /* 144970 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48590 /* 144975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48591 /* 144978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48592 /* 144980 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48593 /* 144983 */ GIR_RootConstrainSelectedInstOperands,
48594 /* 144984 */ // GIR_Coverage, 3157,
48595 /* 144984 */ GIR_EraseRootFromParent_Done,
48596 /* 144985 */ // Label 1980: @144985
48597 /* 144985 */ GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(145135), // Rule ID 3821 //
48598 /* 144990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
48599 /* 144993 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48600 /* 144996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48601 /* 145000 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48602 /* 145004 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48603 /* 145008 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48604 /* 145012 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48605 /* 145016 */ // MIs[1] Operand 1
48606 /* 145016 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
48607 /* 145021 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48608 /* 145025 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48609 /* 145029 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
48610 /* 145033 */ // MIs[2] Operand 1
48611 /* 145033 */ // No operand predicates
48612 /* 145033 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48613 /* 145035 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
48614 /* 145035 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48615 /* 145038 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
48616 /* 145042 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48617 /* 145047 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48618 /* 145051 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48619 /* 145054 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48620 /* 145056 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
48621 /* 145059 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
48622 /* 145063 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48623 /* 145068 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
48624 /* 145071 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48625 /* 145073 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
48626 /* 145076 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
48627 /* 145080 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48628 /* 145085 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
48629 /* 145088 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48630 /* 145090 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48631 /* 145093 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48632 /* 145097 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48633 /* 145102 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
48634 /* 145109 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48635 /* 145114 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48636 /* 145119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
48637 /* 145122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48638 /* 145124 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48639 /* 145127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
48640 /* 145130 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
48641 /* 145133 */ GIR_RootConstrainSelectedInstOperands,
48642 /* 145134 */ // GIR_Coverage, 3821,
48643 /* 145134 */ GIR_EraseRootFromParent_Done,
48644 /* 145135 */ // Label 1981: @145135
48645 /* 145135 */ GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(145285), // Rule ID 3837 //
48646 /* 145140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
48647 /* 145143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48648 /* 145146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48649 /* 145150 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48650 /* 145154 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48651 /* 145158 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48652 /* 145162 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48653 /* 145166 */ // MIs[1] Operand 1
48654 /* 145166 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
48655 /* 145171 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48656 /* 145175 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48657 /* 145179 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
48658 /* 145183 */ // MIs[2] Operand 1
48659 /* 145183 */ // No operand predicates
48660 /* 145183 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48661 /* 145185 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
48662 /* 145185 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48663 /* 145188 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
48664 /* 145192 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48665 /* 145197 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48666 /* 145201 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48667 /* 145204 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48668 /* 145206 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
48669 /* 145209 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
48670 /* 145213 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48671 /* 145218 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
48672 /* 145221 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48673 /* 145223 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
48674 /* 145226 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
48675 /* 145230 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48676 /* 145235 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
48677 /* 145238 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48678 /* 145240 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48679 /* 145243 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48680 /* 145247 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48681 /* 145252 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
48682 /* 145259 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48683 /* 145264 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48684 /* 145269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
48685 /* 145272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48686 /* 145274 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48687 /* 145277 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
48688 /* 145280 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
48689 /* 145283 */ GIR_RootConstrainSelectedInstOperands,
48690 /* 145284 */ // GIR_Coverage, 3837,
48691 /* 145284 */ GIR_EraseRootFromParent_Done,
48692 /* 145285 */ // Label 1982: @145285
48693 /* 145285 */ GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(145435), // Rule ID 3845 //
48694 /* 145290 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
48695 /* 145293 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48696 /* 145296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48697 /* 145300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48698 /* 145304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48699 /* 145308 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48700 /* 145312 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48701 /* 145316 */ // MIs[1] Operand 1
48702 /* 145316 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
48703 /* 145321 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48704 /* 145325 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48705 /* 145329 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
48706 /* 145333 */ // MIs[2] Operand 1
48707 /* 145333 */ // No operand predicates
48708 /* 145333 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48709 /* 145335 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
48710 /* 145335 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48711 /* 145338 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
48712 /* 145342 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48713 /* 145347 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48714 /* 145351 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48715 /* 145354 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48716 /* 145356 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
48717 /* 145359 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
48718 /* 145363 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48719 /* 145368 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
48720 /* 145371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48721 /* 145373 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
48722 /* 145376 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
48723 /* 145380 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48724 /* 145385 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
48725 /* 145388 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48726 /* 145390 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48727 /* 145393 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48728 /* 145397 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48729 /* 145402 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
48730 /* 145409 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48731 /* 145414 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48732 /* 145419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
48733 /* 145422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48734 /* 145424 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48735 /* 145427 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
48736 /* 145430 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
48737 /* 145433 */ GIR_RootConstrainSelectedInstOperands,
48738 /* 145434 */ // GIR_Coverage, 3845,
48739 /* 145434 */ GIR_EraseRootFromParent_Done,
48740 /* 145435 */ // Label 1983: @145435
48741 /* 145435 */ GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(145585), // Rule ID 3917 //
48742 /* 145440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
48743 /* 145443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48744 /* 145446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48745 /* 145450 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48746 /* 145454 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48747 /* 145458 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48748 /* 145462 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48749 /* 145466 */ // MIs[1] Operand 1
48750 /* 145466 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
48751 /* 145471 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48752 /* 145475 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48753 /* 145479 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
48754 /* 145483 */ // MIs[2] Operand 1
48755 /* 145483 */ // No operand predicates
48756 /* 145483 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48757 /* 145485 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
48758 /* 145485 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48759 /* 145488 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
48760 /* 145492 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48761 /* 145497 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48762 /* 145501 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48763 /* 145504 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48764 /* 145506 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
48765 /* 145509 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
48766 /* 145513 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48767 /* 145518 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
48768 /* 145521 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48769 /* 145523 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
48770 /* 145526 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
48771 /* 145530 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48772 /* 145535 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
48773 /* 145538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48774 /* 145540 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48775 /* 145543 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48776 /* 145547 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48777 /* 145552 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
48778 /* 145559 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48779 /* 145564 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48780 /* 145569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
48781 /* 145572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48782 /* 145574 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48783 /* 145577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
48784 /* 145580 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
48785 /* 145583 */ GIR_RootConstrainSelectedInstOperands,
48786 /* 145584 */ // GIR_Coverage, 3917,
48787 /* 145584 */ GIR_EraseRootFromParent_Done,
48788 /* 145585 */ // Label 1984: @145585
48789 /* 145585 */ GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(145735), // Rule ID 3933 //
48790 /* 145590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
48791 /* 145593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48792 /* 145596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48793 /* 145600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48794 /* 145604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48795 /* 145608 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48796 /* 145612 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48797 /* 145616 */ // MIs[1] Operand 1
48798 /* 145616 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
48799 /* 145621 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48800 /* 145625 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48801 /* 145629 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
48802 /* 145633 */ // MIs[2] Operand 1
48803 /* 145633 */ // No operand predicates
48804 /* 145633 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48805 /* 145635 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
48806 /* 145635 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48807 /* 145638 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
48808 /* 145642 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48809 /* 145647 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48810 /* 145651 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48811 /* 145654 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48812 /* 145656 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
48813 /* 145659 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
48814 /* 145663 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48815 /* 145668 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
48816 /* 145671 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48817 /* 145673 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
48818 /* 145676 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
48819 /* 145680 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48820 /* 145685 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
48821 /* 145688 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48822 /* 145690 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48823 /* 145693 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48824 /* 145697 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48825 /* 145702 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
48826 /* 145709 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48827 /* 145714 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48828 /* 145719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
48829 /* 145722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48830 /* 145724 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48831 /* 145727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
48832 /* 145730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
48833 /* 145733 */ GIR_RootConstrainSelectedInstOperands,
48834 /* 145734 */ // GIR_Coverage, 3933,
48835 /* 145734 */ GIR_EraseRootFromParent_Done,
48836 /* 145735 */ // Label 1985: @145735
48837 /* 145735 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(145885), // Rule ID 3941 //
48838 /* 145740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
48839 /* 145743 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48840 /* 145746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48841 /* 145750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48842 /* 145754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
48843 /* 145758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48844 /* 145762 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
48845 /* 145766 */ // MIs[1] Operand 1
48846 /* 145766 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
48847 /* 145771 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
48848 /* 145775 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48849 /* 145779 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
48850 /* 145783 */ // MIs[2] Operand 1
48851 /* 145783 */ // No operand predicates
48852 /* 145783 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
48853 /* 145785 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
48854 /* 145785 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48855 /* 145788 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
48856 /* 145792 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48857 /* 145797 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48858 /* 145801 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm
48859 /* 145804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48860 /* 145806 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
48861 /* 145809 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
48862 /* 145813 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48863 /* 145818 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
48864 /* 145821 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
48865 /* 145823 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
48866 /* 145826 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
48867 /* 145830 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48868 /* 145835 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
48869 /* 145838 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
48870 /* 145840 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48871 /* 145843 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48872 /* 145847 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48873 /* 145852 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
48874 /* 145859 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48875 /* 145864 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48876 /* 145869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
48877 /* 145872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
48878 /* 145874 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48879 /* 145877 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
48880 /* 145880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
48881 /* 145883 */ GIR_RootConstrainSelectedInstOperands,
48882 /* 145884 */ // GIR_Coverage, 3941,
48883 /* 145884 */ GIR_EraseRootFromParent_Done,
48884 /* 145885 */ // Label 1986: @145885
48885 /* 145885 */ GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(145984), // Rule ID 3181 //
48886 /* 145890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
48887 /* 145893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48888 /* 145896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48889 /* 145900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48890 /* 145904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
48891 /* 145908 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48892 /* 145912 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48893 /* 145916 */ // MIs[1] Operand 1
48894 /* 145916 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
48895 /* 145921 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48896 /* 145923 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }))
48897 /* 145923 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48898 /* 145926 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
48899 /* 145930 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48900 /* 145935 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48901 /* 145939 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
48902 /* 145943 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48903 /* 145945 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48904 /* 145948 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48905 /* 145952 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48906 /* 145957 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
48907 /* 145964 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48908 /* 145969 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48909 /* 145974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48910 /* 145977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48911 /* 145979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48912 /* 145982 */ GIR_RootConstrainSelectedInstOperands,
48913 /* 145983 */ // GIR_Coverage, 3181,
48914 /* 145983 */ GIR_EraseRootFromParent_Done,
48915 /* 145984 */ // Label 1987: @145984
48916 /* 145984 */ GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(146083), // Rule ID 3197 //
48917 /* 145989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
48918 /* 145992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48919 /* 145995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48920 /* 145999 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48921 /* 146003 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
48922 /* 146007 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48923 /* 146011 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48924 /* 146015 */ // MIs[1] Operand 1
48925 /* 146015 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
48926 /* 146020 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48927 /* 146022 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
48928 /* 146022 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48929 /* 146025 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
48930 /* 146029 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48931 /* 146034 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48932 /* 146038 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
48933 /* 146042 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48934 /* 146044 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48935 /* 146047 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48936 /* 146051 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48937 /* 146056 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
48938 /* 146063 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48939 /* 146068 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48940 /* 146073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48941 /* 146076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48942 /* 146078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48943 /* 146081 */ GIR_RootConstrainSelectedInstOperands,
48944 /* 146082 */ // GIR_Coverage, 3197,
48945 /* 146082 */ GIR_EraseRootFromParent_Done,
48946 /* 146083 */ // Label 1988: @146083
48947 /* 146083 */ GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(146182), // Rule ID 3213 //
48948 /* 146088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
48949 /* 146091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48950 /* 146094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48951 /* 146098 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48952 /* 146102 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
48953 /* 146106 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48954 /* 146110 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48955 /* 146114 */ // MIs[1] Operand 1
48956 /* 146114 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
48957 /* 146119 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48958 /* 146121 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }))
48959 /* 146121 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48960 /* 146124 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
48961 /* 146128 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48962 /* 146133 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48963 /* 146137 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
48964 /* 146141 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48965 /* 146143 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48966 /* 146146 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48967 /* 146150 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48968 /* 146155 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
48969 /* 146162 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
48970 /* 146167 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
48971 /* 146172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
48972 /* 146175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
48973 /* 146177 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48974 /* 146180 */ GIR_RootConstrainSelectedInstOperands,
48975 /* 146181 */ // GIR_Coverage, 3213,
48976 /* 146181 */ GIR_EraseRootFromParent_Done,
48977 /* 146182 */ // Label 1989: @146182
48978 /* 146182 */ GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(146281), // Rule ID 3229 //
48979 /* 146187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
48980 /* 146190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
48981 /* 146193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
48982 /* 146197 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
48983 /* 146201 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
48984 /* 146205 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
48985 /* 146209 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
48986 /* 146213 */ // MIs[1] Operand 1
48987 /* 146213 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
48988 /* 146218 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48989 /* 146220 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }))
48990 /* 146220 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
48991 /* 146223 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
48992 /* 146227 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48993 /* 146232 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
48994 /* 146236 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
48995 /* 146240 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
48996 /* 146242 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
48997 /* 146245 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
48998 /* 146249 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48999 /* 146254 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
49000 /* 146261 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49001 /* 146266 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49002 /* 146271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49003 /* 146274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49004 /* 146276 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49005 /* 146279 */ GIR_RootConstrainSelectedInstOperands,
49006 /* 146280 */ // GIR_Coverage, 3229,
49007 /* 146280 */ GIR_EraseRootFromParent_Done,
49008 /* 146281 */ // Label 1990: @146281
49009 /* 146281 */ GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(146380), // Rule ID 3237 //
49010 /* 146286 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
49011 /* 146289 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49012 /* 146292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49013 /* 146296 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49014 /* 146300 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49015 /* 146304 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49016 /* 146308 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49017 /* 146312 */ // MIs[1] Operand 1
49018 /* 146312 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
49019 /* 146317 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49020 /* 146319 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }))
49021 /* 146319 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49022 /* 146322 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
49023 /* 146326 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49024 /* 146331 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49025 /* 146335 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49026 /* 146339 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49027 /* 146341 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49028 /* 146344 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49029 /* 146348 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49030 /* 146353 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
49031 /* 146360 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49032 /* 146365 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49033 /* 146370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49034 /* 146373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49035 /* 146375 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49036 /* 146378 */ GIR_RootConstrainSelectedInstOperands,
49037 /* 146379 */ // GIR_Coverage, 3237,
49038 /* 146379 */ GIR_EraseRootFromParent_Done,
49039 /* 146380 */ // Label 1991: @146380
49040 /* 146380 */ GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(146479), // Rule ID 3253 //
49041 /* 146385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
49042 /* 146388 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49043 /* 146391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49044 /* 146395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49045 /* 146399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49046 /* 146403 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49047 /* 146407 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49048 /* 146411 */ // MIs[1] Operand 1
49049 /* 146411 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
49050 /* 146416 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49051 /* 146418 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
49052 /* 146418 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49053 /* 146421 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
49054 /* 146425 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49055 /* 146430 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49056 /* 146434 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49057 /* 146438 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49058 /* 146440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49059 /* 146443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49060 /* 146447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49061 /* 146452 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49062 /* 146459 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49063 /* 146464 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49064 /* 146469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49065 /* 146472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49066 /* 146474 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49067 /* 146477 */ GIR_RootConstrainSelectedInstOperands,
49068 /* 146478 */ // GIR_Coverage, 3253,
49069 /* 146478 */ GIR_EraseRootFromParent_Done,
49070 /* 146479 */ // Label 1992: @146479
49071 /* 146479 */ GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(146578), // Rule ID 3269 //
49072 /* 146484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
49073 /* 146487 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49074 /* 146490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49075 /* 146494 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49076 /* 146498 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49077 /* 146502 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49078 /* 146506 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49079 /* 146510 */ // MIs[1] Operand 1
49080 /* 146510 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
49081 /* 146515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49082 /* 146517 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }))
49083 /* 146517 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49084 /* 146520 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
49085 /* 146524 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49086 /* 146529 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49087 /* 146533 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49088 /* 146537 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49089 /* 146539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49090 /* 146542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49091 /* 146546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49092 /* 146551 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
49093 /* 146558 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49094 /* 146563 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49095 /* 146568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49096 /* 146571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49097 /* 146573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49098 /* 146576 */ GIR_RootConstrainSelectedInstOperands,
49099 /* 146577 */ // GIR_Coverage, 3269,
49100 /* 146577 */ GIR_EraseRootFromParent_Done,
49101 /* 146578 */ // Label 1993: @146578
49102 /* 146578 */ GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(146677), // Rule ID 3285 //
49103 /* 146583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
49104 /* 146586 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49105 /* 146589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49106 /* 146593 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49107 /* 146597 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49108 /* 146601 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49109 /* 146605 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49110 /* 146609 */ // MIs[1] Operand 1
49111 /* 146609 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
49112 /* 146614 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49113 /* 146616 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }))
49114 /* 146616 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49115 /* 146619 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
49116 /* 146623 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49117 /* 146628 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49118 /* 146632 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49119 /* 146636 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49120 /* 146638 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49121 /* 146641 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49122 /* 146645 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49123 /* 146650 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
49124 /* 146657 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49125 /* 146662 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49126 /* 146667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49127 /* 146670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49128 /* 146672 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49129 /* 146675 */ GIR_RootConstrainSelectedInstOperands,
49130 /* 146676 */ // GIR_Coverage, 3285,
49131 /* 146676 */ GIR_EraseRootFromParent_Done,
49132 /* 146677 */ // Label 1994: @146677
49133 /* 146677 */ GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(146776), // Rule ID 3293 //
49134 /* 146682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
49135 /* 146685 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49136 /* 146688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49137 /* 146692 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49138 /* 146696 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49139 /* 146700 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
49140 /* 146704 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
49141 /* 146708 */ // MIs[1] Operand 1
49142 /* 146708 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
49143 /* 146713 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49144 /* 146715 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }))
49145 /* 146715 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49146 /* 146718 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
49147 /* 146722 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49148 /* 146727 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49149 /* 146731 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49150 /* 146735 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49151 /* 146737 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49152 /* 146740 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49153 /* 146744 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49154 /* 146749 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
49155 /* 146756 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49156 /* 146761 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49157 /* 146766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49158 /* 146769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49159 /* 146771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49160 /* 146774 */ GIR_RootConstrainSelectedInstOperands,
49161 /* 146775 */ // GIR_Coverage, 3293,
49162 /* 146775 */ GIR_EraseRootFromParent_Done,
49163 /* 146776 */ // Label 1995: @146776
49164 /* 146776 */ GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(146875), // Rule ID 3309 //
49165 /* 146781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
49166 /* 146784 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49167 /* 146787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49168 /* 146791 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49169 /* 146795 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49170 /* 146799 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
49171 /* 146803 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
49172 /* 146807 */ // MIs[1] Operand 1
49173 /* 146807 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
49174 /* 146812 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49175 /* 146814 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }))
49176 /* 146814 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49177 /* 146817 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
49178 /* 146821 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49179 /* 146826 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49180 /* 146830 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49181 /* 146834 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49182 /* 146836 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49183 /* 146839 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49184 /* 146843 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49185 /* 146848 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49186 /* 146855 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49187 /* 146860 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49188 /* 146865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49189 /* 146868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49190 /* 146870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49191 /* 146873 */ GIR_RootConstrainSelectedInstOperands,
49192 /* 146874 */ // GIR_Coverage, 3309,
49193 /* 146874 */ GIR_EraseRootFromParent_Done,
49194 /* 146875 */ // Label 1996: @146875
49195 /* 146875 */ GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(146974), // Rule ID 3325 //
49196 /* 146880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
49197 /* 146883 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49198 /* 146886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49199 /* 146890 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49200 /* 146894 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49201 /* 146898 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
49202 /* 146902 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
49203 /* 146906 */ // MIs[1] Operand 1
49204 /* 146906 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
49205 /* 146911 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49206 /* 146913 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }))
49207 /* 146913 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49208 /* 146916 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
49209 /* 146920 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49210 /* 146925 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49211 /* 146929 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49212 /* 146933 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49213 /* 146935 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49214 /* 146938 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49215 /* 146942 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49216 /* 146947 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
49217 /* 146954 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49218 /* 146959 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49219 /* 146964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49220 /* 146967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49221 /* 146969 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49222 /* 146972 */ GIR_RootConstrainSelectedInstOperands,
49223 /* 146973 */ // GIR_Coverage, 3325,
49224 /* 146973 */ GIR_EraseRootFromParent_Done,
49225 /* 146974 */ // Label 1997: @146974
49226 /* 146974 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(147073), // Rule ID 3341 //
49227 /* 146979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
49228 /* 146982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49229 /* 146985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49230 /* 146989 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49231 /* 146993 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49232 /* 146997 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
49233 /* 147001 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
49234 /* 147005 */ // MIs[1] Operand 1
49235 /* 147005 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
49236 /* 147010 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49237 /* 147012 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }))
49238 /* 147012 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49239 /* 147015 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
49240 /* 147019 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49241 /* 147024 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49242 /* 147028 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49243 /* 147032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49244 /* 147034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49245 /* 147037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49246 /* 147041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49247 /* 147046 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
49248 /* 147053 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49249 /* 147058 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49250 /* 147063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
49251 /* 147066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
49252 /* 147068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49253 /* 147071 */ GIR_RootConstrainSelectedInstOperands,
49254 /* 147072 */ // GIR_Coverage, 3341,
49255 /* 147072 */ GIR_EraseRootFromParent_Done,
49256 /* 147073 */ // Label 1998: @147073
49257 /* 147073 */ GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(147212), // Rule ID 4024 //
49258 /* 147078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49259 /* 147081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49260 /* 147084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49261 /* 147088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49262 /* 147092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49263 /* 147096 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
49264 /* 147100 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
49265 /* 147104 */ // MIs[1] Operand 1
49266 /* 147104 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
49267 /* 147109 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49268 /* 147111 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49269 /* 147111 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49270 /* 147114 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
49271 /* 147118 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49272 /* 147123 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49273 /* 147127 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49274 /* 147131 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49275 /* 147133 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49276 /* 147136 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49277 /* 147140 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49278 /* 147145 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49279 /* 147148 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49280 /* 147150 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49281 /* 147153 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49282 /* 147157 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49283 /* 147162 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49284 /* 147165 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49285 /* 147167 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49286 /* 147170 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49287 /* 147174 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49288 /* 147179 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
49289 /* 147186 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49290 /* 147191 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49291 /* 147196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49292 /* 147199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49293 /* 147201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49294 /* 147204 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49295 /* 147207 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49296 /* 147210 */ GIR_RootConstrainSelectedInstOperands,
49297 /* 147211 */ // GIR_Coverage, 4024,
49298 /* 147211 */ GIR_EraseRootFromParent_Done,
49299 /* 147212 */ // Label 1999: @147212
49300 /* 147212 */ GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(147351), // Rule ID 4056 //
49301 /* 147217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49302 /* 147220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49303 /* 147223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49304 /* 147227 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49305 /* 147231 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49306 /* 147235 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
49307 /* 147239 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
49308 /* 147243 */ // MIs[1] Operand 1
49309 /* 147243 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
49310 /* 147248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49311 /* 147250 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49312 /* 147250 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49313 /* 147253 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
49314 /* 147257 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49315 /* 147262 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49316 /* 147266 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49317 /* 147270 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49318 /* 147272 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49319 /* 147275 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49320 /* 147279 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49321 /* 147284 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49322 /* 147287 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49323 /* 147289 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49324 /* 147292 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49325 /* 147296 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49326 /* 147301 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49327 /* 147304 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49328 /* 147306 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49329 /* 147309 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49330 /* 147313 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49331 /* 147318 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49332 /* 147325 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49333 /* 147330 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49334 /* 147335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49335 /* 147338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49336 /* 147340 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49337 /* 147343 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49338 /* 147346 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49339 /* 147349 */ GIR_RootConstrainSelectedInstOperands,
49340 /* 147350 */ // GIR_Coverage, 4056,
49341 /* 147350 */ GIR_EraseRootFromParent_Done,
49342 /* 147351 */ // Label 2000: @147351
49343 /* 147351 */ GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(147490), // Rule ID 4088 //
49344 /* 147356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49345 /* 147359 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49346 /* 147362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49347 /* 147366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49348 /* 147370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49349 /* 147374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
49350 /* 147378 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
49351 /* 147382 */ // MIs[1] Operand 1
49352 /* 147382 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
49353 /* 147387 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49354 /* 147389 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49355 /* 147389 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49356 /* 147392 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
49357 /* 147396 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49358 /* 147401 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49359 /* 147405 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49360 /* 147409 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49361 /* 147411 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49362 /* 147414 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49363 /* 147418 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49364 /* 147423 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49365 /* 147426 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49366 /* 147428 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49367 /* 147431 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49368 /* 147435 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49369 /* 147440 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49370 /* 147443 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49371 /* 147445 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49372 /* 147448 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49373 /* 147452 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49374 /* 147457 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
49375 /* 147464 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49376 /* 147469 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49377 /* 147474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49378 /* 147477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49379 /* 147479 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49380 /* 147482 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49381 /* 147485 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49382 /* 147488 */ GIR_RootConstrainSelectedInstOperands,
49383 /* 147489 */ // GIR_Coverage, 4088,
49384 /* 147489 */ GIR_EraseRootFromParent_Done,
49385 /* 147490 */ // Label 2001: @147490
49386 /* 147490 */ GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(147629), // Rule ID 4120 //
49387 /* 147495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49388 /* 147498 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49389 /* 147501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49390 /* 147505 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49391 /* 147509 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49392 /* 147513 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
49393 /* 147517 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
49394 /* 147521 */ // MIs[1] Operand 1
49395 /* 147521 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
49396 /* 147526 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49397 /* 147528 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49398 /* 147528 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49399 /* 147531 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
49400 /* 147535 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49401 /* 147540 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49402 /* 147544 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49403 /* 147548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49404 /* 147550 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49405 /* 147553 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49406 /* 147557 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49407 /* 147562 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49408 /* 147565 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49409 /* 147567 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49410 /* 147570 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49411 /* 147574 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49412 /* 147579 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49413 /* 147582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49414 /* 147584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49415 /* 147587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49416 /* 147591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49417 /* 147596 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
49418 /* 147603 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49419 /* 147608 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49420 /* 147613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49421 /* 147616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49422 /* 147618 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49423 /* 147621 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49424 /* 147624 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49425 /* 147627 */ GIR_RootConstrainSelectedInstOperands,
49426 /* 147628 */ // GIR_Coverage, 4120,
49427 /* 147628 */ GIR_EraseRootFromParent_Done,
49428 /* 147629 */ // Label 2002: @147629
49429 /* 147629 */ GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(147768), // Rule ID 4136 //
49430 /* 147634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49431 /* 147637 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49432 /* 147640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49433 /* 147644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49434 /* 147648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49435 /* 147652 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49436 /* 147656 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49437 /* 147660 */ // MIs[1] Operand 1
49438 /* 147660 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
49439 /* 147665 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49440 /* 147667 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49441 /* 147667 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49442 /* 147670 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
49443 /* 147674 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49444 /* 147679 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49445 /* 147683 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49446 /* 147687 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49447 /* 147689 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49448 /* 147692 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49449 /* 147696 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49450 /* 147701 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49451 /* 147704 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49452 /* 147706 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49453 /* 147709 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49454 /* 147713 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49455 /* 147718 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49456 /* 147721 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49457 /* 147723 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49458 /* 147726 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49459 /* 147730 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49460 /* 147735 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
49461 /* 147742 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49462 /* 147747 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49463 /* 147752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49464 /* 147755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49465 /* 147757 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49466 /* 147760 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49467 /* 147763 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49468 /* 147766 */ GIR_RootConstrainSelectedInstOperands,
49469 /* 147767 */ // GIR_Coverage, 4136,
49470 /* 147767 */ GIR_EraseRootFromParent_Done,
49471 /* 147768 */ // Label 2003: @147768
49472 /* 147768 */ GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(147907), // Rule ID 4168 //
49473 /* 147773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49474 /* 147776 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49475 /* 147779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49476 /* 147783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49477 /* 147787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49478 /* 147791 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49479 /* 147795 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49480 /* 147799 */ // MIs[1] Operand 1
49481 /* 147799 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
49482 /* 147804 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49483 /* 147806 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49484 /* 147806 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49485 /* 147809 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
49486 /* 147813 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49487 /* 147818 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49488 /* 147822 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49489 /* 147826 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49490 /* 147828 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49491 /* 147831 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49492 /* 147835 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49493 /* 147840 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49494 /* 147843 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49495 /* 147845 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49496 /* 147848 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49497 /* 147852 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49498 /* 147857 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49499 /* 147860 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49500 /* 147862 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49501 /* 147865 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49502 /* 147869 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49503 /* 147874 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49504 /* 147881 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49505 /* 147886 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49506 /* 147891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49507 /* 147894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49508 /* 147896 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49509 /* 147899 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49510 /* 147902 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49511 /* 147905 */ GIR_RootConstrainSelectedInstOperands,
49512 /* 147906 */ // GIR_Coverage, 4168,
49513 /* 147906 */ GIR_EraseRootFromParent_Done,
49514 /* 147907 */ // Label 2004: @147907
49515 /* 147907 */ GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(148046), // Rule ID 4200 //
49516 /* 147912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49517 /* 147915 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49518 /* 147918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49519 /* 147922 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49520 /* 147926 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49521 /* 147930 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49522 /* 147934 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49523 /* 147938 */ // MIs[1] Operand 1
49524 /* 147938 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
49525 /* 147943 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49526 /* 147945 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49527 /* 147945 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49528 /* 147948 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
49529 /* 147952 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49530 /* 147957 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49531 /* 147961 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49532 /* 147965 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49533 /* 147967 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49534 /* 147970 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49535 /* 147974 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49536 /* 147979 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49537 /* 147982 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49538 /* 147984 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49539 /* 147987 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49540 /* 147991 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49541 /* 147996 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49542 /* 147999 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49543 /* 148001 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49544 /* 148004 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49545 /* 148008 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49546 /* 148013 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
49547 /* 148020 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49548 /* 148025 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49549 /* 148030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49550 /* 148033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49551 /* 148035 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49552 /* 148038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49553 /* 148041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49554 /* 148044 */ GIR_RootConstrainSelectedInstOperands,
49555 /* 148045 */ // GIR_Coverage, 4200,
49556 /* 148045 */ GIR_EraseRootFromParent_Done,
49557 /* 148046 */ // Label 2005: @148046
49558 /* 148046 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(148185), // Rule ID 4232 //
49559 /* 148051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49560 /* 148054 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49561 /* 148057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49562 /* 148061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49563 /* 148065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49564 /* 148069 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49565 /* 148073 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49566 /* 148077 */ // MIs[1] Operand 1
49567 /* 148077 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
49568 /* 148082 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49569 /* 148084 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49570 /* 148084 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49571 /* 148087 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
49572 /* 148091 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49573 /* 148096 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49574 /* 148100 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49575 /* 148104 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49576 /* 148106 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49577 /* 148109 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49578 /* 148113 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49579 /* 148118 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49580 /* 148121 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49581 /* 148123 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49582 /* 148126 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49583 /* 148130 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49584 /* 148135 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49585 /* 148138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49586 /* 148140 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49587 /* 148143 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49588 /* 148147 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49589 /* 148152 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
49590 /* 148159 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49591 /* 148164 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49592 /* 148169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49593 /* 148172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49594 /* 148174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49595 /* 148177 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49596 /* 148180 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49597 /* 148183 */ GIR_RootConstrainSelectedInstOperands,
49598 /* 148184 */ // GIR_Coverage, 4232,
49599 /* 148184 */ GIR_EraseRootFromParent_Done,
49600 /* 148185 */ // Label 2006: @148185
49601 /* 148185 */ GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(148324), // Rule ID 4262 //
49602 /* 148190 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49603 /* 148193 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49604 /* 148196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49605 /* 148200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49606 /* 148204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49607 /* 148208 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
49608 /* 148212 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
49609 /* 148216 */ // MIs[1] Operand 1
49610 /* 148216 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
49611 /* 148221 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49612 /* 148223 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49613 /* 148223 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49614 /* 148226 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
49615 /* 148230 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49616 /* 148235 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49617 /* 148239 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49618 /* 148243 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49619 /* 148245 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49620 /* 148248 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49621 /* 148252 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49622 /* 148257 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49623 /* 148260 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49624 /* 148262 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49625 /* 148265 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49626 /* 148269 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49627 /* 148274 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49628 /* 148277 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49629 /* 148279 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49630 /* 148282 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49631 /* 148286 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49632 /* 148291 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
49633 /* 148298 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49634 /* 148303 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49635 /* 148308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49636 /* 148311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49637 /* 148313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49638 /* 148316 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49639 /* 148319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49640 /* 148322 */ GIR_RootConstrainSelectedInstOperands,
49641 /* 148323 */ // GIR_Coverage, 4262,
49642 /* 148323 */ GIR_EraseRootFromParent_Done,
49643 /* 148324 */ // Label 2007: @148324
49644 /* 148324 */ GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(148463), // Rule ID 4294 //
49645 /* 148329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49646 /* 148332 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49647 /* 148335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49648 /* 148339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49649 /* 148343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49650 /* 148347 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
49651 /* 148351 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
49652 /* 148355 */ // MIs[1] Operand 1
49653 /* 148355 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
49654 /* 148360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49655 /* 148362 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49656 /* 148362 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49657 /* 148365 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
49658 /* 148369 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49659 /* 148374 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49660 /* 148378 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49661 /* 148382 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49662 /* 148384 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49663 /* 148387 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49664 /* 148391 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49665 /* 148396 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49666 /* 148399 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49667 /* 148401 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49668 /* 148404 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49669 /* 148408 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49670 /* 148413 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49671 /* 148416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49672 /* 148418 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49673 /* 148421 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49674 /* 148425 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49675 /* 148430 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49676 /* 148437 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49677 /* 148442 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49678 /* 148447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49679 /* 148450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49680 /* 148452 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49681 /* 148455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49682 /* 148458 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49683 /* 148461 */ GIR_RootConstrainSelectedInstOperands,
49684 /* 148462 */ // GIR_Coverage, 4294,
49685 /* 148462 */ GIR_EraseRootFromParent_Done,
49686 /* 148463 */ // Label 2008: @148463
49687 /* 148463 */ GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(148602), // Rule ID 4326 //
49688 /* 148468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49689 /* 148471 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49690 /* 148474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49691 /* 148478 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49692 /* 148482 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49693 /* 148486 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
49694 /* 148490 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
49695 /* 148494 */ // MIs[1] Operand 1
49696 /* 148494 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
49697 /* 148499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49698 /* 148501 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49699 /* 148501 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49700 /* 148504 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
49701 /* 148508 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49702 /* 148513 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49703 /* 148517 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49704 /* 148521 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49705 /* 148523 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49706 /* 148526 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49707 /* 148530 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49708 /* 148535 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49709 /* 148538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49710 /* 148540 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49711 /* 148543 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49712 /* 148547 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49713 /* 148552 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49714 /* 148555 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49715 /* 148557 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49716 /* 148560 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49717 /* 148564 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49718 /* 148569 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
49719 /* 148576 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49720 /* 148581 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49721 /* 148586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49722 /* 148589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49723 /* 148591 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49724 /* 148594 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49725 /* 148597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49726 /* 148600 */ GIR_RootConstrainSelectedInstOperands,
49727 /* 148601 */ // GIR_Coverage, 4326,
49728 /* 148601 */ GIR_EraseRootFromParent_Done,
49729 /* 148602 */ // Label 2009: @148602
49730 /* 148602 */ GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(148741), // Rule ID 4358 //
49731 /* 148607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
49732 /* 148610 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49733 /* 148613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49734 /* 148617 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49735 /* 148621 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49736 /* 148625 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
49737 /* 148629 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
49738 /* 148633 */ // MIs[1] Operand 1
49739 /* 148633 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
49740 /* 148638 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49741 /* 148640 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49742 /* 148640 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49743 /* 148643 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
49744 /* 148647 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49745 /* 148652 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49746 /* 148656 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49747 /* 148660 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49748 /* 148662 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49749 /* 148665 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49750 /* 148669 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49751 /* 148674 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49752 /* 148677 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49753 /* 148679 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49754 /* 148682 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49755 /* 148686 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49756 /* 148691 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49757 /* 148694 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49758 /* 148696 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49759 /* 148699 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49760 /* 148703 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49761 /* 148708 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
49762 /* 148715 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49763 /* 148720 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49764 /* 148725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49765 /* 148728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49766 /* 148730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49767 /* 148733 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49768 /* 148736 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49769 /* 148739 */ GIR_RootConstrainSelectedInstOperands,
49770 /* 148740 */ // GIR_Coverage, 4358,
49771 /* 148740 */ GIR_EraseRootFromParent_Done,
49772 /* 148741 */ // Label 2010: @148741
49773 /* 148741 */ GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(148880), // Rule ID 4589 //
49774 /* 148746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
49775 /* 148749 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49776 /* 148752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49777 /* 148756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49778 /* 148760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49779 /* 148764 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
49780 /* 148768 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
49781 /* 148772 */ // MIs[1] Operand 1
49782 /* 148772 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
49783 /* 148777 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49784 /* 148779 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49785 /* 148779 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49786 /* 148782 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
49787 /* 148786 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49788 /* 148791 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49789 /* 148795 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49790 /* 148799 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49791 /* 148801 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49792 /* 148804 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49793 /* 148808 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49794 /* 148813 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49795 /* 148816 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49796 /* 148818 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49797 /* 148821 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49798 /* 148825 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49799 /* 148830 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49800 /* 148833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49801 /* 148835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49802 /* 148838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49803 /* 148842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49804 /* 148847 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49805 /* 148854 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49806 /* 148859 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49807 /* 148864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49808 /* 148867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49809 /* 148869 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49810 /* 148872 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49811 /* 148875 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49812 /* 148878 */ GIR_RootConstrainSelectedInstOperands,
49813 /* 148879 */ // GIR_Coverage, 4589,
49814 /* 148879 */ GIR_EraseRootFromParent_Done,
49815 /* 148880 */ // Label 2011: @148880
49816 /* 148880 */ GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(149019), // Rule ID 4621 //
49817 /* 148885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
49818 /* 148888 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49819 /* 148891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49820 /* 148895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49821 /* 148899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49822 /* 148903 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
49823 /* 148907 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
49824 /* 148911 */ // MIs[1] Operand 1
49825 /* 148911 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
49826 /* 148916 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49827 /* 148918 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49828 /* 148918 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49829 /* 148921 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
49830 /* 148925 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49831 /* 148930 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49832 /* 148934 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49833 /* 148938 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49834 /* 148940 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49835 /* 148943 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49836 /* 148947 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49837 /* 148952 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49838 /* 148955 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49839 /* 148957 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49840 /* 148960 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49841 /* 148964 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49842 /* 148969 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49843 /* 148972 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49844 /* 148974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49845 /* 148977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49846 /* 148981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49847 /* 148986 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49848 /* 148993 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49849 /* 148998 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49850 /* 149003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49851 /* 149006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49852 /* 149008 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49853 /* 149011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49854 /* 149014 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49855 /* 149017 */ GIR_RootConstrainSelectedInstOperands,
49856 /* 149018 */ // GIR_Coverage, 4621,
49857 /* 149018 */ GIR_EraseRootFromParent_Done,
49858 /* 149019 */ // Label 2012: @149019
49859 /* 149019 */ GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(149158), // Rule ID 4653 //
49860 /* 149024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
49861 /* 149027 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49862 /* 149030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49863 /* 149034 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49864 /* 149038 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49865 /* 149042 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
49866 /* 149046 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
49867 /* 149050 */ // MIs[1] Operand 1
49868 /* 149050 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
49869 /* 149055 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49870 /* 149057 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49871 /* 149057 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49872 /* 149060 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
49873 /* 149064 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49874 /* 149069 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49875 /* 149073 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49876 /* 149077 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49877 /* 149079 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49878 /* 149082 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49879 /* 149086 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49880 /* 149091 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49881 /* 149094 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49882 /* 149096 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49883 /* 149099 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49884 /* 149103 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49885 /* 149108 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49886 /* 149111 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49887 /* 149113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49888 /* 149116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49889 /* 149120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49890 /* 149125 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49891 /* 149132 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49892 /* 149137 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49893 /* 149142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49894 /* 149145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49895 /* 149147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49896 /* 149150 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49897 /* 149153 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49898 /* 149156 */ GIR_RootConstrainSelectedInstOperands,
49899 /* 149157 */ // GIR_Coverage, 4653,
49900 /* 149157 */ GIR_EraseRootFromParent_Done,
49901 /* 149158 */ // Label 2013: @149158
49902 /* 149158 */ GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(149297), // Rule ID 4697 //
49903 /* 149163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
49904 /* 149166 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49905 /* 149169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49906 /* 149173 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49907 /* 149177 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49908 /* 149181 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49909 /* 149185 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49910 /* 149189 */ // MIs[1] Operand 1
49911 /* 149189 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
49912 /* 149194 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49913 /* 149196 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49914 /* 149196 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49915 /* 149199 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
49916 /* 149203 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49917 /* 149208 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49918 /* 149212 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49919 /* 149216 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49920 /* 149218 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49921 /* 149221 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49922 /* 149225 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49923 /* 149230 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49924 /* 149233 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49925 /* 149235 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49926 /* 149238 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49927 /* 149242 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49928 /* 149247 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49929 /* 149250 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49930 /* 149252 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49931 /* 149255 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49932 /* 149259 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49933 /* 149264 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49934 /* 149271 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49935 /* 149276 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49936 /* 149281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49937 /* 149284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49938 /* 149286 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49939 /* 149289 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49940 /* 149292 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49941 /* 149295 */ GIR_RootConstrainSelectedInstOperands,
49942 /* 149296 */ // GIR_Coverage, 4697,
49943 /* 149296 */ GIR_EraseRootFromParent_Done,
49944 /* 149297 */ // Label 2014: @149297
49945 /* 149297 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(149436), // Rule ID 4729 //
49946 /* 149302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
49947 /* 149305 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49948 /* 149308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49949 /* 149312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49950 /* 149316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49951 /* 149320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49952 /* 149324 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49953 /* 149328 */ // MIs[1] Operand 1
49954 /* 149328 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
49955 /* 149333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49956 /* 149335 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
49957 /* 149335 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
49958 /* 149338 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
49959 /* 149342 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49960 /* 149347 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
49961 /* 149351 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
49962 /* 149355 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49963 /* 149357 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
49964 /* 149360 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
49965 /* 149364 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49966 /* 149369 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
49967 /* 149372 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
49968 /* 149374 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
49969 /* 149377 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
49970 /* 149381 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49971 /* 149386 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
49972 /* 149389 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
49973 /* 149391 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
49974 /* 149394 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49975 /* 149398 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49976 /* 149403 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
49977 /* 149410 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
49978 /* 149415 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
49979 /* 149420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
49980 /* 149423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49981 /* 149425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49982 /* 149428 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
49983 /* 149431 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
49984 /* 149434 */ GIR_RootConstrainSelectedInstOperands,
49985 /* 149435 */ // GIR_Coverage, 4729,
49986 /* 149435 */ GIR_EraseRootFromParent_Done,
49987 /* 149436 */ // Label 2015: @149436
49988 /* 149436 */ GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(149575), // Rule ID 4761 //
49989 /* 149441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
49990 /* 149444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
49991 /* 149447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
49992 /* 149451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49993 /* 149455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCMP),
49994 /* 149459 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
49995 /* 149463 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
49996 /* 149467 */ // MIs[1] Operand 1
49997 /* 149467 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
49998 /* 149472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49999 /* 149474 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50000 /* 149474 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50001 /* 149477 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
50002 /* 149481 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50003 /* 149486 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50004 /* 149490 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50005 /* 149494 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50006 /* 149496 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50007 /* 149499 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50008 /* 149503 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50009 /* 149508 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50010 /* 149511 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50011 /* 149513 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50012 /* 149516 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50013 /* 149520 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50014 /* 149525 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50015 /* 149528 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50016 /* 149530 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50017 /* 149533 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50018 /* 149537 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50019 /* 149542 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50020 /* 149549 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50021 /* 149554 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50022 /* 149559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50023 /* 149562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50024 /* 149564 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50025 /* 149567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50026 /* 149570 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50027 /* 149573 */ GIR_RootConstrainSelectedInstOperands,
50028 /* 149574 */ // GIR_Coverage, 4761,
50029 /* 149574 */ GIR_EraseRootFromParent_Done,
50030 /* 149575 */ // Label 2016: @149575
50031 /* 149575 */ GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(149674), // Rule ID 2983 //
50032 /* 149580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50033 /* 149583 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50034 /* 149586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50035 /* 149590 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50036 /* 149594 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50037 /* 149598 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50038 /* 149602 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50039 /* 149606 */ // MIs[1] Operand 1
50040 /* 149606 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
50041 /* 149611 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50042 /* 149613 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
50043 /* 149613 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50044 /* 149616 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
50045 /* 149620 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50046 /* 149625 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50047 /* 149629 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50048 /* 149633 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50049 /* 149635 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50050 /* 149638 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50051 /* 149642 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50052 /* 149647 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
50053 /* 149654 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50054 /* 149659 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50055 /* 149664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50056 /* 149667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50057 /* 149669 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50058 /* 149672 */ GIR_RootConstrainSelectedInstOperands,
50059 /* 149673 */ // GIR_Coverage, 2983,
50060 /* 149673 */ GIR_EraseRootFromParent_Done,
50061 /* 149674 */ // Label 2017: @149674
50062 /* 149674 */ GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(149773), // Rule ID 2997 //
50063 /* 149679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50064 /* 149682 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50065 /* 149685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50066 /* 149689 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50067 /* 149693 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50068 /* 149697 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50069 /* 149701 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50070 /* 149705 */ // MIs[1] Operand 1
50071 /* 149705 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
50072 /* 149710 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50073 /* 149712 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
50074 /* 149712 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50075 /* 149715 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
50076 /* 149719 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50077 /* 149724 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50078 /* 149728 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50079 /* 149732 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50080 /* 149734 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50081 /* 149737 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50082 /* 149741 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50083 /* 149746 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
50084 /* 149753 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50085 /* 149758 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50086 /* 149763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50087 /* 149766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50088 /* 149768 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50089 /* 149771 */ GIR_RootConstrainSelectedInstOperands,
50090 /* 149772 */ // GIR_Coverage, 2997,
50091 /* 149772 */ GIR_EraseRootFromParent_Done,
50092 /* 149773 */ // Label 2018: @149773
50093 /* 149773 */ GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(149872), // Rule ID 3005 //
50094 /* 149778 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50095 /* 149781 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50096 /* 149784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50097 /* 149788 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50098 /* 149792 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50099 /* 149796 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50100 /* 149800 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50101 /* 149804 */ // MIs[1] Operand 1
50102 /* 149804 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
50103 /* 149809 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50104 /* 149811 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
50105 /* 149811 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50106 /* 149814 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
50107 /* 149818 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50108 /* 149823 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50109 /* 149827 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50110 /* 149831 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50111 /* 149833 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50112 /* 149836 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50113 /* 149840 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50114 /* 149845 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50115 /* 149852 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50116 /* 149857 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50117 /* 149862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50118 /* 149865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50119 /* 149867 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50120 /* 149870 */ GIR_RootConstrainSelectedInstOperands,
50121 /* 149871 */ // GIR_Coverage, 3005,
50122 /* 149871 */ GIR_EraseRootFromParent_Done,
50123 /* 149872 */ // Label 2019: @149872
50124 /* 149872 */ GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(149971), // Rule ID 3013 //
50125 /* 149877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50126 /* 149880 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50127 /* 149883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50128 /* 149887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50129 /* 149891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50130 /* 149895 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50131 /* 149899 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50132 /* 149903 */ // MIs[1] Operand 1
50133 /* 149903 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
50134 /* 149908 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50135 /* 149910 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
50136 /* 149910 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50137 /* 149913 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
50138 /* 149917 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50139 /* 149922 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50140 /* 149926 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50141 /* 149930 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50142 /* 149932 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50143 /* 149935 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50144 /* 149939 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50145 /* 149944 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50146 /* 149951 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50147 /* 149956 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50148 /* 149961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50149 /* 149964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50150 /* 149966 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50151 /* 149969 */ GIR_RootConstrainSelectedInstOperands,
50152 /* 149970 */ // GIR_Coverage, 3013,
50153 /* 149970 */ GIR_EraseRootFromParent_Done,
50154 /* 149971 */ // Label 2020: @149971
50155 /* 149971 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(150070), // Rule ID 3021 //
50156 /* 149976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50157 /* 149979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50158 /* 149982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50159 /* 149986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50160 /* 149990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50161 /* 149994 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50162 /* 149998 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50163 /* 150002 */ // MIs[1] Operand 1
50164 /* 150002 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
50165 /* 150007 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50166 /* 150009 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }))
50167 /* 150009 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50168 /* 150012 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
50169 /* 150016 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50170 /* 150021 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50171 /* 150025 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50172 /* 150029 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50173 /* 150031 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50174 /* 150034 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50175 /* 150038 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50176 /* 150043 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
50177 /* 150050 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50178 /* 150055 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50179 /* 150060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50180 /* 150063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50181 /* 150065 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50182 /* 150068 */ GIR_RootConstrainSelectedInstOperands,
50183 /* 150069 */ // GIR_Coverage, 3021,
50184 /* 150069 */ GIR_EraseRootFromParent_Done,
50185 /* 150070 */ // Label 2021: @150070
50186 /* 150070 */ GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(150169), // Rule ID 3085 //
50187 /* 150075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50188 /* 150078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50189 /* 150081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50190 /* 150085 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50191 /* 150089 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50192 /* 150093 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50193 /* 150097 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50194 /* 150101 */ // MIs[1] Operand 1
50195 /* 150101 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
50196 /* 150106 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50197 /* 150108 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
50198 /* 150108 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50199 /* 150111 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
50200 /* 150115 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50201 /* 150120 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50202 /* 150124 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50203 /* 150128 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50204 /* 150130 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50205 /* 150133 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50206 /* 150137 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50207 /* 150142 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
50208 /* 150149 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50209 /* 150154 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50210 /* 150159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50211 /* 150162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50212 /* 150164 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50213 /* 150167 */ GIR_RootConstrainSelectedInstOperands,
50214 /* 150168 */ // GIR_Coverage, 3085,
50215 /* 150168 */ GIR_EraseRootFromParent_Done,
50216 /* 150169 */ // Label 2022: @150169
50217 /* 150169 */ GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(150268), // Rule ID 3093 //
50218 /* 150174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50219 /* 150177 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50220 /* 150180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50221 /* 150184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50222 /* 150188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50223 /* 150192 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50224 /* 150196 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50225 /* 150200 */ // MIs[1] Operand 1
50226 /* 150200 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
50227 /* 150205 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50228 /* 150207 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
50229 /* 150207 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50230 /* 150210 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
50231 /* 150214 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50232 /* 150219 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50233 /* 150223 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50234 /* 150227 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50235 /* 150229 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50236 /* 150232 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50237 /* 150236 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50238 /* 150241 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
50239 /* 150248 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50240 /* 150253 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50241 /* 150258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50242 /* 150261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50243 /* 150263 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50244 /* 150266 */ GIR_RootConstrainSelectedInstOperands,
50245 /* 150267 */ // GIR_Coverage, 3093,
50246 /* 150267 */ GIR_EraseRootFromParent_Done,
50247 /* 150268 */ // Label 2023: @150268
50248 /* 150268 */ GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(150367), // Rule ID 3101 //
50249 /* 150273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50250 /* 150276 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50251 /* 150279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50252 /* 150283 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50253 /* 150287 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50254 /* 150291 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50255 /* 150295 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50256 /* 150299 */ // MIs[1] Operand 1
50257 /* 150299 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
50258 /* 150304 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50259 /* 150306 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
50260 /* 150306 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50261 /* 150309 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
50262 /* 150313 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50263 /* 150318 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50264 /* 150322 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50265 /* 150326 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50266 /* 150328 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50267 /* 150331 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50268 /* 150335 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50269 /* 150340 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50270 /* 150347 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50271 /* 150352 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50272 /* 150357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50273 /* 150360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50274 /* 150362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50275 /* 150365 */ GIR_RootConstrainSelectedInstOperands,
50276 /* 150366 */ // GIR_Coverage, 3101,
50277 /* 150366 */ GIR_EraseRootFromParent_Done,
50278 /* 150367 */ // Label 2024: @150367
50279 /* 150367 */ GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(150466), // Rule ID 3109 //
50280 /* 150372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50281 /* 150375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50282 /* 150378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50283 /* 150382 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50284 /* 150386 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50285 /* 150390 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50286 /* 150394 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50287 /* 150398 */ // MIs[1] Operand 1
50288 /* 150398 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
50289 /* 150403 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50290 /* 150405 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
50291 /* 150405 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50292 /* 150408 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
50293 /* 150412 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50294 /* 150417 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50295 /* 150421 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50296 /* 150425 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50297 /* 150427 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50298 /* 150430 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50299 /* 150434 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50300 /* 150439 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50301 /* 150446 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50302 /* 150451 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50303 /* 150456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50304 /* 150459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50305 /* 150461 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50306 /* 150464 */ GIR_RootConstrainSelectedInstOperands,
50307 /* 150465 */ // GIR_Coverage, 3109,
50308 /* 150465 */ GIR_EraseRootFromParent_Done,
50309 /* 150466 */ // Label 2025: @150466
50310 /* 150466 */ GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(150565), // Rule ID 3117 //
50311 /* 150471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50312 /* 150474 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50313 /* 150477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50314 /* 150481 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50315 /* 150485 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50316 /* 150489 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50317 /* 150493 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50318 /* 150497 */ // MIs[1] Operand 1
50319 /* 150497 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
50320 /* 150502 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50321 /* 150504 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SETBCR8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }))
50322 /* 150504 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50323 /* 150507 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
50324 /* 150511 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50325 /* 150516 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50326 /* 150520 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50327 /* 150524 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50328 /* 150526 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50329 /* 150529 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50330 /* 150533 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50331 /* 150538 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
50332 /* 150545 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50333 /* 150550 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50334 /* 150555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETBCR8),
50335 /* 150558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
50336 /* 150560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50337 /* 150563 */ GIR_RootConstrainSelectedInstOperands,
50338 /* 150564 */ // GIR_Coverage, 3117,
50339 /* 150564 */ GIR_EraseRootFromParent_Done,
50340 /* 150565 */ // Label 2026: @150565
50341 /* 150565 */ GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(150704), // Rule ID 3869 //
50342 /* 150570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50343 /* 150573 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50344 /* 150576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50345 /* 150580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50346 /* 150584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50347 /* 150588 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50348 /* 150592 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50349 /* 150596 */ // MIs[1] Operand 1
50350 /* 150596 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
50351 /* 150601 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50352 /* 150603 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50353 /* 150603 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50354 /* 150606 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
50355 /* 150610 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50356 /* 150615 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50357 /* 150619 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50358 /* 150623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50359 /* 150625 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50360 /* 150628 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50361 /* 150632 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50362 /* 150637 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50363 /* 150640 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50364 /* 150642 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50365 /* 150645 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50366 /* 150649 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50367 /* 150654 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50368 /* 150657 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50369 /* 150659 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50370 /* 150662 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50371 /* 150666 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50372 /* 150671 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
50373 /* 150678 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50374 /* 150683 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50375 /* 150688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50376 /* 150691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50377 /* 150693 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50378 /* 150696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50379 /* 150699 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50380 /* 150702 */ GIR_RootConstrainSelectedInstOperands,
50381 /* 150703 */ // GIR_Coverage, 3869,
50382 /* 150703 */ GIR_EraseRootFromParent_Done,
50383 /* 150704 */ // Label 2027: @150704
50384 /* 150704 */ GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(150843), // Rule ID 3877 //
50385 /* 150709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50386 /* 150712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50387 /* 150715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50388 /* 150719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50389 /* 150723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50390 /* 150727 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50391 /* 150731 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50392 /* 150735 */ // MIs[1] Operand 1
50393 /* 150735 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
50394 /* 150740 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50395 /* 150742 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50396 /* 150742 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50397 /* 150745 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
50398 /* 150749 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50399 /* 150754 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50400 /* 150758 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50401 /* 150762 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50402 /* 150764 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50403 /* 150767 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50404 /* 150771 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50405 /* 150776 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50406 /* 150779 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50407 /* 150781 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50408 /* 150784 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50409 /* 150788 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50410 /* 150793 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50411 /* 150796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50412 /* 150798 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50413 /* 150801 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50414 /* 150805 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50415 /* 150810 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
50416 /* 150817 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50417 /* 150822 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50418 /* 150827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50419 /* 150830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50420 /* 150832 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50421 /* 150835 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50422 /* 150838 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50423 /* 150841 */ GIR_RootConstrainSelectedInstOperands,
50424 /* 150842 */ // GIR_Coverage, 3877,
50425 /* 150842 */ GIR_EraseRootFromParent_Done,
50426 /* 150843 */ // Label 2028: @150843
50427 /* 150843 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(150982), // Rule ID 3885 //
50428 /* 150848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50429 /* 150851 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50430 /* 150854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50431 /* 150858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50432 /* 150862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50433 /* 150866 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50434 /* 150870 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50435 /* 150874 */ // MIs[1] Operand 1
50436 /* 150874 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
50437 /* 150879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50438 /* 150881 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50439 /* 150881 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50440 /* 150884 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
50441 /* 150888 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50442 /* 150893 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50443 /* 150897 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50444 /* 150901 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50445 /* 150903 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50446 /* 150906 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50447 /* 150910 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50448 /* 150915 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50449 /* 150918 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50450 /* 150920 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50451 /* 150923 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50452 /* 150927 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50453 /* 150932 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50454 /* 150935 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50455 /* 150937 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50456 /* 150940 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50457 /* 150944 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50458 /* 150949 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50459 /* 150956 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50460 /* 150961 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50461 /* 150966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50462 /* 150969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50463 /* 150971 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50464 /* 150974 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50465 /* 150977 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50466 /* 150980 */ GIR_RootConstrainSelectedInstOperands,
50467 /* 150981 */ // GIR_Coverage, 3885,
50468 /* 150981 */ GIR_EraseRootFromParent_Done,
50469 /* 150982 */ // Label 2029: @150982
50470 /* 150982 */ GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(151121), // Rule ID 3893 //
50471 /* 150987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50472 /* 150990 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50473 /* 150993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50474 /* 150997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50475 /* 151001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50476 /* 151005 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50477 /* 151009 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50478 /* 151013 */ // MIs[1] Operand 1
50479 /* 151013 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
50480 /* 151018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50481 /* 151020 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50482 /* 151020 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50483 /* 151023 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
50484 /* 151027 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50485 /* 151032 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50486 /* 151036 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50487 /* 151040 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50488 /* 151042 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50489 /* 151045 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50490 /* 151049 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50491 /* 151054 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50492 /* 151057 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50493 /* 151059 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50494 /* 151062 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50495 /* 151066 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50496 /* 151071 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50497 /* 151074 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50498 /* 151076 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50499 /* 151079 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50500 /* 151083 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50501 /* 151088 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50502 /* 151095 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50503 /* 151100 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50504 /* 151105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50505 /* 151108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50506 /* 151110 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50507 /* 151113 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50508 /* 151116 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50509 /* 151119 */ GIR_RootConstrainSelectedInstOperands,
50510 /* 151120 */ // GIR_Coverage, 3893,
50511 /* 151120 */ GIR_EraseRootFromParent_Done,
50512 /* 151121 */ // Label 2030: @151121
50513 /* 151121 */ GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(151260), // Rule ID 3901 //
50514 /* 151126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50515 /* 151129 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50516 /* 151132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50517 /* 151136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50518 /* 151140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50519 /* 151144 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
50520 /* 151148 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
50521 /* 151152 */ // MIs[1] Operand 1
50522 /* 151152 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
50523 /* 151157 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50524 /* 151159 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50525 /* 151159 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50526 /* 151162 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
50527 /* 151166 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50528 /* 151171 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50529 /* 151175 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50530 /* 151179 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50531 /* 151181 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50532 /* 151184 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50533 /* 151188 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50534 /* 151193 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50535 /* 151196 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50536 /* 151198 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50537 /* 151201 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50538 /* 151205 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50539 /* 151210 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50540 /* 151213 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50541 /* 151215 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50542 /* 151218 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50543 /* 151222 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50544 /* 151227 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
50545 /* 151234 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50546 /* 151239 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50547 /* 151244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50548 /* 151247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50549 /* 151249 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50550 /* 151252 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50551 /* 151255 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50552 /* 151258 */ GIR_RootConstrainSelectedInstOperands,
50553 /* 151259 */ // GIR_Coverage, 3901,
50554 /* 151259 */ GIR_EraseRootFromParent_Done,
50555 /* 151260 */ // Label 2031: @151260
50556 /* 151260 */ GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(151399), // Rule ID 3965 //
50557 /* 151265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50558 /* 151268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50559 /* 151271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50560 /* 151275 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50561 /* 151279 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50562 /* 151283 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50563 /* 151287 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50564 /* 151291 */ // MIs[1] Operand 1
50565 /* 151291 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
50566 /* 151296 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50567 /* 151298 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50568 /* 151298 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50569 /* 151301 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
50570 /* 151305 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50571 /* 151310 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50572 /* 151314 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50573 /* 151318 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50574 /* 151320 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50575 /* 151323 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50576 /* 151327 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50577 /* 151332 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50578 /* 151335 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50579 /* 151337 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50580 /* 151340 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50581 /* 151344 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50582 /* 151349 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50583 /* 151352 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50584 /* 151354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50585 /* 151357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50586 /* 151361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50587 /* 151366 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
50588 /* 151373 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50589 /* 151378 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50590 /* 151383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50591 /* 151386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50592 /* 151388 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50593 /* 151391 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50594 /* 151394 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50595 /* 151397 */ GIR_RootConstrainSelectedInstOperands,
50596 /* 151398 */ // GIR_Coverage, 3965,
50597 /* 151398 */ GIR_EraseRootFromParent_Done,
50598 /* 151399 */ // Label 2032: @151399
50599 /* 151399 */ GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(151538), // Rule ID 3973 //
50600 /* 151404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50601 /* 151407 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50602 /* 151410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50603 /* 151414 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50604 /* 151418 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50605 /* 151422 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50606 /* 151426 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50607 /* 151430 */ // MIs[1] Operand 1
50608 /* 151430 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
50609 /* 151435 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50610 /* 151437 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50611 /* 151437 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50612 /* 151440 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
50613 /* 151444 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50614 /* 151449 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50615 /* 151453 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50616 /* 151457 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50617 /* 151459 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50618 /* 151462 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50619 /* 151466 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50620 /* 151471 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50621 /* 151474 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50622 /* 151476 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50623 /* 151479 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50624 /* 151483 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50625 /* 151488 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50626 /* 151491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50627 /* 151493 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50628 /* 151496 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50629 /* 151500 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50630 /* 151505 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
50631 /* 151512 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50632 /* 151517 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50633 /* 151522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50634 /* 151525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50635 /* 151527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50636 /* 151530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50637 /* 151533 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50638 /* 151536 */ GIR_RootConstrainSelectedInstOperands,
50639 /* 151537 */ // GIR_Coverage, 3973,
50640 /* 151537 */ GIR_EraseRootFromParent_Done,
50641 /* 151538 */ // Label 2033: @151538
50642 /* 151538 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(151677), // Rule ID 3981 //
50643 /* 151543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50644 /* 151546 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50645 /* 151549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50646 /* 151553 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50647 /* 151557 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50648 /* 151561 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50649 /* 151565 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50650 /* 151569 */ // MIs[1] Operand 1
50651 /* 151569 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
50652 /* 151574 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50653 /* 151576 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50654 /* 151576 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50655 /* 151579 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
50656 /* 151583 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50657 /* 151588 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50658 /* 151592 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50659 /* 151596 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50660 /* 151598 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50661 /* 151601 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50662 /* 151605 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50663 /* 151610 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50664 /* 151613 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50665 /* 151615 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50666 /* 151618 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50667 /* 151622 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50668 /* 151627 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50669 /* 151630 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50670 /* 151632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50671 /* 151635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50672 /* 151639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50673 /* 151644 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50674 /* 151651 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50675 /* 151656 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50676 /* 151661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50677 /* 151664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50678 /* 151666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50679 /* 151669 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50680 /* 151672 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50681 /* 151675 */ GIR_RootConstrainSelectedInstOperands,
50682 /* 151676 */ // GIR_Coverage, 3981,
50683 /* 151676 */ GIR_EraseRootFromParent_Done,
50684 /* 151677 */ // Label 2034: @151677
50685 /* 151677 */ GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(151816), // Rule ID 3989 //
50686 /* 151682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50687 /* 151685 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50688 /* 151688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50689 /* 151692 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50690 /* 151696 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50691 /* 151700 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50692 /* 151704 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50693 /* 151708 */ // MIs[1] Operand 1
50694 /* 151708 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
50695 /* 151713 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50696 /* 151715 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50697 /* 151715 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50698 /* 151718 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
50699 /* 151722 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50700 /* 151727 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50701 /* 151731 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50702 /* 151735 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50703 /* 151737 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50704 /* 151740 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50705 /* 151744 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50706 /* 151749 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50707 /* 151752 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50708 /* 151754 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50709 /* 151757 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50710 /* 151761 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50711 /* 151766 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50712 /* 151769 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50713 /* 151771 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50714 /* 151774 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50715 /* 151778 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50716 /* 151783 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
50717 /* 151790 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50718 /* 151795 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50719 /* 151800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50720 /* 151803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50721 /* 151805 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50722 /* 151808 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50723 /* 151811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50724 /* 151814 */ GIR_RootConstrainSelectedInstOperands,
50725 /* 151815 */ // GIR_Coverage, 3989,
50726 /* 151815 */ GIR_EraseRootFromParent_Done,
50727 /* 151816 */ // Label 2035: @151816
50728 /* 151816 */ GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(151955), // Rule ID 3997 //
50729 /* 151821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
50730 /* 151824 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50731 /* 151827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50732 /* 151831 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50733 /* 151835 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
50734 /* 151839 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
50735 /* 151843 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
50736 /* 151847 */ // MIs[1] Operand 1
50737 /* 151847 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
50738 /* 151852 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50739 /* 151854 */ // (zext:{ *:[i64] } (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] })) => (SELECT_I8:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }), (LI8:{ *:[i64] } 0:{ *:[i64] }), (LI8:{ *:[i64] } 1:{ *:[i64] }))
50740 /* 151854 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
50741 /* 151857 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
50742 /* 151861 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50743 /* 151866 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // s1
50744 /* 151870 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // s2
50745 /* 151874 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50746 /* 151876 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
50747 /* 151879 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::LI8),
50748 /* 151883 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50749 /* 151888 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
50750 /* 151891 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
50751 /* 151893 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
50752 /* 151896 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::LI8),
50753 /* 151900 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50754 /* 151905 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
50755 /* 151908 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
50756 /* 151910 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
50757 /* 151913 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50758 /* 151917 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50759 /* 151922 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
50760 /* 151929 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
50761 /* 151934 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
50762 /* 151939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50763 /* 151942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50764 /* 151944 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50765 /* 151947 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
50766 /* 151950 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
50767 /* 151953 */ GIR_RootConstrainSelectedInstOperands,
50768 /* 151954 */ // GIR_Coverage, 3997,
50769 /* 151954 */ GIR_EraseRootFromParent_Done,
50770 /* 151955 */ // Label 2036: @151955
50771 /* 151955 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(151977), // Rule ID 2989 //
50772 /* 151960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50773 /* 151963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50774 /* 151966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50775 /* 151970 */ // (zext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SETBC8:{ *:[i64] } ?:{ *:[i1] }:$in)
50776 /* 151970 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETBC8),
50777 /* 151975 */ GIR_RootConstrainSelectedInstOperands,
50778 /* 151976 */ // GIR_Coverage, 2989,
50779 /* 151976 */ GIR_Done,
50780 /* 151977 */ // Label 2037: @151977
50781 /* 151977 */ GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(152038), // Rule ID 3675 //
50782 /* 151982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
50783 /* 151985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50784 /* 151989 */ // (zext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SELECT_I8:{ *:[i64] } ?:{ *:[i1] }:$in, (LI8:{ *:[i64] } 1:{ *:[i64] }), (LI8:{ *:[i64] } 0:{ *:[i64] }))
50785 /* 151989 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
50786 /* 151992 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI8),
50787 /* 151996 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50788 /* 152001 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
50789 /* 152004 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50790 /* 152006 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
50791 /* 152009 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI8),
50792 /* 152013 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50793 /* 152018 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
50794 /* 152021 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50795 /* 152023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
50796 /* 152026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50797 /* 152028 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
50798 /* 152030 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50799 /* 152033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
50800 /* 152036 */ GIR_RootConstrainSelectedInstOperands,
50801 /* 152037 */ // GIR_Coverage, 3675,
50802 /* 152037 */ GIR_EraseRootFromParent_Done,
50803 /* 152038 */ // Label 2038: @152038
50804 /* 152038 */ GIM_Reject,
50805 /* 152039 */ // Label 1852: @152039
50806 /* 152039 */ GIM_Reject,
50807 /* 152040 */ // Label 27: @152040
50808 /* 152040 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 2046*/ GIMT_Encode4(152395),
50809 /* 152051 */ /*GILLT_s32*//*Label 2039*/ GIMT_Encode4(152079),
50810 /* 152055 */ /*GILLT_s64*//*Label 2040*/ GIMT_Encode4(152102),
50811 /* 152059 */ /*GILLT_s128*//*Label 2041*/ GIMT_Encode4(152125),
50812 /* 152063 */ /*GILLT_v2s64*//*Label 2042*/ GIMT_Encode4(152291),
50813 /* 152067 */ /*GILLT_v4s32*//*Label 2043*/ GIMT_Encode4(152317),
50814 /* 152071 */ /*GILLT_v8s16*//*Label 2044*/ GIMT_Encode4(152343),
50815 /* 152075 */ /*GILLT_v16s8*//*Label 2045*/ GIMT_Encode4(152369),
50816 /* 152079 */ // Label 2039: @152079
50817 /* 152079 */ GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(152101), // Rule ID 1257 //
50818 /* 152084 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
50819 /* 152087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
50820 /* 152090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
50821 /* 152094 */ // (shl:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (SLW:{ *:[i32] } ?:{ *:[i32] }:$rS, ?:{ *:[i32] }:$rB)
50822 /* 152094 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SLW),
50823 /* 152099 */ GIR_RootConstrainSelectedInstOperands,
50824 /* 152100 */ // GIR_Coverage, 1257,
50825 /* 152100 */ GIR_Done,
50826 /* 152101 */ // Label 2047: @152101
50827 /* 152101 */ GIM_Reject,
50828 /* 152102 */ // Label 2040: @152102
50829 /* 152102 */ GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(152124), // Rule ID 1538 //
50830 /* 152107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
50831 /* 152110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
50832 /* 152113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
50833 /* 152117 */ // (shl:{ *:[i64] } i64:{ *:[i64] }:$rS, i32:{ *:[i32] }:$rB) => (SLD:{ *:[i64] } ?:{ *:[i64] }:$rS, ?:{ *:[i32] }:$rB)
50834 /* 152117 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SLD),
50835 /* 152122 */ GIR_RootConstrainSelectedInstOperands,
50836 /* 152123 */ // GIR_Coverage, 1538,
50837 /* 152123 */ GIR_Done,
50838 /* 152124 */ // Label 2048: @152124
50839 /* 152124 */ GIM_Reject,
50840 /* 152125 */ // Label 2041: @152125
50841 /* 152125 */ GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(152290),
50842 /* 152130 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
50843 /* 152133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
50844 /* 152136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
50845 /* 152140 */ GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(152225), // Rule ID 3376 //
50846 /* 152145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1),
50847 /* 152148 */ // (shl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, v1i128:{ *:[v1i128] }:$VRB) => (VSLQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, (XXPERMDI:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), 2:{ *:[i32] }))
50848 /* 152148 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
50849 /* 152151 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50850 /* 152155 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50851 /* 152160 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // VRB
50852 /* 152164 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
50853 /* 152169 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
50854 /* 152172 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
50855 /* 152176 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50856 /* 152181 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // VRB
50857 /* 152185 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
50858 /* 152190 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
50859 /* 152193 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI),
50860 /* 152197 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50861 /* 152202 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
50862 /* 152205 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
50863 /* 152208 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
50864 /* 152211 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50865 /* 152213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLQ),
50866 /* 152216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
50867 /* 152218 */ GIR_RootToRootCopy, /*OpIdx*/1, // VRA
50868 /* 152220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50869 /* 152223 */ GIR_RootConstrainSelectedInstOperands,
50870 /* 152224 */ // GIR_Coverage, 3376,
50871 /* 152224 */ GIR_EraseRootFromParent_Done,
50872 /* 152225 */ // Label 2050: @152225
50873 /* 152225 */ GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(152289), // Rule ID 1396 //
50874 /* 152230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
50875 /* 152233 */ // (shl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VSL:{ *:[v1i128] } (VSLO:{ *:[v16i8] } ?:{ *:[v1i128] }:$vA, ?:{ *:[v1i128] }:$vB), (VSPLTB:{ *:[v16i8] } 15:{ *:[i32] }, ?:{ *:[v1i128] }:$vB))
50876 /* 152233 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
50877 /* 152236 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::VSPLTB),
50878 /* 152240 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50879 /* 152245 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/15,
50880 /* 152248 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vB
50881 /* 152252 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50882 /* 152254 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
50883 /* 152257 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::VSLO),
50884 /* 152261 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50885 /* 152266 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vA
50886 /* 152270 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vB
50887 /* 152274 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50888 /* 152276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSL),
50889 /* 152279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
50890 /* 152281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50891 /* 152284 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
50892 /* 152287 */ GIR_RootConstrainSelectedInstOperands,
50893 /* 152288 */ // GIR_Coverage, 1396,
50894 /* 152288 */ GIR_EraseRootFromParent_Done,
50895 /* 152289 */ // Label 2051: @152289
50896 /* 152289 */ GIM_Reject,
50897 /* 152290 */ // Label 2049: @152290
50898 /* 152290 */ GIM_Reject,
50899 /* 152291 */ // Label 2042: @152291
50900 /* 152291 */ GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(152316), // Rule ID 1444 //
50901 /* 152296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
50902 /* 152299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
50903 /* 152302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
50904 /* 152305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
50905 /* 152309 */ // (shl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VSLD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB)
50906 /* 152309 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSLD),
50907 /* 152314 */ GIR_RootConstrainSelectedInstOperands,
50908 /* 152315 */ // GIR_Coverage, 1444,
50909 /* 152315 */ GIR_Done,
50910 /* 152316 */ // Label 2052: @152316
50911 /* 152316 */ GIM_Reject,
50912 /* 152317 */ // Label 2043: @152317
50913 /* 152317 */ GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(152342), // Rule ID 1395 //
50914 /* 152322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
50915 /* 152325 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
50916 /* 152328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
50917 /* 152331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
50918 /* 152335 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSLW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
50919 /* 152335 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSLW),
50920 /* 152340 */ GIR_RootConstrainSelectedInstOperands,
50921 /* 152341 */ // GIR_Coverage, 1395,
50922 /* 152341 */ GIR_Done,
50923 /* 152342 */ // Label 2053: @152342
50924 /* 152342 */ GIM_Reject,
50925 /* 152343 */ // Label 2044: @152343
50926 /* 152343 */ GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(152368), // Rule ID 1394 //
50927 /* 152348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
50928 /* 152351 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
50929 /* 152354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
50930 /* 152357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
50931 /* 152361 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSLH:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB)
50932 /* 152361 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSLH),
50933 /* 152366 */ GIR_RootConstrainSelectedInstOperands,
50934 /* 152367 */ // GIR_Coverage, 1394,
50935 /* 152367 */ GIR_Done,
50936 /* 152368 */ // Label 2054: @152368
50937 /* 152368 */ GIM_Reject,
50938 /* 152369 */ // Label 2045: @152369
50939 /* 152369 */ GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(152394), // Rule ID 1393 //
50940 /* 152374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
50941 /* 152377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
50942 /* 152380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
50943 /* 152383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
50944 /* 152387 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSLB:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB)
50945 /* 152387 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSLB),
50946 /* 152392 */ GIR_RootConstrainSelectedInstOperands,
50947 /* 152393 */ // GIR_Coverage, 1393,
50948 /* 152393 */ GIR_Done,
50949 /* 152394 */ // Label 2055: @152394
50950 /* 152394 */ GIM_Reject,
50951 /* 152395 */ // Label 2046: @152395
50952 /* 152395 */ GIM_Reject,
50953 /* 152396 */ // Label 28: @152396
50954 /* 152396 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 2063*/ GIMT_Encode4(152817),
50955 /* 152407 */ /*GILLT_s32*//*Label 2056*/ GIMT_Encode4(152435),
50956 /* 152411 */ /*GILLT_s64*//*Label 2057*/ GIMT_Encode4(152524),
50957 /* 152415 */ /*GILLT_s128*//*Label 2058*/ GIMT_Encode4(152547),
50958 /* 152419 */ /*GILLT_v2s64*//*Label 2059*/ GIMT_Encode4(152713),
50959 /* 152423 */ /*GILLT_v4s32*//*Label 2060*/ GIMT_Encode4(152739),
50960 /* 152427 */ /*GILLT_v8s16*//*Label 2061*/ GIMT_Encode4(152765),
50961 /* 152431 */ /*GILLT_v16s8*//*Label 2062*/ GIMT_Encode4(152791),
50962 /* 152435 */ // Label 2056: @152435
50963 /* 152435 */ GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(152523),
50964 /* 152440 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
50965 /* 152443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
50966 /* 152446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
50967 /* 152450 */ GIM_Try, /*On fail goto*//*Label 2065*/ GIMT_Encode4(152510), // Rule ID 3356 //
50968 /* 152455 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
50969 /* 152458 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50970 /* 152462 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
50971 /* 152466 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
50972 /* 152470 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
50973 /* 152474 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50974 /* 152476 */ // (srl:{ *:[i32] } (bswap:{ *:[i32] } i32:{ *:[i32] }:$RS), 16:{ *:[i32] }) => (RLDICL_32:{ *:[i32] } (BRH:{ *:[i32] } ?:{ *:[i32] }:$RS), 0:{ *:[i32] }, 48:{ *:[i32] })
50975 /* 152476 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50976 /* 152479 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::BRH),
50977 /* 152483 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50978 /* 152488 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // RS
50979 /* 152492 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50980 /* 152494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL_32),
50981 /* 152497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
50982 /* 152499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50983 /* 152502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50984 /* 152505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/48,
50985 /* 152508 */ GIR_RootConstrainSelectedInstOperands,
50986 /* 152509 */ // GIR_Coverage, 3356,
50987 /* 152509 */ GIR_EraseRootFromParent_Done,
50988 /* 152510 */ // Label 2065: @152510
50989 /* 152510 */ GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(152522), // Rule ID 1256 //
50990 /* 152515 */ // (srl:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (SRW:{ *:[i32] } ?:{ *:[i32] }:$rS, ?:{ *:[i32] }:$rB)
50991 /* 152515 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SRW),
50992 /* 152520 */ GIR_RootConstrainSelectedInstOperands,
50993 /* 152521 */ // GIR_Coverage, 1256,
50994 /* 152521 */ GIR_Done,
50995 /* 152522 */ // Label 2066: @152522
50996 /* 152522 */ GIM_Reject,
50997 /* 152523 */ // Label 2064: @152523
50998 /* 152523 */ GIM_Reject,
50999 /* 152524 */ // Label 2057: @152524
51000 /* 152524 */ GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(152546), // Rule ID 1537 //
51001 /* 152529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
51002 /* 152532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51003 /* 152535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
51004 /* 152539 */ // (srl:{ *:[i64] } i64:{ *:[i64] }:$rS, i32:{ *:[i32] }:$rB) => (SRD:{ *:[i64] } ?:{ *:[i64] }:$rS, ?:{ *:[i32] }:$rB)
51005 /* 152539 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SRD),
51006 /* 152544 */ GIR_RootConstrainSelectedInstOperands,
51007 /* 152545 */ // GIR_Coverage, 1537,
51008 /* 152545 */ GIR_Done,
51009 /* 152546 */ // Label 2067: @152546
51010 /* 152546 */ GIM_Reject,
51011 /* 152547 */ // Label 2058: @152547
51012 /* 152547 */ GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(152712),
51013 /* 152552 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
51014 /* 152555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
51015 /* 152558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51016 /* 152562 */ GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(152647), // Rule ID 3378 //
51017 /* 152567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1),
51018 /* 152570 */ // (srl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, v1i128:{ *:[v1i128] }:$VRB) => (VSRQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, (XXPERMDI:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), 2:{ *:[i32] }))
51019 /* 152570 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
51020 /* 152573 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51021 /* 152577 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51022 /* 152582 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // VRB
51023 /* 152586 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
51024 /* 152591 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
51025 /* 152594 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51026 /* 152598 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51027 /* 152603 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // VRB
51028 /* 152607 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
51029 /* 152612 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
51030 /* 152615 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI),
51031 /* 152619 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51032 /* 152624 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
51033 /* 152627 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
51034 /* 152630 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
51035 /* 152633 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51036 /* 152635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRQ),
51037 /* 152638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
51038 /* 152640 */ GIR_RootToRootCopy, /*OpIdx*/1, // VRA
51039 /* 152642 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51040 /* 152645 */ GIR_RootConstrainSelectedInstOperands,
51041 /* 152646 */ // GIR_Coverage, 3378,
51042 /* 152646 */ GIR_EraseRootFromParent_Done,
51043 /* 152647 */ // Label 2069: @152647
51044 /* 152647 */ GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(152711), // Rule ID 1404 //
51045 /* 152652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51046 /* 152655 */ // (srl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VSR:{ *:[v1i128] } (VSRO:{ *:[v16i8] } ?:{ *:[v1i128] }:$vA, ?:{ *:[v1i128] }:$vB), (VSPLTB:{ *:[v16i8] } 15:{ *:[i32] }, ?:{ *:[v1i128] }:$vB))
51047 /* 152655 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
51048 /* 152658 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::VSPLTB),
51049 /* 152662 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51050 /* 152667 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/15,
51051 /* 152670 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vB
51052 /* 152674 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51053 /* 152676 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
51054 /* 152679 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::VSRO),
51055 /* 152683 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51056 /* 152688 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vA
51057 /* 152692 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vB
51058 /* 152696 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51059 /* 152698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSR),
51060 /* 152701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
51061 /* 152703 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51062 /* 152706 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
51063 /* 152709 */ GIR_RootConstrainSelectedInstOperands,
51064 /* 152710 */ // GIR_Coverage, 1404,
51065 /* 152710 */ GIR_EraseRootFromParent_Done,
51066 /* 152711 */ // Label 2070: @152711
51067 /* 152711 */ GIM_Reject,
51068 /* 152712 */ // Label 2068: @152712
51069 /* 152712 */ GIM_Reject,
51070 /* 152713 */ // Label 2059: @152713
51071 /* 152713 */ GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(152738), // Rule ID 1446 //
51072 /* 152718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
51073 /* 152721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
51074 /* 152724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51075 /* 152727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51076 /* 152731 */ // (srl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VSRD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB)
51077 /* 152731 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRD),
51078 /* 152736 */ GIR_RootConstrainSelectedInstOperands,
51079 /* 152737 */ // GIR_Coverage, 1446,
51080 /* 152737 */ GIR_Done,
51081 /* 152738 */ // Label 2071: @152738
51082 /* 152738 */ GIM_Reject,
51083 /* 152739 */ // Label 2060: @152739
51084 /* 152739 */ GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(152764), // Rule ID 1403 //
51085 /* 152744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51086 /* 152747 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
51087 /* 152750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51088 /* 152753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51089 /* 152757 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSRW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
51090 /* 152757 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRW),
51091 /* 152762 */ GIR_RootConstrainSelectedInstOperands,
51092 /* 152763 */ // GIR_Coverage, 1403,
51093 /* 152763 */ GIR_Done,
51094 /* 152764 */ // Label 2072: @152764
51095 /* 152764 */ GIM_Reject,
51096 /* 152765 */ // Label 2061: @152765
51097 /* 152765 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(152790), // Rule ID 1402 //
51098 /* 152770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51099 /* 152773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
51100 /* 152776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51101 /* 152779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51102 /* 152783 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSRH:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB)
51103 /* 152783 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRH),
51104 /* 152788 */ GIR_RootConstrainSelectedInstOperands,
51105 /* 152789 */ // GIR_Coverage, 1402,
51106 /* 152789 */ GIR_Done,
51107 /* 152790 */ // Label 2073: @152790
51108 /* 152790 */ GIM_Reject,
51109 /* 152791 */ // Label 2062: @152791
51110 /* 152791 */ GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(152816), // Rule ID 1401 //
51111 /* 152796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51112 /* 152799 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
51113 /* 152802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
51114 /* 152805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51115 /* 152809 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSRB:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB)
51116 /* 152809 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRB),
51117 /* 152814 */ GIR_RootConstrainSelectedInstOperands,
51118 /* 152815 */ // GIR_Coverage, 1401,
51119 /* 152815 */ GIR_Done,
51120 /* 152816 */ // Label 2074: @152816
51121 /* 152816 */ GIM_Reject,
51122 /* 152817 */ // Label 2063: @152817
51123 /* 152817 */ GIM_Reject,
51124 /* 152818 */ // Label 29: @152818
51125 /* 152818 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 2082*/ GIMT_Encode4(153187),
51126 /* 152829 */ /*GILLT_s32*//*Label 2075*/ GIMT_Encode4(152857),
51127 /* 152833 */ /*GILLT_s64*//*Label 2076*/ GIMT_Encode4(152922),
51128 /* 152837 */ /*GILLT_s128*//*Label 2077*/ GIMT_Encode4(152987),
51129 /* 152841 */ /*GILLT_v2s64*//*Label 2078*/ GIMT_Encode4(153083),
51130 /* 152845 */ /*GILLT_v4s32*//*Label 2079*/ GIMT_Encode4(153109),
51131 /* 152849 */ /*GILLT_v8s16*//*Label 2080*/ GIMT_Encode4(153135),
51132 /* 152853 */ /*GILLT_v16s8*//*Label 2081*/ GIMT_Encode4(153161),
51133 /* 152857 */ // Label 2075: @152857
51134 /* 152857 */ GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(152921),
51135 /* 152862 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
51136 /* 152865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51137 /* 152868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
51138 /* 152872 */ GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(152902), // Rule ID 132 //
51139 /* 152877 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
51140 /* 152881 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51141 /* 152885 */ // MIs[1] Operand 1
51142 /* 152885 */ // No operand predicates
51143 /* 152885 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51144 /* 152887 */ // (sra:{ *:[i32] } i32:{ *:[i32] }:$RST, (imm:{ *:[i32] }):$RB) => (SRAWI:{ *:[i32] }:{ *:[i32] } i32:{ *:[i32] }:$RST, (imm:{ *:[i32] }):$RB)
51145 /* 152887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SRAWI),
51146 /* 152890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
51147 /* 152892 */ GIR_RootToRootCopy, /*OpIdx*/1, // RST
51148 /* 152894 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // RB
51149 /* 152897 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0,
51150 /* 152900 */ GIR_RootConstrainSelectedInstOperands,
51151 /* 152901 */ // GIR_Coverage, 132,
51152 /* 152901 */ GIR_EraseRootFromParent_Done,
51153 /* 152902 */ // Label 2084: @152902
51154 /* 152902 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(152920), // Rule ID 1255 //
51155 /* 152907 */ // (sra:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (SRAW:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$rS, ?:{ *:[i32] }:$rB)
51156 /* 152907 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SRAW),
51157 /* 152912 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(PPC::CARRY), GIMT_Encode2(RegState::Dead),
51158 /* 152918 */ GIR_RootConstrainSelectedInstOperands,
51159 /* 152919 */ // GIR_Coverage, 1255,
51160 /* 152919 */ GIR_Done,
51161 /* 152920 */ // Label 2085: @152920
51162 /* 152920 */ GIM_Reject,
51163 /* 152921 */ // Label 2083: @152921
51164 /* 152921 */ GIM_Reject,
51165 /* 152922 */ // Label 2076: @152922
51166 /* 152922 */ GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(152986),
51167 /* 152927 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
51168 /* 152930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51169 /* 152933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
51170 /* 152937 */ GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(152967), // Rule ID 685 //
51171 /* 152942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
51172 /* 152946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51173 /* 152950 */ // MIs[1] Operand 1
51174 /* 152950 */ // No operand predicates
51175 /* 152950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51176 /* 152952 */ // (sra:{ *:[i64] } i64:{ *:[i64] }:$RS, (imm:{ *:[i32] }):$SH) => (SRADI:{ *:[i64] }:{ *:[i32] } i64:{ *:[i64] }:$RS, (imm:{ *:[i32] }):$SH)
51177 /* 152952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SRADI),
51178 /* 152955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
51179 /* 152957 */ GIR_RootToRootCopy, /*OpIdx*/1, // RS
51180 /* 152959 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SH
51181 /* 152962 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0,
51182 /* 152965 */ GIR_RootConstrainSelectedInstOperands,
51183 /* 152966 */ // GIR_Coverage, 685,
51184 /* 152966 */ GIR_EraseRootFromParent_Done,
51185 /* 152967 */ // Label 2087: @152967
51186 /* 152967 */ GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(152985), // Rule ID 1536 //
51187 /* 152972 */ // (sra:{ *:[i64] } i64:{ *:[i64] }:$rS, i32:{ *:[i32] }:$rB) => (SRAD:{ *:[i64] }:{ *:[i32] } ?:{ *:[i64] }:$rS, ?:{ *:[i32] }:$rB)
51188 /* 152972 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SRAD),
51189 /* 152977 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(PPC::CARRY), GIMT_Encode2(RegState::Dead),
51190 /* 152983 */ GIR_RootConstrainSelectedInstOperands,
51191 /* 152984 */ // GIR_Coverage, 1536,
51192 /* 152984 */ GIR_Done,
51193 /* 152985 */ // Label 2088: @152985
51194 /* 152985 */ GIM_Reject,
51195 /* 152986 */ // Label 2086: @152986
51196 /* 152986 */ GIM_Reject,
51197 /* 152987 */ // Label 2077: @152987
51198 /* 152987 */ GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(153082), // Rule ID 3380 //
51199 /* 152992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1),
51200 /* 152995 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
51201 /* 152998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
51202 /* 153001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51203 /* 153005 */ // (sra:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, v1i128:{ *:[v1i128] }:$VRB) => (VSRAQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, (XXPERMDI:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), 2:{ *:[i32] }))
51204 /* 153005 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
51205 /* 153008 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51206 /* 153012 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51207 /* 153017 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // VRB
51208 /* 153021 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
51209 /* 153026 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
51210 /* 153029 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51211 /* 153033 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51212 /* 153038 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // VRB
51213 /* 153042 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
51214 /* 153047 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
51215 /* 153050 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI),
51216 /* 153054 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51217 /* 153059 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
51218 /* 153062 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
51219 /* 153065 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
51220 /* 153068 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51221 /* 153070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAQ),
51222 /* 153073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
51223 /* 153075 */ GIR_RootToRootCopy, /*OpIdx*/1, // VRA
51224 /* 153077 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51225 /* 153080 */ GIR_RootConstrainSelectedInstOperands,
51226 /* 153081 */ // GIR_Coverage, 3380,
51227 /* 153081 */ GIR_EraseRootFromParent_Done,
51228 /* 153082 */ // Label 2089: @153082
51229 /* 153082 */ GIM_Reject,
51230 /* 153083 */ // Label 2078: @153083
51231 /* 153083 */ GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(153108), // Rule ID 1448 //
51232 /* 153088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
51233 /* 153091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
51234 /* 153094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51235 /* 153097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51236 /* 153101 */ // (sra:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VSRAD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB)
51237 /* 153101 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRAD),
51238 /* 153106 */ GIR_RootConstrainSelectedInstOperands,
51239 /* 153107 */ // GIR_Coverage, 1448,
51240 /* 153107 */ GIR_Done,
51241 /* 153108 */ // Label 2090: @153108
51242 /* 153108 */ GIM_Reject,
51243 /* 153109 */ // Label 2079: @153109
51244 /* 153109 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(153134), // Rule ID 1411 //
51245 /* 153114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51246 /* 153117 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
51247 /* 153120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51248 /* 153123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51249 /* 153127 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSRAW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
51250 /* 153127 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRAW),
51251 /* 153132 */ GIR_RootConstrainSelectedInstOperands,
51252 /* 153133 */ // GIR_Coverage, 1411,
51253 /* 153133 */ GIR_Done,
51254 /* 153134 */ // Label 2091: @153134
51255 /* 153134 */ GIM_Reject,
51256 /* 153135 */ // Label 2080: @153135
51257 /* 153135 */ GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(153160), // Rule ID 1410 //
51258 /* 153140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51259 /* 153143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
51260 /* 153146 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51261 /* 153149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51262 /* 153153 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSRAH:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB)
51263 /* 153153 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRAH),
51264 /* 153158 */ GIR_RootConstrainSelectedInstOperands,
51265 /* 153159 */ // GIR_Coverage, 1410,
51266 /* 153159 */ GIR_Done,
51267 /* 153160 */ // Label 2092: @153160
51268 /* 153160 */ GIM_Reject,
51269 /* 153161 */ // Label 2081: @153161
51270 /* 153161 */ GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(153186), // Rule ID 1409 //
51271 /* 153166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51272 /* 153169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
51273 /* 153172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
51274 /* 153175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51275 /* 153179 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSRAB:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB)
51276 /* 153179 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRAB),
51277 /* 153184 */ GIR_RootConstrainSelectedInstOperands,
51278 /* 153185 */ // GIR_Coverage, 1409,
51279 /* 153185 */ GIR_Done,
51280 /* 153186 */ // Label 2093: @153186
51281 /* 153186 */ GIM_Reject,
51282 /* 153187 */ // Label 2082: @153187
51283 /* 153187 */ GIM_Reject,
51284 /* 153188 */ // Label 30: @153188
51285 /* 153188 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 2101*/ GIMT_Encode4(153495),
51286 /* 153199 */ /*GILLT_s32*//*Label 2094*/ GIMT_Encode4(153227),
51287 /* 153203 */ /*GILLT_s64*//*Label 2095*/ GIMT_Encode4(153299),
51288 /* 153207 */ /*GILLT_s128*//*Label 2096*/ GIMT_Encode4(153365),
51289 /* 153211 */ /*GILLT_v2s64*//*Label 2097*/ GIMT_Encode4(153391),
51290 /* 153215 */ /*GILLT_v4s32*//*Label 2098*/ GIMT_Encode4(153417),
51291 /* 153219 */ /*GILLT_v8s16*//*Label 2099*/ GIMT_Encode4(153443),
51292 /* 153223 */ /*GILLT_v16s8*//*Label 2100*/ GIMT_Encode4(153469),
51293 /* 153227 */ // Label 2094: @153227
51294 /* 153227 */ GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(153298),
51295 /* 153232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
51296 /* 153235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51297 /* 153238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
51298 /* 153242 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(153275), // Rule ID 1221 //
51299 /* 153247 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
51300 /* 153251 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51301 /* 153255 */ // MIs[1] Operand 1
51302 /* 153255 */ // No operand predicates
51303 /* 153255 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51304 /* 153257 */ // (rotl:{ *:[i32] } i32:{ *:[i32] }:$in, (imm:{ *:[i32] }):$imm) => (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$in, (imm:{ *:[i32] }):$imm, 0:{ *:[i32] }, 31:{ *:[i32] })
51305 /* 153257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
51306 /* 153260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
51307 /* 153262 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
51308 /* 153264 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51309 /* 153267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
51310 /* 153270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
51311 /* 153273 */ GIR_RootConstrainSelectedInstOperands,
51312 /* 153274 */ // GIR_Coverage, 1221,
51313 /* 153274 */ GIR_EraseRootFromParent_Done,
51314 /* 153275 */ // Label 2103: @153275
51315 /* 153275 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(153297), // Rule ID 1220 //
51316 /* 153280 */ // (rotl:{ *:[i32] } i32:{ *:[i32] }:$in, i32:{ *:[i32] }:$sh) => (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$in, ?:{ *:[i32] }:$sh, 0:{ *:[i32] }, 31:{ *:[i32] })
51317 /* 153280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM),
51318 /* 153283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
51319 /* 153285 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
51320 /* 153287 */ GIR_RootToRootCopy, /*OpIdx*/2, // sh
51321 /* 153289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
51322 /* 153292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
51323 /* 153295 */ GIR_RootConstrainSelectedInstOperands,
51324 /* 153296 */ // GIR_Coverage, 1220,
51325 /* 153296 */ GIR_EraseRootFromParent_Done,
51326 /* 153297 */ // Label 2104: @153297
51327 /* 153297 */ GIM_Reject,
51328 /* 153298 */ // Label 2102: @153298
51329 /* 153298 */ GIM_Reject,
51330 /* 153299 */ // Label 2095: @153299
51331 /* 153299 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(153364),
51332 /* 153304 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
51333 /* 153307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51334 /* 153310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
51335 /* 153314 */ GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(153344), // Rule ID 1543 //
51336 /* 153319 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
51337 /* 153323 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51338 /* 153327 */ // MIs[1] Operand 1
51339 /* 153327 */ // No operand predicates
51340 /* 153327 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51341 /* 153329 */ // (rotl:{ *:[i64] } i64:{ *:[i64] }:$in, (imm:{ *:[i32] }):$imm) => (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$in, (imm:{ *:[i32] }):$imm, 0:{ *:[i32] })
51342 /* 153329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
51343 /* 153332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
51344 /* 153334 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
51345 /* 153336 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51346 /* 153339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
51347 /* 153342 */ GIR_RootConstrainSelectedInstOperands,
51348 /* 153343 */ // GIR_Coverage, 1543,
51349 /* 153343 */ GIR_EraseRootFromParent_Done,
51350 /* 153344 */ // Label 2106: @153344
51351 /* 153344 */ GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(153363), // Rule ID 1542 //
51352 /* 153349 */ // (rotl:{ *:[i64] } i64:{ *:[i64] }:$in, i32:{ *:[i32] }:$sh) => (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$in, ?:{ *:[i32] }:$sh, 0:{ *:[i32] })
51353 /* 153349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL),
51354 /* 153352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
51355 /* 153354 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
51356 /* 153356 */ GIR_RootToRootCopy, /*OpIdx*/2, // sh
51357 /* 153358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
51358 /* 153361 */ GIR_RootConstrainSelectedInstOperands,
51359 /* 153362 */ // GIR_Coverage, 1542,
51360 /* 153362 */ GIR_EraseRootFromParent_Done,
51361 /* 153363 */ // Label 2107: @153363
51362 /* 153363 */ GIM_Reject,
51363 /* 153364 */ // Label 2105: @153364
51364 /* 153364 */ GIM_Reject,
51365 /* 153365 */ // Label 2096: @153365
51366 /* 153365 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(153390), // Rule ID 3362 //
51367 /* 153370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
51368 /* 153373 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
51369 /* 153376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
51370 /* 153379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51371 /* 153383 */ // (rotl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VRLQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB)
51372 /* 153383 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLQ),
51373 /* 153388 */ GIR_RootConstrainSelectedInstOperands,
51374 /* 153389 */ // GIR_Coverage, 3362,
51375 /* 153389 */ GIR_Done,
51376 /* 153390 */ // Label 2108: @153390
51377 /* 153390 */ GIM_Reject,
51378 /* 153391 */ // Label 2097: @153391
51379 /* 153391 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(153416), // Rule ID 1443 //
51380 /* 153396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
51381 /* 153399 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
51382 /* 153402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51383 /* 153405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51384 /* 153409 */ // (rotl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VRLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB)
51385 /* 153409 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLD),
51386 /* 153414 */ GIR_RootConstrainSelectedInstOperands,
51387 /* 153415 */ // GIR_Coverage, 1443,
51388 /* 153415 */ GIR_Done,
51389 /* 153416 */ // Label 2109: @153416
51390 /* 153416 */ GIM_Reject,
51391 /* 153417 */ // Label 2098: @153417
51392 /* 153417 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(153442), // Rule ID 1294 //
51393 /* 153422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51394 /* 153425 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
51395 /* 153428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51396 /* 153431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51397 /* 153435 */ // (rotl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VRLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB)
51398 /* 153435 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLW),
51399 /* 153440 */ GIR_RootConstrainSelectedInstOperands,
51400 /* 153441 */ // GIR_Coverage, 1294,
51401 /* 153441 */ GIR_Done,
51402 /* 153442 */ // Label 2110: @153442
51403 /* 153442 */ GIM_Reject,
51404 /* 153443 */ // Label 2099: @153443
51405 /* 153443 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(153468), // Rule ID 1293 //
51406 /* 153448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51407 /* 153451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
51408 /* 153454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51409 /* 153457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51410 /* 153461 */ // (rotl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VRLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB)
51411 /* 153461 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLH),
51412 /* 153466 */ GIR_RootConstrainSelectedInstOperands,
51413 /* 153467 */ // GIR_Coverage, 1293,
51414 /* 153467 */ GIR_Done,
51415 /* 153468 */ // Label 2111: @153468
51416 /* 153468 */ GIM_Reject,
51417 /* 153469 */ // Label 2100: @153469
51418 /* 153469 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(153494), // Rule ID 1292 //
51419 /* 153474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
51420 /* 153477 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
51421 /* 153480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
51422 /* 153483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
51423 /* 153487 */ // (rotl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB)
51424 /* 153487 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLB),
51425 /* 153492 */ GIR_RootConstrainSelectedInstOperands,
51426 /* 153493 */ // GIR_Coverage, 1292,
51427 /* 153493 */ GIR_Done,
51428 /* 153494 */ // Label 2112: @153494
51429 /* 153494 */ GIM_Reject,
51430 /* 153495 */ // Label 2101: @153495
51431 /* 153495 */ GIM_Reject,
51432 /* 153496 */ // Label 31: @153496
51433 /* 153496 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(157497),
51434 /* 153501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
51435 /* 153504 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2116*/ GIMT_Encode4(154073),
51436 /* 153515 */ /*GILLT_s32*//*Label 2114*/ GIMT_Encode4(153523),
51437 /* 153519 */ /*GILLT_s64*//*Label 2115*/ GIMT_Encode4(153798),
51438 /* 153523 */ // Label 2114: @153523
51439 /* 153523 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(153797),
51440 /* 153528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51441 /* 153531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
51442 /* 153535 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(153622), // Rule ID 3034 //
51443 /* 153540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
51444 /* 153543 */ // MIs[0] Operand 1
51445 /* 153543 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
51446 /* 153548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51447 /* 153552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51448 /* 153556 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51449 /* 153560 */ // MIs[1] Operand 1
51450 /* 153560 */ // No operand predicates
51451 /* 153560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51452 /* 153562 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }))
51453 /* 153562 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51454 /* 153565 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51455 /* 153569 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51456 /* 153574 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51457 /* 153578 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51458 /* 153581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51459 /* 153583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51460 /* 153586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51461 /* 153590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51462 /* 153595 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
51463 /* 153602 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51464 /* 153607 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51465 /* 153612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51466 /* 153615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51467 /* 153617 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51468 /* 153620 */ GIR_RootConstrainSelectedInstOperands,
51469 /* 153621 */ // GIR_Coverage, 3034,
51470 /* 153621 */ GIR_EraseRootFromParent_Done,
51471 /* 153622 */ // Label 2118: @153622
51472 /* 153622 */ GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(153709), // Rule ID 3050 //
51473 /* 153627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
51474 /* 153630 */ // MIs[0] Operand 1
51475 /* 153630 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
51476 /* 153635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51477 /* 153639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51478 /* 153643 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51479 /* 153647 */ // MIs[1] Operand 1
51480 /* 153647 */ // No operand predicates
51481 /* 153647 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51482 /* 153649 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }))
51483 /* 153649 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51484 /* 153652 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51485 /* 153656 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51486 /* 153661 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51487 /* 153665 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51488 /* 153668 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51489 /* 153670 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51490 /* 153673 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51491 /* 153677 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51492 /* 153682 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
51493 /* 153689 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51494 /* 153694 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51495 /* 153699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51496 /* 153702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51497 /* 153704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51498 /* 153707 */ GIR_RootConstrainSelectedInstOperands,
51499 /* 153708 */ // GIR_Coverage, 3050,
51500 /* 153708 */ GIR_EraseRootFromParent_Done,
51501 /* 153709 */ // Label 2119: @153709
51502 /* 153709 */ GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(153796), // Rule ID 3058 //
51503 /* 153714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
51504 /* 153717 */ // MIs[0] Operand 1
51505 /* 153717 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
51506 /* 153722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51507 /* 153726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51508 /* 153730 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51509 /* 153734 */ // MIs[1] Operand 1
51510 /* 153734 */ // No operand predicates
51511 /* 153734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51512 /* 153736 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }))
51513 /* 153736 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51514 /* 153739 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51515 /* 153743 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51516 /* 153748 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51517 /* 153752 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51518 /* 153755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51519 /* 153757 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51520 /* 153760 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51521 /* 153764 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51522 /* 153769 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
51523 /* 153776 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51524 /* 153781 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51525 /* 153786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51526 /* 153789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51527 /* 153791 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51528 /* 153794 */ GIR_RootConstrainSelectedInstOperands,
51529 /* 153795 */ // GIR_Coverage, 3058,
51530 /* 153795 */ GIR_EraseRootFromParent_Done,
51531 /* 153796 */ // Label 2120: @153796
51532 /* 153796 */ GIM_Reject,
51533 /* 153797 */ // Label 2117: @153797
51534 /* 153797 */ GIM_Reject,
51535 /* 153798 */ // Label 2115: @153798
51536 /* 153798 */ GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(154072),
51537 /* 153803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
51538 /* 153806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
51539 /* 153810 */ GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(153897), // Rule ID 3130 //
51540 /* 153815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
51541 /* 153818 */ // MIs[0] Operand 1
51542 /* 153818 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
51543 /* 153823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51544 /* 153827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51545 /* 153831 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51546 /* 153835 */ // MIs[1] Operand 1
51547 /* 153835 */ // No operand predicates
51548 /* 153835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51549 /* 153837 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }))
51550 /* 153837 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51551 /* 153840 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51552 /* 153844 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51553 /* 153849 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51554 /* 153853 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51555 /* 153856 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51556 /* 153858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51557 /* 153861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51558 /* 153865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51559 /* 153870 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
51560 /* 153877 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51561 /* 153882 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51562 /* 153887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51563 /* 153890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51564 /* 153892 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51565 /* 153895 */ GIR_RootConstrainSelectedInstOperands,
51566 /* 153896 */ // GIR_Coverage, 3130,
51567 /* 153896 */ GIR_EraseRootFromParent_Done,
51568 /* 153897 */ // Label 2122: @153897
51569 /* 153897 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(153984), // Rule ID 3146 //
51570 /* 153902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
51571 /* 153905 */ // MIs[0] Operand 1
51572 /* 153905 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
51573 /* 153910 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51574 /* 153914 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51575 /* 153918 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51576 /* 153922 */ // MIs[1] Operand 1
51577 /* 153922 */ // No operand predicates
51578 /* 153922 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51579 /* 153924 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }))
51580 /* 153924 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51581 /* 153927 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51582 /* 153931 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51583 /* 153936 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51584 /* 153940 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51585 /* 153943 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51586 /* 153945 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51587 /* 153948 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51588 /* 153952 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51589 /* 153957 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
51590 /* 153964 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51591 /* 153969 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51592 /* 153974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51593 /* 153977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51594 /* 153979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51595 /* 153982 */ GIR_RootConstrainSelectedInstOperands,
51596 /* 153983 */ // GIR_Coverage, 3146,
51597 /* 153983 */ GIR_EraseRootFromParent_Done,
51598 /* 153984 */ // Label 2123: @153984
51599 /* 153984 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(154071), // Rule ID 3154 //
51600 /* 153989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
51601 /* 153992 */ // MIs[0] Operand 1
51602 /* 153992 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
51603 /* 153997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51604 /* 154001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51605 /* 154005 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51606 /* 154009 */ // MIs[1] Operand 1
51607 /* 154009 */ // No operand predicates
51608 /* 154009 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51609 /* 154011 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }))
51610 /* 154011 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51611 /* 154014 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51612 /* 154018 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51613 /* 154023 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51614 /* 154027 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51615 /* 154030 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51616 /* 154032 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51617 /* 154035 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51618 /* 154039 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51619 /* 154044 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
51620 /* 154051 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51621 /* 154056 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51622 /* 154061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51623 /* 154064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51624 /* 154066 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51625 /* 154069 */ GIR_RootConstrainSelectedInstOperands,
51626 /* 154070 */ // GIR_Coverage, 3154,
51627 /* 154070 */ GIR_EraseRootFromParent_Done,
51628 /* 154071 */ // Label 2124: @154071
51629 /* 154071 */ GIM_Reject,
51630 /* 154072 */ // Label 2121: @154072
51631 /* 154072 */ GIM_Reject,
51632 /* 154073 */ // Label 2116: @154073
51633 /* 154073 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2127*/ GIMT_Encode4(154528),
51634 /* 154084 */ /*GILLT_s32*//*Label 2125*/ GIMT_Encode4(154092),
51635 /* 154088 */ /*GILLT_s64*//*Label 2126*/ GIMT_Encode4(154310),
51636 /* 154092 */ // Label 2125: @154092
51637 /* 154092 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(154309),
51638 /* 154097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51639 /* 154100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
51640 /* 154104 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(154172), // Rule ID 3794 //
51641 /* 154109 */ // MIs[0] Operand 1
51642 /* 154109 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
51643 /* 154114 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51644 /* 154118 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51645 /* 154122 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51646 /* 154126 */ // MIs[1] Operand 1
51647 /* 154126 */ // No operand predicates
51648 /* 154126 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51649 /* 154128 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] })
51650 /* 154128 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
51651 /* 154131 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51652 /* 154135 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51653 /* 154140 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
51654 /* 154144 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
51655 /* 154147 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51656 /* 154149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51657 /* 154152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51658 /* 154154 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
51659 /* 154161 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51660 /* 154166 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51661 /* 154171 */ // GIR_Coverage, 3794,
51662 /* 154171 */ GIR_EraseRootFromParent_Done,
51663 /* 154172 */ // Label 2129: @154172
51664 /* 154172 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(154240), // Rule ID 3796 //
51665 /* 154177 */ // MIs[0] Operand 1
51666 /* 154177 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
51667 /* 154182 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51668 /* 154186 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51669 /* 154190 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51670 /* 154194 */ // MIs[1] Operand 1
51671 /* 154194 */ // No operand predicates
51672 /* 154194 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51673 /* 154196 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] })
51674 /* 154196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
51675 /* 154199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51676 /* 154203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51677 /* 154208 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
51678 /* 154212 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
51679 /* 154215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51680 /* 154217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51681 /* 154220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51682 /* 154222 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
51683 /* 154229 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51684 /* 154234 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51685 /* 154239 */ // GIR_Coverage, 3796,
51686 /* 154239 */ GIR_EraseRootFromParent_Done,
51687 /* 154240 */ // Label 2130: @154240
51688 /* 154240 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(154308), // Rule ID 3797 //
51689 /* 154245 */ // MIs[0] Operand 1
51690 /* 154245 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
51691 /* 154250 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51692 /* 154254 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51693 /* 154258 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51694 /* 154262 */ // MIs[1] Operand 1
51695 /* 154262 */ // No operand predicates
51696 /* 154262 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51697 /* 154264 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] })
51698 /* 154264 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
51699 /* 154267 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51700 /* 154271 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51701 /* 154276 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
51702 /* 154280 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
51703 /* 154283 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51704 /* 154285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51705 /* 154288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51706 /* 154290 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
51707 /* 154297 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51708 /* 154302 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51709 /* 154307 */ // GIR_Coverage, 3797,
51710 /* 154307 */ GIR_EraseRootFromParent_Done,
51711 /* 154308 */ // Label 2131: @154308
51712 /* 154308 */ GIM_Reject,
51713 /* 154309 */ // Label 2128: @154309
51714 /* 154309 */ GIM_Reject,
51715 /* 154310 */ // Label 2126: @154310
51716 /* 154310 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(154527),
51717 /* 154315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
51718 /* 154318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
51719 /* 154322 */ GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(154390), // Rule ID 3806 //
51720 /* 154327 */ // MIs[0] Operand 1
51721 /* 154327 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
51722 /* 154332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51723 /* 154336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51724 /* 154340 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51725 /* 154344 */ // MIs[1] Operand 1
51726 /* 154344 */ // No operand predicates
51727 /* 154344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51728 /* 154346 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] })
51729 /* 154346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
51730 /* 154349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51731 /* 154353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51732 /* 154358 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
51733 /* 154362 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
51734 /* 154365 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51735 /* 154367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51736 /* 154370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51737 /* 154372 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
51738 /* 154379 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51739 /* 154384 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51740 /* 154389 */ // GIR_Coverage, 3806,
51741 /* 154389 */ GIR_EraseRootFromParent_Done,
51742 /* 154390 */ // Label 2133: @154390
51743 /* 154390 */ GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(154458), // Rule ID 3808 //
51744 /* 154395 */ // MIs[0] Operand 1
51745 /* 154395 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
51746 /* 154400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51747 /* 154404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51748 /* 154408 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51749 /* 154412 */ // MIs[1] Operand 1
51750 /* 154412 */ // No operand predicates
51751 /* 154412 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51752 /* 154414 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] })
51753 /* 154414 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
51754 /* 154417 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51755 /* 154421 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51756 /* 154426 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
51757 /* 154430 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
51758 /* 154433 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51759 /* 154435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51760 /* 154438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51761 /* 154440 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
51762 /* 154447 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51763 /* 154452 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51764 /* 154457 */ // GIR_Coverage, 3808,
51765 /* 154457 */ GIR_EraseRootFromParent_Done,
51766 /* 154458 */ // Label 2134: @154458
51767 /* 154458 */ GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(154526), // Rule ID 3809 //
51768 /* 154463 */ // MIs[0] Operand 1
51769 /* 154463 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
51770 /* 154468 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51771 /* 154472 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51772 /* 154476 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51773 /* 154480 */ // MIs[1] Operand 1
51774 /* 154480 */ // No operand predicates
51775 /* 154480 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51776 /* 154482 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] })
51777 /* 154482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
51778 /* 154485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51779 /* 154489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51780 /* 154494 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
51781 /* 154498 */ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
51782 /* 154501 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
51783 /* 154503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51784 /* 154506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51785 /* 154508 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
51786 /* 154515 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51787 /* 154520 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51788 /* 154525 */ // GIR_Coverage, 3809,
51789 /* 154525 */ GIR_EraseRootFromParent_Done,
51790 /* 154526 */ // Label 2135: @154526
51791 /* 154526 */ GIM_Reject,
51792 /* 154527 */ // Label 2132: @154527
51793 /* 154527 */ GIM_Reject,
51794 /* 154528 */ // Label 2127: @154528
51795 /* 154528 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2138*/ GIMT_Encode4(155097),
51796 /* 154539 */ /*GILLT_s32*//*Label 2136*/ GIMT_Encode4(154547),
51797 /* 154543 */ /*GILLT_s64*//*Label 2137*/ GIMT_Encode4(154822),
51798 /* 154547 */ // Label 2136: @154547
51799 /* 154547 */ GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(154821),
51800 /* 154552 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51801 /* 154555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
51802 /* 154559 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(154646), // Rule ID 3817 //
51803 /* 154564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
51804 /* 154567 */ // MIs[0] Operand 1
51805 /* 154567 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
51806 /* 154572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51807 /* 154576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51808 /* 154580 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51809 /* 154584 */ // MIs[1] Operand 1
51810 /* 154584 */ // No operand predicates
51811 /* 154584 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51812 /* 154586 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }))
51813 /* 154586 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51814 /* 154589 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51815 /* 154593 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51816 /* 154598 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51817 /* 154602 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51818 /* 154605 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51819 /* 154607 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51820 /* 154610 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51821 /* 154614 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51822 /* 154619 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
51823 /* 154626 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51824 /* 154631 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51825 /* 154636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51826 /* 154639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51827 /* 154641 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51828 /* 154644 */ GIR_RootConstrainSelectedInstOperands,
51829 /* 154645 */ // GIR_Coverage, 3817,
51830 /* 154645 */ GIR_EraseRootFromParent_Done,
51831 /* 154646 */ // Label 2140: @154646
51832 /* 154646 */ GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(154733), // Rule ID 3833 //
51833 /* 154651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
51834 /* 154654 */ // MIs[0] Operand 1
51835 /* 154654 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
51836 /* 154659 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51837 /* 154663 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51838 /* 154667 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51839 /* 154671 */ // MIs[1] Operand 1
51840 /* 154671 */ // No operand predicates
51841 /* 154671 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51842 /* 154673 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }))
51843 /* 154673 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51844 /* 154676 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51845 /* 154680 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51846 /* 154685 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51847 /* 154689 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51848 /* 154692 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51849 /* 154694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51850 /* 154697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51851 /* 154701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51852 /* 154706 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
51853 /* 154713 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51854 /* 154718 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51855 /* 154723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51856 /* 154726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51857 /* 154728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51858 /* 154731 */ GIR_RootConstrainSelectedInstOperands,
51859 /* 154732 */ // GIR_Coverage, 3833,
51860 /* 154732 */ GIR_EraseRootFromParent_Done,
51861 /* 154733 */ // Label 2141: @154733
51862 /* 154733 */ GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(154820), // Rule ID 3841 //
51863 /* 154738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
51864 /* 154741 */ // MIs[0] Operand 1
51865 /* 154741 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
51866 /* 154746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51867 /* 154750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51868 /* 154754 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16),
51869 /* 154758 */ // MIs[1] Operand 1
51870 /* 154758 */ // No operand predicates
51871 /* 154758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51872 /* 154760 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }))
51873 /* 154760 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51874 /* 154763 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI),
51875 /* 154767 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51876 /* 154772 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51877 /* 154776 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51878 /* 154779 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51879 /* 154781 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51880 /* 154784 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51881 /* 154788 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51882 /* 154793 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
51883 /* 154800 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51884 /* 154805 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51885 /* 154810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51886 /* 154813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51887 /* 154815 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51888 /* 154818 */ GIR_RootConstrainSelectedInstOperands,
51889 /* 154819 */ // GIR_Coverage, 3841,
51890 /* 154819 */ GIR_EraseRootFromParent_Done,
51891 /* 154820 */ // Label 2142: @154820
51892 /* 154820 */ GIM_Reject,
51893 /* 154821 */ // Label 2139: @154821
51894 /* 154821 */ GIM_Reject,
51895 /* 154822 */ // Label 2137: @154822
51896 /* 154822 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(155096),
51897 /* 154827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
51898 /* 154830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
51899 /* 154834 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(154921), // Rule ID 3913 //
51900 /* 154839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
51901 /* 154842 */ // MIs[0] Operand 1
51902 /* 154842 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
51903 /* 154847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51904 /* 154851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51905 /* 154855 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51906 /* 154859 */ // MIs[1] Operand 1
51907 /* 154859 */ // No operand predicates
51908 /* 154859 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51909 /* 154861 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }))
51910 /* 154861 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51911 /* 154864 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51912 /* 154868 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51913 /* 154873 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51914 /* 154877 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51915 /* 154880 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51916 /* 154882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51917 /* 154885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51918 /* 154889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51919 /* 154894 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
51920 /* 154901 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51921 /* 154906 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51922 /* 154911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51923 /* 154914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51924 /* 154916 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51925 /* 154919 */ GIR_RootConstrainSelectedInstOperands,
51926 /* 154920 */ // GIR_Coverage, 3913,
51927 /* 154920 */ GIR_EraseRootFromParent_Done,
51928 /* 154921 */ // Label 2144: @154921
51929 /* 154921 */ GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(155008), // Rule ID 3929 //
51930 /* 154926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
51931 /* 154929 */ // MIs[0] Operand 1
51932 /* 154929 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
51933 /* 154934 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51934 /* 154938 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51935 /* 154942 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51936 /* 154946 */ // MIs[1] Operand 1
51937 /* 154946 */ // No operand predicates
51938 /* 154946 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51939 /* 154948 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }))
51940 /* 154948 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51941 /* 154951 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51942 /* 154955 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51943 /* 154960 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51944 /* 154964 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51945 /* 154967 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51946 /* 154969 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51947 /* 154972 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51948 /* 154976 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51949 /* 154981 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
51950 /* 154988 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51951 /* 154993 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51952 /* 154998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51953 /* 155001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51954 /* 155003 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51955 /* 155006 */ GIR_RootConstrainSelectedInstOperands,
51956 /* 155007 */ // GIR_Coverage, 3929,
51957 /* 155007 */ GIR_EraseRootFromParent_Done,
51958 /* 155008 */ // Label 2145: @155008
51959 /* 155008 */ GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(155095), // Rule ID 3937 //
51960 /* 155013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
51961 /* 155016 */ // MIs[0] Operand 1
51962 /* 155016 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
51963 /* 155021 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51964 /* 155025 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51965 /* 155029 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16),
51966 /* 155033 */ // MIs[1] Operand 1
51967 /* 155033 */ // No operand predicates
51968 /* 155033 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
51969 /* 155035 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }))
51970 /* 155035 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
51971 /* 155038 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI),
51972 /* 155042 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51973 /* 155047 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
51974 /* 155051 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
51975 /* 155054 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
51976 /* 155056 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
51977 /* 155059 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
51978 /* 155063 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
51979 /* 155068 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
51980 /* 155075 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
51981 /* 155080 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
51982 /* 155085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
51983 /* 155088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
51984 /* 155090 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
51985 /* 155093 */ GIR_RootConstrainSelectedInstOperands,
51986 /* 155094 */ // GIR_Coverage, 3937,
51987 /* 155094 */ GIR_EraseRootFromParent_Done,
51988 /* 155095 */ // Label 2146: @155095
51989 /* 155095 */ GIM_Reject,
51990 /* 155096 */ // Label 2143: @155096
51991 /* 155096 */ GIM_Reject,
51992 /* 155097 */ // Label 2138: @155097
51993 /* 155097 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2150*/ GIMT_Encode4(156112),
51994 /* 155108 */ /*GILLT_s1*//*Label 2147*/ GIMT_Encode4(155120),
51995 /* 155112 */ /*GILLT_s32*//*Label 2148*/ GIMT_Encode4(155344),
51996 /* 155116 */ /*GILLT_s64*//*Label 2149*/ GIMT_Encode4(155728),
51997 /* 155120 */ // Label 2147: @155120
51998 /* 155120 */ GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(155343),
51999 /* 155125 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s1,
52000 /* 155128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52001 /* 155132 */ GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(155153), // Rule ID 3679 //
52002 /* 155137 */ // MIs[0] Operand 1
52003 /* 155137 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
52004 /* 155142 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETLT:{ *:[Other] }) => (CRANDC:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2)
52005 /* 155142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC),
52006 /* 155145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52007 /* 155147 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52008 /* 155149 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52009 /* 155151 */ GIR_RootConstrainSelectedInstOperands,
52010 /* 155152 */ // GIR_Coverage, 3679,
52011 /* 155152 */ GIR_EraseRootFromParent_Done,
52012 /* 155153 */ // Label 2152: @155153
52013 /* 155153 */ GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(155174), // Rule ID 3680 //
52014 /* 155158 */ // MIs[0] Operand 1
52015 /* 155158 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
52016 /* 155163 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETULT:{ *:[Other] }) => (CRANDC:{ *:[i1] } ?:{ *:[i1] }:$s2, ?:{ *:[i1] }:$s1)
52017 /* 155163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC),
52018 /* 155166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52019 /* 155168 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52020 /* 155170 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52021 /* 155172 */ GIR_RootConstrainSelectedInstOperands,
52022 /* 155173 */ // GIR_Coverage, 3680,
52023 /* 155173 */ GIR_EraseRootFromParent_Done,
52024 /* 155174 */ // Label 2153: @155174
52025 /* 155174 */ GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(155195), // Rule ID 3681 //
52026 /* 155179 */ // MIs[0] Operand 1
52027 /* 155179 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
52028 /* 155184 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETLE:{ *:[Other] }) => (CRORC:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2)
52029 /* 155184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC),
52030 /* 155187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52031 /* 155189 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52032 /* 155191 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52033 /* 155193 */ GIR_RootConstrainSelectedInstOperands,
52034 /* 155194 */ // GIR_Coverage, 3681,
52035 /* 155194 */ GIR_EraseRootFromParent_Done,
52036 /* 155195 */ // Label 2154: @155195
52037 /* 155195 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(155216), // Rule ID 3682 //
52038 /* 155200 */ // MIs[0] Operand 1
52039 /* 155200 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
52040 /* 155205 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETULE:{ *:[Other] }) => (CRORC:{ *:[i1] } ?:{ *:[i1] }:$s2, ?:{ *:[i1] }:$s1)
52041 /* 155205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC),
52042 /* 155208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52043 /* 155210 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52044 /* 155212 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52045 /* 155214 */ GIR_RootConstrainSelectedInstOperands,
52046 /* 155215 */ // GIR_Coverage, 3682,
52047 /* 155215 */ GIR_EraseRootFromParent_Done,
52048 /* 155216 */ // Label 2155: @155216
52049 /* 155216 */ GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(155237), // Rule ID 3683 //
52050 /* 155221 */ // MIs[0] Operand 1
52051 /* 155221 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
52052 /* 155226 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETEQ:{ *:[Other] }) => (CREQV:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2)
52053 /* 155226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV),
52054 /* 155229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52055 /* 155231 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52056 /* 155233 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52057 /* 155235 */ GIR_RootConstrainSelectedInstOperands,
52058 /* 155236 */ // GIR_Coverage, 3683,
52059 /* 155236 */ GIR_EraseRootFromParent_Done,
52060 /* 155237 */ // Label 2156: @155237
52061 /* 155237 */ GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(155258), // Rule ID 3684 //
52062 /* 155242 */ // MIs[0] Operand 1
52063 /* 155242 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
52064 /* 155247 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETGE:{ *:[Other] }) => (CRORC:{ *:[i1] } ?:{ *:[i1] }:$s2, ?:{ *:[i1] }:$s1)
52065 /* 155247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC),
52066 /* 155250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52067 /* 155252 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52068 /* 155254 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52069 /* 155256 */ GIR_RootConstrainSelectedInstOperands,
52070 /* 155257 */ // GIR_Coverage, 3684,
52071 /* 155257 */ GIR_EraseRootFromParent_Done,
52072 /* 155258 */ // Label 2157: @155258
52073 /* 155258 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(155279), // Rule ID 3685 //
52074 /* 155263 */ // MIs[0] Operand 1
52075 /* 155263 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
52076 /* 155268 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETUGE:{ *:[Other] }) => (CRORC:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2)
52077 /* 155268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC),
52078 /* 155271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52079 /* 155273 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52080 /* 155275 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52081 /* 155277 */ GIR_RootConstrainSelectedInstOperands,
52082 /* 155278 */ // GIR_Coverage, 3685,
52083 /* 155278 */ GIR_EraseRootFromParent_Done,
52084 /* 155279 */ // Label 2158: @155279
52085 /* 155279 */ GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(155300), // Rule ID 3686 //
52086 /* 155284 */ // MIs[0] Operand 1
52087 /* 155284 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
52088 /* 155289 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETGT:{ *:[Other] }) => (CRANDC:{ *:[i1] } ?:{ *:[i1] }:$s2, ?:{ *:[i1] }:$s1)
52089 /* 155289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC),
52090 /* 155292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52091 /* 155294 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52092 /* 155296 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52093 /* 155298 */ GIR_RootConstrainSelectedInstOperands,
52094 /* 155299 */ // GIR_Coverage, 3686,
52095 /* 155299 */ GIR_EraseRootFromParent_Done,
52096 /* 155300 */ // Label 2159: @155300
52097 /* 155300 */ GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(155321), // Rule ID 3687 //
52098 /* 155305 */ // MIs[0] Operand 1
52099 /* 155305 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
52100 /* 155310 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETUGT:{ *:[Other] }) => (CRANDC:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2)
52101 /* 155310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC),
52102 /* 155313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52103 /* 155315 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52104 /* 155317 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52105 /* 155319 */ GIR_RootConstrainSelectedInstOperands,
52106 /* 155320 */ // GIR_Coverage, 3687,
52107 /* 155320 */ GIR_EraseRootFromParent_Done,
52108 /* 155321 */ // Label 2160: @155321
52109 /* 155321 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(155342), // Rule ID 3688 //
52110 /* 155326 */ // MIs[0] Operand 1
52111 /* 155326 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
52112 /* 155331 */ // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETNE:{ *:[Other] }) => (CRXOR:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2)
52113 /* 155331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRXOR),
52114 /* 155334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52115 /* 155336 */ GIR_RootToRootCopy, /*OpIdx*/2, // s1
52116 /* 155338 */ GIR_RootToRootCopy, /*OpIdx*/3, // s2
52117 /* 155340 */ GIR_RootConstrainSelectedInstOperands,
52118 /* 155341 */ // GIR_Coverage, 3688,
52119 /* 155341 */ GIR_EraseRootFromParent_Done,
52120 /* 155342 */ // Label 2161: @155342
52121 /* 155342 */ GIM_Reject,
52122 /* 155343 */ // Label 2151: @155343
52123 /* 155343 */ GIM_Reject,
52124 /* 155344 */ // Label 2148: @155344
52125 /* 155344 */ GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(155727),
52126 /* 155349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
52127 /* 155352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52128 /* 155356 */ GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(155430), // Rule ID 2980 //
52129 /* 155361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52130 /* 155364 */ // MIs[0] Operand 1
52131 /* 155364 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
52132 /* 155369 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
52133 /* 155369 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52134 /* 155372 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
52135 /* 155376 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52136 /* 155381 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52137 /* 155385 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52138 /* 155389 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52139 /* 155391 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52140 /* 155394 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52141 /* 155398 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52142 /* 155403 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52143 /* 155410 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52144 /* 155415 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52145 /* 155420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52146 /* 155423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52147 /* 155425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52148 /* 155428 */ GIR_RootConstrainSelectedInstOperands,
52149 /* 155429 */ // GIR_Coverage, 2980,
52150 /* 155429 */ GIR_EraseRootFromParent_Done,
52151 /* 155430 */ // Label 2163: @155430
52152 /* 155430 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(155504), // Rule ID 2994 //
52153 /* 155435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52154 /* 155438 */ // MIs[0] Operand 1
52155 /* 155438 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
52156 /* 155443 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
52157 /* 155443 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52158 /* 155446 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52159 /* 155450 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52160 /* 155455 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52161 /* 155459 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52162 /* 155463 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52163 /* 155465 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52164 /* 155468 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52165 /* 155472 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52166 /* 155477 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52167 /* 155484 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52168 /* 155489 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52169 /* 155494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52170 /* 155497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52171 /* 155499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52172 /* 155502 */ GIR_RootConstrainSelectedInstOperands,
52173 /* 155503 */ // GIR_Coverage, 2994,
52174 /* 155503 */ GIR_EraseRootFromParent_Done,
52175 /* 155504 */ // Label 2164: @155504
52176 /* 155504 */ GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(155578), // Rule ID 3002 //
52177 /* 155509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52178 /* 155512 */ // MIs[0] Operand 1
52179 /* 155512 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
52180 /* 155517 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
52181 /* 155517 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52182 /* 155520 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
52183 /* 155524 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52184 /* 155529 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52185 /* 155533 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52186 /* 155537 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52187 /* 155539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52188 /* 155542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52189 /* 155546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52190 /* 155551 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52191 /* 155558 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52192 /* 155563 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52193 /* 155568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52194 /* 155571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52195 /* 155573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52196 /* 155576 */ GIR_RootConstrainSelectedInstOperands,
52197 /* 155577 */ // GIR_Coverage, 3002,
52198 /* 155577 */ GIR_EraseRootFromParent_Done,
52199 /* 155578 */ // Label 2165: @155578
52200 /* 155578 */ GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(155652), // Rule ID 3010 //
52201 /* 155583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52202 /* 155586 */ // MIs[0] Operand 1
52203 /* 155586 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
52204 /* 155591 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
52205 /* 155591 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52206 /* 155594 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52207 /* 155598 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52208 /* 155603 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52209 /* 155607 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52210 /* 155611 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52211 /* 155613 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52212 /* 155616 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52213 /* 155620 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52214 /* 155625 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52215 /* 155632 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52216 /* 155637 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52217 /* 155642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52218 /* 155645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52219 /* 155647 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52220 /* 155650 */ GIR_RootConstrainSelectedInstOperands,
52221 /* 155651 */ // GIR_Coverage, 3010,
52222 /* 155651 */ GIR_EraseRootFromParent_Done,
52223 /* 155652 */ // Label 2166: @155652
52224 /* 155652 */ GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(155726), // Rule ID 3018 //
52225 /* 155657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52226 /* 155660 */ // MIs[0] Operand 1
52227 /* 155660 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
52228 /* 155665 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }))
52229 /* 155665 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52230 /* 155668 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52231 /* 155672 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52232 /* 155677 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52233 /* 155681 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52234 /* 155685 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52235 /* 155687 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52236 /* 155690 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52237 /* 155694 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52238 /* 155699 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
52239 /* 155706 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52240 /* 155711 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52241 /* 155716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52242 /* 155719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52243 /* 155721 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52244 /* 155724 */ GIR_RootConstrainSelectedInstOperands,
52245 /* 155725 */ // GIR_Coverage, 3018,
52246 /* 155725 */ GIR_EraseRootFromParent_Done,
52247 /* 155726 */ // Label 2167: @155726
52248 /* 155726 */ GIM_Reject,
52249 /* 155727 */ // Label 2162: @155727
52250 /* 155727 */ GIM_Reject,
52251 /* 155728 */ // Label 2149: @155728
52252 /* 155728 */ GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(156111),
52253 /* 155733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
52254 /* 155736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52255 /* 155740 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(155814), // Rule ID 3082 //
52256 /* 155745 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52257 /* 155748 */ // MIs[0] Operand 1
52258 /* 155748 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
52259 /* 155753 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
52260 /* 155753 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52261 /* 155756 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
52262 /* 155760 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52263 /* 155765 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52264 /* 155769 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52265 /* 155773 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52266 /* 155775 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52267 /* 155778 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52268 /* 155782 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52269 /* 155787 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52270 /* 155794 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52271 /* 155799 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52272 /* 155804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52273 /* 155807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52274 /* 155809 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52275 /* 155812 */ GIR_RootConstrainSelectedInstOperands,
52276 /* 155813 */ // GIR_Coverage, 3082,
52277 /* 155813 */ GIR_EraseRootFromParent_Done,
52278 /* 155814 */ // Label 2169: @155814
52279 /* 155814 */ GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(155888), // Rule ID 3090 //
52280 /* 155819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52281 /* 155822 */ // MIs[0] Operand 1
52282 /* 155822 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
52283 /* 155827 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
52284 /* 155827 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52285 /* 155830 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52286 /* 155834 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52287 /* 155839 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52288 /* 155843 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52289 /* 155847 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52290 /* 155849 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52291 /* 155852 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52292 /* 155856 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52293 /* 155861 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52294 /* 155868 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52295 /* 155873 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52296 /* 155878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52297 /* 155881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52298 /* 155883 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52299 /* 155886 */ GIR_RootConstrainSelectedInstOperands,
52300 /* 155887 */ // GIR_Coverage, 3090,
52301 /* 155887 */ GIR_EraseRootFromParent_Done,
52302 /* 155888 */ // Label 2170: @155888
52303 /* 155888 */ GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(155962), // Rule ID 3098 //
52304 /* 155893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52305 /* 155896 */ // MIs[0] Operand 1
52306 /* 155896 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
52307 /* 155901 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
52308 /* 155901 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52309 /* 155904 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
52310 /* 155908 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52311 /* 155913 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52312 /* 155917 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52313 /* 155921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52314 /* 155923 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52315 /* 155926 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52316 /* 155930 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52317 /* 155935 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52318 /* 155942 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52319 /* 155947 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52320 /* 155952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52321 /* 155955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52322 /* 155957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52323 /* 155960 */ GIR_RootConstrainSelectedInstOperands,
52324 /* 155961 */ // GIR_Coverage, 3098,
52325 /* 155961 */ GIR_EraseRootFromParent_Done,
52326 /* 155962 */ // Label 2171: @155962
52327 /* 155962 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(156036), // Rule ID 3106 //
52328 /* 155967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52329 /* 155970 */ // MIs[0] Operand 1
52330 /* 155970 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
52331 /* 155975 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
52332 /* 155975 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52333 /* 155978 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52334 /* 155982 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52335 /* 155987 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52336 /* 155991 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52337 /* 155995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52338 /* 155997 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52339 /* 156000 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52340 /* 156004 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52341 /* 156009 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52342 /* 156016 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52343 /* 156021 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52344 /* 156026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52345 /* 156029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52346 /* 156031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52347 /* 156034 */ GIR_RootConstrainSelectedInstOperands,
52348 /* 156035 */ // GIR_Coverage, 3106,
52349 /* 156035 */ GIR_EraseRootFromParent_Done,
52350 /* 156036 */ // Label 2172: @156036
52351 /* 156036 */ GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(156110), // Rule ID 3114 //
52352 /* 156041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
52353 /* 156044 */ // MIs[0] Operand 1
52354 /* 156044 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
52355 /* 156049 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }))
52356 /* 156049 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52357 /* 156052 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52358 /* 156056 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52359 /* 156061 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52360 /* 156065 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52361 /* 156069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52362 /* 156071 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52363 /* 156074 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52364 /* 156078 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52365 /* 156083 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
52366 /* 156090 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52367 /* 156095 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52368 /* 156100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52369 /* 156103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52370 /* 156105 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52371 /* 156108 */ GIR_RootConstrainSelectedInstOperands,
52372 /* 156109 */ // GIR_Coverage, 3114,
52373 /* 156109 */ GIR_EraseRootFromParent_Done,
52374 /* 156110 */ // Label 2173: @156110
52375 /* 156110 */ GIM_Reject,
52376 /* 156111 */ // Label 2168: @156111
52377 /* 156111 */ GIM_Reject,
52378 /* 156112 */ // Label 2150: @156112
52379 /* 156112 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2176*/ GIMT_Encode4(156709),
52380 /* 156123 */ /*GILLT_s32*//*Label 2174*/ GIMT_Encode4(156131),
52381 /* 156127 */ /*GILLT_s64*//*Label 2175*/ GIMT_Encode4(156420),
52382 /* 156131 */ // Label 2174: @156131
52383 /* 156131 */ GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(156419),
52384 /* 156136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
52385 /* 156139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52386 /* 156143 */ GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(156198), // Rule ID 3800 //
52387 /* 156148 */ // MIs[0] Operand 1
52388 /* 156148 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
52389 /* 156153 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })
52390 /* 156153 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52391 /* 156156 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
52392 /* 156160 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52393 /* 156165 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52394 /* 156169 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52395 /* 156173 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52396 /* 156175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52397 /* 156178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52398 /* 156180 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52399 /* 156187 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52400 /* 156192 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52401 /* 156197 */ // GIR_Coverage, 3800,
52402 /* 156197 */ GIR_EraseRootFromParent_Done,
52403 /* 156198 */ // Label 2178: @156198
52404 /* 156198 */ GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(156253), // Rule ID 3801 //
52405 /* 156203 */ // MIs[0] Operand 1
52406 /* 156203 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
52407 /* 156208 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })
52408 /* 156208 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52409 /* 156211 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52410 /* 156215 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52411 /* 156220 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52412 /* 156224 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52413 /* 156228 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52414 /* 156230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52415 /* 156233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52416 /* 156235 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52417 /* 156242 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52418 /* 156247 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52419 /* 156252 */ // GIR_Coverage, 3801,
52420 /* 156252 */ GIR_EraseRootFromParent_Done,
52421 /* 156253 */ // Label 2179: @156253
52422 /* 156253 */ GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(156308), // Rule ID 3802 //
52423 /* 156258 */ // MIs[0] Operand 1
52424 /* 156258 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
52425 /* 156263 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })
52426 /* 156263 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52427 /* 156266 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
52428 /* 156270 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52429 /* 156275 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52430 /* 156279 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52431 /* 156283 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52432 /* 156285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52433 /* 156288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52434 /* 156290 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52435 /* 156297 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52436 /* 156302 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52437 /* 156307 */ // GIR_Coverage, 3802,
52438 /* 156307 */ GIR_EraseRootFromParent_Done,
52439 /* 156308 */ // Label 2180: @156308
52440 /* 156308 */ GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(156363), // Rule ID 3803 //
52441 /* 156313 */ // MIs[0] Operand 1
52442 /* 156313 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
52443 /* 156318 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })
52444 /* 156318 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52445 /* 156321 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52446 /* 156325 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52447 /* 156330 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52448 /* 156334 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52449 /* 156338 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52450 /* 156340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52451 /* 156343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52452 /* 156345 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52453 /* 156352 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52454 /* 156357 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52455 /* 156362 */ // GIR_Coverage, 3803,
52456 /* 156362 */ GIR_EraseRootFromParent_Done,
52457 /* 156363 */ // Label 2181: @156363
52458 /* 156363 */ GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(156418), // Rule ID 3804 //
52459 /* 156368 */ // MIs[0] Operand 1
52460 /* 156368 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
52461 /* 156373 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] })
52462 /* 156373 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52463 /* 156376 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52464 /* 156380 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52465 /* 156385 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52466 /* 156389 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52467 /* 156393 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52468 /* 156395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52469 /* 156398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52470 /* 156400 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
52471 /* 156407 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52472 /* 156412 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52473 /* 156417 */ // GIR_Coverage, 3804,
52474 /* 156417 */ GIR_EraseRootFromParent_Done,
52475 /* 156418 */ // Label 2182: @156418
52476 /* 156418 */ GIM_Reject,
52477 /* 156419 */ // Label 2177: @156419
52478 /* 156419 */ GIM_Reject,
52479 /* 156420 */ // Label 2175: @156420
52480 /* 156420 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(156708),
52481 /* 156425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
52482 /* 156428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52483 /* 156432 */ GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(156487), // Rule ID 3812 //
52484 /* 156437 */ // MIs[0] Operand 1
52485 /* 156437 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
52486 /* 156442 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })
52487 /* 156442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52488 /* 156445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
52489 /* 156449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52490 /* 156454 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52491 /* 156458 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52492 /* 156462 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52493 /* 156464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52494 /* 156467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52495 /* 156469 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52496 /* 156476 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52497 /* 156481 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52498 /* 156486 */ // GIR_Coverage, 3812,
52499 /* 156486 */ GIR_EraseRootFromParent_Done,
52500 /* 156487 */ // Label 2184: @156487
52501 /* 156487 */ GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(156542), // Rule ID 3813 //
52502 /* 156492 */ // MIs[0] Operand 1
52503 /* 156492 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
52504 /* 156497 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })
52505 /* 156497 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52506 /* 156500 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52507 /* 156504 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52508 /* 156509 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52509 /* 156513 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52510 /* 156517 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52511 /* 156519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52512 /* 156522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52513 /* 156524 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52514 /* 156531 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52515 /* 156536 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52516 /* 156541 */ // GIR_Coverage, 3813,
52517 /* 156541 */ GIR_EraseRootFromParent_Done,
52518 /* 156542 */ // Label 2185: @156542
52519 /* 156542 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(156597), // Rule ID 3814 //
52520 /* 156547 */ // MIs[0] Operand 1
52521 /* 156547 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
52522 /* 156552 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })
52523 /* 156552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52524 /* 156555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
52525 /* 156559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52526 /* 156564 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52527 /* 156568 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52528 /* 156572 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52529 /* 156574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52530 /* 156577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52531 /* 156579 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52532 /* 156586 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52533 /* 156591 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52534 /* 156596 */ // GIR_Coverage, 3814,
52535 /* 156596 */ GIR_EraseRootFromParent_Done,
52536 /* 156597 */ // Label 2186: @156597
52537 /* 156597 */ GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(156652), // Rule ID 3815 //
52538 /* 156602 */ // MIs[0] Operand 1
52539 /* 156602 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
52540 /* 156607 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })
52541 /* 156607 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52542 /* 156610 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52543 /* 156614 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52544 /* 156619 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52545 /* 156623 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52546 /* 156627 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52547 /* 156629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52548 /* 156632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52549 /* 156634 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52550 /* 156641 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52551 /* 156646 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52552 /* 156651 */ // GIR_Coverage, 3815,
52553 /* 156651 */ GIR_EraseRootFromParent_Done,
52554 /* 156652 */ // Label 2187: @156652
52555 /* 156652 */ GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(156707), // Rule ID 3816 //
52556 /* 156657 */ // MIs[0] Operand 1
52557 /* 156657 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
52558 /* 156662 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] })
52559 /* 156662 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52560 /* 156665 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52561 /* 156669 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52562 /* 156674 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
52563 /* 156678 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
52564 /* 156682 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
52565 /* 156684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52566 /* 156687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
52567 /* 156689 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
52568 /* 156696 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52569 /* 156701 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52570 /* 156706 */ // GIR_Coverage, 3816,
52571 /* 156706 */ GIR_EraseRootFromParent_Done,
52572 /* 156707 */ // Label 2188: @156707
52573 /* 156707 */ GIM_Reject,
52574 /* 156708 */ // Label 2183: @156708
52575 /* 156708 */ GIM_Reject,
52576 /* 156709 */ // Label 2176: @156709
52577 /* 156709 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2191*/ GIMT_Encode4(157496),
52578 /* 156720 */ /*GILLT_s32*//*Label 2189*/ GIMT_Encode4(156728),
52579 /* 156724 */ /*GILLT_s64*//*Label 2190*/ GIMT_Encode4(157112),
52580 /* 156728 */ // Label 2189: @156728
52581 /* 156728 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(157111),
52582 /* 156733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
52583 /* 156736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52584 /* 156740 */ GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(156814), // Rule ID 3865 //
52585 /* 156745 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52586 /* 156748 */ // MIs[0] Operand 1
52587 /* 156748 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
52588 /* 156753 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
52589 /* 156753 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52590 /* 156756 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
52591 /* 156760 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52592 /* 156765 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52593 /* 156769 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52594 /* 156773 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52595 /* 156775 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52596 /* 156778 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52597 /* 156782 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52598 /* 156787 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52599 /* 156794 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52600 /* 156799 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52601 /* 156804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52602 /* 156807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52603 /* 156809 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52604 /* 156812 */ GIR_RootConstrainSelectedInstOperands,
52605 /* 156813 */ // GIR_Coverage, 3865,
52606 /* 156813 */ GIR_EraseRootFromParent_Done,
52607 /* 156814 */ // Label 2193: @156814
52608 /* 156814 */ GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(156888), // Rule ID 3873 //
52609 /* 156819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52610 /* 156822 */ // MIs[0] Operand 1
52611 /* 156822 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
52612 /* 156827 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }))
52613 /* 156827 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52614 /* 156830 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52615 /* 156834 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52616 /* 156839 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52617 /* 156843 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52618 /* 156847 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52619 /* 156849 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52620 /* 156852 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52621 /* 156856 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52622 /* 156861 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52623 /* 156868 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52624 /* 156873 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52625 /* 156878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52626 /* 156881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52627 /* 156883 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52628 /* 156886 */ GIR_RootConstrainSelectedInstOperands,
52629 /* 156887 */ // GIR_Coverage, 3873,
52630 /* 156887 */ GIR_EraseRootFromParent_Done,
52631 /* 156888 */ // Label 2194: @156888
52632 /* 156888 */ GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(156962), // Rule ID 3881 //
52633 /* 156893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52634 /* 156896 */ // MIs[0] Operand 1
52635 /* 156896 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
52636 /* 156901 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
52637 /* 156901 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52638 /* 156904 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW),
52639 /* 156908 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52640 /* 156913 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52641 /* 156917 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52642 /* 156921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52643 /* 156923 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52644 /* 156926 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52645 /* 156930 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52646 /* 156935 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52647 /* 156942 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52648 /* 156947 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52649 /* 156952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52650 /* 156955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52651 /* 156957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52652 /* 156960 */ GIR_RootConstrainSelectedInstOperands,
52653 /* 156961 */ // GIR_Coverage, 3881,
52654 /* 156961 */ GIR_EraseRootFromParent_Done,
52655 /* 156962 */ // Label 2195: @156962
52656 /* 156962 */ GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(157036), // Rule ID 3889 //
52657 /* 156967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52658 /* 156970 */ // MIs[0] Operand 1
52659 /* 156970 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
52660 /* 156975 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }))
52661 /* 156975 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52662 /* 156978 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52663 /* 156982 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52664 /* 156987 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52665 /* 156991 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52666 /* 156995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52667 /* 156997 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52668 /* 157000 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52669 /* 157004 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52670 /* 157009 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52671 /* 157016 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52672 /* 157021 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52673 /* 157026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52674 /* 157029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52675 /* 157031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52676 /* 157034 */ GIR_RootConstrainSelectedInstOperands,
52677 /* 157035 */ // GIR_Coverage, 3889,
52678 /* 157035 */ GIR_EraseRootFromParent_Done,
52679 /* 157036 */ // Label 2196: @157036
52680 /* 157036 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(157110), // Rule ID 3897 //
52681 /* 157041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52682 /* 157044 */ // MIs[0] Operand 1
52683 /* 157044 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
52684 /* 157049 */ // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }))
52685 /* 157049 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52686 /* 157052 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW),
52687 /* 157056 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52688 /* 157061 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52689 /* 157065 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52690 /* 157069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52691 /* 157071 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52692 /* 157074 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52693 /* 157078 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52694 /* 157083 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
52695 /* 157090 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52696 /* 157095 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52697 /* 157100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52698 /* 157103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52699 /* 157105 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52700 /* 157108 */ GIR_RootConstrainSelectedInstOperands,
52701 /* 157109 */ // GIR_Coverage, 3897,
52702 /* 157109 */ GIR_EraseRootFromParent_Done,
52703 /* 157110 */ // Label 2197: @157110
52704 /* 157110 */ GIM_Reject,
52705 /* 157111 */ // Label 2192: @157111
52706 /* 157111 */ GIM_Reject,
52707 /* 157112 */ // Label 2190: @157112
52708 /* 157112 */ GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(157495),
52709 /* 157117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
52710 /* 157120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52711 /* 157124 */ GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(157198), // Rule ID 3961 //
52712 /* 157129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52713 /* 157132 */ // MIs[0] Operand 1
52714 /* 157132 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
52715 /* 157137 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
52716 /* 157137 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52717 /* 157140 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
52718 /* 157144 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52719 /* 157149 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52720 /* 157153 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52721 /* 157157 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52722 /* 157159 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52723 /* 157162 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52724 /* 157166 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52725 /* 157171 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52726 /* 157178 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52727 /* 157183 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52728 /* 157188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52729 /* 157191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52730 /* 157193 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52731 /* 157196 */ GIR_RootConstrainSelectedInstOperands,
52732 /* 157197 */ // GIR_Coverage, 3961,
52733 /* 157197 */ GIR_EraseRootFromParent_Done,
52734 /* 157198 */ // Label 2199: @157198
52735 /* 157198 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(157272), // Rule ID 3969 //
52736 /* 157203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52737 /* 157206 */ // MIs[0] Operand 1
52738 /* 157206 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
52739 /* 157211 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }))
52740 /* 157211 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52741 /* 157214 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52742 /* 157218 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52743 /* 157223 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52744 /* 157227 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52745 /* 157231 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52746 /* 157233 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52747 /* 157236 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52748 /* 157240 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52749 /* 157245 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52750 /* 157252 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52751 /* 157257 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52752 /* 157262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52753 /* 157265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52754 /* 157267 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52755 /* 157270 */ GIR_RootConstrainSelectedInstOperands,
52756 /* 157271 */ // GIR_Coverage, 3969,
52757 /* 157271 */ GIR_EraseRootFromParent_Done,
52758 /* 157272 */ // Label 2200: @157272
52759 /* 157272 */ GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(157346), // Rule ID 3977 //
52760 /* 157277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52761 /* 157280 */ // MIs[0] Operand 1
52762 /* 157280 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
52763 /* 157285 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
52764 /* 157285 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52765 /* 157288 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD),
52766 /* 157292 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52767 /* 157297 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52768 /* 157301 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52769 /* 157305 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52770 /* 157307 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52771 /* 157310 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52772 /* 157314 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52773 /* 157319 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52774 /* 157326 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52775 /* 157331 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52776 /* 157336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52777 /* 157339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52778 /* 157341 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52779 /* 157344 */ GIR_RootConstrainSelectedInstOperands,
52780 /* 157345 */ // GIR_Coverage, 3977,
52781 /* 157345 */ GIR_EraseRootFromParent_Done,
52782 /* 157346 */ // Label 2201: @157346
52783 /* 157346 */ GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(157420), // Rule ID 3985 //
52784 /* 157351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52785 /* 157354 */ // MIs[0] Operand 1
52786 /* 157354 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
52787 /* 157359 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }))
52788 /* 157359 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52789 /* 157362 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52790 /* 157366 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52791 /* 157371 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52792 /* 157375 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52793 /* 157379 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52794 /* 157381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52795 /* 157384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52796 /* 157388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52797 /* 157393 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52798 /* 157400 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52799 /* 157405 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52800 /* 157410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52801 /* 157413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52802 /* 157415 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52803 /* 157418 */ GIR_RootConstrainSelectedInstOperands,
52804 /* 157419 */ // GIR_Coverage, 3985,
52805 /* 157419 */ GIR_EraseRootFromParent_Done,
52806 /* 157420 */ // Label 2202: @157420
52807 /* 157420 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(157494), // Rule ID 3993 //
52808 /* 157425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1),
52809 /* 157428 */ // MIs[0] Operand 1
52810 /* 157428 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
52811 /* 157433 */ // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }))
52812 /* 157433 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52813 /* 157436 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD),
52814 /* 157440 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52815 /* 157445 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52816 /* 157449 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52817 /* 157453 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52818 /* 157455 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52819 /* 157458 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52820 /* 157462 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52821 /* 157467 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
52822 /* 157474 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52823 /* 157479 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52824 /* 157484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52825 /* 157487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52826 /* 157489 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52827 /* 157492 */ GIR_RootConstrainSelectedInstOperands,
52828 /* 157493 */ // GIR_Coverage, 3993,
52829 /* 157493 */ GIR_EraseRootFromParent_Done,
52830 /* 157494 */ // Label 2203: @157494
52831 /* 157494 */ GIM_Reject,
52832 /* 157495 */ // Label 2198: @157495
52833 /* 157495 */ GIM_Reject,
52834 /* 157496 */ // Label 2191: @157496
52835 /* 157496 */ GIM_Reject,
52836 /* 157497 */ // Label 2113: @157497
52837 /* 157497 */ GIM_Reject,
52838 /* 157498 */ // Label 32: @157498
52839 /* 157498 */ GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(160948),
52840 /* 157503 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
52841 /* 157506 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2208*/ GIMT_Encode4(158459),
52842 /* 157517 */ /*GILLT_s32*//*Label 2205*/ GIMT_Encode4(157529),
52843 /* 157521 */ /*GILLT_s64*//*Label 2206*/ GIMT_Encode4(157839),
52844 /* 157525 */ /*GILLT_s128*//*Label 2207*/ GIMT_Encode4(158149),
52845 /* 157529 */ // Label 2205: @157529
52846 /* 157529 */ GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(157838),
52847 /* 157534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
52848 /* 157537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52849 /* 157541 */ GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(157615), // Rule ID 3178 //
52850 /* 157546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
52851 /* 157549 */ // MIs[0] Operand 1
52852 /* 157549 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
52853 /* 157554 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }))
52854 /* 157554 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52855 /* 157557 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
52856 /* 157561 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52857 /* 157566 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52858 /* 157570 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52859 /* 157574 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52860 /* 157576 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52861 /* 157579 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52862 /* 157583 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52863 /* 157588 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52864 /* 157595 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52865 /* 157600 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52866 /* 157605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52867 /* 157608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52868 /* 157610 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52869 /* 157613 */ GIR_RootConstrainSelectedInstOperands,
52870 /* 157614 */ // GIR_Coverage, 3178,
52871 /* 157614 */ GIR_EraseRootFromParent_Done,
52872 /* 157615 */ // Label 2210: @157615
52873 /* 157615 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(157689), // Rule ID 3194 //
52874 /* 157620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
52875 /* 157623 */ // MIs[0] Operand 1
52876 /* 157623 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
52877 /* 157628 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
52878 /* 157628 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52879 /* 157631 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
52880 /* 157635 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52881 /* 157640 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52882 /* 157644 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52883 /* 157648 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52884 /* 157650 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52885 /* 157653 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52886 /* 157657 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52887 /* 157662 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52888 /* 157669 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52889 /* 157674 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52890 /* 157679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52891 /* 157682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52892 /* 157684 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52893 /* 157687 */ GIR_RootConstrainSelectedInstOperands,
52894 /* 157688 */ // GIR_Coverage, 3194,
52895 /* 157688 */ GIR_EraseRootFromParent_Done,
52896 /* 157689 */ // Label 2211: @157689
52897 /* 157689 */ GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(157763), // Rule ID 3210 //
52898 /* 157694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
52899 /* 157697 */ // MIs[0] Operand 1
52900 /* 157697 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
52901 /* 157702 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }))
52902 /* 157702 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52903 /* 157705 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
52904 /* 157709 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52905 /* 157714 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52906 /* 157718 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52907 /* 157722 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52908 /* 157724 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52909 /* 157727 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52910 /* 157731 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52911 /* 157736 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
52912 /* 157743 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52913 /* 157748 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52914 /* 157753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52915 /* 157756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52916 /* 157758 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52917 /* 157761 */ GIR_RootConstrainSelectedInstOperands,
52918 /* 157762 */ // GIR_Coverage, 3210,
52919 /* 157762 */ GIR_EraseRootFromParent_Done,
52920 /* 157763 */ // Label 2212: @157763
52921 /* 157763 */ GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(157837), // Rule ID 3226 //
52922 /* 157768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
52923 /* 157771 */ // MIs[0] Operand 1
52924 /* 157771 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
52925 /* 157776 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }))
52926 /* 157776 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52927 /* 157779 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
52928 /* 157783 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52929 /* 157788 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52930 /* 157792 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52931 /* 157796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52932 /* 157798 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52933 /* 157801 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52934 /* 157805 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52935 /* 157810 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
52936 /* 157817 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52937 /* 157822 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52938 /* 157827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52939 /* 157830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52940 /* 157832 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52941 /* 157835 */ GIR_RootConstrainSelectedInstOperands,
52942 /* 157836 */ // GIR_Coverage, 3226,
52943 /* 157836 */ GIR_EraseRootFromParent_Done,
52944 /* 157837 */ // Label 2213: @157837
52945 /* 157837 */ GIM_Reject,
52946 /* 157838 */ // Label 2209: @157838
52947 /* 157838 */ GIM_Reject,
52948 /* 157839 */ // Label 2206: @157839
52949 /* 157839 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(158148),
52950 /* 157844 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
52951 /* 157847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
52952 /* 157851 */ GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(157925), // Rule ID 3234 //
52953 /* 157856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
52954 /* 157859 */ // MIs[0] Operand 1
52955 /* 157859 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
52956 /* 157864 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }))
52957 /* 157864 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52958 /* 157867 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
52959 /* 157871 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52960 /* 157876 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52961 /* 157880 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52962 /* 157884 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52963 /* 157886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52964 /* 157889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52965 /* 157893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52966 /* 157898 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
52967 /* 157905 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52968 /* 157910 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52969 /* 157915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52970 /* 157918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52971 /* 157920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52972 /* 157923 */ GIR_RootConstrainSelectedInstOperands,
52973 /* 157924 */ // GIR_Coverage, 3234,
52974 /* 157924 */ GIR_EraseRootFromParent_Done,
52975 /* 157925 */ // Label 2215: @157925
52976 /* 157925 */ GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(157999), // Rule ID 3250 //
52977 /* 157930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
52978 /* 157933 */ // MIs[0] Operand 1
52979 /* 157933 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
52980 /* 157938 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
52981 /* 157938 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
52982 /* 157941 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
52983 /* 157945 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52984 /* 157950 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
52985 /* 157954 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
52986 /* 157958 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
52987 /* 157960 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
52988 /* 157963 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
52989 /* 157967 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
52990 /* 157972 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
52991 /* 157979 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
52992 /* 157984 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
52993 /* 157989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
52994 /* 157992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
52995 /* 157994 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
52996 /* 157997 */ GIR_RootConstrainSelectedInstOperands,
52997 /* 157998 */ // GIR_Coverage, 3250,
52998 /* 157998 */ GIR_EraseRootFromParent_Done,
52999 /* 157999 */ // Label 2216: @157999
53000 /* 157999 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(158073), // Rule ID 3266 //
53001 /* 158004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
53002 /* 158007 */ // MIs[0] Operand 1
53003 /* 158007 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
53004 /* 158012 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }))
53005 /* 158012 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53006 /* 158015 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53007 /* 158019 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53008 /* 158024 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53009 /* 158028 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53010 /* 158032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53011 /* 158034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53012 /* 158037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53013 /* 158041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53014 /* 158046 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
53015 /* 158053 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53016 /* 158058 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53017 /* 158063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53018 /* 158066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53019 /* 158068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53020 /* 158071 */ GIR_RootConstrainSelectedInstOperands,
53021 /* 158072 */ // GIR_Coverage, 3266,
53022 /* 158072 */ GIR_EraseRootFromParent_Done,
53023 /* 158073 */ // Label 2217: @158073
53024 /* 158073 */ GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(158147), // Rule ID 3282 //
53025 /* 158078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
53026 /* 158081 */ // MIs[0] Operand 1
53027 /* 158081 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
53028 /* 158086 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }))
53029 /* 158086 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53030 /* 158089 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53031 /* 158093 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53032 /* 158098 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53033 /* 158102 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53034 /* 158106 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53035 /* 158108 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53036 /* 158111 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53037 /* 158115 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53038 /* 158120 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
53039 /* 158127 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53040 /* 158132 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53041 /* 158137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53042 /* 158140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53043 /* 158142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53044 /* 158145 */ GIR_RootConstrainSelectedInstOperands,
53045 /* 158146 */ // GIR_Coverage, 3282,
53046 /* 158146 */ GIR_EraseRootFromParent_Done,
53047 /* 158147 */ // Label 2218: @158147
53048 /* 158147 */ GIM_Reject,
53049 /* 158148 */ // Label 2214: @158148
53050 /* 158148 */ GIM_Reject,
53051 /* 158149 */ // Label 2207: @158149
53052 /* 158149 */ GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(158458),
53053 /* 158154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
53054 /* 158157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
53055 /* 158161 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(158235), // Rule ID 3290 //
53056 /* 158166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
53057 /* 158169 */ // MIs[0] Operand 1
53058 /* 158169 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
53059 /* 158174 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }))
53060 /* 158174 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53061 /* 158177 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53062 /* 158181 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53063 /* 158186 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53064 /* 158190 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53065 /* 158194 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53066 /* 158196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53067 /* 158199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53068 /* 158203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53069 /* 158208 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
53070 /* 158215 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53071 /* 158220 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53072 /* 158225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53073 /* 158228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53074 /* 158230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53075 /* 158233 */ GIR_RootConstrainSelectedInstOperands,
53076 /* 158234 */ // GIR_Coverage, 3290,
53077 /* 158234 */ GIR_EraseRootFromParent_Done,
53078 /* 158235 */ // Label 2220: @158235
53079 /* 158235 */ GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(158309), // Rule ID 3306 //
53080 /* 158240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
53081 /* 158243 */ // MIs[0] Operand 1
53082 /* 158243 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
53083 /* 158248 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }))
53084 /* 158248 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53085 /* 158251 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53086 /* 158255 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53087 /* 158260 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53088 /* 158264 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53089 /* 158268 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53090 /* 158270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53091 /* 158273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53092 /* 158277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53093 /* 158282 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53094 /* 158289 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53095 /* 158294 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53096 /* 158299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53097 /* 158302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53098 /* 158304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53099 /* 158307 */ GIR_RootConstrainSelectedInstOperands,
53100 /* 158308 */ // GIR_Coverage, 3306,
53101 /* 158308 */ GIR_EraseRootFromParent_Done,
53102 /* 158309 */ // Label 2221: @158309
53103 /* 158309 */ GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(158383), // Rule ID 3322 //
53104 /* 158314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
53105 /* 158317 */ // MIs[0] Operand 1
53106 /* 158317 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
53107 /* 158322 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }))
53108 /* 158322 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53109 /* 158325 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53110 /* 158329 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53111 /* 158334 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53112 /* 158338 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53113 /* 158342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53114 /* 158344 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53115 /* 158347 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53116 /* 158351 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53117 /* 158356 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
53118 /* 158363 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53119 /* 158368 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53120 /* 158373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53121 /* 158376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53122 /* 158378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53123 /* 158381 */ GIR_RootConstrainSelectedInstOperands,
53124 /* 158382 */ // GIR_Coverage, 3322,
53125 /* 158382 */ GIR_EraseRootFromParent_Done,
53126 /* 158383 */ // Label 2222: @158383
53127 /* 158383 */ GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(158457), // Rule ID 3338 //
53128 /* 158388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1),
53129 /* 158391 */ // MIs[0] Operand 1
53130 /* 158391 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
53131 /* 158396 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }))
53132 /* 158396 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53133 /* 158399 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53134 /* 158403 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53135 /* 158408 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53136 /* 158412 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53137 /* 158416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53138 /* 158418 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53139 /* 158421 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53140 /* 158425 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53141 /* 158430 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
53142 /* 158437 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53143 /* 158442 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53144 /* 158447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53145 /* 158450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53146 /* 158452 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53147 /* 158455 */ GIR_RootConstrainSelectedInstOperands,
53148 /* 158456 */ // GIR_Coverage, 3338,
53149 /* 158456 */ GIR_EraseRootFromParent_Done,
53150 /* 158457 */ // Label 2223: @158457
53151 /* 158457 */ GIM_Reject,
53152 /* 158458 */ // Label 2219: @158458
53153 /* 158458 */ GIM_Reject,
53154 /* 158459 */ // Label 2208: @158459
53155 /* 158459 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2227*/ GIMT_Encode4(160108),
53156 /* 158470 */ /*GILLT_s32*//*Label 2224*/ GIMT_Encode4(158482),
53157 /* 158474 */ /*GILLT_s64*//*Label 2225*/ GIMT_Encode4(159024),
53158 /* 158478 */ /*GILLT_s128*//*Label 2226*/ GIMT_Encode4(159566),
53159 /* 158482 */ // Label 2224: @158482
53160 /* 158482 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(159023),
53161 /* 158487 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
53162 /* 158490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
53163 /* 158494 */ GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(158552), // Rule ID 4002 //
53164 /* 158499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53165 /* 158502 */ // MIs[0] Operand 1
53166 /* 158502 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
53167 /* 158507 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] })
53168 /* 158507 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53169 /* 158510 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
53170 /* 158514 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53171 /* 158519 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53172 /* 158523 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53173 /* 158527 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53174 /* 158529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53175 /* 158532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53176 /* 158534 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
53177 /* 158541 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53178 /* 158546 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53179 /* 158551 */ // GIR_Coverage, 4002,
53180 /* 158551 */ GIR_EraseRootFromParent_Done,
53181 /* 158552 */ // Label 2229: @158552
53182 /* 158552 */ GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(158610), // Rule ID 4006 //
53183 /* 158557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53184 /* 158560 */ // MIs[0] Operand 1
53185 /* 158560 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
53186 /* 158565 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
53187 /* 158565 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53188 /* 158568 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
53189 /* 158572 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53190 /* 158577 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53191 /* 158581 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53192 /* 158585 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53193 /* 158587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53194 /* 158590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53195 /* 158592 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53196 /* 158599 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53197 /* 158604 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53198 /* 158609 */ // GIR_Coverage, 4006,
53199 /* 158609 */ GIR_EraseRootFromParent_Done,
53200 /* 158610 */ // Label 2230: @158610
53201 /* 158610 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(158668), // Rule ID 4010 //
53202 /* 158615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53203 /* 158618 */ // MIs[0] Operand 1
53204 /* 158618 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
53205 /* 158623 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] })
53206 /* 158623 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53207 /* 158626 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
53208 /* 158630 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53209 /* 158635 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53210 /* 158639 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53211 /* 158643 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53212 /* 158645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53213 /* 158648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53214 /* 158650 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
53215 /* 158657 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53216 /* 158662 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53217 /* 158667 */ // GIR_Coverage, 4010,
53218 /* 158667 */ GIR_EraseRootFromParent_Done,
53219 /* 158668 */ // Label 2231: @158668
53220 /* 158668 */ GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(158726), // Rule ID 4014 //
53221 /* 158673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53222 /* 158676 */ // MIs[0] Operand 1
53223 /* 158676 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
53224 /* 158681 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] })
53225 /* 158681 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53226 /* 158684 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
53227 /* 158688 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53228 /* 158693 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53229 /* 158697 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53230 /* 158701 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53231 /* 158703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53232 /* 158706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53233 /* 158708 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
53234 /* 158715 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53235 /* 158720 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53236 /* 158725 */ // GIR_Coverage, 4014,
53237 /* 158725 */ GIR_EraseRootFromParent_Done,
53238 /* 158726 */ // Label 2232: @158726
53239 /* 158726 */ GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(158800), // Rule ID 4016 //
53240 /* 158731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53241 /* 158734 */ // MIs[0] Operand 1
53242 /* 158734 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
53243 /* 158739 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }))
53244 /* 158739 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53245 /* 158742 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
53246 /* 158746 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53247 /* 158751 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53248 /* 158755 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53249 /* 158759 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53250 /* 158761 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53251 /* 158764 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53252 /* 158768 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53253 /* 158773 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
53254 /* 158780 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53255 /* 158785 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53256 /* 158790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53257 /* 158793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53258 /* 158795 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53259 /* 158798 */ GIR_RootConstrainSelectedInstOperands,
53260 /* 158799 */ // GIR_Coverage, 4016,
53261 /* 158799 */ GIR_EraseRootFromParent_Done,
53262 /* 158800 */ // Label 2233: @158800
53263 /* 158800 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(158874), // Rule ID 4048 //
53264 /* 158805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53265 /* 158808 */ // MIs[0] Operand 1
53266 /* 158808 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
53267 /* 158813 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
53268 /* 158813 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53269 /* 158816 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
53270 /* 158820 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53271 /* 158825 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53272 /* 158829 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53273 /* 158833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53274 /* 158835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53275 /* 158838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53276 /* 158842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53277 /* 158847 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53278 /* 158854 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53279 /* 158859 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53280 /* 158864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53281 /* 158867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53282 /* 158869 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53283 /* 158872 */ GIR_RootConstrainSelectedInstOperands,
53284 /* 158873 */ // GIR_Coverage, 4048,
53285 /* 158873 */ GIR_EraseRootFromParent_Done,
53286 /* 158874 */ // Label 2234: @158874
53287 /* 158874 */ GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(158948), // Rule ID 4080 //
53288 /* 158879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53289 /* 158882 */ // MIs[0] Operand 1
53290 /* 158882 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
53291 /* 158887 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }))
53292 /* 158887 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53293 /* 158890 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
53294 /* 158894 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53295 /* 158899 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53296 /* 158903 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53297 /* 158907 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53298 /* 158909 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53299 /* 158912 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53300 /* 158916 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53301 /* 158921 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
53302 /* 158928 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53303 /* 158933 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53304 /* 158938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53305 /* 158941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53306 /* 158943 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53307 /* 158946 */ GIR_RootConstrainSelectedInstOperands,
53308 /* 158947 */ // GIR_Coverage, 4080,
53309 /* 158947 */ GIR_EraseRootFromParent_Done,
53310 /* 158948 */ // Label 2235: @158948
53311 /* 158948 */ GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(159022), // Rule ID 4112 //
53312 /* 158953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53313 /* 158956 */ // MIs[0] Operand 1
53314 /* 158956 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
53315 /* 158961 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }))
53316 /* 158961 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53317 /* 158964 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS),
53318 /* 158968 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53319 /* 158973 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53320 /* 158977 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53321 /* 158981 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53322 /* 158983 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53323 /* 158986 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53324 /* 158990 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53325 /* 158995 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
53326 /* 159002 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53327 /* 159007 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53328 /* 159012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53329 /* 159015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53330 /* 159017 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53331 /* 159020 */ GIR_RootConstrainSelectedInstOperands,
53332 /* 159021 */ // GIR_Coverage, 4112,
53333 /* 159021 */ GIR_EraseRootFromParent_Done,
53334 /* 159022 */ // Label 2236: @159022
53335 /* 159022 */ GIM_Reject,
53336 /* 159023 */ // Label 2228: @159023
53337 /* 159023 */ GIM_Reject,
53338 /* 159024 */ // Label 2225: @159024
53339 /* 159024 */ GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(159565),
53340 /* 159029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
53341 /* 159032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
53342 /* 159036 */ GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(159110), // Rule ID 4128 //
53343 /* 159041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53344 /* 159044 */ // MIs[0] Operand 1
53345 /* 159044 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
53346 /* 159049 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }))
53347 /* 159049 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53348 /* 159052 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53349 /* 159056 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53350 /* 159061 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53351 /* 159065 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53352 /* 159069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53353 /* 159071 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53354 /* 159074 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53355 /* 159078 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53356 /* 159083 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
53357 /* 159090 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53358 /* 159095 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53359 /* 159100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53360 /* 159103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53361 /* 159105 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53362 /* 159108 */ GIR_RootConstrainSelectedInstOperands,
53363 /* 159109 */ // GIR_Coverage, 4128,
53364 /* 159109 */ GIR_EraseRootFromParent_Done,
53365 /* 159110 */ // Label 2238: @159110
53366 /* 159110 */ GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(159184), // Rule ID 4160 //
53367 /* 159115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53368 /* 159118 */ // MIs[0] Operand 1
53369 /* 159118 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
53370 /* 159123 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
53371 /* 159123 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53372 /* 159126 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53373 /* 159130 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53374 /* 159135 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53375 /* 159139 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53376 /* 159143 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53377 /* 159145 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53378 /* 159148 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53379 /* 159152 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53380 /* 159157 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53381 /* 159164 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53382 /* 159169 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53383 /* 159174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53384 /* 159177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53385 /* 159179 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53386 /* 159182 */ GIR_RootConstrainSelectedInstOperands,
53387 /* 159183 */ // GIR_Coverage, 4160,
53388 /* 159183 */ GIR_EraseRootFromParent_Done,
53389 /* 159184 */ // Label 2239: @159184
53390 /* 159184 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(159258), // Rule ID 4192 //
53391 /* 159189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53392 /* 159192 */ // MIs[0] Operand 1
53393 /* 159192 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
53394 /* 159197 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }))
53395 /* 159197 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53396 /* 159200 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53397 /* 159204 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53398 /* 159209 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53399 /* 159213 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53400 /* 159217 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53401 /* 159219 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53402 /* 159222 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53403 /* 159226 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53404 /* 159231 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
53405 /* 159238 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53406 /* 159243 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53407 /* 159248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53408 /* 159251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53409 /* 159253 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53410 /* 159256 */ GIR_RootConstrainSelectedInstOperands,
53411 /* 159257 */ // GIR_Coverage, 4192,
53412 /* 159257 */ GIR_EraseRootFromParent_Done,
53413 /* 159258 */ // Label 2240: @159258
53414 /* 159258 */ GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(159332), // Rule ID 4224 //
53415 /* 159263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53416 /* 159266 */ // MIs[0] Operand 1
53417 /* 159266 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
53418 /* 159271 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }))
53419 /* 159271 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53420 /* 159274 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53421 /* 159278 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53422 /* 159283 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53423 /* 159287 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53424 /* 159291 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53425 /* 159293 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53426 /* 159296 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53427 /* 159300 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53428 /* 159305 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
53429 /* 159312 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53430 /* 159317 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53431 /* 159322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53432 /* 159325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53433 /* 159327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53434 /* 159330 */ GIR_RootConstrainSelectedInstOperands,
53435 /* 159331 */ // GIR_Coverage, 4224,
53436 /* 159331 */ GIR_EraseRootFromParent_Done,
53437 /* 159332 */ // Label 2241: @159332
53438 /* 159332 */ GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(159390), // Rule ID 4240 //
53439 /* 159337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53440 /* 159340 */ // MIs[0] Operand 1
53441 /* 159340 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
53442 /* 159345 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] })
53443 /* 159345 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53444 /* 159348 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53445 /* 159352 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53446 /* 159357 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53447 /* 159361 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53448 /* 159365 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53449 /* 159367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53450 /* 159370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53451 /* 159372 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
53452 /* 159379 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53453 /* 159384 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53454 /* 159389 */ // GIR_Coverage, 4240,
53455 /* 159389 */ GIR_EraseRootFromParent_Done,
53456 /* 159390 */ // Label 2242: @159390
53457 /* 159390 */ GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(159448), // Rule ID 4244 //
53458 /* 159395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53459 /* 159398 */ // MIs[0] Operand 1
53460 /* 159398 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
53461 /* 159403 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
53462 /* 159403 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53463 /* 159406 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53464 /* 159410 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53465 /* 159415 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53466 /* 159419 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53467 /* 159423 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53468 /* 159425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53469 /* 159428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53470 /* 159430 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53471 /* 159437 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53472 /* 159442 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53473 /* 159447 */ // GIR_Coverage, 4244,
53474 /* 159447 */ GIR_EraseRootFromParent_Done,
53475 /* 159448 */ // Label 2243: @159448
53476 /* 159448 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(159506), // Rule ID 4248 //
53477 /* 159453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53478 /* 159456 */ // MIs[0] Operand 1
53479 /* 159456 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
53480 /* 159461 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] })
53481 /* 159461 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53482 /* 159464 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53483 /* 159468 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53484 /* 159473 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53485 /* 159477 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53486 /* 159481 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53487 /* 159483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53488 /* 159486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53489 /* 159488 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
53490 /* 159495 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53491 /* 159500 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53492 /* 159505 */ // GIR_Coverage, 4248,
53493 /* 159505 */ GIR_EraseRootFromParent_Done,
53494 /* 159506 */ // Label 2244: @159506
53495 /* 159506 */ GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(159564), // Rule ID 4252 //
53496 /* 159511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53497 /* 159514 */ // MIs[0] Operand 1
53498 /* 159514 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
53499 /* 159519 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] })
53500 /* 159519 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53501 /* 159522 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD),
53502 /* 159526 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53503 /* 159531 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53504 /* 159535 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53505 /* 159539 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53506 /* 159541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53507 /* 159544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53508 /* 159546 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
53509 /* 159553 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53510 /* 159558 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53511 /* 159563 */ // GIR_Coverage, 4252,
53512 /* 159563 */ GIR_EraseRootFromParent_Done,
53513 /* 159564 */ // Label 2245: @159564
53514 /* 159564 */ GIM_Reject,
53515 /* 159565 */ // Label 2237: @159565
53516 /* 159565 */ GIM_Reject,
53517 /* 159566 */ // Label 2226: @159566
53518 /* 159566 */ GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(160107),
53519 /* 159571 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
53520 /* 159574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
53521 /* 159578 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(159652), // Rule ID 4254 //
53522 /* 159583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53523 /* 159586 */ // MIs[0] Operand 1
53524 /* 159586 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
53525 /* 159591 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }))
53526 /* 159591 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53527 /* 159594 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53528 /* 159598 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53529 /* 159603 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53530 /* 159607 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53531 /* 159611 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53532 /* 159613 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53533 /* 159616 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53534 /* 159620 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53535 /* 159625 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
53536 /* 159632 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53537 /* 159637 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53538 /* 159642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53539 /* 159645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53540 /* 159647 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53541 /* 159650 */ GIR_RootConstrainSelectedInstOperands,
53542 /* 159651 */ // GIR_Coverage, 4254,
53543 /* 159651 */ GIR_EraseRootFromParent_Done,
53544 /* 159652 */ // Label 2247: @159652
53545 /* 159652 */ GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(159726), // Rule ID 4286 //
53546 /* 159657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53547 /* 159660 */ // MIs[0] Operand 1
53548 /* 159660 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
53549 /* 159665 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }))
53550 /* 159665 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53551 /* 159668 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53552 /* 159672 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53553 /* 159677 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53554 /* 159681 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53555 /* 159685 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53556 /* 159687 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53557 /* 159690 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53558 /* 159694 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53559 /* 159699 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53560 /* 159706 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53561 /* 159711 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53562 /* 159716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53563 /* 159719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53564 /* 159721 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53565 /* 159724 */ GIR_RootConstrainSelectedInstOperands,
53566 /* 159725 */ // GIR_Coverage, 4286,
53567 /* 159725 */ GIR_EraseRootFromParent_Done,
53568 /* 159726 */ // Label 2248: @159726
53569 /* 159726 */ GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(159800), // Rule ID 4318 //
53570 /* 159731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53571 /* 159734 */ // MIs[0] Operand 1
53572 /* 159734 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
53573 /* 159739 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }))
53574 /* 159739 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53575 /* 159742 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53576 /* 159746 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53577 /* 159751 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53578 /* 159755 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53579 /* 159759 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53580 /* 159761 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53581 /* 159764 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53582 /* 159768 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53583 /* 159773 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
53584 /* 159780 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53585 /* 159785 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53586 /* 159790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53587 /* 159793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53588 /* 159795 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53589 /* 159798 */ GIR_RootConstrainSelectedInstOperands,
53590 /* 159799 */ // GIR_Coverage, 4318,
53591 /* 159799 */ GIR_EraseRootFromParent_Done,
53592 /* 159800 */ // Label 2249: @159800
53593 /* 159800 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(159874), // Rule ID 4350 //
53594 /* 159805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53595 /* 159808 */ // MIs[0] Operand 1
53596 /* 159808 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
53597 /* 159813 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }))
53598 /* 159813 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53599 /* 159816 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53600 /* 159820 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53601 /* 159825 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53602 /* 159829 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53603 /* 159833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53604 /* 159835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53605 /* 159838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53606 /* 159842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53607 /* 159847 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
53608 /* 159854 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53609 /* 159859 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53610 /* 159864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53611 /* 159867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53612 /* 159869 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53613 /* 159872 */ GIR_RootConstrainSelectedInstOperands,
53614 /* 159873 */ // GIR_Coverage, 4350,
53615 /* 159873 */ GIR_EraseRootFromParent_Done,
53616 /* 159874 */ // Label 2250: @159874
53617 /* 159874 */ GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(159932), // Rule ID 4366 //
53618 /* 159879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53619 /* 159882 */ // MIs[0] Operand 1
53620 /* 159882 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
53621 /* 159887 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] })
53622 /* 159887 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53623 /* 159890 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53624 /* 159894 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53625 /* 159899 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53626 /* 159903 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53627 /* 159907 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53628 /* 159909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53629 /* 159912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53630 /* 159914 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt),
53631 /* 159921 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53632 /* 159926 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53633 /* 159931 */ // GIR_Coverage, 4366,
53634 /* 159931 */ GIR_EraseRootFromParent_Done,
53635 /* 159932 */ // Label 2251: @159932
53636 /* 159932 */ GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(159990), // Rule ID 4370 //
53637 /* 159937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53638 /* 159940 */ // MIs[0] Operand 1
53639 /* 159940 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
53640 /* 159945 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] })
53641 /* 159945 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53642 /* 159948 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53643 /* 159952 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53644 /* 159957 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53645 /* 159961 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53646 /* 159965 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53647 /* 159967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53648 /* 159970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53649 /* 159972 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53650 /* 159979 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53651 /* 159984 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53652 /* 159989 */ // GIR_Coverage, 4370,
53653 /* 159989 */ GIR_EraseRootFromParent_Done,
53654 /* 159990 */ // Label 2252: @159990
53655 /* 159990 */ GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(160048), // Rule ID 4374 //
53656 /* 159995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53657 /* 159998 */ // MIs[0] Operand 1
53658 /* 159998 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
53659 /* 160003 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] })
53660 /* 160003 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53661 /* 160006 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53662 /* 160010 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53663 /* 160015 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53664 /* 160019 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53665 /* 160023 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53666 /* 160025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53667 /* 160028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53668 /* 160030 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq),
53669 /* 160037 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53670 /* 160042 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53671 /* 160047 */ // GIR_Coverage, 4374,
53672 /* 160047 */ GIR_EraseRootFromParent_Done,
53673 /* 160048 */ // Label 2253: @160048
53674 /* 160048 */ GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(160106), // Rule ID 4378 //
53675 /* 160053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
53676 /* 160056 */ // MIs[0] Operand 1
53677 /* 160056 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
53678 /* 160061 */ // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] })
53679 /* 160061 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53680 /* 160064 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP),
53681 /* 160068 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53682 /* 160073 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53683 /* 160077 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53684 /* 160081 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53685 /* 160083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53686 /* 160086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53687 /* 160088 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un),
53688 /* 160095 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53689 /* 160100 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53690 /* 160105 */ // GIR_Coverage, 4378,
53691 /* 160105 */ GIR_EraseRootFromParent_Done,
53692 /* 160106 */ // Label 2254: @160106
53693 /* 160106 */ GIM_Reject,
53694 /* 160107 */ // Label 2246: @160107
53695 /* 160107 */ GIM_Reject,
53696 /* 160108 */ // Label 2227: @160108
53697 /* 160108 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2257*/ GIMT_Encode4(160947),
53698 /* 160119 */ /*GILLT_s32*//*Label 2255*/ GIMT_Encode4(160127),
53699 /* 160123 */ /*GILLT_s64*//*Label 2256*/ GIMT_Encode4(160537),
53700 /* 160127 */ // Label 2255: @160127
53701 /* 160127 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(160536),
53702 /* 160132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
53703 /* 160135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
53704 /* 160139 */ GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(160197), // Rule ID 4569 //
53705 /* 160144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53706 /* 160147 */ // MIs[0] Operand 1
53707 /* 160147 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
53708 /* 160152 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
53709 /* 160152 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53710 /* 160155 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
53711 /* 160159 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53712 /* 160164 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53713 /* 160168 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53714 /* 160172 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53715 /* 160174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53716 /* 160177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53717 /* 160179 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53718 /* 160186 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53719 /* 160191 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53720 /* 160196 */ // GIR_Coverage, 4569,
53721 /* 160196 */ GIR_EraseRootFromParent_Done,
53722 /* 160197 */ // Label 2259: @160197
53723 /* 160197 */ GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(160255), // Rule ID 4573 //
53724 /* 160202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53725 /* 160205 */ // MIs[0] Operand 1
53726 /* 160205 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
53727 /* 160210 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
53728 /* 160210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53729 /* 160213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
53730 /* 160217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53731 /* 160222 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53732 /* 160226 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53733 /* 160230 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53734 /* 160232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53735 /* 160235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53736 /* 160237 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53737 /* 160244 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53738 /* 160249 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53739 /* 160254 */ // GIR_Coverage, 4573,
53740 /* 160254 */ GIR_EraseRootFromParent_Done,
53741 /* 160255 */ // Label 2260: @160255
53742 /* 160255 */ GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(160313), // Rule ID 4577 //
53743 /* 160260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53744 /* 160263 */ // MIs[0] Operand 1
53745 /* 160263 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
53746 /* 160268 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })
53747 /* 160268 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53748 /* 160271 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
53749 /* 160275 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53750 /* 160280 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53751 /* 160284 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53752 /* 160288 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53753 /* 160290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53754 /* 160293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53755 /* 160295 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53756 /* 160302 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53757 /* 160307 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53758 /* 160312 */ // GIR_Coverage, 4577,
53759 /* 160312 */ GIR_EraseRootFromParent_Done,
53760 /* 160313 */ // Label 2261: @160313
53761 /* 160313 */ GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(160387), // Rule ID 4581 //
53762 /* 160318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53763 /* 160321 */ // MIs[0] Operand 1
53764 /* 160321 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
53765 /* 160326 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
53766 /* 160326 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53767 /* 160329 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT),
53768 /* 160333 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53769 /* 160338 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53770 /* 160342 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53771 /* 160346 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53772 /* 160348 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53773 /* 160351 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53774 /* 160355 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53775 /* 160360 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53776 /* 160367 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53777 /* 160372 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53778 /* 160377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53779 /* 160380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53780 /* 160382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53781 /* 160385 */ GIR_RootConstrainSelectedInstOperands,
53782 /* 160386 */ // GIR_Coverage, 4581,
53783 /* 160386 */ GIR_EraseRootFromParent_Done,
53784 /* 160387 */ // Label 2262: @160387
53785 /* 160387 */ GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(160461), // Rule ID 4613 //
53786 /* 160392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53787 /* 160395 */ // MIs[0] Operand 1
53788 /* 160395 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
53789 /* 160400 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
53790 /* 160400 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53791 /* 160403 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT),
53792 /* 160407 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53793 /* 160412 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53794 /* 160416 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53795 /* 160420 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53796 /* 160422 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53797 /* 160425 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53798 /* 160429 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53799 /* 160434 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53800 /* 160441 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53801 /* 160446 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53802 /* 160451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53803 /* 160454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53804 /* 160456 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53805 /* 160459 */ GIR_RootConstrainSelectedInstOperands,
53806 /* 160460 */ // GIR_Coverage, 4613,
53807 /* 160460 */ GIR_EraseRootFromParent_Done,
53808 /* 160461 */ // Label 2263: @160461
53809 /* 160461 */ GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(160535), // Rule ID 4645 //
53810 /* 160466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53811 /* 160469 */ // MIs[0] Operand 1
53812 /* 160469 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
53813 /* 160474 */ // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }))
53814 /* 160474 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53815 /* 160477 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ),
53816 /* 160481 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53817 /* 160486 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53818 /* 160490 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53819 /* 160494 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53820 /* 160496 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53821 /* 160499 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53822 /* 160503 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53823 /* 160508 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53824 /* 160515 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53825 /* 160520 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53826 /* 160525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53827 /* 160528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53828 /* 160530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53829 /* 160533 */ GIR_RootConstrainSelectedInstOperands,
53830 /* 160534 */ // GIR_Coverage, 4645,
53831 /* 160534 */ GIR_EraseRootFromParent_Done,
53832 /* 160535 */ // Label 2264: @160535
53833 /* 160535 */ GIM_Reject,
53834 /* 160536 */ // Label 2258: @160536
53835 /* 160536 */ GIM_Reject,
53836 /* 160537 */ // Label 2256: @160537
53837 /* 160537 */ GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(160946),
53838 /* 160542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
53839 /* 160545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
53840 /* 160549 */ GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(160607), // Rule ID 4677 //
53841 /* 160554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53842 /* 160557 */ // MIs[0] Operand 1
53843 /* 160557 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
53844 /* 160562 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
53845 /* 160562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53846 /* 160565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
53847 /* 160569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53848 /* 160574 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53849 /* 160578 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53850 /* 160582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53851 /* 160584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53852 /* 160587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53853 /* 160589 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53854 /* 160596 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53855 /* 160601 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53856 /* 160606 */ // GIR_Coverage, 4677,
53857 /* 160606 */ GIR_EraseRootFromParent_Done,
53858 /* 160607 */ // Label 2266: @160607
53859 /* 160607 */ GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(160665), // Rule ID 4681 //
53860 /* 160612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53861 /* 160615 */ // MIs[0] Operand 1
53862 /* 160615 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
53863 /* 160620 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
53864 /* 160620 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53865 /* 160623 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
53866 /* 160627 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53867 /* 160632 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53868 /* 160636 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53869 /* 160640 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53870 /* 160642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53871 /* 160645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53872 /* 160647 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53873 /* 160654 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53874 /* 160659 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53875 /* 160664 */ // GIR_Coverage, 4681,
53876 /* 160664 */ GIR_EraseRootFromParent_Done,
53877 /* 160665 */ // Label 2267: @160665
53878 /* 160665 */ GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(160723), // Rule ID 4685 //
53879 /* 160670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53880 /* 160673 */ // MIs[0] Operand 1
53881 /* 160673 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
53882 /* 160678 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })
53883 /* 160678 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
53884 /* 160681 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
53885 /* 160685 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53886 /* 160690 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1
53887 /* 160694 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2
53888 /* 160698 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
53889 /* 160700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53890 /* 160703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
53891 /* 160705 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53892 /* 160712 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53893 /* 160717 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53894 /* 160722 */ // GIR_Coverage, 4685,
53895 /* 160722 */ GIR_EraseRootFromParent_Done,
53896 /* 160723 */ // Label 2268: @160723
53897 /* 160723 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(160797), // Rule ID 4689 //
53898 /* 160728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53899 /* 160731 */ // MIs[0] Operand 1
53900 /* 160731 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
53901 /* 160736 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
53902 /* 160736 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53903 /* 160739 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT),
53904 /* 160743 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53905 /* 160748 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53906 /* 160752 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53907 /* 160756 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53908 /* 160758 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53909 /* 160761 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53910 /* 160765 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53911 /* 160770 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53912 /* 160777 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53913 /* 160782 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53914 /* 160787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53915 /* 160790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53916 /* 160792 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53917 /* 160795 */ GIR_RootConstrainSelectedInstOperands,
53918 /* 160796 */ // GIR_Coverage, 4689,
53919 /* 160796 */ GIR_EraseRootFromParent_Done,
53920 /* 160797 */ // Label 2269: @160797
53921 /* 160797 */ GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(160871), // Rule ID 4721 //
53922 /* 160802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53923 /* 160805 */ // MIs[0] Operand 1
53924 /* 160805 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
53925 /* 160810 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
53926 /* 160810 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53927 /* 160813 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT),
53928 /* 160817 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53929 /* 160822 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53930 /* 160826 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53931 /* 160830 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53932 /* 160832 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53933 /* 160835 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53934 /* 160839 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53935 /* 160844 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53936 /* 160851 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53937 /* 160856 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53938 /* 160861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53939 /* 160864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53940 /* 160866 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53941 /* 160869 */ GIR_RootConstrainSelectedInstOperands,
53942 /* 160870 */ // GIR_Coverage, 4721,
53943 /* 160870 */ GIR_EraseRootFromParent_Done,
53944 /* 160871 */ // Label 2270: @160871
53945 /* 160871 */ GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(160945), // Rule ID 4753 //
53946 /* 160876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
53947 /* 160879 */ // MIs[0] Operand 1
53948 /* 160879 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
53949 /* 160884 */ // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }))
53950 /* 160884 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
53951 /* 160887 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ),
53952 /* 160891 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53953 /* 160896 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1
53954 /* 160900 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2
53955 /* 160904 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
53956 /* 160906 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
53957 /* 160909 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
53958 /* 160913 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53959 /* 160918 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt),
53960 /* 160925 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID),
53961 /* 160930 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID),
53962 /* 160935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53963 /* 160938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
53964 /* 160940 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
53965 /* 160943 */ GIR_RootConstrainSelectedInstOperands,
53966 /* 160944 */ // GIR_Coverage, 4753,
53967 /* 160944 */ GIR_EraseRootFromParent_Done,
53968 /* 160945 */ // Label 2271: @160945
53969 /* 160945 */ GIM_Reject,
53970 /* 160946 */ // Label 2265: @160946
53971 /* 160946 */ GIM_Reject,
53972 /* 160947 */ // Label 2257: @160947
53973 /* 160947 */ GIM_Reject,
53974 /* 160948 */ // Label 2204: @160948
53975 /* 160948 */ GIM_Reject,
53976 /* 160949 */ // Label 33: @160949
53977 /* 160949 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 2280*/ GIMT_Encode4(162072),
53978 /* 160960 */ /*GILLT_s1*//*Label 2272*/ GIMT_Encode4(160992),
53979 /* 160964 */ /*GILLT_s32*//*Label 2273*/ GIMT_Encode4(161085),
53980 /* 160968 */ /*GILLT_s64*//*Label 2274*/ GIMT_Encode4(161174),
53981 /* 160972 */ /*GILLT_s128*//*Label 2275*/ GIMT_Encode4(161263),
53982 /* 160976 */ /*GILLT_v2s64*//*Label 2276*/ GIMT_Encode4(161447),
53983 /* 160980 */ /*GILLT_v4s32*//*Label 2277*/ GIMT_Encode4(161612),
53984 /* 160984 */ /*GILLT_v8s16*//*Label 2278*/ GIMT_Encode4(161774),
53985 /* 160988 */ /*GILLT_v16s8*//*Label 2279*/ GIMT_Encode4(161923),
53986 /* 160992 */ // Label 2272: @160992
53987 /* 160992 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(161084), // Rule ID 4784 //
53988 /* 160997 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
53989 /* 161000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
53990 /* 161003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s1,
53991 /* 161006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID),
53992 /* 161010 */ // (select:{ *:[i1] } i1:{ *:[i1] }:$cond, i1:{ *:[i1] }:$tval, i1:{ *:[i1] }:$fval) => (CROR:{ *:[i1] } (CRAND:{ *:[i1] } ?:{ *:[i1] }:$cond, ?:{ *:[i1] }:$tval), (CRAND:{ *:[i1] } (CRNOT:{ *:[i1] } ?:{ *:[i1] }:$cond), ?:{ *:[i1] }:$fval))
53993 /* 161010 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1,
53994 /* 161013 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CRNOT),
53995 /* 161017 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
53996 /* 161022 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // cond
53997 /* 161026 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
53998 /* 161028 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
53999 /* 161031 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CRAND),
54000 /* 161035 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54001 /* 161040 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
54002 /* 161043 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // fval
54003 /* 161047 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
54004 /* 161049 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
54005 /* 161052 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CRAND),
54006 /* 161056 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54007 /* 161061 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
54008 /* 161065 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // tval
54009 /* 161069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
54010 /* 161071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CROR),
54011 /* 161074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD]
54012 /* 161076 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
54013 /* 161079 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
54014 /* 161082 */ GIR_RootConstrainSelectedInstOperands,
54015 /* 161083 */ // GIR_Coverage, 4784,
54016 /* 161083 */ GIR_EraseRootFromParent_Done,
54017 /* 161084 */ // Label 2281: @161084
54018 /* 161084 */ GIM_Reject,
54019 /* 161085 */ // Label 2273: @161085
54020 /* 161085 */ GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(161173),
54021 /* 161090 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
54022 /* 161093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
54023 /* 161096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
54024 /* 161099 */ GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(161118), // Rule ID 1055 //
54025 /* 161104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54026 /* 161107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
54027 /* 161111 */ // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_VSSRC:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F)
54028 /* 161111 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_VSSRC),
54029 /* 161116 */ GIR_RootConstrainSelectedInstOperands,
54030 /* 161117 */ // GIR_Coverage, 1055,
54031 /* 161117 */ GIR_Done,
54032 /* 161118 */ // Label 2283: @161118
54033 /* 161118 */ GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(161134), // Rule ID 5 //
54034 /* 161123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
54035 /* 161127 */ // (select:{ *:[i32] } i1:{ *:[i1] }:$cond, i32:{ *:[i32] }:$T, i32:{ *:[i32] }:$F) => (SELECT_I4:{ *:[i32] } i1:{ *:[i1] }:$cond, i32:{ *:[i32] }:$T, i32:{ *:[i32] }:$F)
54036 /* 161127 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4),
54037 /* 161132 */ GIR_RootConstrainSelectedInstOperands,
54038 /* 161133 */ // GIR_Coverage, 5,
54039 /* 161133 */ GIR_Done,
54040 /* 161134 */ // Label 2284: @161134
54041 /* 161134 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(161153), // Rule ID 7 //
54042 /* 161139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
54043 /* 161142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
54044 /* 161146 */ // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_F4:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F)
54045 /* 161146 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_F4),
54046 /* 161151 */ GIR_RootConstrainSelectedInstOperands,
54047 /* 161152 */ // GIR_Coverage, 7,
54048 /* 161152 */ GIR_Done,
54049 /* 161153 */ // Label 2285: @161153
54050 /* 161153 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(161172), // Rule ID 610 //
54051 /* 161158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
54052 /* 161161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
54053 /* 161165 */ // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_SPE4:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F)
54054 /* 161165 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_SPE4),
54055 /* 161170 */ GIR_RootConstrainSelectedInstOperands,
54056 /* 161171 */ // GIR_Coverage, 610,
54057 /* 161171 */ GIR_Done,
54058 /* 161172 */ // Label 2286: @161172
54059 /* 161172 */ GIM_Reject,
54060 /* 161173 */ // Label 2282: @161173
54061 /* 161173 */ GIM_Reject,
54062 /* 161174 */ // Label 2274: @161174
54063 /* 161174 */ GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(161262),
54064 /* 161179 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
54065 /* 161182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
54066 /* 161185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
54067 /* 161188 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(161207), // Rule ID 1054 //
54068 /* 161193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54069 /* 161196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
54070 /* 161200 */ // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_VSFRC:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F)
54071 /* 161200 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_VSFRC),
54072 /* 161205 */ GIR_RootConstrainSelectedInstOperands,
54073 /* 161206 */ // GIR_Coverage, 1054,
54074 /* 161206 */ GIR_Done,
54075 /* 161207 */ // Label 2288: @161207
54076 /* 161207 */ GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(161223), // Rule ID 6 //
54077 /* 161212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
54078 /* 161216 */ // (select:{ *:[i64] } i1:{ *:[i1] }:$cond, i64:{ *:[i64] }:$T, i64:{ *:[i64] }:$F) => (SELECT_I8:{ *:[i64] } i1:{ *:[i1] }:$cond, i64:{ *:[i64] }:$T, i64:{ *:[i64] }:$F)
54079 /* 161216 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8),
54080 /* 161221 */ GIR_RootConstrainSelectedInstOperands,
54081 /* 161222 */ // GIR_Coverage, 6,
54082 /* 161222 */ GIR_Done,
54083 /* 161223 */ // Label 2289: @161223
54084 /* 161223 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(161242), // Rule ID 8 //
54085 /* 161228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
54086 /* 161231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
54087 /* 161235 */ // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_F8:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F)
54088 /* 161235 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_F8),
54089 /* 161240 */ GIR_RootConstrainSelectedInstOperands,
54090 /* 161241 */ // GIR_Coverage, 8,
54091 /* 161241 */ GIR_Done,
54092 /* 161242 */ // Label 2290: @161242
54093 /* 161242 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(161261), // Rule ID 611 //
54094 /* 161247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
54095 /* 161250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
54096 /* 161254 */ // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_SPE:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F)
54097 /* 161254 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_SPE),
54098 /* 161259 */ GIR_RootConstrainSelectedInstOperands,
54099 /* 161260 */ // GIR_Coverage, 611,
54100 /* 161260 */ GIR_Done,
54101 /* 161261 */ // Label 2291: @161261
54102 /* 161261 */ GIM_Reject,
54103 /* 161262 */ // Label 2287: @161262
54104 /* 161262 */ GIM_Reject,
54105 /* 161263 */ // Label 2275: @161263
54106 /* 161263 */ GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(161384), // Rule ID 1675 //
54107 /* 161268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54108 /* 161271 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
54109 /* 161274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
54110 /* 161277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
54111 /* 161280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54112 /* 161284 */ // (vselect:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (COPY_TO_REGCLASS:{ *:[v1i128] } (XXSEL:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$vC, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$vB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$vA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] })
54113 /* 161284 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
54114 /* 161287 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54115 /* 161291 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54116 /* 161296 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // vA
54117 /* 161300 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54118 /* 161305 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
54119 /* 161308 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54120 /* 161312 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54121 /* 161317 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // vB
54122 /* 161321 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54123 /* 161326 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
54124 /* 161329 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54125 /* 161333 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54126 /* 161338 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // vC
54127 /* 161342 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54128 /* 161347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
54129 /* 161350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
54130 /* 161354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54131 /* 161359 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
54132 /* 161362 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
54133 /* 161365 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
54134 /* 161368 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
54135 /* 161370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54136 /* 161373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
54137 /* 161375 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
54138 /* 161378 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
54139 /* 161383 */ // GIR_Coverage, 1675,
54140 /* 161383 */ GIR_EraseRootFromParent_Done,
54141 /* 161384 */ // Label 2292: @161384
54142 /* 161384 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(161412), // Rule ID 9 //
54143 /* 161389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
54144 /* 161392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
54145 /* 161395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
54146 /* 161398 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
54147 /* 161401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54148 /* 161405 */ // (select:{ *:[f128] } i1:{ *:[i1] }:$cond, f128:{ *:[f128] }:$T, f128:{ *:[f128] }:$F) => (SELECT_F16:{ *:[f128] } i1:{ *:[i1] }:$cond, f128:{ *:[f128] }:$T, f128:{ *:[f128] }:$F)
54149 /* 161405 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_F16),
54150 /* 161410 */ GIR_RootConstrainSelectedInstOperands,
54151 /* 161411 */ // GIR_Coverage, 9,
54152 /* 161411 */ GIR_Done,
54153 /* 161412 */ // Label 2293: @161412
54154 /* 161412 */ GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(161446), // Rule ID 1429 //
54155 /* 161417 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54156 /* 161420 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
54157 /* 161423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
54158 /* 161426 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
54159 /* 161429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54160 /* 161433 */ // (vselect:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (VSEL:{ *:[v1i128] } ?:{ *:[v1i128] }:$vC, ?:{ *:[v1i128] }:$vB, ?:{ *:[v1i128] }:$vA)
54161 /* 161433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL),
54162 /* 161436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
54163 /* 161438 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54164 /* 161440 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54165 /* 161442 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54166 /* 161444 */ GIR_RootConstrainSelectedInstOperands,
54167 /* 161445 */ // GIR_Coverage, 1429,
54168 /* 161445 */ GIR_EraseRootFromParent_Done,
54169 /* 161446 */ // Label 2294: @161446
54170 /* 161446 */ GIM_Reject,
54171 /* 161447 */ // Label 2276: @161447
54172 /* 161447 */ GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(161475), // Rule ID 1053 //
54173 /* 161452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54174 /* 161455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
54175 /* 161458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54176 /* 161461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54177 /* 161464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54178 /* 161468 */ // (select:{ *:[v2f64] } i1:{ *:[i1] }:$cond, v2f64:{ *:[v2f64] }:$T, v2f64:{ *:[v2f64] }:$F) => (SELECT_VSRC:{ *:[v2f64] } i1:{ *:[i1] }:$cond, v2f64:{ *:[v2f64] }:$T, v2f64:{ *:[v2f64] }:$F)
54179 /* 161468 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_VSRC),
54180 /* 161473 */ GIR_RootConstrainSelectedInstOperands,
54181 /* 161474 */ // GIR_Coverage, 1053,
54182 /* 161474 */ GIR_Done,
54183 /* 161475 */ // Label 2295: @161475
54184 /* 161475 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(161509), // Rule ID 1672 //
54185 /* 161480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54186 /* 161483 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
54187 /* 161486 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54188 /* 161489 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54189 /* 161492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54190 /* 161496 */ // (vselect:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v2i64:{ *:[v2i64] }:$vC) => (XXSEL:{ *:[v2i64] } ?:{ *:[v2i64] }:$vC, ?:{ *:[v2i64] }:$vB, ?:{ *:[v2i64] }:$vA)
54191 /* 161496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
54192 /* 161499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
54193 /* 161501 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54194 /* 161503 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54195 /* 161505 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54196 /* 161507 */ GIR_RootConstrainSelectedInstOperands,
54197 /* 161508 */ // GIR_Coverage, 1672,
54198 /* 161508 */ GIR_EraseRootFromParent_Done,
54199 /* 161509 */ // Label 2296: @161509
54200 /* 161509 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(161543), // Rule ID 1674 //
54201 /* 161514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54202 /* 161517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
54203 /* 161520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54204 /* 161523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54205 /* 161526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54206 /* 161530 */ // (vselect:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$vA, v2f64:{ *:[v2f64] }:$vB, v2f64:{ *:[v2f64] }:$vC) => (XXSEL:{ *:[v2f64] } ?:{ *:[v2f64] }:$vC, ?:{ *:[v2f64] }:$vB, ?:{ *:[v2i64] }:$vA)
54207 /* 161530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
54208 /* 161533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
54209 /* 161535 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54210 /* 161537 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54211 /* 161539 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54212 /* 161541 */ GIR_RootConstrainSelectedInstOperands,
54213 /* 161542 */ // GIR_Coverage, 1674,
54214 /* 161542 */ GIR_EraseRootFromParent_Done,
54215 /* 161543 */ // Label 2297: @161543
54216 /* 161543 */ GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(161577), // Rule ID 1426 //
54217 /* 161548 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54218 /* 161551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
54219 /* 161554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54220 /* 161557 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54221 /* 161560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54222 /* 161564 */ // (vselect:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v2i64:{ *:[v2i64] }:$vC) => (VSEL:{ *:[v2i64] } ?:{ *:[v2i64] }:$vC, ?:{ *:[v2i64] }:$vB, ?:{ *:[v2i64] }:$vA)
54223 /* 161564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL),
54224 /* 161567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
54225 /* 161569 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54226 /* 161571 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54227 /* 161573 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54228 /* 161575 */ GIR_RootConstrainSelectedInstOperands,
54229 /* 161576 */ // GIR_Coverage, 1426,
54230 /* 161576 */ GIR_EraseRootFromParent_Done,
54231 /* 161577 */ // Label 2298: @161577
54232 /* 161577 */ GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(161611), // Rule ID 1428 //
54233 /* 161582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54234 /* 161585 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
54235 /* 161588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54236 /* 161591 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54237 /* 161594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54238 /* 161598 */ // (vselect:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$vA, v2f64:{ *:[v2f64] }:$vB, v2f64:{ *:[v2f64] }:$vC) => (VSEL:{ *:[v2f64] } ?:{ *:[v2f64] }:$vC, ?:{ *:[v2f64] }:$vB, ?:{ *:[v2i64] }:$vA)
54239 /* 161598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL),
54240 /* 161601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
54241 /* 161603 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54242 /* 161605 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54243 /* 161607 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54244 /* 161609 */ GIR_RootConstrainSelectedInstOperands,
54245 /* 161610 */ // GIR_Coverage, 1428,
54246 /* 161610 */ GIR_EraseRootFromParent_Done,
54247 /* 161611 */ // Label 2299: @161611
54248 /* 161611 */ GIM_Reject,
54249 /* 161612 */ // Label 2277: @161612
54250 /* 161612 */ GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(161646), // Rule ID 1671 //
54251 /* 161617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54252 /* 161620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54253 /* 161623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54254 /* 161626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54255 /* 161629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54256 /* 161633 */ // (vselect:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vC, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vA)
54257 /* 161633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
54258 /* 161636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
54259 /* 161638 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54260 /* 161640 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54261 /* 161642 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54262 /* 161644 */ GIR_RootConstrainSelectedInstOperands,
54263 /* 161645 */ // GIR_Coverage, 1671,
54264 /* 161645 */ GIR_EraseRootFromParent_Done,
54265 /* 161646 */ // Label 2300: @161646
54266 /* 161646 */ GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(161680), // Rule ID 1673 //
54267 /* 161651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54268 /* 161654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54269 /* 161657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54270 /* 161660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54271 /* 161663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54272 /* 161667 */ // (vselect:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vA, v4f32:{ *:[v4f32] }:$vB, v4f32:{ *:[v4f32] }:$vC) => (XXSEL:{ *:[v4f32] } ?:{ *:[v4f32] }:$vC, ?:{ *:[v4f32] }:$vB, ?:{ *:[v4i32] }:$vA)
54273 /* 161667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
54274 /* 161670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
54275 /* 161672 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54276 /* 161674 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54277 /* 161676 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54278 /* 161678 */ GIR_RootConstrainSelectedInstOperands,
54279 /* 161679 */ // GIR_Coverage, 1673,
54280 /* 161679 */ GIR_EraseRootFromParent_Done,
54281 /* 161680 */ // Label 2301: @161680
54282 /* 161680 */ GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(161705), // Rule ID 10 //
54283 /* 161685 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
54284 /* 161688 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54285 /* 161691 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54286 /* 161694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54287 /* 161698 */ // (select:{ *:[v4i32] } i1:{ *:[i1] }:$cond, v4i32:{ *:[v4i32] }:$T, v4i32:{ *:[v4i32] }:$F) => (SELECT_VRRC:{ *:[v4i32] } i1:{ *:[i1] }:$cond, v4i32:{ *:[v4i32] }:$T, v4i32:{ *:[v4i32] }:$F)
54288 /* 161698 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_VRRC),
54289 /* 161703 */ GIR_RootConstrainSelectedInstOperands,
54290 /* 161704 */ // GIR_Coverage, 10,
54291 /* 161704 */ GIR_Done,
54292 /* 161705 */ // Label 2302: @161705
54293 /* 161705 */ GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(161739), // Rule ID 1425 //
54294 /* 161710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54295 /* 161713 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54296 /* 161716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54297 /* 161719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54298 /* 161722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54299 /* 161726 */ // (vselect:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vC, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vA)
54300 /* 161726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL),
54301 /* 161729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
54302 /* 161731 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54303 /* 161733 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54304 /* 161735 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54305 /* 161737 */ GIR_RootConstrainSelectedInstOperands,
54306 /* 161738 */ // GIR_Coverage, 1425,
54307 /* 161738 */ GIR_EraseRootFromParent_Done,
54308 /* 161739 */ // Label 2303: @161739
54309 /* 161739 */ GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(161773), // Rule ID 1427 //
54310 /* 161744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54311 /* 161747 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54312 /* 161750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54313 /* 161753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54314 /* 161756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54315 /* 161760 */ // (vselect:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vA, v4f32:{ *:[v4f32] }:$vB, v4f32:{ *:[v4f32] }:$vC) => (VSEL:{ *:[v4f32] } ?:{ *:[v4f32] }:$vC, ?:{ *:[v4f32] }:$vB, ?:{ *:[v4i32] }:$vA)
54316 /* 161760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL),
54317 /* 161763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
54318 /* 161765 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54319 /* 161767 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54320 /* 161769 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54321 /* 161771 */ GIR_RootConstrainSelectedInstOperands,
54322 /* 161772 */ // GIR_Coverage, 1427,
54323 /* 161772 */ GIR_EraseRootFromParent_Done,
54324 /* 161773 */ // Label 2304: @161773
54325 /* 161773 */ GIM_Reject,
54326 /* 161774 */ // Label 2278: @161774
54327 /* 161774 */ GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(161922),
54328 /* 161779 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
54329 /* 161782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54330 /* 161785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54331 /* 161788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54332 /* 161792 */ GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(161900), // Rule ID 1670 //
54333 /* 161797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54334 /* 161800 */ // (vselect:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXSEL:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$vC, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$vB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$vA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] })
54335 /* 161800 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
54336 /* 161803 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54337 /* 161807 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54338 /* 161812 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // vA
54339 /* 161816 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54340 /* 161821 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
54341 /* 161824 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54342 /* 161828 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54343 /* 161833 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // vB
54344 /* 161837 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54345 /* 161842 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
54346 /* 161845 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54347 /* 161849 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54348 /* 161854 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // vC
54349 /* 161858 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54350 /* 161863 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
54351 /* 161866 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
54352 /* 161870 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54353 /* 161875 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
54354 /* 161878 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
54355 /* 161881 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
54356 /* 161884 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
54357 /* 161886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54358 /* 161889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
54359 /* 161891 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
54360 /* 161894 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
54361 /* 161899 */ // GIR_Coverage, 1670,
54362 /* 161899 */ GIR_EraseRootFromParent_Done,
54363 /* 161900 */ // Label 2306: @161900
54364 /* 161900 */ GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(161921), // Rule ID 1424 //
54365 /* 161905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54366 /* 161908 */ // (vselect:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) => (VSEL:{ *:[v8i16] } ?:{ *:[v8i16] }:$vC, ?:{ *:[v8i16] }:$vB, ?:{ *:[v8i16] }:$vA)
54367 /* 161908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL),
54368 /* 161911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
54369 /* 161913 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54370 /* 161915 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54371 /* 161917 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54372 /* 161919 */ GIR_RootConstrainSelectedInstOperands,
54373 /* 161920 */ // GIR_Coverage, 1424,
54374 /* 161920 */ GIR_EraseRootFromParent_Done,
54375 /* 161921 */ // Label 2307: @161921
54376 /* 161921 */ GIM_Reject,
54377 /* 161922 */ // Label 2305: @161922
54378 /* 161922 */ GIM_Reject,
54379 /* 161923 */ // Label 2279: @161923
54380 /* 161923 */ GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(162071),
54381 /* 161928 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
54382 /* 161931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54383 /* 161934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54384 /* 161937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54385 /* 161941 */ GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(162049), // Rule ID 1669 //
54386 /* 161946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54387 /* 161949 */ // (vselect:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, v16i8:{ *:[v16i8] }:$vC) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXSEL:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$vC, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$vB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$vA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] })
54388 /* 161949 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
54389 /* 161952 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54390 /* 161956 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54391 /* 161961 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // vA
54392 /* 161965 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54393 /* 161970 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
54394 /* 161973 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54395 /* 161977 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54396 /* 161982 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // vB
54397 /* 161986 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54398 /* 161991 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
54399 /* 161994 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54400 /* 161998 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54401 /* 162003 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // vC
54402 /* 162007 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
54403 /* 162012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
54404 /* 162015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSEL),
54405 /* 162019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
54406 /* 162024 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
54407 /* 162027 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
54408 /* 162030 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
54409 /* 162033 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
54410 /* 162035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
54411 /* 162038 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
54412 /* 162040 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
54413 /* 162043 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
54414 /* 162048 */ // GIR_Coverage, 1669,
54415 /* 162048 */ GIR_EraseRootFromParent_Done,
54416 /* 162049 */ // Label 2309: @162049
54417 /* 162049 */ GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(162070), // Rule ID 1423 //
54418 /* 162054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54419 /* 162057 */ // (vselect:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, v16i8:{ *:[v16i8] }:$vC) => (VSEL:{ *:[v16i8] } ?:{ *:[v16i8] }:$vC, ?:{ *:[v16i8] }:$vB, ?:{ *:[v16i8] }:$vA)
54420 /* 162057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL),
54421 /* 162060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
54422 /* 162062 */ GIR_RootToRootCopy, /*OpIdx*/3, // vC
54423 /* 162064 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
54424 /* 162066 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
54425 /* 162068 */ GIR_RootConstrainSelectedInstOperands,
54426 /* 162069 */ // GIR_Coverage, 1423,
54427 /* 162069 */ GIR_EraseRootFromParent_Done,
54428 /* 162070 */ // Label 2310: @162070
54429 /* 162070 */ GIM_Reject,
54430 /* 162071 */ // Label 2308: @162071
54431 /* 162071 */ GIM_Reject,
54432 /* 162072 */ // Label 2280: @162072
54433 /* 162072 */ GIM_Reject,
54434 /* 162073 */ // Label 34: @162073
54435 /* 162073 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2315*/ GIMT_Encode4(162202),
54436 /* 162084 */ /*GILLT_s32*//*Label 2311*/ GIMT_Encode4(162104),
54437 /* 162088 */ /*GILLT_s64*//*Label 2312*/ GIMT_Encode4(162127), GIMT_Encode4(0),
54438 /* 162096 */ /*GILLT_v2s64*//*Label 2313*/ GIMT_Encode4(162150),
54439 /* 162100 */ /*GILLT_v4s32*//*Label 2314*/ GIMT_Encode4(162176),
54440 /* 162104 */ // Label 2311: @162104
54441 /* 162104 */ GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(162126), // Rule ID 207 //
54442 /* 162109 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
54443 /* 162112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
54444 /* 162115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
54445 /* 162119 */ // (mulhu:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MULHWU:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
54446 /* 162119 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULHWU),
54447 /* 162124 */ GIR_RootConstrainSelectedInstOperands,
54448 /* 162125 */ // GIR_Coverage, 207,
54449 /* 162125 */ GIR_Done,
54450 /* 162126 */ // Label 2316: @162126
54451 /* 162126 */ GIM_Reject,
54452 /* 162127 */ // Label 2312: @162127
54453 /* 162127 */ GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(162149), // Rule ID 677 //
54454 /* 162132 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
54455 /* 162135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
54456 /* 162138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
54457 /* 162142 */ // (mulhu:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MULHDU:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
54458 /* 162142 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULHDU),
54459 /* 162147 */ GIR_RootConstrainSelectedInstOperands,
54460 /* 162148 */ // GIR_Coverage, 677,
54461 /* 162148 */ GIR_Done,
54462 /* 162149 */ // Label 2317: @162149
54463 /* 162149 */ GIM_Reject,
54464 /* 162150 */ // Label 2313: @162150
54465 /* 162150 */ GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(162175), // Rule ID 1128 //
54466 /* 162155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
54467 /* 162158 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
54468 /* 162161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54469 /* 162164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54470 /* 162168 */ // (mulhu:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULHUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
54471 /* 162168 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULHUD),
54472 /* 162173 */ GIR_RootConstrainSelectedInstOperands,
54473 /* 162174 */ // GIR_Coverage, 1128,
54474 /* 162174 */ GIR_Done,
54475 /* 162175 */ // Label 2318: @162175
54476 /* 162175 */ GIM_Reject,
54477 /* 162176 */ // Label 2314: @162176
54478 /* 162176 */ GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(162201), // Rule ID 1126 //
54479 /* 162181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
54480 /* 162184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54481 /* 162187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54482 /* 162190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54483 /* 162194 */ // (mulhu:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULHUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
54484 /* 162194 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULHUW),
54485 /* 162199 */ GIR_RootConstrainSelectedInstOperands,
54486 /* 162200 */ // GIR_Coverage, 1126,
54487 /* 162200 */ GIR_Done,
54488 /* 162201 */ // Label 2319: @162201
54489 /* 162201 */ GIM_Reject,
54490 /* 162202 */ // Label 2315: @162202
54491 /* 162202 */ GIM_Reject,
54492 /* 162203 */ // Label 35: @162203
54493 /* 162203 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2324*/ GIMT_Encode4(162332),
54494 /* 162214 */ /*GILLT_s32*//*Label 2320*/ GIMT_Encode4(162234),
54495 /* 162218 */ /*GILLT_s64*//*Label 2321*/ GIMT_Encode4(162257), GIMT_Encode4(0),
54496 /* 162226 */ /*GILLT_v2s64*//*Label 2322*/ GIMT_Encode4(162280),
54497 /* 162230 */ /*GILLT_v4s32*//*Label 2323*/ GIMT_Encode4(162306),
54498 /* 162234 */ // Label 2320: @162234
54499 /* 162234 */ GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(162256), // Rule ID 206 //
54500 /* 162239 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
54501 /* 162242 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
54502 /* 162245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
54503 /* 162249 */ // (mulhs:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MULHW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB)
54504 /* 162249 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULHW),
54505 /* 162254 */ GIR_RootConstrainSelectedInstOperands,
54506 /* 162255 */ // GIR_Coverage, 206,
54507 /* 162255 */ GIR_Done,
54508 /* 162256 */ // Label 2325: @162256
54509 /* 162256 */ GIM_Reject,
54510 /* 162257 */ // Label 2321: @162257
54511 /* 162257 */ GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(162279), // Rule ID 676 //
54512 /* 162262 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
54513 /* 162265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
54514 /* 162268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
54515 /* 162272 */ // (mulhs:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MULHD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB)
54516 /* 162272 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULHD),
54517 /* 162277 */ GIR_RootConstrainSelectedInstOperands,
54518 /* 162278 */ // GIR_Coverage, 676,
54519 /* 162278 */ GIR_Done,
54520 /* 162279 */ // Label 2326: @162279
54521 /* 162279 */ GIM_Reject,
54522 /* 162280 */ // Label 2322: @162280
54523 /* 162280 */ GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(162305), // Rule ID 1127 //
54524 /* 162285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
54525 /* 162288 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
54526 /* 162291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54527 /* 162294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54528 /* 162298 */ // (mulhs:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULHSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB)
54529 /* 162298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULHSD),
54530 /* 162303 */ GIR_RootConstrainSelectedInstOperands,
54531 /* 162304 */ // GIR_Coverage, 1127,
54532 /* 162304 */ GIR_Done,
54533 /* 162305 */ // Label 2327: @162305
54534 /* 162305 */ GIM_Reject,
54535 /* 162306 */ // Label 2323: @162306
54536 /* 162306 */ GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(162331), // Rule ID 1125 //
54537 /* 162311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
54538 /* 162314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54539 /* 162317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54540 /* 162320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54541 /* 162324 */ // (mulhs:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULHSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB)
54542 /* 162324 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULHSW),
54543 /* 162329 */ GIR_RootConstrainSelectedInstOperands,
54544 /* 162330 */ // GIR_Coverage, 1125,
54545 /* 162330 */ GIR_Done,
54546 /* 162331 */ // Label 2328: @162331
54547 /* 162331 */ GIM_Reject,
54548 /* 162332 */ // Label 2324: @162332
54549 /* 162332 */ GIM_Reject,
54550 /* 162333 */ // Label 36: @162333
54551 /* 162333 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 2332*/ GIMT_Encode4(162434),
54552 /* 162344 */ /*GILLT_v4s32*//*Label 2329*/ GIMT_Encode4(162356),
54553 /* 162348 */ /*GILLT_v8s16*//*Label 2330*/ GIMT_Encode4(162382),
54554 /* 162352 */ /*GILLT_v16s8*//*Label 2331*/ GIMT_Encode4(162408),
54555 /* 162356 */ // Label 2329: @162356
54556 /* 162356 */ GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(162381), // Rule ID 1302 //
54557 /* 162361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54558 /* 162364 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54559 /* 162367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54560 /* 162370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54561 /* 162374 */ // (uaddsat:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VADDUWS:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
54562 /* 162374 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUWS),
54563 /* 162379 */ GIR_RootConstrainSelectedInstOperands,
54564 /* 162380 */ // GIR_Coverage, 1302,
54565 /* 162380 */ GIR_Done,
54566 /* 162381 */ // Label 2333: @162381
54567 /* 162381 */ GIM_Reject,
54568 /* 162382 */ // Label 2330: @162382
54569 /* 162382 */ GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(162407), // Rule ID 1300 //
54570 /* 162387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54571 /* 162390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
54572 /* 162393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54573 /* 162396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54574 /* 162400 */ // (uaddsat:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VADDUHS:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB)
54575 /* 162400 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUHS),
54576 /* 162405 */ GIR_RootConstrainSelectedInstOperands,
54577 /* 162406 */ // GIR_Coverage, 1300,
54578 /* 162406 */ GIR_Done,
54579 /* 162407 */ // Label 2334: @162407
54580 /* 162407 */ GIM_Reject,
54581 /* 162408 */ // Label 2331: @162408
54582 /* 162408 */ GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(162433), // Rule ID 1298 //
54583 /* 162413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54584 /* 162416 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
54585 /* 162419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54586 /* 162422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54587 /* 162426 */ // (uaddsat:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VADDUBS:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB)
54588 /* 162426 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUBS),
54589 /* 162431 */ GIR_RootConstrainSelectedInstOperands,
54590 /* 162432 */ // GIR_Coverage, 1298,
54591 /* 162432 */ GIR_Done,
54592 /* 162433 */ // Label 2335: @162433
54593 /* 162433 */ GIM_Reject,
54594 /* 162434 */ // Label 2332: @162434
54595 /* 162434 */ GIM_Reject,
54596 /* 162435 */ // Label 37: @162435
54597 /* 162435 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 2339*/ GIMT_Encode4(162536),
54598 /* 162446 */ /*GILLT_v4s32*//*Label 2336*/ GIMT_Encode4(162458),
54599 /* 162450 */ /*GILLT_v8s16*//*Label 2337*/ GIMT_Encode4(162484),
54600 /* 162454 */ /*GILLT_v16s8*//*Label 2338*/ GIMT_Encode4(162510),
54601 /* 162458 */ // Label 2336: @162458
54602 /* 162458 */ GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(162483), // Rule ID 1301 //
54603 /* 162463 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54604 /* 162466 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54605 /* 162469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54606 /* 162472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54607 /* 162476 */ // (saddsat:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VADDSWS:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
54608 /* 162476 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDSWS),
54609 /* 162481 */ GIR_RootConstrainSelectedInstOperands,
54610 /* 162482 */ // GIR_Coverage, 1301,
54611 /* 162482 */ GIR_Done,
54612 /* 162483 */ // Label 2340: @162483
54613 /* 162483 */ GIM_Reject,
54614 /* 162484 */ // Label 2337: @162484
54615 /* 162484 */ GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(162509), // Rule ID 1299 //
54616 /* 162489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54617 /* 162492 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
54618 /* 162495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54619 /* 162498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54620 /* 162502 */ // (saddsat:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VADDSHS:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB)
54621 /* 162502 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDSHS),
54622 /* 162507 */ GIR_RootConstrainSelectedInstOperands,
54623 /* 162508 */ // GIR_Coverage, 1299,
54624 /* 162508 */ GIR_Done,
54625 /* 162509 */ // Label 2341: @162509
54626 /* 162509 */ GIM_Reject,
54627 /* 162510 */ // Label 2338: @162510
54628 /* 162510 */ GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(162535), // Rule ID 1297 //
54629 /* 162515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54630 /* 162518 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
54631 /* 162521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54632 /* 162524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54633 /* 162528 */ // (saddsat:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VADDSBS:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB)
54634 /* 162528 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDSBS),
54635 /* 162533 */ GIR_RootConstrainSelectedInstOperands,
54636 /* 162534 */ // GIR_Coverage, 1297,
54637 /* 162534 */ GIR_Done,
54638 /* 162535 */ // Label 2342: @162535
54639 /* 162535 */ GIM_Reject,
54640 /* 162536 */ // Label 2339: @162536
54641 /* 162536 */ GIM_Reject,
54642 /* 162537 */ // Label 38: @162537
54643 /* 162537 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 2346*/ GIMT_Encode4(162638),
54644 /* 162548 */ /*GILLT_v4s32*//*Label 2343*/ GIMT_Encode4(162560),
54645 /* 162552 */ /*GILLT_v8s16*//*Label 2344*/ GIMT_Encode4(162586),
54646 /* 162556 */ /*GILLT_v16s8*//*Label 2345*/ GIMT_Encode4(162612),
54647 /* 162560 */ // Label 2343: @162560
54648 /* 162560 */ GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(162585), // Rule ID 1308 //
54649 /* 162565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54650 /* 162568 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54651 /* 162571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54652 /* 162574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54653 /* 162578 */ // (usubsat:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUBUWS:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
54654 /* 162578 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUWS),
54655 /* 162583 */ GIR_RootConstrainSelectedInstOperands,
54656 /* 162584 */ // GIR_Coverage, 1308,
54657 /* 162584 */ GIR_Done,
54658 /* 162585 */ // Label 2347: @162585
54659 /* 162585 */ GIM_Reject,
54660 /* 162586 */ // Label 2344: @162586
54661 /* 162586 */ GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(162611), // Rule ID 1306 //
54662 /* 162591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54663 /* 162594 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
54664 /* 162597 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54665 /* 162600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54666 /* 162604 */ // (usubsat:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSUBUHS:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB)
54667 /* 162604 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUHS),
54668 /* 162609 */ GIR_RootConstrainSelectedInstOperands,
54669 /* 162610 */ // GIR_Coverage, 1306,
54670 /* 162610 */ GIR_Done,
54671 /* 162611 */ // Label 2348: @162611
54672 /* 162611 */ GIM_Reject,
54673 /* 162612 */ // Label 2345: @162612
54674 /* 162612 */ GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(162637), // Rule ID 1304 //
54675 /* 162617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54676 /* 162620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
54677 /* 162623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54678 /* 162626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54679 /* 162630 */ // (usubsat:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSUBUBS:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB)
54680 /* 162630 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUBS),
54681 /* 162635 */ GIR_RootConstrainSelectedInstOperands,
54682 /* 162636 */ // GIR_Coverage, 1304,
54683 /* 162636 */ GIR_Done,
54684 /* 162637 */ // Label 2349: @162637
54685 /* 162637 */ GIM_Reject,
54686 /* 162638 */ // Label 2346: @162638
54687 /* 162638 */ GIM_Reject,
54688 /* 162639 */ // Label 39: @162639
54689 /* 162639 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 2353*/ GIMT_Encode4(162740),
54690 /* 162650 */ /*GILLT_v4s32*//*Label 2350*/ GIMT_Encode4(162662),
54691 /* 162654 */ /*GILLT_v8s16*//*Label 2351*/ GIMT_Encode4(162688),
54692 /* 162658 */ /*GILLT_v16s8*//*Label 2352*/ GIMT_Encode4(162714),
54693 /* 162662 */ // Label 2350: @162662
54694 /* 162662 */ GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(162687), // Rule ID 1307 //
54695 /* 162667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54696 /* 162670 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54697 /* 162673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54698 /* 162676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54699 /* 162680 */ // (ssubsat:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUBSWS:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB)
54700 /* 162680 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBSWS),
54701 /* 162685 */ GIR_RootConstrainSelectedInstOperands,
54702 /* 162686 */ // GIR_Coverage, 1307,
54703 /* 162686 */ GIR_Done,
54704 /* 162687 */ // Label 2354: @162687
54705 /* 162687 */ GIM_Reject,
54706 /* 162688 */ // Label 2351: @162688
54707 /* 162688 */ GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(162713), // Rule ID 1305 //
54708 /* 162693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54709 /* 162696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
54710 /* 162699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54711 /* 162702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54712 /* 162706 */ // (ssubsat:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSUBSHS:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB)
54713 /* 162706 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBSHS),
54714 /* 162711 */ GIR_RootConstrainSelectedInstOperands,
54715 /* 162712 */ // GIR_Coverage, 1305,
54716 /* 162712 */ GIR_Done,
54717 /* 162713 */ // Label 2355: @162713
54718 /* 162713 */ GIM_Reject,
54719 /* 162714 */ // Label 2352: @162714
54720 /* 162714 */ GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(162739), // Rule ID 1303 //
54721 /* 162719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54722 /* 162722 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
54723 /* 162725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54724 /* 162728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54725 /* 162732 */ // (ssubsat:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSUBSBS:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB)
54726 /* 162732 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBSBS),
54727 /* 162737 */ GIR_RootConstrainSelectedInstOperands,
54728 /* 162738 */ // GIR_Coverage, 1303,
54729 /* 162738 */ GIR_Done,
54730 /* 162739 */ // Label 2356: @162739
54731 /* 162739 */ GIM_Reject,
54732 /* 162740 */ // Label 2353: @162740
54733 /* 162740 */ GIM_Reject,
54734 /* 162741 */ // Label 40: @162741
54735 /* 162741 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2362*/ GIMT_Encode4(163035),
54736 /* 162752 */ /*GILLT_s32*//*Label 2357*/ GIMT_Encode4(162772),
54737 /* 162756 */ /*GILLT_s64*//*Label 2358*/ GIMT_Encode4(162846),
54738 /* 162760 */ /*GILLT_s128*//*Label 2359*/ GIMT_Encode4(162924),
54739 /* 162764 */ /*GILLT_v2s64*//*Label 2360*/ GIMT_Encode4(162950),
54740 /* 162768 */ /*GILLT_v4s32*//*Label 2361*/ GIMT_Encode4(162980),
54741 /* 162772 */ // Label 2357: @162772
54742 /* 162772 */ GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(162845),
54743 /* 162777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
54744 /* 162780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
54745 /* 162783 */ GIM_Try, /*On fail goto*//*Label 2364*/ GIMT_Encode4(162802), // Rule ID 953 //
54746 /* 162788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
54747 /* 162791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
54748 /* 162795 */ // (fadd:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSADDSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
54749 /* 162795 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDSP),
54750 /* 162800 */ GIR_RootConstrainSelectedInstOperands,
54751 /* 162801 */ // GIR_Coverage, 953,
54752 /* 162801 */ GIR_Done,
54753 /* 162802 */ // Label 2364: @162802
54754 /* 162802 */ GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(162825), // Rule ID 239 //
54755 /* 162807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
54756 /* 162810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
54757 /* 162814 */ // (fadd:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB)
54758 /* 162814 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FADDS),
54759 /* 162819 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54760 /* 162823 */ GIR_RootConstrainSelectedInstOperands,
54761 /* 162824 */ // GIR_Coverage, 239,
54762 /* 162824 */ GIR_Done,
54763 /* 162825 */ // Label 2365: @162825
54764 /* 162825 */ GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(162844), // Rule ID 583 //
54765 /* 162830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
54766 /* 162833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
54767 /* 162837 */ // (fadd:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSADD:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
54768 /* 162837 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSADD),
54769 /* 162842 */ GIR_RootConstrainSelectedInstOperands,
54770 /* 162843 */ // GIR_Coverage, 583,
54771 /* 162843 */ GIR_Done,
54772 /* 162844 */ // Label 2366: @162844
54773 /* 162844 */ GIM_Reject,
54774 /* 162845 */ // Label 2363: @162845
54775 /* 162845 */ GIM_Reject,
54776 /* 162846 */ // Label 2358: @162846
54777 /* 162846 */ GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(162923),
54778 /* 162851 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
54779 /* 162854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
54780 /* 162857 */ GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(162880), // Rule ID 770 //
54781 /* 162862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54782 /* 162865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
54783 /* 162869 */ // (fadd:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSADDDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
54784 /* 162869 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDDP),
54785 /* 162874 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54786 /* 162878 */ GIR_RootConstrainSelectedInstOperands,
54787 /* 162879 */ // GIR_Coverage, 770,
54788 /* 162879 */ GIR_Done,
54789 /* 162880 */ // Label 2368: @162880
54790 /* 162880 */ GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(162903), // Rule ID 237 //
54791 /* 162885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
54792 /* 162888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
54793 /* 162892 */ // (fadd:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB)
54794 /* 162892 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FADD),
54795 /* 162897 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54796 /* 162901 */ GIR_RootConstrainSelectedInstOperands,
54797 /* 162902 */ // GIR_Coverage, 237,
54798 /* 162902 */ GIR_Done,
54799 /* 162903 */ // Label 2369: @162903
54800 /* 162903 */ GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(162922), // Rule ID 562 //
54801 /* 162908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
54802 /* 162911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
54803 /* 162915 */ // (fadd:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDADD:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
54804 /* 162915 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDADD),
54805 /* 162920 */ GIR_RootConstrainSelectedInstOperands,
54806 /* 162921 */ // GIR_Coverage, 562,
54807 /* 162921 */ GIR_Done,
54808 /* 162922 */ // Label 2370: @162922
54809 /* 162922 */ GIM_Reject,
54810 /* 162923 */ // Label 2367: @162923
54811 /* 162923 */ GIM_Reject,
54812 /* 162924 */ // Label 2359: @162924
54813 /* 162924 */ GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(162949), // Rule ID 988 //
54814 /* 162929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
54815 /* 162932 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
54816 /* 162935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
54817 /* 162938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54818 /* 162942 */ // (fadd:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSADDQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
54819 /* 162942 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDQP),
54820 /* 162947 */ GIR_RootConstrainSelectedInstOperands,
54821 /* 162948 */ // GIR_Coverage, 988,
54822 /* 162948 */ GIR_Done,
54823 /* 162949 */ // Label 2371: @162949
54824 /* 162949 */ GIM_Reject,
54825 /* 162950 */ // Label 2360: @162950
54826 /* 162950 */ GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(162979), // Rule ID 774 //
54827 /* 162955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54828 /* 162958 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
54829 /* 162961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54830 /* 162964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54831 /* 162968 */ // (fadd:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVADDDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
54832 /* 162968 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVADDDP),
54833 /* 162973 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54834 /* 162977 */ GIR_RootConstrainSelectedInstOperands,
54835 /* 162978 */ // GIR_Coverage, 774,
54836 /* 162978 */ GIR_Done,
54837 /* 162979 */ // Label 2372: @162979
54838 /* 162979 */ GIM_Reject,
54839 /* 162980 */ // Label 2361: @162980
54840 /* 162980 */ GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(163034),
54841 /* 162985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54842 /* 162988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54843 /* 162991 */ GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(163014), // Rule ID 776 //
54844 /* 162996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54845 /* 162999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54846 /* 163003 */ // (fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVADDSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
54847 /* 163003 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVADDSP),
54848 /* 163008 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54849 /* 163012 */ GIR_RootConstrainSelectedInstOperands,
54850 /* 163013 */ // GIR_Coverage, 776,
54851 /* 163013 */ GIR_Done,
54852 /* 163014 */ // Label 2374: @163014
54853 /* 163014 */ GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(163033), // Rule ID 300 //
54854 /* 163019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54855 /* 163022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54856 /* 163026 */ // (fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VADDFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB)
54857 /* 163026 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDFP),
54858 /* 163031 */ GIR_RootConstrainSelectedInstOperands,
54859 /* 163032 */ // GIR_Coverage, 300,
54860 /* 163032 */ GIR_Done,
54861 /* 163033 */ // Label 2375: @163033
54862 /* 163033 */ GIM_Reject,
54863 /* 163034 */ // Label 2373: @163034
54864 /* 163034 */ GIM_Reject,
54865 /* 163035 */ // Label 2362: @163035
54866 /* 163035 */ GIM_Reject,
54867 /* 163036 */ // Label 41: @163036
54868 /* 163036 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2381*/ GIMT_Encode4(163330),
54869 /* 163047 */ /*GILLT_s32*//*Label 2376*/ GIMT_Encode4(163067),
54870 /* 163051 */ /*GILLT_s64*//*Label 2377*/ GIMT_Encode4(163141),
54871 /* 163055 */ /*GILLT_s128*//*Label 2378*/ GIMT_Encode4(163219),
54872 /* 163059 */ /*GILLT_v2s64*//*Label 2379*/ GIMT_Encode4(163245),
54873 /* 163063 */ /*GILLT_v4s32*//*Label 2380*/ GIMT_Encode4(163275),
54874 /* 163067 */ // Label 2376: @163067
54875 /* 163067 */ GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(163140),
54876 /* 163072 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
54877 /* 163075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
54878 /* 163078 */ GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(163097), // Rule ID 957 //
54879 /* 163083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
54880 /* 163086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
54881 /* 163090 */ // (fsub:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSSUBSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
54882 /* 163090 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBSP),
54883 /* 163095 */ GIR_RootConstrainSelectedInstOperands,
54884 /* 163096 */ // GIR_Coverage, 957,
54885 /* 163096 */ GIR_Done,
54886 /* 163097 */ // Label 2383: @163097
54887 /* 163097 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(163120), // Rule ID 251 //
54888 /* 163102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
54889 /* 163105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
54890 /* 163109 */ // (fsub:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB)
54891 /* 163109 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSUBS),
54892 /* 163114 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54893 /* 163118 */ GIR_RootConstrainSelectedInstOperands,
54894 /* 163119 */ // GIR_Coverage, 251,
54895 /* 163119 */ GIR_Done,
54896 /* 163120 */ // Label 2384: @163120
54897 /* 163120 */ GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(163139), // Rule ID 601 //
54898 /* 163125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
54899 /* 163128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
54900 /* 163132 */ // (fsub:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSSUB:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
54901 /* 163132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSSUB),
54902 /* 163137 */ GIR_RootConstrainSelectedInstOperands,
54903 /* 163138 */ // GIR_Coverage, 601,
54904 /* 163138 */ GIR_Done,
54905 /* 163139 */ // Label 2385: @163139
54906 /* 163139 */ GIM_Reject,
54907 /* 163140 */ // Label 2382: @163140
54908 /* 163140 */ GIM_Reject,
54909 /* 163141 */ // Label 2377: @163141
54910 /* 163141 */ GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(163218),
54911 /* 163146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
54912 /* 163149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
54913 /* 163152 */ GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(163175), // Rule ID 782 //
54914 /* 163157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54915 /* 163160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
54916 /* 163164 */ // (fsub:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSSUBDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
54917 /* 163164 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBDP),
54918 /* 163169 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54919 /* 163173 */ GIR_RootConstrainSelectedInstOperands,
54920 /* 163174 */ // GIR_Coverage, 782,
54921 /* 163174 */ GIR_Done,
54922 /* 163175 */ // Label 2387: @163175
54923 /* 163175 */ GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(163198), // Rule ID 249 //
54924 /* 163180 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
54925 /* 163183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
54926 /* 163187 */ // (fsub:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB)
54927 /* 163187 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSUB),
54928 /* 163192 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54929 /* 163196 */ GIR_RootConstrainSelectedInstOperands,
54930 /* 163197 */ // GIR_Coverage, 249,
54931 /* 163197 */ GIR_Done,
54932 /* 163198 */ // Label 2388: @163198
54933 /* 163198 */ GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(163217), // Rule ID 580 //
54934 /* 163203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
54935 /* 163206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
54936 /* 163210 */ // (fsub:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDSUB:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
54937 /* 163210 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDSUB),
54938 /* 163215 */ GIR_RootConstrainSelectedInstOperands,
54939 /* 163216 */ // GIR_Coverage, 580,
54940 /* 163216 */ GIR_Done,
54941 /* 163217 */ // Label 2389: @163217
54942 /* 163217 */ GIM_Reject,
54943 /* 163218 */ // Label 2386: @163218
54944 /* 163218 */ GIM_Reject,
54945 /* 163219 */ // Label 2378: @163219
54946 /* 163219 */ GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(163244), // Rule ID 992 //
54947 /* 163224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
54948 /* 163227 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
54949 /* 163230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
54950 /* 163233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54951 /* 163237 */ // (fsub:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
54952 /* 163237 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBQP),
54953 /* 163242 */ GIR_RootConstrainSelectedInstOperands,
54954 /* 163243 */ // GIR_Coverage, 992,
54955 /* 163243 */ GIR_Done,
54956 /* 163244 */ // Label 2390: @163244
54957 /* 163244 */ GIM_Reject,
54958 /* 163245 */ // Label 2379: @163245
54959 /* 163245 */ GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(163274), // Rule ID 784 //
54960 /* 163250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54961 /* 163253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
54962 /* 163256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54963 /* 163259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54964 /* 163263 */ // (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVSUBDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
54965 /* 163263 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSUBDP),
54966 /* 163268 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54967 /* 163272 */ GIR_RootConstrainSelectedInstOperands,
54968 /* 163273 */ // GIR_Coverage, 784,
54969 /* 163273 */ GIR_Done,
54970 /* 163274 */ // Label 2391: @163274
54971 /* 163274 */ GIM_Reject,
54972 /* 163275 */ // Label 2380: @163275
54973 /* 163275 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(163329),
54974 /* 163280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
54975 /* 163283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54976 /* 163286 */ GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(163309), // Rule ID 786 //
54977 /* 163291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
54978 /* 163294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
54979 /* 163298 */ // (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVSUBSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
54980 /* 163298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSUBSP),
54981 /* 163303 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
54982 /* 163307 */ GIR_RootConstrainSelectedInstOperands,
54983 /* 163308 */ // GIR_Coverage, 786,
54984 /* 163308 */ GIR_Done,
54985 /* 163309 */ // Label 2393: @163309
54986 /* 163309 */ GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(163328), // Rule ID 370 //
54987 /* 163314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
54988 /* 163317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
54989 /* 163321 */ // (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VSUBFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB)
54990 /* 163321 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBFP),
54991 /* 163326 */ GIR_RootConstrainSelectedInstOperands,
54992 /* 163327 */ // GIR_Coverage, 370,
54993 /* 163327 */ GIR_Done,
54994 /* 163328 */ // Label 2394: @163328
54995 /* 163328 */ GIM_Reject,
54996 /* 163329 */ // Label 2392: @163329
54997 /* 163329 */ GIM_Reject,
54998 /* 163330 */ // Label 2381: @163330
54999 /* 163330 */ GIM_Reject,
55000 /* 163331 */ // Label 42: @163331
55001 /* 163331 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2400*/ GIMT_Encode4(163680),
55002 /* 163342 */ /*GILLT_s32*//*Label 2395*/ GIMT_Encode4(163362),
55003 /* 163346 */ /*GILLT_s64*//*Label 2396*/ GIMT_Encode4(163436),
55004 /* 163350 */ /*GILLT_s128*//*Label 2397*/ GIMT_Encode4(163514),
55005 /* 163354 */ /*GILLT_v2s64*//*Label 2398*/ GIMT_Encode4(163540),
55006 /* 163358 */ /*GILLT_v4s32*//*Label 2399*/ GIMT_Encode4(163570),
55007 /* 163362 */ // Label 2395: @163362
55008 /* 163362 */ GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(163435),
55009 /* 163367 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
55010 /* 163370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55011 /* 163373 */ GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(163392), // Rule ID 955 //
55012 /* 163378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55013 /* 163381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55014 /* 163385 */ // (fmul:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSMULSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
55015 /* 163385 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULSP),
55016 /* 163390 */ GIR_RootConstrainSelectedInstOperands,
55017 /* 163391 */ // GIR_Coverage, 955,
55018 /* 163391 */ GIR_Done,
55019 /* 163392 */ // Label 2402: @163392
55020 /* 163392 */ GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(163415), // Rule ID 247 //
55021 /* 163397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55022 /* 163400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55023 /* 163404 */ // (fmul:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) => (FMULS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC)
55024 /* 163404 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMULS),
55025 /* 163409 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55026 /* 163413 */ GIR_RootConstrainSelectedInstOperands,
55027 /* 163414 */ // GIR_Coverage, 247,
55028 /* 163414 */ GIR_Done,
55029 /* 163415 */ // Label 2403: @163415
55030 /* 163415 */ GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(163434), // Rule ID 597 //
55031 /* 163420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
55032 /* 163423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
55033 /* 163427 */ // (fmul:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSMUL:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
55034 /* 163427 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSMUL),
55035 /* 163432 */ GIR_RootConstrainSelectedInstOperands,
55036 /* 163433 */ // GIR_Coverage, 597,
55037 /* 163433 */ GIR_Done,
55038 /* 163434 */ // Label 2404: @163434
55039 /* 163434 */ GIM_Reject,
55040 /* 163435 */ // Label 2401: @163435
55041 /* 163435 */ GIM_Reject,
55042 /* 163436 */ // Label 2396: @163436
55043 /* 163436 */ GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(163513),
55044 /* 163441 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
55045 /* 163444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55046 /* 163447 */ GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(163470), // Rule ID 772 //
55047 /* 163452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55048 /* 163455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55049 /* 163459 */ // (fmul:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSMULDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
55050 /* 163459 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULDP),
55051 /* 163464 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55052 /* 163468 */ GIR_RootConstrainSelectedInstOperands,
55053 /* 163469 */ // GIR_Coverage, 772,
55054 /* 163469 */ GIR_Done,
55055 /* 163470 */ // Label 2406: @163470
55056 /* 163470 */ GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(163493), // Rule ID 245 //
55057 /* 163475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55058 /* 163478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
55059 /* 163482 */ // (fmul:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) => (FMUL:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC)
55060 /* 163482 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMUL),
55061 /* 163487 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55062 /* 163491 */ GIR_RootConstrainSelectedInstOperands,
55063 /* 163492 */ // GIR_Coverage, 245,
55064 /* 163492 */ GIR_Done,
55065 /* 163493 */ // Label 2407: @163493
55066 /* 163493 */ GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(163512), // Rule ID 576 //
55067 /* 163498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
55068 /* 163501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
55069 /* 163505 */ // (fmul:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDMUL:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
55070 /* 163505 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDMUL),
55071 /* 163510 */ GIR_RootConstrainSelectedInstOperands,
55072 /* 163511 */ // GIR_Coverage, 576,
55073 /* 163511 */ GIR_Done,
55074 /* 163512 */ // Label 2408: @163512
55075 /* 163512 */ GIM_Reject,
55076 /* 163513 */ // Label 2405: @163513
55077 /* 163513 */ GIM_Reject,
55078 /* 163514 */ // Label 2397: @163514
55079 /* 163514 */ GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(163539), // Rule ID 990 //
55080 /* 163519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
55081 /* 163522 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
55082 /* 163525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
55083 /* 163528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
55084 /* 163532 */ // (fmul:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSMULQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
55085 /* 163532 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULQP),
55086 /* 163537 */ GIR_RootConstrainSelectedInstOperands,
55087 /* 163538 */ // GIR_Coverage, 990,
55088 /* 163538 */ GIR_Done,
55089 /* 163539 */ // Label 2409: @163539
55090 /* 163539 */ GIM_Reject,
55091 /* 163540 */ // Label 2398: @163540
55092 /* 163540 */ GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(163569), // Rule ID 778 //
55093 /* 163545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55094 /* 163548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
55095 /* 163551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
55096 /* 163554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
55097 /* 163558 */ // (fmul:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVMULDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
55098 /* 163558 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMULDP),
55099 /* 163563 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55100 /* 163567 */ GIR_RootConstrainSelectedInstOperands,
55101 /* 163568 */ // GIR_Coverage, 778,
55102 /* 163568 */ GIR_Done,
55103 /* 163569 */ // Label 2410: @163569
55104 /* 163569 */ GIM_Reject,
55105 /* 163570 */ // Label 2399: @163570
55106 /* 163570 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(163679),
55107 /* 163575 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
55108 /* 163578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
55109 /* 163581 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(163604), // Rule ID 780 //
55110 /* 163586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55111 /* 163589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
55112 /* 163593 */ // (fmul:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVMULSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
55113 /* 163593 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMULSP),
55114 /* 163598 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55115 /* 163602 */ GIR_RootConstrainSelectedInstOperands,
55116 /* 163603 */ // GIR_Coverage, 780,
55117 /* 163603 */ GIR_Done,
55118 /* 163604 */ // Label 2412: @163604
55119 /* 163604 */ GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(163678), // Rule ID 1385 //
55120 /* 163609 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
55121 /* 163612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
55122 /* 163616 */ // (fmul:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) => (VMADDFP:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA, ?:{ *:[v4f32] }:$vB, (VSLW:{ *:[v4i32] } (V_SETALLONES:{ *:[v4i32] }), (V_SETALLONES:{ *:[v4i32] })))
55123 /* 163616 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
55124 /* 163619 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::V_SETALLONES),
55125 /* 163623 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
55126 /* 163628 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
55127 /* 163630 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
55128 /* 163633 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::V_SETALLONES),
55129 /* 163637 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
55130 /* 163642 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
55131 /* 163644 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
55132 /* 163647 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::VSLW),
55133 /* 163651 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
55134 /* 163656 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
55135 /* 163659 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
55136 /* 163662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
55137 /* 163664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMADDFP),
55138 /* 163667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
55139 /* 163669 */ GIR_RootToRootCopy, /*OpIdx*/1, // vA
55140 /* 163671 */ GIR_RootToRootCopy, /*OpIdx*/2, // vB
55141 /* 163673 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
55142 /* 163676 */ GIR_RootConstrainSelectedInstOperands,
55143 /* 163677 */ // GIR_Coverage, 1385,
55144 /* 163677 */ GIR_EraseRootFromParent_Done,
55145 /* 163678 */ // Label 2413: @163678
55146 /* 163678 */ GIM_Reject,
55147 /* 163679 */ // Label 2411: @163679
55148 /* 163679 */ GIM_Reject,
55149 /* 163680 */ // Label 2400: @163680
55150 /* 163680 */ GIM_Reject,
55151 /* 163681 */ // Label 43: @163681
55152 /* 163681 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2419*/ GIMT_Encode4(164261),
55153 /* 163692 */ /*GILLT_s32*//*Label 2414*/ GIMT_Encode4(163712),
55154 /* 163696 */ /*GILLT_s64*//*Label 2415*/ GIMT_Encode4(163858),
55155 /* 163700 */ /*GILLT_s128*//*Label 2416*/ GIMT_Encode4(164004),
55156 /* 163704 */ /*GILLT_v2s64*//*Label 2417*/ GIMT_Encode4(164082),
55157 /* 163708 */ /*GILLT_v4s32*//*Label 2418*/ GIMT_Encode4(164160),
55158 /* 163712 */ // Label 2414: @163712
55159 /* 163712 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(163857),
55160 /* 163717 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
55161 /* 163720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55162 /* 163723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55163 /* 163726 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(163767), // Rule ID 969 //
55164 /* 163731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55165 /* 163734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55166 /* 163738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
55167 /* 163742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
55168 /* 163746 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55169 /* 163750 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55170 /* 163752 */ // (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi)) => (XSMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
55171 /* 163752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBASP),
55172 /* 163755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55173 /* 163757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi
55174 /* 163761 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
55175 /* 163763 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
55176 /* 163765 */ GIR_RootConstrainSelectedInstOperands,
55177 /* 163766 */ // GIR_Coverage, 969,
55178 /* 163766 */ GIR_EraseRootFromParent_Done,
55179 /* 163767 */ // Label 2421: @163767
55180 /* 163767 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(163792), // Rule ID 967 //
55181 /* 163772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55182 /* 163775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55183 /* 163779 */ // (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi) => (XSMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
55184 /* 163779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDASP),
55185 /* 163782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55186 /* 163784 */ GIR_RootToRootCopy, /*OpIdx*/3, // XTi
55187 /* 163786 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
55188 /* 163788 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
55189 /* 163790 */ GIR_RootConstrainSelectedInstOperands,
55190 /* 163791 */ // GIR_Coverage, 967,
55191 /* 163791 */ GIR_EraseRootFromParent_Done,
55192 /* 163792 */ // Label 2422: @163792
55193 /* 163792 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(163833), // Rule ID 225 //
55194 /* 163797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55195 /* 163800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55196 /* 163804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
55197 /* 163808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
55198 /* 163812 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55199 /* 163816 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55200 /* 163818 */ // (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB)) => (FMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)
55201 /* 163818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUBS),
55202 /* 163821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55203 /* 163823 */ GIR_RootToRootCopy, /*OpIdx*/1, // FRA
55204 /* 163825 */ GIR_RootToRootCopy, /*OpIdx*/2, // FRC
55205 /* 163827 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB
55206 /* 163831 */ GIR_RootConstrainSelectedInstOperands,
55207 /* 163832 */ // GIR_Coverage, 225,
55208 /* 163832 */ GIR_EraseRootFromParent_Done,
55209 /* 163833 */ // Label 2423: @163833
55210 /* 163833 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(163856), // Rule ID 221 //
55211 /* 163838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55212 /* 163841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55213 /* 163845 */ // (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) => (FMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)
55214 /* 163845 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMADDS),
55215 /* 163850 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55216 /* 163854 */ GIR_RootConstrainSelectedInstOperands,
55217 /* 163855 */ // GIR_Coverage, 221,
55218 /* 163855 */ GIR_Done,
55219 /* 163856 */ // Label 2424: @163856
55220 /* 163856 */ GIM_Reject,
55221 /* 163857 */ // Label 2420: @163857
55222 /* 163857 */ GIM_Reject,
55223 /* 163858 */ // Label 2415: @163858
55224 /* 163858 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(164003),
55225 /* 163863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
55226 /* 163866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55227 /* 163869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55228 /* 163872 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(163913), // Rule ID 790 //
55229 /* 163877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55230 /* 163880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55231 /* 163884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
55232 /* 163888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
55233 /* 163892 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55234 /* 163896 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55235 /* 163898 */ // (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi)) => (XSMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
55236 /* 163898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBADP),
55237 /* 163901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55238 /* 163903 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi
55239 /* 163907 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
55240 /* 163909 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
55241 /* 163911 */ GIR_RootConstrainSelectedInstOperands,
55242 /* 163912 */ // GIR_Coverage, 790,
55243 /* 163912 */ GIR_EraseRootFromParent_Done,
55244 /* 163913 */ // Label 2426: @163913
55245 /* 163913 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(163938), // Rule ID 788 //
55246 /* 163918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55247 /* 163921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55248 /* 163925 */ // (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi) => (XSMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
55249 /* 163925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDADP),
55250 /* 163928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55251 /* 163930 */ GIR_RootToRootCopy, /*OpIdx*/3, // XTi
55252 /* 163932 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
55253 /* 163934 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
55254 /* 163936 */ GIR_RootConstrainSelectedInstOperands,
55255 /* 163937 */ // GIR_Coverage, 788,
55256 /* 163937 */ GIR_EraseRootFromParent_Done,
55257 /* 163938 */ // Label 2427: @163938
55258 /* 163938 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(163979), // Rule ID 223 //
55259 /* 163943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55260 /* 163946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
55261 /* 163950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
55262 /* 163954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
55263 /* 163958 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55264 /* 163962 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55265 /* 163964 */ // (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB)) => (FMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)
55266 /* 163964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUB),
55267 /* 163967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55268 /* 163969 */ GIR_RootToRootCopy, /*OpIdx*/1, // FRA
55269 /* 163971 */ GIR_RootToRootCopy, /*OpIdx*/2, // FRC
55270 /* 163973 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB
55271 /* 163977 */ GIR_RootConstrainSelectedInstOperands,
55272 /* 163978 */ // GIR_Coverage, 223,
55273 /* 163978 */ GIR_EraseRootFromParent_Done,
55274 /* 163979 */ // Label 2428: @163979
55275 /* 163979 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(164002), // Rule ID 219 //
55276 /* 163984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55277 /* 163987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
55278 /* 163991 */ // (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) => (FMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)
55279 /* 163991 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMADD),
55280 /* 163996 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55281 /* 164000 */ GIR_RootConstrainSelectedInstOperands,
55282 /* 164001 */ // GIR_Coverage, 219,
55283 /* 164001 */ GIR_Done,
55284 /* 164002 */ // Label 2429: @164002
55285 /* 164002 */ GIM_Reject,
55286 /* 164003 */ // Label 2425: @164003
55287 /* 164003 */ GIM_Reject,
55288 /* 164004 */ // Label 2416: @164004
55289 /* 164004 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(164081),
55290 /* 164009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
55291 /* 164012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
55292 /* 164015 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
55293 /* 164018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
55294 /* 164022 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(164059), // Rule ID 1000 //
55295 /* 164027 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
55296 /* 164030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
55297 /* 164034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
55298 /* 164038 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128,
55299 /* 164042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55300 /* 164044 */ // (fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi)) => (XSMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
55301 /* 164044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBQP),
55302 /* 164047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
55303 /* 164049 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RSTi
55304 /* 164053 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
55305 /* 164055 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
55306 /* 164057 */ GIR_RootConstrainSelectedInstOperands,
55307 /* 164058 */ // GIR_Coverage, 1000,
55308 /* 164058 */ GIR_EraseRootFromParent_Done,
55309 /* 164059 */ // Label 2431: @164059
55310 /* 164059 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(164080), // Rule ID 998 //
55311 /* 164064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
55312 /* 164067 */ // (fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi) => (XSMADDQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
55313 /* 164067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDQP),
55314 /* 164070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
55315 /* 164072 */ GIR_RootToRootCopy, /*OpIdx*/3, // RSTi
55316 /* 164074 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
55317 /* 164076 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
55318 /* 164078 */ GIR_RootConstrainSelectedInstOperands,
55319 /* 164079 */ // GIR_Coverage, 998,
55320 /* 164079 */ GIR_EraseRootFromParent_Done,
55321 /* 164080 */ // Label 2432: @164080
55322 /* 164080 */ GIM_Reject,
55323 /* 164081 */ // Label 2430: @164081
55324 /* 164081 */ GIM_Reject,
55325 /* 164082 */ // Label 2417: @164082
55326 /* 164082 */ GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(164159),
55327 /* 164087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
55328 /* 164090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
55329 /* 164093 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
55330 /* 164096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
55331 /* 164100 */ GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(164137), // Rule ID 800 //
55332 /* 164105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55333 /* 164108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
55334 /* 164112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
55335 /* 164116 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
55336 /* 164120 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55337 /* 164122 */ // (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi)) => (XVMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
55338 /* 164122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMSUBADP),
55339 /* 164125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55340 /* 164127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi
55341 /* 164131 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
55342 /* 164133 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
55343 /* 164135 */ GIR_RootConstrainSelectedInstOperands,
55344 /* 164136 */ // GIR_Coverage, 800,
55345 /* 164136 */ GIR_EraseRootFromParent_Done,
55346 /* 164137 */ // Label 2434: @164137
55347 /* 164137 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(164158), // Rule ID 796 //
55348 /* 164142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55349 /* 164145 */ // (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi) => (XVMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
55350 /* 164145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMADDADP),
55351 /* 164148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55352 /* 164150 */ GIR_RootToRootCopy, /*OpIdx*/3, // XTi
55353 /* 164152 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
55354 /* 164154 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
55355 /* 164156 */ GIR_RootConstrainSelectedInstOperands,
55356 /* 164157 */ // GIR_Coverage, 796,
55357 /* 164157 */ GIR_EraseRootFromParent_Done,
55358 /* 164158 */ // Label 2435: @164158
55359 /* 164158 */ GIM_Reject,
55360 /* 164159 */ // Label 2433: @164159
55361 /* 164159 */ GIM_Reject,
55362 /* 164160 */ // Label 2418: @164160
55363 /* 164160 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(164260),
55364 /* 164165 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
55365 /* 164168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
55366 /* 164171 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
55367 /* 164174 */ GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(164215), // Rule ID 802 //
55368 /* 164179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55369 /* 164182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
55370 /* 164186 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
55371 /* 164190 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
55372 /* 164194 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
55373 /* 164198 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55374 /* 164200 */ // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi)) => (XVMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
55375 /* 164200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMSUBASP),
55376 /* 164203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55377 /* 164205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi
55378 /* 164209 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
55379 /* 164211 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
55380 /* 164213 */ GIR_RootConstrainSelectedInstOperands,
55381 /* 164214 */ // GIR_Coverage, 802,
55382 /* 164214 */ GIR_EraseRootFromParent_Done,
55383 /* 164215 */ // Label 2437: @164215
55384 /* 164215 */ GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(164240), // Rule ID 798 //
55385 /* 164220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55386 /* 164223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
55387 /* 164227 */ // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi) => (XVMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
55388 /* 164227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMADDASP),
55389 /* 164230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55390 /* 164232 */ GIR_RootToRootCopy, /*OpIdx*/3, // XTi
55391 /* 164234 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
55392 /* 164236 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
55393 /* 164238 */ GIR_RootConstrainSelectedInstOperands,
55394 /* 164239 */ // GIR_Coverage, 798,
55395 /* 164239 */ GIR_EraseRootFromParent_Done,
55396 /* 164240 */ // Label 2438: @164240
55397 /* 164240 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(164259), // Rule ID 292 //
55398 /* 164245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
55399 /* 164248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
55400 /* 164252 */ // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RA, v4f32:{ *:[v4f32] }:$RC, v4f32:{ *:[v4f32] }:$RB) => (VMADDFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RA, v4f32:{ *:[v4f32] }:$RC, v4f32:{ *:[v4f32] }:$RB)
55401 /* 164252 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMADDFP),
55402 /* 164257 */ GIR_RootConstrainSelectedInstOperands,
55403 /* 164258 */ // GIR_Coverage, 292,
55404 /* 164258 */ GIR_Done,
55405 /* 164259 */ // Label 2439: @164259
55406 /* 164259 */ GIM_Reject,
55407 /* 164260 */ // Label 2436: @164260
55408 /* 164260 */ GIM_Reject,
55409 /* 164261 */ // Label 2419: @164261
55410 /* 164261 */ GIM_Reject,
55411 /* 164262 */ // Label 44: @164262
55412 /* 164262 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2445*/ GIMT_Encode4(164531),
55413 /* 164273 */ /*GILLT_s32*//*Label 2440*/ GIMT_Encode4(164293),
55414 /* 164277 */ /*GILLT_s64*//*Label 2441*/ GIMT_Encode4(164367),
55415 /* 164281 */ /*GILLT_s128*//*Label 2442*/ GIMT_Encode4(164445),
55416 /* 164285 */ /*GILLT_v2s64*//*Label 2443*/ GIMT_Encode4(164471),
55417 /* 164289 */ /*GILLT_v4s32*//*Label 2444*/ GIMT_Encode4(164501),
55418 /* 164293 */ // Label 2440: @164293
55419 /* 164293 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(164366),
55420 /* 164298 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
55421 /* 164301 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55422 /* 164304 */ GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(164323), // Rule ID 959 //
55423 /* 164309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55424 /* 164312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55425 /* 164316 */ // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSDIVSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
55426 /* 164316 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVSP),
55427 /* 164321 */ GIR_RootConstrainSelectedInstOperands,
55428 /* 164322 */ // GIR_Coverage, 959,
55429 /* 164322 */ GIR_Done,
55430 /* 164323 */ // Label 2447: @164323
55431 /* 164323 */ GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(164346), // Rule ID 243 //
55432 /* 164328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55433 /* 164331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55434 /* 164335 */ // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FDIVS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB)
55435 /* 164335 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FDIVS),
55436 /* 164340 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55437 /* 164344 */ GIR_RootConstrainSelectedInstOperands,
55438 /* 164345 */ // GIR_Coverage, 243,
55439 /* 164345 */ GIR_Done,
55440 /* 164346 */ // Label 2448: @164346
55441 /* 164346 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(164365), // Rule ID 595 //
55442 /* 164351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
55443 /* 164354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
55444 /* 164358 */ // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSDIV:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
55445 /* 164358 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSDIV),
55446 /* 164363 */ GIR_RootConstrainSelectedInstOperands,
55447 /* 164364 */ // GIR_Coverage, 595,
55448 /* 164364 */ GIR_Done,
55449 /* 164365 */ // Label 2449: @164365
55450 /* 164365 */ GIM_Reject,
55451 /* 164366 */ // Label 2446: @164366
55452 /* 164366 */ GIM_Reject,
55453 /* 164367 */ // Label 2441: @164367
55454 /* 164367 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(164444),
55455 /* 164372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
55456 /* 164375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55457 /* 164378 */ GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(164401), // Rule ID 811 //
55458 /* 164383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55459 /* 164386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55460 /* 164390 */ // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSDIVDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
55461 /* 164390 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVDP),
55462 /* 164395 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55463 /* 164399 */ GIR_RootConstrainSelectedInstOperands,
55464 /* 164400 */ // GIR_Coverage, 811,
55465 /* 164400 */ GIR_Done,
55466 /* 164401 */ // Label 2451: @164401
55467 /* 164401 */ GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(164424), // Rule ID 241 //
55468 /* 164406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55469 /* 164409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
55470 /* 164413 */ // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FDIV:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB)
55471 /* 164413 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FDIV),
55472 /* 164418 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55473 /* 164422 */ GIR_RootConstrainSelectedInstOperands,
55474 /* 164423 */ // GIR_Coverage, 241,
55475 /* 164423 */ GIR_Done,
55476 /* 164424 */ // Label 2452: @164424
55477 /* 164424 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(164443), // Rule ID 574 //
55478 /* 164429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
55479 /* 164432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
55480 /* 164436 */ // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDDIV:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
55481 /* 164436 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDDIV),
55482 /* 164441 */ GIR_RootConstrainSelectedInstOperands,
55483 /* 164442 */ // GIR_Coverage, 574,
55484 /* 164442 */ GIR_Done,
55485 /* 164443 */ // Label 2453: @164443
55486 /* 164443 */ GIM_Reject,
55487 /* 164444 */ // Label 2450: @164444
55488 /* 164444 */ GIM_Reject,
55489 /* 164445 */ // Label 2442: @164445
55490 /* 164445 */ GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(164470), // Rule ID 994 //
55491 /* 164450 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
55492 /* 164453 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
55493 /* 164456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
55494 /* 164459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
55495 /* 164463 */ // (fdiv:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSDIVQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
55496 /* 164463 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVQP),
55497 /* 164468 */ GIR_RootConstrainSelectedInstOperands,
55498 /* 164469 */ // GIR_Coverage, 994,
55499 /* 164469 */ GIR_Done,
55500 /* 164470 */ // Label 2454: @164470
55501 /* 164470 */ GIM_Reject,
55502 /* 164471 */ // Label 2443: @164471
55503 /* 164471 */ GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(164500), // Rule ID 820 //
55504 /* 164476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55505 /* 164479 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
55506 /* 164482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
55507 /* 164485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
55508 /* 164489 */ // (fdiv:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVDIVDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
55509 /* 164489 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVDIVDP),
55510 /* 164494 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55511 /* 164498 */ GIR_RootConstrainSelectedInstOperands,
55512 /* 164499 */ // GIR_Coverage, 820,
55513 /* 164499 */ GIR_Done,
55514 /* 164500 */ // Label 2455: @164500
55515 /* 164500 */ GIM_Reject,
55516 /* 164501 */ // Label 2444: @164501
55517 /* 164501 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(164530), // Rule ID 822 //
55518 /* 164506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55519 /* 164509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
55520 /* 164512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
55521 /* 164515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
55522 /* 164519 */ // (fdiv:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVDIVSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
55523 /* 164519 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVDIVSP),
55524 /* 164524 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55525 /* 164528 */ GIR_RootConstrainSelectedInstOperands,
55526 /* 164529 */ // GIR_Coverage, 822,
55527 /* 164529 */ GIR_Done,
55528 /* 164530 */ // Label 2456: @164530
55529 /* 164530 */ GIM_Reject,
55530 /* 164531 */ // Label 2445: @164531
55531 /* 164531 */ GIM_Reject,
55532 /* 164532 */ // Label 45: @164532
55533 /* 164532 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2462*/ GIMT_Encode4(167002),
55534 /* 164543 */ /*GILLT_s32*//*Label 2457*/ GIMT_Encode4(164563),
55535 /* 164547 */ /*GILLT_s64*//*Label 2458*/ GIMT_Encode4(165336),
55536 /* 164551 */ /*GILLT_s128*//*Label 2459*/ GIMT_Encode4(165990),
55537 /* 164555 */ /*GILLT_v2s64*//*Label 2460*/ GIMT_Encode4(166398),
55538 /* 164559 */ /*GILLT_v4s32*//*Label 2461*/ GIMT_Encode4(166684),
55539 /* 164563 */ // Label 2457: @164563
55540 /* 164563 */ GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(165335),
55541 /* 164568 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
55542 /* 164571 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(164636), // Rule ID 973 //
55543 /* 164576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55544 /* 164579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55545 /* 164583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55546 /* 164587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
55547 /* 164591 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55548 /* 164595 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
55549 /* 164599 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
55550 /* 164603 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
55551 /* 164607 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
55552 /* 164611 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
55553 /* 164615 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
55554 /* 164617 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi))) => (XSNMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
55555 /* 164617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBASP),
55556 /* 164620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55557 /* 164622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi
55558 /* 164626 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
55559 /* 164630 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
55560 /* 164634 */ GIR_RootConstrainSelectedInstOperands,
55561 /* 164635 */ // GIR_Coverage, 973,
55562 /* 164635 */ GIR_EraseRootFromParent_Done,
55563 /* 164636 */ // Label 2464: @164636
55564 /* 164636 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(164701), // Rule ID 972 //
55565 /* 164641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55566 /* 164644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55567 /* 164648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55568 /* 164652 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
55569 /* 164656 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55570 /* 164660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
55571 /* 164664 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
55572 /* 164668 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
55573 /* 164672 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
55574 /* 164676 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
55575 /* 164680 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
55576 /* 164682 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi))) => (XSNMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
55577 /* 164682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBASP),
55578 /* 164685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55579 /* 164687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi
55580 /* 164691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
55581 /* 164695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
55582 /* 164699 */ GIR_RootConstrainSelectedInstOperands,
55583 /* 164700 */ // GIR_Coverage, 972,
55584 /* 164700 */ GIR_EraseRootFromParent_Done,
55585 /* 164701 */ // Label 2465: @164701
55586 /* 164701 */ GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(164754), // Rule ID 971 //
55587 /* 164706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55588 /* 164709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55589 /* 164713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55590 /* 164717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
55591 /* 164721 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55592 /* 164725 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
55593 /* 164729 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
55594 /* 164733 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55595 /* 164735 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi)) => (XSNMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
55596 /* 164735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDASP),
55597 /* 164738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55598 /* 164740 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi
55599 /* 164744 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
55600 /* 164748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
55601 /* 164752 */ GIR_RootConstrainSelectedInstOperands,
55602 /* 164753 */ // GIR_Coverage, 971,
55603 /* 164753 */ GIR_EraseRootFromParent_Done,
55604 /* 164754 */ // Label 2466: @164754
55605 /* 164754 */ GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(164807), // Rule ID 970 //
55606 /* 164759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55607 /* 164762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55608 /* 164766 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55609 /* 164770 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
55610 /* 164774 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55611 /* 164778 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
55612 /* 164782 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
55613 /* 164786 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55614 /* 164788 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi)) => (XSNMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
55615 /* 164788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDASP),
55616 /* 164791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55617 /* 164793 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi
55618 /* 164797 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
55619 /* 164801 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
55620 /* 164805 */ GIR_RootConstrainSelectedInstOperands,
55621 /* 164806 */ // GIR_Coverage, 970,
55622 /* 164806 */ GIR_EraseRootFromParent_Done,
55623 /* 164807 */ // Label 2467: @164807
55624 /* 164807 */ GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(164844), // Rule ID 845 //
55625 /* 164812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55626 /* 164815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55627 /* 164819 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55628 /* 164823 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
55629 /* 164827 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55630 /* 164831 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55631 /* 164833 */ // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$XB)) => (XSNABSDPs:{ *:[f32] } f32:{ *:[f32] }:$XB)
55632 /* 164833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDPs),
55633 /* 164836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55634 /* 164838 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB
55635 /* 164842 */ GIR_RootConstrainSelectedInstOperands,
55636 /* 164843 */ // GIR_Coverage, 845,
55637 /* 164843 */ GIR_EraseRootFromParent_Done,
55638 /* 164844 */ // Label 2468: @164844
55639 /* 164844 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(164922), // Rule ID 1685 //
55640 /* 164849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55641 /* 164852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55642 /* 164856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55643 /* 164860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
55644 /* 164864 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55645 /* 164868 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55646 /* 164870 */ // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$S)) => (COPY_TO_REGCLASS:{ *:[f32] } (XSNABSDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
55647 /* 164870 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
55648 /* 164873 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
55649 /* 164877 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
55650 /* 164882 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // S
55651 /* 164886 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
55652 /* 164891 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
55653 /* 164894 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSNABSDP),
55654 /* 164898 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
55655 /* 164903 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
55656 /* 164906 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
55657 /* 164908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
55658 /* 164911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
55659 /* 164913 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
55660 /* 164916 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
55661 /* 164921 */ // GIR_Coverage, 1685,
55662 /* 164921 */ GIR_EraseRootFromParent_Done,
55663 /* 164922 */ // Label 2469: @164922
55664 /* 164922 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(164986), // Rule ID 1926 //
55665 /* 164927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
55666 /* 164930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
55667 /* 164934 */ // (fneg:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSNEGDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
55668 /* 164934 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
55669 /* 164937 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
55670 /* 164941 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
55671 /* 164946 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
55672 /* 164950 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
55673 /* 164955 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
55674 /* 164958 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSNEGDP),
55675 /* 164962 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
55676 /* 164967 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
55677 /* 164970 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
55678 /* 164972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
55679 /* 164975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
55680 /* 164977 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
55681 /* 164980 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
55682 /* 164985 */ // GIR_Coverage, 1926,
55683 /* 164985 */ GIR_EraseRootFromParent_Done,
55684 /* 164986 */ // Label 2470: @164986
55685 /* 164986 */ GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(165051), // Rule ID 233 //
55686 /* 164991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55687 /* 164994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55688 /* 164998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55689 /* 165002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
55690 /* 165006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55691 /* 165010 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
55692 /* 165014 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
55693 /* 165018 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
55694 /* 165022 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
55695 /* 165026 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
55696 /* 165030 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
55697 /* 165032 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB))) => (FNMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)
55698 /* 165032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMSUBS),
55699 /* 165035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55700 /* 165037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA
55701 /* 165041 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC
55702 /* 165045 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB
55703 /* 165049 */ GIR_RootConstrainSelectedInstOperands,
55704 /* 165050 */ // GIR_Coverage, 233,
55705 /* 165050 */ GIR_EraseRootFromParent_Done,
55706 /* 165051 */ // Label 2471: @165051
55707 /* 165051 */ GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(165116), // Rule ID 232 //
55708 /* 165056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55709 /* 165059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55710 /* 165063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55711 /* 165067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
55712 /* 165071 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55713 /* 165075 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
55714 /* 165079 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
55715 /* 165083 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
55716 /* 165087 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
55717 /* 165091 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
55718 /* 165095 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
55719 /* 165097 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB))) => (FNMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)
55720 /* 165097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMSUBS),
55721 /* 165100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55722 /* 165102 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA
55723 /* 165106 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC
55724 /* 165110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB
55725 /* 165114 */ GIR_RootConstrainSelectedInstOperands,
55726 /* 165115 */ // GIR_Coverage, 232,
55727 /* 165115 */ GIR_EraseRootFromParent_Done,
55728 /* 165116 */ // Label 2472: @165116
55729 /* 165116 */ GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(165169), // Rule ID 229 //
55730 /* 165121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55731 /* 165124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55732 /* 165128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55733 /* 165132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
55734 /* 165136 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55735 /* 165140 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
55736 /* 165144 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
55737 /* 165148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55738 /* 165150 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)) => (FNMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)
55739 /* 165150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADDS),
55740 /* 165153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55741 /* 165155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA
55742 /* 165159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC
55743 /* 165163 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB
55744 /* 165167 */ GIR_RootConstrainSelectedInstOperands,
55745 /* 165168 */ // GIR_Coverage, 229,
55746 /* 165168 */ GIR_EraseRootFromParent_Done,
55747 /* 165169 */ // Label 2473: @165169
55748 /* 165169 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(165222), // Rule ID 228 //
55749 /* 165174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55750 /* 165177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55751 /* 165181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55752 /* 165185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
55753 /* 165189 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55754 /* 165193 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
55755 /* 165197 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
55756 /* 165201 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55757 /* 165203 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)) => (FNMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)
55758 /* 165203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADDS),
55759 /* 165206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55760 /* 165208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA
55761 /* 165212 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC
55762 /* 165216 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB
55763 /* 165220 */ GIR_RootConstrainSelectedInstOperands,
55764 /* 165221 */ // GIR_Coverage, 228,
55765 /* 165221 */ GIR_EraseRootFromParent_Done,
55766 /* 165222 */ // Label 2474: @165222
55767 /* 165222 */ GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(165259), // Rule ID 165 //
55768 /* 165227 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55769 /* 165230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55770 /* 165234 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55771 /* 165238 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
55772 /* 165242 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55773 /* 165246 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55774 /* 165248 */ // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$RB)) => (FNABSS:{ *:[f32] } f32:{ *:[f32] }:$RB)
55775 /* 165248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSS),
55776 /* 165251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
55777 /* 165253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
55778 /* 165257 */ GIR_RootConstrainSelectedInstOperands,
55779 /* 165258 */ // GIR_Coverage, 165,
55780 /* 165258 */ GIR_EraseRootFromParent_Done,
55781 /* 165259 */ // Label 2475: @165259
55782 /* 165259 */ GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(165296), // Rule ID 598 //
55783 /* 165264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
55784 /* 165267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
55785 /* 165271 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55786 /* 165275 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
55787 /* 165279 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
55788 /* 165283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55789 /* 165285 */ // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$RA)) => (EFSNABS:{ *:[f32] } f32:{ *:[f32] }:$RA)
55790 /* 165285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EFSNABS),
55791 /* 165288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
55792 /* 165290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA
55793 /* 165294 */ GIR_RootConstrainSelectedInstOperands,
55794 /* 165295 */ // GIR_Coverage, 598,
55795 /* 165295 */ GIR_EraseRootFromParent_Done,
55796 /* 165296 */ // Label 2476: @165296
55797 /* 165296 */ GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(165315), // Rule ID 167 //
55798 /* 165301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55799 /* 165304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
55800 /* 165308 */ // (fneg:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FNEGS:{ *:[f32] } f32:{ *:[f32] }:$RB)
55801 /* 165308 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FNEGS),
55802 /* 165313 */ GIR_RootConstrainSelectedInstOperands,
55803 /* 165314 */ // GIR_Coverage, 167,
55804 /* 165314 */ GIR_Done,
55805 /* 165315 */ // Label 2477: @165315
55806 /* 165315 */ GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(165334), // Rule ID 599 //
55807 /* 165320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
55808 /* 165323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
55809 /* 165327 */ // (fneg:{ *:[f32] } f32:{ *:[f32] }:$RA) => (EFSNEG:{ *:[f32] } f32:{ *:[f32] }:$RA)
55810 /* 165327 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSNEG),
55811 /* 165332 */ GIR_RootConstrainSelectedInstOperands,
55812 /* 165333 */ // GIR_Coverage, 599,
55813 /* 165333 */ GIR_Done,
55814 /* 165334 */ // Label 2478: @165334
55815 /* 165334 */ GIM_Reject,
55816 /* 165335 */ // Label 2463: @165335
55817 /* 165335 */ GIM_Reject,
55818 /* 165336 */ // Label 2458: @165336
55819 /* 165336 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(165989),
55820 /* 165341 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
55821 /* 165344 */ GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(165409), // Rule ID 794 //
55822 /* 165349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55823 /* 165352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55824 /* 165356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55825 /* 165360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
55826 /* 165364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55827 /* 165368 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
55828 /* 165372 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
55829 /* 165376 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
55830 /* 165380 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
55831 /* 165384 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
55832 /* 165388 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
55833 /* 165390 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi))) => (XSNMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
55834 /* 165390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBADP),
55835 /* 165393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55836 /* 165395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi
55837 /* 165399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
55838 /* 165403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
55839 /* 165407 */ GIR_RootConstrainSelectedInstOperands,
55840 /* 165408 */ // GIR_Coverage, 794,
55841 /* 165408 */ GIR_EraseRootFromParent_Done,
55842 /* 165409 */ // Label 2480: @165409
55843 /* 165409 */ GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(165474), // Rule ID 793 //
55844 /* 165414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55845 /* 165417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55846 /* 165421 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55847 /* 165425 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
55848 /* 165429 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55849 /* 165433 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
55850 /* 165437 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
55851 /* 165441 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
55852 /* 165445 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
55853 /* 165449 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
55854 /* 165453 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
55855 /* 165455 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi))) => (XSNMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
55856 /* 165455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBADP),
55857 /* 165458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55858 /* 165460 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi
55859 /* 165464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
55860 /* 165468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
55861 /* 165472 */ GIR_RootConstrainSelectedInstOperands,
55862 /* 165473 */ // GIR_Coverage, 793,
55863 /* 165473 */ GIR_EraseRootFromParent_Done,
55864 /* 165474 */ // Label 2481: @165474
55865 /* 165474 */ GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(165527), // Rule ID 792 //
55866 /* 165479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55867 /* 165482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55868 /* 165486 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55869 /* 165490 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
55870 /* 165494 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55871 /* 165498 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
55872 /* 165502 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
55873 /* 165506 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55874 /* 165508 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi)) => (XSNMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
55875 /* 165508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDADP),
55876 /* 165511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55877 /* 165513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi
55878 /* 165517 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
55879 /* 165521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
55880 /* 165525 */ GIR_RootConstrainSelectedInstOperands,
55881 /* 165526 */ // GIR_Coverage, 792,
55882 /* 165526 */ GIR_EraseRootFromParent_Done,
55883 /* 165527 */ // Label 2482: @165527
55884 /* 165527 */ GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(165580), // Rule ID 791 //
55885 /* 165532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55886 /* 165535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55887 /* 165539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55888 /* 165543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
55889 /* 165547 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55890 /* 165551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
55891 /* 165555 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
55892 /* 165559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55893 /* 165561 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi)) => (XSNMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
55894 /* 165561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDADP),
55895 /* 165564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55896 /* 165566 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi
55897 /* 165570 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
55898 /* 165574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
55899 /* 165578 */ GIR_RootConstrainSelectedInstOperands,
55900 /* 165579 */ // GIR_Coverage, 791,
55901 /* 165579 */ GIR_EraseRootFromParent_Done,
55902 /* 165580 */ // Label 2483: @165580
55903 /* 165580 */ GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(165617), // Rule ID 844 //
55904 /* 165585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55905 /* 165588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55906 /* 165592 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55907 /* 165596 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
55908 /* 165600 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55909 /* 165604 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55910 /* 165606 */ // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$XB)) => (XSNABSDP:{ *:[f64] } f64:{ *:[f64] }:$XB)
55911 /* 165606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDP),
55912 /* 165609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
55913 /* 165611 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB
55914 /* 165615 */ GIR_RootConstrainSelectedInstOperands,
55915 /* 165616 */ // GIR_Coverage, 844,
55916 /* 165616 */ GIR_EraseRootFromParent_Done,
55917 /* 165617 */ // Label 2484: @165617
55918 /* 165617 */ GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(165640), // Rule ID 846 //
55919 /* 165622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
55920 /* 165625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
55921 /* 165629 */ // (fneg:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSNEGDP:{ *:[f64] } f64:{ *:[f64] }:$XB)
55922 /* 165629 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSNEGDP),
55923 /* 165634 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
55924 /* 165638 */ GIR_RootConstrainSelectedInstOperands,
55925 /* 165639 */ // GIR_Coverage, 846,
55926 /* 165639 */ GIR_Done,
55927 /* 165640 */ // Label 2485: @165640
55928 /* 165640 */ GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(165705), // Rule ID 231 //
55929 /* 165645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55930 /* 165648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
55931 /* 165652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55932 /* 165656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
55933 /* 165660 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55934 /* 165664 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
55935 /* 165668 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
55936 /* 165672 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
55937 /* 165676 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
55938 /* 165680 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
55939 /* 165684 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
55940 /* 165686 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB))) => (FNMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)
55941 /* 165686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMSUB),
55942 /* 165689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55943 /* 165691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA
55944 /* 165695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC
55945 /* 165699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB
55946 /* 165703 */ GIR_RootConstrainSelectedInstOperands,
55947 /* 165704 */ // GIR_Coverage, 231,
55948 /* 165704 */ GIR_EraseRootFromParent_Done,
55949 /* 165705 */ // Label 2486: @165705
55950 /* 165705 */ GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(165770), // Rule ID 230 //
55951 /* 165710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55952 /* 165713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
55953 /* 165717 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55954 /* 165721 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
55955 /* 165725 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55956 /* 165729 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
55957 /* 165733 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
55958 /* 165737 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
55959 /* 165741 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
55960 /* 165745 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
55961 /* 165749 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
55962 /* 165751 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB))) => (FNMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)
55963 /* 165751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMSUB),
55964 /* 165754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55965 /* 165756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA
55966 /* 165760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC
55967 /* 165764 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB
55968 /* 165768 */ GIR_RootConstrainSelectedInstOperands,
55969 /* 165769 */ // GIR_Coverage, 230,
55970 /* 165769 */ GIR_EraseRootFromParent_Done,
55971 /* 165770 */ // Label 2487: @165770
55972 /* 165770 */ GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(165823), // Rule ID 227 //
55973 /* 165775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55974 /* 165778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
55975 /* 165782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55976 /* 165786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
55977 /* 165790 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55978 /* 165794 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
55979 /* 165798 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
55980 /* 165802 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
55981 /* 165804 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)) => (FNMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)
55982 /* 165804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADD),
55983 /* 165807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
55984 /* 165809 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA
55985 /* 165813 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC
55986 /* 165817 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB
55987 /* 165821 */ GIR_RootConstrainSelectedInstOperands,
55988 /* 165822 */ // GIR_Coverage, 227,
55989 /* 165822 */ GIR_EraseRootFromParent_Done,
55990 /* 165823 */ // Label 2488: @165823
55991 /* 165823 */ GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(165876), // Rule ID 226 //
55992 /* 165828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
55993 /* 165831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
55994 /* 165835 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
55995 /* 165839 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
55996 /* 165843 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
55997 /* 165847 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
55998 /* 165851 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
55999 /* 165855 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56000 /* 165857 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)) => (FNMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)
56001 /* 165857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADD),
56002 /* 165860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
56003 /* 165862 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA
56004 /* 165866 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC
56005 /* 165870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB
56006 /* 165874 */ GIR_RootConstrainSelectedInstOperands,
56007 /* 165875 */ // GIR_Coverage, 226,
56008 /* 165875 */ GIR_EraseRootFromParent_Done,
56009 /* 165876 */ // Label 2489: @165876
56010 /* 165876 */ GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(165913), // Rule ID 166 //
56011 /* 165881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
56012 /* 165884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
56013 /* 165888 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56014 /* 165892 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
56015 /* 165896 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
56016 /* 165900 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56017 /* 165902 */ // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$RB)) => (FNABSD:{ *:[f64] } f64:{ *:[f64] }:$RB)
56018 /* 165902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSD),
56019 /* 165905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56020 /* 165907 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
56021 /* 165911 */ GIR_RootConstrainSelectedInstOperands,
56022 /* 165912 */ // GIR_Coverage, 166,
56023 /* 165912 */ GIR_EraseRootFromParent_Done,
56024 /* 165913 */ // Label 2490: @165913
56025 /* 165913 */ GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(165950), // Rule ID 577 //
56026 /* 165918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56027 /* 165921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
56028 /* 165925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56029 /* 165929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
56030 /* 165933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
56031 /* 165937 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56032 /* 165939 */ // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$RA)) => (EFDNABS:{ *:[f64] } f64:{ *:[f64] }:$RA)
56033 /* 165939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EFDNABS),
56034 /* 165942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
56035 /* 165944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA
56036 /* 165948 */ GIR_RootConstrainSelectedInstOperands,
56037 /* 165949 */ // GIR_Coverage, 577,
56038 /* 165949 */ GIR_EraseRootFromParent_Done,
56039 /* 165950 */ // Label 2491: @165950
56040 /* 165950 */ GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(165969), // Rule ID 168 //
56041 /* 165955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
56042 /* 165958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
56043 /* 165962 */ // (fneg:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FNEGD:{ *:[f64] } f64:{ *:[f64] }:$RB)
56044 /* 165962 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FNEGD),
56045 /* 165967 */ GIR_RootConstrainSelectedInstOperands,
56046 /* 165968 */ // GIR_Coverage, 168,
56047 /* 165968 */ GIR_Done,
56048 /* 165969 */ // Label 2492: @165969
56049 /* 165969 */ GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(165988), // Rule ID 578 //
56050 /* 165974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56051 /* 165977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
56052 /* 165981 */ // (fneg:{ *:[f64] } f64:{ *:[f64] }:$RA) => (EFDNEG:{ *:[f64] } f64:{ *:[f64] }:$RA)
56053 /* 165981 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDNEG),
56054 /* 165986 */ GIR_RootConstrainSelectedInstOperands,
56055 /* 165987 */ // GIR_Coverage, 578,
56056 /* 165987 */ GIR_Done,
56057 /* 165988 */ // Label 2493: @165988
56058 /* 165988 */ GIM_Reject,
56059 /* 165989 */ // Label 2479: @165989
56060 /* 165989 */ GIM_Reject,
56061 /* 165990 */ // Label 2459: @165990
56062 /* 165990 */ GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(166397),
56063 /* 165995 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
56064 /* 165998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56065 /* 166002 */ GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(166071), // Rule ID 1013 //
56066 /* 166007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56067 /* 166010 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56068 /* 166014 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
56069 /* 166018 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5,
56070 /* 166021 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd),
56071 /* 166026 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
56072 /* 166030 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
56073 /* 166034 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_s128,
56074 /* 166038 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/4, // MIs[2]
56075 /* 166042 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
56076 /* 166046 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128,
56077 /* 166050 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
56078 /* 166052 */ // (fneg:{ *:[f128] } (intrinsic_wo_chain:{ *:[f128] } 10640:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi))) => (XSNMSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
56079 /* 166052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBQPO),
56080 /* 166055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56081 /* 166057 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RSTi
56082 /* 166061 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RA
56083 /* 166065 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // RB
56084 /* 166069 */ GIR_RootConstrainSelectedInstOperands,
56085 /* 166070 */ // GIR_Coverage, 1013,
56086 /* 166070 */ GIR_EraseRootFromParent_Done,
56087 /* 166071 */ // Label 2495: @166071
56088 /* 166071 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(166128), // Rule ID 1012 //
56089 /* 166076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56090 /* 166079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56091 /* 166083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
56092 /* 166087 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5,
56093 /* 166090 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd),
56094 /* 166095 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
56095 /* 166099 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
56096 /* 166103 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_s128,
56097 /* 166107 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56098 /* 166109 */ // (fneg:{ *:[f128] } (intrinsic_wo_chain:{ *:[f128] } 10640:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi)) => (XSNMADDQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
56099 /* 166109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDQPO),
56100 /* 166112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56101 /* 166114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // RSTi
56102 /* 166118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RA
56103 /* 166122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // RB
56104 /* 166126 */ GIR_RootConstrainSelectedInstOperands,
56105 /* 166127 */ // GIR_Coverage, 1012,
56106 /* 166127 */ GIR_EraseRootFromParent_Done,
56107 /* 166128 */ // Label 2496: @166128
56108 /* 166128 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(166189), // Rule ID 1004 //
56109 /* 166133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56110 /* 166136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56111 /* 166140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
56112 /* 166144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128,
56113 /* 166148 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
56114 /* 166152 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
56115 /* 166156 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
56116 /* 166160 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
56117 /* 166164 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128,
56118 /* 166168 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
56119 /* 166170 */ // (fneg:{ *:[f128] } (fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi))) => (XSNMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
56120 /* 166170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBQP),
56121 /* 166173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56122 /* 166175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RSTi
56123 /* 166179 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA
56124 /* 166183 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
56125 /* 166187 */ GIR_RootConstrainSelectedInstOperands,
56126 /* 166188 */ // GIR_Coverage, 1004,
56127 /* 166188 */ GIR_EraseRootFromParent_Done,
56128 /* 166189 */ // Label 2497: @166189
56129 /* 166189 */ GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(166250), // Rule ID 1003 //
56130 /* 166194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56131 /* 166197 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56132 /* 166201 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
56133 /* 166205 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128,
56134 /* 166209 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
56135 /* 166213 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
56136 /* 166217 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
56137 /* 166221 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
56138 /* 166225 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128,
56139 /* 166229 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
56140 /* 166231 */ // (fneg:{ *:[f128] } (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi))) => (XSNMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
56141 /* 166231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBQP),
56142 /* 166234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56143 /* 166236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RSTi
56144 /* 166240 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA
56145 /* 166244 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
56146 /* 166248 */ GIR_RootConstrainSelectedInstOperands,
56147 /* 166249 */ // GIR_Coverage, 1003,
56148 /* 166249 */ GIR_EraseRootFromParent_Done,
56149 /* 166250 */ // Label 2498: @166250
56150 /* 166250 */ GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(166299), // Rule ID 1002 //
56151 /* 166255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56152 /* 166258 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56153 /* 166262 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
56154 /* 166266 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128,
56155 /* 166270 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
56156 /* 166274 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
56157 /* 166278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56158 /* 166280 */ // (fneg:{ *:[f128] } (fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi)) => (XSNMADDQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
56159 /* 166280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDQP),
56160 /* 166283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56161 /* 166285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // RSTi
56162 /* 166289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA
56163 /* 166293 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
56164 /* 166297 */ GIR_RootConstrainSelectedInstOperands,
56165 /* 166298 */ // GIR_Coverage, 1002,
56166 /* 166298 */ GIR_EraseRootFromParent_Done,
56167 /* 166299 */ // Label 2499: @166299
56168 /* 166299 */ GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(166348), // Rule ID 1001 //
56169 /* 166304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56170 /* 166307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56171 /* 166311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
56172 /* 166315 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128,
56173 /* 166319 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128,
56174 /* 166323 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128,
56175 /* 166327 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56176 /* 166329 */ // (fneg:{ *:[f128] } (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi)) => (XSNMADDQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
56177 /* 166329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDQP),
56178 /* 166332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56179 /* 166334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // RSTi
56180 /* 166338 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA
56181 /* 166342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB
56182 /* 166346 */ GIR_RootConstrainSelectedInstOperands,
56183 /* 166347 */ // GIR_Coverage, 1001,
56184 /* 166347 */ GIR_EraseRootFromParent_Done,
56185 /* 166348 */ // Label 2500: @166348
56186 /* 166348 */ GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(166381), // Rule ID 985 //
56187 /* 166353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56188 /* 166356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56189 /* 166360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
56190 /* 166364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128,
56191 /* 166368 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56192 /* 166370 */ // (fneg:{ *:[f128] } (fabs:{ *:[f128] } f128:{ *:[f128] }:$RB)) => (XSNABSQP:{ *:[f128] } f128:{ *:[f128] }:$RB)
56193 /* 166370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSQP),
56194 /* 166373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56195 /* 166375 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB
56196 /* 166379 */ GIR_RootConstrainSelectedInstOperands,
56197 /* 166380 */ // GIR_Coverage, 985,
56198 /* 166380 */ GIR_EraseRootFromParent_Done,
56199 /* 166381 */ // Label 2501: @166381
56200 /* 166381 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(166396), // Rule ID 986 //
56201 /* 166386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56202 /* 166389 */ // (fneg:{ *:[f128] } f128:{ *:[f128] }:$RB) => (XSNEGQP:{ *:[f128] } f128:{ *:[f128] }:$RB)
56203 /* 166389 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSNEGQP),
56204 /* 166394 */ GIR_RootConstrainSelectedInstOperands,
56205 /* 166395 */ // GIR_Coverage, 986,
56206 /* 166395 */ GIR_Done,
56207 /* 166396 */ // Label 2502: @166396
56208 /* 166396 */ GIM_Reject,
56209 /* 166397 */ // Label 2494: @166397
56210 /* 166397 */ GIM_Reject,
56211 /* 166398 */ // Label 2460: @166398
56212 /* 166398 */ GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(166683),
56213 /* 166403 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
56214 /* 166406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56215 /* 166410 */ GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(166471), // Rule ID 807 //
56216 /* 166415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56217 /* 166418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56218 /* 166422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
56219 /* 166426 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
56220 /* 166430 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
56221 /* 166434 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
56222 /* 166438 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
56223 /* 166442 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
56224 /* 166446 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
56225 /* 166450 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
56226 /* 166452 */ // (fneg:{ *:[v2f64] } (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi))) => (XVNMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
56227 /* 166452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMSUBADP),
56228 /* 166455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56229 /* 166457 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi
56230 /* 166461 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
56231 /* 166465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
56232 /* 166469 */ GIR_RootConstrainSelectedInstOperands,
56233 /* 166470 */ // GIR_Coverage, 807,
56234 /* 166470 */ GIR_EraseRootFromParent_Done,
56235 /* 166471 */ // Label 2504: @166471
56236 /* 166471 */ GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(166532), // Rule ID 806 //
56237 /* 166476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56238 /* 166479 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56239 /* 166483 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
56240 /* 166487 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
56241 /* 166491 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
56242 /* 166495 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
56243 /* 166499 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
56244 /* 166503 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
56245 /* 166507 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
56246 /* 166511 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
56247 /* 166513 */ // (fneg:{ *:[v2f64] } (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi))) => (XVNMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
56248 /* 166513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMSUBADP),
56249 /* 166516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56250 /* 166518 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi
56251 /* 166522 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
56252 /* 166526 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
56253 /* 166530 */ GIR_RootConstrainSelectedInstOperands,
56254 /* 166531 */ // GIR_Coverage, 806,
56255 /* 166531 */ GIR_EraseRootFromParent_Done,
56256 /* 166532 */ // Label 2505: @166532
56257 /* 166532 */ GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(166581), // Rule ID 804 //
56258 /* 166537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56259 /* 166540 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56260 /* 166544 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
56261 /* 166548 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
56262 /* 166552 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
56263 /* 166556 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
56264 /* 166560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56265 /* 166562 */ // (fneg:{ *:[v2f64] } (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi)) => (XVNMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
56266 /* 166562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMADDADP),
56267 /* 166565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56268 /* 166567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi
56269 /* 166571 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
56270 /* 166575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
56271 /* 166579 */ GIR_RootConstrainSelectedInstOperands,
56272 /* 166580 */ // GIR_Coverage, 804,
56273 /* 166580 */ GIR_EraseRootFromParent_Done,
56274 /* 166581 */ // Label 2506: @166581
56275 /* 166581 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(166630), // Rule ID 803 //
56276 /* 166586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56277 /* 166589 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56278 /* 166593 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
56279 /* 166597 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
56280 /* 166601 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
56281 /* 166605 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
56282 /* 166609 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56283 /* 166611 */ // (fneg:{ *:[v2f64] } (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi)) => (XVNMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
56284 /* 166611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMADDADP),
56285 /* 166614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56286 /* 166616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi
56287 /* 166620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
56288 /* 166624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
56289 /* 166628 */ GIR_RootConstrainSelectedInstOperands,
56290 /* 166629 */ // GIR_Coverage, 803,
56291 /* 166629 */ GIR_EraseRootFromParent_Done,
56292 /* 166630 */ // Label 2507: @166630
56293 /* 166630 */ GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(166663), // Rule ID 852 //
56294 /* 166635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56295 /* 166638 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56296 /* 166642 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
56297 /* 166646 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
56298 /* 166650 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56299 /* 166652 */ // (fneg:{ *:[v2f64] } (fabs:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)) => (XVNABSDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
56300 /* 166652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNABSDP),
56301 /* 166655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56302 /* 166657 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB
56303 /* 166661 */ GIR_RootConstrainSelectedInstOperands,
56304 /* 166662 */ // GIR_Coverage, 852,
56305 /* 166662 */ GIR_EraseRootFromParent_Done,
56306 /* 166663 */ // Label 2508: @166663
56307 /* 166663 */ GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(166682), // Rule ID 854 //
56308 /* 166668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56309 /* 166671 */ // (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVNEGDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
56310 /* 166671 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVNEGDP),
56311 /* 166676 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56312 /* 166680 */ GIR_RootConstrainSelectedInstOperands,
56313 /* 166681 */ // GIR_Coverage, 854,
56314 /* 166681 */ GIR_Done,
56315 /* 166682 */ // Label 2509: @166682
56316 /* 166682 */ GIM_Reject,
56317 /* 166683 */ // Label 2503: @166683
56318 /* 166683 */ GIM_Reject,
56319 /* 166684 */ // Label 2461: @166684
56320 /* 166684 */ GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(167001),
56321 /* 166689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
56322 /* 166692 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(166757), // Rule ID 809 //
56323 /* 166697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56324 /* 166700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56325 /* 166704 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56326 /* 166708 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
56327 /* 166712 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
56328 /* 166716 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
56329 /* 166720 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
56330 /* 166724 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
56331 /* 166728 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
56332 /* 166732 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
56333 /* 166736 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
56334 /* 166738 */ // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi))) => (XVNMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
56335 /* 166738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMSUBASP),
56336 /* 166741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56337 /* 166743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi
56338 /* 166747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
56339 /* 166751 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
56340 /* 166755 */ GIR_RootConstrainSelectedInstOperands,
56341 /* 166756 */ // GIR_Coverage, 809,
56342 /* 166756 */ GIR_EraseRootFromParent_Done,
56343 /* 166757 */ // Label 2511: @166757
56344 /* 166757 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(166822), // Rule ID 808 //
56345 /* 166762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56346 /* 166765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56347 /* 166769 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56348 /* 166773 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
56349 /* 166777 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
56350 /* 166781 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
56351 /* 166785 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
56352 /* 166789 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
56353 /* 166793 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
56354 /* 166797 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
56355 /* 166801 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
56356 /* 166803 */ // (fneg:{ *:[v4f32] } (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi))) => (XVNMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
56357 /* 166803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMSUBASP),
56358 /* 166806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56359 /* 166808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi
56360 /* 166812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
56361 /* 166816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
56362 /* 166820 */ GIR_RootConstrainSelectedInstOperands,
56363 /* 166821 */ // GIR_Coverage, 808,
56364 /* 166821 */ GIR_EraseRootFromParent_Done,
56365 /* 166822 */ // Label 2512: @166822
56366 /* 166822 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(166875), // Rule ID 805 //
56367 /* 166827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56368 /* 166830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56369 /* 166834 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56370 /* 166838 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
56371 /* 166842 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
56372 /* 166846 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
56373 /* 166850 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
56374 /* 166854 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56375 /* 166856 */ // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi)) => (XVNMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
56376 /* 166856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMADDASP),
56377 /* 166859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56378 /* 166861 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi
56379 /* 166865 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA
56380 /* 166869 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB
56381 /* 166873 */ GIR_RootConstrainSelectedInstOperands,
56382 /* 166874 */ // GIR_Coverage, 805,
56383 /* 166874 */ GIR_EraseRootFromParent_Done,
56384 /* 166875 */ // Label 2513: @166875
56385 /* 166875 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(166912), // Rule ID 853 //
56386 /* 166880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56387 /* 166883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56388 /* 166887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56389 /* 166891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
56390 /* 166895 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
56391 /* 166899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
56392 /* 166901 */ // (fneg:{ *:[v4f32] } (fabs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)) => (XVNABSSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
56393 /* 166901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNABSSP),
56394 /* 166904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56395 /* 166906 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB
56396 /* 166910 */ GIR_RootConstrainSelectedInstOperands,
56397 /* 166911 */ // GIR_Coverage, 853,
56398 /* 166911 */ GIR_EraseRootFromParent_Done,
56399 /* 166912 */ // Label 2514: @166912
56400 /* 166912 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(166935), // Rule ID 855 //
56401 /* 166917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56402 /* 166920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56403 /* 166924 */ // (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVNEGSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
56404 /* 166924 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVNEGSP),
56405 /* 166929 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56406 /* 166933 */ GIR_RootConstrainSelectedInstOperands,
56407 /* 166934 */ // GIR_Coverage, 855,
56408 /* 166934 */ GIR_Done,
56409 /* 166935 */ // Label 2515: @166935
56410 /* 166935 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(167000), // Rule ID 293 //
56411 /* 166940 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
56412 /* 166943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56413 /* 166947 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
56414 /* 166951 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
56415 /* 166955 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
56416 /* 166959 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
56417 /* 166963 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
56418 /* 166967 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
56419 /* 166971 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
56420 /* 166975 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
56421 /* 166979 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
56422 /* 166981 */ // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RA, v4f32:{ *:[v4f32] }:$RC, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RB))) => (VNMSUBFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RA, v4f32:{ *:[v4f32] }:$RC, v4f32:{ *:[v4f32] }:$RB)
56423 /* 166981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNMSUBFP),
56424 /* 166984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT]
56425 /* 166986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA
56426 /* 166990 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RC
56427 /* 166994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RB
56428 /* 166998 */ GIR_RootConstrainSelectedInstOperands,
56429 /* 166999 */ // GIR_Coverage, 293,
56430 /* 166999 */ GIR_EraseRootFromParent_Done,
56431 /* 167000 */ // Label 2516: @167000
56432 /* 167000 */ GIM_Reject,
56433 /* 167001 */ // Label 2510: @167001
56434 /* 167001 */ GIM_Reject,
56435 /* 167002 */ // Label 2462: @167002
56436 /* 167002 */ GIM_Reject,
56437 /* 167003 */ // Label 46: @167003
56438 /* 167003 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2519*/ GIMT_Encode4(167166),
56439 /* 167014 */ /*GILLT_s64*//*Label 2517*/ GIMT_Encode4(167022),
56440 /* 167018 */ /*GILLT_s128*//*Label 2518*/ GIMT_Encode4(167097),
56441 /* 167022 */ // Label 2517: @167022
56442 /* 167022 */ GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(167096),
56443 /* 167027 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56444 /* 167030 */ GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(167053), // Rule ID 1910 //
56445 /* 167035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
56446 /* 167038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
56447 /* 167042 */ // (fpextend:{ *:[f64] } f32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$src, VSFRC:{ *:[i32] })
56448 /* 167042 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
56449 /* 167047 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
56450 /* 167052 */ // GIR_Coverage, 1910,
56451 /* 167052 */ GIR_Done,
56452 /* 167053 */ // Label 2521: @167053
56453 /* 167053 */ GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(167072), // Rule ID 564 //
56454 /* 167058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56455 /* 167061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
56456 /* 167065 */ // (fpextend:{ *:[f64] } f32:{ *:[f32] }:$RB) => (EFDCFS:{ *:[f64] } f32:{ *:[f32] }:$RB)
56457 /* 167065 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCFS),
56458 /* 167070 */ GIR_RootConstrainSelectedInstOperands,
56459 /* 167071 */ // GIR_Coverage, 564,
56460 /* 167071 */ GIR_Done,
56461 /* 167072 */ // Label 2522: @167072
56462 /* 167072 */ GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(167095), // Rule ID 1269 //
56463 /* 167077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
56464 /* 167080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
56465 /* 167084 */ // (fpextend:{ *:[f64] } f32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$src, F8RC:{ *:[i32] })
56466 /* 167084 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
56467 /* 167089 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::F8RCRegClassID),
56468 /* 167094 */ // GIR_Coverage, 1269,
56469 /* 167094 */ GIR_Done,
56470 /* 167095 */ // Label 2523: @167095
56471 /* 167095 */ GIM_Reject,
56472 /* 167096 */ // Label 2520: @167096
56473 /* 167096 */ GIM_Reject,
56474 /* 167097 */ // Label 2518: @167097
56475 /* 167097 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(167119), // Rule ID 1015 //
56476 /* 167102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56477 /* 167105 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
56478 /* 167108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56479 /* 167112 */ // (fpextend:{ *:[f128] } f64:{ *:[f64] }:$RB) => (XSCVDPQP:{ *:[f128] } f64:{ *:[f64] }:$RB)
56480 /* 167112 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSCVDPQP),
56481 /* 167117 */ GIR_RootConstrainSelectedInstOperands,
56482 /* 167118 */ // GIR_Coverage, 1015,
56483 /* 167118 */ GIR_Done,
56484 /* 167119 */ // Label 2524: @167119
56485 /* 167119 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(167165), // Rule ID 2264 //
56486 /* 167124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56487 /* 167127 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56488 /* 167130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56489 /* 167134 */ // (fpextend:{ *:[f128] } f32:{ *:[f32] }:$src) => (XSCVDPQP:{ *:[f128] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$src, VFRC:{ *:[i32] }))
56490 /* 167134 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
56491 /* 167137 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
56492 /* 167141 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56493 /* 167146 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
56494 /* 167150 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VFRCRegClassID),
56495 /* 167155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPQP),
56496 /* 167158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56497 /* 167160 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56498 /* 167163 */ GIR_RootConstrainSelectedInstOperands,
56499 /* 167164 */ // GIR_Coverage, 2264,
56500 /* 167164 */ GIR_EraseRootFromParent_Done,
56501 /* 167165 */ // Label 2525: @167165
56502 /* 167165 */ GIM_Reject,
56503 /* 167166 */ // Label 2519: @167166
56504 /* 167166 */ GIM_Reject,
56505 /* 167167 */ // Label 47: @167167
56506 /* 167167 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2528*/ GIMT_Encode4(167323),
56507 /* 167178 */ /*GILLT_s32*//*Label 2526*/ GIMT_Encode4(167186),
56508 /* 167182 */ /*GILLT_s64*//*Label 2527*/ GIMT_Encode4(167300),
56509 /* 167186 */ // Label 2526: @167186
56510 /* 167186 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(167208), // Rule ID 962 //
56511 /* 167191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
56512 /* 167194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
56513 /* 167197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
56514 /* 167201 */ // (fpround:{ *:[f32] } f64:{ *:[f64] }:$XB) => (XSRSP:{ *:[f32] } f64:{ *:[f64] }:$XB)
56515 /* 167201 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRSP),
56516 /* 167206 */ GIR_RootConstrainSelectedInstOperands,
56517 /* 167207 */ // GIR_Coverage, 962,
56518 /* 167207 */ GIR_Done,
56519 /* 167208 */ // Label 2529: @167208
56520 /* 167208 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(167251), // Rule ID 2262 //
56521 /* 167213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56522 /* 167216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
56523 /* 167219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
56524 /* 167223 */ // (fpround:{ *:[f32] } f128:{ *:[f128] }:$src) => (XSRSP:{ *:[f32] } (XSCVQPDPO:{ *:[f64] } ?:{ *:[f128] }:$src))
56525 /* 167223 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
56526 /* 167226 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVQPDPO),
56527 /* 167230 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56528 /* 167235 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
56529 /* 167239 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
56530 /* 167241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRSP),
56531 /* 167244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
56532 /* 167246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56533 /* 167249 */ GIR_RootConstrainSelectedInstOperands,
56534 /* 167250 */ // GIR_Coverage, 2262,
56535 /* 167250 */ GIR_EraseRootFromParent_Done,
56536 /* 167251 */ // Label 2530: @167251
56537 /* 167251 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(167277), // Rule ID 158 //
56538 /* 167256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
56539 /* 167259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
56540 /* 167262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
56541 /* 167266 */ // (fpround:{ *:[f32] } f64:{ *:[f64] }:$RB) => (FRSP:{ *:[f32] } f64:{ *:[f64] }:$RB)
56542 /* 167266 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRSP),
56543 /* 167271 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56544 /* 167275 */ GIR_RootConstrainSelectedInstOperands,
56545 /* 167276 */ // GIR_Coverage, 158,
56546 /* 167276 */ GIR_Done,
56547 /* 167277 */ // Label 2531: @167277
56548 /* 167277 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(167299), // Rule ID 585 //
56549 /* 167282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56550 /* 167285 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
56551 /* 167288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56552 /* 167292 */ // (fpround:{ *:[f32] } f64:{ *:[f64] }:$RB) => (EFSCFD:{ *:[f32] } f64:{ *:[f64] }:$RB)
56553 /* 167292 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCFD),
56554 /* 167297 */ GIR_RootConstrainSelectedInstOperands,
56555 /* 167298 */ // GIR_Coverage, 585,
56556 /* 167298 */ GIR_Done,
56557 /* 167299 */ // Label 2532: @167299
56558 /* 167299 */ GIM_Reject,
56559 /* 167300 */ // Label 2527: @167300
56560 /* 167300 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(167322), // Rule ID 2260 //
56561 /* 167305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56562 /* 167308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
56563 /* 167311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VFRCRegClassID),
56564 /* 167315 */ // (fpround:{ *:[f64] } f128:{ *:[f128] }:$src) => (XSCVQPDP:{ *:[f64] } ?:{ *:[f128] }:$src)
56565 /* 167315 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSCVQPDP),
56566 /* 167320 */ GIR_RootConstrainSelectedInstOperands,
56567 /* 167321 */ // GIR_Coverage, 2260,
56568 /* 167321 */ GIR_Done,
56569 /* 167322 */ // Label 2533: @167322
56570 /* 167322 */ GIM_Reject,
56571 /* 167323 */ // Label 2528: @167323
56572 /* 167323 */ GIM_Reject,
56573 /* 167324 */ // Label 48: @167324
56574 /* 167324 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2538*/ GIMT_Encode4(167586),
56575 /* 167335 */ /*GILLT_s32*//*Label 2534*/ GIMT_Encode4(167355),
56576 /* 167339 */ /*GILLT_s64*//*Label 2535*/ GIMT_Encode4(167463), GIMT_Encode4(0),
56577 /* 167347 */ /*GILLT_v2s64*//*Label 2536*/ GIMT_Encode4(167507),
56578 /* 167351 */ /*GILLT_v4s32*//*Label 2537*/ GIMT_Encode4(167534),
56579 /* 167355 */ // Label 2534: @167355
56580 /* 167355 */ GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(167418), // Rule ID 2250 //
56581 /* 167360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56582 /* 167363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
56583 /* 167366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56584 /* 167370 */ // (fp_to_sint:{ *:[i32] } f128:{ *:[f128] }:$src) => (MFVSRWZ:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[f64] } (XSCVQPSWZ:{ *:[f128] } ?:{ *:[f128] }:$src), VFRC:{ *:[i32] }))
56585 /* 167370 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
56586 /* 167373 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVQPSWZ),
56587 /* 167377 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56588 /* 167382 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
56589 /* 167386 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
56590 /* 167388 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
56591 /* 167391 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
56592 /* 167395 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56593 /* 167400 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
56594 /* 167403 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VFRCRegClassID),
56595 /* 167408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ),
56596 /* 167411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
56597 /* 167413 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56598 /* 167416 */ GIR_RootConstrainSelectedInstOperands,
56599 /* 167417 */ // GIR_Coverage, 2250,
56600 /* 167417 */ GIR_EraseRootFromParent_Done,
56601 /* 167418 */ // Label 2539: @167418
56602 /* 167418 */ GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(167440), // Rule ID 570 //
56603 /* 167423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56604 /* 167426 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
56605 /* 167429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56606 /* 167433 */ // (fp_to_sint:{ *:[i32] } f64:{ *:[f64] }:$RB) => (EFDCTSIZ:{ *:[i32] } f64:{ *:[f64] }:$RB)
56607 /* 167433 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCTSIZ),
56608 /* 167438 */ GIR_RootConstrainSelectedInstOperands,
56609 /* 167439 */ // GIR_Coverage, 570,
56610 /* 167439 */ GIR_Done,
56611 /* 167440 */ // Label 2540: @167440
56612 /* 167440 */ GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(167462), // Rule ID 591 //
56613 /* 167445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56614 /* 167448 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56615 /* 167451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56616 /* 167455 */ // (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$RB) => (EFSCTSIZ:{ *:[i32] } f32:{ *:[f32] }:$RB)
56617 /* 167455 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCTSIZ),
56618 /* 167460 */ GIR_RootConstrainSelectedInstOperands,
56619 /* 167461 */ // GIR_Coverage, 591,
56620 /* 167461 */ GIR_Done,
56621 /* 167462 */ // Label 2541: @167462
56622 /* 167462 */ GIM_Reject,
56623 /* 167463 */ // Label 2535: @167463
56624 /* 167463 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(167506), // Rule ID 2246 //
56625 /* 167468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56626 /* 167471 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
56627 /* 167474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
56628 /* 167478 */ // (fp_to_sint:{ *:[i64] } f128:{ *:[f128] }:$src) => (MFVRD:{ *:[i64] } (XSCVQPSDZ:{ *:[v4i32] } ?:{ *:[f128] }:$src))
56629 /* 167478 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
56630 /* 167481 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVQPSDZ),
56631 /* 167485 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56632 /* 167490 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
56633 /* 167494 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
56634 /* 167496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVRD),
56635 /* 167499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
56636 /* 167501 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56637 /* 167504 */ GIR_RootConstrainSelectedInstOperands,
56638 /* 167505 */ // GIR_Coverage, 2246,
56639 /* 167505 */ GIR_EraseRootFromParent_Done,
56640 /* 167506 */ // Label 2542: @167506
56641 /* 167506 */ GIM_Reject,
56642 /* 167507 */ // Label 2536: @167507
56643 /* 167507 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(167533), // Rule ID 878 //
56644 /* 167512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56645 /* 167515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
56646 /* 167518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56647 /* 167522 */ // (fp_to_sint:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSXDS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB)
56648 /* 167522 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVDPSXDS),
56649 /* 167527 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56650 /* 167531 */ GIR_RootConstrainSelectedInstOperands,
56651 /* 167532 */ // GIR_Coverage, 878,
56652 /* 167532 */ GIR_Done,
56653 /* 167533 */ // Label 2543: @167533
56654 /* 167533 */ GIM_Reject,
56655 /* 167534 */ // Label 2537: @167534
56656 /* 167534 */ GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(167585),
56657 /* 167539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
56658 /* 167542 */ GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(167565), // Rule ID 886 //
56659 /* 167547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56660 /* 167550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56661 /* 167554 */ // (fp_to_sint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) => (XVCVSPSXWS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB)
56662 /* 167554 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVSPSXWS),
56663 /* 167559 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56664 /* 167563 */ GIR_RootConstrainSelectedInstOperands,
56665 /* 167564 */ // GIR_Coverage, 886,
56666 /* 167564 */ GIR_Done,
56667 /* 167565 */ // Label 2545: @167565
56668 /* 167565 */ GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(167584), // Rule ID 1415 //
56669 /* 167570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
56670 /* 167573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56671 /* 167577 */ // (fp_to_sint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$vA) => (VCTSXS_0:{ *:[v4i32] } ?:{ *:[v4f32] }:$vA)
56672 /* 167577 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTSXS_0),
56673 /* 167582 */ GIR_RootConstrainSelectedInstOperands,
56674 /* 167583 */ // GIR_Coverage, 1415,
56675 /* 167583 */ GIR_Done,
56676 /* 167584 */ // Label 2546: @167584
56677 /* 167584 */ GIM_Reject,
56678 /* 167585 */ // Label 2544: @167585
56679 /* 167585 */ GIM_Reject,
56680 /* 167586 */ // Label 2538: @167586
56681 /* 167586 */ GIM_Reject,
56682 /* 167587 */ // Label 49: @167587
56683 /* 167587 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2551*/ GIMT_Encode4(167849),
56684 /* 167598 */ /*GILLT_s32*//*Label 2547*/ GIMT_Encode4(167618),
56685 /* 167602 */ /*GILLT_s64*//*Label 2548*/ GIMT_Encode4(167726), GIMT_Encode4(0),
56686 /* 167610 */ /*GILLT_v2s64*//*Label 2549*/ GIMT_Encode4(167770),
56687 /* 167614 */ /*GILLT_v4s32*//*Label 2550*/ GIMT_Encode4(167797),
56688 /* 167618 */ // Label 2547: @167618
56689 /* 167618 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(167681), // Rule ID 2252 //
56690 /* 167623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56691 /* 167626 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
56692 /* 167629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56693 /* 167633 */ // (fp_to_uint:{ *:[i32] } f128:{ *:[f128] }:$src) => (MFVSRWZ:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[f64] } (XSCVQPUWZ:{ *:[f128] } ?:{ *:[f128] }:$src), VFRC:{ *:[i32] }))
56694 /* 167633 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
56695 /* 167636 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVQPUWZ),
56696 /* 167640 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56697 /* 167645 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
56698 /* 167649 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
56699 /* 167651 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
56700 /* 167654 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
56701 /* 167658 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56702 /* 167663 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
56703 /* 167666 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VFRCRegClassID),
56704 /* 167671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ),
56705 /* 167674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
56706 /* 167676 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56707 /* 167679 */ GIR_RootConstrainSelectedInstOperands,
56708 /* 167680 */ // GIR_Coverage, 2252,
56709 /* 167680 */ GIR_EraseRootFromParent_Done,
56710 /* 167681 */ // Label 2552: @167681
56711 /* 167681 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(167703), // Rule ID 572 //
56712 /* 167686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56713 /* 167689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
56714 /* 167692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56715 /* 167696 */ // (fp_to_uint:{ *:[i32] } f64:{ *:[f64] }:$RB) => (EFDCTUIZ:{ *:[i32] } f64:{ *:[f64] }:$RB)
56716 /* 167696 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCTUIZ),
56717 /* 167701 */ GIR_RootConstrainSelectedInstOperands,
56718 /* 167702 */ // GIR_Coverage, 572,
56719 /* 167702 */ GIR_Done,
56720 /* 167703 */ // Label 2553: @167703
56721 /* 167703 */ GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(167725), // Rule ID 593 //
56722 /* 167708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56723 /* 167711 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56724 /* 167714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56725 /* 167718 */ // (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$RB) => (EFSCTUIZ:{ *:[i32] } f32:{ *:[f32] }:$RB)
56726 /* 167718 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCTUIZ),
56727 /* 167723 */ GIR_RootConstrainSelectedInstOperands,
56728 /* 167724 */ // GIR_Coverage, 593,
56729 /* 167724 */ GIR_Done,
56730 /* 167725 */ // Label 2554: @167725
56731 /* 167725 */ GIM_Reject,
56732 /* 167726 */ // Label 2548: @167726
56733 /* 167726 */ GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(167769), // Rule ID 2248 //
56734 /* 167731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56735 /* 167734 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
56736 /* 167737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
56737 /* 167741 */ // (fp_to_uint:{ *:[i64] } f128:{ *:[f128] }:$src) => (MFVRD:{ *:[i64] } (XSCVQPUDZ:{ *:[v4i32] } ?:{ *:[f128] }:$src))
56738 /* 167741 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
56739 /* 167744 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVQPUDZ),
56740 /* 167748 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56741 /* 167753 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
56742 /* 167757 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
56743 /* 167759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVRD),
56744 /* 167762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
56745 /* 167764 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56746 /* 167767 */ GIR_RootConstrainSelectedInstOperands,
56747 /* 167768 */ // GIR_Coverage, 2248,
56748 /* 167768 */ GIR_EraseRootFromParent_Done,
56749 /* 167769 */ // Label 2555: @167769
56750 /* 167769 */ GIM_Reject,
56751 /* 167770 */ // Label 2549: @167770
56752 /* 167770 */ GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(167796), // Rule ID 881 //
56753 /* 167775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56754 /* 167778 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
56755 /* 167781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56756 /* 167785 */ // (fp_to_uint:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) => (XVCVDPUXDS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB)
56757 /* 167785 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVDPUXDS),
56758 /* 167790 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56759 /* 167794 */ GIR_RootConstrainSelectedInstOperands,
56760 /* 167795 */ // GIR_Coverage, 881,
56761 /* 167795 */ GIR_Done,
56762 /* 167796 */ // Label 2556: @167796
56763 /* 167796 */ GIM_Reject,
56764 /* 167797 */ // Label 2550: @167797
56765 /* 167797 */ GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(167848),
56766 /* 167802 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
56767 /* 167805 */ GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(167828), // Rule ID 889 //
56768 /* 167810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56769 /* 167813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56770 /* 167817 */ // (fp_to_uint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) => (XVCVSPUXWS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB)
56771 /* 167817 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVSPUXWS),
56772 /* 167822 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56773 /* 167826 */ GIR_RootConstrainSelectedInstOperands,
56774 /* 167827 */ // GIR_Coverage, 889,
56775 /* 167827 */ GIR_Done,
56776 /* 167828 */ // Label 2558: @167828
56777 /* 167828 */ GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(167847), // Rule ID 1416 //
56778 /* 167833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
56779 /* 167836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56780 /* 167840 */ // (fp_to_uint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$vA) => (VCTUXS_0:{ *:[v4i32] } ?:{ *:[v4f32] }:$vA)
56781 /* 167840 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTUXS_0),
56782 /* 167845 */ GIR_RootConstrainSelectedInstOperands,
56783 /* 167846 */ // GIR_Coverage, 1416,
56784 /* 167846 */ GIR_Done,
56785 /* 167847 */ // Label 2559: @167847
56786 /* 167847 */ GIM_Reject,
56787 /* 167848 */ // Label 2557: @167848
56788 /* 167848 */ GIM_Reject,
56789 /* 167849 */ // Label 2551: @167849
56790 /* 167849 */ GIM_Reject,
56791 /* 167850 */ // Label 50: @167850
56792 /* 167850 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2565*/ GIMT_Encode4(168096),
56793 /* 167861 */ /*GILLT_s32*//*Label 2560*/ GIMT_Encode4(167881),
56794 /* 167865 */ /*GILLT_s64*//*Label 2561*/ GIMT_Encode4(167904),
56795 /* 167869 */ /*GILLT_s128*//*Label 2562*/ GIMT_Encode4(167927),
56796 /* 167873 */ /*GILLT_v2s64*//*Label 2563*/ GIMT_Encode4(168017),
56797 /* 167877 */ /*GILLT_v4s32*//*Label 2564*/ GIMT_Encode4(168044),
56798 /* 167881 */ // Label 2560: @167881
56799 /* 167881 */ GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(167903), // Rule ID 587 //
56800 /* 167886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56801 /* 167889 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56802 /* 167892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56803 /* 167896 */ // (sint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$RB) => (EFSCFSI:{ *:[f32] } i32:{ *:[i32] }:$RB)
56804 /* 167896 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCFSI),
56805 /* 167901 */ GIR_RootConstrainSelectedInstOperands,
56806 /* 167902 */ // GIR_Coverage, 587,
56807 /* 167902 */ GIR_Done,
56808 /* 167903 */ // Label 2566: @167903
56809 /* 167903 */ GIM_Reject,
56810 /* 167904 */ // Label 2561: @167904
56811 /* 167904 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(167926), // Rule ID 566 //
56812 /* 167909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56813 /* 167912 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56814 /* 167915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
56815 /* 167919 */ // (sint_to_fp:{ *:[f64] } i32:{ *:[i32] }:$RB) => (EFDCFSI:{ *:[f64] } i32:{ *:[i32] }:$RB)
56816 /* 167919 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCFSI),
56817 /* 167924 */ GIR_RootConstrainSelectedInstOperands,
56818 /* 167925 */ // GIR_Coverage, 566,
56819 /* 167925 */ GIR_Done,
56820 /* 167926 */ // Label 2567: @167926
56821 /* 167926 */ GIM_Reject,
56822 /* 167927 */ // Label 2562: @167927
56823 /* 167927 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(167973), // Rule ID 2141 //
56824 /* 167932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56825 /* 167935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
56826 /* 167938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56827 /* 167942 */ // (sint_to_fp:{ *:[f128] } i64:{ *:[i64] }:$src) => (XSCVSDQP:{ *:[f128] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[i64] }:$src, VFRC:{ *:[i32] }))
56828 /* 167942 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
56829 /* 167945 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
56830 /* 167949 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56831 /* 167954 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
56832 /* 167958 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VFRCRegClassID),
56833 /* 167963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVSDQP),
56834 /* 167966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56835 /* 167968 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56836 /* 167971 */ GIR_RootConstrainSelectedInstOperands,
56837 /* 167972 */ // GIR_Coverage, 2141,
56838 /* 167972 */ GIR_EraseRootFromParent_Done,
56839 /* 167973 */ // Label 2568: @167973
56840 /* 167973 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(168016), // Rule ID 2151 //
56841 /* 167978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56842 /* 167981 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56843 /* 167984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56844 /* 167988 */ // (sint_to_fp:{ *:[f128] } i32:{ *:[i32] }:$src) => (XSCVSDQP:{ *:[f128] } (MTVSRWA:{ *:[f64] } ?:{ *:[i32] }:$src))
56845 /* 167988 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
56846 /* 167991 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::MTVSRWA),
56847 /* 167995 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56848 /* 168000 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
56849 /* 168004 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
56850 /* 168006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVSDQP),
56851 /* 168009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56852 /* 168011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56853 /* 168014 */ GIR_RootConstrainSelectedInstOperands,
56854 /* 168015 */ // GIR_Coverage, 2151,
56855 /* 168015 */ GIR_EraseRootFromParent_Done,
56856 /* 168016 */ // Label 2569: @168016
56857 /* 168016 */ GIM_Reject,
56858 /* 168017 */ // Label 2563: @168017
56859 /* 168017 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(168043), // Rule ID 891 //
56860 /* 168022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56861 /* 168025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
56862 /* 168028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56863 /* 168032 */ // (sint_to_fp:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) => (XVCVSXDDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB)
56864 /* 168032 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVSXDDP),
56865 /* 168037 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56866 /* 168041 */ GIR_RootConstrainSelectedInstOperands,
56867 /* 168042 */ // GIR_Coverage, 891,
56868 /* 168042 */ GIR_Done,
56869 /* 168043 */ // Label 2570: @168043
56870 /* 168043 */ GIM_Reject,
56871 /* 168044 */ // Label 2564: @168044
56872 /* 168044 */ GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(168095),
56873 /* 168049 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
56874 /* 168052 */ GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(168075), // Rule ID 894 //
56875 /* 168057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56876 /* 168060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56877 /* 168064 */ // (sint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) => (XVCVSXWSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB)
56878 /* 168064 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVSXWSP),
56879 /* 168069 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56880 /* 168073 */ GIR_RootConstrainSelectedInstOperands,
56881 /* 168074 */ // GIR_Coverage, 894,
56882 /* 168074 */ GIR_Done,
56883 /* 168075 */ // Label 2572: @168075
56884 /* 168075 */ GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(168094), // Rule ID 1417 //
56885 /* 168080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
56886 /* 168083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56887 /* 168087 */ // (sint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vA) => (VCFSX_0:{ *:[v4f32] } ?:{ *:[v4i32] }:$vA)
56888 /* 168087 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCFSX_0),
56889 /* 168092 */ GIR_RootConstrainSelectedInstOperands,
56890 /* 168093 */ // GIR_Coverage, 1417,
56891 /* 168093 */ GIR_Done,
56892 /* 168094 */ // Label 2573: @168094
56893 /* 168094 */ GIM_Reject,
56894 /* 168095 */ // Label 2571: @168095
56895 /* 168095 */ GIM_Reject,
56896 /* 168096 */ // Label 2565: @168096
56897 /* 168096 */ GIM_Reject,
56898 /* 168097 */ // Label 51: @168097
56899 /* 168097 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2579*/ GIMT_Encode4(168343),
56900 /* 168108 */ /*GILLT_s32*//*Label 2574*/ GIMT_Encode4(168128),
56901 /* 168112 */ /*GILLT_s64*//*Label 2575*/ GIMT_Encode4(168151),
56902 /* 168116 */ /*GILLT_s128*//*Label 2576*/ GIMT_Encode4(168174),
56903 /* 168120 */ /*GILLT_v2s64*//*Label 2577*/ GIMT_Encode4(168264),
56904 /* 168124 */ /*GILLT_v4s32*//*Label 2578*/ GIMT_Encode4(168291),
56905 /* 168128 */ // Label 2574: @168128
56906 /* 168128 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(168150), // Rule ID 589 //
56907 /* 168133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56908 /* 168136 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56909 /* 168139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
56910 /* 168143 */ // (uint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$RB) => (EFSCFUI:{ *:[f32] } i32:{ *:[i32] }:$RB)
56911 /* 168143 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCFUI),
56912 /* 168148 */ GIR_RootConstrainSelectedInstOperands,
56913 /* 168149 */ // GIR_Coverage, 589,
56914 /* 168149 */ GIR_Done,
56915 /* 168150 */ // Label 2580: @168150
56916 /* 168150 */ GIM_Reject,
56917 /* 168151 */ // Label 2575: @168151
56918 /* 168151 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(168173), // Rule ID 568 //
56919 /* 168156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
56920 /* 168159 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56921 /* 168162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
56922 /* 168166 */ // (uint_to_fp:{ *:[f64] } i32:{ *:[i32] }:$RB) => (EFDCFUI:{ *:[f64] } i32:{ *:[i32] }:$RB)
56923 /* 168166 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCFUI),
56924 /* 168171 */ GIR_RootConstrainSelectedInstOperands,
56925 /* 168172 */ // GIR_Coverage, 568,
56926 /* 168172 */ GIR_Done,
56927 /* 168173 */ // Label 2581: @168173
56928 /* 168173 */ GIM_Reject,
56929 /* 168174 */ // Label 2576: @168174
56930 /* 168174 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(168220), // Rule ID 2147 //
56931 /* 168179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56932 /* 168182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
56933 /* 168185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56934 /* 168189 */ // (uint_to_fp:{ *:[f128] } i64:{ *:[i64] }:$src) => (XSCVUDQP:{ *:[f128] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[i64] }:$src, VFRC:{ *:[i32] }))
56935 /* 168189 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
56936 /* 168192 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
56937 /* 168196 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56938 /* 168201 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
56939 /* 168205 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VFRCRegClassID),
56940 /* 168210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVUDQP),
56941 /* 168213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56942 /* 168215 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56943 /* 168218 */ GIR_RootConstrainSelectedInstOperands,
56944 /* 168219 */ // GIR_Coverage, 2147,
56945 /* 168219 */ GIR_EraseRootFromParent_Done,
56946 /* 168220 */ // Label 2582: @168220
56947 /* 168220 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(168263), // Rule ID 2155 //
56948 /* 168225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
56949 /* 168228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
56950 /* 168231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56951 /* 168235 */ // (uint_to_fp:{ *:[f128] } i32:{ *:[i32] }:$src) => (XSCVUDQP:{ *:[f128] } (MTVSRWZ:{ *:[f64] } ?:{ *:[i32] }:$src))
56952 /* 168235 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
56953 /* 168238 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::MTVSRWZ),
56954 /* 168242 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
56955 /* 168247 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
56956 /* 168251 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
56957 /* 168253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVUDQP),
56958 /* 168256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
56959 /* 168258 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
56960 /* 168261 */ GIR_RootConstrainSelectedInstOperands,
56961 /* 168262 */ // GIR_Coverage, 2155,
56962 /* 168262 */ GIR_EraseRootFromParent_Done,
56963 /* 168263 */ // Label 2583: @168263
56964 /* 168263 */ GIM_Reject,
56965 /* 168264 */ // Label 2577: @168264
56966 /* 168264 */ GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(168290), // Rule ID 896 //
56967 /* 168269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56968 /* 168272 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
56969 /* 168275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56970 /* 168279 */ // (uint_to_fp:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) => (XVCVUXDDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB)
56971 /* 168279 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVUXDDP),
56972 /* 168284 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56973 /* 168288 */ GIR_RootConstrainSelectedInstOperands,
56974 /* 168289 */ // GIR_Coverage, 896,
56975 /* 168289 */ GIR_Done,
56976 /* 168290 */ // Label 2584: @168290
56977 /* 168290 */ GIM_Reject,
56978 /* 168291 */ // Label 2578: @168291
56979 /* 168291 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(168342),
56980 /* 168296 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
56981 /* 168299 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(168322), // Rule ID 899 //
56982 /* 168304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
56983 /* 168307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
56984 /* 168311 */ // (uint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) => (XVCVUXWSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB)
56985 /* 168311 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVUXWSP),
56986 /* 168316 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
56987 /* 168320 */ GIR_RootConstrainSelectedInstOperands,
56988 /* 168321 */ // GIR_Coverage, 899,
56989 /* 168321 */ GIR_Done,
56990 /* 168322 */ // Label 2586: @168322
56991 /* 168322 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(168341), // Rule ID 1418 //
56992 /* 168327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
56993 /* 168330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
56994 /* 168334 */ // (uint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vA) => (VCFUX_0:{ *:[v4f32] } ?:{ *:[v4i32] }:$vA)
56995 /* 168334 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCFUX_0),
56996 /* 168339 */ GIR_RootConstrainSelectedInstOperands,
56997 /* 168340 */ // GIR_Coverage, 1418,
56998 /* 168340 */ GIR_Done,
56999 /* 168341 */ // Label 2587: @168341
57000 /* 168341 */ GIM_Reject,
57001 /* 168342 */ // Label 2585: @168342
57002 /* 168342 */ GIM_Reject,
57003 /* 168343 */ // Label 2579: @168343
57004 /* 168343 */ GIM_Reject,
57005 /* 168344 */ // Label 52: @168344
57006 /* 168344 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2593*/ GIMT_Encode4(168635),
57007 /* 168355 */ /*GILLT_s32*//*Label 2588*/ GIMT_Encode4(168375),
57008 /* 168359 */ /*GILLT_s64*//*Label 2589*/ GIMT_Encode4(168487),
57009 /* 168363 */ /*GILLT_s128*//*Label 2590*/ GIMT_Encode4(168558),
57010 /* 168367 */ /*GILLT_v2s64*//*Label 2591*/ GIMT_Encode4(168581),
57011 /* 168371 */ /*GILLT_v4s32*//*Label 2592*/ GIMT_Encode4(168608),
57012 /* 168375 */ // Label 2588: @168375
57013 /* 168375 */ GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(168486),
57014 /* 168380 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
57015 /* 168383 */ GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(168447), // Rule ID 1684 //
57016 /* 168388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57017 /* 168391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
57018 /* 168395 */ // (fabs:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSABSDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57019 /* 168395 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57020 /* 168398 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57021 /* 168402 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57022 /* 168407 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
57023 /* 168411 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57024 /* 168416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57025 /* 168419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSABSDP),
57026 /* 168423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57027 /* 168428 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57028 /* 168431 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57029 /* 168433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57030 /* 168436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57031 /* 168438 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57032 /* 168441 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57033 /* 168446 */ // GIR_Coverage, 1684,
57034 /* 168446 */ GIR_EraseRootFromParent_Done,
57035 /* 168447 */ // Label 2595: @168447
57036 /* 168447 */ GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(168466), // Rule ID 163 //
57037 /* 168452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
57038 /* 168455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
57039 /* 168459 */ // (fabs:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FABSS:{ *:[f32] } f32:{ *:[f32] }:$RB)
57040 /* 168459 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FABSS),
57041 /* 168464 */ GIR_RootConstrainSelectedInstOperands,
57042 /* 168465 */ // GIR_Coverage, 163,
57043 /* 168465 */ GIR_Done,
57044 /* 168466 */ // Label 2596: @168466
57045 /* 168466 */ GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(168485), // Rule ID 581 //
57046 /* 168471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
57047 /* 168474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
57048 /* 168478 */ // (fabs:{ *:[f32] } f32:{ *:[f32] }:$RA) => (EFSABS:{ *:[f32] } f32:{ *:[f32] }:$RA)
57049 /* 168478 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSABS),
57050 /* 168483 */ GIR_RootConstrainSelectedInstOperands,
57051 /* 168484 */ // GIR_Coverage, 581,
57052 /* 168484 */ GIR_Done,
57053 /* 168485 */ // Label 2597: @168485
57054 /* 168485 */ GIM_Reject,
57055 /* 168486 */ // Label 2594: @168486
57056 /* 168486 */ GIM_Reject,
57057 /* 168487 */ // Label 2589: @168487
57058 /* 168487 */ GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(168557),
57059 /* 168492 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
57060 /* 168495 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(168518), // Rule ID 843 //
57061 /* 168500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57062 /* 168503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
57063 /* 168507 */ // (fabs:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSABSDP:{ *:[f64] } f64:{ *:[f64] }:$XB)
57064 /* 168507 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSABSDP),
57065 /* 168512 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57066 /* 168516 */ GIR_RootConstrainSelectedInstOperands,
57067 /* 168517 */ // GIR_Coverage, 843,
57068 /* 168517 */ GIR_Done,
57069 /* 168518 */ // Label 2599: @168518
57070 /* 168518 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(168537), // Rule ID 164 //
57071 /* 168523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
57072 /* 168526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
57073 /* 168530 */ // (fabs:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FABSD:{ *:[f64] } f64:{ *:[f64] }:$RB)
57074 /* 168530 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FABSD),
57075 /* 168535 */ GIR_RootConstrainSelectedInstOperands,
57076 /* 168536 */ // GIR_Coverage, 164,
57077 /* 168536 */ GIR_Done,
57078 /* 168537 */ // Label 2600: @168537
57079 /* 168537 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(168556), // Rule ID 560 //
57080 /* 168542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
57081 /* 168545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
57082 /* 168549 */ // (fabs:{ *:[f64] } f64:{ *:[f64] }:$RA) => (EFDABS:{ *:[f64] } f64:{ *:[f64] }:$RA)
57083 /* 168549 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDABS),
57084 /* 168554 */ GIR_RootConstrainSelectedInstOperands,
57085 /* 168555 */ // GIR_Coverage, 560,
57086 /* 168555 */ GIR_Done,
57087 /* 168556 */ // Label 2601: @168556
57088 /* 168556 */ GIM_Reject,
57089 /* 168557 */ // Label 2598: @168557
57090 /* 168557 */ GIM_Reject,
57091 /* 168558 */ // Label 2590: @168558
57092 /* 168558 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(168580), // Rule ID 984 //
57093 /* 168563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
57094 /* 168566 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
57095 /* 168569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57096 /* 168573 */ // (fabs:{ *:[f128] } f128:{ *:[f128] }:$RB) => (XSABSQP:{ *:[f128] } f128:{ *:[f128] }:$RB)
57097 /* 168573 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSABSQP),
57098 /* 168578 */ GIR_RootConstrainSelectedInstOperands,
57099 /* 168579 */ // GIR_Coverage, 984,
57100 /* 168579 */ GIR_Done,
57101 /* 168580 */ // Label 2602: @168580
57102 /* 168580 */ GIM_Reject,
57103 /* 168581 */ // Label 2591: @168581
57104 /* 168581 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(168607), // Rule ID 848 //
57105 /* 168586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57106 /* 168589 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
57107 /* 168592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
57108 /* 168596 */ // (fabs:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVABSDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
57109 /* 168596 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVABSDP),
57110 /* 168601 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57111 /* 168605 */ GIR_RootConstrainSelectedInstOperands,
57112 /* 168606 */ // GIR_Coverage, 848,
57113 /* 168606 */ GIR_Done,
57114 /* 168607 */ // Label 2603: @168607
57115 /* 168607 */ GIM_Reject,
57116 /* 168608 */ // Label 2592: @168608
57117 /* 168608 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(168634), // Rule ID 849 //
57118 /* 168613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57119 /* 168616 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
57120 /* 168619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
57121 /* 168623 */ // (fabs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVABSSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
57122 /* 168623 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVABSSP),
57123 /* 168628 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57124 /* 168632 */ GIR_RootConstrainSelectedInstOperands,
57125 /* 168633 */ // GIR_Coverage, 849,
57126 /* 168633 */ GIR_Done,
57127 /* 168634 */ // Label 2604: @168634
57128 /* 168634 */ GIM_Reject,
57129 /* 168635 */ // Label 2593: @168635
57130 /* 168635 */ GIM_Reject,
57131 /* 168636 */ // Label 53: @168636
57132 /* 168636 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2610*/ GIMT_Encode4(168951),
57133 /* 168647 */ /*GILLT_s32*//*Label 2605*/ GIMT_Encode4(168667),
57134 /* 168651 */ /*GILLT_s64*//*Label 2606*/ GIMT_Encode4(168751),
57135 /* 168655 */ /*GILLT_s128*//*Label 2607*/ GIMT_Encode4(168861),
57136 /* 168659 */ /*GILLT_v2s64*//*Label 2608*/ GIMT_Encode4(168891),
57137 /* 168663 */ /*GILLT_v4s32*//*Label 2609*/ GIMT_Encode4(168921),
57138 /* 168667 */ // Label 2605: @168667
57139 /* 168667 */ GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(168750),
57140 /* 168672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
57141 /* 168675 */ GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(168701), // Rule ID 169 //
57142 /* 168680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
57143 /* 168683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57144 /* 168686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
57145 /* 168690 */ // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$RB, f32:{ *:[f32] }:$RA) => (FCPSGNS:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
57146 /* 168690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCPSGNS),
57147 /* 168693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
57148 /* 168695 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
57149 /* 168697 */ GIR_RootToRootCopy, /*OpIdx*/1, // RB
57150 /* 168699 */ GIR_RootConstrainSelectedInstOperands,
57151 /* 168700 */ // GIR_Coverage, 169,
57152 /* 168700 */ GIR_EraseRootFromParent_Done,
57153 /* 168701 */ // Label 2612: @168701
57154 /* 168701 */ GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(168749), // Rule ID 1281 //
57155 /* 168706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
57156 /* 168709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57157 /* 168712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
57158 /* 168716 */ // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$frB, f64:{ *:[f64] }:$frA) => (FCPSGNS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } ?:{ *:[f64] }:$frA, F4RC:{ *:[i32] }), ?:{ *:[f32] }:$frB)
57159 /* 168716 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
57160 /* 168719 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57161 /* 168723 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57162 /* 168728 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // frA
57163 /* 168732 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::F4RCRegClassID),
57164 /* 168737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCPSGNS),
57165 /* 168740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
57166 /* 168742 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57167 /* 168745 */ GIR_RootToRootCopy, /*OpIdx*/1, // frB
57168 /* 168747 */ GIR_RootConstrainSelectedInstOperands,
57169 /* 168748 */ // GIR_Coverage, 1281,
57170 /* 168748 */ GIR_EraseRootFromParent_Done,
57171 /* 168749 */ // Label 2613: @168749
57172 /* 168749 */ GIM_Reject,
57173 /* 168750 */ // Label 2611: @168750
57174 /* 168750 */ GIM_Reject,
57175 /* 168751 */ // Label 2606: @168751
57176 /* 168751 */ GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(168860),
57177 /* 168756 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
57178 /* 168759 */ GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(168785), // Rule ID 847 //
57179 /* 168764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57180 /* 168767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57181 /* 168770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
57182 /* 168774 */ // (fcopysign:{ *:[f64] } f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XA) => (XSCPSGNDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
57183 /* 168774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCPSGNDP),
57184 /* 168777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57185 /* 168779 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
57186 /* 168781 */ GIR_RootToRootCopy, /*OpIdx*/1, // XB
57187 /* 168783 */ GIR_RootConstrainSelectedInstOperands,
57188 /* 168784 */ // GIR_Coverage, 847,
57189 /* 168784 */ GIR_EraseRootFromParent_Done,
57190 /* 168785 */ // Label 2615: @168785
57191 /* 168785 */ GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(168811), // Rule ID 170 //
57192 /* 168790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
57193 /* 168793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57194 /* 168796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
57195 /* 168800 */ // (fcopysign:{ *:[f64] } f64:{ *:[f64] }:$RB, f64:{ *:[f64] }:$RA) => (FCPSGND:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
57196 /* 168800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCPSGND),
57197 /* 168803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
57198 /* 168805 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
57199 /* 168807 */ GIR_RootToRootCopy, /*OpIdx*/1, // RB
57200 /* 168809 */ GIR_RootConstrainSelectedInstOperands,
57201 /* 168810 */ // GIR_Coverage, 170,
57202 /* 168810 */ GIR_EraseRootFromParent_Done,
57203 /* 168811 */ // Label 2616: @168811
57204 /* 168811 */ GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(168859), // Rule ID 1280 //
57205 /* 168816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
57206 /* 168819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57207 /* 168822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
57208 /* 168826 */ // (fcopysign:{ *:[f64] } f64:{ *:[f64] }:$frB, f32:{ *:[f32] }:$frA) => (FCPSGND:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$frA, F8RC:{ *:[i32] }), ?:{ *:[f64] }:$frB)
57209 /* 168826 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57210 /* 168829 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57211 /* 168833 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57212 /* 168838 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // frA
57213 /* 168842 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::F8RCRegClassID),
57214 /* 168847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCPSGND),
57215 /* 168850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
57216 /* 168852 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57217 /* 168855 */ GIR_RootToRootCopy, /*OpIdx*/1, // frB
57218 /* 168857 */ GIR_RootConstrainSelectedInstOperands,
57219 /* 168858 */ // GIR_Coverage, 1280,
57220 /* 168858 */ GIR_EraseRootFromParent_Done,
57221 /* 168859 */ // Label 2617: @168859
57222 /* 168859 */ GIM_Reject,
57223 /* 168860 */ // Label 2614: @168860
57224 /* 168860 */ GIM_Reject,
57225 /* 168861 */ // Label 2607: @168861
57226 /* 168861 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(168890), // Rule ID 983 //
57227 /* 168866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
57228 /* 168869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
57229 /* 168872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
57230 /* 168875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57231 /* 168879 */ // (fcopysign:{ *:[f128] } f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RA) => (XSCPSGNQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
57232 /* 168879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCPSGNQP),
57233 /* 168882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
57234 /* 168884 */ GIR_RootToRootCopy, /*OpIdx*/2, // RA
57235 /* 168886 */ GIR_RootToRootCopy, /*OpIdx*/1, // RB
57236 /* 168888 */ GIR_RootConstrainSelectedInstOperands,
57237 /* 168889 */ // GIR_Coverage, 983,
57238 /* 168889 */ GIR_EraseRootFromParent_Done,
57239 /* 168890 */ // Label 2618: @168890
57240 /* 168890 */ GIM_Reject,
57241 /* 168891 */ // Label 2608: @168891
57242 /* 168891 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(168920), // Rule ID 850 //
57243 /* 168896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57244 /* 168899 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
57245 /* 168902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
57246 /* 168905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
57247 /* 168909 */ // (fcopysign:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XA) => (XVCPSGNDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
57248 /* 168909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCPSGNDP),
57249 /* 168912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57250 /* 168914 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
57251 /* 168916 */ GIR_RootToRootCopy, /*OpIdx*/1, // XB
57252 /* 168918 */ GIR_RootConstrainSelectedInstOperands,
57253 /* 168919 */ // GIR_Coverage, 850,
57254 /* 168919 */ GIR_EraseRootFromParent_Done,
57255 /* 168920 */ // Label 2619: @168920
57256 /* 168920 */ GIM_Reject,
57257 /* 168921 */ // Label 2609: @168921
57258 /* 168921 */ GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(168950), // Rule ID 851 //
57259 /* 168926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57260 /* 168929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
57261 /* 168932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
57262 /* 168935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
57263 /* 168939 */ // (fcopysign:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XA) => (XVCPSGNSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
57264 /* 168939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCPSGNSP),
57265 /* 168942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57266 /* 168944 */ GIR_RootToRootCopy, /*OpIdx*/2, // XA
57267 /* 168946 */ GIR_RootToRootCopy, /*OpIdx*/1, // XB
57268 /* 168948 */ GIR_RootConstrainSelectedInstOperands,
57269 /* 168949 */ // GIR_Coverage, 851,
57270 /* 168949 */ GIR_EraseRootFromParent_Done,
57271 /* 168950 */ // Label 2620: @168950
57272 /* 168950 */ GIM_Reject,
57273 /* 168951 */ // Label 2610: @168951
57274 /* 168951 */ GIM_Reject,
57275 /* 168952 */ // Label 54: @168952
57276 /* 168952 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2623*/ GIMT_Encode4(169031),
57277 /* 168963 */ /*GILLT_v2s64*//*Label 2621*/ GIMT_Encode4(168971),
57278 /* 168967 */ /*GILLT_v4s32*//*Label 2622*/ GIMT_Encode4(169001),
57279 /* 168971 */ // Label 2621: @168971
57280 /* 168971 */ GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(169000), // Rule ID 1683 //
57281 /* 168976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57282 /* 168979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
57283 /* 168982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
57284 /* 168985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
57285 /* 168989 */ // (fminnum:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$src1, v2f64:{ *:[v2f64] }:$src2) => (XVMINDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$src1, ?:{ *:[v2f64] }:$src2)
57286 /* 168989 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMINDP),
57287 /* 168994 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57288 /* 168998 */ GIR_RootConstrainSelectedInstOperands,
57289 /* 168999 */ // GIR_Coverage, 1683,
57290 /* 168999 */ GIR_Done,
57291 /* 169000 */ // Label 2624: @169000
57292 /* 169000 */ GIM_Reject,
57293 /* 169001 */ // Label 2622: @169001
57294 /* 169001 */ GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(169030), // Rule ID 1679 //
57295 /* 169006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57296 /* 169009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
57297 /* 169012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
57298 /* 169015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
57299 /* 169019 */ // (fminnum:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src1, v4f32:{ *:[v4f32] }:$src2) => (XVMINSP:{ *:[v4f32] } ?:{ *:[v4f32] }:$src1, ?:{ *:[v4f32] }:$src2)
57300 /* 169019 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMINSP),
57301 /* 169024 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57302 /* 169028 */ GIR_RootConstrainSelectedInstOperands,
57303 /* 169029 */ // GIR_Coverage, 1679,
57304 /* 169029 */ GIR_Done,
57305 /* 169030 */ // Label 2625: @169030
57306 /* 169030 */ GIM_Reject,
57307 /* 169031 */ // Label 2623: @169031
57308 /* 169031 */ GIM_Reject,
57309 /* 169032 */ // Label 55: @169032
57310 /* 169032 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2628*/ GIMT_Encode4(169111),
57311 /* 169043 */ /*GILLT_v2s64*//*Label 2626*/ GIMT_Encode4(169051),
57312 /* 169047 */ /*GILLT_v4s32*//*Label 2627*/ GIMT_Encode4(169081),
57313 /* 169051 */ // Label 2626: @169051
57314 /* 169051 */ GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(169080), // Rule ID 1681 //
57315 /* 169056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57316 /* 169059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
57317 /* 169062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
57318 /* 169065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
57319 /* 169069 */ // (fmaxnum:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$src1, v2f64:{ *:[v2f64] }:$src2) => (XVMAXDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$src1, ?:{ *:[v2f64] }:$src2)
57320 /* 169069 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMAXDP),
57321 /* 169074 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57322 /* 169078 */ GIR_RootConstrainSelectedInstOperands,
57323 /* 169079 */ // GIR_Coverage, 1681,
57324 /* 169079 */ GIR_Done,
57325 /* 169080 */ // Label 2629: @169080
57326 /* 169080 */ GIM_Reject,
57327 /* 169081 */ // Label 2627: @169081
57328 /* 169081 */ GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(169110), // Rule ID 1677 //
57329 /* 169086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57330 /* 169089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
57331 /* 169092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
57332 /* 169095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
57333 /* 169099 */ // (fmaxnum:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src1, v4f32:{ *:[v4f32] }:$src2) => (XVMAXSP:{ *:[v4f32] } ?:{ *:[v4f32] }:$src1, ?:{ *:[v4f32] }:$src2)
57334 /* 169099 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMAXSP),
57335 /* 169104 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57336 /* 169108 */ GIR_RootConstrainSelectedInstOperands,
57337 /* 169109 */ // GIR_Coverage, 1677,
57338 /* 169109 */ GIR_Done,
57339 /* 169110 */ // Label 2630: @169110
57340 /* 169110 */ GIM_Reject,
57341 /* 169111 */ // Label 2628: @169111
57342 /* 169111 */ GIM_Reject,
57343 /* 169112 */ // Label 56: @169112
57344 /* 169112 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2633*/ GIMT_Encode4(169693),
57345 /* 169123 */ /*GILLT_s32*//*Label 2631*/ GIMT_Encode4(169131),
57346 /* 169127 */ /*GILLT_s64*//*Label 2632*/ GIMT_Encode4(169538),
57347 /* 169131 */ // Label 2631: @169131
57348 /* 169131 */ GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(169537),
57349 /* 169136 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
57350 /* 169139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57351 /* 169142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
57352 /* 169146 */ GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(169256), // Rule ID 1689 //
57353 /* 169151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57354 /* 169154 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
57355 /* 169158 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57356 /* 169162 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
57357 /* 169166 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
57358 /* 169170 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57359 /* 169174 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
57360 /* 169178 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
57361 /* 169180 */ // (fminnum_ieee:{ *:[f32] } (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$A), (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$B)) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMINDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57362 /* 169180 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
57363 /* 169183 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57364 /* 169187 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57365 /* 169192 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // B
57366 /* 169196 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57367 /* 169201 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57368 /* 169204 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57369 /* 169208 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57370 /* 169213 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // A
57371 /* 169217 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57372 /* 169222 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57373 /* 169225 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
57374 /* 169229 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57375 /* 169234 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57376 /* 169237 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
57377 /* 169240 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57378 /* 169242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57379 /* 169245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57380 /* 169247 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57381 /* 169250 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57382 /* 169255 */ // GIR_Coverage, 1689,
57383 /* 169255 */ GIR_EraseRootFromParent_Done,
57384 /* 169256 */ // Label 2635: @169256
57385 /* 169256 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(169354), // Rule ID 1687 //
57386 /* 169261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57387 /* 169264 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
57388 /* 169268 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57389 /* 169272 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
57390 /* 169276 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
57391 /* 169278 */ // (fminnum_ieee:{ *:[f32] } (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$A), f32:{ *:[f32] }:$B) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMINDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57392 /* 169278 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
57393 /* 169281 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57394 /* 169285 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57395 /* 169290 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // B
57396 /* 169294 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57397 /* 169299 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57398 /* 169302 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57399 /* 169306 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57400 /* 169311 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // A
57401 /* 169315 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57402 /* 169320 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57403 /* 169323 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
57404 /* 169327 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57405 /* 169332 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57406 /* 169335 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
57407 /* 169338 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57408 /* 169340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57409 /* 169343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57410 /* 169345 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57411 /* 169348 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57412 /* 169353 */ // GIR_Coverage, 1687,
57413 /* 169353 */ GIR_EraseRootFromParent_Done,
57414 /* 169354 */ // Label 2636: @169354
57415 /* 169354 */ GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(169452), // Rule ID 1688 //
57416 /* 169359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57417 /* 169362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
57418 /* 169366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57419 /* 169370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
57420 /* 169374 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
57421 /* 169376 */ // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$A, (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$B)) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMINDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57422 /* 169376 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
57423 /* 169379 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57424 /* 169383 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57425 /* 169388 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // B
57426 /* 169392 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57427 /* 169397 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57428 /* 169400 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57429 /* 169404 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57430 /* 169409 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
57431 /* 169413 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57432 /* 169418 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57433 /* 169421 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
57434 /* 169425 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57435 /* 169430 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57436 /* 169433 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
57437 /* 169436 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57438 /* 169438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57439 /* 169441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57440 /* 169443 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57441 /* 169446 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57442 /* 169451 */ // GIR_Coverage, 1688,
57443 /* 169451 */ GIR_EraseRootFromParent_Done,
57444 /* 169452 */ // Label 2637: @169452
57445 /* 169452 */ GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(169536), // Rule ID 1686 //
57446 /* 169457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57447 /* 169460 */ // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMINDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57448 /* 169460 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
57449 /* 169463 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57450 /* 169467 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57451 /* 169472 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // B
57452 /* 169476 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57453 /* 169481 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57454 /* 169484 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57455 /* 169488 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57456 /* 169493 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
57457 /* 169497 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57458 /* 169502 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57459 /* 169505 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
57460 /* 169509 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57461 /* 169514 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57462 /* 169517 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
57463 /* 169520 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57464 /* 169522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57465 /* 169525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57466 /* 169527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57467 /* 169530 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57468 /* 169535 */ // GIR_Coverage, 1686,
57469 /* 169535 */ GIR_EraseRootFromParent_Done,
57470 /* 169536 */ // Label 2638: @169536
57471 /* 169536 */ GIM_Reject,
57472 /* 169537 */ // Label 2634: @169537
57473 /* 169537 */ GIM_Reject,
57474 /* 169538 */ // Label 2632: @169538
57475 /* 169538 */ GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(169692),
57476 /* 169543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
57477 /* 169546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57478 /* 169549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
57479 /* 169553 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(169602), // Rule ID 1697 //
57480 /* 169558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57481 /* 169561 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
57482 /* 169565 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57483 /* 169569 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
57484 /* 169573 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
57485 /* 169577 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57486 /* 169581 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
57487 /* 169585 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
57488 /* 169587 */ // (fminnum_ieee:{ *:[f64] } (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$A), (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$B)) => (XSMINDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B)
57489 /* 169587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
57490 /* 169590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57491 /* 169592 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
57492 /* 169596 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // B
57493 /* 169600 */ GIR_RootConstrainSelectedInstOperands,
57494 /* 169601 */ // GIR_Coverage, 1697,
57495 /* 169601 */ GIR_EraseRootFromParent_Done,
57496 /* 169602 */ // Label 2640: @169602
57497 /* 169602 */ GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(169637), // Rule ID 1695 //
57498 /* 169607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57499 /* 169610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
57500 /* 169614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57501 /* 169618 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
57502 /* 169622 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
57503 /* 169624 */ // (fminnum_ieee:{ *:[f64] } (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$A), f64:{ *:[f64] }:$B) => (XSMINDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B)
57504 /* 169624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
57505 /* 169627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57506 /* 169629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
57507 /* 169633 */ GIR_RootToRootCopy, /*OpIdx*/2, // B
57508 /* 169635 */ GIR_RootConstrainSelectedInstOperands,
57509 /* 169636 */ // GIR_Coverage, 1695,
57510 /* 169636 */ GIR_EraseRootFromParent_Done,
57511 /* 169637 */ // Label 2641: @169637
57512 /* 169637 */ GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(169672), // Rule ID 1696 //
57513 /* 169642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57514 /* 169645 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
57515 /* 169649 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57516 /* 169653 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
57517 /* 169657 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
57518 /* 169659 */ // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$A, (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$B)) => (XSMINDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B)
57519 /* 169659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
57520 /* 169662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57521 /* 169664 */ GIR_RootToRootCopy, /*OpIdx*/1, // A
57522 /* 169666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // B
57523 /* 169670 */ GIR_RootConstrainSelectedInstOperands,
57524 /* 169671 */ // GIR_Coverage, 1696,
57525 /* 169671 */ GIR_EraseRootFromParent_Done,
57526 /* 169672 */ // Label 2642: @169672
57527 /* 169672 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(169691), // Rule ID 1694 //
57528 /* 169677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57529 /* 169680 */ // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B) => (XSMINDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B)
57530 /* 169680 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMINDP),
57531 /* 169685 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57532 /* 169689 */ GIR_RootConstrainSelectedInstOperands,
57533 /* 169690 */ // GIR_Coverage, 1694,
57534 /* 169690 */ GIR_Done,
57535 /* 169691 */ // Label 2643: @169691
57536 /* 169691 */ GIM_Reject,
57537 /* 169692 */ // Label 2639: @169692
57538 /* 169692 */ GIM_Reject,
57539 /* 169693 */ // Label 2633: @169693
57540 /* 169693 */ GIM_Reject,
57541 /* 169694 */ // Label 57: @169694
57542 /* 169694 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2646*/ GIMT_Encode4(170275),
57543 /* 169705 */ /*GILLT_s32*//*Label 2644*/ GIMT_Encode4(169713),
57544 /* 169709 */ /*GILLT_s64*//*Label 2645*/ GIMT_Encode4(170120),
57545 /* 169713 */ // Label 2644: @169713
57546 /* 169713 */ GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(170119),
57547 /* 169718 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
57548 /* 169721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57549 /* 169724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
57550 /* 169728 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(169838), // Rule ID 1693 //
57551 /* 169733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57552 /* 169736 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
57553 /* 169740 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57554 /* 169744 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
57555 /* 169748 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
57556 /* 169752 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57557 /* 169756 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
57558 /* 169760 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
57559 /* 169762 */ // (fmaxnum_ieee:{ *:[f32] } (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$A), (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$B)) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMAXDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57560 /* 169762 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
57561 /* 169765 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57562 /* 169769 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57563 /* 169774 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // B
57564 /* 169778 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57565 /* 169783 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57566 /* 169786 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57567 /* 169790 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57568 /* 169795 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // A
57569 /* 169799 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57570 /* 169804 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57571 /* 169807 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
57572 /* 169811 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57573 /* 169816 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57574 /* 169819 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
57575 /* 169822 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57576 /* 169824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57577 /* 169827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57578 /* 169829 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57579 /* 169832 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57580 /* 169837 */ // GIR_Coverage, 1693,
57581 /* 169837 */ GIR_EraseRootFromParent_Done,
57582 /* 169838 */ // Label 2648: @169838
57583 /* 169838 */ GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(169936), // Rule ID 1691 //
57584 /* 169843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57585 /* 169846 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
57586 /* 169850 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57587 /* 169854 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
57588 /* 169858 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
57589 /* 169860 */ // (fmaxnum_ieee:{ *:[f32] } (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$A), f32:{ *:[f32] }:$B) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMAXDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57590 /* 169860 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
57591 /* 169863 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57592 /* 169867 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57593 /* 169872 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // B
57594 /* 169876 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57595 /* 169881 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57596 /* 169884 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57597 /* 169888 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57598 /* 169893 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // A
57599 /* 169897 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57600 /* 169902 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57601 /* 169905 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
57602 /* 169909 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57603 /* 169914 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57604 /* 169917 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
57605 /* 169920 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57606 /* 169922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57607 /* 169925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57608 /* 169927 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57609 /* 169930 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57610 /* 169935 */ // GIR_Coverage, 1691,
57611 /* 169935 */ GIR_EraseRootFromParent_Done,
57612 /* 169936 */ // Label 2649: @169936
57613 /* 169936 */ GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(170034), // Rule ID 1692 //
57614 /* 169941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57615 /* 169944 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
57616 /* 169948 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57617 /* 169952 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
57618 /* 169956 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
57619 /* 169958 */ // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$A, (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$B)) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMAXDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57620 /* 169958 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
57621 /* 169961 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57622 /* 169965 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57623 /* 169970 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // B
57624 /* 169974 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57625 /* 169979 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57626 /* 169982 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57627 /* 169986 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57628 /* 169991 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
57629 /* 169995 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57630 /* 170000 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57631 /* 170003 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
57632 /* 170007 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57633 /* 170012 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57634 /* 170015 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
57635 /* 170018 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57636 /* 170020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57637 /* 170023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57638 /* 170025 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57639 /* 170028 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57640 /* 170033 */ // GIR_Coverage, 1692,
57641 /* 170033 */ GIR_EraseRootFromParent_Done,
57642 /* 170034 */ // Label 2650: @170034
57643 /* 170034 */ GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(170118), // Rule ID 1690 //
57644 /* 170039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57645 /* 170042 */ // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMAXDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
57646 /* 170042 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
57647 /* 170045 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57648 /* 170049 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57649 /* 170054 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // B
57650 /* 170058 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57651 /* 170063 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
57652 /* 170066 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57653 /* 170070 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57654 /* 170075 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
57655 /* 170079 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
57656 /* 170084 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
57657 /* 170087 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
57658 /* 170091 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57659 /* 170096 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
57660 /* 170099 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
57661 /* 170102 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57662 /* 170104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57663 /* 170107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57664 /* 170109 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57665 /* 170112 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
57666 /* 170117 */ // GIR_Coverage, 1690,
57667 /* 170117 */ GIR_EraseRootFromParent_Done,
57668 /* 170118 */ // Label 2651: @170118
57669 /* 170118 */ GIM_Reject,
57670 /* 170119 */ // Label 2647: @170119
57671 /* 170119 */ GIM_Reject,
57672 /* 170120 */ // Label 2645: @170120
57673 /* 170120 */ GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(170274),
57674 /* 170125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
57675 /* 170128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57676 /* 170131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
57677 /* 170135 */ GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(170184), // Rule ID 1701 //
57678 /* 170140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57679 /* 170143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
57680 /* 170147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57681 /* 170151 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
57682 /* 170155 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
57683 /* 170159 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57684 /* 170163 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
57685 /* 170167 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
57686 /* 170169 */ // (fmaxnum_ieee:{ *:[f64] } (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$A), (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$B)) => (XSMAXDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B)
57687 /* 170169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
57688 /* 170172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57689 /* 170174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
57690 /* 170178 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // B
57691 /* 170182 */ GIR_RootConstrainSelectedInstOperands,
57692 /* 170183 */ // GIR_Coverage, 1701,
57693 /* 170183 */ GIR_EraseRootFromParent_Done,
57694 /* 170184 */ // Label 2653: @170184
57695 /* 170184 */ GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(170219), // Rule ID 1699 //
57696 /* 170189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57697 /* 170192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
57698 /* 170196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57699 /* 170200 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
57700 /* 170204 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
57701 /* 170206 */ // (fmaxnum_ieee:{ *:[f64] } (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$A), f64:{ *:[f64] }:$B) => (XSMAXDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B)
57702 /* 170206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
57703 /* 170209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57704 /* 170211 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
57705 /* 170215 */ GIR_RootToRootCopy, /*OpIdx*/2, // B
57706 /* 170217 */ GIR_RootConstrainSelectedInstOperands,
57707 /* 170218 */ // GIR_Coverage, 1699,
57708 /* 170218 */ GIR_EraseRootFromParent_Done,
57709 /* 170219 */ // Label 2654: @170219
57710 /* 170219 */ GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(170254), // Rule ID 1700 //
57711 /* 170224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57712 /* 170227 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
57713 /* 170231 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
57714 /* 170235 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
57715 /* 170239 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
57716 /* 170241 */ // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$A, (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$B)) => (XSMAXDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B)
57717 /* 170241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
57718 /* 170244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
57719 /* 170246 */ GIR_RootToRootCopy, /*OpIdx*/1, // A
57720 /* 170248 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // B
57721 /* 170252 */ GIR_RootConstrainSelectedInstOperands,
57722 /* 170253 */ // GIR_Coverage, 1700,
57723 /* 170253 */ GIR_EraseRootFromParent_Done,
57724 /* 170254 */ // Label 2655: @170254
57725 /* 170254 */ GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(170273), // Rule ID 1698 //
57726 /* 170259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
57727 /* 170262 */ // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B) => (XSMAXDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B)
57728 /* 170262 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP),
57729 /* 170267 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
57730 /* 170271 */ GIR_RootConstrainSelectedInstOperands,
57731 /* 170272 */ // GIR_Coverage, 1698,
57732 /* 170272 */ GIR_Done,
57733 /* 170273 */ // Label 2656: @170273
57734 /* 170273 */ GIM_Reject,
57735 /* 170274 */ // Label 2652: @170274
57736 /* 170274 */ GIM_Reject,
57737 /* 170275 */ // Label 2646: @170275
57738 /* 170275 */ GIM_Reject,
57739 /* 170276 */ // Label 58: @170276
57740 /* 170276 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(8), /*)*//*default:*//*Label 2661*/ GIMT_Encode4(170455),
57741 /* 170287 */ /*GILLT_v2s64*//*Label 2657*/ GIMT_Encode4(170303),
57742 /* 170291 */ /*GILLT_v4s32*//*Label 2658*/ GIMT_Encode4(170377),
57743 /* 170295 */ /*GILLT_v8s16*//*Label 2659*/ GIMT_Encode4(170403),
57744 /* 170299 */ /*GILLT_v16s8*//*Label 2660*/ GIMT_Encode4(170429),
57745 /* 170303 */ // Label 2657: @170303
57746 /* 170303 */ GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(170376), // Rule ID 1933 //
57747 /* 170308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
57748 /* 170311 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
57749 /* 170314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
57750 /* 170317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57751 /* 170321 */ // (smin:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src1, v2i64:{ *:[v2i64] }:$src2) => (VMINSD:{ *:[v2i64] } (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src1, VRRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src2, VRRC:{ *:[i32] }))
57752 /* 170321 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
57753 /* 170324 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57754 /* 170328 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57755 /* 170333 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
57756 /* 170337 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
57757 /* 170342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
57758 /* 170345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57759 /* 170349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57760 /* 170354 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src1
57761 /* 170358 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
57762 /* 170363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSD),
57763 /* 170366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
57764 /* 170368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57765 /* 170371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
57766 /* 170374 */ GIR_RootConstrainSelectedInstOperands,
57767 /* 170375 */ // GIR_Coverage, 1933,
57768 /* 170375 */ GIR_EraseRootFromParent_Done,
57769 /* 170376 */ // Label 2662: @170376
57770 /* 170376 */ GIM_Reject,
57771 /* 170377 */ // Label 2658: @170377
57772 /* 170377 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(170402), // Rule ID 1362 //
57773 /* 170382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57774 /* 170385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
57775 /* 170388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
57776 /* 170391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57777 /* 170395 */ // (smin:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (VMINSW:{ *:[v4i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
57778 /* 170395 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINSW),
57779 /* 170400 */ GIR_RootConstrainSelectedInstOperands,
57780 /* 170401 */ // GIR_Coverage, 1362,
57781 /* 170401 */ GIR_Done,
57782 /* 170402 */ // Label 2663: @170402
57783 /* 170402 */ GIM_Reject,
57784 /* 170403 */ // Label 2659: @170403
57785 /* 170403 */ GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(170428), // Rule ID 1360 //
57786 /* 170408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57787 /* 170411 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
57788 /* 170414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
57789 /* 170417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57790 /* 170421 */ // (smin:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2) => (VMINSH:{ *:[v8i16] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
57791 /* 170421 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINSH),
57792 /* 170426 */ GIR_RootConstrainSelectedInstOperands,
57793 /* 170427 */ // GIR_Coverage, 1360,
57794 /* 170427 */ GIR_Done,
57795 /* 170428 */ // Label 2664: @170428
57796 /* 170428 */ GIM_Reject,
57797 /* 170429 */ // Label 2660: @170429
57798 /* 170429 */ GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(170454), // Rule ID 1358 //
57799 /* 170434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57800 /* 170437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
57801 /* 170440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
57802 /* 170443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57803 /* 170447 */ // (smin:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src1, v16i8:{ *:[v16i8] }:$src2) => (VMINSB:{ *:[v16i8] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
57804 /* 170447 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINSB),
57805 /* 170452 */ GIR_RootConstrainSelectedInstOperands,
57806 /* 170453 */ // GIR_Coverage, 1358,
57807 /* 170453 */ GIR_Done,
57808 /* 170454 */ // Label 2665: @170454
57809 /* 170454 */ GIM_Reject,
57810 /* 170455 */ // Label 2661: @170455
57811 /* 170455 */ GIM_Reject,
57812 /* 170456 */ // Label 59: @170456
57813 /* 170456 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(8), /*)*//*default:*//*Label 2670*/ GIMT_Encode4(170635),
57814 /* 170467 */ /*GILLT_v2s64*//*Label 2666*/ GIMT_Encode4(170483),
57815 /* 170471 */ /*GILLT_v4s32*//*Label 2667*/ GIMT_Encode4(170557),
57816 /* 170475 */ /*GILLT_v8s16*//*Label 2668*/ GIMT_Encode4(170583),
57817 /* 170479 */ /*GILLT_v16s8*//*Label 2669*/ GIMT_Encode4(170609),
57818 /* 170483 */ // Label 2666: @170483
57819 /* 170483 */ GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(170556), // Rule ID 1931 //
57820 /* 170488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
57821 /* 170491 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
57822 /* 170494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
57823 /* 170497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57824 /* 170501 */ // (smax:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src1, v2i64:{ *:[v2i64] }:$src2) => (VMAXSD:{ *:[v2i64] } (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src1, VRRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src2, VRRC:{ *:[i32] }))
57825 /* 170501 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
57826 /* 170504 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57827 /* 170508 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57828 /* 170513 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
57829 /* 170517 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
57830 /* 170522 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
57831 /* 170525 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57832 /* 170529 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57833 /* 170534 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src1
57834 /* 170538 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
57835 /* 170543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSD),
57836 /* 170546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
57837 /* 170548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57838 /* 170551 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
57839 /* 170554 */ GIR_RootConstrainSelectedInstOperands,
57840 /* 170555 */ // GIR_Coverage, 1931,
57841 /* 170555 */ GIR_EraseRootFromParent_Done,
57842 /* 170556 */ // Label 2671: @170556
57843 /* 170556 */ GIM_Reject,
57844 /* 170557 */ // Label 2667: @170557
57845 /* 170557 */ GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(170582), // Rule ID 1356 //
57846 /* 170562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57847 /* 170565 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
57848 /* 170568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
57849 /* 170571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57850 /* 170575 */ // (smax:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (VMAXSW:{ *:[v4i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
57851 /* 170575 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXSW),
57852 /* 170580 */ GIR_RootConstrainSelectedInstOperands,
57853 /* 170581 */ // GIR_Coverage, 1356,
57854 /* 170581 */ GIR_Done,
57855 /* 170582 */ // Label 2672: @170582
57856 /* 170582 */ GIM_Reject,
57857 /* 170583 */ // Label 2668: @170583
57858 /* 170583 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(170608), // Rule ID 1354 //
57859 /* 170588 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57860 /* 170591 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
57861 /* 170594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
57862 /* 170597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57863 /* 170601 */ // (smax:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2) => (VMAXSH:{ *:[v8i16] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
57864 /* 170601 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXSH),
57865 /* 170606 */ GIR_RootConstrainSelectedInstOperands,
57866 /* 170607 */ // GIR_Coverage, 1354,
57867 /* 170607 */ GIR_Done,
57868 /* 170608 */ // Label 2673: @170608
57869 /* 170608 */ GIM_Reject,
57870 /* 170609 */ // Label 2669: @170609
57871 /* 170609 */ GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(170634), // Rule ID 1352 //
57872 /* 170614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57873 /* 170617 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
57874 /* 170620 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
57875 /* 170623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57876 /* 170627 */ // (smax:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src1, v16i8:{ *:[v16i8] }:$src2) => (VMAXSB:{ *:[v16i8] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
57877 /* 170627 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXSB),
57878 /* 170632 */ GIR_RootConstrainSelectedInstOperands,
57879 /* 170633 */ // GIR_Coverage, 1352,
57880 /* 170633 */ GIR_Done,
57881 /* 170634 */ // Label 2674: @170634
57882 /* 170634 */ GIM_Reject,
57883 /* 170635 */ // Label 2670: @170635
57884 /* 170635 */ GIM_Reject,
57885 /* 170636 */ // Label 60: @170636
57886 /* 170636 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(8), /*)*//*default:*//*Label 2679*/ GIMT_Encode4(170815),
57887 /* 170647 */ /*GILLT_v2s64*//*Label 2675*/ GIMT_Encode4(170663),
57888 /* 170651 */ /*GILLT_v4s32*//*Label 2676*/ GIMT_Encode4(170737),
57889 /* 170655 */ /*GILLT_v8s16*//*Label 2677*/ GIMT_Encode4(170763),
57890 /* 170659 */ /*GILLT_v16s8*//*Label 2678*/ GIMT_Encode4(170789),
57891 /* 170663 */ // Label 2675: @170663
57892 /* 170663 */ GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(170736), // Rule ID 1934 //
57893 /* 170668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
57894 /* 170671 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
57895 /* 170674 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
57896 /* 170677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57897 /* 170681 */ // (umin:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src1, v2i64:{ *:[v2i64] }:$src2) => (VMINUD:{ *:[v2i64] } (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src1, VRRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src2, VRRC:{ *:[i32] }))
57898 /* 170681 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
57899 /* 170684 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57900 /* 170688 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57901 /* 170693 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
57902 /* 170697 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
57903 /* 170702 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
57904 /* 170705 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57905 /* 170709 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57906 /* 170714 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src1
57907 /* 170718 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
57908 /* 170723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUD),
57909 /* 170726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
57910 /* 170728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57911 /* 170731 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
57912 /* 170734 */ GIR_RootConstrainSelectedInstOperands,
57913 /* 170735 */ // GIR_Coverage, 1934,
57914 /* 170735 */ GIR_EraseRootFromParent_Done,
57915 /* 170736 */ // Label 2680: @170736
57916 /* 170736 */ GIM_Reject,
57917 /* 170737 */ // Label 2676: @170737
57918 /* 170737 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(170762), // Rule ID 1361 //
57919 /* 170742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57920 /* 170745 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
57921 /* 170748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
57922 /* 170751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57923 /* 170755 */ // (umin:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (VMINUW:{ *:[v4i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
57924 /* 170755 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINUW),
57925 /* 170760 */ GIR_RootConstrainSelectedInstOperands,
57926 /* 170761 */ // GIR_Coverage, 1361,
57927 /* 170761 */ GIR_Done,
57928 /* 170762 */ // Label 2681: @170762
57929 /* 170762 */ GIM_Reject,
57930 /* 170763 */ // Label 2677: @170763
57931 /* 170763 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(170788), // Rule ID 1359 //
57932 /* 170768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57933 /* 170771 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
57934 /* 170774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
57935 /* 170777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57936 /* 170781 */ // (umin:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2) => (VMINUH:{ *:[v8i16] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
57937 /* 170781 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINUH),
57938 /* 170786 */ GIR_RootConstrainSelectedInstOperands,
57939 /* 170787 */ // GIR_Coverage, 1359,
57940 /* 170787 */ GIR_Done,
57941 /* 170788 */ // Label 2682: @170788
57942 /* 170788 */ GIM_Reject,
57943 /* 170789 */ // Label 2678: @170789
57944 /* 170789 */ GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(170814), // Rule ID 1357 //
57945 /* 170794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57946 /* 170797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
57947 /* 170800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
57948 /* 170803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57949 /* 170807 */ // (umin:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src1, v16i8:{ *:[v16i8] }:$src2) => (VMINUB:{ *:[v16i8] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
57950 /* 170807 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINUB),
57951 /* 170812 */ GIR_RootConstrainSelectedInstOperands,
57952 /* 170813 */ // GIR_Coverage, 1357,
57953 /* 170813 */ GIR_Done,
57954 /* 170814 */ // Label 2683: @170814
57955 /* 170814 */ GIM_Reject,
57956 /* 170815 */ // Label 2679: @170815
57957 /* 170815 */ GIM_Reject,
57958 /* 170816 */ // Label 61: @170816
57959 /* 170816 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(8), /*)*//*default:*//*Label 2688*/ GIMT_Encode4(170995),
57960 /* 170827 */ /*GILLT_v2s64*//*Label 2684*/ GIMT_Encode4(170843),
57961 /* 170831 */ /*GILLT_v4s32*//*Label 2685*/ GIMT_Encode4(170917),
57962 /* 170835 */ /*GILLT_v8s16*//*Label 2686*/ GIMT_Encode4(170943),
57963 /* 170839 */ /*GILLT_v16s8*//*Label 2687*/ GIMT_Encode4(170969),
57964 /* 170843 */ // Label 2684: @170843
57965 /* 170843 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(170916), // Rule ID 1932 //
57966 /* 170848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
57967 /* 170851 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
57968 /* 170854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
57969 /* 170857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57970 /* 170861 */ // (umax:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src1, v2i64:{ *:[v2i64] }:$src2) => (VMAXUD:{ *:[v2i64] } (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src1, VRRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src2, VRRC:{ *:[i32] }))
57971 /* 170861 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
57972 /* 170864 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57973 /* 170868 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57974 /* 170873 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
57975 /* 170877 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
57976 /* 170882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
57977 /* 170885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
57978 /* 170889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57979 /* 170894 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src1
57980 /* 170898 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
57981 /* 170903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUD),
57982 /* 170906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
57983 /* 170908 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57984 /* 170911 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
57985 /* 170914 */ GIR_RootConstrainSelectedInstOperands,
57986 /* 170915 */ // GIR_Coverage, 1932,
57987 /* 170915 */ GIR_EraseRootFromParent_Done,
57988 /* 170916 */ // Label 2689: @170916
57989 /* 170916 */ GIM_Reject,
57990 /* 170917 */ // Label 2685: @170917
57991 /* 170917 */ GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(170942), // Rule ID 1355 //
57992 /* 170922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
57993 /* 170925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
57994 /* 170928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
57995 /* 170931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
57996 /* 170935 */ // (umax:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (VMAXUW:{ *:[v4i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
57997 /* 170935 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXUW),
57998 /* 170940 */ GIR_RootConstrainSelectedInstOperands,
57999 /* 170941 */ // GIR_Coverage, 1355,
58000 /* 170941 */ GIR_Done,
58001 /* 170942 */ // Label 2690: @170942
58002 /* 170942 */ GIM_Reject,
58003 /* 170943 */ // Label 2686: @170943
58004 /* 170943 */ GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(170968), // Rule ID 1353 //
58005 /* 170948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
58006 /* 170951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
58007 /* 170954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
58008 /* 170957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58009 /* 170961 */ // (umax:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2) => (VMAXUH:{ *:[v8i16] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
58010 /* 170961 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXUH),
58011 /* 170966 */ GIR_RootConstrainSelectedInstOperands,
58012 /* 170967 */ // GIR_Coverage, 1353,
58013 /* 170967 */ GIR_Done,
58014 /* 170968 */ // Label 2691: @170968
58015 /* 170968 */ GIM_Reject,
58016 /* 170969 */ // Label 2687: @170969
58017 /* 170969 */ GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(170994), // Rule ID 1351 //
58018 /* 170974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
58019 /* 170977 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
58020 /* 170980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
58021 /* 170983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58022 /* 170987 */ // (umax:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src1, v16i8:{ *:[v16i8] }:$src2) => (VMAXUB:{ *:[v16i8] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
58023 /* 170987 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXUB),
58024 /* 170992 */ GIR_RootConstrainSelectedInstOperands,
58025 /* 170993 */ // GIR_Coverage, 1351,
58026 /* 170993 */ GIR_Done,
58027 /* 170994 */ // Label 2692: @170994
58028 /* 170994 */ GIM_Reject,
58029 /* 170995 */ // Label 2688: @170995
58030 /* 170995 */ GIM_Reject,
58031 /* 170996 */ // Label 62: @170996
58032 /* 170996 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2695*/ GIMT_Encode4(171297),
58033 /* 171007 */ /*GILLT_s32*//*Label 2693*/ GIMT_Encode4(171015),
58034 /* 171011 */ /*GILLT_s64*//*Label 2694*/ GIMT_Encode4(171156),
58035 /* 171015 */ // Label 2693: @171015
58036 /* 171015 */ GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(171075), // Rule ID 2039 //
58037 /* 171020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
58038 /* 171023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
58039 /* 171026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
58040 /* 171030 */ // (lround:{ *:[i32] } f64:{ *:[f64] }:$S) => (MFVSRWZ:{ *:[i32] } (FCTIW:{ *:[f64] } (XSRDPI:{ *:[f64] } ?:{ *:[f64] }:$S)))
58041 /* 171030 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
58042 /* 171033 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI),
58043 /* 171037 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58044 /* 171042 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
58045 /* 171046 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
58046 /* 171048 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
58047 /* 171051 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTIW),
58048 /* 171055 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58049 /* 171060 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
58050 /* 171063 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58051 /* 171065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ),
58052 /* 171068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
58053 /* 171070 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58054 /* 171073 */ GIR_RootConstrainSelectedInstOperands,
58055 /* 171074 */ // GIR_Coverage, 2039,
58056 /* 171074 */ GIR_EraseRootFromParent_Done,
58057 /* 171075 */ // Label 2696: @171075
58058 /* 171075 */ GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(171155), // Rule ID 2040 //
58059 /* 171080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
58060 /* 171083 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
58061 /* 171086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
58062 /* 171090 */ // (lround:{ *:[i32] } f32:{ *:[f32] }:$S) => (MFVSRWZ:{ *:[i32] } (FCTIW:{ *:[f64] } (XSRDPI:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] }))))
58063 /* 171090 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
58064 /* 171093 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
58065 /* 171097 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58066 /* 171102 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // S
58067 /* 171106 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
58068 /* 171111 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
58069 /* 171114 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI),
58070 /* 171118 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58071 /* 171123 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
58072 /* 171126 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
58073 /* 171128 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
58074 /* 171131 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTIW),
58075 /* 171135 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58076 /* 171140 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
58077 /* 171143 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58078 /* 171145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ),
58079 /* 171148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
58080 /* 171150 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58081 /* 171153 */ GIR_RootConstrainSelectedInstOperands,
58082 /* 171154 */ // GIR_Coverage, 2040,
58083 /* 171154 */ GIR_EraseRootFromParent_Done,
58084 /* 171155 */ // Label 2697: @171155
58085 /* 171155 */ GIM_Reject,
58086 /* 171156 */ // Label 2694: @171156
58087 /* 171156 */ GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(171216), // Rule ID 2037 //
58088 /* 171161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
58089 /* 171164 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
58090 /* 171167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
58091 /* 171171 */ // (lround:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (XSRDPI:{ *:[f64] } ?:{ *:[f64] }:$S)))
58092 /* 171171 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
58093 /* 171174 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI),
58094 /* 171178 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58095 /* 171183 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
58096 /* 171187 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
58097 /* 171189 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
58098 /* 171192 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID),
58099 /* 171196 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58100 /* 171201 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
58101 /* 171204 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58102 /* 171206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
58103 /* 171209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
58104 /* 171211 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58105 /* 171214 */ GIR_RootConstrainSelectedInstOperands,
58106 /* 171215 */ // GIR_Coverage, 2037,
58107 /* 171215 */ GIR_EraseRootFromParent_Done,
58108 /* 171216 */ // Label 2698: @171216
58109 /* 171216 */ GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(171296), // Rule ID 2038 //
58110 /* 171221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
58111 /* 171224 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
58112 /* 171227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
58113 /* 171231 */ // (lround:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (XSRDPI:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] }))))
58114 /* 171231 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
58115 /* 171234 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
58116 /* 171238 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58117 /* 171243 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // S
58118 /* 171247 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
58119 /* 171252 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
58120 /* 171255 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI),
58121 /* 171259 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58122 /* 171264 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
58123 /* 171267 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
58124 /* 171269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
58125 /* 171272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID),
58126 /* 171276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58127 /* 171281 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
58128 /* 171284 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58129 /* 171286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
58130 /* 171289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
58131 /* 171291 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58132 /* 171294 */ GIR_RootConstrainSelectedInstOperands,
58133 /* 171295 */ // GIR_Coverage, 2038,
58134 /* 171295 */ GIR_EraseRootFromParent_Done,
58135 /* 171296 */ // Label 2699: @171296
58136 /* 171296 */ GIM_Reject,
58137 /* 171297 */ // Label 2695: @171297
58138 /* 171297 */ GIM_Reject,
58139 /* 171298 */ // Label 63: @171298
58140 /* 171298 */ GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(171462),
58141 /* 171303 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
58142 /* 171306 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2703*/ GIMT_Encode4(171461),
58143 /* 171317 */ /*GILLT_s32*//*Label 2701*/ GIMT_Encode4(171325),
58144 /* 171321 */ /*GILLT_s64*//*Label 2702*/ GIMT_Encode4(171403),
58145 /* 171325 */ // Label 2701: @171325
58146 /* 171325 */ GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(171402), // Rule ID 2042 //
58147 /* 171330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
58148 /* 171333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
58149 /* 171337 */ // (llround:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (XSRDPI:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] }))))
58150 /* 171337 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
58151 /* 171340 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
58152 /* 171344 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58153 /* 171349 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // S
58154 /* 171353 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
58155 /* 171358 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
58156 /* 171361 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI),
58157 /* 171365 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58158 /* 171370 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
58159 /* 171373 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
58160 /* 171375 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
58161 /* 171378 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID),
58162 /* 171382 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58163 /* 171387 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
58164 /* 171390 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58165 /* 171392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
58166 /* 171395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
58167 /* 171397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58168 /* 171400 */ GIR_RootConstrainSelectedInstOperands,
58169 /* 171401 */ // GIR_Coverage, 2042,
58170 /* 171401 */ GIR_EraseRootFromParent_Done,
58171 /* 171402 */ // Label 2704: @171402
58172 /* 171402 */ GIM_Reject,
58173 /* 171403 */ // Label 2702: @171403
58174 /* 171403 */ GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(171460), // Rule ID 2041 //
58175 /* 171408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX),
58176 /* 171411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
58177 /* 171415 */ // (llround:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (XSRDPI:{ *:[f64] } ?:{ *:[f64] }:$S)))
58178 /* 171415 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
58179 /* 171418 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI),
58180 /* 171422 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58181 /* 171427 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
58182 /* 171431 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
58183 /* 171433 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
58184 /* 171436 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID),
58185 /* 171440 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58186 /* 171445 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
58187 /* 171448 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58188 /* 171450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD),
58189 /* 171453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
58190 /* 171455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58191 /* 171458 */ GIR_RootConstrainSelectedInstOperands,
58192 /* 171459 */ // GIR_Coverage, 2041,
58193 /* 171459 */ GIR_EraseRootFromParent_Done,
58194 /* 171460 */ // Label 2705: @171460
58195 /* 171460 */ GIM_Reject,
58196 /* 171461 */ // Label 2703: @171461
58197 /* 171461 */ GIM_Reject,
58198 /* 171462 */ // Label 2700: @171462
58199 /* 171462 */ GIM_Reject,
58200 /* 171463 */ // Label 64: @171463
58201 /* 171463 */ GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(171478), // Rule ID 15 //
58202 /* 171468 */ // MIs[0] LI
58203 /* 171468 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
58204 /* 171471 */ // (br (bb:{ *:[Other] }):$LI) => (B (bb:{ *:[Other] }):$LI)
58205 /* 171471 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::B),
58206 /* 171476 */ GIR_RootConstrainSelectedInstOperands,
58207 /* 171477 */ // GIR_Coverage, 15,
58208 /* 171477 */ GIR_Done,
58209 /* 171478 */ // Label 2706: @171478
58210 /* 171478 */ GIM_Reject,
58211 /* 171479 */ // Label 65: @171479
58212 /* 171479 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 2709*/ GIMT_Encode4(171596),
58213 /* 171490 */ /*GILLT_v8s16*//*Label 2707*/ GIMT_Encode4(171498),
58214 /* 171494 */ /*GILLT_v16s8*//*Label 2708*/ GIMT_Encode4(171561),
58215 /* 171498 */ // Label 2707: @171498
58216 /* 171498 */ GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(171560), // Rule ID 3494 //
58217 /* 171503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsBigEndian_IsISA3_1_IsPPC32),
58218 /* 171506 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
58219 /* 171509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
58220 /* 171512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
58221 /* 171515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58222 /* 171519 */ // (vector_insert:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSHLX:{ *:[v8i16] } ?:{ *:[v8i16] }:$vDi, (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$rB, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), ?:{ *:[i32] }:$rA)
58223 /* 171519 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
58224 /* 171522 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58225 /* 171526 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58226 /* 171531 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rB
58227 /* 171535 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
58228 /* 171538 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
58229 /* 171541 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/30,
58230 /* 171544 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58231 /* 171546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHLX),
58232 /* 171549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
58233 /* 171551 */ GIR_RootToRootCopy, /*OpIdx*/1, // vDi
58234 /* 171553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58235 /* 171556 */ GIR_RootToRootCopy, /*OpIdx*/2, // rA
58236 /* 171558 */ GIR_RootConstrainSelectedInstOperands,
58237 /* 171559 */ // GIR_Coverage, 3494,
58238 /* 171559 */ GIR_EraseRootFromParent_Done,
58239 /* 171560 */ // Label 2710: @171560
58240 /* 171560 */ GIM_Reject,
58241 /* 171561 */ // Label 2708: @171561
58242 /* 171561 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(171595), // Rule ID 3493 //
58243 /* 171566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsBigEndian_IsISA3_1_IsPPC32),
58244 /* 171569 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
58245 /* 171572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
58246 /* 171575 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
58247 /* 171578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58248 /* 171582 */ // (vector_insert:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSBLX:{ *:[v16i8] } ?:{ *:[v16i8] }:$vDi, ?:{ *:[i32] }:$rB, ?:{ *:[i32] }:$rA)
58249 /* 171582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBLX),
58250 /* 171585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD]
58251 /* 171587 */ GIR_RootToRootCopy, /*OpIdx*/1, // vDi
58252 /* 171589 */ GIR_RootToRootCopy, /*OpIdx*/3, // rB
58253 /* 171591 */ GIR_RootToRootCopy, /*OpIdx*/2, // rA
58254 /* 171593 */ GIR_RootConstrainSelectedInstOperands,
58255 /* 171594 */ // GIR_Coverage, 3493,
58256 /* 171594 */ GIR_EraseRootFromParent_Done,
58257 /* 171595 */ // Label 2711: @171595
58258 /* 171595 */ GIM_Reject,
58259 /* 171596 */ // Label 2709: @171596
58260 /* 171596 */ GIM_Reject,
58261 /* 171597 */ // Label 66: @171597
58262 /* 171597 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 2718*/ GIMT_Encode4(171774),
58263 /* 171608 */ /*GILLT_s32*//*Label 2712*/ GIMT_Encode4(171636),
58264 /* 171612 */ /*GILLT_s64*//*Label 2713*/ GIMT_Encode4(171659), GIMT_Encode4(0),
58265 /* 171620 */ /*GILLT_v2s64*//*Label 2714*/ GIMT_Encode4(171682),
58266 /* 171624 */ /*GILLT_v4s32*//*Label 2715*/ GIMT_Encode4(171705),
58267 /* 171628 */ /*GILLT_v8s16*//*Label 2716*/ GIMT_Encode4(171728),
58268 /* 171632 */ /*GILLT_v16s8*//*Label 2717*/ GIMT_Encode4(171751),
58269 /* 171636 */ // Label 2712: @171636
58270 /* 171636 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(171658), // Rule ID 134 //
58271 /* 171641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
58272 /* 171644 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
58273 /* 171647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
58274 /* 171651 */ // (cttz:{ *:[i32] } i32:{ *:[i32] }:$RST) => (CNTTZW:{ *:[i32] } i32:{ *:[i32] }:$RST)
58275 /* 171651 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CNTTZW),
58276 /* 171656 */ GIR_RootConstrainSelectedInstOperands,
58277 /* 171657 */ // GIR_Coverage, 134,
58278 /* 171657 */ GIR_Done,
58279 /* 171658 */ // Label 2719: @171658
58280 /* 171658 */ GIM_Reject,
58281 /* 171659 */ // Label 2713: @171659
58282 /* 171659 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(171681), // Rule ID 688 //
58283 /* 171664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0),
58284 /* 171667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
58285 /* 171670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
58286 /* 171674 */ // (cttz:{ *:[i64] } i64:{ *:[i64] }:$RST) => (CNTTZD:{ *:[i64] } i64:{ *:[i64] }:$RST)
58287 /* 171674 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CNTTZD),
58288 /* 171679 */ GIR_RootConstrainSelectedInstOperands,
58289 /* 171680 */ // GIR_Coverage, 688,
58290 /* 171680 */ GIR_Done,
58291 /* 171681 */ // Label 2720: @171681
58292 /* 171681 */ GIM_Reject,
58293 /* 171682 */ // Label 2714: @171682
58294 /* 171682 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(171704), // Rule ID 535 //
58295 /* 171687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
58296 /* 171690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
58297 /* 171693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58298 /* 171697 */ // (cttz:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) => (VCTZD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB)
58299 /* 171697 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTZD),
58300 /* 171702 */ GIR_RootConstrainSelectedInstOperands,
58301 /* 171703 */ // GIR_Coverage, 535,
58302 /* 171703 */ GIR_Done,
58303 /* 171704 */ // Label 2721: @171704
58304 /* 171704 */ GIM_Reject,
58305 /* 171705 */ // Label 2715: @171705
58306 /* 171705 */ GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(171727), // Rule ID 534 //
58307 /* 171710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
58308 /* 171713 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
58309 /* 171716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58310 /* 171720 */ // (cttz:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) => (VCTZW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB)
58311 /* 171720 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTZW),
58312 /* 171725 */ GIR_RootConstrainSelectedInstOperands,
58313 /* 171726 */ // GIR_Coverage, 534,
58314 /* 171726 */ GIR_Done,
58315 /* 171727 */ // Label 2722: @171727
58316 /* 171727 */ GIM_Reject,
58317 /* 171728 */ // Label 2716: @171728
58318 /* 171728 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(171750), // Rule ID 533 //
58319 /* 171733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
58320 /* 171736 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
58321 /* 171739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58322 /* 171743 */ // (cttz:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) => (VCTZH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB)
58323 /* 171743 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTZH),
58324 /* 171748 */ GIR_RootConstrainSelectedInstOperands,
58325 /* 171749 */ // GIR_Coverage, 533,
58326 /* 171749 */ GIR_Done,
58327 /* 171750 */ // Label 2723: @171750
58328 /* 171750 */ GIM_Reject,
58329 /* 171751 */ // Label 2717: @171751
58330 /* 171751 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(171773), // Rule ID 532 //
58331 /* 171756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec),
58332 /* 171759 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
58333 /* 171762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58334 /* 171766 */ // (cttz:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) => (VCTZB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB)
58335 /* 171766 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTZB),
58336 /* 171771 */ GIR_RootConstrainSelectedInstOperands,
58337 /* 171772 */ // GIR_Coverage, 532,
58338 /* 171772 */ GIR_Done,
58339 /* 171773 */ // Label 2724: @171773
58340 /* 171773 */ GIM_Reject,
58341 /* 171774 */ // Label 2718: @171774
58342 /* 171774 */ GIM_Reject,
58343 /* 171775 */ // Label 67: @171775
58344 /* 171775 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 2731*/ GIMT_Encode4(171946),
58345 /* 171786 */ /*GILLT_s32*//*Label 2725*/ GIMT_Encode4(171814),
58346 /* 171790 */ /*GILLT_s64*//*Label 2726*/ GIMT_Encode4(171834), GIMT_Encode4(0),
58347 /* 171798 */ /*GILLT_v2s64*//*Label 2727*/ GIMT_Encode4(171854),
58348 /* 171802 */ /*GILLT_v4s32*//*Label 2728*/ GIMT_Encode4(171877),
58349 /* 171806 */ /*GILLT_v8s16*//*Label 2729*/ GIMT_Encode4(171900),
58350 /* 171810 */ /*GILLT_v16s8*//*Label 2730*/ GIMT_Encode4(171923),
58351 /* 171814 */ // Label 2725: @171814
58352 /* 171814 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(171833), // Rule ID 133 //
58353 /* 171819 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
58354 /* 171822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
58355 /* 171826 */ // (ctlz:{ *:[i32] } i32:{ *:[i32] }:$RST) => (CNTLZW:{ *:[i32] } i32:{ *:[i32] }:$RST)
58356 /* 171826 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CNTLZW),
58357 /* 171831 */ GIR_RootConstrainSelectedInstOperands,
58358 /* 171832 */ // GIR_Coverage, 133,
58359 /* 171832 */ GIR_Done,
58360 /* 171833 */ // Label 2732: @171833
58361 /* 171833 */ GIM_Reject,
58362 /* 171834 */ // Label 2726: @171834
58363 /* 171834 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(171853), // Rule ID 687 //
58364 /* 171839 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
58365 /* 171842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
58366 /* 171846 */ // (ctlz:{ *:[i64] } i64:{ *:[i64] }:$RST) => (CNTLZD:{ *:[i64] } i64:{ *:[i64] }:$RST)
58367 /* 171846 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CNTLZD),
58368 /* 171851 */ GIR_RootConstrainSelectedInstOperands,
58369 /* 171852 */ // GIR_Coverage, 687,
58370 /* 171852 */ GIR_Done,
58371 /* 171853 */ // Label 2733: @171853
58372 /* 171853 */ GIM_Reject,
58373 /* 171854 */ // Label 2727: @171854
58374 /* 171854 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(171876), // Rule ID 482 //
58375 /* 171859 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
58376 /* 171862 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
58377 /* 171865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58378 /* 171869 */ // (ctlz:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) => (VCLZD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB)
58379 /* 171869 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCLZD),
58380 /* 171874 */ GIR_RootConstrainSelectedInstOperands,
58381 /* 171875 */ // GIR_Coverage, 482,
58382 /* 171875 */ GIR_Done,
58383 /* 171876 */ // Label 2734: @171876
58384 /* 171876 */ GIM_Reject,
58385 /* 171877 */ // Label 2728: @171877
58386 /* 171877 */ GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(171899), // Rule ID 481 //
58387 /* 171882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
58388 /* 171885 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
58389 /* 171888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58390 /* 171892 */ // (ctlz:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) => (VCLZW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB)
58391 /* 171892 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCLZW),
58392 /* 171897 */ GIR_RootConstrainSelectedInstOperands,
58393 /* 171898 */ // GIR_Coverage, 481,
58394 /* 171898 */ GIR_Done,
58395 /* 171899 */ // Label 2735: @171899
58396 /* 171899 */ GIM_Reject,
58397 /* 171900 */ // Label 2729: @171900
58398 /* 171900 */ GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(171922), // Rule ID 480 //
58399 /* 171905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
58400 /* 171908 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
58401 /* 171911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58402 /* 171915 */ // (ctlz:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) => (VCLZH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB)
58403 /* 171915 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCLZH),
58404 /* 171920 */ GIR_RootConstrainSelectedInstOperands,
58405 /* 171921 */ // GIR_Coverage, 480,
58406 /* 171921 */ GIR_Done,
58407 /* 171922 */ // Label 2736: @171922
58408 /* 171922 */ GIM_Reject,
58409 /* 171923 */ // Label 2730: @171923
58410 /* 171923 */ GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(171945), // Rule ID 479 //
58411 /* 171928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
58412 /* 171931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
58413 /* 171934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58414 /* 171938 */ // (ctlz:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) => (VCLZB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB)
58415 /* 171938 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCLZB),
58416 /* 171943 */ GIR_RootConstrainSelectedInstOperands,
58417 /* 171944 */ // GIR_Coverage, 479,
58418 /* 171944 */ GIR_Done,
58419 /* 171945 */ // Label 2737: @171945
58420 /* 171945 */ GIM_Reject,
58421 /* 171946 */ // Label 2731: @171946
58422 /* 171946 */ GIM_Reject,
58423 /* 171947 */ // Label 68: @171947
58424 /* 171947 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 2744*/ GIMT_Encode4(172118),
58425 /* 171958 */ /*GILLT_s32*//*Label 2738*/ GIMT_Encode4(171986),
58426 /* 171962 */ /*GILLT_s64*//*Label 2739*/ GIMT_Encode4(172006), GIMT_Encode4(0),
58427 /* 171970 */ /*GILLT_v2s64*//*Label 2740*/ GIMT_Encode4(172026),
58428 /* 171974 */ /*GILLT_v4s32*//*Label 2741*/ GIMT_Encode4(172049),
58429 /* 171978 */ /*GILLT_v8s16*//*Label 2742*/ GIMT_Encode4(172072),
58430 /* 171982 */ /*GILLT_v16s8*//*Label 2743*/ GIMT_Encode4(172095),
58431 /* 171986 */ // Label 2738: @171986
58432 /* 171986 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(172005), // Rule ID 692 //
58433 /* 171991 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
58434 /* 171994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
58435 /* 171998 */ // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$RST) => (POPCNTW:{ *:[i32] } i32:{ *:[i32] }:$RST)
58436 /* 171998 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::POPCNTW),
58437 /* 172003 */ GIR_RootConstrainSelectedInstOperands,
58438 /* 172004 */ // GIR_Coverage, 692,
58439 /* 172004 */ GIR_Done,
58440 /* 172005 */ // Label 2745: @172005
58441 /* 172005 */ GIM_Reject,
58442 /* 172006 */ // Label 2739: @172006
58443 /* 172006 */ GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(172025), // Rule ID 689 //
58444 /* 172011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
58445 /* 172014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
58446 /* 172018 */ // (ctpop:{ *:[i64] } i64:{ *:[i64] }:$RST) => (POPCNTD:{ *:[i64] } i64:{ *:[i64] }:$RST)
58447 /* 172018 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::POPCNTD),
58448 /* 172023 */ GIR_RootConstrainSelectedInstOperands,
58449 /* 172024 */ // GIR_Coverage, 689,
58450 /* 172024 */ GIR_Done,
58451 /* 172025 */ // Label 2746: @172025
58452 /* 172025 */ GIM_Reject,
58453 /* 172026 */ // Label 2740: @172026
58454 /* 172026 */ GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(172048), // Rule ID 486 //
58455 /* 172031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
58456 /* 172034 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
58457 /* 172037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58458 /* 172041 */ // (ctpop:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) => (VPOPCNTD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB)
58459 /* 172041 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VPOPCNTD),
58460 /* 172046 */ GIR_RootConstrainSelectedInstOperands,
58461 /* 172047 */ // GIR_Coverage, 486,
58462 /* 172047 */ GIR_Done,
58463 /* 172048 */ // Label 2747: @172048
58464 /* 172048 */ GIM_Reject,
58465 /* 172049 */ // Label 2741: @172049
58466 /* 172049 */ GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(172071), // Rule ID 485 //
58467 /* 172054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
58468 /* 172057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
58469 /* 172060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58470 /* 172064 */ // (ctpop:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) => (VPOPCNTW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB)
58471 /* 172064 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VPOPCNTW),
58472 /* 172069 */ GIR_RootConstrainSelectedInstOperands,
58473 /* 172070 */ // GIR_Coverage, 485,
58474 /* 172070 */ GIR_Done,
58475 /* 172071 */ // Label 2748: @172071
58476 /* 172071 */ GIM_Reject,
58477 /* 172072 */ // Label 2742: @172072
58478 /* 172072 */ GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(172094), // Rule ID 484 //
58479 /* 172077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
58480 /* 172080 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
58481 /* 172083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58482 /* 172087 */ // (ctpop:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) => (VPOPCNTH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB)
58483 /* 172087 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VPOPCNTH),
58484 /* 172092 */ GIR_RootConstrainSelectedInstOperands,
58485 /* 172093 */ // GIR_Coverage, 484,
58486 /* 172093 */ GIR_Done,
58487 /* 172094 */ // Label 2749: @172094
58488 /* 172094 */ GIM_Reject,
58489 /* 172095 */ // Label 2743: @172095
58490 /* 172095 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(172117), // Rule ID 483 //
58491 /* 172100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec),
58492 /* 172103 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
58493 /* 172106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58494 /* 172110 */ // (ctpop:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) => (VPOPCNTB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB)
58495 /* 172110 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VPOPCNTB),
58496 /* 172115 */ GIR_RootConstrainSelectedInstOperands,
58497 /* 172116 */ // GIR_Coverage, 483,
58498 /* 172116 */ GIR_Done,
58499 /* 172117 */ // Label 2750: @172117
58500 /* 172117 */ GIM_Reject,
58501 /* 172118 */ // Label 2744: @172118
58502 /* 172118 */ GIM_Reject,
58503 /* 172119 */ // Label 69: @172119
58504 /* 172119 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 2757*/ GIMT_Encode4(172382),
58505 /* 172130 */ /*GILLT_s32*//*Label 2751*/ GIMT_Encode4(172154),
58506 /* 172134 */ /*GILLT_s64*//*Label 2752*/ GIMT_Encode4(172177),
58507 /* 172138 */ /*GILLT_s128*//*Label 2753*/ GIMT_Encode4(172200),
58508 /* 172142 */ /*GILLT_v2s64*//*Label 2754*/ GIMT_Encode4(172268),
58509 /* 172146 */ /*GILLT_v4s32*//*Label 2755*/ GIMT_Encode4(172291),
58510 /* 172150 */ /*GILLT_v8s16*//*Label 2756*/ GIMT_Encode4(172314),
58511 /* 172154 */ // Label 2751: @172154
58512 /* 172154 */ GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(172176), // Rule ID 1141 //
58513 /* 172159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
58514 /* 172162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
58515 /* 172165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
58516 /* 172169 */ // (bswap:{ *:[i32] } i32:{ *:[i32] }:$RST) => (BRW:{ *:[i32] } i32:{ *:[i32] }:$RST)
58517 /* 172169 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::BRW),
58518 /* 172174 */ GIR_RootConstrainSelectedInstOperands,
58519 /* 172175 */ // GIR_Coverage, 1141,
58520 /* 172175 */ GIR_Done,
58521 /* 172176 */ // Label 2758: @172176
58522 /* 172176 */ GIM_Reject,
58523 /* 172177 */ // Label 2752: @172177
58524 /* 172177 */ GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(172199), // Rule ID 1142 //
58525 /* 172182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1),
58526 /* 172185 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
58527 /* 172188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
58528 /* 172192 */ // (bswap:{ *:[i64] } i64:{ *:[i64] }:$RST) => (BRD:{ *:[i64] } i64:{ *:[i64] }:$RST)
58529 /* 172192 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::BRD),
58530 /* 172197 */ GIR_RootConstrainSelectedInstOperands,
58531 /* 172198 */ // GIR_Coverage, 1142,
58532 /* 172198 */ GIR_Done,
58533 /* 172199 */ // Label 2759: @172199
58534 /* 172199 */ GIM_Reject,
58535 /* 172200 */ // Label 2753: @172200
58536 /* 172200 */ GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(172267), // Rule ID 2176 //
58537 /* 172205 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
58538 /* 172208 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
58539 /* 172211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58540 /* 172215 */ // (bswap:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$A) => (COPY_TO_REGCLASS:{ *:[v1i128] } (XXBRQ:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$A, VSRC:{ *:[i32] })), VRRC:{ *:[i32] })
58541 /* 172215 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
58542 /* 172218 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
58543 /* 172222 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58544 /* 172227 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
58545 /* 172231 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
58546 /* 172236 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
58547 /* 172239 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBRQ),
58548 /* 172243 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58549 /* 172248 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
58550 /* 172251 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58551 /* 172253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
58552 /* 172256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
58553 /* 172258 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58554 /* 172261 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
58555 /* 172266 */ // GIR_Coverage, 2176,
58556 /* 172266 */ GIR_EraseRootFromParent_Done,
58557 /* 172267 */ // Label 2760: @172267
58558 /* 172267 */ GIM_Reject,
58559 /* 172268 */ // Label 2754: @172268
58560 /* 172268 */ GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(172290), // Rule ID 1038 //
58561 /* 172273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
58562 /* 172276 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
58563 /* 172279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
58564 /* 172283 */ // (bswap:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XB) => (XXBRD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XB)
58565 /* 172283 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXBRD),
58566 /* 172288 */ GIR_RootConstrainSelectedInstOperands,
58567 /* 172289 */ // GIR_Coverage, 1038,
58568 /* 172289 */ GIR_Done,
58569 /* 172290 */ // Label 2761: @172290
58570 /* 172290 */ GIM_Reject,
58571 /* 172291 */ // Label 2755: @172291
58572 /* 172291 */ GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(172313), // Rule ID 1037 //
58573 /* 172296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
58574 /* 172299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
58575 /* 172302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
58576 /* 172306 */ // (bswap:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB) => (XXBRW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB)
58577 /* 172306 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXBRW),
58578 /* 172311 */ GIR_RootConstrainSelectedInstOperands,
58579 /* 172312 */ // GIR_Coverage, 1037,
58580 /* 172312 */ GIR_Done,
58581 /* 172313 */ // Label 2762: @172313
58582 /* 172313 */ GIM_Reject,
58583 /* 172314 */ // Label 2756: @172314
58584 /* 172314 */ GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(172381), // Rule ID 2175 //
58585 /* 172319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
58586 /* 172322 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
58587 /* 172325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
58588 /* 172329 */ // (bswap:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXBRH:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] })), VRRC:{ *:[i32] })
58589 /* 172329 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
58590 /* 172332 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
58591 /* 172336 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58592 /* 172341 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A
58593 /* 172345 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID),
58594 /* 172350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
58595 /* 172353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBRH),
58596 /* 172357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58597 /* 172362 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
58598 /* 172365 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
58599 /* 172367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
58600 /* 172370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
58601 /* 172372 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
58602 /* 172375 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID),
58603 /* 172380 */ // GIR_Coverage, 2175,
58604 /* 172380 */ GIR_EraseRootFromParent_Done,
58605 /* 172381 */ // Label 2763: @172381
58606 /* 172381 */ GIM_Reject,
58607 /* 172382 */ // Label 2757: @172382
58608 /* 172382 */ GIM_Reject,
58609 /* 172383 */ // Label 70: @172383
58610 /* 172383 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2766*/ GIMT_Encode4(208388),
58611 /* 172394 */ /*GILLT_s32*//*Label 2764*/ GIMT_Encode4(172402),
58612 /* 172398 */ /*GILLT_s64*//*Label 2765*/ GIMT_Encode4(182697),
58613 /* 172402 */ // Label 2764: @172402
58614 /* 172402 */ GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(182696),
58615 /* 172407 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
58616 /* 172410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
58617 /* 172414 */ GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(177570), // Rule ID 4889 //
58618 /* 172419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode),
58619 /* 172422 */ // (bitreverse:{ *:[i32] } i32:{ *:[i32] }:$A) => (RLDICL_32:{ *:[i32] } (RLWIMI:{ *:[i32] } (RLWIMI:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 24:{ *:[i32] }, 0:{ *:[i32] }, 31:{ *:[i32] }), (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 8:{ *:[i32] }, 8:{ *:[i32] }, 15:{ *:[i32] }), (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 8:{ *:[i32] }, 24:{ *:[i32] }, 31:{ *:[i32] }), 0:{ *:[i32] }, 32:{ *:[i32] })
58620 /* 172422 */ GIR_MakeTempReg, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, /*TypeID*/GILLT_s32,
58621 /* 172426 */ GIR_BuildMI, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58622 /* 172431 */ GIR_AddTempRegister, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58623 /* 172438 */ GIR_AddImm, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
58624 /* 172449 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 192(*/0xC0, 0x01/*)*/,
58625 /* 172452 */ GIR_MakeTempReg, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TypeID*/GILLT_s32,
58626 /* 172456 */ GIR_BuildMI, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58627 /* 172461 */ GIR_AddTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58628 /* 172468 */ GIR_AddSimpleTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/,
58629 /* 172473 */ GIR_AddImm, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
58630 /* 172484 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 191(*/0xBF, 0x01/*)*/,
58631 /* 172487 */ GIR_MakeTempReg, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TypeID*/GILLT_s32,
58632 /* 172491 */ GIR_BuildMI, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58633 /* 172496 */ GIR_AddTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58634 /* 172503 */ GIR_AddImm, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
58635 /* 172514 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 190(*/0xBE, 0x01/*)*/,
58636 /* 172517 */ GIR_MakeTempReg, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TypeID*/GILLT_s32,
58637 /* 172521 */ GIR_BuildMI, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58638 /* 172526 */ GIR_AddTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58639 /* 172533 */ GIR_AddSimpleTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/,
58640 /* 172538 */ GIR_AddImm, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
58641 /* 172549 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 189(*/0xBD, 0x01/*)*/,
58642 /* 172552 */ GIR_MakeTempReg, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TypeID*/GILLT_s32,
58643 /* 172556 */ GIR_BuildMI, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58644 /* 172561 */ GIR_AddTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58645 /* 172568 */ GIR_AddImm, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
58646 /* 172579 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 188(*/0xBC, 0x01/*)*/,
58647 /* 172582 */ GIR_MakeTempReg, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TypeID*/GILLT_s32,
58648 /* 172586 */ GIR_BuildMI, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58649 /* 172591 */ GIR_AddTempRegister, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58650 /* 172598 */ GIR_AddSimpleTempRegister, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/,
58651 /* 172603 */ GIR_AddImm, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
58652 /* 172614 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 187(*/0xBB, 0x01/*)*/,
58653 /* 172617 */ GIR_MakeTempReg, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TypeID*/GILLT_s32,
58654 /* 172621 */ GIR_BuildMI, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58655 /* 172626 */ GIR_AddTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58656 /* 172633 */ GIR_Copy, /*NewInsnID*//* 186(*/0xBA, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
58657 /* 172638 */ GIR_AddImm8, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Imm*/1,
58658 /* 172642 */ GIR_AddImm8, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Imm*/0,
58659 /* 172646 */ GIR_AddImm8, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Imm*/30,
58660 /* 172650 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 186(*/0xBA, 0x01/*)*/,
58661 /* 172653 */ GIR_MakeTempReg, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TypeID*/GILLT_s32,
58662 /* 172657 */ GIR_BuildMI, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58663 /* 172662 */ GIR_AddTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58664 /* 172669 */ GIR_AddSimpleTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/,
58665 /* 172674 */ GIR_AddSimpleTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/,
58666 /* 172679 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 185(*/0xB9, 0x01/*)*/,
58667 /* 172682 */ GIR_MakeTempReg, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TypeID*/GILLT_s32,
58668 /* 172686 */ GIR_BuildMI, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58669 /* 172691 */ GIR_AddTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58670 /* 172698 */ GIR_AddImm, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
58671 /* 172709 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 184(*/0xB8, 0x01/*)*/,
58672 /* 172712 */ GIR_MakeTempReg, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TypeID*/GILLT_s32,
58673 /* 172716 */ GIR_BuildMI, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58674 /* 172721 */ GIR_AddTempRegister, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58675 /* 172728 */ GIR_AddSimpleTempRegister, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/,
58676 /* 172733 */ GIR_AddImm, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
58677 /* 172744 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 183(*/0xB7, 0x01/*)*/,
58678 /* 172747 */ GIR_MakeTempReg, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TypeID*/GILLT_s32,
58679 /* 172751 */ GIR_BuildMI, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58680 /* 172756 */ GIR_AddTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58681 /* 172763 */ GIR_Copy, /*NewInsnID*//* 182(*/0xB6, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
58682 /* 172768 */ GIR_AddImm8, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/31,
58683 /* 172772 */ GIR_AddImm8, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/1,
58684 /* 172776 */ GIR_AddImm8, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/31,
58685 /* 172780 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 182(*/0xB6, 0x01/*)*/,
58686 /* 172783 */ GIR_MakeTempReg, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TypeID*/GILLT_s32,
58687 /* 172787 */ GIR_BuildMI, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58688 /* 172792 */ GIR_AddTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58689 /* 172799 */ GIR_AddSimpleTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/,
58690 /* 172804 */ GIR_AddSimpleTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/,
58691 /* 172809 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 181(*/0xB5, 0x01/*)*/,
58692 /* 172812 */ GIR_MakeTempReg, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TypeID*/GILLT_s32,
58693 /* 172816 */ GIR_BuildMI, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
58694 /* 172821 */ GIR_AddTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58695 /* 172828 */ GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/,
58696 /* 172833 */ GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/,
58697 /* 172838 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 180(*/0xB4, 0x01/*)*/,
58698 /* 172841 */ GIR_MakeTempReg, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TypeID*/GILLT_s32,
58699 /* 172845 */ GIR_BuildMI, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58700 /* 172850 */ GIR_AddTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58701 /* 172857 */ GIR_AddSimpleTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/,
58702 /* 172862 */ GIR_AddImm8, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Imm*/2,
58703 /* 172866 */ GIR_AddImm8, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Imm*/0,
58704 /* 172870 */ GIR_AddImm8, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Imm*/29,
58705 /* 172874 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 179(*/0xB3, 0x01/*)*/,
58706 /* 172877 */ GIR_MakeTempReg, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TypeID*/GILLT_s32,
58707 /* 172881 */ GIR_BuildMI, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58708 /* 172886 */ GIR_AddTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58709 /* 172893 */ GIR_AddSimpleTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/,
58710 /* 172898 */ GIR_AddSimpleTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/,
58711 /* 172903 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 178(*/0xB2, 0x01/*)*/,
58712 /* 172906 */ GIR_MakeTempReg, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TypeID*/GILLT_s32,
58713 /* 172910 */ GIR_BuildMI, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58714 /* 172915 */ GIR_AddTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58715 /* 172922 */ GIR_AddImm, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
58716 /* 172933 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 177(*/0xB1, 0x01/*)*/,
58717 /* 172936 */ GIR_MakeTempReg, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TypeID*/GILLT_s32,
58718 /* 172940 */ GIR_BuildMI, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58719 /* 172945 */ GIR_AddTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58720 /* 172952 */ GIR_AddSimpleTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/,
58721 /* 172957 */ GIR_AddImm, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
58722 /* 172968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 176(*/0xB0, 0x01/*)*/,
58723 /* 172971 */ GIR_MakeTempReg, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TypeID*/GILLT_s32,
58724 /* 172975 */ GIR_BuildMI, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58725 /* 172980 */ GIR_AddTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58726 /* 172987 */ GIR_AddImm, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
58727 /* 172998 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 175(*/0xAF, 0x01/*)*/,
58728 /* 173001 */ GIR_MakeTempReg, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TypeID*/GILLT_s32,
58729 /* 173005 */ GIR_BuildMI, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58730 /* 173010 */ GIR_AddTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58731 /* 173017 */ GIR_AddSimpleTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/,
58732 /* 173022 */ GIR_AddImm, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
58733 /* 173033 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 174(*/0xAE, 0x01/*)*/,
58734 /* 173036 */ GIR_MakeTempReg, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TypeID*/GILLT_s32,
58735 /* 173040 */ GIR_BuildMI, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58736 /* 173045 */ GIR_AddTempRegister, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58737 /* 173052 */ GIR_Copy, /*NewInsnID*//* 173(*/0xAD, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
58738 /* 173057 */ GIR_AddImm8, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/1,
58739 /* 173061 */ GIR_AddImm8, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/0,
58740 /* 173065 */ GIR_AddImm8, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/30,
58741 /* 173069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 173(*/0xAD, 0x01/*)*/,
58742 /* 173072 */ GIR_MakeTempReg, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TypeID*/GILLT_s32,
58743 /* 173076 */ GIR_BuildMI, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58744 /* 173081 */ GIR_AddTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58745 /* 173088 */ GIR_AddSimpleTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/,
58746 /* 173093 */ GIR_AddSimpleTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/,
58747 /* 173098 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 172(*/0xAC, 0x01/*)*/,
58748 /* 173101 */ GIR_MakeTempReg, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TypeID*/GILLT_s32,
58749 /* 173105 */ GIR_BuildMI, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58750 /* 173110 */ GIR_AddTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58751 /* 173117 */ GIR_AddImm, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
58752 /* 173128 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 171(*/0xAB, 0x01/*)*/,
58753 /* 173131 */ GIR_MakeTempReg, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TypeID*/GILLT_s32,
58754 /* 173135 */ GIR_BuildMI, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58755 /* 173140 */ GIR_AddTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58756 /* 173147 */ GIR_AddSimpleTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/,
58757 /* 173152 */ GIR_AddImm, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
58758 /* 173163 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 170(*/0xAA, 0x01/*)*/,
58759 /* 173166 */ GIR_MakeTempReg, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TypeID*/GILLT_s32,
58760 /* 173170 */ GIR_BuildMI, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58761 /* 173175 */ GIR_AddTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58762 /* 173182 */ GIR_Copy, /*NewInsnID*//* 169(*/0xA9, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
58763 /* 173187 */ GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/31,
58764 /* 173191 */ GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/1,
58765 /* 173195 */ GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/31,
58766 /* 173199 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 169(*/0xA9, 0x01/*)*/,
58767 /* 173202 */ GIR_MakeTempReg, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TypeID*/GILLT_s32,
58768 /* 173206 */ GIR_BuildMI, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58769 /* 173211 */ GIR_AddTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58770 /* 173218 */ GIR_AddSimpleTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/,
58771 /* 173223 */ GIR_AddSimpleTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/,
58772 /* 173228 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 168(*/0xA8, 0x01/*)*/,
58773 /* 173231 */ GIR_MakeTempReg, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TypeID*/GILLT_s32,
58774 /* 173235 */ GIR_BuildMI, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
58775 /* 173240 */ GIR_AddTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58776 /* 173247 */ GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/,
58777 /* 173252 */ GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/,
58778 /* 173257 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 167(*/0xA7, 0x01/*)*/,
58779 /* 173260 */ GIR_MakeTempReg, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TypeID*/GILLT_s32,
58780 /* 173264 */ GIR_BuildMI, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58781 /* 173269 */ GIR_AddTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58782 /* 173276 */ GIR_AddSimpleTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/,
58783 /* 173281 */ GIR_AddImm8, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Imm*/30,
58784 /* 173285 */ GIR_AddImm8, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Imm*/2,
58785 /* 173289 */ GIR_AddImm8, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Imm*/31,
58786 /* 173293 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 166(*/0xA6, 0x01/*)*/,
58787 /* 173296 */ GIR_MakeTempReg, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TypeID*/GILLT_s32,
58788 /* 173300 */ GIR_BuildMI, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58789 /* 173305 */ GIR_AddTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58790 /* 173312 */ GIR_AddSimpleTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/,
58791 /* 173317 */ GIR_AddSimpleTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/,
58792 /* 173322 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 165(*/0xA5, 0x01/*)*/,
58793 /* 173325 */ GIR_MakeTempReg, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TypeID*/GILLT_s32,
58794 /* 173329 */ GIR_BuildMI, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
58795 /* 173334 */ GIR_AddTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58796 /* 173341 */ GIR_AddSimpleTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/,
58797 /* 173346 */ GIR_AddSimpleTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/,
58798 /* 173351 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 164(*/0xA4, 0x01/*)*/,
58799 /* 173354 */ GIR_MakeTempReg, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TypeID*/GILLT_s32,
58800 /* 173358 */ GIR_BuildMI, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58801 /* 173363 */ GIR_AddTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58802 /* 173370 */ GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/,
58803 /* 173375 */ GIR_AddImm8, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Imm*/4,
58804 /* 173379 */ GIR_AddImm8, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Imm*/0,
58805 /* 173383 */ GIR_AddImm8, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Imm*/27,
58806 /* 173387 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 163(*/0xA3, 0x01/*)*/,
58807 /* 173390 */ GIR_MakeTempReg, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TypeID*/GILLT_s32,
58808 /* 173394 */ GIR_BuildMI, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58809 /* 173399 */ GIR_AddTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58810 /* 173406 */ GIR_AddSimpleTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/,
58811 /* 173411 */ GIR_AddSimpleTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/,
58812 /* 173416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 162(*/0xA2, 0x01/*)*/,
58813 /* 173419 */ GIR_MakeTempReg, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TypeID*/GILLT_s32,
58814 /* 173423 */ GIR_BuildMI, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58815 /* 173428 */ GIR_AddTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58816 /* 173435 */ GIR_AddImm, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855),
58817 /* 173446 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 161(*/0xA1, 0x01/*)*/,
58818 /* 173449 */ GIR_MakeTempReg, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TypeID*/GILLT_s32,
58819 /* 173453 */ GIR_BuildMI, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58820 /* 173458 */ GIR_AddTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58821 /* 173465 */ GIR_AddSimpleTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/,
58822 /* 173470 */ GIR_AddImm, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855),
58823 /* 173481 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 160(*/0xA0, 0x01/*)*/,
58824 /* 173484 */ GIR_MakeTempReg, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TypeID*/GILLT_s32,
58825 /* 173488 */ GIR_BuildMI, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58826 /* 173493 */ GIR_AddTempRegister, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58827 /* 173500 */ GIR_AddImm, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
58828 /* 173511 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 159(*/0x9F, 0x01/*)*/,
58829 /* 173514 */ GIR_MakeTempReg, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TypeID*/GILLT_s32,
58830 /* 173518 */ GIR_BuildMI, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58831 /* 173523 */ GIR_AddTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58832 /* 173530 */ GIR_AddSimpleTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/,
58833 /* 173535 */ GIR_AddImm, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
58834 /* 173546 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 158(*/0x9E, 0x01/*)*/,
58835 /* 173549 */ GIR_MakeTempReg, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TypeID*/GILLT_s32,
58836 /* 173553 */ GIR_BuildMI, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58837 /* 173558 */ GIR_AddTempRegister, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58838 /* 173565 */ GIR_AddImm, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
58839 /* 173576 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 157(*/0x9D, 0x01/*)*/,
58840 /* 173579 */ GIR_MakeTempReg, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TypeID*/GILLT_s32,
58841 /* 173583 */ GIR_BuildMI, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58842 /* 173588 */ GIR_AddTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58843 /* 173595 */ GIR_AddSimpleTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/,
58844 /* 173600 */ GIR_AddImm, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
58845 /* 173611 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 156(*/0x9C, 0x01/*)*/,
58846 /* 173614 */ GIR_MakeTempReg, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TypeID*/GILLT_s32,
58847 /* 173618 */ GIR_BuildMI, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58848 /* 173623 */ GIR_AddTempRegister, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58849 /* 173630 */ GIR_Copy, /*NewInsnID*//* 155(*/0x9B, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
58850 /* 173635 */ GIR_AddImm8, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Imm*/1,
58851 /* 173639 */ GIR_AddImm8, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Imm*/0,
58852 /* 173643 */ GIR_AddImm8, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Imm*/30,
58853 /* 173647 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 155(*/0x9B, 0x01/*)*/,
58854 /* 173650 */ GIR_MakeTempReg, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TypeID*/GILLT_s32,
58855 /* 173654 */ GIR_BuildMI, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58856 /* 173659 */ GIR_AddTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58857 /* 173666 */ GIR_AddSimpleTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/,
58858 /* 173671 */ GIR_AddSimpleTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/,
58859 /* 173676 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 154(*/0x9A, 0x01/*)*/,
58860 /* 173679 */ GIR_MakeTempReg, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TypeID*/GILLT_s32,
58861 /* 173683 */ GIR_BuildMI, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58862 /* 173688 */ GIR_AddTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58863 /* 173695 */ GIR_AddImm, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
58864 /* 173706 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 153(*/0x99, 0x01/*)*/,
58865 /* 173709 */ GIR_MakeTempReg, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TypeID*/GILLT_s32,
58866 /* 173713 */ GIR_BuildMI, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58867 /* 173718 */ GIR_AddTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58868 /* 173725 */ GIR_AddSimpleTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/,
58869 /* 173730 */ GIR_AddImm, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
58870 /* 173741 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 152(*/0x98, 0x01/*)*/,
58871 /* 173744 */ GIR_MakeTempReg, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TypeID*/GILLT_s32,
58872 /* 173748 */ GIR_BuildMI, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58873 /* 173753 */ GIR_AddTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58874 /* 173760 */ GIR_Copy, /*NewInsnID*//* 151(*/0x97, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
58875 /* 173765 */ GIR_AddImm8, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/31,
58876 /* 173769 */ GIR_AddImm8, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/1,
58877 /* 173773 */ GIR_AddImm8, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/31,
58878 /* 173777 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 151(*/0x97, 0x01/*)*/,
58879 /* 173780 */ GIR_MakeTempReg, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TypeID*/GILLT_s32,
58880 /* 173784 */ GIR_BuildMI, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58881 /* 173789 */ GIR_AddTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58882 /* 173796 */ GIR_AddSimpleTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/,
58883 /* 173801 */ GIR_AddSimpleTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/,
58884 /* 173806 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 150(*/0x96, 0x01/*)*/,
58885 /* 173809 */ GIR_MakeTempReg, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TypeID*/GILLT_s32,
58886 /* 173813 */ GIR_BuildMI, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
58887 /* 173818 */ GIR_AddTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58888 /* 173825 */ GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/,
58889 /* 173830 */ GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/,
58890 /* 173835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 149(*/0x95, 0x01/*)*/,
58891 /* 173838 */ GIR_MakeTempReg, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TypeID*/GILLT_s32,
58892 /* 173842 */ GIR_BuildMI, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58893 /* 173847 */ GIR_AddTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58894 /* 173854 */ GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/,
58895 /* 173859 */ GIR_AddImm8, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Imm*/2,
58896 /* 173863 */ GIR_AddImm8, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Imm*/0,
58897 /* 173867 */ GIR_AddImm8, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Imm*/29,
58898 /* 173871 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 148(*/0x94, 0x01/*)*/,
58899 /* 173874 */ GIR_MakeTempReg, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TypeID*/GILLT_s32,
58900 /* 173878 */ GIR_BuildMI, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58901 /* 173883 */ GIR_AddTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58902 /* 173890 */ GIR_AddSimpleTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/,
58903 /* 173895 */ GIR_AddSimpleTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/,
58904 /* 173900 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 147(*/0x93, 0x01/*)*/,
58905 /* 173903 */ GIR_MakeTempReg, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TypeID*/GILLT_s32,
58906 /* 173907 */ GIR_BuildMI, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58907 /* 173912 */ GIR_AddTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58908 /* 173919 */ GIR_AddImm, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
58909 /* 173930 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 146(*/0x92, 0x01/*)*/,
58910 /* 173933 */ GIR_MakeTempReg, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TypeID*/GILLT_s32,
58911 /* 173937 */ GIR_BuildMI, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58912 /* 173942 */ GIR_AddTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58913 /* 173949 */ GIR_AddSimpleTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/,
58914 /* 173954 */ GIR_AddImm, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
58915 /* 173965 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 145(*/0x91, 0x01/*)*/,
58916 /* 173968 */ GIR_MakeTempReg, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TypeID*/GILLT_s32,
58917 /* 173972 */ GIR_BuildMI, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58918 /* 173977 */ GIR_AddTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58919 /* 173984 */ GIR_AddImm, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
58920 /* 173995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 144(*/0x90, 0x01/*)*/,
58921 /* 173998 */ GIR_MakeTempReg, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TypeID*/GILLT_s32,
58922 /* 174002 */ GIR_BuildMI, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58923 /* 174007 */ GIR_AddTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58924 /* 174014 */ GIR_AddSimpleTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/,
58925 /* 174019 */ GIR_AddImm, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
58926 /* 174030 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 143(*/0x8F, 0x01/*)*/,
58927 /* 174033 */ GIR_MakeTempReg, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TypeID*/GILLT_s32,
58928 /* 174037 */ GIR_BuildMI, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58929 /* 174042 */ GIR_AddTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58930 /* 174049 */ GIR_Copy, /*NewInsnID*//* 142(*/0x8E, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
58931 /* 174054 */ GIR_AddImm8, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Imm*/1,
58932 /* 174058 */ GIR_AddImm8, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Imm*/0,
58933 /* 174062 */ GIR_AddImm8, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Imm*/30,
58934 /* 174066 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 142(*/0x8E, 0x01/*)*/,
58935 /* 174069 */ GIR_MakeTempReg, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TypeID*/GILLT_s32,
58936 /* 174073 */ GIR_BuildMI, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58937 /* 174078 */ GIR_AddTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58938 /* 174085 */ GIR_AddSimpleTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/,
58939 /* 174090 */ GIR_AddSimpleTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/,
58940 /* 174095 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 141(*/0x8D, 0x01/*)*/,
58941 /* 174098 */ GIR_MakeTempReg, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TypeID*/GILLT_s32,
58942 /* 174102 */ GIR_BuildMI, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
58943 /* 174107 */ GIR_AddTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58944 /* 174114 */ GIR_AddImm, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
58945 /* 174125 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 140(*/0x8C, 0x01/*)*/,
58946 /* 174128 */ GIR_MakeTempReg, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TypeID*/GILLT_s32,
58947 /* 174132 */ GIR_BuildMI, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
58948 /* 174137 */ GIR_AddTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58949 /* 174144 */ GIR_AddSimpleTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/,
58950 /* 174149 */ GIR_AddImm, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
58951 /* 174160 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 139(*/0x8B, 0x01/*)*/,
58952 /* 174163 */ GIR_MakeTempReg, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TypeID*/GILLT_s32,
58953 /* 174167 */ GIR_BuildMI, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58954 /* 174172 */ GIR_AddTempRegister, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58955 /* 174179 */ GIR_Copy, /*NewInsnID*//* 138(*/0x8A, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
58956 /* 174184 */ GIR_AddImm8, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Imm*/31,
58957 /* 174188 */ GIR_AddImm8, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Imm*/1,
58958 /* 174192 */ GIR_AddImm8, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Imm*/31,
58959 /* 174196 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 138(*/0x8A, 0x01/*)*/,
58960 /* 174199 */ GIR_MakeTempReg, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TypeID*/GILLT_s32,
58961 /* 174203 */ GIR_BuildMI, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58962 /* 174208 */ GIR_AddTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58963 /* 174215 */ GIR_AddSimpleTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/,
58964 /* 174220 */ GIR_AddSimpleTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/,
58965 /* 174225 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 137(*/0x89, 0x01/*)*/,
58966 /* 174228 */ GIR_MakeTempReg, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TypeID*/GILLT_s32,
58967 /* 174232 */ GIR_BuildMI, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
58968 /* 174237 */ GIR_AddTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58969 /* 174244 */ GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/,
58970 /* 174249 */ GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/,
58971 /* 174254 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 136(*/0x88, 0x01/*)*/,
58972 /* 174257 */ GIR_MakeTempReg, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TypeID*/GILLT_s32,
58973 /* 174261 */ GIR_BuildMI, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58974 /* 174266 */ GIR_AddTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58975 /* 174273 */ GIR_AddSimpleTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/,
58976 /* 174278 */ GIR_AddImm8, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Imm*/30,
58977 /* 174282 */ GIR_AddImm8, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Imm*/2,
58978 /* 174286 */ GIR_AddImm8, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Imm*/31,
58979 /* 174290 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 135(*/0x87, 0x01/*)*/,
58980 /* 174293 */ GIR_MakeTempReg, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TypeID*/GILLT_s32,
58981 /* 174297 */ GIR_BuildMI, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
58982 /* 174302 */ GIR_AddTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58983 /* 174309 */ GIR_AddSimpleTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/,
58984 /* 174314 */ GIR_AddSimpleTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/,
58985 /* 174319 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 134(*/0x86, 0x01/*)*/,
58986 /* 174322 */ GIR_MakeTempReg, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TypeID*/GILLT_s32,
58987 /* 174326 */ GIR_BuildMI, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
58988 /* 174331 */ GIR_AddTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58989 /* 174338 */ GIR_AddSimpleTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/,
58990 /* 174343 */ GIR_AddSimpleTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/,
58991 /* 174348 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 133(*/0x85, 0x01/*)*/,
58992 /* 174351 */ GIR_MakeTempReg, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TypeID*/GILLT_s32,
58993 /* 174355 */ GIR_BuildMI, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
58994 /* 174360 */ GIR_AddTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
58995 /* 174367 */ GIR_AddSimpleTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/,
58996 /* 174372 */ GIR_AddImm8, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Imm*/28,
58997 /* 174376 */ GIR_AddImm8, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Imm*/4,
58998 /* 174380 */ GIR_AddImm8, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Imm*/31,
58999 /* 174384 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 132(*/0x84, 0x01/*)*/,
59000 /* 174387 */ GIR_MakeTempReg, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TypeID*/GILLT_s32,
59001 /* 174391 */ GIR_BuildMI, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
59002 /* 174396 */ GIR_AddTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59003 /* 174403 */ GIR_AddSimpleTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/,
59004 /* 174408 */ GIR_AddSimpleTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/,
59005 /* 174413 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 131(*/0x83, 0x01/*)*/,
59006 /* 174416 */ GIR_MakeTempReg, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TypeID*/GILLT_s32,
59007 /* 174420 */ GIR_BuildMI, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
59008 /* 174425 */ GIR_AddTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59009 /* 174432 */ GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/,
59010 /* 174437 */ GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/,
59011 /* 174442 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 130(*/0x82, 0x01/*)*/,
59012 /* 174445 */ GIR_MakeTempReg, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TypeID*/GILLT_s32,
59013 /* 174449 */ GIR_BuildMI, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
59014 /* 174454 */ GIR_AddTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59015 /* 174461 */ GIR_AddImm, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
59016 /* 174472 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 129(*/0x81, 0x01/*)*/,
59017 /* 174475 */ GIR_MakeTempReg, /*TempRegID*/127, /*TypeID*/GILLT_s32,
59018 /* 174478 */ GIR_BuildMI, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
59019 /* 174483 */ GIR_AddTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*/127, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59020 /* 174489 */ GIR_AddSimpleTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/,
59021 /* 174494 */ GIR_AddImm, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
59022 /* 174505 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 128(*/0x80, 0x01/*)*/,
59023 /* 174508 */ GIR_MakeTempReg, /*TempRegID*/126, /*TypeID*/GILLT_s32,
59024 /* 174511 */ GIR_BuildMI, /*InsnID*/127, /*Opcode*/GIMT_Encode2(PPC::LIS),
59025 /* 174515 */ GIR_AddTempRegister, /*InsnID*/127, /*TempRegID*/126, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59026 /* 174520 */ GIR_AddImm, /*InsnID*/127, /*Imm*/GIMT_Encode8(52428),
59027 /* 174530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/127,
59028 /* 174532 */ GIR_MakeTempReg, /*TempRegID*/125, /*TypeID*/GILLT_s32,
59029 /* 174535 */ GIR_BuildMI, /*InsnID*/126, /*Opcode*/GIMT_Encode2(PPC::ORI),
59030 /* 174539 */ GIR_AddTempRegister, /*InsnID*/126, /*TempRegID*/125, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59031 /* 174544 */ GIR_AddSimpleTempRegister, /*InsnID*/126, /*TempRegID*/126,
59032 /* 174547 */ GIR_AddImm, /*InsnID*/126, /*Imm*/GIMT_Encode8(52428),
59033 /* 174557 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/126,
59034 /* 174559 */ GIR_MakeTempReg, /*TempRegID*/124, /*TypeID*/GILLT_s32,
59035 /* 174562 */ GIR_BuildMI, /*InsnID*/125, /*Opcode*/GIMT_Encode2(PPC::LIS),
59036 /* 174566 */ GIR_AddTempRegister, /*InsnID*/125, /*TempRegID*/124, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59037 /* 174571 */ GIR_AddImm, /*InsnID*/125, /*Imm*/GIMT_Encode8(43690),
59038 /* 174581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/125,
59039 /* 174583 */ GIR_MakeTempReg, /*TempRegID*/123, /*TypeID*/GILLT_s32,
59040 /* 174586 */ GIR_BuildMI, /*InsnID*/124, /*Opcode*/GIMT_Encode2(PPC::ORI),
59041 /* 174590 */ GIR_AddTempRegister, /*InsnID*/124, /*TempRegID*/123, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59042 /* 174595 */ GIR_AddSimpleTempRegister, /*InsnID*/124, /*TempRegID*/124,
59043 /* 174598 */ GIR_AddImm, /*InsnID*/124, /*Imm*/GIMT_Encode8(43690),
59044 /* 174608 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/124,
59045 /* 174610 */ GIR_MakeTempReg, /*TempRegID*/122, /*TypeID*/GILLT_s32,
59046 /* 174613 */ GIR_BuildMI, /*InsnID*/123, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59047 /* 174617 */ GIR_AddTempRegister, /*InsnID*/123, /*TempRegID*/122, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59048 /* 174622 */ GIR_Copy, /*NewInsnID*/123, /*OldInsnID*/0, /*OpIdx*/1, // A
59049 /* 174626 */ GIR_AddImm8, /*InsnID*/123, /*Imm*/1,
59050 /* 174629 */ GIR_AddImm8, /*InsnID*/123, /*Imm*/0,
59051 /* 174632 */ GIR_AddImm8, /*InsnID*/123, /*Imm*/30,
59052 /* 174635 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/123,
59053 /* 174637 */ GIR_MakeTempReg, /*TempRegID*/121, /*TypeID*/GILLT_s32,
59054 /* 174640 */ GIR_BuildMI, /*InsnID*/122, /*Opcode*/GIMT_Encode2(PPC::AND),
59055 /* 174644 */ GIR_AddTempRegister, /*InsnID*/122, /*TempRegID*/121, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59056 /* 174649 */ GIR_AddSimpleTempRegister, /*InsnID*/122, /*TempRegID*/122,
59057 /* 174652 */ GIR_AddSimpleTempRegister, /*InsnID*/122, /*TempRegID*/123,
59058 /* 174655 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/122,
59059 /* 174657 */ GIR_MakeTempReg, /*TempRegID*/120, /*TypeID*/GILLT_s32,
59060 /* 174660 */ GIR_BuildMI, /*InsnID*/121, /*Opcode*/GIMT_Encode2(PPC::LIS),
59061 /* 174664 */ GIR_AddTempRegister, /*InsnID*/121, /*TempRegID*/120, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59062 /* 174669 */ GIR_AddImm, /*InsnID*/121, /*Imm*/GIMT_Encode8(21845),
59063 /* 174679 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/121,
59064 /* 174681 */ GIR_MakeTempReg, /*TempRegID*/119, /*TypeID*/GILLT_s32,
59065 /* 174684 */ GIR_BuildMI, /*InsnID*/120, /*Opcode*/GIMT_Encode2(PPC::ORI),
59066 /* 174688 */ GIR_AddTempRegister, /*InsnID*/120, /*TempRegID*/119, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59067 /* 174693 */ GIR_AddSimpleTempRegister, /*InsnID*/120, /*TempRegID*/120,
59068 /* 174696 */ GIR_AddImm, /*InsnID*/120, /*Imm*/GIMT_Encode8(21845),
59069 /* 174706 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/120,
59070 /* 174708 */ GIR_MakeTempReg, /*TempRegID*/118, /*TypeID*/GILLT_s32,
59071 /* 174711 */ GIR_BuildMI, /*InsnID*/119, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59072 /* 174715 */ GIR_AddTempRegister, /*InsnID*/119, /*TempRegID*/118, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59073 /* 174720 */ GIR_Copy, /*NewInsnID*/119, /*OldInsnID*/0, /*OpIdx*/1, // A
59074 /* 174724 */ GIR_AddImm8, /*InsnID*/119, /*Imm*/31,
59075 /* 174727 */ GIR_AddImm8, /*InsnID*/119, /*Imm*/1,
59076 /* 174730 */ GIR_AddImm8, /*InsnID*/119, /*Imm*/31,
59077 /* 174733 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/119,
59078 /* 174735 */ GIR_MakeTempReg, /*TempRegID*/117, /*TypeID*/GILLT_s32,
59079 /* 174738 */ GIR_BuildMI, /*InsnID*/118, /*Opcode*/GIMT_Encode2(PPC::AND),
59080 /* 174742 */ GIR_AddTempRegister, /*InsnID*/118, /*TempRegID*/117, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59081 /* 174747 */ GIR_AddSimpleTempRegister, /*InsnID*/118, /*TempRegID*/118,
59082 /* 174750 */ GIR_AddSimpleTempRegister, /*InsnID*/118, /*TempRegID*/119,
59083 /* 174753 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/118,
59084 /* 174755 */ GIR_MakeTempReg, /*TempRegID*/116, /*TypeID*/GILLT_s32,
59085 /* 174758 */ GIR_BuildMI, /*InsnID*/117, /*Opcode*/GIMT_Encode2(PPC::OR),
59086 /* 174762 */ GIR_AddTempRegister, /*InsnID*/117, /*TempRegID*/116, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59087 /* 174767 */ GIR_AddSimpleTempRegister, /*InsnID*/117, /*TempRegID*/117,
59088 /* 174770 */ GIR_AddSimpleTempRegister, /*InsnID*/117, /*TempRegID*/121,
59089 /* 174773 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/117,
59090 /* 174775 */ GIR_MakeTempReg, /*TempRegID*/115, /*TypeID*/GILLT_s32,
59091 /* 174778 */ GIR_BuildMI, /*InsnID*/116, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59092 /* 174782 */ GIR_AddTempRegister, /*InsnID*/116, /*TempRegID*/115, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59093 /* 174787 */ GIR_AddSimpleTempRegister, /*InsnID*/116, /*TempRegID*/116,
59094 /* 174790 */ GIR_AddImm8, /*InsnID*/116, /*Imm*/2,
59095 /* 174793 */ GIR_AddImm8, /*InsnID*/116, /*Imm*/0,
59096 /* 174796 */ GIR_AddImm8, /*InsnID*/116, /*Imm*/29,
59097 /* 174799 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/116,
59098 /* 174801 */ GIR_MakeTempReg, /*TempRegID*/114, /*TypeID*/GILLT_s32,
59099 /* 174804 */ GIR_BuildMI, /*InsnID*/115, /*Opcode*/GIMT_Encode2(PPC::AND),
59100 /* 174808 */ GIR_AddTempRegister, /*InsnID*/115, /*TempRegID*/114, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59101 /* 174813 */ GIR_AddSimpleTempRegister, /*InsnID*/115, /*TempRegID*/115,
59102 /* 174816 */ GIR_AddSimpleTempRegister, /*InsnID*/115, /*TempRegID*/125,
59103 /* 174819 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/115,
59104 /* 174821 */ GIR_MakeTempReg, /*TempRegID*/113, /*TypeID*/GILLT_s32,
59105 /* 174824 */ GIR_BuildMI, /*InsnID*/114, /*Opcode*/GIMT_Encode2(PPC::LIS),
59106 /* 174828 */ GIR_AddTempRegister, /*InsnID*/114, /*TempRegID*/113, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59107 /* 174833 */ GIR_AddImm, /*InsnID*/114, /*Imm*/GIMT_Encode8(13107),
59108 /* 174843 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/114,
59109 /* 174845 */ GIR_MakeTempReg, /*TempRegID*/112, /*TypeID*/GILLT_s32,
59110 /* 174848 */ GIR_BuildMI, /*InsnID*/113, /*Opcode*/GIMT_Encode2(PPC::ORI),
59111 /* 174852 */ GIR_AddTempRegister, /*InsnID*/113, /*TempRegID*/112, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59112 /* 174857 */ GIR_AddSimpleTempRegister, /*InsnID*/113, /*TempRegID*/113,
59113 /* 174860 */ GIR_AddImm, /*InsnID*/113, /*Imm*/GIMT_Encode8(13107),
59114 /* 174870 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/113,
59115 /* 174872 */ GIR_MakeTempReg, /*TempRegID*/111, /*TypeID*/GILLT_s32,
59116 /* 174875 */ GIR_BuildMI, /*InsnID*/112, /*Opcode*/GIMT_Encode2(PPC::LIS),
59117 /* 174879 */ GIR_AddTempRegister, /*InsnID*/112, /*TempRegID*/111, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59118 /* 174884 */ GIR_AddImm, /*InsnID*/112, /*Imm*/GIMT_Encode8(43690),
59119 /* 174894 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/112,
59120 /* 174896 */ GIR_MakeTempReg, /*TempRegID*/110, /*TypeID*/GILLT_s32,
59121 /* 174899 */ GIR_BuildMI, /*InsnID*/111, /*Opcode*/GIMT_Encode2(PPC::ORI),
59122 /* 174903 */ GIR_AddTempRegister, /*InsnID*/111, /*TempRegID*/110, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59123 /* 174908 */ GIR_AddSimpleTempRegister, /*InsnID*/111, /*TempRegID*/111,
59124 /* 174911 */ GIR_AddImm, /*InsnID*/111, /*Imm*/GIMT_Encode8(43690),
59125 /* 174921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/111,
59126 /* 174923 */ GIR_MakeTempReg, /*TempRegID*/109, /*TypeID*/GILLT_s32,
59127 /* 174926 */ GIR_BuildMI, /*InsnID*/110, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59128 /* 174930 */ GIR_AddTempRegister, /*InsnID*/110, /*TempRegID*/109, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59129 /* 174935 */ GIR_Copy, /*NewInsnID*/110, /*OldInsnID*/0, /*OpIdx*/1, // A
59130 /* 174939 */ GIR_AddImm8, /*InsnID*/110, /*Imm*/1,
59131 /* 174942 */ GIR_AddImm8, /*InsnID*/110, /*Imm*/0,
59132 /* 174945 */ GIR_AddImm8, /*InsnID*/110, /*Imm*/30,
59133 /* 174948 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/110,
59134 /* 174950 */ GIR_MakeTempReg, /*TempRegID*/108, /*TypeID*/GILLT_s32,
59135 /* 174953 */ GIR_BuildMI, /*InsnID*/109, /*Opcode*/GIMT_Encode2(PPC::AND),
59136 /* 174957 */ GIR_AddTempRegister, /*InsnID*/109, /*TempRegID*/108, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59137 /* 174962 */ GIR_AddSimpleTempRegister, /*InsnID*/109, /*TempRegID*/109,
59138 /* 174965 */ GIR_AddSimpleTempRegister, /*InsnID*/109, /*TempRegID*/110,
59139 /* 174968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/109,
59140 /* 174970 */ GIR_MakeTempReg, /*TempRegID*/107, /*TypeID*/GILLT_s32,
59141 /* 174973 */ GIR_BuildMI, /*InsnID*/108, /*Opcode*/GIMT_Encode2(PPC::LIS),
59142 /* 174977 */ GIR_AddTempRegister, /*InsnID*/108, /*TempRegID*/107, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59143 /* 174982 */ GIR_AddImm, /*InsnID*/108, /*Imm*/GIMT_Encode8(21845),
59144 /* 174992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/108,
59145 /* 174994 */ GIR_MakeTempReg, /*TempRegID*/106, /*TypeID*/GILLT_s32,
59146 /* 174997 */ GIR_BuildMI, /*InsnID*/107, /*Opcode*/GIMT_Encode2(PPC::ORI),
59147 /* 175001 */ GIR_AddTempRegister, /*InsnID*/107, /*TempRegID*/106, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59148 /* 175006 */ GIR_AddSimpleTempRegister, /*InsnID*/107, /*TempRegID*/107,
59149 /* 175009 */ GIR_AddImm, /*InsnID*/107, /*Imm*/GIMT_Encode8(21845),
59150 /* 175019 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/107,
59151 /* 175021 */ GIR_MakeTempReg, /*TempRegID*/105, /*TypeID*/GILLT_s32,
59152 /* 175024 */ GIR_BuildMI, /*InsnID*/106, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59153 /* 175028 */ GIR_AddTempRegister, /*InsnID*/106, /*TempRegID*/105, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59154 /* 175033 */ GIR_Copy, /*NewInsnID*/106, /*OldInsnID*/0, /*OpIdx*/1, // A
59155 /* 175037 */ GIR_AddImm8, /*InsnID*/106, /*Imm*/31,
59156 /* 175040 */ GIR_AddImm8, /*InsnID*/106, /*Imm*/1,
59157 /* 175043 */ GIR_AddImm8, /*InsnID*/106, /*Imm*/31,
59158 /* 175046 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/106,
59159 /* 175048 */ GIR_MakeTempReg, /*TempRegID*/104, /*TypeID*/GILLT_s32,
59160 /* 175051 */ GIR_BuildMI, /*InsnID*/105, /*Opcode*/GIMT_Encode2(PPC::AND),
59161 /* 175055 */ GIR_AddTempRegister, /*InsnID*/105, /*TempRegID*/104, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59162 /* 175060 */ GIR_AddSimpleTempRegister, /*InsnID*/105, /*TempRegID*/105,
59163 /* 175063 */ GIR_AddSimpleTempRegister, /*InsnID*/105, /*TempRegID*/106,
59164 /* 175066 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/105,
59165 /* 175068 */ GIR_MakeTempReg, /*TempRegID*/103, /*TypeID*/GILLT_s32,
59166 /* 175071 */ GIR_BuildMI, /*InsnID*/104, /*Opcode*/GIMT_Encode2(PPC::OR),
59167 /* 175075 */ GIR_AddTempRegister, /*InsnID*/104, /*TempRegID*/103, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59168 /* 175080 */ GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/104,
59169 /* 175083 */ GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/108,
59170 /* 175086 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/104,
59171 /* 175088 */ GIR_MakeTempReg, /*TempRegID*/102, /*TypeID*/GILLT_s32,
59172 /* 175091 */ GIR_BuildMI, /*InsnID*/103, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59173 /* 175095 */ GIR_AddTempRegister, /*InsnID*/103, /*TempRegID*/102, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59174 /* 175100 */ GIR_AddSimpleTempRegister, /*InsnID*/103, /*TempRegID*/103,
59175 /* 175103 */ GIR_AddImm8, /*InsnID*/103, /*Imm*/30,
59176 /* 175106 */ GIR_AddImm8, /*InsnID*/103, /*Imm*/2,
59177 /* 175109 */ GIR_AddImm8, /*InsnID*/103, /*Imm*/31,
59178 /* 175112 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/103,
59179 /* 175114 */ GIR_MakeTempReg, /*TempRegID*/101, /*TypeID*/GILLT_s32,
59180 /* 175117 */ GIR_BuildMI, /*InsnID*/102, /*Opcode*/GIMT_Encode2(PPC::AND),
59181 /* 175121 */ GIR_AddTempRegister, /*InsnID*/102, /*TempRegID*/101, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59182 /* 175126 */ GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/102,
59183 /* 175129 */ GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/112,
59184 /* 175132 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/102,
59185 /* 175134 */ GIR_MakeTempReg, /*TempRegID*/100, /*TypeID*/GILLT_s32,
59186 /* 175137 */ GIR_BuildMI, /*InsnID*/101, /*Opcode*/GIMT_Encode2(PPC::OR),
59187 /* 175141 */ GIR_AddTempRegister, /*InsnID*/101, /*TempRegID*/100, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59188 /* 175146 */ GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/101,
59189 /* 175149 */ GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/114,
59190 /* 175152 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/101,
59191 /* 175154 */ GIR_MakeTempReg, /*TempRegID*/99, /*TypeID*/GILLT_s32,
59192 /* 175157 */ GIR_BuildMI, /*InsnID*/100, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59193 /* 175161 */ GIR_AddTempRegister, /*InsnID*/100, /*TempRegID*/99, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59194 /* 175166 */ GIR_AddSimpleTempRegister, /*InsnID*/100, /*TempRegID*/100,
59195 /* 175169 */ GIR_AddImm8, /*InsnID*/100, /*Imm*/4,
59196 /* 175172 */ GIR_AddImm8, /*InsnID*/100, /*Imm*/0,
59197 /* 175175 */ GIR_AddImm8, /*InsnID*/100, /*Imm*/27,
59198 /* 175178 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/100,
59199 /* 175180 */ GIR_MakeTempReg, /*TempRegID*/98, /*TypeID*/GILLT_s32,
59200 /* 175183 */ GIR_BuildMI, /*InsnID*/99, /*Opcode*/GIMT_Encode2(PPC::AND),
59201 /* 175187 */ GIR_AddTempRegister, /*InsnID*/99, /*TempRegID*/98, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59202 /* 175192 */ GIR_AddSimpleTempRegister, /*InsnID*/99, /*TempRegID*/99,
59203 /* 175195 */ GIR_AddSimpleTempRegister, /*InsnID*/99, /*TempRegID*/127,
59204 /* 175198 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/99,
59205 /* 175200 */ GIR_MakeTempReg, /*TempRegID*/97, /*TypeID*/GILLT_s32,
59206 /* 175203 */ GIR_BuildMI, /*InsnID*/98, /*Opcode*/GIMT_Encode2(PPC::LIS),
59207 /* 175207 */ GIR_AddTempRegister, /*InsnID*/98, /*TempRegID*/97, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59208 /* 175212 */ GIR_AddImm, /*InsnID*/98, /*Imm*/GIMT_Encode8(3855),
59209 /* 175222 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/98,
59210 /* 175224 */ GIR_MakeTempReg, /*TempRegID*/96, /*TypeID*/GILLT_s32,
59211 /* 175227 */ GIR_BuildMI, /*InsnID*/97, /*Opcode*/GIMT_Encode2(PPC::ORI),
59212 /* 175231 */ GIR_AddTempRegister, /*InsnID*/97, /*TempRegID*/96, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59213 /* 175236 */ GIR_AddSimpleTempRegister, /*InsnID*/97, /*TempRegID*/97,
59214 /* 175239 */ GIR_AddImm, /*InsnID*/97, /*Imm*/GIMT_Encode8(3855),
59215 /* 175249 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/97,
59216 /* 175251 */ GIR_MakeTempReg, /*TempRegID*/95, /*TypeID*/GILLT_s32,
59217 /* 175254 */ GIR_BuildMI, /*InsnID*/96, /*Opcode*/GIMT_Encode2(PPC::LIS),
59218 /* 175258 */ GIR_AddTempRegister, /*InsnID*/96, /*TempRegID*/95, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59219 /* 175263 */ GIR_AddImm, /*InsnID*/96, /*Imm*/GIMT_Encode8(52428),
59220 /* 175273 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/96,
59221 /* 175275 */ GIR_MakeTempReg, /*TempRegID*/94, /*TypeID*/GILLT_s32,
59222 /* 175278 */ GIR_BuildMI, /*InsnID*/95, /*Opcode*/GIMT_Encode2(PPC::ORI),
59223 /* 175282 */ GIR_AddTempRegister, /*InsnID*/95, /*TempRegID*/94, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59224 /* 175287 */ GIR_AddSimpleTempRegister, /*InsnID*/95, /*TempRegID*/95,
59225 /* 175290 */ GIR_AddImm, /*InsnID*/95, /*Imm*/GIMT_Encode8(52428),
59226 /* 175300 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/95,
59227 /* 175302 */ GIR_MakeTempReg, /*TempRegID*/93, /*TypeID*/GILLT_s32,
59228 /* 175305 */ GIR_BuildMI, /*InsnID*/94, /*Opcode*/GIMT_Encode2(PPC::LIS),
59229 /* 175309 */ GIR_AddTempRegister, /*InsnID*/94, /*TempRegID*/93, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59230 /* 175314 */ GIR_AddImm, /*InsnID*/94, /*Imm*/GIMT_Encode8(43690),
59231 /* 175324 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/94,
59232 /* 175326 */ GIR_MakeTempReg, /*TempRegID*/92, /*TypeID*/GILLT_s32,
59233 /* 175329 */ GIR_BuildMI, /*InsnID*/93, /*Opcode*/GIMT_Encode2(PPC::ORI),
59234 /* 175333 */ GIR_AddTempRegister, /*InsnID*/93, /*TempRegID*/92, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59235 /* 175338 */ GIR_AddSimpleTempRegister, /*InsnID*/93, /*TempRegID*/93,
59236 /* 175341 */ GIR_AddImm, /*InsnID*/93, /*Imm*/GIMT_Encode8(43690),
59237 /* 175351 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/93,
59238 /* 175353 */ GIR_MakeTempReg, /*TempRegID*/91, /*TypeID*/GILLT_s32,
59239 /* 175356 */ GIR_BuildMI, /*InsnID*/92, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59240 /* 175360 */ GIR_AddTempRegister, /*InsnID*/92, /*TempRegID*/91, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59241 /* 175365 */ GIR_Copy, /*NewInsnID*/92, /*OldInsnID*/0, /*OpIdx*/1, // A
59242 /* 175369 */ GIR_AddImm8, /*InsnID*/92, /*Imm*/1,
59243 /* 175372 */ GIR_AddImm8, /*InsnID*/92, /*Imm*/0,
59244 /* 175375 */ GIR_AddImm8, /*InsnID*/92, /*Imm*/30,
59245 /* 175378 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/92,
59246 /* 175380 */ GIR_MakeTempReg, /*TempRegID*/90, /*TypeID*/GILLT_s32,
59247 /* 175383 */ GIR_BuildMI, /*InsnID*/91, /*Opcode*/GIMT_Encode2(PPC::AND),
59248 /* 175387 */ GIR_AddTempRegister, /*InsnID*/91, /*TempRegID*/90, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59249 /* 175392 */ GIR_AddSimpleTempRegister, /*InsnID*/91, /*TempRegID*/91,
59250 /* 175395 */ GIR_AddSimpleTempRegister, /*InsnID*/91, /*TempRegID*/92,
59251 /* 175398 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/91,
59252 /* 175400 */ GIR_MakeTempReg, /*TempRegID*/89, /*TypeID*/GILLT_s32,
59253 /* 175403 */ GIR_BuildMI, /*InsnID*/90, /*Opcode*/GIMT_Encode2(PPC::LIS),
59254 /* 175407 */ GIR_AddTempRegister, /*InsnID*/90, /*TempRegID*/89, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59255 /* 175412 */ GIR_AddImm, /*InsnID*/90, /*Imm*/GIMT_Encode8(21845),
59256 /* 175422 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/90,
59257 /* 175424 */ GIR_MakeTempReg, /*TempRegID*/88, /*TypeID*/GILLT_s32,
59258 /* 175427 */ GIR_BuildMI, /*InsnID*/89, /*Opcode*/GIMT_Encode2(PPC::ORI),
59259 /* 175431 */ GIR_AddTempRegister, /*InsnID*/89, /*TempRegID*/88, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59260 /* 175436 */ GIR_AddSimpleTempRegister, /*InsnID*/89, /*TempRegID*/89,
59261 /* 175439 */ GIR_AddImm, /*InsnID*/89, /*Imm*/GIMT_Encode8(21845),
59262 /* 175449 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/89,
59263 /* 175451 */ GIR_MakeTempReg, /*TempRegID*/87, /*TypeID*/GILLT_s32,
59264 /* 175454 */ GIR_BuildMI, /*InsnID*/88, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59265 /* 175458 */ GIR_AddTempRegister, /*InsnID*/88, /*TempRegID*/87, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59266 /* 175463 */ GIR_Copy, /*NewInsnID*/88, /*OldInsnID*/0, /*OpIdx*/1, // A
59267 /* 175467 */ GIR_AddImm8, /*InsnID*/88, /*Imm*/31,
59268 /* 175470 */ GIR_AddImm8, /*InsnID*/88, /*Imm*/1,
59269 /* 175473 */ GIR_AddImm8, /*InsnID*/88, /*Imm*/31,
59270 /* 175476 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/88,
59271 /* 175478 */ GIR_MakeTempReg, /*TempRegID*/86, /*TypeID*/GILLT_s32,
59272 /* 175481 */ GIR_BuildMI, /*InsnID*/87, /*Opcode*/GIMT_Encode2(PPC::AND),
59273 /* 175485 */ GIR_AddTempRegister, /*InsnID*/87, /*TempRegID*/86, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59274 /* 175490 */ GIR_AddSimpleTempRegister, /*InsnID*/87, /*TempRegID*/87,
59275 /* 175493 */ GIR_AddSimpleTempRegister, /*InsnID*/87, /*TempRegID*/88,
59276 /* 175496 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/87,
59277 /* 175498 */ GIR_MakeTempReg, /*TempRegID*/85, /*TypeID*/GILLT_s32,
59278 /* 175501 */ GIR_BuildMI, /*InsnID*/86, /*Opcode*/GIMT_Encode2(PPC::OR),
59279 /* 175505 */ GIR_AddTempRegister, /*InsnID*/86, /*TempRegID*/85, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59280 /* 175510 */ GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/86,
59281 /* 175513 */ GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/90,
59282 /* 175516 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/86,
59283 /* 175518 */ GIR_MakeTempReg, /*TempRegID*/84, /*TypeID*/GILLT_s32,
59284 /* 175521 */ GIR_BuildMI, /*InsnID*/85, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59285 /* 175525 */ GIR_AddTempRegister, /*InsnID*/85, /*TempRegID*/84, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59286 /* 175530 */ GIR_AddSimpleTempRegister, /*InsnID*/85, /*TempRegID*/85,
59287 /* 175533 */ GIR_AddImm8, /*InsnID*/85, /*Imm*/2,
59288 /* 175536 */ GIR_AddImm8, /*InsnID*/85, /*Imm*/0,
59289 /* 175539 */ GIR_AddImm8, /*InsnID*/85, /*Imm*/29,
59290 /* 175542 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/85,
59291 /* 175544 */ GIR_MakeTempReg, /*TempRegID*/83, /*TypeID*/GILLT_s32,
59292 /* 175547 */ GIR_BuildMI, /*InsnID*/84, /*Opcode*/GIMT_Encode2(PPC::AND),
59293 /* 175551 */ GIR_AddTempRegister, /*InsnID*/84, /*TempRegID*/83, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59294 /* 175556 */ GIR_AddSimpleTempRegister, /*InsnID*/84, /*TempRegID*/84,
59295 /* 175559 */ GIR_AddSimpleTempRegister, /*InsnID*/84, /*TempRegID*/94,
59296 /* 175562 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/84,
59297 /* 175564 */ GIR_MakeTempReg, /*TempRegID*/82, /*TypeID*/GILLT_s32,
59298 /* 175567 */ GIR_BuildMI, /*InsnID*/83, /*Opcode*/GIMT_Encode2(PPC::LIS),
59299 /* 175571 */ GIR_AddTempRegister, /*InsnID*/83, /*TempRegID*/82, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59300 /* 175576 */ GIR_AddImm, /*InsnID*/83, /*Imm*/GIMT_Encode8(13107),
59301 /* 175586 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/83,
59302 /* 175588 */ GIR_MakeTempReg, /*TempRegID*/81, /*TypeID*/GILLT_s32,
59303 /* 175591 */ GIR_BuildMI, /*InsnID*/82, /*Opcode*/GIMT_Encode2(PPC::ORI),
59304 /* 175595 */ GIR_AddTempRegister, /*InsnID*/82, /*TempRegID*/81, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59305 /* 175600 */ GIR_AddSimpleTempRegister, /*InsnID*/82, /*TempRegID*/82,
59306 /* 175603 */ GIR_AddImm, /*InsnID*/82, /*Imm*/GIMT_Encode8(13107),
59307 /* 175613 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/82,
59308 /* 175615 */ GIR_MakeTempReg, /*TempRegID*/80, /*TypeID*/GILLT_s32,
59309 /* 175618 */ GIR_BuildMI, /*InsnID*/81, /*Opcode*/GIMT_Encode2(PPC::LIS),
59310 /* 175622 */ GIR_AddTempRegister, /*InsnID*/81, /*TempRegID*/80, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59311 /* 175627 */ GIR_AddImm, /*InsnID*/81, /*Imm*/GIMT_Encode8(43690),
59312 /* 175637 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/81,
59313 /* 175639 */ GIR_MakeTempReg, /*TempRegID*/79, /*TypeID*/GILLT_s32,
59314 /* 175642 */ GIR_BuildMI, /*InsnID*/80, /*Opcode*/GIMT_Encode2(PPC::ORI),
59315 /* 175646 */ GIR_AddTempRegister, /*InsnID*/80, /*TempRegID*/79, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59316 /* 175651 */ GIR_AddSimpleTempRegister, /*InsnID*/80, /*TempRegID*/80,
59317 /* 175654 */ GIR_AddImm, /*InsnID*/80, /*Imm*/GIMT_Encode8(43690),
59318 /* 175664 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/80,
59319 /* 175666 */ GIR_MakeTempReg, /*TempRegID*/78, /*TypeID*/GILLT_s32,
59320 /* 175669 */ GIR_BuildMI, /*InsnID*/79, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59321 /* 175673 */ GIR_AddTempRegister, /*InsnID*/79, /*TempRegID*/78, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59322 /* 175678 */ GIR_Copy, /*NewInsnID*/79, /*OldInsnID*/0, /*OpIdx*/1, // A
59323 /* 175682 */ GIR_AddImm8, /*InsnID*/79, /*Imm*/1,
59324 /* 175685 */ GIR_AddImm8, /*InsnID*/79, /*Imm*/0,
59325 /* 175688 */ GIR_AddImm8, /*InsnID*/79, /*Imm*/30,
59326 /* 175691 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/79,
59327 /* 175693 */ GIR_MakeTempReg, /*TempRegID*/77, /*TypeID*/GILLT_s32,
59328 /* 175696 */ GIR_BuildMI, /*InsnID*/78, /*Opcode*/GIMT_Encode2(PPC::AND),
59329 /* 175700 */ GIR_AddTempRegister, /*InsnID*/78, /*TempRegID*/77, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59330 /* 175705 */ GIR_AddSimpleTempRegister, /*InsnID*/78, /*TempRegID*/78,
59331 /* 175708 */ GIR_AddSimpleTempRegister, /*InsnID*/78, /*TempRegID*/79,
59332 /* 175711 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/78,
59333 /* 175713 */ GIR_MakeTempReg, /*TempRegID*/76, /*TypeID*/GILLT_s32,
59334 /* 175716 */ GIR_BuildMI, /*InsnID*/77, /*Opcode*/GIMT_Encode2(PPC::LIS),
59335 /* 175720 */ GIR_AddTempRegister, /*InsnID*/77, /*TempRegID*/76, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59336 /* 175725 */ GIR_AddImm, /*InsnID*/77, /*Imm*/GIMT_Encode8(21845),
59337 /* 175735 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/77,
59338 /* 175737 */ GIR_MakeTempReg, /*TempRegID*/75, /*TypeID*/GILLT_s32,
59339 /* 175740 */ GIR_BuildMI, /*InsnID*/76, /*Opcode*/GIMT_Encode2(PPC::ORI),
59340 /* 175744 */ GIR_AddTempRegister, /*InsnID*/76, /*TempRegID*/75, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59341 /* 175749 */ GIR_AddSimpleTempRegister, /*InsnID*/76, /*TempRegID*/76,
59342 /* 175752 */ GIR_AddImm, /*InsnID*/76, /*Imm*/GIMT_Encode8(21845),
59343 /* 175762 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/76,
59344 /* 175764 */ GIR_MakeTempReg, /*TempRegID*/74, /*TypeID*/GILLT_s32,
59345 /* 175767 */ GIR_BuildMI, /*InsnID*/75, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59346 /* 175771 */ GIR_AddTempRegister, /*InsnID*/75, /*TempRegID*/74, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59347 /* 175776 */ GIR_Copy, /*NewInsnID*/75, /*OldInsnID*/0, /*OpIdx*/1, // A
59348 /* 175780 */ GIR_AddImm8, /*InsnID*/75, /*Imm*/31,
59349 /* 175783 */ GIR_AddImm8, /*InsnID*/75, /*Imm*/1,
59350 /* 175786 */ GIR_AddImm8, /*InsnID*/75, /*Imm*/31,
59351 /* 175789 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/75,
59352 /* 175791 */ GIR_MakeTempReg, /*TempRegID*/73, /*TypeID*/GILLT_s32,
59353 /* 175794 */ GIR_BuildMI, /*InsnID*/74, /*Opcode*/GIMT_Encode2(PPC::AND),
59354 /* 175798 */ GIR_AddTempRegister, /*InsnID*/74, /*TempRegID*/73, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59355 /* 175803 */ GIR_AddSimpleTempRegister, /*InsnID*/74, /*TempRegID*/74,
59356 /* 175806 */ GIR_AddSimpleTempRegister, /*InsnID*/74, /*TempRegID*/75,
59357 /* 175809 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/74,
59358 /* 175811 */ GIR_MakeTempReg, /*TempRegID*/72, /*TypeID*/GILLT_s32,
59359 /* 175814 */ GIR_BuildMI, /*InsnID*/73, /*Opcode*/GIMT_Encode2(PPC::OR),
59360 /* 175818 */ GIR_AddTempRegister, /*InsnID*/73, /*TempRegID*/72, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59361 /* 175823 */ GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/73,
59362 /* 175826 */ GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/77,
59363 /* 175829 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/73,
59364 /* 175831 */ GIR_MakeTempReg, /*TempRegID*/71, /*TypeID*/GILLT_s32,
59365 /* 175834 */ GIR_BuildMI, /*InsnID*/72, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59366 /* 175838 */ GIR_AddTempRegister, /*InsnID*/72, /*TempRegID*/71, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59367 /* 175843 */ GIR_AddSimpleTempRegister, /*InsnID*/72, /*TempRegID*/72,
59368 /* 175846 */ GIR_AddImm8, /*InsnID*/72, /*Imm*/30,
59369 /* 175849 */ GIR_AddImm8, /*InsnID*/72, /*Imm*/2,
59370 /* 175852 */ GIR_AddImm8, /*InsnID*/72, /*Imm*/31,
59371 /* 175855 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/72,
59372 /* 175857 */ GIR_MakeTempReg, /*TempRegID*/70, /*TypeID*/GILLT_s32,
59373 /* 175860 */ GIR_BuildMI, /*InsnID*/71, /*Opcode*/GIMT_Encode2(PPC::AND),
59374 /* 175864 */ GIR_AddTempRegister, /*InsnID*/71, /*TempRegID*/70, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59375 /* 175869 */ GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/71,
59376 /* 175872 */ GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/81,
59377 /* 175875 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/71,
59378 /* 175877 */ GIR_MakeTempReg, /*TempRegID*/69, /*TypeID*/GILLT_s32,
59379 /* 175880 */ GIR_BuildMI, /*InsnID*/70, /*Opcode*/GIMT_Encode2(PPC::OR),
59380 /* 175884 */ GIR_AddTempRegister, /*InsnID*/70, /*TempRegID*/69, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59381 /* 175889 */ GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/70,
59382 /* 175892 */ GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/83,
59383 /* 175895 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/70,
59384 /* 175897 */ GIR_MakeTempReg, /*TempRegID*/68, /*TypeID*/GILLT_s32,
59385 /* 175900 */ GIR_BuildMI, /*InsnID*/69, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59386 /* 175904 */ GIR_AddTempRegister, /*InsnID*/69, /*TempRegID*/68, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59387 /* 175909 */ GIR_AddSimpleTempRegister, /*InsnID*/69, /*TempRegID*/69,
59388 /* 175912 */ GIR_AddImm8, /*InsnID*/69, /*Imm*/28,
59389 /* 175915 */ GIR_AddImm8, /*InsnID*/69, /*Imm*/4,
59390 /* 175918 */ GIR_AddImm8, /*InsnID*/69, /*Imm*/31,
59391 /* 175921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/69,
59392 /* 175923 */ GIR_MakeTempReg, /*TempRegID*/67, /*TypeID*/GILLT_s32,
59393 /* 175926 */ GIR_BuildMI, /*InsnID*/68, /*Opcode*/GIMT_Encode2(PPC::AND),
59394 /* 175930 */ GIR_AddTempRegister, /*InsnID*/68, /*TempRegID*/67, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59395 /* 175935 */ GIR_AddSimpleTempRegister, /*InsnID*/68, /*TempRegID*/68,
59396 /* 175938 */ GIR_AddSimpleTempRegister, /*InsnID*/68, /*TempRegID*/96,
59397 /* 175941 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/68,
59398 /* 175943 */ GIR_MakeTempReg, /*TempRegID*/66, /*TypeID*/GILLT_s32,
59399 /* 175946 */ GIR_BuildMI, /*InsnID*/67, /*Opcode*/GIMT_Encode2(PPC::OR),
59400 /* 175950 */ GIR_AddTempRegister, /*InsnID*/67, /*TempRegID*/66, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59401 /* 175955 */ GIR_AddSimpleTempRegister, /*InsnID*/67, /*TempRegID*/67,
59402 /* 175958 */ GIR_AddSimpleTempRegister, /*InsnID*/67, /*TempRegID*/98,
59403 /* 175961 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/67,
59404 /* 175963 */ GIR_MakeTempReg, /*TempRegID*/65, /*TypeID*/GILLT_s32,
59405 /* 175966 */ GIR_BuildMI, /*InsnID*/66, /*Opcode*/GIMT_Encode2(PPC::LIS),
59406 /* 175970 */ GIR_AddTempRegister, /*InsnID*/66, /*TempRegID*/65, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59407 /* 175975 */ GIR_AddImm, /*InsnID*/66, /*Imm*/GIMT_Encode8(61680),
59408 /* 175985 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/66,
59409 /* 175987 */ GIR_MakeTempReg, /*TempRegID*/64, /*TypeID*/GILLT_s32,
59410 /* 175990 */ GIR_BuildMI, /*InsnID*/65, /*Opcode*/GIMT_Encode2(PPC::ORI),
59411 /* 175994 */ GIR_AddTempRegister, /*InsnID*/65, /*TempRegID*/64, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59412 /* 175999 */ GIR_AddSimpleTempRegister, /*InsnID*/65, /*TempRegID*/65,
59413 /* 176002 */ GIR_AddImm, /*InsnID*/65, /*Imm*/GIMT_Encode8(61680),
59414 /* 176012 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/65,
59415 /* 176014 */ GIR_MakeTempReg, /*TempRegID*/63, /*TypeID*/GILLT_s32,
59416 /* 176017 */ GIR_BuildMI, /*InsnID*/64, /*Opcode*/GIMT_Encode2(PPC::LIS),
59417 /* 176021 */ GIR_AddTempRegister, /*InsnID*/64, /*TempRegID*/63, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59418 /* 176026 */ GIR_AddImm, /*InsnID*/64, /*Imm*/GIMT_Encode8(52428),
59419 /* 176036 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/64,
59420 /* 176038 */ GIR_MakeTempReg, /*TempRegID*/62, /*TypeID*/GILLT_s32,
59421 /* 176041 */ GIR_BuildMI, /*InsnID*/63, /*Opcode*/GIMT_Encode2(PPC::ORI),
59422 /* 176045 */ GIR_AddTempRegister, /*InsnID*/63, /*TempRegID*/62, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59423 /* 176050 */ GIR_AddSimpleTempRegister, /*InsnID*/63, /*TempRegID*/63,
59424 /* 176053 */ GIR_AddImm, /*InsnID*/63, /*Imm*/GIMT_Encode8(52428),
59425 /* 176063 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/63,
59426 /* 176065 */ GIR_MakeTempReg, /*TempRegID*/61, /*TypeID*/GILLT_s32,
59427 /* 176068 */ GIR_BuildMI, /*InsnID*/62, /*Opcode*/GIMT_Encode2(PPC::LIS),
59428 /* 176072 */ GIR_AddTempRegister, /*InsnID*/62, /*TempRegID*/61, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59429 /* 176077 */ GIR_AddImm, /*InsnID*/62, /*Imm*/GIMT_Encode8(43690),
59430 /* 176087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/62,
59431 /* 176089 */ GIR_MakeTempReg, /*TempRegID*/60, /*TypeID*/GILLT_s32,
59432 /* 176092 */ GIR_BuildMI, /*InsnID*/61, /*Opcode*/GIMT_Encode2(PPC::ORI),
59433 /* 176096 */ GIR_AddTempRegister, /*InsnID*/61, /*TempRegID*/60, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59434 /* 176101 */ GIR_AddSimpleTempRegister, /*InsnID*/61, /*TempRegID*/61,
59435 /* 176104 */ GIR_AddImm, /*InsnID*/61, /*Imm*/GIMT_Encode8(43690),
59436 /* 176114 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/61,
59437 /* 176116 */ GIR_MakeTempReg, /*TempRegID*/59, /*TypeID*/GILLT_s32,
59438 /* 176119 */ GIR_BuildMI, /*InsnID*/60, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59439 /* 176123 */ GIR_AddTempRegister, /*InsnID*/60, /*TempRegID*/59, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59440 /* 176128 */ GIR_Copy, /*NewInsnID*/60, /*OldInsnID*/0, /*OpIdx*/1, // A
59441 /* 176132 */ GIR_AddImm8, /*InsnID*/60, /*Imm*/1,
59442 /* 176135 */ GIR_AddImm8, /*InsnID*/60, /*Imm*/0,
59443 /* 176138 */ GIR_AddImm8, /*InsnID*/60, /*Imm*/30,
59444 /* 176141 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/60,
59445 /* 176143 */ GIR_MakeTempReg, /*TempRegID*/58, /*TypeID*/GILLT_s32,
59446 /* 176146 */ GIR_BuildMI, /*InsnID*/59, /*Opcode*/GIMT_Encode2(PPC::AND),
59447 /* 176150 */ GIR_AddTempRegister, /*InsnID*/59, /*TempRegID*/58, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59448 /* 176155 */ GIR_AddSimpleTempRegister, /*InsnID*/59, /*TempRegID*/59,
59449 /* 176158 */ GIR_AddSimpleTempRegister, /*InsnID*/59, /*TempRegID*/60,
59450 /* 176161 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/59,
59451 /* 176163 */ GIR_MakeTempReg, /*TempRegID*/57, /*TypeID*/GILLT_s32,
59452 /* 176166 */ GIR_BuildMI, /*InsnID*/58, /*Opcode*/GIMT_Encode2(PPC::LIS),
59453 /* 176170 */ GIR_AddTempRegister, /*InsnID*/58, /*TempRegID*/57, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59454 /* 176175 */ GIR_AddImm, /*InsnID*/58, /*Imm*/GIMT_Encode8(21845),
59455 /* 176185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/58,
59456 /* 176187 */ GIR_MakeTempReg, /*TempRegID*/56, /*TypeID*/GILLT_s32,
59457 /* 176190 */ GIR_BuildMI, /*InsnID*/57, /*Opcode*/GIMT_Encode2(PPC::ORI),
59458 /* 176194 */ GIR_AddTempRegister, /*InsnID*/57, /*TempRegID*/56, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59459 /* 176199 */ GIR_AddSimpleTempRegister, /*InsnID*/57, /*TempRegID*/57,
59460 /* 176202 */ GIR_AddImm, /*InsnID*/57, /*Imm*/GIMT_Encode8(21845),
59461 /* 176212 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/57,
59462 /* 176214 */ GIR_MakeTempReg, /*TempRegID*/55, /*TypeID*/GILLT_s32,
59463 /* 176217 */ GIR_BuildMI, /*InsnID*/56, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59464 /* 176221 */ GIR_AddTempRegister, /*InsnID*/56, /*TempRegID*/55, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59465 /* 176226 */ GIR_Copy, /*NewInsnID*/56, /*OldInsnID*/0, /*OpIdx*/1, // A
59466 /* 176230 */ GIR_AddImm8, /*InsnID*/56, /*Imm*/31,
59467 /* 176233 */ GIR_AddImm8, /*InsnID*/56, /*Imm*/1,
59468 /* 176236 */ GIR_AddImm8, /*InsnID*/56, /*Imm*/31,
59469 /* 176239 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/56,
59470 /* 176241 */ GIR_MakeTempReg, /*TempRegID*/54, /*TypeID*/GILLT_s32,
59471 /* 176244 */ GIR_BuildMI, /*InsnID*/55, /*Opcode*/GIMT_Encode2(PPC::AND),
59472 /* 176248 */ GIR_AddTempRegister, /*InsnID*/55, /*TempRegID*/54, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59473 /* 176253 */ GIR_AddSimpleTempRegister, /*InsnID*/55, /*TempRegID*/55,
59474 /* 176256 */ GIR_AddSimpleTempRegister, /*InsnID*/55, /*TempRegID*/56,
59475 /* 176259 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/55,
59476 /* 176261 */ GIR_MakeTempReg, /*TempRegID*/53, /*TypeID*/GILLT_s32,
59477 /* 176264 */ GIR_BuildMI, /*InsnID*/54, /*Opcode*/GIMT_Encode2(PPC::OR),
59478 /* 176268 */ GIR_AddTempRegister, /*InsnID*/54, /*TempRegID*/53, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59479 /* 176273 */ GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/54,
59480 /* 176276 */ GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/58,
59481 /* 176279 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/54,
59482 /* 176281 */ GIR_MakeTempReg, /*TempRegID*/52, /*TypeID*/GILLT_s32,
59483 /* 176284 */ GIR_BuildMI, /*InsnID*/53, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59484 /* 176288 */ GIR_AddTempRegister, /*InsnID*/53, /*TempRegID*/52, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59485 /* 176293 */ GIR_AddSimpleTempRegister, /*InsnID*/53, /*TempRegID*/53,
59486 /* 176296 */ GIR_AddImm8, /*InsnID*/53, /*Imm*/2,
59487 /* 176299 */ GIR_AddImm8, /*InsnID*/53, /*Imm*/0,
59488 /* 176302 */ GIR_AddImm8, /*InsnID*/53, /*Imm*/29,
59489 /* 176305 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/53,
59490 /* 176307 */ GIR_MakeTempReg, /*TempRegID*/51, /*TypeID*/GILLT_s32,
59491 /* 176310 */ GIR_BuildMI, /*InsnID*/52, /*Opcode*/GIMT_Encode2(PPC::AND),
59492 /* 176314 */ GIR_AddTempRegister, /*InsnID*/52, /*TempRegID*/51, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59493 /* 176319 */ GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/52,
59494 /* 176322 */ GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/62,
59495 /* 176325 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/52,
59496 /* 176327 */ GIR_MakeTempReg, /*TempRegID*/50, /*TypeID*/GILLT_s32,
59497 /* 176330 */ GIR_BuildMI, /*InsnID*/51, /*Opcode*/GIMT_Encode2(PPC::LIS),
59498 /* 176334 */ GIR_AddTempRegister, /*InsnID*/51, /*TempRegID*/50, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59499 /* 176339 */ GIR_AddImm, /*InsnID*/51, /*Imm*/GIMT_Encode8(13107),
59500 /* 176349 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/51,
59501 /* 176351 */ GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_s32,
59502 /* 176354 */ GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(PPC::ORI),
59503 /* 176358 */ GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59504 /* 176363 */ GIR_AddSimpleTempRegister, /*InsnID*/50, /*TempRegID*/50,
59505 /* 176366 */ GIR_AddImm, /*InsnID*/50, /*Imm*/GIMT_Encode8(13107),
59506 /* 176376 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
59507 /* 176378 */ GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_s32,
59508 /* 176381 */ GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(PPC::LIS),
59509 /* 176385 */ GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59510 /* 176390 */ GIR_AddImm, /*InsnID*/49, /*Imm*/GIMT_Encode8(43690),
59511 /* 176400 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
59512 /* 176402 */ GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_s32,
59513 /* 176405 */ GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(PPC::ORI),
59514 /* 176409 */ GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59515 /* 176414 */ GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
59516 /* 176417 */ GIR_AddImm, /*InsnID*/48, /*Imm*/GIMT_Encode8(43690),
59517 /* 176427 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
59518 /* 176429 */ GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s32,
59519 /* 176432 */ GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59520 /* 176436 */ GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59521 /* 176441 */ GIR_Copy, /*NewInsnID*/47, /*OldInsnID*/0, /*OpIdx*/1, // A
59522 /* 176445 */ GIR_AddImm8, /*InsnID*/47, /*Imm*/1,
59523 /* 176448 */ GIR_AddImm8, /*InsnID*/47, /*Imm*/0,
59524 /* 176451 */ GIR_AddImm8, /*InsnID*/47, /*Imm*/30,
59525 /* 176454 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
59526 /* 176456 */ GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s32,
59527 /* 176459 */ GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(PPC::AND),
59528 /* 176463 */ GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59529 /* 176468 */ GIR_AddSimpleTempRegister, /*InsnID*/46, /*TempRegID*/46,
59530 /* 176471 */ GIR_AddSimpleTempRegister, /*InsnID*/46, /*TempRegID*/47,
59531 /* 176474 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
59532 /* 176476 */ GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s32,
59533 /* 176479 */ GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(PPC::LIS),
59534 /* 176483 */ GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59535 /* 176488 */ GIR_AddImm, /*InsnID*/45, /*Imm*/GIMT_Encode8(21845),
59536 /* 176498 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
59537 /* 176500 */ GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s32,
59538 /* 176503 */ GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(PPC::ORI),
59539 /* 176507 */ GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59540 /* 176512 */ GIR_AddSimpleTempRegister, /*InsnID*/44, /*TempRegID*/44,
59541 /* 176515 */ GIR_AddImm, /*InsnID*/44, /*Imm*/GIMT_Encode8(21845),
59542 /* 176525 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
59543 /* 176527 */ GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s32,
59544 /* 176530 */ GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59545 /* 176534 */ GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59546 /* 176539 */ GIR_Copy, /*NewInsnID*/43, /*OldInsnID*/0, /*OpIdx*/1, // A
59547 /* 176543 */ GIR_AddImm8, /*InsnID*/43, /*Imm*/31,
59548 /* 176546 */ GIR_AddImm8, /*InsnID*/43, /*Imm*/1,
59549 /* 176549 */ GIR_AddImm8, /*InsnID*/43, /*Imm*/31,
59550 /* 176552 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
59551 /* 176554 */ GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_s32,
59552 /* 176557 */ GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(PPC::AND),
59553 /* 176561 */ GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59554 /* 176566 */ GIR_AddSimpleTempRegister, /*InsnID*/42, /*TempRegID*/42,
59555 /* 176569 */ GIR_AddSimpleTempRegister, /*InsnID*/42, /*TempRegID*/43,
59556 /* 176572 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
59557 /* 176574 */ GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_s32,
59558 /* 176577 */ GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(PPC::OR),
59559 /* 176581 */ GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59560 /* 176586 */ GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/41,
59561 /* 176589 */ GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/45,
59562 /* 176592 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
59563 /* 176594 */ GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_s32,
59564 /* 176597 */ GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59565 /* 176601 */ GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59566 /* 176606 */ GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
59567 /* 176609 */ GIR_AddImm8, /*InsnID*/40, /*Imm*/30,
59568 /* 176612 */ GIR_AddImm8, /*InsnID*/40, /*Imm*/2,
59569 /* 176615 */ GIR_AddImm8, /*InsnID*/40, /*Imm*/31,
59570 /* 176618 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
59571 /* 176620 */ GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s32,
59572 /* 176623 */ GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(PPC::AND),
59573 /* 176627 */ GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59574 /* 176632 */ GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
59575 /* 176635 */ GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/49,
59576 /* 176638 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
59577 /* 176640 */ GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s32,
59578 /* 176643 */ GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(PPC::OR),
59579 /* 176647 */ GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59580 /* 176652 */ GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
59581 /* 176655 */ GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/51,
59582 /* 176658 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
59583 /* 176660 */ GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_s32,
59584 /* 176663 */ GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59585 /* 176667 */ GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59586 /* 176672 */ GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
59587 /* 176675 */ GIR_AddImm8, /*InsnID*/37, /*Imm*/4,
59588 /* 176678 */ GIR_AddImm8, /*InsnID*/37, /*Imm*/0,
59589 /* 176681 */ GIR_AddImm8, /*InsnID*/37, /*Imm*/27,
59590 /* 176684 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
59591 /* 176686 */ GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s32,
59592 /* 176689 */ GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(PPC::AND),
59593 /* 176693 */ GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59594 /* 176698 */ GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
59595 /* 176701 */ GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/64,
59596 /* 176704 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
59597 /* 176706 */ GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s32,
59598 /* 176709 */ GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(PPC::LIS),
59599 /* 176713 */ GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59600 /* 176718 */ GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(3855),
59601 /* 176728 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
59602 /* 176730 */ GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s32,
59603 /* 176733 */ GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(PPC::ORI),
59604 /* 176737 */ GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59605 /* 176742 */ GIR_AddSimpleTempRegister, /*InsnID*/34, /*TempRegID*/34,
59606 /* 176745 */ GIR_AddImm, /*InsnID*/34, /*Imm*/GIMT_Encode8(3855),
59607 /* 176755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
59608 /* 176757 */ GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s32,
59609 /* 176760 */ GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(PPC::LIS),
59610 /* 176764 */ GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59611 /* 176769 */ GIR_AddImm, /*InsnID*/33, /*Imm*/GIMT_Encode8(52428),
59612 /* 176779 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
59613 /* 176781 */ GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s32,
59614 /* 176784 */ GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(PPC::ORI),
59615 /* 176788 */ GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59616 /* 176793 */ GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
59617 /* 176796 */ GIR_AddImm, /*InsnID*/32, /*Imm*/GIMT_Encode8(52428),
59618 /* 176806 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
59619 /* 176808 */ GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s32,
59620 /* 176811 */ GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(PPC::LIS),
59621 /* 176815 */ GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59622 /* 176820 */ GIR_AddImm, /*InsnID*/31, /*Imm*/GIMT_Encode8(43690),
59623 /* 176830 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
59624 /* 176832 */ GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s32,
59625 /* 176835 */ GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(PPC::ORI),
59626 /* 176839 */ GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59627 /* 176844 */ GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
59628 /* 176847 */ GIR_AddImm, /*InsnID*/30, /*Imm*/GIMT_Encode8(43690),
59629 /* 176857 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
59630 /* 176859 */ GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s32,
59631 /* 176862 */ GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59632 /* 176866 */ GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59633 /* 176871 */ GIR_Copy, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/1, // A
59634 /* 176875 */ GIR_AddImm8, /*InsnID*/29, /*Imm*/1,
59635 /* 176878 */ GIR_AddImm8, /*InsnID*/29, /*Imm*/0,
59636 /* 176881 */ GIR_AddImm8, /*InsnID*/29, /*Imm*/30,
59637 /* 176884 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
59638 /* 176886 */ GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s32,
59639 /* 176889 */ GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(PPC::AND),
59640 /* 176893 */ GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59641 /* 176898 */ GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
59642 /* 176901 */ GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/29,
59643 /* 176904 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
59644 /* 176906 */ GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_s32,
59645 /* 176909 */ GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(PPC::LIS),
59646 /* 176913 */ GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59647 /* 176918 */ GIR_AddImm, /*InsnID*/27, /*Imm*/GIMT_Encode8(21845),
59648 /* 176928 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
59649 /* 176930 */ GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_s32,
59650 /* 176933 */ GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(PPC::ORI),
59651 /* 176937 */ GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59652 /* 176942 */ GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
59653 /* 176945 */ GIR_AddImm, /*InsnID*/26, /*Imm*/GIMT_Encode8(21845),
59654 /* 176955 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
59655 /* 176957 */ GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_s32,
59656 /* 176960 */ GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59657 /* 176964 */ GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59658 /* 176969 */ GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // A
59659 /* 176973 */ GIR_AddImm8, /*InsnID*/25, /*Imm*/31,
59660 /* 176976 */ GIR_AddImm8, /*InsnID*/25, /*Imm*/1,
59661 /* 176979 */ GIR_AddImm8, /*InsnID*/25, /*Imm*/31,
59662 /* 176982 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
59663 /* 176984 */ GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s32,
59664 /* 176987 */ GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(PPC::AND),
59665 /* 176991 */ GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59666 /* 176996 */ GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
59667 /* 176999 */ GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/25,
59668 /* 177002 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
59669 /* 177004 */ GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s32,
59670 /* 177007 */ GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(PPC::OR),
59671 /* 177011 */ GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59672 /* 177016 */ GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
59673 /* 177019 */ GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/27,
59674 /* 177022 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
59675 /* 177024 */ GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s32,
59676 /* 177027 */ GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59677 /* 177031 */ GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59678 /* 177036 */ GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
59679 /* 177039 */ GIR_AddImm8, /*InsnID*/22, /*Imm*/2,
59680 /* 177042 */ GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
59681 /* 177045 */ GIR_AddImm8, /*InsnID*/22, /*Imm*/29,
59682 /* 177048 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
59683 /* 177050 */ GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s32,
59684 /* 177053 */ GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(PPC::AND),
59685 /* 177057 */ GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59686 /* 177062 */ GIR_AddSimpleTempRegister, /*InsnID*/21, /*TempRegID*/21,
59687 /* 177065 */ GIR_AddSimpleTempRegister, /*InsnID*/21, /*TempRegID*/31,
59688 /* 177068 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
59689 /* 177070 */ GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s32,
59690 /* 177073 */ GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(PPC::LIS),
59691 /* 177077 */ GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59692 /* 177082 */ GIR_AddImm, /*InsnID*/20, /*Imm*/GIMT_Encode8(13107),
59693 /* 177092 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
59694 /* 177094 */ GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_s32,
59695 /* 177097 */ GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(PPC::ORI),
59696 /* 177101 */ GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59697 /* 177106 */ GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
59698 /* 177109 */ GIR_AddImm, /*InsnID*/19, /*Imm*/GIMT_Encode8(13107),
59699 /* 177119 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
59700 /* 177121 */ GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s32,
59701 /* 177124 */ GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(PPC::LIS),
59702 /* 177128 */ GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59703 /* 177133 */ GIR_AddImm, /*InsnID*/18, /*Imm*/GIMT_Encode8(43690),
59704 /* 177143 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
59705 /* 177145 */ GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s32,
59706 /* 177148 */ GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(PPC::ORI),
59707 /* 177152 */ GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59708 /* 177157 */ GIR_AddSimpleTempRegister, /*InsnID*/17, /*TempRegID*/17,
59709 /* 177160 */ GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(43690),
59710 /* 177170 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
59711 /* 177172 */ GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s32,
59712 /* 177175 */ GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59713 /* 177179 */ GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59714 /* 177184 */ GIR_Copy, /*NewInsnID*/16, /*OldInsnID*/0, /*OpIdx*/1, // A
59715 /* 177188 */ GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
59716 /* 177191 */ GIR_AddImm8, /*InsnID*/16, /*Imm*/0,
59717 /* 177194 */ GIR_AddImm8, /*InsnID*/16, /*Imm*/30,
59718 /* 177197 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
59719 /* 177199 */ GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s32,
59720 /* 177202 */ GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(PPC::AND),
59721 /* 177206 */ GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59722 /* 177211 */ GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
59723 /* 177214 */ GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/16,
59724 /* 177217 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
59725 /* 177219 */ GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s32,
59726 /* 177222 */ GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(PPC::LIS),
59727 /* 177226 */ GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59728 /* 177231 */ GIR_AddImm, /*InsnID*/14, /*Imm*/GIMT_Encode8(21845),
59729 /* 177241 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
59730 /* 177243 */ GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s32,
59731 /* 177246 */ GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(PPC::ORI),
59732 /* 177250 */ GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59733 /* 177255 */ GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
59734 /* 177258 */ GIR_AddImm, /*InsnID*/13, /*Imm*/GIMT_Encode8(21845),
59735 /* 177268 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
59736 /* 177270 */ GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
59737 /* 177273 */ GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59738 /* 177277 */ GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59739 /* 177282 */ GIR_Copy, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/1, // A
59740 /* 177286 */ GIR_AddImm8, /*InsnID*/12, /*Imm*/31,
59741 /* 177289 */ GIR_AddImm8, /*InsnID*/12, /*Imm*/1,
59742 /* 177292 */ GIR_AddImm8, /*InsnID*/12, /*Imm*/31,
59743 /* 177295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
59744 /* 177297 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
59745 /* 177300 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(PPC::AND),
59746 /* 177304 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59747 /* 177309 */ GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
59748 /* 177312 */ GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/12,
59749 /* 177315 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
59750 /* 177317 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
59751 /* 177320 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(PPC::OR),
59752 /* 177324 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59753 /* 177329 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
59754 /* 177332 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/14,
59755 /* 177335 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
59756 /* 177337 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
59757 /* 177340 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59758 /* 177344 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59759 /* 177349 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
59760 /* 177352 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/30,
59761 /* 177355 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/2,
59762 /* 177358 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/31,
59763 /* 177361 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
59764 /* 177363 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
59765 /* 177366 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(PPC::AND),
59766 /* 177370 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59767 /* 177375 */ GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
59768 /* 177378 */ GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/18,
59769 /* 177381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
59770 /* 177383 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
59771 /* 177386 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(PPC::OR),
59772 /* 177390 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59773 /* 177395 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
59774 /* 177398 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/20,
59775 /* 177401 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
59776 /* 177403 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
59777 /* 177406 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59778 /* 177410 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59779 /* 177415 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
59780 /* 177418 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/28,
59781 /* 177421 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/4,
59782 /* 177424 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/31,
59783 /* 177427 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
59784 /* 177429 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
59785 /* 177432 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(PPC::AND),
59786 /* 177436 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59787 /* 177441 */ GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
59788 /* 177444 */ GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/33,
59789 /* 177447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
59790 /* 177449 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
59791 /* 177452 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::OR),
59792 /* 177456 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59793 /* 177461 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
59794 /* 177464 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/35,
59795 /* 177467 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
59796 /* 177469 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
59797 /* 177472 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59798 /* 177476 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59799 /* 177481 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
59800 /* 177484 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/24,
59801 /* 177487 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
59802 /* 177490 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/31,
59803 /* 177493 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
59804 /* 177495 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
59805 /* 177498 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWIMI),
59806 /* 177502 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59807 /* 177507 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
59808 /* 177510 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/66,
59809 /* 177513 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/8,
59810 /* 177516 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/8,
59811 /* 177519 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/15,
59812 /* 177522 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
59813 /* 177524 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
59814 /* 177527 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLWIMI),
59815 /* 177531 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59816 /* 177536 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
59817 /* 177539 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*//* 129(*/0x81, 0x01/*)*/,
59818 /* 177543 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
59819 /* 177546 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/24,
59820 /* 177549 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
59821 /* 177552 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
59822 /* 177554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL_32),
59823 /* 177557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
59824 /* 177559 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
59825 /* 177562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
59826 /* 177565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
59827 /* 177568 */ GIR_RootConstrainSelectedInstOperands,
59828 /* 177569 */ // GIR_Coverage, 4889,
59829 /* 177569 */ GIR_EraseRootFromParent_Done,
59830 /* 177570 */ // Label 2768: @177570
59831 /* 177570 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(182695), // Rule ID 4890 //
59832 /* 177575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_In32BitMode),
59833 /* 177578 */ // (bitreverse:{ *:[i32] } i32:{ *:[i32] }:$A) => (RLWIMI:{ *:[i32] } (RLWIMI:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 24:{ *:[i32] }, 0:{ *:[i32] }, 31:{ *:[i32] }), (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 8:{ *:[i32] }, 8:{ *:[i32] }, 15:{ *:[i32] }), (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 8:{ *:[i32] }, 24:{ *:[i32] }, 31:{ *:[i32] })
59834 /* 177578 */ GIR_MakeTempReg, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TypeID*/GILLT_s32,
59835 /* 177582 */ GIR_BuildMI, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
59836 /* 177587 */ GIR_AddTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59837 /* 177594 */ GIR_AddImm, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
59838 /* 177605 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 191(*/0xBF, 0x01/*)*/,
59839 /* 177608 */ GIR_MakeTempReg, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TypeID*/GILLT_s32,
59840 /* 177612 */ GIR_BuildMI, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
59841 /* 177617 */ GIR_AddTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59842 /* 177624 */ GIR_AddSimpleTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/,
59843 /* 177629 */ GIR_AddImm, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
59844 /* 177640 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 190(*/0xBE, 0x01/*)*/,
59845 /* 177643 */ GIR_MakeTempReg, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TypeID*/GILLT_s32,
59846 /* 177647 */ GIR_BuildMI, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
59847 /* 177652 */ GIR_AddTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59848 /* 177659 */ GIR_AddImm, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
59849 /* 177670 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 189(*/0xBD, 0x01/*)*/,
59850 /* 177673 */ GIR_MakeTempReg, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TypeID*/GILLT_s32,
59851 /* 177677 */ GIR_BuildMI, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
59852 /* 177682 */ GIR_AddTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59853 /* 177689 */ GIR_AddSimpleTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/,
59854 /* 177694 */ GIR_AddImm, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
59855 /* 177705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 188(*/0xBC, 0x01/*)*/,
59856 /* 177708 */ GIR_MakeTempReg, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TypeID*/GILLT_s32,
59857 /* 177712 */ GIR_BuildMI, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
59858 /* 177717 */ GIR_AddTempRegister, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59859 /* 177724 */ GIR_AddImm, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
59860 /* 177735 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 187(*/0xBB, 0x01/*)*/,
59861 /* 177738 */ GIR_MakeTempReg, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TypeID*/GILLT_s32,
59862 /* 177742 */ GIR_BuildMI, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
59863 /* 177747 */ GIR_AddTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59864 /* 177754 */ GIR_AddSimpleTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/,
59865 /* 177759 */ GIR_AddImm, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
59866 /* 177770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 186(*/0xBA, 0x01/*)*/,
59867 /* 177773 */ GIR_MakeTempReg, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TypeID*/GILLT_s32,
59868 /* 177777 */ GIR_BuildMI, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59869 /* 177782 */ GIR_AddTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59870 /* 177789 */ GIR_Copy, /*NewInsnID*//* 185(*/0xB9, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
59871 /* 177794 */ GIR_AddImm8, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Imm*/1,
59872 /* 177798 */ GIR_AddImm8, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Imm*/0,
59873 /* 177802 */ GIR_AddImm8, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Imm*/30,
59874 /* 177806 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 185(*/0xB9, 0x01/*)*/,
59875 /* 177809 */ GIR_MakeTempReg, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TypeID*/GILLT_s32,
59876 /* 177813 */ GIR_BuildMI, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
59877 /* 177818 */ GIR_AddTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59878 /* 177825 */ GIR_AddSimpleTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/,
59879 /* 177830 */ GIR_AddSimpleTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/,
59880 /* 177835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 184(*/0xB8, 0x01/*)*/,
59881 /* 177838 */ GIR_MakeTempReg, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TypeID*/GILLT_s32,
59882 /* 177842 */ GIR_BuildMI, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
59883 /* 177847 */ GIR_AddTempRegister, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59884 /* 177854 */ GIR_AddImm, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
59885 /* 177865 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 183(*/0xB7, 0x01/*)*/,
59886 /* 177868 */ GIR_MakeTempReg, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TypeID*/GILLT_s32,
59887 /* 177872 */ GIR_BuildMI, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
59888 /* 177877 */ GIR_AddTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59889 /* 177884 */ GIR_AddSimpleTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/,
59890 /* 177889 */ GIR_AddImm, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
59891 /* 177900 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 182(*/0xB6, 0x01/*)*/,
59892 /* 177903 */ GIR_MakeTempReg, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TypeID*/GILLT_s32,
59893 /* 177907 */ GIR_BuildMI, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59894 /* 177912 */ GIR_AddTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59895 /* 177919 */ GIR_Copy, /*NewInsnID*//* 181(*/0xB5, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
59896 /* 177924 */ GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/31,
59897 /* 177928 */ GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/1,
59898 /* 177932 */ GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/31,
59899 /* 177936 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 181(*/0xB5, 0x01/*)*/,
59900 /* 177939 */ GIR_MakeTempReg, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TypeID*/GILLT_s32,
59901 /* 177943 */ GIR_BuildMI, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
59902 /* 177948 */ GIR_AddTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59903 /* 177955 */ GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/,
59904 /* 177960 */ GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/,
59905 /* 177965 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 180(*/0xB4, 0x01/*)*/,
59906 /* 177968 */ GIR_MakeTempReg, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TypeID*/GILLT_s32,
59907 /* 177972 */ GIR_BuildMI, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
59908 /* 177977 */ GIR_AddTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59909 /* 177984 */ GIR_AddSimpleTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/,
59910 /* 177989 */ GIR_AddSimpleTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/,
59911 /* 177994 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 179(*/0xB3, 0x01/*)*/,
59912 /* 177997 */ GIR_MakeTempReg, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TypeID*/GILLT_s32,
59913 /* 178001 */ GIR_BuildMI, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59914 /* 178006 */ GIR_AddTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59915 /* 178013 */ GIR_AddSimpleTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/,
59916 /* 178018 */ GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/2,
59917 /* 178022 */ GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/0,
59918 /* 178026 */ GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/29,
59919 /* 178030 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 178(*/0xB2, 0x01/*)*/,
59920 /* 178033 */ GIR_MakeTempReg, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TypeID*/GILLT_s32,
59921 /* 178037 */ GIR_BuildMI, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
59922 /* 178042 */ GIR_AddTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59923 /* 178049 */ GIR_AddSimpleTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/,
59924 /* 178054 */ GIR_AddSimpleTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/,
59925 /* 178059 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 177(*/0xB1, 0x01/*)*/,
59926 /* 178062 */ GIR_MakeTempReg, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TypeID*/GILLT_s32,
59927 /* 178066 */ GIR_BuildMI, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
59928 /* 178071 */ GIR_AddTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59929 /* 178078 */ GIR_AddImm, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
59930 /* 178089 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 176(*/0xB0, 0x01/*)*/,
59931 /* 178092 */ GIR_MakeTempReg, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TypeID*/GILLT_s32,
59932 /* 178096 */ GIR_BuildMI, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
59933 /* 178101 */ GIR_AddTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59934 /* 178108 */ GIR_AddSimpleTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/,
59935 /* 178113 */ GIR_AddImm, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
59936 /* 178124 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 175(*/0xAF, 0x01/*)*/,
59937 /* 178127 */ GIR_MakeTempReg, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TypeID*/GILLT_s32,
59938 /* 178131 */ GIR_BuildMI, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
59939 /* 178136 */ GIR_AddTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59940 /* 178143 */ GIR_AddImm, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
59941 /* 178154 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 174(*/0xAE, 0x01/*)*/,
59942 /* 178157 */ GIR_MakeTempReg, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TypeID*/GILLT_s32,
59943 /* 178161 */ GIR_BuildMI, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
59944 /* 178166 */ GIR_AddTempRegister, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59945 /* 178173 */ GIR_AddSimpleTempRegister, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/,
59946 /* 178178 */ GIR_AddImm, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
59947 /* 178189 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 173(*/0xAD, 0x01/*)*/,
59948 /* 178192 */ GIR_MakeTempReg, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TypeID*/GILLT_s32,
59949 /* 178196 */ GIR_BuildMI, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59950 /* 178201 */ GIR_AddTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59951 /* 178208 */ GIR_Copy, /*NewInsnID*//* 172(*/0xAC, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
59952 /* 178213 */ GIR_AddImm8, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Imm*/1,
59953 /* 178217 */ GIR_AddImm8, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Imm*/0,
59954 /* 178221 */ GIR_AddImm8, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Imm*/30,
59955 /* 178225 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 172(*/0xAC, 0x01/*)*/,
59956 /* 178228 */ GIR_MakeTempReg, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TypeID*/GILLT_s32,
59957 /* 178232 */ GIR_BuildMI, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
59958 /* 178237 */ GIR_AddTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59959 /* 178244 */ GIR_AddSimpleTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/,
59960 /* 178249 */ GIR_AddSimpleTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/,
59961 /* 178254 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 171(*/0xAB, 0x01/*)*/,
59962 /* 178257 */ GIR_MakeTempReg, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TypeID*/GILLT_s32,
59963 /* 178261 */ GIR_BuildMI, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
59964 /* 178266 */ GIR_AddTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59965 /* 178273 */ GIR_AddImm, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
59966 /* 178284 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 170(*/0xAA, 0x01/*)*/,
59967 /* 178287 */ GIR_MakeTempReg, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TypeID*/GILLT_s32,
59968 /* 178291 */ GIR_BuildMI, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
59969 /* 178296 */ GIR_AddTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59970 /* 178303 */ GIR_AddSimpleTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/,
59971 /* 178308 */ GIR_AddImm, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
59972 /* 178319 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 169(*/0xA9, 0x01/*)*/,
59973 /* 178322 */ GIR_MakeTempReg, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TypeID*/GILLT_s32,
59974 /* 178326 */ GIR_BuildMI, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59975 /* 178331 */ GIR_AddTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59976 /* 178338 */ GIR_Copy, /*NewInsnID*//* 168(*/0xA8, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
59977 /* 178343 */ GIR_AddImm8, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Imm*/31,
59978 /* 178347 */ GIR_AddImm8, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Imm*/1,
59979 /* 178351 */ GIR_AddImm8, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Imm*/31,
59980 /* 178355 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 168(*/0xA8, 0x01/*)*/,
59981 /* 178358 */ GIR_MakeTempReg, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TypeID*/GILLT_s32,
59982 /* 178362 */ GIR_BuildMI, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
59983 /* 178367 */ GIR_AddTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59984 /* 178374 */ GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/,
59985 /* 178379 */ GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/,
59986 /* 178384 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 167(*/0xA7, 0x01/*)*/,
59987 /* 178387 */ GIR_MakeTempReg, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TypeID*/GILLT_s32,
59988 /* 178391 */ GIR_BuildMI, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
59989 /* 178396 */ GIR_AddTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59990 /* 178403 */ GIR_AddSimpleTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/,
59991 /* 178408 */ GIR_AddSimpleTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/,
59992 /* 178413 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 166(*/0xA6, 0x01/*)*/,
59993 /* 178416 */ GIR_MakeTempReg, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TypeID*/GILLT_s32,
59994 /* 178420 */ GIR_BuildMI, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
59995 /* 178425 */ GIR_AddTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
59996 /* 178432 */ GIR_AddSimpleTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/,
59997 /* 178437 */ GIR_AddImm8, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Imm*/30,
59998 /* 178441 */ GIR_AddImm8, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Imm*/2,
59999 /* 178445 */ GIR_AddImm8, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Imm*/31,
60000 /* 178449 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 165(*/0xA5, 0x01/*)*/,
60001 /* 178452 */ GIR_MakeTempReg, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TypeID*/GILLT_s32,
60002 /* 178456 */ GIR_BuildMI, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60003 /* 178461 */ GIR_AddTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60004 /* 178468 */ GIR_AddSimpleTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/,
60005 /* 178473 */ GIR_AddSimpleTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/,
60006 /* 178478 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 164(*/0xA4, 0x01/*)*/,
60007 /* 178481 */ GIR_MakeTempReg, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TypeID*/GILLT_s32,
60008 /* 178485 */ GIR_BuildMI, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
60009 /* 178490 */ GIR_AddTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60010 /* 178497 */ GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/,
60011 /* 178502 */ GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/,
60012 /* 178507 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 163(*/0xA3, 0x01/*)*/,
60013 /* 178510 */ GIR_MakeTempReg, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TypeID*/GILLT_s32,
60014 /* 178514 */ GIR_BuildMI, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60015 /* 178519 */ GIR_AddTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60016 /* 178526 */ GIR_AddSimpleTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/,
60017 /* 178531 */ GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/4,
60018 /* 178535 */ GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/0,
60019 /* 178539 */ GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/27,
60020 /* 178543 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 162(*/0xA2, 0x01/*)*/,
60021 /* 178546 */ GIR_MakeTempReg, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TypeID*/GILLT_s32,
60022 /* 178550 */ GIR_BuildMI, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60023 /* 178555 */ GIR_AddTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60024 /* 178562 */ GIR_AddSimpleTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/,
60025 /* 178567 */ GIR_AddSimpleTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/,
60026 /* 178572 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 161(*/0xA1, 0x01/*)*/,
60027 /* 178575 */ GIR_MakeTempReg, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TypeID*/GILLT_s32,
60028 /* 178579 */ GIR_BuildMI, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
60029 /* 178584 */ GIR_AddTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60030 /* 178591 */ GIR_AddImm, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855),
60031 /* 178602 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 160(*/0xA0, 0x01/*)*/,
60032 /* 178605 */ GIR_MakeTempReg, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TypeID*/GILLT_s32,
60033 /* 178609 */ GIR_BuildMI, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
60034 /* 178614 */ GIR_AddTempRegister, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60035 /* 178621 */ GIR_AddSimpleTempRegister, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/,
60036 /* 178626 */ GIR_AddImm, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855),
60037 /* 178637 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 159(*/0x9F, 0x01/*)*/,
60038 /* 178640 */ GIR_MakeTempReg, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TypeID*/GILLT_s32,
60039 /* 178644 */ GIR_BuildMI, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
60040 /* 178649 */ GIR_AddTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60041 /* 178656 */ GIR_AddImm, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
60042 /* 178667 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 158(*/0x9E, 0x01/*)*/,
60043 /* 178670 */ GIR_MakeTempReg, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TypeID*/GILLT_s32,
60044 /* 178674 */ GIR_BuildMI, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
60045 /* 178679 */ GIR_AddTempRegister, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60046 /* 178686 */ GIR_AddSimpleTempRegister, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/,
60047 /* 178691 */ GIR_AddImm, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
60048 /* 178702 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 157(*/0x9D, 0x01/*)*/,
60049 /* 178705 */ GIR_MakeTempReg, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TypeID*/GILLT_s32,
60050 /* 178709 */ GIR_BuildMI, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
60051 /* 178714 */ GIR_AddTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60052 /* 178721 */ GIR_AddImm, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
60053 /* 178732 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 156(*/0x9C, 0x01/*)*/,
60054 /* 178735 */ GIR_MakeTempReg, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TypeID*/GILLT_s32,
60055 /* 178739 */ GIR_BuildMI, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
60056 /* 178744 */ GIR_AddTempRegister, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60057 /* 178751 */ GIR_AddSimpleTempRegister, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/,
60058 /* 178756 */ GIR_AddImm, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
60059 /* 178767 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 155(*/0x9B, 0x01/*)*/,
60060 /* 178770 */ GIR_MakeTempReg, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TypeID*/GILLT_s32,
60061 /* 178774 */ GIR_BuildMI, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60062 /* 178779 */ GIR_AddTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60063 /* 178786 */ GIR_Copy, /*NewInsnID*//* 154(*/0x9A, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
60064 /* 178791 */ GIR_AddImm8, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Imm*/1,
60065 /* 178795 */ GIR_AddImm8, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Imm*/0,
60066 /* 178799 */ GIR_AddImm8, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Imm*/30,
60067 /* 178803 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 154(*/0x9A, 0x01/*)*/,
60068 /* 178806 */ GIR_MakeTempReg, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TypeID*/GILLT_s32,
60069 /* 178810 */ GIR_BuildMI, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60070 /* 178815 */ GIR_AddTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60071 /* 178822 */ GIR_AddSimpleTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/,
60072 /* 178827 */ GIR_AddSimpleTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/,
60073 /* 178832 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 153(*/0x99, 0x01/*)*/,
60074 /* 178835 */ GIR_MakeTempReg, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TypeID*/GILLT_s32,
60075 /* 178839 */ GIR_BuildMI, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
60076 /* 178844 */ GIR_AddTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60077 /* 178851 */ GIR_AddImm, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
60078 /* 178862 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 152(*/0x98, 0x01/*)*/,
60079 /* 178865 */ GIR_MakeTempReg, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TypeID*/GILLT_s32,
60080 /* 178869 */ GIR_BuildMI, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
60081 /* 178874 */ GIR_AddTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60082 /* 178881 */ GIR_AddSimpleTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/,
60083 /* 178886 */ GIR_AddImm, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
60084 /* 178897 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 151(*/0x97, 0x01/*)*/,
60085 /* 178900 */ GIR_MakeTempReg, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TypeID*/GILLT_s32,
60086 /* 178904 */ GIR_BuildMI, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60087 /* 178909 */ GIR_AddTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60088 /* 178916 */ GIR_Copy, /*NewInsnID*//* 150(*/0x96, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
60089 /* 178921 */ GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/31,
60090 /* 178925 */ GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/1,
60091 /* 178929 */ GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/31,
60092 /* 178933 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 150(*/0x96, 0x01/*)*/,
60093 /* 178936 */ GIR_MakeTempReg, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TypeID*/GILLT_s32,
60094 /* 178940 */ GIR_BuildMI, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60095 /* 178945 */ GIR_AddTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60096 /* 178952 */ GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/,
60097 /* 178957 */ GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/,
60098 /* 178962 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 149(*/0x95, 0x01/*)*/,
60099 /* 178965 */ GIR_MakeTempReg, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TypeID*/GILLT_s32,
60100 /* 178969 */ GIR_BuildMI, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
60101 /* 178974 */ GIR_AddTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60102 /* 178981 */ GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/,
60103 /* 178986 */ GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/,
60104 /* 178991 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 148(*/0x94, 0x01/*)*/,
60105 /* 178994 */ GIR_MakeTempReg, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TypeID*/GILLT_s32,
60106 /* 178998 */ GIR_BuildMI, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60107 /* 179003 */ GIR_AddTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60108 /* 179010 */ GIR_AddSimpleTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/,
60109 /* 179015 */ GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/2,
60110 /* 179019 */ GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/0,
60111 /* 179023 */ GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/29,
60112 /* 179027 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 147(*/0x93, 0x01/*)*/,
60113 /* 179030 */ GIR_MakeTempReg, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TypeID*/GILLT_s32,
60114 /* 179034 */ GIR_BuildMI, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60115 /* 179039 */ GIR_AddTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60116 /* 179046 */ GIR_AddSimpleTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/,
60117 /* 179051 */ GIR_AddSimpleTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/,
60118 /* 179056 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 146(*/0x92, 0x01/*)*/,
60119 /* 179059 */ GIR_MakeTempReg, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TypeID*/GILLT_s32,
60120 /* 179063 */ GIR_BuildMI, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
60121 /* 179068 */ GIR_AddTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60122 /* 179075 */ GIR_AddImm, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
60123 /* 179086 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 145(*/0x91, 0x01/*)*/,
60124 /* 179089 */ GIR_MakeTempReg, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TypeID*/GILLT_s32,
60125 /* 179093 */ GIR_BuildMI, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
60126 /* 179098 */ GIR_AddTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60127 /* 179105 */ GIR_AddSimpleTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/,
60128 /* 179110 */ GIR_AddImm, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
60129 /* 179121 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 144(*/0x90, 0x01/*)*/,
60130 /* 179124 */ GIR_MakeTempReg, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TypeID*/GILLT_s32,
60131 /* 179128 */ GIR_BuildMI, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
60132 /* 179133 */ GIR_AddTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60133 /* 179140 */ GIR_AddImm, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
60134 /* 179151 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 143(*/0x8F, 0x01/*)*/,
60135 /* 179154 */ GIR_MakeTempReg, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TypeID*/GILLT_s32,
60136 /* 179158 */ GIR_BuildMI, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
60137 /* 179163 */ GIR_AddTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60138 /* 179170 */ GIR_AddSimpleTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/,
60139 /* 179175 */ GIR_AddImm, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
60140 /* 179186 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 142(*/0x8E, 0x01/*)*/,
60141 /* 179189 */ GIR_MakeTempReg, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TypeID*/GILLT_s32,
60142 /* 179193 */ GIR_BuildMI, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60143 /* 179198 */ GIR_AddTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60144 /* 179205 */ GIR_Copy, /*NewInsnID*//* 141(*/0x8D, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
60145 /* 179210 */ GIR_AddImm8, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Imm*/1,
60146 /* 179214 */ GIR_AddImm8, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Imm*/0,
60147 /* 179218 */ GIR_AddImm8, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Imm*/30,
60148 /* 179222 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 141(*/0x8D, 0x01/*)*/,
60149 /* 179225 */ GIR_MakeTempReg, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TypeID*/GILLT_s32,
60150 /* 179229 */ GIR_BuildMI, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60151 /* 179234 */ GIR_AddTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60152 /* 179241 */ GIR_AddSimpleTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/,
60153 /* 179246 */ GIR_AddSimpleTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/,
60154 /* 179251 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 140(*/0x8C, 0x01/*)*/,
60155 /* 179254 */ GIR_MakeTempReg, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TypeID*/GILLT_s32,
60156 /* 179258 */ GIR_BuildMI, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
60157 /* 179263 */ GIR_AddTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60158 /* 179270 */ GIR_AddImm, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
60159 /* 179281 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 139(*/0x8B, 0x01/*)*/,
60160 /* 179284 */ GIR_MakeTempReg, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TypeID*/GILLT_s32,
60161 /* 179288 */ GIR_BuildMI, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
60162 /* 179293 */ GIR_AddTempRegister, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60163 /* 179300 */ GIR_AddSimpleTempRegister, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/,
60164 /* 179305 */ GIR_AddImm, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
60165 /* 179316 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 138(*/0x8A, 0x01/*)*/,
60166 /* 179319 */ GIR_MakeTempReg, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TypeID*/GILLT_s32,
60167 /* 179323 */ GIR_BuildMI, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60168 /* 179328 */ GIR_AddTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60169 /* 179335 */ GIR_Copy, /*NewInsnID*//* 137(*/0x89, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
60170 /* 179340 */ GIR_AddImm8, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Imm*/31,
60171 /* 179344 */ GIR_AddImm8, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Imm*/1,
60172 /* 179348 */ GIR_AddImm8, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Imm*/31,
60173 /* 179352 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 137(*/0x89, 0x01/*)*/,
60174 /* 179355 */ GIR_MakeTempReg, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TypeID*/GILLT_s32,
60175 /* 179359 */ GIR_BuildMI, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60176 /* 179364 */ GIR_AddTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60177 /* 179371 */ GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/,
60178 /* 179376 */ GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/,
60179 /* 179381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 136(*/0x88, 0x01/*)*/,
60180 /* 179384 */ GIR_MakeTempReg, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TypeID*/GILLT_s32,
60181 /* 179388 */ GIR_BuildMI, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
60182 /* 179393 */ GIR_AddTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60183 /* 179400 */ GIR_AddSimpleTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/,
60184 /* 179405 */ GIR_AddSimpleTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/,
60185 /* 179410 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 135(*/0x87, 0x01/*)*/,
60186 /* 179413 */ GIR_MakeTempReg, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TypeID*/GILLT_s32,
60187 /* 179417 */ GIR_BuildMI, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60188 /* 179422 */ GIR_AddTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60189 /* 179429 */ GIR_AddSimpleTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/,
60190 /* 179434 */ GIR_AddImm8, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Imm*/30,
60191 /* 179438 */ GIR_AddImm8, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Imm*/2,
60192 /* 179442 */ GIR_AddImm8, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Imm*/31,
60193 /* 179446 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 134(*/0x86, 0x01/*)*/,
60194 /* 179449 */ GIR_MakeTempReg, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TypeID*/GILLT_s32,
60195 /* 179453 */ GIR_BuildMI, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60196 /* 179458 */ GIR_AddTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60197 /* 179465 */ GIR_AddSimpleTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/,
60198 /* 179470 */ GIR_AddSimpleTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/,
60199 /* 179475 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 133(*/0x85, 0x01/*)*/,
60200 /* 179478 */ GIR_MakeTempReg, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TypeID*/GILLT_s32,
60201 /* 179482 */ GIR_BuildMI, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
60202 /* 179487 */ GIR_AddTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60203 /* 179494 */ GIR_AddSimpleTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/,
60204 /* 179499 */ GIR_AddSimpleTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/,
60205 /* 179504 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 132(*/0x84, 0x01/*)*/,
60206 /* 179507 */ GIR_MakeTempReg, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TypeID*/GILLT_s32,
60207 /* 179511 */ GIR_BuildMI, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60208 /* 179516 */ GIR_AddTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60209 /* 179523 */ GIR_AddSimpleTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/,
60210 /* 179528 */ GIR_AddImm8, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Imm*/28,
60211 /* 179532 */ GIR_AddImm8, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Imm*/4,
60212 /* 179536 */ GIR_AddImm8, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Imm*/31,
60213 /* 179540 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 131(*/0x83, 0x01/*)*/,
60214 /* 179543 */ GIR_MakeTempReg, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TypeID*/GILLT_s32,
60215 /* 179547 */ GIR_BuildMI, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND),
60216 /* 179552 */ GIR_AddTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60217 /* 179559 */ GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/,
60218 /* 179564 */ GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/,
60219 /* 179569 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 130(*/0x82, 0x01/*)*/,
60220 /* 179572 */ GIR_MakeTempReg, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TypeID*/GILLT_s32,
60221 /* 179576 */ GIR_BuildMI, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR),
60222 /* 179581 */ GIR_AddTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60223 /* 179588 */ GIR_AddSimpleTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/,
60224 /* 179593 */ GIR_AddSimpleTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/,
60225 /* 179598 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 129(*/0x81, 0x01/*)*/,
60226 /* 179601 */ GIR_MakeTempReg, /*TempRegID*/127, /*TypeID*/GILLT_s32,
60227 /* 179604 */ GIR_BuildMI, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
60228 /* 179609 */ GIR_AddTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*/127, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60229 /* 179615 */ GIR_AddImm, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
60230 /* 179626 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 128(*/0x80, 0x01/*)*/,
60231 /* 179629 */ GIR_MakeTempReg, /*TempRegID*/126, /*TypeID*/GILLT_s32,
60232 /* 179632 */ GIR_BuildMI, /*InsnID*/127, /*Opcode*/GIMT_Encode2(PPC::ORI),
60233 /* 179636 */ GIR_AddTempRegister, /*InsnID*/127, /*TempRegID*/126, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60234 /* 179641 */ GIR_AddSimpleTempRegister, /*InsnID*/127, /*TempRegID*/127,
60235 /* 179644 */ GIR_AddImm, /*InsnID*/127, /*Imm*/GIMT_Encode8(61680),
60236 /* 179654 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/127,
60237 /* 179656 */ GIR_MakeTempReg, /*TempRegID*/125, /*TypeID*/GILLT_s32,
60238 /* 179659 */ GIR_BuildMI, /*InsnID*/126, /*Opcode*/GIMT_Encode2(PPC::LIS),
60239 /* 179663 */ GIR_AddTempRegister, /*InsnID*/126, /*TempRegID*/125, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60240 /* 179668 */ GIR_AddImm, /*InsnID*/126, /*Imm*/GIMT_Encode8(52428),
60241 /* 179678 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/126,
60242 /* 179680 */ GIR_MakeTempReg, /*TempRegID*/124, /*TypeID*/GILLT_s32,
60243 /* 179683 */ GIR_BuildMI, /*InsnID*/125, /*Opcode*/GIMT_Encode2(PPC::ORI),
60244 /* 179687 */ GIR_AddTempRegister, /*InsnID*/125, /*TempRegID*/124, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60245 /* 179692 */ GIR_AddSimpleTempRegister, /*InsnID*/125, /*TempRegID*/125,
60246 /* 179695 */ GIR_AddImm, /*InsnID*/125, /*Imm*/GIMT_Encode8(52428),
60247 /* 179705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/125,
60248 /* 179707 */ GIR_MakeTempReg, /*TempRegID*/123, /*TypeID*/GILLT_s32,
60249 /* 179710 */ GIR_BuildMI, /*InsnID*/124, /*Opcode*/GIMT_Encode2(PPC::LIS),
60250 /* 179714 */ GIR_AddTempRegister, /*InsnID*/124, /*TempRegID*/123, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60251 /* 179719 */ GIR_AddImm, /*InsnID*/124, /*Imm*/GIMT_Encode8(43690),
60252 /* 179729 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/124,
60253 /* 179731 */ GIR_MakeTempReg, /*TempRegID*/122, /*TypeID*/GILLT_s32,
60254 /* 179734 */ GIR_BuildMI, /*InsnID*/123, /*Opcode*/GIMT_Encode2(PPC::ORI),
60255 /* 179738 */ GIR_AddTempRegister, /*InsnID*/123, /*TempRegID*/122, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60256 /* 179743 */ GIR_AddSimpleTempRegister, /*InsnID*/123, /*TempRegID*/123,
60257 /* 179746 */ GIR_AddImm, /*InsnID*/123, /*Imm*/GIMT_Encode8(43690),
60258 /* 179756 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/123,
60259 /* 179758 */ GIR_MakeTempReg, /*TempRegID*/121, /*TypeID*/GILLT_s32,
60260 /* 179761 */ GIR_BuildMI, /*InsnID*/122, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60261 /* 179765 */ GIR_AddTempRegister, /*InsnID*/122, /*TempRegID*/121, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60262 /* 179770 */ GIR_Copy, /*NewInsnID*/122, /*OldInsnID*/0, /*OpIdx*/1, // A
60263 /* 179774 */ GIR_AddImm8, /*InsnID*/122, /*Imm*/1,
60264 /* 179777 */ GIR_AddImm8, /*InsnID*/122, /*Imm*/0,
60265 /* 179780 */ GIR_AddImm8, /*InsnID*/122, /*Imm*/30,
60266 /* 179783 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/122,
60267 /* 179785 */ GIR_MakeTempReg, /*TempRegID*/120, /*TypeID*/GILLT_s32,
60268 /* 179788 */ GIR_BuildMI, /*InsnID*/121, /*Opcode*/GIMT_Encode2(PPC::AND),
60269 /* 179792 */ GIR_AddTempRegister, /*InsnID*/121, /*TempRegID*/120, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60270 /* 179797 */ GIR_AddSimpleTempRegister, /*InsnID*/121, /*TempRegID*/121,
60271 /* 179800 */ GIR_AddSimpleTempRegister, /*InsnID*/121, /*TempRegID*/122,
60272 /* 179803 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/121,
60273 /* 179805 */ GIR_MakeTempReg, /*TempRegID*/119, /*TypeID*/GILLT_s32,
60274 /* 179808 */ GIR_BuildMI, /*InsnID*/120, /*Opcode*/GIMT_Encode2(PPC::LIS),
60275 /* 179812 */ GIR_AddTempRegister, /*InsnID*/120, /*TempRegID*/119, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60276 /* 179817 */ GIR_AddImm, /*InsnID*/120, /*Imm*/GIMT_Encode8(21845),
60277 /* 179827 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/120,
60278 /* 179829 */ GIR_MakeTempReg, /*TempRegID*/118, /*TypeID*/GILLT_s32,
60279 /* 179832 */ GIR_BuildMI, /*InsnID*/119, /*Opcode*/GIMT_Encode2(PPC::ORI),
60280 /* 179836 */ GIR_AddTempRegister, /*InsnID*/119, /*TempRegID*/118, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60281 /* 179841 */ GIR_AddSimpleTempRegister, /*InsnID*/119, /*TempRegID*/119,
60282 /* 179844 */ GIR_AddImm, /*InsnID*/119, /*Imm*/GIMT_Encode8(21845),
60283 /* 179854 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/119,
60284 /* 179856 */ GIR_MakeTempReg, /*TempRegID*/117, /*TypeID*/GILLT_s32,
60285 /* 179859 */ GIR_BuildMI, /*InsnID*/118, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60286 /* 179863 */ GIR_AddTempRegister, /*InsnID*/118, /*TempRegID*/117, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60287 /* 179868 */ GIR_Copy, /*NewInsnID*/118, /*OldInsnID*/0, /*OpIdx*/1, // A
60288 /* 179872 */ GIR_AddImm8, /*InsnID*/118, /*Imm*/31,
60289 /* 179875 */ GIR_AddImm8, /*InsnID*/118, /*Imm*/1,
60290 /* 179878 */ GIR_AddImm8, /*InsnID*/118, /*Imm*/31,
60291 /* 179881 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/118,
60292 /* 179883 */ GIR_MakeTempReg, /*TempRegID*/116, /*TypeID*/GILLT_s32,
60293 /* 179886 */ GIR_BuildMI, /*InsnID*/117, /*Opcode*/GIMT_Encode2(PPC::AND),
60294 /* 179890 */ GIR_AddTempRegister, /*InsnID*/117, /*TempRegID*/116, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60295 /* 179895 */ GIR_AddSimpleTempRegister, /*InsnID*/117, /*TempRegID*/117,
60296 /* 179898 */ GIR_AddSimpleTempRegister, /*InsnID*/117, /*TempRegID*/118,
60297 /* 179901 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/117,
60298 /* 179903 */ GIR_MakeTempReg, /*TempRegID*/115, /*TypeID*/GILLT_s32,
60299 /* 179906 */ GIR_BuildMI, /*InsnID*/116, /*Opcode*/GIMT_Encode2(PPC::OR),
60300 /* 179910 */ GIR_AddTempRegister, /*InsnID*/116, /*TempRegID*/115, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60301 /* 179915 */ GIR_AddSimpleTempRegister, /*InsnID*/116, /*TempRegID*/116,
60302 /* 179918 */ GIR_AddSimpleTempRegister, /*InsnID*/116, /*TempRegID*/120,
60303 /* 179921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/116,
60304 /* 179923 */ GIR_MakeTempReg, /*TempRegID*/114, /*TypeID*/GILLT_s32,
60305 /* 179926 */ GIR_BuildMI, /*InsnID*/115, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60306 /* 179930 */ GIR_AddTempRegister, /*InsnID*/115, /*TempRegID*/114, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60307 /* 179935 */ GIR_AddSimpleTempRegister, /*InsnID*/115, /*TempRegID*/115,
60308 /* 179938 */ GIR_AddImm8, /*InsnID*/115, /*Imm*/2,
60309 /* 179941 */ GIR_AddImm8, /*InsnID*/115, /*Imm*/0,
60310 /* 179944 */ GIR_AddImm8, /*InsnID*/115, /*Imm*/29,
60311 /* 179947 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/115,
60312 /* 179949 */ GIR_MakeTempReg, /*TempRegID*/113, /*TypeID*/GILLT_s32,
60313 /* 179952 */ GIR_BuildMI, /*InsnID*/114, /*Opcode*/GIMT_Encode2(PPC::AND),
60314 /* 179956 */ GIR_AddTempRegister, /*InsnID*/114, /*TempRegID*/113, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60315 /* 179961 */ GIR_AddSimpleTempRegister, /*InsnID*/114, /*TempRegID*/114,
60316 /* 179964 */ GIR_AddSimpleTempRegister, /*InsnID*/114, /*TempRegID*/124,
60317 /* 179967 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/114,
60318 /* 179969 */ GIR_MakeTempReg, /*TempRegID*/112, /*TypeID*/GILLT_s32,
60319 /* 179972 */ GIR_BuildMI, /*InsnID*/113, /*Opcode*/GIMT_Encode2(PPC::LIS),
60320 /* 179976 */ GIR_AddTempRegister, /*InsnID*/113, /*TempRegID*/112, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60321 /* 179981 */ GIR_AddImm, /*InsnID*/113, /*Imm*/GIMT_Encode8(13107),
60322 /* 179991 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/113,
60323 /* 179993 */ GIR_MakeTempReg, /*TempRegID*/111, /*TypeID*/GILLT_s32,
60324 /* 179996 */ GIR_BuildMI, /*InsnID*/112, /*Opcode*/GIMT_Encode2(PPC::ORI),
60325 /* 180000 */ GIR_AddTempRegister, /*InsnID*/112, /*TempRegID*/111, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60326 /* 180005 */ GIR_AddSimpleTempRegister, /*InsnID*/112, /*TempRegID*/112,
60327 /* 180008 */ GIR_AddImm, /*InsnID*/112, /*Imm*/GIMT_Encode8(13107),
60328 /* 180018 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/112,
60329 /* 180020 */ GIR_MakeTempReg, /*TempRegID*/110, /*TypeID*/GILLT_s32,
60330 /* 180023 */ GIR_BuildMI, /*InsnID*/111, /*Opcode*/GIMT_Encode2(PPC::LIS),
60331 /* 180027 */ GIR_AddTempRegister, /*InsnID*/111, /*TempRegID*/110, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60332 /* 180032 */ GIR_AddImm, /*InsnID*/111, /*Imm*/GIMT_Encode8(43690),
60333 /* 180042 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/111,
60334 /* 180044 */ GIR_MakeTempReg, /*TempRegID*/109, /*TypeID*/GILLT_s32,
60335 /* 180047 */ GIR_BuildMI, /*InsnID*/110, /*Opcode*/GIMT_Encode2(PPC::ORI),
60336 /* 180051 */ GIR_AddTempRegister, /*InsnID*/110, /*TempRegID*/109, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60337 /* 180056 */ GIR_AddSimpleTempRegister, /*InsnID*/110, /*TempRegID*/110,
60338 /* 180059 */ GIR_AddImm, /*InsnID*/110, /*Imm*/GIMT_Encode8(43690),
60339 /* 180069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/110,
60340 /* 180071 */ GIR_MakeTempReg, /*TempRegID*/108, /*TypeID*/GILLT_s32,
60341 /* 180074 */ GIR_BuildMI, /*InsnID*/109, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60342 /* 180078 */ GIR_AddTempRegister, /*InsnID*/109, /*TempRegID*/108, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60343 /* 180083 */ GIR_Copy, /*NewInsnID*/109, /*OldInsnID*/0, /*OpIdx*/1, // A
60344 /* 180087 */ GIR_AddImm8, /*InsnID*/109, /*Imm*/1,
60345 /* 180090 */ GIR_AddImm8, /*InsnID*/109, /*Imm*/0,
60346 /* 180093 */ GIR_AddImm8, /*InsnID*/109, /*Imm*/30,
60347 /* 180096 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/109,
60348 /* 180098 */ GIR_MakeTempReg, /*TempRegID*/107, /*TypeID*/GILLT_s32,
60349 /* 180101 */ GIR_BuildMI, /*InsnID*/108, /*Opcode*/GIMT_Encode2(PPC::AND),
60350 /* 180105 */ GIR_AddTempRegister, /*InsnID*/108, /*TempRegID*/107, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60351 /* 180110 */ GIR_AddSimpleTempRegister, /*InsnID*/108, /*TempRegID*/108,
60352 /* 180113 */ GIR_AddSimpleTempRegister, /*InsnID*/108, /*TempRegID*/109,
60353 /* 180116 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/108,
60354 /* 180118 */ GIR_MakeTempReg, /*TempRegID*/106, /*TypeID*/GILLT_s32,
60355 /* 180121 */ GIR_BuildMI, /*InsnID*/107, /*Opcode*/GIMT_Encode2(PPC::LIS),
60356 /* 180125 */ GIR_AddTempRegister, /*InsnID*/107, /*TempRegID*/106, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60357 /* 180130 */ GIR_AddImm, /*InsnID*/107, /*Imm*/GIMT_Encode8(21845),
60358 /* 180140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/107,
60359 /* 180142 */ GIR_MakeTempReg, /*TempRegID*/105, /*TypeID*/GILLT_s32,
60360 /* 180145 */ GIR_BuildMI, /*InsnID*/106, /*Opcode*/GIMT_Encode2(PPC::ORI),
60361 /* 180149 */ GIR_AddTempRegister, /*InsnID*/106, /*TempRegID*/105, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60362 /* 180154 */ GIR_AddSimpleTempRegister, /*InsnID*/106, /*TempRegID*/106,
60363 /* 180157 */ GIR_AddImm, /*InsnID*/106, /*Imm*/GIMT_Encode8(21845),
60364 /* 180167 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/106,
60365 /* 180169 */ GIR_MakeTempReg, /*TempRegID*/104, /*TypeID*/GILLT_s32,
60366 /* 180172 */ GIR_BuildMI, /*InsnID*/105, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60367 /* 180176 */ GIR_AddTempRegister, /*InsnID*/105, /*TempRegID*/104, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60368 /* 180181 */ GIR_Copy, /*NewInsnID*/105, /*OldInsnID*/0, /*OpIdx*/1, // A
60369 /* 180185 */ GIR_AddImm8, /*InsnID*/105, /*Imm*/31,
60370 /* 180188 */ GIR_AddImm8, /*InsnID*/105, /*Imm*/1,
60371 /* 180191 */ GIR_AddImm8, /*InsnID*/105, /*Imm*/31,
60372 /* 180194 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/105,
60373 /* 180196 */ GIR_MakeTempReg, /*TempRegID*/103, /*TypeID*/GILLT_s32,
60374 /* 180199 */ GIR_BuildMI, /*InsnID*/104, /*Opcode*/GIMT_Encode2(PPC::AND),
60375 /* 180203 */ GIR_AddTempRegister, /*InsnID*/104, /*TempRegID*/103, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60376 /* 180208 */ GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/104,
60377 /* 180211 */ GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/105,
60378 /* 180214 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/104,
60379 /* 180216 */ GIR_MakeTempReg, /*TempRegID*/102, /*TypeID*/GILLT_s32,
60380 /* 180219 */ GIR_BuildMI, /*InsnID*/103, /*Opcode*/GIMT_Encode2(PPC::OR),
60381 /* 180223 */ GIR_AddTempRegister, /*InsnID*/103, /*TempRegID*/102, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60382 /* 180228 */ GIR_AddSimpleTempRegister, /*InsnID*/103, /*TempRegID*/103,
60383 /* 180231 */ GIR_AddSimpleTempRegister, /*InsnID*/103, /*TempRegID*/107,
60384 /* 180234 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/103,
60385 /* 180236 */ GIR_MakeTempReg, /*TempRegID*/101, /*TypeID*/GILLT_s32,
60386 /* 180239 */ GIR_BuildMI, /*InsnID*/102, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60387 /* 180243 */ GIR_AddTempRegister, /*InsnID*/102, /*TempRegID*/101, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60388 /* 180248 */ GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/102,
60389 /* 180251 */ GIR_AddImm8, /*InsnID*/102, /*Imm*/30,
60390 /* 180254 */ GIR_AddImm8, /*InsnID*/102, /*Imm*/2,
60391 /* 180257 */ GIR_AddImm8, /*InsnID*/102, /*Imm*/31,
60392 /* 180260 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/102,
60393 /* 180262 */ GIR_MakeTempReg, /*TempRegID*/100, /*TypeID*/GILLT_s32,
60394 /* 180265 */ GIR_BuildMI, /*InsnID*/101, /*Opcode*/GIMT_Encode2(PPC::AND),
60395 /* 180269 */ GIR_AddTempRegister, /*InsnID*/101, /*TempRegID*/100, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60396 /* 180274 */ GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/101,
60397 /* 180277 */ GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/111,
60398 /* 180280 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/101,
60399 /* 180282 */ GIR_MakeTempReg, /*TempRegID*/99, /*TypeID*/GILLT_s32,
60400 /* 180285 */ GIR_BuildMI, /*InsnID*/100, /*Opcode*/GIMT_Encode2(PPC::OR),
60401 /* 180289 */ GIR_AddTempRegister, /*InsnID*/100, /*TempRegID*/99, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60402 /* 180294 */ GIR_AddSimpleTempRegister, /*InsnID*/100, /*TempRegID*/100,
60403 /* 180297 */ GIR_AddSimpleTempRegister, /*InsnID*/100, /*TempRegID*/113,
60404 /* 180300 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/100,
60405 /* 180302 */ GIR_MakeTempReg, /*TempRegID*/98, /*TypeID*/GILLT_s32,
60406 /* 180305 */ GIR_BuildMI, /*InsnID*/99, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60407 /* 180309 */ GIR_AddTempRegister, /*InsnID*/99, /*TempRegID*/98, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60408 /* 180314 */ GIR_AddSimpleTempRegister, /*InsnID*/99, /*TempRegID*/99,
60409 /* 180317 */ GIR_AddImm8, /*InsnID*/99, /*Imm*/4,
60410 /* 180320 */ GIR_AddImm8, /*InsnID*/99, /*Imm*/0,
60411 /* 180323 */ GIR_AddImm8, /*InsnID*/99, /*Imm*/27,
60412 /* 180326 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/99,
60413 /* 180328 */ GIR_MakeTempReg, /*TempRegID*/97, /*TypeID*/GILLT_s32,
60414 /* 180331 */ GIR_BuildMI, /*InsnID*/98, /*Opcode*/GIMT_Encode2(PPC::AND),
60415 /* 180335 */ GIR_AddTempRegister, /*InsnID*/98, /*TempRegID*/97, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60416 /* 180340 */ GIR_AddSimpleTempRegister, /*InsnID*/98, /*TempRegID*/98,
60417 /* 180343 */ GIR_AddSimpleTempRegister, /*InsnID*/98, /*TempRegID*/126,
60418 /* 180346 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/98,
60419 /* 180348 */ GIR_MakeTempReg, /*TempRegID*/96, /*TypeID*/GILLT_s32,
60420 /* 180351 */ GIR_BuildMI, /*InsnID*/97, /*Opcode*/GIMT_Encode2(PPC::LIS),
60421 /* 180355 */ GIR_AddTempRegister, /*InsnID*/97, /*TempRegID*/96, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60422 /* 180360 */ GIR_AddImm, /*InsnID*/97, /*Imm*/GIMT_Encode8(3855),
60423 /* 180370 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/97,
60424 /* 180372 */ GIR_MakeTempReg, /*TempRegID*/95, /*TypeID*/GILLT_s32,
60425 /* 180375 */ GIR_BuildMI, /*InsnID*/96, /*Opcode*/GIMT_Encode2(PPC::ORI),
60426 /* 180379 */ GIR_AddTempRegister, /*InsnID*/96, /*TempRegID*/95, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60427 /* 180384 */ GIR_AddSimpleTempRegister, /*InsnID*/96, /*TempRegID*/96,
60428 /* 180387 */ GIR_AddImm, /*InsnID*/96, /*Imm*/GIMT_Encode8(3855),
60429 /* 180397 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/96,
60430 /* 180399 */ GIR_MakeTempReg, /*TempRegID*/94, /*TypeID*/GILLT_s32,
60431 /* 180402 */ GIR_BuildMI, /*InsnID*/95, /*Opcode*/GIMT_Encode2(PPC::LIS),
60432 /* 180406 */ GIR_AddTempRegister, /*InsnID*/95, /*TempRegID*/94, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60433 /* 180411 */ GIR_AddImm, /*InsnID*/95, /*Imm*/GIMT_Encode8(52428),
60434 /* 180421 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/95,
60435 /* 180423 */ GIR_MakeTempReg, /*TempRegID*/93, /*TypeID*/GILLT_s32,
60436 /* 180426 */ GIR_BuildMI, /*InsnID*/94, /*Opcode*/GIMT_Encode2(PPC::ORI),
60437 /* 180430 */ GIR_AddTempRegister, /*InsnID*/94, /*TempRegID*/93, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60438 /* 180435 */ GIR_AddSimpleTempRegister, /*InsnID*/94, /*TempRegID*/94,
60439 /* 180438 */ GIR_AddImm, /*InsnID*/94, /*Imm*/GIMT_Encode8(52428),
60440 /* 180448 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/94,
60441 /* 180450 */ GIR_MakeTempReg, /*TempRegID*/92, /*TypeID*/GILLT_s32,
60442 /* 180453 */ GIR_BuildMI, /*InsnID*/93, /*Opcode*/GIMT_Encode2(PPC::LIS),
60443 /* 180457 */ GIR_AddTempRegister, /*InsnID*/93, /*TempRegID*/92, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60444 /* 180462 */ GIR_AddImm, /*InsnID*/93, /*Imm*/GIMT_Encode8(43690),
60445 /* 180472 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/93,
60446 /* 180474 */ GIR_MakeTempReg, /*TempRegID*/91, /*TypeID*/GILLT_s32,
60447 /* 180477 */ GIR_BuildMI, /*InsnID*/92, /*Opcode*/GIMT_Encode2(PPC::ORI),
60448 /* 180481 */ GIR_AddTempRegister, /*InsnID*/92, /*TempRegID*/91, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60449 /* 180486 */ GIR_AddSimpleTempRegister, /*InsnID*/92, /*TempRegID*/92,
60450 /* 180489 */ GIR_AddImm, /*InsnID*/92, /*Imm*/GIMT_Encode8(43690),
60451 /* 180499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/92,
60452 /* 180501 */ GIR_MakeTempReg, /*TempRegID*/90, /*TypeID*/GILLT_s32,
60453 /* 180504 */ GIR_BuildMI, /*InsnID*/91, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60454 /* 180508 */ GIR_AddTempRegister, /*InsnID*/91, /*TempRegID*/90, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60455 /* 180513 */ GIR_Copy, /*NewInsnID*/91, /*OldInsnID*/0, /*OpIdx*/1, // A
60456 /* 180517 */ GIR_AddImm8, /*InsnID*/91, /*Imm*/1,
60457 /* 180520 */ GIR_AddImm8, /*InsnID*/91, /*Imm*/0,
60458 /* 180523 */ GIR_AddImm8, /*InsnID*/91, /*Imm*/30,
60459 /* 180526 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/91,
60460 /* 180528 */ GIR_MakeTempReg, /*TempRegID*/89, /*TypeID*/GILLT_s32,
60461 /* 180531 */ GIR_BuildMI, /*InsnID*/90, /*Opcode*/GIMT_Encode2(PPC::AND),
60462 /* 180535 */ GIR_AddTempRegister, /*InsnID*/90, /*TempRegID*/89, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60463 /* 180540 */ GIR_AddSimpleTempRegister, /*InsnID*/90, /*TempRegID*/90,
60464 /* 180543 */ GIR_AddSimpleTempRegister, /*InsnID*/90, /*TempRegID*/91,
60465 /* 180546 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/90,
60466 /* 180548 */ GIR_MakeTempReg, /*TempRegID*/88, /*TypeID*/GILLT_s32,
60467 /* 180551 */ GIR_BuildMI, /*InsnID*/89, /*Opcode*/GIMT_Encode2(PPC::LIS),
60468 /* 180555 */ GIR_AddTempRegister, /*InsnID*/89, /*TempRegID*/88, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60469 /* 180560 */ GIR_AddImm, /*InsnID*/89, /*Imm*/GIMT_Encode8(21845),
60470 /* 180570 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/89,
60471 /* 180572 */ GIR_MakeTempReg, /*TempRegID*/87, /*TypeID*/GILLT_s32,
60472 /* 180575 */ GIR_BuildMI, /*InsnID*/88, /*Opcode*/GIMT_Encode2(PPC::ORI),
60473 /* 180579 */ GIR_AddTempRegister, /*InsnID*/88, /*TempRegID*/87, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60474 /* 180584 */ GIR_AddSimpleTempRegister, /*InsnID*/88, /*TempRegID*/88,
60475 /* 180587 */ GIR_AddImm, /*InsnID*/88, /*Imm*/GIMT_Encode8(21845),
60476 /* 180597 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/88,
60477 /* 180599 */ GIR_MakeTempReg, /*TempRegID*/86, /*TypeID*/GILLT_s32,
60478 /* 180602 */ GIR_BuildMI, /*InsnID*/87, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60479 /* 180606 */ GIR_AddTempRegister, /*InsnID*/87, /*TempRegID*/86, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60480 /* 180611 */ GIR_Copy, /*NewInsnID*/87, /*OldInsnID*/0, /*OpIdx*/1, // A
60481 /* 180615 */ GIR_AddImm8, /*InsnID*/87, /*Imm*/31,
60482 /* 180618 */ GIR_AddImm8, /*InsnID*/87, /*Imm*/1,
60483 /* 180621 */ GIR_AddImm8, /*InsnID*/87, /*Imm*/31,
60484 /* 180624 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/87,
60485 /* 180626 */ GIR_MakeTempReg, /*TempRegID*/85, /*TypeID*/GILLT_s32,
60486 /* 180629 */ GIR_BuildMI, /*InsnID*/86, /*Opcode*/GIMT_Encode2(PPC::AND),
60487 /* 180633 */ GIR_AddTempRegister, /*InsnID*/86, /*TempRegID*/85, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60488 /* 180638 */ GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/86,
60489 /* 180641 */ GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/87,
60490 /* 180644 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/86,
60491 /* 180646 */ GIR_MakeTempReg, /*TempRegID*/84, /*TypeID*/GILLT_s32,
60492 /* 180649 */ GIR_BuildMI, /*InsnID*/85, /*Opcode*/GIMT_Encode2(PPC::OR),
60493 /* 180653 */ GIR_AddTempRegister, /*InsnID*/85, /*TempRegID*/84, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60494 /* 180658 */ GIR_AddSimpleTempRegister, /*InsnID*/85, /*TempRegID*/85,
60495 /* 180661 */ GIR_AddSimpleTempRegister, /*InsnID*/85, /*TempRegID*/89,
60496 /* 180664 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/85,
60497 /* 180666 */ GIR_MakeTempReg, /*TempRegID*/83, /*TypeID*/GILLT_s32,
60498 /* 180669 */ GIR_BuildMI, /*InsnID*/84, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60499 /* 180673 */ GIR_AddTempRegister, /*InsnID*/84, /*TempRegID*/83, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60500 /* 180678 */ GIR_AddSimpleTempRegister, /*InsnID*/84, /*TempRegID*/84,
60501 /* 180681 */ GIR_AddImm8, /*InsnID*/84, /*Imm*/2,
60502 /* 180684 */ GIR_AddImm8, /*InsnID*/84, /*Imm*/0,
60503 /* 180687 */ GIR_AddImm8, /*InsnID*/84, /*Imm*/29,
60504 /* 180690 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/84,
60505 /* 180692 */ GIR_MakeTempReg, /*TempRegID*/82, /*TypeID*/GILLT_s32,
60506 /* 180695 */ GIR_BuildMI, /*InsnID*/83, /*Opcode*/GIMT_Encode2(PPC::AND),
60507 /* 180699 */ GIR_AddTempRegister, /*InsnID*/83, /*TempRegID*/82, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60508 /* 180704 */ GIR_AddSimpleTempRegister, /*InsnID*/83, /*TempRegID*/83,
60509 /* 180707 */ GIR_AddSimpleTempRegister, /*InsnID*/83, /*TempRegID*/93,
60510 /* 180710 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/83,
60511 /* 180712 */ GIR_MakeTempReg, /*TempRegID*/81, /*TypeID*/GILLT_s32,
60512 /* 180715 */ GIR_BuildMI, /*InsnID*/82, /*Opcode*/GIMT_Encode2(PPC::LIS),
60513 /* 180719 */ GIR_AddTempRegister, /*InsnID*/82, /*TempRegID*/81, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60514 /* 180724 */ GIR_AddImm, /*InsnID*/82, /*Imm*/GIMT_Encode8(13107),
60515 /* 180734 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/82,
60516 /* 180736 */ GIR_MakeTempReg, /*TempRegID*/80, /*TypeID*/GILLT_s32,
60517 /* 180739 */ GIR_BuildMI, /*InsnID*/81, /*Opcode*/GIMT_Encode2(PPC::ORI),
60518 /* 180743 */ GIR_AddTempRegister, /*InsnID*/81, /*TempRegID*/80, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60519 /* 180748 */ GIR_AddSimpleTempRegister, /*InsnID*/81, /*TempRegID*/81,
60520 /* 180751 */ GIR_AddImm, /*InsnID*/81, /*Imm*/GIMT_Encode8(13107),
60521 /* 180761 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/81,
60522 /* 180763 */ GIR_MakeTempReg, /*TempRegID*/79, /*TypeID*/GILLT_s32,
60523 /* 180766 */ GIR_BuildMI, /*InsnID*/80, /*Opcode*/GIMT_Encode2(PPC::LIS),
60524 /* 180770 */ GIR_AddTempRegister, /*InsnID*/80, /*TempRegID*/79, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60525 /* 180775 */ GIR_AddImm, /*InsnID*/80, /*Imm*/GIMT_Encode8(43690),
60526 /* 180785 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/80,
60527 /* 180787 */ GIR_MakeTempReg, /*TempRegID*/78, /*TypeID*/GILLT_s32,
60528 /* 180790 */ GIR_BuildMI, /*InsnID*/79, /*Opcode*/GIMT_Encode2(PPC::ORI),
60529 /* 180794 */ GIR_AddTempRegister, /*InsnID*/79, /*TempRegID*/78, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60530 /* 180799 */ GIR_AddSimpleTempRegister, /*InsnID*/79, /*TempRegID*/79,
60531 /* 180802 */ GIR_AddImm, /*InsnID*/79, /*Imm*/GIMT_Encode8(43690),
60532 /* 180812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/79,
60533 /* 180814 */ GIR_MakeTempReg, /*TempRegID*/77, /*TypeID*/GILLT_s32,
60534 /* 180817 */ GIR_BuildMI, /*InsnID*/78, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60535 /* 180821 */ GIR_AddTempRegister, /*InsnID*/78, /*TempRegID*/77, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60536 /* 180826 */ GIR_Copy, /*NewInsnID*/78, /*OldInsnID*/0, /*OpIdx*/1, // A
60537 /* 180830 */ GIR_AddImm8, /*InsnID*/78, /*Imm*/1,
60538 /* 180833 */ GIR_AddImm8, /*InsnID*/78, /*Imm*/0,
60539 /* 180836 */ GIR_AddImm8, /*InsnID*/78, /*Imm*/30,
60540 /* 180839 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/78,
60541 /* 180841 */ GIR_MakeTempReg, /*TempRegID*/76, /*TypeID*/GILLT_s32,
60542 /* 180844 */ GIR_BuildMI, /*InsnID*/77, /*Opcode*/GIMT_Encode2(PPC::AND),
60543 /* 180848 */ GIR_AddTempRegister, /*InsnID*/77, /*TempRegID*/76, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60544 /* 180853 */ GIR_AddSimpleTempRegister, /*InsnID*/77, /*TempRegID*/77,
60545 /* 180856 */ GIR_AddSimpleTempRegister, /*InsnID*/77, /*TempRegID*/78,
60546 /* 180859 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/77,
60547 /* 180861 */ GIR_MakeTempReg, /*TempRegID*/75, /*TypeID*/GILLT_s32,
60548 /* 180864 */ GIR_BuildMI, /*InsnID*/76, /*Opcode*/GIMT_Encode2(PPC::LIS),
60549 /* 180868 */ GIR_AddTempRegister, /*InsnID*/76, /*TempRegID*/75, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60550 /* 180873 */ GIR_AddImm, /*InsnID*/76, /*Imm*/GIMT_Encode8(21845),
60551 /* 180883 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/76,
60552 /* 180885 */ GIR_MakeTempReg, /*TempRegID*/74, /*TypeID*/GILLT_s32,
60553 /* 180888 */ GIR_BuildMI, /*InsnID*/75, /*Opcode*/GIMT_Encode2(PPC::ORI),
60554 /* 180892 */ GIR_AddTempRegister, /*InsnID*/75, /*TempRegID*/74, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60555 /* 180897 */ GIR_AddSimpleTempRegister, /*InsnID*/75, /*TempRegID*/75,
60556 /* 180900 */ GIR_AddImm, /*InsnID*/75, /*Imm*/GIMT_Encode8(21845),
60557 /* 180910 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/75,
60558 /* 180912 */ GIR_MakeTempReg, /*TempRegID*/73, /*TypeID*/GILLT_s32,
60559 /* 180915 */ GIR_BuildMI, /*InsnID*/74, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60560 /* 180919 */ GIR_AddTempRegister, /*InsnID*/74, /*TempRegID*/73, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60561 /* 180924 */ GIR_Copy, /*NewInsnID*/74, /*OldInsnID*/0, /*OpIdx*/1, // A
60562 /* 180928 */ GIR_AddImm8, /*InsnID*/74, /*Imm*/31,
60563 /* 180931 */ GIR_AddImm8, /*InsnID*/74, /*Imm*/1,
60564 /* 180934 */ GIR_AddImm8, /*InsnID*/74, /*Imm*/31,
60565 /* 180937 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/74,
60566 /* 180939 */ GIR_MakeTempReg, /*TempRegID*/72, /*TypeID*/GILLT_s32,
60567 /* 180942 */ GIR_BuildMI, /*InsnID*/73, /*Opcode*/GIMT_Encode2(PPC::AND),
60568 /* 180946 */ GIR_AddTempRegister, /*InsnID*/73, /*TempRegID*/72, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60569 /* 180951 */ GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/73,
60570 /* 180954 */ GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/74,
60571 /* 180957 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/73,
60572 /* 180959 */ GIR_MakeTempReg, /*TempRegID*/71, /*TypeID*/GILLT_s32,
60573 /* 180962 */ GIR_BuildMI, /*InsnID*/72, /*Opcode*/GIMT_Encode2(PPC::OR),
60574 /* 180966 */ GIR_AddTempRegister, /*InsnID*/72, /*TempRegID*/71, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60575 /* 180971 */ GIR_AddSimpleTempRegister, /*InsnID*/72, /*TempRegID*/72,
60576 /* 180974 */ GIR_AddSimpleTempRegister, /*InsnID*/72, /*TempRegID*/76,
60577 /* 180977 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/72,
60578 /* 180979 */ GIR_MakeTempReg, /*TempRegID*/70, /*TypeID*/GILLT_s32,
60579 /* 180982 */ GIR_BuildMI, /*InsnID*/71, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60580 /* 180986 */ GIR_AddTempRegister, /*InsnID*/71, /*TempRegID*/70, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60581 /* 180991 */ GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/71,
60582 /* 180994 */ GIR_AddImm8, /*InsnID*/71, /*Imm*/30,
60583 /* 180997 */ GIR_AddImm8, /*InsnID*/71, /*Imm*/2,
60584 /* 181000 */ GIR_AddImm8, /*InsnID*/71, /*Imm*/31,
60585 /* 181003 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/71,
60586 /* 181005 */ GIR_MakeTempReg, /*TempRegID*/69, /*TypeID*/GILLT_s32,
60587 /* 181008 */ GIR_BuildMI, /*InsnID*/70, /*Opcode*/GIMT_Encode2(PPC::AND),
60588 /* 181012 */ GIR_AddTempRegister, /*InsnID*/70, /*TempRegID*/69, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60589 /* 181017 */ GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/70,
60590 /* 181020 */ GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/80,
60591 /* 181023 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/70,
60592 /* 181025 */ GIR_MakeTempReg, /*TempRegID*/68, /*TypeID*/GILLT_s32,
60593 /* 181028 */ GIR_BuildMI, /*InsnID*/69, /*Opcode*/GIMT_Encode2(PPC::OR),
60594 /* 181032 */ GIR_AddTempRegister, /*InsnID*/69, /*TempRegID*/68, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60595 /* 181037 */ GIR_AddSimpleTempRegister, /*InsnID*/69, /*TempRegID*/69,
60596 /* 181040 */ GIR_AddSimpleTempRegister, /*InsnID*/69, /*TempRegID*/82,
60597 /* 181043 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/69,
60598 /* 181045 */ GIR_MakeTempReg, /*TempRegID*/67, /*TypeID*/GILLT_s32,
60599 /* 181048 */ GIR_BuildMI, /*InsnID*/68, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60600 /* 181052 */ GIR_AddTempRegister, /*InsnID*/68, /*TempRegID*/67, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60601 /* 181057 */ GIR_AddSimpleTempRegister, /*InsnID*/68, /*TempRegID*/68,
60602 /* 181060 */ GIR_AddImm8, /*InsnID*/68, /*Imm*/28,
60603 /* 181063 */ GIR_AddImm8, /*InsnID*/68, /*Imm*/4,
60604 /* 181066 */ GIR_AddImm8, /*InsnID*/68, /*Imm*/31,
60605 /* 181069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/68,
60606 /* 181071 */ GIR_MakeTempReg, /*TempRegID*/66, /*TypeID*/GILLT_s32,
60607 /* 181074 */ GIR_BuildMI, /*InsnID*/67, /*Opcode*/GIMT_Encode2(PPC::AND),
60608 /* 181078 */ GIR_AddTempRegister, /*InsnID*/67, /*TempRegID*/66, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60609 /* 181083 */ GIR_AddSimpleTempRegister, /*InsnID*/67, /*TempRegID*/67,
60610 /* 181086 */ GIR_AddSimpleTempRegister, /*InsnID*/67, /*TempRegID*/95,
60611 /* 181089 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/67,
60612 /* 181091 */ GIR_MakeTempReg, /*TempRegID*/65, /*TypeID*/GILLT_s32,
60613 /* 181094 */ GIR_BuildMI, /*InsnID*/66, /*Opcode*/GIMT_Encode2(PPC::OR),
60614 /* 181098 */ GIR_AddTempRegister, /*InsnID*/66, /*TempRegID*/65, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60615 /* 181103 */ GIR_AddSimpleTempRegister, /*InsnID*/66, /*TempRegID*/66,
60616 /* 181106 */ GIR_AddSimpleTempRegister, /*InsnID*/66, /*TempRegID*/97,
60617 /* 181109 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/66,
60618 /* 181111 */ GIR_MakeTempReg, /*TempRegID*/64, /*TypeID*/GILLT_s32,
60619 /* 181114 */ GIR_BuildMI, /*InsnID*/65, /*Opcode*/GIMT_Encode2(PPC::LIS),
60620 /* 181118 */ GIR_AddTempRegister, /*InsnID*/65, /*TempRegID*/64, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60621 /* 181123 */ GIR_AddImm, /*InsnID*/65, /*Imm*/GIMT_Encode8(61680),
60622 /* 181133 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/65,
60623 /* 181135 */ GIR_MakeTempReg, /*TempRegID*/63, /*TypeID*/GILLT_s32,
60624 /* 181138 */ GIR_BuildMI, /*InsnID*/64, /*Opcode*/GIMT_Encode2(PPC::ORI),
60625 /* 181142 */ GIR_AddTempRegister, /*InsnID*/64, /*TempRegID*/63, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60626 /* 181147 */ GIR_AddSimpleTempRegister, /*InsnID*/64, /*TempRegID*/64,
60627 /* 181150 */ GIR_AddImm, /*InsnID*/64, /*Imm*/GIMT_Encode8(61680),
60628 /* 181160 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/64,
60629 /* 181162 */ GIR_MakeTempReg, /*TempRegID*/62, /*TypeID*/GILLT_s32,
60630 /* 181165 */ GIR_BuildMI, /*InsnID*/63, /*Opcode*/GIMT_Encode2(PPC::LIS),
60631 /* 181169 */ GIR_AddTempRegister, /*InsnID*/63, /*TempRegID*/62, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60632 /* 181174 */ GIR_AddImm, /*InsnID*/63, /*Imm*/GIMT_Encode8(52428),
60633 /* 181184 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/63,
60634 /* 181186 */ GIR_MakeTempReg, /*TempRegID*/61, /*TypeID*/GILLT_s32,
60635 /* 181189 */ GIR_BuildMI, /*InsnID*/62, /*Opcode*/GIMT_Encode2(PPC::ORI),
60636 /* 181193 */ GIR_AddTempRegister, /*InsnID*/62, /*TempRegID*/61, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60637 /* 181198 */ GIR_AddSimpleTempRegister, /*InsnID*/62, /*TempRegID*/62,
60638 /* 181201 */ GIR_AddImm, /*InsnID*/62, /*Imm*/GIMT_Encode8(52428),
60639 /* 181211 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/62,
60640 /* 181213 */ GIR_MakeTempReg, /*TempRegID*/60, /*TypeID*/GILLT_s32,
60641 /* 181216 */ GIR_BuildMI, /*InsnID*/61, /*Opcode*/GIMT_Encode2(PPC::LIS),
60642 /* 181220 */ GIR_AddTempRegister, /*InsnID*/61, /*TempRegID*/60, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60643 /* 181225 */ GIR_AddImm, /*InsnID*/61, /*Imm*/GIMT_Encode8(43690),
60644 /* 181235 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/61,
60645 /* 181237 */ GIR_MakeTempReg, /*TempRegID*/59, /*TypeID*/GILLT_s32,
60646 /* 181240 */ GIR_BuildMI, /*InsnID*/60, /*Opcode*/GIMT_Encode2(PPC::ORI),
60647 /* 181244 */ GIR_AddTempRegister, /*InsnID*/60, /*TempRegID*/59, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60648 /* 181249 */ GIR_AddSimpleTempRegister, /*InsnID*/60, /*TempRegID*/60,
60649 /* 181252 */ GIR_AddImm, /*InsnID*/60, /*Imm*/GIMT_Encode8(43690),
60650 /* 181262 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/60,
60651 /* 181264 */ GIR_MakeTempReg, /*TempRegID*/58, /*TypeID*/GILLT_s32,
60652 /* 181267 */ GIR_BuildMI, /*InsnID*/59, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60653 /* 181271 */ GIR_AddTempRegister, /*InsnID*/59, /*TempRegID*/58, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60654 /* 181276 */ GIR_Copy, /*NewInsnID*/59, /*OldInsnID*/0, /*OpIdx*/1, // A
60655 /* 181280 */ GIR_AddImm8, /*InsnID*/59, /*Imm*/1,
60656 /* 181283 */ GIR_AddImm8, /*InsnID*/59, /*Imm*/0,
60657 /* 181286 */ GIR_AddImm8, /*InsnID*/59, /*Imm*/30,
60658 /* 181289 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/59,
60659 /* 181291 */ GIR_MakeTempReg, /*TempRegID*/57, /*TypeID*/GILLT_s32,
60660 /* 181294 */ GIR_BuildMI, /*InsnID*/58, /*Opcode*/GIMT_Encode2(PPC::AND),
60661 /* 181298 */ GIR_AddTempRegister, /*InsnID*/58, /*TempRegID*/57, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60662 /* 181303 */ GIR_AddSimpleTempRegister, /*InsnID*/58, /*TempRegID*/58,
60663 /* 181306 */ GIR_AddSimpleTempRegister, /*InsnID*/58, /*TempRegID*/59,
60664 /* 181309 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/58,
60665 /* 181311 */ GIR_MakeTempReg, /*TempRegID*/56, /*TypeID*/GILLT_s32,
60666 /* 181314 */ GIR_BuildMI, /*InsnID*/57, /*Opcode*/GIMT_Encode2(PPC::LIS),
60667 /* 181318 */ GIR_AddTempRegister, /*InsnID*/57, /*TempRegID*/56, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60668 /* 181323 */ GIR_AddImm, /*InsnID*/57, /*Imm*/GIMT_Encode8(21845),
60669 /* 181333 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/57,
60670 /* 181335 */ GIR_MakeTempReg, /*TempRegID*/55, /*TypeID*/GILLT_s32,
60671 /* 181338 */ GIR_BuildMI, /*InsnID*/56, /*Opcode*/GIMT_Encode2(PPC::ORI),
60672 /* 181342 */ GIR_AddTempRegister, /*InsnID*/56, /*TempRegID*/55, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60673 /* 181347 */ GIR_AddSimpleTempRegister, /*InsnID*/56, /*TempRegID*/56,
60674 /* 181350 */ GIR_AddImm, /*InsnID*/56, /*Imm*/GIMT_Encode8(21845),
60675 /* 181360 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/56,
60676 /* 181362 */ GIR_MakeTempReg, /*TempRegID*/54, /*TypeID*/GILLT_s32,
60677 /* 181365 */ GIR_BuildMI, /*InsnID*/55, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60678 /* 181369 */ GIR_AddTempRegister, /*InsnID*/55, /*TempRegID*/54, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60679 /* 181374 */ GIR_Copy, /*NewInsnID*/55, /*OldInsnID*/0, /*OpIdx*/1, // A
60680 /* 181378 */ GIR_AddImm8, /*InsnID*/55, /*Imm*/31,
60681 /* 181381 */ GIR_AddImm8, /*InsnID*/55, /*Imm*/1,
60682 /* 181384 */ GIR_AddImm8, /*InsnID*/55, /*Imm*/31,
60683 /* 181387 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/55,
60684 /* 181389 */ GIR_MakeTempReg, /*TempRegID*/53, /*TypeID*/GILLT_s32,
60685 /* 181392 */ GIR_BuildMI, /*InsnID*/54, /*Opcode*/GIMT_Encode2(PPC::AND),
60686 /* 181396 */ GIR_AddTempRegister, /*InsnID*/54, /*TempRegID*/53, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60687 /* 181401 */ GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/54,
60688 /* 181404 */ GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/55,
60689 /* 181407 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/54,
60690 /* 181409 */ GIR_MakeTempReg, /*TempRegID*/52, /*TypeID*/GILLT_s32,
60691 /* 181412 */ GIR_BuildMI, /*InsnID*/53, /*Opcode*/GIMT_Encode2(PPC::OR),
60692 /* 181416 */ GIR_AddTempRegister, /*InsnID*/53, /*TempRegID*/52, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60693 /* 181421 */ GIR_AddSimpleTempRegister, /*InsnID*/53, /*TempRegID*/53,
60694 /* 181424 */ GIR_AddSimpleTempRegister, /*InsnID*/53, /*TempRegID*/57,
60695 /* 181427 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/53,
60696 /* 181429 */ GIR_MakeTempReg, /*TempRegID*/51, /*TypeID*/GILLT_s32,
60697 /* 181432 */ GIR_BuildMI, /*InsnID*/52, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60698 /* 181436 */ GIR_AddTempRegister, /*InsnID*/52, /*TempRegID*/51, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60699 /* 181441 */ GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/52,
60700 /* 181444 */ GIR_AddImm8, /*InsnID*/52, /*Imm*/2,
60701 /* 181447 */ GIR_AddImm8, /*InsnID*/52, /*Imm*/0,
60702 /* 181450 */ GIR_AddImm8, /*InsnID*/52, /*Imm*/29,
60703 /* 181453 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/52,
60704 /* 181455 */ GIR_MakeTempReg, /*TempRegID*/50, /*TypeID*/GILLT_s32,
60705 /* 181458 */ GIR_BuildMI, /*InsnID*/51, /*Opcode*/GIMT_Encode2(PPC::AND),
60706 /* 181462 */ GIR_AddTempRegister, /*InsnID*/51, /*TempRegID*/50, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60707 /* 181467 */ GIR_AddSimpleTempRegister, /*InsnID*/51, /*TempRegID*/51,
60708 /* 181470 */ GIR_AddSimpleTempRegister, /*InsnID*/51, /*TempRegID*/61,
60709 /* 181473 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/51,
60710 /* 181475 */ GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_s32,
60711 /* 181478 */ GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(PPC::LIS),
60712 /* 181482 */ GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60713 /* 181487 */ GIR_AddImm, /*InsnID*/50, /*Imm*/GIMT_Encode8(13107),
60714 /* 181497 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
60715 /* 181499 */ GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_s32,
60716 /* 181502 */ GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(PPC::ORI),
60717 /* 181506 */ GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60718 /* 181511 */ GIR_AddSimpleTempRegister, /*InsnID*/49, /*TempRegID*/49,
60719 /* 181514 */ GIR_AddImm, /*InsnID*/49, /*Imm*/GIMT_Encode8(13107),
60720 /* 181524 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
60721 /* 181526 */ GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_s32,
60722 /* 181529 */ GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(PPC::LIS),
60723 /* 181533 */ GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60724 /* 181538 */ GIR_AddImm, /*InsnID*/48, /*Imm*/GIMT_Encode8(43690),
60725 /* 181548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
60726 /* 181550 */ GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s32,
60727 /* 181553 */ GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(PPC::ORI),
60728 /* 181557 */ GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60729 /* 181562 */ GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
60730 /* 181565 */ GIR_AddImm, /*InsnID*/47, /*Imm*/GIMT_Encode8(43690),
60731 /* 181575 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
60732 /* 181577 */ GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s32,
60733 /* 181580 */ GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60734 /* 181584 */ GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60735 /* 181589 */ GIR_Copy, /*NewInsnID*/46, /*OldInsnID*/0, /*OpIdx*/1, // A
60736 /* 181593 */ GIR_AddImm8, /*InsnID*/46, /*Imm*/1,
60737 /* 181596 */ GIR_AddImm8, /*InsnID*/46, /*Imm*/0,
60738 /* 181599 */ GIR_AddImm8, /*InsnID*/46, /*Imm*/30,
60739 /* 181602 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
60740 /* 181604 */ GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s32,
60741 /* 181607 */ GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(PPC::AND),
60742 /* 181611 */ GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60743 /* 181616 */ GIR_AddSimpleTempRegister, /*InsnID*/45, /*TempRegID*/45,
60744 /* 181619 */ GIR_AddSimpleTempRegister, /*InsnID*/45, /*TempRegID*/46,
60745 /* 181622 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
60746 /* 181624 */ GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s32,
60747 /* 181627 */ GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(PPC::LIS),
60748 /* 181631 */ GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60749 /* 181636 */ GIR_AddImm, /*InsnID*/44, /*Imm*/GIMT_Encode8(21845),
60750 /* 181646 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
60751 /* 181648 */ GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s32,
60752 /* 181651 */ GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(PPC::ORI),
60753 /* 181655 */ GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60754 /* 181660 */ GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
60755 /* 181663 */ GIR_AddImm, /*InsnID*/43, /*Imm*/GIMT_Encode8(21845),
60756 /* 181673 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
60757 /* 181675 */ GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_s32,
60758 /* 181678 */ GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60759 /* 181682 */ GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60760 /* 181687 */ GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/1, // A
60761 /* 181691 */ GIR_AddImm8, /*InsnID*/42, /*Imm*/31,
60762 /* 181694 */ GIR_AddImm8, /*InsnID*/42, /*Imm*/1,
60763 /* 181697 */ GIR_AddImm8, /*InsnID*/42, /*Imm*/31,
60764 /* 181700 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
60765 /* 181702 */ GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_s32,
60766 /* 181705 */ GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(PPC::AND),
60767 /* 181709 */ GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60768 /* 181714 */ GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/41,
60769 /* 181717 */ GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/42,
60770 /* 181720 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
60771 /* 181722 */ GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_s32,
60772 /* 181725 */ GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(PPC::OR),
60773 /* 181729 */ GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60774 /* 181734 */ GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
60775 /* 181737 */ GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/44,
60776 /* 181740 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
60777 /* 181742 */ GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s32,
60778 /* 181745 */ GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60779 /* 181749 */ GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60780 /* 181754 */ GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
60781 /* 181757 */ GIR_AddImm8, /*InsnID*/39, /*Imm*/30,
60782 /* 181760 */ GIR_AddImm8, /*InsnID*/39, /*Imm*/2,
60783 /* 181763 */ GIR_AddImm8, /*InsnID*/39, /*Imm*/31,
60784 /* 181766 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
60785 /* 181768 */ GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s32,
60786 /* 181771 */ GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(PPC::AND),
60787 /* 181775 */ GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60788 /* 181780 */ GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
60789 /* 181783 */ GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/48,
60790 /* 181786 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
60791 /* 181788 */ GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_s32,
60792 /* 181791 */ GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(PPC::OR),
60793 /* 181795 */ GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60794 /* 181800 */ GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
60795 /* 181803 */ GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/50,
60796 /* 181806 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
60797 /* 181808 */ GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s32,
60798 /* 181811 */ GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60799 /* 181815 */ GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60800 /* 181820 */ GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
60801 /* 181823 */ GIR_AddImm8, /*InsnID*/36, /*Imm*/4,
60802 /* 181826 */ GIR_AddImm8, /*InsnID*/36, /*Imm*/0,
60803 /* 181829 */ GIR_AddImm8, /*InsnID*/36, /*Imm*/27,
60804 /* 181832 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
60805 /* 181834 */ GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s32,
60806 /* 181837 */ GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(PPC::AND),
60807 /* 181841 */ GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60808 /* 181846 */ GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
60809 /* 181849 */ GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/63,
60810 /* 181852 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
60811 /* 181854 */ GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s32,
60812 /* 181857 */ GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(PPC::LIS),
60813 /* 181861 */ GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60814 /* 181866 */ GIR_AddImm, /*InsnID*/34, /*Imm*/GIMT_Encode8(3855),
60815 /* 181876 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
60816 /* 181878 */ GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s32,
60817 /* 181881 */ GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(PPC::ORI),
60818 /* 181885 */ GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60819 /* 181890 */ GIR_AddSimpleTempRegister, /*InsnID*/33, /*TempRegID*/33,
60820 /* 181893 */ GIR_AddImm, /*InsnID*/33, /*Imm*/GIMT_Encode8(3855),
60821 /* 181903 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
60822 /* 181905 */ GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s32,
60823 /* 181908 */ GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(PPC::LIS),
60824 /* 181912 */ GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60825 /* 181917 */ GIR_AddImm, /*InsnID*/32, /*Imm*/GIMT_Encode8(52428),
60826 /* 181927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
60827 /* 181929 */ GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s32,
60828 /* 181932 */ GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(PPC::ORI),
60829 /* 181936 */ GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60830 /* 181941 */ GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
60831 /* 181944 */ GIR_AddImm, /*InsnID*/31, /*Imm*/GIMT_Encode8(52428),
60832 /* 181954 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
60833 /* 181956 */ GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s32,
60834 /* 181959 */ GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(PPC::LIS),
60835 /* 181963 */ GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60836 /* 181968 */ GIR_AddImm, /*InsnID*/30, /*Imm*/GIMT_Encode8(43690),
60837 /* 181978 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
60838 /* 181980 */ GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s32,
60839 /* 181983 */ GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(PPC::ORI),
60840 /* 181987 */ GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60841 /* 181992 */ GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
60842 /* 181995 */ GIR_AddImm, /*InsnID*/29, /*Imm*/GIMT_Encode8(43690),
60843 /* 182005 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
60844 /* 182007 */ GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s32,
60845 /* 182010 */ GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60846 /* 182014 */ GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60847 /* 182019 */ GIR_Copy, /*NewInsnID*/28, /*OldInsnID*/0, /*OpIdx*/1, // A
60848 /* 182023 */ GIR_AddImm8, /*InsnID*/28, /*Imm*/1,
60849 /* 182026 */ GIR_AddImm8, /*InsnID*/28, /*Imm*/0,
60850 /* 182029 */ GIR_AddImm8, /*InsnID*/28, /*Imm*/30,
60851 /* 182032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
60852 /* 182034 */ GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_s32,
60853 /* 182037 */ GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(PPC::AND),
60854 /* 182041 */ GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60855 /* 182046 */ GIR_AddSimpleTempRegister, /*InsnID*/27, /*TempRegID*/27,
60856 /* 182049 */ GIR_AddSimpleTempRegister, /*InsnID*/27, /*TempRegID*/28,
60857 /* 182052 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
60858 /* 182054 */ GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_s32,
60859 /* 182057 */ GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(PPC::LIS),
60860 /* 182061 */ GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60861 /* 182066 */ GIR_AddImm, /*InsnID*/26, /*Imm*/GIMT_Encode8(21845),
60862 /* 182076 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
60863 /* 182078 */ GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_s32,
60864 /* 182081 */ GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(PPC::ORI),
60865 /* 182085 */ GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60866 /* 182090 */ GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
60867 /* 182093 */ GIR_AddImm, /*InsnID*/25, /*Imm*/GIMT_Encode8(21845),
60868 /* 182103 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
60869 /* 182105 */ GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s32,
60870 /* 182108 */ GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60871 /* 182112 */ GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60872 /* 182117 */ GIR_Copy, /*NewInsnID*/24, /*OldInsnID*/0, /*OpIdx*/1, // A
60873 /* 182121 */ GIR_AddImm8, /*InsnID*/24, /*Imm*/31,
60874 /* 182124 */ GIR_AddImm8, /*InsnID*/24, /*Imm*/1,
60875 /* 182127 */ GIR_AddImm8, /*InsnID*/24, /*Imm*/31,
60876 /* 182130 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
60877 /* 182132 */ GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s32,
60878 /* 182135 */ GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(PPC::AND),
60879 /* 182139 */ GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60880 /* 182144 */ GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
60881 /* 182147 */ GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/24,
60882 /* 182150 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
60883 /* 182152 */ GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s32,
60884 /* 182155 */ GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(PPC::OR),
60885 /* 182159 */ GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60886 /* 182164 */ GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
60887 /* 182167 */ GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/26,
60888 /* 182170 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
60889 /* 182172 */ GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s32,
60890 /* 182175 */ GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60891 /* 182179 */ GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60892 /* 182184 */ GIR_AddSimpleTempRegister, /*InsnID*/21, /*TempRegID*/21,
60893 /* 182187 */ GIR_AddImm8, /*InsnID*/21, /*Imm*/2,
60894 /* 182190 */ GIR_AddImm8, /*InsnID*/21, /*Imm*/0,
60895 /* 182193 */ GIR_AddImm8, /*InsnID*/21, /*Imm*/29,
60896 /* 182196 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
60897 /* 182198 */ GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s32,
60898 /* 182201 */ GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(PPC::AND),
60899 /* 182205 */ GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60900 /* 182210 */ GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
60901 /* 182213 */ GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/30,
60902 /* 182216 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
60903 /* 182218 */ GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_s32,
60904 /* 182221 */ GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(PPC::LIS),
60905 /* 182225 */ GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60906 /* 182230 */ GIR_AddImm, /*InsnID*/19, /*Imm*/GIMT_Encode8(13107),
60907 /* 182240 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
60908 /* 182242 */ GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s32,
60909 /* 182245 */ GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(PPC::ORI),
60910 /* 182249 */ GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60911 /* 182254 */ GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
60912 /* 182257 */ GIR_AddImm, /*InsnID*/18, /*Imm*/GIMT_Encode8(13107),
60913 /* 182267 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
60914 /* 182269 */ GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s32,
60915 /* 182272 */ GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(PPC::LIS),
60916 /* 182276 */ GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60917 /* 182281 */ GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(43690),
60918 /* 182291 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
60919 /* 182293 */ GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s32,
60920 /* 182296 */ GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(PPC::ORI),
60921 /* 182300 */ GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60922 /* 182305 */ GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
60923 /* 182308 */ GIR_AddImm, /*InsnID*/16, /*Imm*/GIMT_Encode8(43690),
60924 /* 182318 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
60925 /* 182320 */ GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s32,
60926 /* 182323 */ GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60927 /* 182327 */ GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60928 /* 182332 */ GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // A
60929 /* 182336 */ GIR_AddImm8, /*InsnID*/15, /*Imm*/1,
60930 /* 182339 */ GIR_AddImm8, /*InsnID*/15, /*Imm*/0,
60931 /* 182342 */ GIR_AddImm8, /*InsnID*/15, /*Imm*/30,
60932 /* 182345 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
60933 /* 182347 */ GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s32,
60934 /* 182350 */ GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(PPC::AND),
60935 /* 182354 */ GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60936 /* 182359 */ GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
60937 /* 182362 */ GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
60938 /* 182365 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
60939 /* 182367 */ GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s32,
60940 /* 182370 */ GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(PPC::LIS),
60941 /* 182374 */ GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60942 /* 182379 */ GIR_AddImm, /*InsnID*/13, /*Imm*/GIMT_Encode8(21845),
60943 /* 182389 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
60944 /* 182391 */ GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
60945 /* 182394 */ GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(PPC::ORI),
60946 /* 182398 */ GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60947 /* 182403 */ GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
60948 /* 182406 */ GIR_AddImm, /*InsnID*/12, /*Imm*/GIMT_Encode8(21845),
60949 /* 182416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
60950 /* 182418 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
60951 /* 182421 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60952 /* 182425 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60953 /* 182430 */ GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/1, // A
60954 /* 182434 */ GIR_AddImm8, /*InsnID*/11, /*Imm*/31,
60955 /* 182437 */ GIR_AddImm8, /*InsnID*/11, /*Imm*/1,
60956 /* 182440 */ GIR_AddImm8, /*InsnID*/11, /*Imm*/31,
60957 /* 182443 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
60958 /* 182445 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
60959 /* 182448 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(PPC::AND),
60960 /* 182452 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60961 /* 182457 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
60962 /* 182460 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/11,
60963 /* 182463 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
60964 /* 182465 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
60965 /* 182468 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(PPC::OR),
60966 /* 182472 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60967 /* 182477 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
60968 /* 182480 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/13,
60969 /* 182483 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
60970 /* 182485 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
60971 /* 182488 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60972 /* 182492 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60973 /* 182497 */ GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
60974 /* 182500 */ GIR_AddImm8, /*InsnID*/8, /*Imm*/30,
60975 /* 182503 */ GIR_AddImm8, /*InsnID*/8, /*Imm*/2,
60976 /* 182506 */ GIR_AddImm8, /*InsnID*/8, /*Imm*/31,
60977 /* 182509 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
60978 /* 182511 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
60979 /* 182514 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(PPC::AND),
60980 /* 182518 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60981 /* 182523 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
60982 /* 182526 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/17,
60983 /* 182529 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
60984 /* 182531 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
60985 /* 182534 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(PPC::OR),
60986 /* 182538 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60987 /* 182543 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
60988 /* 182546 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/19,
60989 /* 182549 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
60990 /* 182551 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
60991 /* 182554 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
60992 /* 182558 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
60993 /* 182563 */ GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
60994 /* 182566 */ GIR_AddImm8, /*InsnID*/5, /*Imm*/28,
60995 /* 182569 */ GIR_AddImm8, /*InsnID*/5, /*Imm*/4,
60996 /* 182572 */ GIR_AddImm8, /*InsnID*/5, /*Imm*/31,
60997 /* 182575 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
60998 /* 182577 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
60999 /* 182580 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::AND),
61000 /* 182584 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61001 /* 182589 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
61002 /* 182592 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/32,
61003 /* 182595 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
61004 /* 182597 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
61005 /* 182600 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::OR),
61006 /* 182604 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61007 /* 182609 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
61008 /* 182612 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/34,
61009 /* 182615 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
61010 /* 182617 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
61011 /* 182620 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
61012 /* 182624 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61013 /* 182629 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
61014 /* 182632 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/24,
61015 /* 182635 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
61016 /* 182638 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
61017 /* 182641 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
61018 /* 182643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
61019 /* 182646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLWIMI),
61020 /* 182650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61021 /* 182655 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
61022 /* 182658 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/65,
61023 /* 182661 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
61024 /* 182664 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
61025 /* 182667 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
61026 /* 182670 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
61027 /* 182672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWIMI),
61028 /* 182675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
61029 /* 182677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
61030 /* 182680 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*//* 128(*/0x80, 0x01/*)*/,
61031 /* 182684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
61032 /* 182687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/24,
61033 /* 182690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
61034 /* 182693 */ GIR_RootConstrainSelectedInstOperands,
61035 /* 182694 */ // GIR_Coverage, 4890,
61036 /* 182694 */ GIR_EraseRootFromParent_Done,
61037 /* 182695 */ // Label 2769: @182695
61038 /* 182695 */ GIM_Reject,
61039 /* 182696 */ // Label 2767: @182696
61040 /* 182696 */ GIM_Reject,
61041 /* 182697 */ // Label 2765: @182697
61042 /* 182697 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(208387), // Rule ID 4891 //
61043 /* 182702 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
61044 /* 182705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID),
61045 /* 182709 */ // (bitreverse:{ *:[i64] } i64:{ *:[i64] }:$A) => (OR8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWIMI:{ *:[i32] } (RLWIMI:{ *:[i32] } (RLWINM:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 60:{ *:[i32] }, 4:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 3855:{ *:[i64] }), 3855:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ 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} (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 60:{ *:[i32] }, 4:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 3855:{ *:[i64] }), 3855:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 4:{ *:[i32] }, 59:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 61680:{ *:[i64] }), 61680:{ *:[i64] }))), 32:{ *:[i32] }, 32:{ *:[i32] }), sub_32:{ *:[i32] }), 8:{ *:[i32] }, 24:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] }))
61046 /* 182709 */ GIR_MakeTempReg, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TypeID*/GILLT_s32,
61047 /* 182713 */ GIR_BuildMI, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
61048 /* 182718 */ GIR_AddTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61049 /* 182725 */ GIR_AddImm, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
61050 /* 182736 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 140(*/0x8C, 0x01/*)*/,
61051 /* 182739 */ GIR_MakeTempReg, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TypeID*/GILLT_s32,
61052 /* 182743 */ GIR_BuildMI, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
61053 /* 182748 */ GIR_AddTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61054 /* 182755 */ GIR_AddSimpleTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/,
61055 /* 182760 */ GIR_AddImm, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
61056 /* 182771 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 139(*/0x8B, 0x01/*)*/,
61057 /* 182774 */ GIR_MakeTempReg, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TypeID*/GILLT_s64,
61058 /* 182778 */ GIR_BuildMI, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61059 /* 182783 */ GIR_AddTempRegister, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61060 /* 182790 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 138(*/0x8A, 0x01/*)*/,
61061 /* 182793 */ GIR_MakeTempReg, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TypeID*/GILLT_s64,
61062 /* 182797 */ GIR_BuildMI, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61063 /* 182802 */ GIR_AddTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61064 /* 182809 */ GIR_AddSimpleTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/,
61065 /* 182814 */ GIR_AddSimpleTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/,
61066 /* 182819 */ GIR_AddImm8, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Imm*/1,
61067 /* 182823 */ GIR_ConstrainOperandRC, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61068 /* 182829 */ GIR_ConstrainOperandRC, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61069 /* 182835 */ GIR_ConstrainOperandRC, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61070 /* 182841 */ GIR_MakeTempReg, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TypeID*/GILLT_s64,
61071 /* 182845 */ GIR_BuildMI, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61072 /* 182850 */ GIR_AddTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61073 /* 182857 */ GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/,
61074 /* 182862 */ GIR_AddImm8, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Imm*/32,
61075 /* 182866 */ GIR_AddImm8, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Imm*/31,
61076 /* 182870 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 136(*/0x88, 0x01/*)*/,
61077 /* 182873 */ GIR_MakeTempReg, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TypeID*/GILLT_s64,
61078 /* 182877 */ GIR_BuildMI, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61079 /* 182882 */ GIR_AddTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61080 /* 182889 */ GIR_AddSimpleTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/,
61081 /* 182894 */ GIR_AddImm, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
61082 /* 182905 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 135(*/0x87, 0x01/*)*/,
61083 /* 182908 */ GIR_MakeTempReg, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TypeID*/GILLT_s64,
61084 /* 182912 */ GIR_BuildMI, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61085 /* 182917 */ GIR_AddTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61086 /* 182924 */ GIR_AddSimpleTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/,
61087 /* 182929 */ GIR_AddImm, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680),
61088 /* 182940 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 134(*/0x86, 0x01/*)*/,
61089 /* 182943 */ GIR_MakeTempReg, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TypeID*/GILLT_s32,
61090 /* 182947 */ GIR_BuildMI, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
61091 /* 182952 */ GIR_AddTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61092 /* 182959 */ GIR_AddImm, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
61093 /* 182970 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 133(*/0x85, 0x01/*)*/,
61094 /* 182973 */ GIR_MakeTempReg, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TypeID*/GILLT_s32,
61095 /* 182977 */ GIR_BuildMI, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
61096 /* 182982 */ GIR_AddTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61097 /* 182989 */ GIR_AddSimpleTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/,
61098 /* 182994 */ GIR_AddImm, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
61099 /* 183005 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 132(*/0x84, 0x01/*)*/,
61100 /* 183008 */ GIR_MakeTempReg, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TypeID*/GILLT_s64,
61101 /* 183012 */ GIR_BuildMI, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61102 /* 183017 */ GIR_AddTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61103 /* 183024 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 131(*/0x83, 0x01/*)*/,
61104 /* 183027 */ GIR_MakeTempReg, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TypeID*/GILLT_s64,
61105 /* 183031 */ GIR_BuildMI, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61106 /* 183036 */ GIR_AddTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61107 /* 183043 */ GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/,
61108 /* 183048 */ GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/,
61109 /* 183053 */ GIR_AddImm8, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Imm*/1,
61110 /* 183057 */ GIR_ConstrainOperandRC, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61111 /* 183063 */ GIR_ConstrainOperandRC, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61112 /* 183069 */ GIR_ConstrainOperandRC, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61113 /* 183075 */ GIR_MakeTempReg, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TypeID*/GILLT_s64,
61114 /* 183079 */ GIR_BuildMI, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61115 /* 183084 */ GIR_AddTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61116 /* 183091 */ GIR_AddSimpleTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/,
61117 /* 183096 */ GIR_AddImm8, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Imm*/32,
61118 /* 183100 */ GIR_AddImm8, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Imm*/31,
61119 /* 183104 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 129(*/0x81, 0x01/*)*/,
61120 /* 183107 */ GIR_MakeTempReg, /*TempRegID*/127, /*TypeID*/GILLT_s64,
61121 /* 183110 */ GIR_BuildMI, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61122 /* 183115 */ GIR_AddTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*/127, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61123 /* 183121 */ GIR_AddSimpleTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/,
61124 /* 183126 */ GIR_AddImm, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
61125 /* 183137 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 128(*/0x80, 0x01/*)*/,
61126 /* 183140 */ GIR_MakeTempReg, /*TempRegID*/126, /*TypeID*/GILLT_s64,
61127 /* 183143 */ GIR_BuildMI, /*InsnID*/127, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61128 /* 183147 */ GIR_AddTempRegister, /*InsnID*/127, /*TempRegID*/126, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61129 /* 183152 */ GIR_AddSimpleTempRegister, /*InsnID*/127, /*TempRegID*/127,
61130 /* 183155 */ GIR_AddImm, /*InsnID*/127, /*Imm*/GIMT_Encode8(52428),
61131 /* 183165 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/127,
61132 /* 183167 */ GIR_MakeTempReg, /*TempRegID*/125, /*TypeID*/GILLT_s32,
61133 /* 183170 */ GIR_BuildMI, /*InsnID*/126, /*Opcode*/GIMT_Encode2(PPC::LIS),
61134 /* 183174 */ GIR_AddTempRegister, /*InsnID*/126, /*TempRegID*/125, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61135 /* 183179 */ GIR_AddImm, /*InsnID*/126, /*Imm*/GIMT_Encode8(43690),
61136 /* 183189 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/126,
61137 /* 183191 */ GIR_MakeTempReg, /*TempRegID*/124, /*TypeID*/GILLT_s32,
61138 /* 183194 */ GIR_BuildMI, /*InsnID*/125, /*Opcode*/GIMT_Encode2(PPC::ORI),
61139 /* 183198 */ GIR_AddTempRegister, /*InsnID*/125, /*TempRegID*/124, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61140 /* 183203 */ GIR_AddSimpleTempRegister, /*InsnID*/125, /*TempRegID*/125,
61141 /* 183206 */ GIR_AddImm, /*InsnID*/125, /*Imm*/GIMT_Encode8(43690),
61142 /* 183216 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/125,
61143 /* 183218 */ GIR_MakeTempReg, /*TempRegID*/123, /*TypeID*/GILLT_s64,
61144 /* 183221 */ GIR_BuildMI, /*InsnID*/124, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61145 /* 183225 */ GIR_AddTempRegister, /*InsnID*/124, /*TempRegID*/123, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61146 /* 183230 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/124,
61147 /* 183232 */ GIR_MakeTempReg, /*TempRegID*/122, /*TypeID*/GILLT_s64,
61148 /* 183235 */ GIR_BuildMI, /*InsnID*/123, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61149 /* 183239 */ GIR_AddTempRegister, /*InsnID*/123, /*TempRegID*/122, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61150 /* 183244 */ GIR_AddSimpleTempRegister, /*InsnID*/123, /*TempRegID*/123,
61151 /* 183247 */ GIR_AddSimpleTempRegister, /*InsnID*/123, /*TempRegID*/124,
61152 /* 183250 */ GIR_AddImm8, /*InsnID*/123, /*Imm*/1,
61153 /* 183253 */ GIR_ConstrainOperandRC, /*InsnID*/123, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61154 /* 183258 */ GIR_ConstrainOperandRC, /*InsnID*/123, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61155 /* 183263 */ GIR_ConstrainOperandRC, /*InsnID*/123, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61156 /* 183268 */ GIR_MakeTempReg, /*TempRegID*/121, /*TypeID*/GILLT_s64,
61157 /* 183271 */ GIR_BuildMI, /*InsnID*/122, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61158 /* 183275 */ GIR_AddTempRegister, /*InsnID*/122, /*TempRegID*/121, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61159 /* 183280 */ GIR_AddSimpleTempRegister, /*InsnID*/122, /*TempRegID*/122,
61160 /* 183283 */ GIR_AddImm8, /*InsnID*/122, /*Imm*/32,
61161 /* 183286 */ GIR_AddImm8, /*InsnID*/122, /*Imm*/31,
61162 /* 183289 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/122,
61163 /* 183291 */ GIR_MakeTempReg, /*TempRegID*/120, /*TypeID*/GILLT_s64,
61164 /* 183294 */ GIR_BuildMI, /*InsnID*/121, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61165 /* 183298 */ GIR_AddTempRegister, /*InsnID*/121, /*TempRegID*/120, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61166 /* 183303 */ GIR_AddSimpleTempRegister, /*InsnID*/121, /*TempRegID*/121,
61167 /* 183306 */ GIR_AddImm, /*InsnID*/121, /*Imm*/GIMT_Encode8(43690),
61168 /* 183316 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/121,
61169 /* 183318 */ GIR_MakeTempReg, /*TempRegID*/119, /*TypeID*/GILLT_s64,
61170 /* 183321 */ GIR_BuildMI, /*InsnID*/120, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61171 /* 183325 */ GIR_AddTempRegister, /*InsnID*/120, /*TempRegID*/119, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61172 /* 183330 */ GIR_AddSimpleTempRegister, /*InsnID*/120, /*TempRegID*/120,
61173 /* 183333 */ GIR_AddImm, /*InsnID*/120, /*Imm*/GIMT_Encode8(43690),
61174 /* 183343 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/120,
61175 /* 183345 */ GIR_MakeTempReg, /*TempRegID*/118, /*TypeID*/GILLT_s64,
61176 /* 183348 */ GIR_BuildMI, /*InsnID*/119, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61177 /* 183352 */ GIR_AddTempRegister, /*InsnID*/119, /*TempRegID*/118, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61178 /* 183357 */ GIR_Copy, /*NewInsnID*/119, /*OldInsnID*/0, /*OpIdx*/1, // A
61179 /* 183361 */ GIR_AddImm8, /*InsnID*/119, /*Imm*/1,
61180 /* 183364 */ GIR_AddImm8, /*InsnID*/119, /*Imm*/62,
61181 /* 183367 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/119,
61182 /* 183369 */ GIR_MakeTempReg, /*TempRegID*/117, /*TypeID*/GILLT_s64,
61183 /* 183372 */ GIR_BuildMI, /*InsnID*/118, /*Opcode*/GIMT_Encode2(PPC::AND8),
61184 /* 183376 */ GIR_AddTempRegister, /*InsnID*/118, /*TempRegID*/117, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61185 /* 183381 */ GIR_AddSimpleTempRegister, /*InsnID*/118, /*TempRegID*/118,
61186 /* 183384 */ GIR_AddSimpleTempRegister, /*InsnID*/118, /*TempRegID*/119,
61187 /* 183387 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/118,
61188 /* 183389 */ GIR_MakeTempReg, /*TempRegID*/116, /*TypeID*/GILLT_s32,
61189 /* 183392 */ GIR_BuildMI, /*InsnID*/117, /*Opcode*/GIMT_Encode2(PPC::LIS),
61190 /* 183396 */ GIR_AddTempRegister, /*InsnID*/117, /*TempRegID*/116, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61191 /* 183401 */ GIR_AddImm, /*InsnID*/117, /*Imm*/GIMT_Encode8(21845),
61192 /* 183411 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/117,
61193 /* 183413 */ GIR_MakeTempReg, /*TempRegID*/115, /*TypeID*/GILLT_s32,
61194 /* 183416 */ GIR_BuildMI, /*InsnID*/116, /*Opcode*/GIMT_Encode2(PPC::ORI),
61195 /* 183420 */ GIR_AddTempRegister, /*InsnID*/116, /*TempRegID*/115, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61196 /* 183425 */ GIR_AddSimpleTempRegister, /*InsnID*/116, /*TempRegID*/116,
61197 /* 183428 */ GIR_AddImm, /*InsnID*/116, /*Imm*/GIMT_Encode8(21845),
61198 /* 183438 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/116,
61199 /* 183440 */ GIR_MakeTempReg, /*TempRegID*/114, /*TypeID*/GILLT_s64,
61200 /* 183443 */ GIR_BuildMI, /*InsnID*/115, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61201 /* 183447 */ GIR_AddTempRegister, /*InsnID*/115, /*TempRegID*/114, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61202 /* 183452 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/115,
61203 /* 183454 */ GIR_MakeTempReg, /*TempRegID*/113, /*TypeID*/GILLT_s64,
61204 /* 183457 */ GIR_BuildMI, /*InsnID*/114, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61205 /* 183461 */ GIR_AddTempRegister, /*InsnID*/114, /*TempRegID*/113, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61206 /* 183466 */ GIR_AddSimpleTempRegister, /*InsnID*/114, /*TempRegID*/114,
61207 /* 183469 */ GIR_AddSimpleTempRegister, /*InsnID*/114, /*TempRegID*/115,
61208 /* 183472 */ GIR_AddImm8, /*InsnID*/114, /*Imm*/1,
61209 /* 183475 */ GIR_ConstrainOperandRC, /*InsnID*/114, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61210 /* 183480 */ GIR_ConstrainOperandRC, /*InsnID*/114, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61211 /* 183485 */ GIR_ConstrainOperandRC, /*InsnID*/114, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61212 /* 183490 */ GIR_MakeTempReg, /*TempRegID*/112, /*TypeID*/GILLT_s64,
61213 /* 183493 */ GIR_BuildMI, /*InsnID*/113, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61214 /* 183497 */ GIR_AddTempRegister, /*InsnID*/113, /*TempRegID*/112, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61215 /* 183502 */ GIR_AddSimpleTempRegister, /*InsnID*/113, /*TempRegID*/113,
61216 /* 183505 */ GIR_AddImm8, /*InsnID*/113, /*Imm*/32,
61217 /* 183508 */ GIR_AddImm8, /*InsnID*/113, /*Imm*/31,
61218 /* 183511 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/113,
61219 /* 183513 */ GIR_MakeTempReg, /*TempRegID*/111, /*TypeID*/GILLT_s64,
61220 /* 183516 */ GIR_BuildMI, /*InsnID*/112, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61221 /* 183520 */ GIR_AddTempRegister, /*InsnID*/112, /*TempRegID*/111, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61222 /* 183525 */ GIR_AddSimpleTempRegister, /*InsnID*/112, /*TempRegID*/112,
61223 /* 183528 */ GIR_AddImm, /*InsnID*/112, /*Imm*/GIMT_Encode8(21845),
61224 /* 183538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/112,
61225 /* 183540 */ GIR_MakeTempReg, /*TempRegID*/110, /*TypeID*/GILLT_s64,
61226 /* 183543 */ GIR_BuildMI, /*InsnID*/111, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61227 /* 183547 */ GIR_AddTempRegister, /*InsnID*/111, /*TempRegID*/110, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61228 /* 183552 */ GIR_AddSimpleTempRegister, /*InsnID*/111, /*TempRegID*/111,
61229 /* 183555 */ GIR_AddImm, /*InsnID*/111, /*Imm*/GIMT_Encode8(21845),
61230 /* 183565 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/111,
61231 /* 183567 */ GIR_MakeTempReg, /*TempRegID*/109, /*TypeID*/GILLT_s64,
61232 /* 183570 */ GIR_BuildMI, /*InsnID*/110, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
61233 /* 183574 */ GIR_AddTempRegister, /*InsnID*/110, /*TempRegID*/109, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61234 /* 183579 */ GIR_Copy, /*NewInsnID*/110, /*OldInsnID*/0, /*OpIdx*/1, // A
61235 /* 183583 */ GIR_AddImm8, /*InsnID*/110, /*Imm*/63,
61236 /* 183586 */ GIR_AddImm8, /*InsnID*/110, /*Imm*/1,
61237 /* 183589 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/110,
61238 /* 183591 */ GIR_MakeTempReg, /*TempRegID*/108, /*TypeID*/GILLT_s64,
61239 /* 183594 */ GIR_BuildMI, /*InsnID*/109, /*Opcode*/GIMT_Encode2(PPC::AND8),
61240 /* 183598 */ GIR_AddTempRegister, /*InsnID*/109, /*TempRegID*/108, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61241 /* 183603 */ GIR_AddSimpleTempRegister, /*InsnID*/109, /*TempRegID*/109,
61242 /* 183606 */ GIR_AddSimpleTempRegister, /*InsnID*/109, /*TempRegID*/110,
61243 /* 183609 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/109,
61244 /* 183611 */ GIR_MakeTempReg, /*TempRegID*/107, /*TypeID*/GILLT_s64,
61245 /* 183614 */ GIR_BuildMI, /*InsnID*/108, /*Opcode*/GIMT_Encode2(PPC::OR8),
61246 /* 183618 */ GIR_AddTempRegister, /*InsnID*/108, /*TempRegID*/107, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61247 /* 183623 */ GIR_AddSimpleTempRegister, /*InsnID*/108, /*TempRegID*/108,
61248 /* 183626 */ GIR_AddSimpleTempRegister, /*InsnID*/108, /*TempRegID*/117,
61249 /* 183629 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/108,
61250 /* 183631 */ GIR_MakeTempReg, /*TempRegID*/106, /*TypeID*/GILLT_s64,
61251 /* 183634 */ GIR_BuildMI, /*InsnID*/107, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61252 /* 183638 */ GIR_AddTempRegister, /*InsnID*/107, /*TempRegID*/106, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61253 /* 183643 */ GIR_AddSimpleTempRegister, /*InsnID*/107, /*TempRegID*/107,
61254 /* 183646 */ GIR_AddImm8, /*InsnID*/107, /*Imm*/2,
61255 /* 183649 */ GIR_AddImm8, /*InsnID*/107, /*Imm*/61,
61256 /* 183652 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/107,
61257 /* 183654 */ GIR_MakeTempReg, /*TempRegID*/105, /*TypeID*/GILLT_s64,
61258 /* 183657 */ GIR_BuildMI, /*InsnID*/106, /*Opcode*/GIMT_Encode2(PPC::AND8),
61259 /* 183661 */ GIR_AddTempRegister, /*InsnID*/106, /*TempRegID*/105, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61260 /* 183666 */ GIR_AddSimpleTempRegister, /*InsnID*/106, /*TempRegID*/106,
61261 /* 183669 */ GIR_AddSimpleTempRegister, /*InsnID*/106, /*TempRegID*/126,
61262 /* 183672 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/106,
61263 /* 183674 */ GIR_MakeTempReg, /*TempRegID*/104, /*TypeID*/GILLT_s32,
61264 /* 183677 */ GIR_BuildMI, /*InsnID*/105, /*Opcode*/GIMT_Encode2(PPC::LIS),
61265 /* 183681 */ GIR_AddTempRegister, /*InsnID*/105, /*TempRegID*/104, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61266 /* 183686 */ GIR_AddImm, /*InsnID*/105, /*Imm*/GIMT_Encode8(13107),
61267 /* 183696 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/105,
61268 /* 183698 */ GIR_MakeTempReg, /*TempRegID*/103, /*TypeID*/GILLT_s32,
61269 /* 183701 */ GIR_BuildMI, /*InsnID*/104, /*Opcode*/GIMT_Encode2(PPC::ORI),
61270 /* 183705 */ GIR_AddTempRegister, /*InsnID*/104, /*TempRegID*/103, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61271 /* 183710 */ GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/104,
61272 /* 183713 */ GIR_AddImm, /*InsnID*/104, /*Imm*/GIMT_Encode8(13107),
61273 /* 183723 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/104,
61274 /* 183725 */ GIR_MakeTempReg, /*TempRegID*/102, /*TypeID*/GILLT_s64,
61275 /* 183728 */ GIR_BuildMI, /*InsnID*/103, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61276 /* 183732 */ GIR_AddTempRegister, /*InsnID*/103, /*TempRegID*/102, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61277 /* 183737 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/103,
61278 /* 183739 */ GIR_MakeTempReg, /*TempRegID*/101, /*TypeID*/GILLT_s64,
61279 /* 183742 */ GIR_BuildMI, /*InsnID*/102, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61280 /* 183746 */ GIR_AddTempRegister, /*InsnID*/102, /*TempRegID*/101, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61281 /* 183751 */ GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/102,
61282 /* 183754 */ GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/103,
61283 /* 183757 */ GIR_AddImm8, /*InsnID*/102, /*Imm*/1,
61284 /* 183760 */ GIR_ConstrainOperandRC, /*InsnID*/102, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61285 /* 183765 */ GIR_ConstrainOperandRC, /*InsnID*/102, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61286 /* 183770 */ GIR_ConstrainOperandRC, /*InsnID*/102, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61287 /* 183775 */ GIR_MakeTempReg, /*TempRegID*/100, /*TypeID*/GILLT_s64,
61288 /* 183778 */ GIR_BuildMI, /*InsnID*/101, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61289 /* 183782 */ GIR_AddTempRegister, /*InsnID*/101, /*TempRegID*/100, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61290 /* 183787 */ GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/101,
61291 /* 183790 */ GIR_AddImm8, /*InsnID*/101, /*Imm*/32,
61292 /* 183793 */ GIR_AddImm8, /*InsnID*/101, /*Imm*/31,
61293 /* 183796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/101,
61294 /* 183798 */ GIR_MakeTempReg, /*TempRegID*/99, /*TypeID*/GILLT_s64,
61295 /* 183801 */ GIR_BuildMI, /*InsnID*/100, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61296 /* 183805 */ GIR_AddTempRegister, /*InsnID*/100, /*TempRegID*/99, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61297 /* 183810 */ GIR_AddSimpleTempRegister, /*InsnID*/100, /*TempRegID*/100,
61298 /* 183813 */ GIR_AddImm, /*InsnID*/100, /*Imm*/GIMT_Encode8(13107),
61299 /* 183823 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/100,
61300 /* 183825 */ GIR_MakeTempReg, /*TempRegID*/98, /*TypeID*/GILLT_s64,
61301 /* 183828 */ GIR_BuildMI, /*InsnID*/99, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61302 /* 183832 */ GIR_AddTempRegister, /*InsnID*/99, /*TempRegID*/98, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61303 /* 183837 */ GIR_AddSimpleTempRegister, /*InsnID*/99, /*TempRegID*/99,
61304 /* 183840 */ GIR_AddImm, /*InsnID*/99, /*Imm*/GIMT_Encode8(13107),
61305 /* 183850 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/99,
61306 /* 183852 */ GIR_MakeTempReg, /*TempRegID*/97, /*TypeID*/GILLT_s32,
61307 /* 183855 */ GIR_BuildMI, /*InsnID*/98, /*Opcode*/GIMT_Encode2(PPC::LIS),
61308 /* 183859 */ GIR_AddTempRegister, /*InsnID*/98, /*TempRegID*/97, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61309 /* 183864 */ GIR_AddImm, /*InsnID*/98, /*Imm*/GIMT_Encode8(43690),
61310 /* 183874 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/98,
61311 /* 183876 */ GIR_MakeTempReg, /*TempRegID*/96, /*TypeID*/GILLT_s32,
61312 /* 183879 */ GIR_BuildMI, /*InsnID*/97, /*Opcode*/GIMT_Encode2(PPC::ORI),
61313 /* 183883 */ GIR_AddTempRegister, /*InsnID*/97, /*TempRegID*/96, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61314 /* 183888 */ GIR_AddSimpleTempRegister, /*InsnID*/97, /*TempRegID*/97,
61315 /* 183891 */ GIR_AddImm, /*InsnID*/97, /*Imm*/GIMT_Encode8(43690),
61316 /* 183901 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/97,
61317 /* 183903 */ GIR_MakeTempReg, /*TempRegID*/95, /*TypeID*/GILLT_s64,
61318 /* 183906 */ GIR_BuildMI, /*InsnID*/96, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61319 /* 183910 */ GIR_AddTempRegister, /*InsnID*/96, /*TempRegID*/95, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61320 /* 183915 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/96,
61321 /* 183917 */ GIR_MakeTempReg, /*TempRegID*/94, /*TypeID*/GILLT_s64,
61322 /* 183920 */ GIR_BuildMI, /*InsnID*/95, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61323 /* 183924 */ GIR_AddTempRegister, /*InsnID*/95, /*TempRegID*/94, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61324 /* 183929 */ GIR_AddSimpleTempRegister, /*InsnID*/95, /*TempRegID*/95,
61325 /* 183932 */ GIR_AddSimpleTempRegister, /*InsnID*/95, /*TempRegID*/96,
61326 /* 183935 */ GIR_AddImm8, /*InsnID*/95, /*Imm*/1,
61327 /* 183938 */ GIR_ConstrainOperandRC, /*InsnID*/95, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61328 /* 183943 */ GIR_ConstrainOperandRC, /*InsnID*/95, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61329 /* 183948 */ GIR_ConstrainOperandRC, /*InsnID*/95, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61330 /* 183953 */ GIR_MakeTempReg, /*TempRegID*/93, /*TypeID*/GILLT_s64,
61331 /* 183956 */ GIR_BuildMI, /*InsnID*/94, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61332 /* 183960 */ GIR_AddTempRegister, /*InsnID*/94, /*TempRegID*/93, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61333 /* 183965 */ GIR_AddSimpleTempRegister, /*InsnID*/94, /*TempRegID*/94,
61334 /* 183968 */ GIR_AddImm8, /*InsnID*/94, /*Imm*/32,
61335 /* 183971 */ GIR_AddImm8, /*InsnID*/94, /*Imm*/31,
61336 /* 183974 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/94,
61337 /* 183976 */ GIR_MakeTempReg, /*TempRegID*/92, /*TypeID*/GILLT_s64,
61338 /* 183979 */ GIR_BuildMI, /*InsnID*/93, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61339 /* 183983 */ GIR_AddTempRegister, /*InsnID*/93, /*TempRegID*/92, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61340 /* 183988 */ GIR_AddSimpleTempRegister, /*InsnID*/93, /*TempRegID*/93,
61341 /* 183991 */ GIR_AddImm, /*InsnID*/93, /*Imm*/GIMT_Encode8(43690),
61342 /* 184001 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/93,
61343 /* 184003 */ GIR_MakeTempReg, /*TempRegID*/91, /*TypeID*/GILLT_s64,
61344 /* 184006 */ GIR_BuildMI, /*InsnID*/92, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61345 /* 184010 */ GIR_AddTempRegister, /*InsnID*/92, /*TempRegID*/91, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61346 /* 184015 */ GIR_AddSimpleTempRegister, /*InsnID*/92, /*TempRegID*/92,
61347 /* 184018 */ GIR_AddImm, /*InsnID*/92, /*Imm*/GIMT_Encode8(43690),
61348 /* 184028 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/92,
61349 /* 184030 */ GIR_MakeTempReg, /*TempRegID*/90, /*TypeID*/GILLT_s64,
61350 /* 184033 */ GIR_BuildMI, /*InsnID*/91, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61351 /* 184037 */ GIR_AddTempRegister, /*InsnID*/91, /*TempRegID*/90, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61352 /* 184042 */ GIR_Copy, /*NewInsnID*/91, /*OldInsnID*/0, /*OpIdx*/1, // A
61353 /* 184046 */ GIR_AddImm8, /*InsnID*/91, /*Imm*/1,
61354 /* 184049 */ GIR_AddImm8, /*InsnID*/91, /*Imm*/62,
61355 /* 184052 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/91,
61356 /* 184054 */ GIR_MakeTempReg, /*TempRegID*/89, /*TypeID*/GILLT_s64,
61357 /* 184057 */ GIR_BuildMI, /*InsnID*/90, /*Opcode*/GIMT_Encode2(PPC::AND8),
61358 /* 184061 */ GIR_AddTempRegister, /*InsnID*/90, /*TempRegID*/89, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61359 /* 184066 */ GIR_AddSimpleTempRegister, /*InsnID*/90, /*TempRegID*/90,
61360 /* 184069 */ GIR_AddSimpleTempRegister, /*InsnID*/90, /*TempRegID*/91,
61361 /* 184072 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/90,
61362 /* 184074 */ GIR_MakeTempReg, /*TempRegID*/88, /*TypeID*/GILLT_s32,
61363 /* 184077 */ GIR_BuildMI, /*InsnID*/89, /*Opcode*/GIMT_Encode2(PPC::LIS),
61364 /* 184081 */ GIR_AddTempRegister, /*InsnID*/89, /*TempRegID*/88, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61365 /* 184086 */ GIR_AddImm, /*InsnID*/89, /*Imm*/GIMT_Encode8(21845),
61366 /* 184096 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/89,
61367 /* 184098 */ GIR_MakeTempReg, /*TempRegID*/87, /*TypeID*/GILLT_s32,
61368 /* 184101 */ GIR_BuildMI, /*InsnID*/88, /*Opcode*/GIMT_Encode2(PPC::ORI),
61369 /* 184105 */ GIR_AddTempRegister, /*InsnID*/88, /*TempRegID*/87, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61370 /* 184110 */ GIR_AddSimpleTempRegister, /*InsnID*/88, /*TempRegID*/88,
61371 /* 184113 */ GIR_AddImm, /*InsnID*/88, /*Imm*/GIMT_Encode8(21845),
61372 /* 184123 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/88,
61373 /* 184125 */ GIR_MakeTempReg, /*TempRegID*/86, /*TypeID*/GILLT_s64,
61374 /* 184128 */ GIR_BuildMI, /*InsnID*/87, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61375 /* 184132 */ GIR_AddTempRegister, /*InsnID*/87, /*TempRegID*/86, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61376 /* 184137 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/87,
61377 /* 184139 */ GIR_MakeTempReg, /*TempRegID*/85, /*TypeID*/GILLT_s64,
61378 /* 184142 */ GIR_BuildMI, /*InsnID*/86, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61379 /* 184146 */ GIR_AddTempRegister, /*InsnID*/86, /*TempRegID*/85, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61380 /* 184151 */ GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/86,
61381 /* 184154 */ GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/87,
61382 /* 184157 */ GIR_AddImm8, /*InsnID*/86, /*Imm*/1,
61383 /* 184160 */ GIR_ConstrainOperandRC, /*InsnID*/86, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61384 /* 184165 */ GIR_ConstrainOperandRC, /*InsnID*/86, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61385 /* 184170 */ GIR_ConstrainOperandRC, /*InsnID*/86, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61386 /* 184175 */ GIR_MakeTempReg, /*TempRegID*/84, /*TypeID*/GILLT_s64,
61387 /* 184178 */ GIR_BuildMI, /*InsnID*/85, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61388 /* 184182 */ GIR_AddTempRegister, /*InsnID*/85, /*TempRegID*/84, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61389 /* 184187 */ GIR_AddSimpleTempRegister, /*InsnID*/85, /*TempRegID*/85,
61390 /* 184190 */ GIR_AddImm8, /*InsnID*/85, /*Imm*/32,
61391 /* 184193 */ GIR_AddImm8, /*InsnID*/85, /*Imm*/31,
61392 /* 184196 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/85,
61393 /* 184198 */ GIR_MakeTempReg, /*TempRegID*/83, /*TypeID*/GILLT_s64,
61394 /* 184201 */ GIR_BuildMI, /*InsnID*/84, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61395 /* 184205 */ GIR_AddTempRegister, /*InsnID*/84, /*TempRegID*/83, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61396 /* 184210 */ GIR_AddSimpleTempRegister, /*InsnID*/84, /*TempRegID*/84,
61397 /* 184213 */ GIR_AddImm, /*InsnID*/84, /*Imm*/GIMT_Encode8(21845),
61398 /* 184223 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/84,
61399 /* 184225 */ GIR_MakeTempReg, /*TempRegID*/82, /*TypeID*/GILLT_s64,
61400 /* 184228 */ GIR_BuildMI, /*InsnID*/83, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61401 /* 184232 */ GIR_AddTempRegister, /*InsnID*/83, /*TempRegID*/82, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61402 /* 184237 */ GIR_AddSimpleTempRegister, /*InsnID*/83, /*TempRegID*/83,
61403 /* 184240 */ GIR_AddImm, /*InsnID*/83, /*Imm*/GIMT_Encode8(21845),
61404 /* 184250 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/83,
61405 /* 184252 */ GIR_MakeTempReg, /*TempRegID*/81, /*TypeID*/GILLT_s64,
61406 /* 184255 */ GIR_BuildMI, /*InsnID*/82, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
61407 /* 184259 */ GIR_AddTempRegister, /*InsnID*/82, /*TempRegID*/81, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61408 /* 184264 */ GIR_Copy, /*NewInsnID*/82, /*OldInsnID*/0, /*OpIdx*/1, // A
61409 /* 184268 */ GIR_AddImm8, /*InsnID*/82, /*Imm*/63,
61410 /* 184271 */ GIR_AddImm8, /*InsnID*/82, /*Imm*/1,
61411 /* 184274 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/82,
61412 /* 184276 */ GIR_MakeTempReg, /*TempRegID*/80, /*TypeID*/GILLT_s64,
61413 /* 184279 */ GIR_BuildMI, /*InsnID*/81, /*Opcode*/GIMT_Encode2(PPC::AND8),
61414 /* 184283 */ GIR_AddTempRegister, /*InsnID*/81, /*TempRegID*/80, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61415 /* 184288 */ GIR_AddSimpleTempRegister, /*InsnID*/81, /*TempRegID*/81,
61416 /* 184291 */ GIR_AddSimpleTempRegister, /*InsnID*/81, /*TempRegID*/82,
61417 /* 184294 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/81,
61418 /* 184296 */ GIR_MakeTempReg, /*TempRegID*/79, /*TypeID*/GILLT_s64,
61419 /* 184299 */ GIR_BuildMI, /*InsnID*/80, /*Opcode*/GIMT_Encode2(PPC::OR8),
61420 /* 184303 */ GIR_AddTempRegister, /*InsnID*/80, /*TempRegID*/79, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61421 /* 184308 */ GIR_AddSimpleTempRegister, /*InsnID*/80, /*TempRegID*/80,
61422 /* 184311 */ GIR_AddSimpleTempRegister, /*InsnID*/80, /*TempRegID*/89,
61423 /* 184314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/80,
61424 /* 184316 */ GIR_MakeTempReg, /*TempRegID*/78, /*TypeID*/GILLT_s64,
61425 /* 184319 */ GIR_BuildMI, /*InsnID*/79, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
61426 /* 184323 */ GIR_AddTempRegister, /*InsnID*/79, /*TempRegID*/78, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61427 /* 184328 */ GIR_AddSimpleTempRegister, /*InsnID*/79, /*TempRegID*/79,
61428 /* 184331 */ GIR_AddImm8, /*InsnID*/79, /*Imm*/62,
61429 /* 184334 */ GIR_AddImm8, /*InsnID*/79, /*Imm*/2,
61430 /* 184337 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/79,
61431 /* 184339 */ GIR_MakeTempReg, /*TempRegID*/77, /*TypeID*/GILLT_s64,
61432 /* 184342 */ GIR_BuildMI, /*InsnID*/78, /*Opcode*/GIMT_Encode2(PPC::AND8),
61433 /* 184346 */ GIR_AddTempRegister, /*InsnID*/78, /*TempRegID*/77, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61434 /* 184351 */ GIR_AddSimpleTempRegister, /*InsnID*/78, /*TempRegID*/78,
61435 /* 184354 */ GIR_AddSimpleTempRegister, /*InsnID*/78, /*TempRegID*/98,
61436 /* 184357 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/78,
61437 /* 184359 */ GIR_MakeTempReg, /*TempRegID*/76, /*TypeID*/GILLT_s64,
61438 /* 184362 */ GIR_BuildMI, /*InsnID*/77, /*Opcode*/GIMT_Encode2(PPC::OR8),
61439 /* 184366 */ GIR_AddTempRegister, /*InsnID*/77, /*TempRegID*/76, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61440 /* 184371 */ GIR_AddSimpleTempRegister, /*InsnID*/77, /*TempRegID*/77,
61441 /* 184374 */ GIR_AddSimpleTempRegister, /*InsnID*/77, /*TempRegID*/105,
61442 /* 184377 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/77,
61443 /* 184379 */ GIR_MakeTempReg, /*TempRegID*/75, /*TypeID*/GILLT_s64,
61444 /* 184382 */ GIR_BuildMI, /*InsnID*/76, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61445 /* 184386 */ GIR_AddTempRegister, /*InsnID*/76, /*TempRegID*/75, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61446 /* 184391 */ GIR_AddSimpleTempRegister, /*InsnID*/76, /*TempRegID*/76,
61447 /* 184394 */ GIR_AddImm8, /*InsnID*/76, /*Imm*/4,
61448 /* 184397 */ GIR_AddImm8, /*InsnID*/76, /*Imm*/59,
61449 /* 184400 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/76,
61450 /* 184402 */ GIR_MakeTempReg, /*TempRegID*/74, /*TypeID*/GILLT_s64,
61451 /* 184405 */ GIR_BuildMI, /*InsnID*/75, /*Opcode*/GIMT_Encode2(PPC::AND8),
61452 /* 184409 */ GIR_AddTempRegister, /*InsnID*/75, /*TempRegID*/74, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61453 /* 184414 */ GIR_AddSimpleTempRegister, /*InsnID*/75, /*TempRegID*/75,
61454 /* 184417 */ GIR_AddSimpleTempRegister, /*InsnID*/75, /*TempRegID*//* 133(*/0x85, 0x01/*)*/,
61455 /* 184421 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/75,
61456 /* 184423 */ GIR_MakeTempReg, /*TempRegID*/73, /*TypeID*/GILLT_s32,
61457 /* 184426 */ GIR_BuildMI, /*InsnID*/74, /*Opcode*/GIMT_Encode2(PPC::LIS),
61458 /* 184430 */ GIR_AddTempRegister, /*InsnID*/74, /*TempRegID*/73, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61459 /* 184435 */ GIR_AddImm, /*InsnID*/74, /*Imm*/GIMT_Encode8(3855),
61460 /* 184445 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/74,
61461 /* 184447 */ GIR_MakeTempReg, /*TempRegID*/72, /*TypeID*/GILLT_s32,
61462 /* 184450 */ GIR_BuildMI, /*InsnID*/73, /*Opcode*/GIMT_Encode2(PPC::ORI),
61463 /* 184454 */ GIR_AddTempRegister, /*InsnID*/73, /*TempRegID*/72, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61464 /* 184459 */ GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/73,
61465 /* 184462 */ GIR_AddImm, /*InsnID*/73, /*Imm*/GIMT_Encode8(3855),
61466 /* 184472 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/73,
61467 /* 184474 */ GIR_MakeTempReg, /*TempRegID*/71, /*TypeID*/GILLT_s64,
61468 /* 184477 */ GIR_BuildMI, /*InsnID*/72, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61469 /* 184481 */ GIR_AddTempRegister, /*InsnID*/72, /*TempRegID*/71, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61470 /* 184486 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/72,
61471 /* 184488 */ GIR_MakeTempReg, /*TempRegID*/70, /*TypeID*/GILLT_s64,
61472 /* 184491 */ GIR_BuildMI, /*InsnID*/71, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61473 /* 184495 */ GIR_AddTempRegister, /*InsnID*/71, /*TempRegID*/70, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61474 /* 184500 */ GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/71,
61475 /* 184503 */ GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/72,
61476 /* 184506 */ GIR_AddImm8, /*InsnID*/71, /*Imm*/1,
61477 /* 184509 */ GIR_ConstrainOperandRC, /*InsnID*/71, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61478 /* 184514 */ GIR_ConstrainOperandRC, /*InsnID*/71, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61479 /* 184519 */ GIR_ConstrainOperandRC, /*InsnID*/71, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61480 /* 184524 */ GIR_MakeTempReg, /*TempRegID*/69, /*TypeID*/GILLT_s64,
61481 /* 184527 */ GIR_BuildMI, /*InsnID*/70, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61482 /* 184531 */ GIR_AddTempRegister, /*InsnID*/70, /*TempRegID*/69, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61483 /* 184536 */ GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/70,
61484 /* 184539 */ GIR_AddImm8, /*InsnID*/70, /*Imm*/32,
61485 /* 184542 */ GIR_AddImm8, /*InsnID*/70, /*Imm*/31,
61486 /* 184545 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/70,
61487 /* 184547 */ GIR_MakeTempReg, /*TempRegID*/68, /*TypeID*/GILLT_s64,
61488 /* 184550 */ GIR_BuildMI, /*InsnID*/69, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61489 /* 184554 */ GIR_AddTempRegister, /*InsnID*/69, /*TempRegID*/68, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61490 /* 184559 */ GIR_AddSimpleTempRegister, /*InsnID*/69, /*TempRegID*/69,
61491 /* 184562 */ GIR_AddImm, /*InsnID*/69, /*Imm*/GIMT_Encode8(3855),
61492 /* 184572 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/69,
61493 /* 184574 */ GIR_MakeTempReg, /*TempRegID*/67, /*TypeID*/GILLT_s64,
61494 /* 184577 */ GIR_BuildMI, /*InsnID*/68, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61495 /* 184581 */ GIR_AddTempRegister, /*InsnID*/68, /*TempRegID*/67, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61496 /* 184586 */ GIR_AddSimpleTempRegister, /*InsnID*/68, /*TempRegID*/68,
61497 /* 184589 */ GIR_AddImm, /*InsnID*/68, /*Imm*/GIMT_Encode8(3855),
61498 /* 184599 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/68,
61499 /* 184601 */ GIR_MakeTempReg, /*TempRegID*/66, /*TypeID*/GILLT_s32,
61500 /* 184604 */ GIR_BuildMI, /*InsnID*/67, /*Opcode*/GIMT_Encode2(PPC::LIS),
61501 /* 184608 */ GIR_AddTempRegister, /*InsnID*/67, /*TempRegID*/66, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61502 /* 184613 */ GIR_AddImm, /*InsnID*/67, /*Imm*/GIMT_Encode8(52428),
61503 /* 184623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/67,
61504 /* 184625 */ GIR_MakeTempReg, /*TempRegID*/65, /*TypeID*/GILLT_s32,
61505 /* 184628 */ GIR_BuildMI, /*InsnID*/66, /*Opcode*/GIMT_Encode2(PPC::ORI),
61506 /* 184632 */ GIR_AddTempRegister, /*InsnID*/66, /*TempRegID*/65, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61507 /* 184637 */ GIR_AddSimpleTempRegister, /*InsnID*/66, /*TempRegID*/66,
61508 /* 184640 */ GIR_AddImm, /*InsnID*/66, /*Imm*/GIMT_Encode8(52428),
61509 /* 184650 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/66,
61510 /* 184652 */ GIR_MakeTempReg, /*TempRegID*/64, /*TypeID*/GILLT_s64,
61511 /* 184655 */ GIR_BuildMI, /*InsnID*/65, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61512 /* 184659 */ GIR_AddTempRegister, /*InsnID*/65, /*TempRegID*/64, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61513 /* 184664 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/65,
61514 /* 184666 */ GIR_MakeTempReg, /*TempRegID*/63, /*TypeID*/GILLT_s64,
61515 /* 184669 */ GIR_BuildMI, /*InsnID*/64, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61516 /* 184673 */ GIR_AddTempRegister, /*InsnID*/64, /*TempRegID*/63, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61517 /* 184678 */ GIR_AddSimpleTempRegister, /*InsnID*/64, /*TempRegID*/64,
61518 /* 184681 */ GIR_AddSimpleTempRegister, /*InsnID*/64, /*TempRegID*/65,
61519 /* 184684 */ GIR_AddImm8, /*InsnID*/64, /*Imm*/1,
61520 /* 184687 */ GIR_ConstrainOperandRC, /*InsnID*/64, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61521 /* 184692 */ GIR_ConstrainOperandRC, /*InsnID*/64, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61522 /* 184697 */ GIR_ConstrainOperandRC, /*InsnID*/64, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61523 /* 184702 */ GIR_MakeTempReg, /*TempRegID*/62, /*TypeID*/GILLT_s64,
61524 /* 184705 */ GIR_BuildMI, /*InsnID*/63, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61525 /* 184709 */ GIR_AddTempRegister, /*InsnID*/63, /*TempRegID*/62, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61526 /* 184714 */ GIR_AddSimpleTempRegister, /*InsnID*/63, /*TempRegID*/63,
61527 /* 184717 */ GIR_AddImm8, /*InsnID*/63, /*Imm*/32,
61528 /* 184720 */ GIR_AddImm8, /*InsnID*/63, /*Imm*/31,
61529 /* 184723 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/63,
61530 /* 184725 */ GIR_MakeTempReg, /*TempRegID*/61, /*TypeID*/GILLT_s64,
61531 /* 184728 */ GIR_BuildMI, /*InsnID*/62, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61532 /* 184732 */ GIR_AddTempRegister, /*InsnID*/62, /*TempRegID*/61, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61533 /* 184737 */ GIR_AddSimpleTempRegister, /*InsnID*/62, /*TempRegID*/62,
61534 /* 184740 */ GIR_AddImm, /*InsnID*/62, /*Imm*/GIMT_Encode8(52428),
61535 /* 184750 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/62,
61536 /* 184752 */ GIR_MakeTempReg, /*TempRegID*/60, /*TypeID*/GILLT_s64,
61537 /* 184755 */ GIR_BuildMI, /*InsnID*/61, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61538 /* 184759 */ GIR_AddTempRegister, /*InsnID*/61, /*TempRegID*/60, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61539 /* 184764 */ GIR_AddSimpleTempRegister, /*InsnID*/61, /*TempRegID*/61,
61540 /* 184767 */ GIR_AddImm, /*InsnID*/61, /*Imm*/GIMT_Encode8(52428),
61541 /* 184777 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/61,
61542 /* 184779 */ GIR_MakeTempReg, /*TempRegID*/59, /*TypeID*/GILLT_s32,
61543 /* 184782 */ GIR_BuildMI, /*InsnID*/60, /*Opcode*/GIMT_Encode2(PPC::LIS),
61544 /* 184786 */ GIR_AddTempRegister, /*InsnID*/60, /*TempRegID*/59, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61545 /* 184791 */ GIR_AddImm, /*InsnID*/60, /*Imm*/GIMT_Encode8(43690),
61546 /* 184801 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/60,
61547 /* 184803 */ GIR_MakeTempReg, /*TempRegID*/58, /*TypeID*/GILLT_s32,
61548 /* 184806 */ GIR_BuildMI, /*InsnID*/59, /*Opcode*/GIMT_Encode2(PPC::ORI),
61549 /* 184810 */ GIR_AddTempRegister, /*InsnID*/59, /*TempRegID*/58, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61550 /* 184815 */ GIR_AddSimpleTempRegister, /*InsnID*/59, /*TempRegID*/59,
61551 /* 184818 */ GIR_AddImm, /*InsnID*/59, /*Imm*/GIMT_Encode8(43690),
61552 /* 184828 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/59,
61553 /* 184830 */ GIR_MakeTempReg, /*TempRegID*/57, /*TypeID*/GILLT_s64,
61554 /* 184833 */ GIR_BuildMI, /*InsnID*/58, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61555 /* 184837 */ GIR_AddTempRegister, /*InsnID*/58, /*TempRegID*/57, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61556 /* 184842 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/58,
61557 /* 184844 */ GIR_MakeTempReg, /*TempRegID*/56, /*TypeID*/GILLT_s64,
61558 /* 184847 */ GIR_BuildMI, /*InsnID*/57, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61559 /* 184851 */ GIR_AddTempRegister, /*InsnID*/57, /*TempRegID*/56, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61560 /* 184856 */ GIR_AddSimpleTempRegister, /*InsnID*/57, /*TempRegID*/57,
61561 /* 184859 */ GIR_AddSimpleTempRegister, /*InsnID*/57, /*TempRegID*/58,
61562 /* 184862 */ GIR_AddImm8, /*InsnID*/57, /*Imm*/1,
61563 /* 184865 */ GIR_ConstrainOperandRC, /*InsnID*/57, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61564 /* 184870 */ GIR_ConstrainOperandRC, /*InsnID*/57, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61565 /* 184875 */ GIR_ConstrainOperandRC, /*InsnID*/57, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61566 /* 184880 */ GIR_MakeTempReg, /*TempRegID*/55, /*TypeID*/GILLT_s64,
61567 /* 184883 */ GIR_BuildMI, /*InsnID*/56, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61568 /* 184887 */ GIR_AddTempRegister, /*InsnID*/56, /*TempRegID*/55, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61569 /* 184892 */ GIR_AddSimpleTempRegister, /*InsnID*/56, /*TempRegID*/56,
61570 /* 184895 */ GIR_AddImm8, /*InsnID*/56, /*Imm*/32,
61571 /* 184898 */ GIR_AddImm8, /*InsnID*/56, /*Imm*/31,
61572 /* 184901 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/56,
61573 /* 184903 */ GIR_MakeTempReg, /*TempRegID*/54, /*TypeID*/GILLT_s64,
61574 /* 184906 */ GIR_BuildMI, /*InsnID*/55, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61575 /* 184910 */ GIR_AddTempRegister, /*InsnID*/55, /*TempRegID*/54, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61576 /* 184915 */ GIR_AddSimpleTempRegister, /*InsnID*/55, /*TempRegID*/55,
61577 /* 184918 */ GIR_AddImm, /*InsnID*/55, /*Imm*/GIMT_Encode8(43690),
61578 /* 184928 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/55,
61579 /* 184930 */ GIR_MakeTempReg, /*TempRegID*/53, /*TypeID*/GILLT_s64,
61580 /* 184933 */ GIR_BuildMI, /*InsnID*/54, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61581 /* 184937 */ GIR_AddTempRegister, /*InsnID*/54, /*TempRegID*/53, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61582 /* 184942 */ GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/54,
61583 /* 184945 */ GIR_AddImm, /*InsnID*/54, /*Imm*/GIMT_Encode8(43690),
61584 /* 184955 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/54,
61585 /* 184957 */ GIR_MakeTempReg, /*TempRegID*/52, /*TypeID*/GILLT_s64,
61586 /* 184960 */ GIR_BuildMI, /*InsnID*/53, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61587 /* 184964 */ GIR_AddTempRegister, /*InsnID*/53, /*TempRegID*/52, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61588 /* 184969 */ GIR_Copy, /*NewInsnID*/53, /*OldInsnID*/0, /*OpIdx*/1, // A
61589 /* 184973 */ GIR_AddImm8, /*InsnID*/53, /*Imm*/1,
61590 /* 184976 */ GIR_AddImm8, /*InsnID*/53, /*Imm*/62,
61591 /* 184979 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/53,
61592 /* 184981 */ GIR_MakeTempReg, /*TempRegID*/51, /*TypeID*/GILLT_s64,
61593 /* 184984 */ GIR_BuildMI, /*InsnID*/52, /*Opcode*/GIMT_Encode2(PPC::AND8),
61594 /* 184988 */ GIR_AddTempRegister, /*InsnID*/52, /*TempRegID*/51, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61595 /* 184993 */ GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/52,
61596 /* 184996 */ GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/53,
61597 /* 184999 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/52,
61598 /* 185001 */ GIR_MakeTempReg, /*TempRegID*/50, /*TypeID*/GILLT_s32,
61599 /* 185004 */ GIR_BuildMI, /*InsnID*/51, /*Opcode*/GIMT_Encode2(PPC::LIS),
61600 /* 185008 */ GIR_AddTempRegister, /*InsnID*/51, /*TempRegID*/50, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61601 /* 185013 */ GIR_AddImm, /*InsnID*/51, /*Imm*/GIMT_Encode8(21845),
61602 /* 185023 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/51,
61603 /* 185025 */ GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_s32,
61604 /* 185028 */ GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(PPC::ORI),
61605 /* 185032 */ GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61606 /* 185037 */ GIR_AddSimpleTempRegister, /*InsnID*/50, /*TempRegID*/50,
61607 /* 185040 */ GIR_AddImm, /*InsnID*/50, /*Imm*/GIMT_Encode8(21845),
61608 /* 185050 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
61609 /* 185052 */ GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_s64,
61610 /* 185055 */ GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61611 /* 185059 */ GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61612 /* 185064 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
61613 /* 185066 */ GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_s64,
61614 /* 185069 */ GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61615 /* 185073 */ GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61616 /* 185078 */ GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
61617 /* 185081 */ GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
61618 /* 185084 */ GIR_AddImm8, /*InsnID*/48, /*Imm*/1,
61619 /* 185087 */ GIR_ConstrainOperandRC, /*InsnID*/48, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61620 /* 185092 */ GIR_ConstrainOperandRC, /*InsnID*/48, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61621 /* 185097 */ GIR_ConstrainOperandRC, /*InsnID*/48, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61622 /* 185102 */ GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s64,
61623 /* 185105 */ GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61624 /* 185109 */ GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61625 /* 185114 */ GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
61626 /* 185117 */ GIR_AddImm8, /*InsnID*/47, /*Imm*/32,
61627 /* 185120 */ GIR_AddImm8, /*InsnID*/47, /*Imm*/31,
61628 /* 185123 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
61629 /* 185125 */ GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s64,
61630 /* 185128 */ GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61631 /* 185132 */ GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61632 /* 185137 */ GIR_AddSimpleTempRegister, /*InsnID*/46, /*TempRegID*/46,
61633 /* 185140 */ GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(21845),
61634 /* 185150 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
61635 /* 185152 */ GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s64,
61636 /* 185155 */ GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61637 /* 185159 */ GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61638 /* 185164 */ GIR_AddSimpleTempRegister, /*InsnID*/45, /*TempRegID*/45,
61639 /* 185167 */ GIR_AddImm, /*InsnID*/45, /*Imm*/GIMT_Encode8(21845),
61640 /* 185177 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
61641 /* 185179 */ GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s64,
61642 /* 185182 */ GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
61643 /* 185186 */ GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61644 /* 185191 */ GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // A
61645 /* 185195 */ GIR_AddImm8, /*InsnID*/44, /*Imm*/63,
61646 /* 185198 */ GIR_AddImm8, /*InsnID*/44, /*Imm*/1,
61647 /* 185201 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
61648 /* 185203 */ GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s64,
61649 /* 185206 */ GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(PPC::AND8),
61650 /* 185210 */ GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61651 /* 185215 */ GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
61652 /* 185218 */ GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
61653 /* 185221 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
61654 /* 185223 */ GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_s64,
61655 /* 185226 */ GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(PPC::OR8),
61656 /* 185230 */ GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61657 /* 185235 */ GIR_AddSimpleTempRegister, /*InsnID*/42, /*TempRegID*/42,
61658 /* 185238 */ GIR_AddSimpleTempRegister, /*InsnID*/42, /*TempRegID*/51,
61659 /* 185241 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
61660 /* 185243 */ GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_s64,
61661 /* 185246 */ GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61662 /* 185250 */ GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61663 /* 185255 */ GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/41,
61664 /* 185258 */ GIR_AddImm8, /*InsnID*/41, /*Imm*/2,
61665 /* 185261 */ GIR_AddImm8, /*InsnID*/41, /*Imm*/61,
61666 /* 185264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
61667 /* 185266 */ GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_s64,
61668 /* 185269 */ GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(PPC::AND8),
61669 /* 185273 */ GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61670 /* 185278 */ GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
61671 /* 185281 */ GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/60,
61672 /* 185284 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
61673 /* 185286 */ GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s32,
61674 /* 185289 */ GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(PPC::LIS),
61675 /* 185293 */ GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61676 /* 185298 */ GIR_AddImm, /*InsnID*/39, /*Imm*/GIMT_Encode8(13107),
61677 /* 185308 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
61678 /* 185310 */ GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s32,
61679 /* 185313 */ GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(PPC::ORI),
61680 /* 185317 */ GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61681 /* 185322 */ GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
61682 /* 185325 */ GIR_AddImm, /*InsnID*/38, /*Imm*/GIMT_Encode8(13107),
61683 /* 185335 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
61684 /* 185337 */ GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_s64,
61685 /* 185340 */ GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61686 /* 185344 */ GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61687 /* 185349 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
61688 /* 185351 */ GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s64,
61689 /* 185354 */ GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61690 /* 185358 */ GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61691 /* 185363 */ GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
61692 /* 185366 */ GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/37,
61693 /* 185369 */ GIR_AddImm8, /*InsnID*/36, /*Imm*/1,
61694 /* 185372 */ GIR_ConstrainOperandRC, /*InsnID*/36, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61695 /* 185377 */ GIR_ConstrainOperandRC, /*InsnID*/36, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61696 /* 185382 */ GIR_ConstrainOperandRC, /*InsnID*/36, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61697 /* 185387 */ GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s64,
61698 /* 185390 */ GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61699 /* 185394 */ GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61700 /* 185399 */ GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
61701 /* 185402 */ GIR_AddImm8, /*InsnID*/35, /*Imm*/32,
61702 /* 185405 */ GIR_AddImm8, /*InsnID*/35, /*Imm*/31,
61703 /* 185408 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
61704 /* 185410 */ GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s64,
61705 /* 185413 */ GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61706 /* 185417 */ GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61707 /* 185422 */ GIR_AddSimpleTempRegister, /*InsnID*/34, /*TempRegID*/34,
61708 /* 185425 */ GIR_AddImm, /*InsnID*/34, /*Imm*/GIMT_Encode8(13107),
61709 /* 185435 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
61710 /* 185437 */ GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s64,
61711 /* 185440 */ GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61712 /* 185444 */ GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61713 /* 185449 */ GIR_AddSimpleTempRegister, /*InsnID*/33, /*TempRegID*/33,
61714 /* 185452 */ GIR_AddImm, /*InsnID*/33, /*Imm*/GIMT_Encode8(13107),
61715 /* 185462 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
61716 /* 185464 */ GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s32,
61717 /* 185467 */ GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(PPC::LIS),
61718 /* 185471 */ GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61719 /* 185476 */ GIR_AddImm, /*InsnID*/32, /*Imm*/GIMT_Encode8(43690),
61720 /* 185486 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
61721 /* 185488 */ GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s32,
61722 /* 185491 */ GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(PPC::ORI),
61723 /* 185495 */ GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61724 /* 185500 */ GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
61725 /* 185503 */ GIR_AddImm, /*InsnID*/31, /*Imm*/GIMT_Encode8(43690),
61726 /* 185513 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
61727 /* 185515 */ GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s64,
61728 /* 185518 */ GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61729 /* 185522 */ GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61730 /* 185527 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
61731 /* 185529 */ GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s64,
61732 /* 185532 */ GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61733 /* 185536 */ GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61734 /* 185541 */ GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
61735 /* 185544 */ GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/30,
61736 /* 185547 */ GIR_AddImm8, /*InsnID*/29, /*Imm*/1,
61737 /* 185550 */ GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61738 /* 185555 */ GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61739 /* 185560 */ GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61740 /* 185565 */ GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s64,
61741 /* 185568 */ GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61742 /* 185572 */ GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61743 /* 185577 */ GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
61744 /* 185580 */ GIR_AddImm8, /*InsnID*/28, /*Imm*/32,
61745 /* 185583 */ GIR_AddImm8, /*InsnID*/28, /*Imm*/31,
61746 /* 185586 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
61747 /* 185588 */ GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_s64,
61748 /* 185591 */ GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61749 /* 185595 */ GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61750 /* 185600 */ GIR_AddSimpleTempRegister, /*InsnID*/27, /*TempRegID*/27,
61751 /* 185603 */ GIR_AddImm, /*InsnID*/27, /*Imm*/GIMT_Encode8(43690),
61752 /* 185613 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
61753 /* 185615 */ GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_s64,
61754 /* 185618 */ GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61755 /* 185622 */ GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61756 /* 185627 */ GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
61757 /* 185630 */ GIR_AddImm, /*InsnID*/26, /*Imm*/GIMT_Encode8(43690),
61758 /* 185640 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
61759 /* 185642 */ GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_s64,
61760 /* 185645 */ GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61761 /* 185649 */ GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61762 /* 185654 */ GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // A
61763 /* 185658 */ GIR_AddImm8, /*InsnID*/25, /*Imm*/1,
61764 /* 185661 */ GIR_AddImm8, /*InsnID*/25, /*Imm*/62,
61765 /* 185664 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
61766 /* 185666 */ GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s64,
61767 /* 185669 */ GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(PPC::AND8),
61768 /* 185673 */ GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61769 /* 185678 */ GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
61770 /* 185681 */ GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/25,
61771 /* 185684 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
61772 /* 185686 */ GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s32,
61773 /* 185689 */ GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(PPC::LIS),
61774 /* 185693 */ GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61775 /* 185698 */ GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(21845),
61776 /* 185708 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
61777 /* 185710 */ GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s32,
61778 /* 185713 */ GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(PPC::ORI),
61779 /* 185717 */ GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61780 /* 185722 */ GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
61781 /* 185725 */ GIR_AddImm, /*InsnID*/22, /*Imm*/GIMT_Encode8(21845),
61782 /* 185735 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
61783 /* 185737 */ GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s64,
61784 /* 185740 */ GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61785 /* 185744 */ GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61786 /* 185749 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
61787 /* 185751 */ GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s64,
61788 /* 185754 */ GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61789 /* 185758 */ GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61790 /* 185763 */ GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
61791 /* 185766 */ GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
61792 /* 185769 */ GIR_AddImm8, /*InsnID*/20, /*Imm*/1,
61793 /* 185772 */ GIR_ConstrainOperandRC, /*InsnID*/20, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61794 /* 185777 */ GIR_ConstrainOperandRC, /*InsnID*/20, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61795 /* 185782 */ GIR_ConstrainOperandRC, /*InsnID*/20, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61796 /* 185787 */ GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_s64,
61797 /* 185790 */ GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61798 /* 185794 */ GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61799 /* 185799 */ GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
61800 /* 185802 */ GIR_AddImm8, /*InsnID*/19, /*Imm*/32,
61801 /* 185805 */ GIR_AddImm8, /*InsnID*/19, /*Imm*/31,
61802 /* 185808 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
61803 /* 185810 */ GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s64,
61804 /* 185813 */ GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61805 /* 185817 */ GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61806 /* 185822 */ GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
61807 /* 185825 */ GIR_AddImm, /*InsnID*/18, /*Imm*/GIMT_Encode8(21845),
61808 /* 185835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
61809 /* 185837 */ GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s64,
61810 /* 185840 */ GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61811 /* 185844 */ GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61812 /* 185849 */ GIR_AddSimpleTempRegister, /*InsnID*/17, /*TempRegID*/17,
61813 /* 185852 */ GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(21845),
61814 /* 185862 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
61815 /* 185864 */ GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s64,
61816 /* 185867 */ GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
61817 /* 185871 */ GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61818 /* 185876 */ GIR_Copy, /*NewInsnID*/16, /*OldInsnID*/0, /*OpIdx*/1, // A
61819 /* 185880 */ GIR_AddImm8, /*InsnID*/16, /*Imm*/63,
61820 /* 185883 */ GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
61821 /* 185886 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
61822 /* 185888 */ GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s64,
61823 /* 185891 */ GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(PPC::AND8),
61824 /* 185895 */ GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61825 /* 185900 */ GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
61826 /* 185903 */ GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/16,
61827 /* 185906 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
61828 /* 185908 */ GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s64,
61829 /* 185911 */ GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(PPC::OR8),
61830 /* 185915 */ GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61831 /* 185920 */ GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
61832 /* 185923 */ GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/23,
61833 /* 185926 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
61834 /* 185928 */ GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s64,
61835 /* 185931 */ GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
61836 /* 185935 */ GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61837 /* 185940 */ GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
61838 /* 185943 */ GIR_AddImm8, /*InsnID*/13, /*Imm*/62,
61839 /* 185946 */ GIR_AddImm8, /*InsnID*/13, /*Imm*/2,
61840 /* 185949 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
61841 /* 185951 */ GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s64,
61842 /* 185954 */ GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(PPC::AND8),
61843 /* 185958 */ GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61844 /* 185963 */ GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
61845 /* 185966 */ GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/32,
61846 /* 185969 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
61847 /* 185971 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s64,
61848 /* 185974 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(PPC::OR8),
61849 /* 185978 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61850 /* 185983 */ GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
61851 /* 185986 */ GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/39,
61852 /* 185989 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
61853 /* 185991 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s64,
61854 /* 185994 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
61855 /* 185998 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61856 /* 186003 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
61857 /* 186006 */ GIR_AddImm8, /*InsnID*/10, /*Imm*/60,
61858 /* 186009 */ GIR_AddImm8, /*InsnID*/10, /*Imm*/4,
61859 /* 186012 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
61860 /* 186014 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s64,
61861 /* 186017 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(PPC::AND8),
61862 /* 186021 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61863 /* 186026 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
61864 /* 186029 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/67,
61865 /* 186032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
61866 /* 186034 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s64,
61867 /* 186037 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(PPC::OR8),
61868 /* 186041 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61869 /* 186046 */ GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
61870 /* 186049 */ GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/74,
61871 /* 186052 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
61872 /* 186054 */ GIR_MakeTempReg, /*TempRegID*//* 273(*/0x91, 0x02/*)*/, /*TypeID*/GILLT_s32,
61873 /* 186058 */ GIR_BuildMI, /*InsnID*//* 274(*/0x92, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
61874 /* 186063 */ GIR_AddTempRegister, /*InsnID*//* 274(*/0x92, 0x02/*)*/, /*TempRegID*//* 273(*/0x91, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61875 /* 186070 */ GIR_AddImm, /*InsnID*//* 274(*/0x92, 0x02/*)*/, /*Imm*/GIMT_Encode8(61680),
61876 /* 186081 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 274(*/0x92, 0x02/*)*/,
61877 /* 186084 */ GIR_MakeTempReg, /*TempRegID*//* 272(*/0x90, 0x02/*)*/, /*TypeID*/GILLT_s32,
61878 /* 186088 */ GIR_BuildMI, /*InsnID*//* 273(*/0x91, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
61879 /* 186093 */ GIR_AddTempRegister, /*InsnID*//* 273(*/0x91, 0x02/*)*/, /*TempRegID*//* 272(*/0x90, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61880 /* 186100 */ GIR_AddSimpleTempRegister, /*InsnID*//* 273(*/0x91, 0x02/*)*/, /*TempRegID*//* 273(*/0x91, 0x02/*)*/,
61881 /* 186105 */ GIR_AddImm, /*InsnID*//* 273(*/0x91, 0x02/*)*/, /*Imm*/GIMT_Encode8(61680),
61882 /* 186116 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 273(*/0x91, 0x02/*)*/,
61883 /* 186119 */ GIR_MakeTempReg, /*TempRegID*//* 271(*/0x8F, 0x02/*)*/, /*TypeID*/GILLT_s64,
61884 /* 186123 */ GIR_BuildMI, /*InsnID*//* 272(*/0x90, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61885 /* 186128 */ GIR_AddTempRegister, /*InsnID*//* 272(*/0x90, 0x02/*)*/, /*TempRegID*//* 271(*/0x8F, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61886 /* 186135 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 272(*/0x90, 0x02/*)*/,
61887 /* 186138 */ GIR_MakeTempReg, /*TempRegID*//* 270(*/0x8E, 0x02/*)*/, /*TypeID*/GILLT_s64,
61888 /* 186142 */ GIR_BuildMI, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61889 /* 186147 */ GIR_AddTempRegister, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*TempRegID*//* 270(*/0x8E, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61890 /* 186154 */ GIR_AddSimpleTempRegister, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*TempRegID*//* 271(*/0x8F, 0x02/*)*/,
61891 /* 186159 */ GIR_AddSimpleTempRegister, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*TempRegID*//* 272(*/0x90, 0x02/*)*/,
61892 /* 186164 */ GIR_AddImm8, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Imm*/1,
61893 /* 186168 */ GIR_ConstrainOperandRC, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61894 /* 186174 */ GIR_ConstrainOperandRC, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61895 /* 186180 */ GIR_ConstrainOperandRC, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61896 /* 186186 */ GIR_MakeTempReg, /*TempRegID*//* 269(*/0x8D, 0x02/*)*/, /*TypeID*/GILLT_s64,
61897 /* 186190 */ GIR_BuildMI, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61898 /* 186195 */ GIR_AddTempRegister, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*TempRegID*//* 269(*/0x8D, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61899 /* 186202 */ GIR_AddSimpleTempRegister, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*TempRegID*//* 270(*/0x8E, 0x02/*)*/,
61900 /* 186207 */ GIR_AddImm8, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*Imm*/32,
61901 /* 186211 */ GIR_AddImm8, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*Imm*/31,
61902 /* 186215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 270(*/0x8E, 0x02/*)*/,
61903 /* 186218 */ GIR_MakeTempReg, /*TempRegID*//* 268(*/0x8C, 0x02/*)*/, /*TypeID*/GILLT_s64,
61904 /* 186222 */ GIR_BuildMI, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61905 /* 186227 */ GIR_AddTempRegister, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, /*TempRegID*//* 268(*/0x8C, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61906 /* 186234 */ GIR_AddSimpleTempRegister, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, /*TempRegID*//* 269(*/0x8D, 0x02/*)*/,
61907 /* 186239 */ GIR_AddImm, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, /*Imm*/GIMT_Encode8(61680),
61908 /* 186250 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 269(*/0x8D, 0x02/*)*/,
61909 /* 186253 */ GIR_MakeTempReg, /*TempRegID*//* 267(*/0x8B, 0x02/*)*/, /*TypeID*/GILLT_s64,
61910 /* 186257 */ GIR_BuildMI, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61911 /* 186262 */ GIR_AddTempRegister, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, /*TempRegID*//* 267(*/0x8B, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61912 /* 186269 */ GIR_AddSimpleTempRegister, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, /*TempRegID*//* 268(*/0x8C, 0x02/*)*/,
61913 /* 186274 */ GIR_AddImm, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, /*Imm*/GIMT_Encode8(61680),
61914 /* 186285 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 268(*/0x8C, 0x02/*)*/,
61915 /* 186288 */ GIR_MakeTempReg, /*TempRegID*//* 266(*/0x8A, 0x02/*)*/, /*TypeID*/GILLT_s32,
61916 /* 186292 */ GIR_BuildMI, /*InsnID*//* 267(*/0x8B, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
61917 /* 186297 */ GIR_AddTempRegister, /*InsnID*//* 267(*/0x8B, 0x02/*)*/, /*TempRegID*//* 266(*/0x8A, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61918 /* 186304 */ GIR_AddImm, /*InsnID*//* 267(*/0x8B, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428),
61919 /* 186315 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 267(*/0x8B, 0x02/*)*/,
61920 /* 186318 */ GIR_MakeTempReg, /*TempRegID*//* 265(*/0x89, 0x02/*)*/, /*TypeID*/GILLT_s32,
61921 /* 186322 */ GIR_BuildMI, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
61922 /* 186327 */ GIR_AddTempRegister, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, /*TempRegID*//* 265(*/0x89, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61923 /* 186334 */ GIR_AddSimpleTempRegister, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, /*TempRegID*//* 266(*/0x8A, 0x02/*)*/,
61924 /* 186339 */ GIR_AddImm, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428),
61925 /* 186350 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 266(*/0x8A, 0x02/*)*/,
61926 /* 186353 */ GIR_MakeTempReg, /*TempRegID*//* 264(*/0x88, 0x02/*)*/, /*TypeID*/GILLT_s64,
61927 /* 186357 */ GIR_BuildMI, /*InsnID*//* 265(*/0x89, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61928 /* 186362 */ GIR_AddTempRegister, /*InsnID*//* 265(*/0x89, 0x02/*)*/, /*TempRegID*//* 264(*/0x88, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61929 /* 186369 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 265(*/0x89, 0x02/*)*/,
61930 /* 186372 */ GIR_MakeTempReg, /*TempRegID*//* 263(*/0x87, 0x02/*)*/, /*TypeID*/GILLT_s64,
61931 /* 186376 */ GIR_BuildMI, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61932 /* 186381 */ GIR_AddTempRegister, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*TempRegID*//* 263(*/0x87, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61933 /* 186388 */ GIR_AddSimpleTempRegister, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*TempRegID*//* 264(*/0x88, 0x02/*)*/,
61934 /* 186393 */ GIR_AddSimpleTempRegister, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*TempRegID*//* 265(*/0x89, 0x02/*)*/,
61935 /* 186398 */ GIR_AddImm8, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Imm*/1,
61936 /* 186402 */ GIR_ConstrainOperandRC, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61937 /* 186408 */ GIR_ConstrainOperandRC, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61938 /* 186414 */ GIR_ConstrainOperandRC, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61939 /* 186420 */ GIR_MakeTempReg, /*TempRegID*//* 262(*/0x86, 0x02/*)*/, /*TypeID*/GILLT_s64,
61940 /* 186424 */ GIR_BuildMI, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61941 /* 186429 */ GIR_AddTempRegister, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*TempRegID*//* 262(*/0x86, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61942 /* 186436 */ GIR_AddSimpleTempRegister, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*TempRegID*//* 263(*/0x87, 0x02/*)*/,
61943 /* 186441 */ GIR_AddImm8, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*Imm*/32,
61944 /* 186445 */ GIR_AddImm8, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*Imm*/31,
61945 /* 186449 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 263(*/0x87, 0x02/*)*/,
61946 /* 186452 */ GIR_MakeTempReg, /*TempRegID*//* 261(*/0x85, 0x02/*)*/, /*TypeID*/GILLT_s64,
61947 /* 186456 */ GIR_BuildMI, /*InsnID*//* 262(*/0x86, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61948 /* 186461 */ GIR_AddTempRegister, /*InsnID*//* 262(*/0x86, 0x02/*)*/, /*TempRegID*//* 261(*/0x85, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61949 /* 186468 */ GIR_AddSimpleTempRegister, /*InsnID*//* 262(*/0x86, 0x02/*)*/, /*TempRegID*//* 262(*/0x86, 0x02/*)*/,
61950 /* 186473 */ GIR_AddImm, /*InsnID*//* 262(*/0x86, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428),
61951 /* 186484 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 262(*/0x86, 0x02/*)*/,
61952 /* 186487 */ GIR_MakeTempReg, /*TempRegID*//* 260(*/0x84, 0x02/*)*/, /*TypeID*/GILLT_s64,
61953 /* 186491 */ GIR_BuildMI, /*InsnID*//* 261(*/0x85, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61954 /* 186496 */ GIR_AddTempRegister, /*InsnID*//* 261(*/0x85, 0x02/*)*/, /*TempRegID*//* 260(*/0x84, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61955 /* 186503 */ GIR_AddSimpleTempRegister, /*InsnID*//* 261(*/0x85, 0x02/*)*/, /*TempRegID*//* 261(*/0x85, 0x02/*)*/,
61956 /* 186508 */ GIR_AddImm, /*InsnID*//* 261(*/0x85, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428),
61957 /* 186519 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 261(*/0x85, 0x02/*)*/,
61958 /* 186522 */ GIR_MakeTempReg, /*TempRegID*//* 259(*/0x83, 0x02/*)*/, /*TypeID*/GILLT_s32,
61959 /* 186526 */ GIR_BuildMI, /*InsnID*//* 260(*/0x84, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
61960 /* 186531 */ GIR_AddTempRegister, /*InsnID*//* 260(*/0x84, 0x02/*)*/, /*TempRegID*//* 259(*/0x83, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61961 /* 186538 */ GIR_AddImm, /*InsnID*//* 260(*/0x84, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
61962 /* 186549 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 260(*/0x84, 0x02/*)*/,
61963 /* 186552 */ GIR_MakeTempReg, /*TempRegID*//* 258(*/0x82, 0x02/*)*/, /*TypeID*/GILLT_s32,
61964 /* 186556 */ GIR_BuildMI, /*InsnID*//* 259(*/0x83, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
61965 /* 186561 */ GIR_AddTempRegister, /*InsnID*//* 259(*/0x83, 0x02/*)*/, /*TempRegID*//* 258(*/0x82, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61966 /* 186568 */ GIR_AddSimpleTempRegister, /*InsnID*//* 259(*/0x83, 0x02/*)*/, /*TempRegID*//* 259(*/0x83, 0x02/*)*/,
61967 /* 186573 */ GIR_AddImm, /*InsnID*//* 259(*/0x83, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
61968 /* 186584 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 259(*/0x83, 0x02/*)*/,
61969 /* 186587 */ GIR_MakeTempReg, /*TempRegID*//* 257(*/0x81, 0x02/*)*/, /*TypeID*/GILLT_s64,
61970 /* 186591 */ GIR_BuildMI, /*InsnID*//* 258(*/0x82, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
61971 /* 186596 */ GIR_AddTempRegister, /*InsnID*//* 258(*/0x82, 0x02/*)*/, /*TempRegID*//* 257(*/0x81, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61972 /* 186603 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 258(*/0x82, 0x02/*)*/,
61973 /* 186606 */ GIR_MakeTempReg, /*TempRegID*//* 256(*/0x80, 0x02/*)*/, /*TypeID*/GILLT_s64,
61974 /* 186610 */ GIR_BuildMI, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
61975 /* 186615 */ GIR_AddTempRegister, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*TempRegID*//* 256(*/0x80, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61976 /* 186622 */ GIR_AddSimpleTempRegister, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*TempRegID*//* 257(*/0x81, 0x02/*)*/,
61977 /* 186627 */ GIR_AddSimpleTempRegister, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*TempRegID*//* 258(*/0x82, 0x02/*)*/,
61978 /* 186632 */ GIR_AddImm8, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Imm*/1,
61979 /* 186636 */ GIR_ConstrainOperandRC, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
61980 /* 186642 */ GIR_ConstrainOperandRC, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
61981 /* 186648 */ GIR_ConstrainOperandRC, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
61982 /* 186654 */ GIR_MakeTempReg, /*TempRegID*//* 255(*/0xFF, 0x01/*)*/, /*TypeID*/GILLT_s64,
61983 /* 186658 */ GIR_BuildMI, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
61984 /* 186663 */ GIR_AddTempRegister, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*TempRegID*//* 255(*/0xFF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61985 /* 186670 */ GIR_AddSimpleTempRegister, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*TempRegID*//* 256(*/0x80, 0x02/*)*/,
61986 /* 186675 */ GIR_AddImm8, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*Imm*/32,
61987 /* 186679 */ GIR_AddImm8, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*Imm*/31,
61988 /* 186683 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 256(*/0x80, 0x02/*)*/,
61989 /* 186686 */ GIR_MakeTempReg, /*TempRegID*//* 254(*/0xFE, 0x01/*)*/, /*TypeID*/GILLT_s64,
61990 /* 186690 */ GIR_BuildMI, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
61991 /* 186695 */ GIR_AddTempRegister, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, /*TempRegID*//* 254(*/0xFE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61992 /* 186702 */ GIR_AddSimpleTempRegister, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, /*TempRegID*//* 255(*/0xFF, 0x01/*)*/,
61993 /* 186707 */ GIR_AddImm, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
61994 /* 186718 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 255(*/0xFF, 0x01/*)*/,
61995 /* 186721 */ GIR_MakeTempReg, /*TempRegID*//* 253(*/0xFD, 0x01/*)*/, /*TypeID*/GILLT_s64,
61996 /* 186725 */ GIR_BuildMI, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
61997 /* 186730 */ GIR_AddTempRegister, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, /*TempRegID*//* 253(*/0xFD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
61998 /* 186737 */ GIR_AddSimpleTempRegister, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, /*TempRegID*//* 254(*/0xFE, 0x01/*)*/,
61999 /* 186742 */ GIR_AddImm, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62000 /* 186753 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 254(*/0xFE, 0x01/*)*/,
62001 /* 186756 */ GIR_MakeTempReg, /*TempRegID*//* 252(*/0xFC, 0x01/*)*/, /*TypeID*/GILLT_s64,
62002 /* 186760 */ GIR_BuildMI, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62003 /* 186765 */ GIR_AddTempRegister, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, /*TempRegID*//* 252(*/0xFC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62004 /* 186772 */ GIR_Copy, /*NewInsnID*//* 253(*/0xFD, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62005 /* 186777 */ GIR_AddImm8, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, /*Imm*/1,
62006 /* 186781 */ GIR_AddImm8, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, /*Imm*/62,
62007 /* 186785 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 253(*/0xFD, 0x01/*)*/,
62008 /* 186788 */ GIR_MakeTempReg, /*TempRegID*//* 251(*/0xFB, 0x01/*)*/, /*TypeID*/GILLT_s64,
62009 /* 186792 */ GIR_BuildMI, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62010 /* 186797 */ GIR_AddTempRegister, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, /*TempRegID*//* 251(*/0xFB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62011 /* 186804 */ GIR_AddSimpleTempRegister, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, /*TempRegID*//* 252(*/0xFC, 0x01/*)*/,
62012 /* 186809 */ GIR_AddSimpleTempRegister, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, /*TempRegID*//* 253(*/0xFD, 0x01/*)*/,
62013 /* 186814 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 252(*/0xFC, 0x01/*)*/,
62014 /* 186817 */ GIR_MakeTempReg, /*TempRegID*//* 250(*/0xFA, 0x01/*)*/, /*TypeID*/GILLT_s32,
62015 /* 186821 */ GIR_BuildMI, /*InsnID*//* 251(*/0xFB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62016 /* 186826 */ GIR_AddTempRegister, /*InsnID*//* 251(*/0xFB, 0x01/*)*/, /*TempRegID*//* 250(*/0xFA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62017 /* 186833 */ GIR_AddImm, /*InsnID*//* 251(*/0xFB, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62018 /* 186844 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 251(*/0xFB, 0x01/*)*/,
62019 /* 186847 */ GIR_MakeTempReg, /*TempRegID*//* 249(*/0xF9, 0x01/*)*/, /*TypeID*/GILLT_s32,
62020 /* 186851 */ GIR_BuildMI, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62021 /* 186856 */ GIR_AddTempRegister, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, /*TempRegID*//* 249(*/0xF9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62022 /* 186863 */ GIR_AddSimpleTempRegister, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, /*TempRegID*//* 250(*/0xFA, 0x01/*)*/,
62023 /* 186868 */ GIR_AddImm, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62024 /* 186879 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 250(*/0xFA, 0x01/*)*/,
62025 /* 186882 */ GIR_MakeTempReg, /*TempRegID*//* 248(*/0xF8, 0x01/*)*/, /*TypeID*/GILLT_s64,
62026 /* 186886 */ GIR_BuildMI, /*InsnID*//* 249(*/0xF9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62027 /* 186891 */ GIR_AddTempRegister, /*InsnID*//* 249(*/0xF9, 0x01/*)*/, /*TempRegID*//* 248(*/0xF8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62028 /* 186898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 249(*/0xF9, 0x01/*)*/,
62029 /* 186901 */ GIR_MakeTempReg, /*TempRegID*//* 247(*/0xF7, 0x01/*)*/, /*TypeID*/GILLT_s64,
62030 /* 186905 */ GIR_BuildMI, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62031 /* 186910 */ GIR_AddTempRegister, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*TempRegID*//* 247(*/0xF7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62032 /* 186917 */ GIR_AddSimpleTempRegister, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*TempRegID*//* 248(*/0xF8, 0x01/*)*/,
62033 /* 186922 */ GIR_AddSimpleTempRegister, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*TempRegID*//* 249(*/0xF9, 0x01/*)*/,
62034 /* 186927 */ GIR_AddImm8, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Imm*/1,
62035 /* 186931 */ GIR_ConstrainOperandRC, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62036 /* 186937 */ GIR_ConstrainOperandRC, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62037 /* 186943 */ GIR_ConstrainOperandRC, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62038 /* 186949 */ GIR_MakeTempReg, /*TempRegID*//* 246(*/0xF6, 0x01/*)*/, /*TypeID*/GILLT_s64,
62039 /* 186953 */ GIR_BuildMI, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62040 /* 186958 */ GIR_AddTempRegister, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*TempRegID*//* 246(*/0xF6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62041 /* 186965 */ GIR_AddSimpleTempRegister, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*TempRegID*//* 247(*/0xF7, 0x01/*)*/,
62042 /* 186970 */ GIR_AddImm8, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*Imm*/32,
62043 /* 186974 */ GIR_AddImm8, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*Imm*/31,
62044 /* 186978 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 247(*/0xF7, 0x01/*)*/,
62045 /* 186981 */ GIR_MakeTempReg, /*TempRegID*//* 245(*/0xF5, 0x01/*)*/, /*TypeID*/GILLT_s64,
62046 /* 186985 */ GIR_BuildMI, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62047 /* 186990 */ GIR_AddTempRegister, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, /*TempRegID*//* 245(*/0xF5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62048 /* 186997 */ GIR_AddSimpleTempRegister, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, /*TempRegID*//* 246(*/0xF6, 0x01/*)*/,
62049 /* 187002 */ GIR_AddImm, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62050 /* 187013 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 246(*/0xF6, 0x01/*)*/,
62051 /* 187016 */ GIR_MakeTempReg, /*TempRegID*//* 244(*/0xF4, 0x01/*)*/, /*TypeID*/GILLT_s64,
62052 /* 187020 */ GIR_BuildMI, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62053 /* 187025 */ GIR_AddTempRegister, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, /*TempRegID*//* 244(*/0xF4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62054 /* 187032 */ GIR_AddSimpleTempRegister, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, /*TempRegID*//* 245(*/0xF5, 0x01/*)*/,
62055 /* 187037 */ GIR_AddImm, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62056 /* 187048 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 245(*/0xF5, 0x01/*)*/,
62057 /* 187051 */ GIR_MakeTempReg, /*TempRegID*//* 243(*/0xF3, 0x01/*)*/, /*TypeID*/GILLT_s64,
62058 /* 187055 */ GIR_BuildMI, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
62059 /* 187060 */ GIR_AddTempRegister, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, /*TempRegID*//* 243(*/0xF3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62060 /* 187067 */ GIR_Copy, /*NewInsnID*//* 244(*/0xF4, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62061 /* 187072 */ GIR_AddImm8, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, /*Imm*/63,
62062 /* 187076 */ GIR_AddImm8, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, /*Imm*/1,
62063 /* 187080 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 244(*/0xF4, 0x01/*)*/,
62064 /* 187083 */ GIR_MakeTempReg, /*TempRegID*//* 242(*/0xF2, 0x01/*)*/, /*TypeID*/GILLT_s64,
62065 /* 187087 */ GIR_BuildMI, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62066 /* 187092 */ GIR_AddTempRegister, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, /*TempRegID*//* 242(*/0xF2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62067 /* 187099 */ GIR_AddSimpleTempRegister, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, /*TempRegID*//* 243(*/0xF3, 0x01/*)*/,
62068 /* 187104 */ GIR_AddSimpleTempRegister, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, /*TempRegID*//* 244(*/0xF4, 0x01/*)*/,
62069 /* 187109 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 243(*/0xF3, 0x01/*)*/,
62070 /* 187112 */ GIR_MakeTempReg, /*TempRegID*//* 241(*/0xF1, 0x01/*)*/, /*TypeID*/GILLT_s64,
62071 /* 187116 */ GIR_BuildMI, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
62072 /* 187121 */ GIR_AddTempRegister, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, /*TempRegID*//* 241(*/0xF1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62073 /* 187128 */ GIR_AddSimpleTempRegister, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, /*TempRegID*//* 242(*/0xF2, 0x01/*)*/,
62074 /* 187133 */ GIR_AddSimpleTempRegister, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, /*TempRegID*//* 251(*/0xFB, 0x01/*)*/,
62075 /* 187138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 242(*/0xF2, 0x01/*)*/,
62076 /* 187141 */ GIR_MakeTempReg, /*TempRegID*//* 240(*/0xF0, 0x01/*)*/, /*TypeID*/GILLT_s64,
62077 /* 187145 */ GIR_BuildMI, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62078 /* 187150 */ GIR_AddTempRegister, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*TempRegID*//* 240(*/0xF0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62079 /* 187157 */ GIR_AddSimpleTempRegister, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*TempRegID*//* 241(*/0xF1, 0x01/*)*/,
62080 /* 187162 */ GIR_AddImm8, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*Imm*/2,
62081 /* 187166 */ GIR_AddImm8, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*Imm*/61,
62082 /* 187170 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 241(*/0xF1, 0x01/*)*/,
62083 /* 187173 */ GIR_MakeTempReg, /*TempRegID*//* 239(*/0xEF, 0x01/*)*/, /*TypeID*/GILLT_s64,
62084 /* 187177 */ GIR_BuildMI, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62085 /* 187182 */ GIR_AddTempRegister, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, /*TempRegID*//* 239(*/0xEF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62086 /* 187189 */ GIR_AddSimpleTempRegister, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, /*TempRegID*//* 240(*/0xF0, 0x01/*)*/,
62087 /* 187194 */ GIR_AddSimpleTempRegister, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, /*TempRegID*//* 260(*/0x84, 0x02/*)*/,
62088 /* 187199 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 240(*/0xF0, 0x01/*)*/,
62089 /* 187202 */ GIR_MakeTempReg, /*TempRegID*//* 238(*/0xEE, 0x01/*)*/, /*TypeID*/GILLT_s32,
62090 /* 187206 */ GIR_BuildMI, /*InsnID*//* 239(*/0xEF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62091 /* 187211 */ GIR_AddTempRegister, /*InsnID*//* 239(*/0xEF, 0x01/*)*/, /*TempRegID*//* 238(*/0xEE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62092 /* 187218 */ GIR_AddImm, /*InsnID*//* 239(*/0xEF, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
62093 /* 187229 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 239(*/0xEF, 0x01/*)*/,
62094 /* 187232 */ GIR_MakeTempReg, /*TempRegID*//* 237(*/0xED, 0x01/*)*/, /*TypeID*/GILLT_s32,
62095 /* 187236 */ GIR_BuildMI, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62096 /* 187241 */ GIR_AddTempRegister, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, /*TempRegID*//* 237(*/0xED, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62097 /* 187248 */ GIR_AddSimpleTempRegister, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, /*TempRegID*//* 238(*/0xEE, 0x01/*)*/,
62098 /* 187253 */ GIR_AddImm, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
62099 /* 187264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 238(*/0xEE, 0x01/*)*/,
62100 /* 187267 */ GIR_MakeTempReg, /*TempRegID*//* 236(*/0xEC, 0x01/*)*/, /*TypeID*/GILLT_s64,
62101 /* 187271 */ GIR_BuildMI, /*InsnID*//* 237(*/0xED, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62102 /* 187276 */ GIR_AddTempRegister, /*InsnID*//* 237(*/0xED, 0x01/*)*/, /*TempRegID*//* 236(*/0xEC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62103 /* 187283 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 237(*/0xED, 0x01/*)*/,
62104 /* 187286 */ GIR_MakeTempReg, /*TempRegID*//* 235(*/0xEB, 0x01/*)*/, /*TypeID*/GILLT_s64,
62105 /* 187290 */ GIR_BuildMI, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62106 /* 187295 */ GIR_AddTempRegister, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*TempRegID*//* 235(*/0xEB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62107 /* 187302 */ GIR_AddSimpleTempRegister, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*TempRegID*//* 236(*/0xEC, 0x01/*)*/,
62108 /* 187307 */ GIR_AddSimpleTempRegister, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*TempRegID*//* 237(*/0xED, 0x01/*)*/,
62109 /* 187312 */ GIR_AddImm8, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Imm*/1,
62110 /* 187316 */ GIR_ConstrainOperandRC, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62111 /* 187322 */ GIR_ConstrainOperandRC, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62112 /* 187328 */ GIR_ConstrainOperandRC, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62113 /* 187334 */ GIR_MakeTempReg, /*TempRegID*//* 234(*/0xEA, 0x01/*)*/, /*TypeID*/GILLT_s64,
62114 /* 187338 */ GIR_BuildMI, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62115 /* 187343 */ GIR_AddTempRegister, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*TempRegID*//* 234(*/0xEA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62116 /* 187350 */ GIR_AddSimpleTempRegister, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*TempRegID*//* 235(*/0xEB, 0x01/*)*/,
62117 /* 187355 */ GIR_AddImm8, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*Imm*/32,
62118 /* 187359 */ GIR_AddImm8, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*Imm*/31,
62119 /* 187363 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 235(*/0xEB, 0x01/*)*/,
62120 /* 187366 */ GIR_MakeTempReg, /*TempRegID*//* 233(*/0xE9, 0x01/*)*/, /*TypeID*/GILLT_s64,
62121 /* 187370 */ GIR_BuildMI, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62122 /* 187375 */ GIR_AddTempRegister, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, /*TempRegID*//* 233(*/0xE9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62123 /* 187382 */ GIR_AddSimpleTempRegister, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, /*TempRegID*//* 234(*/0xEA, 0x01/*)*/,
62124 /* 187387 */ GIR_AddImm, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
62125 /* 187398 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 234(*/0xEA, 0x01/*)*/,
62126 /* 187401 */ GIR_MakeTempReg, /*TempRegID*//* 232(*/0xE8, 0x01/*)*/, /*TypeID*/GILLT_s64,
62127 /* 187405 */ GIR_BuildMI, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62128 /* 187410 */ GIR_AddTempRegister, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, /*TempRegID*//* 232(*/0xE8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62129 /* 187417 */ GIR_AddSimpleTempRegister, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, /*TempRegID*//* 233(*/0xE9, 0x01/*)*/,
62130 /* 187422 */ GIR_AddImm, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
62131 /* 187433 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 233(*/0xE9, 0x01/*)*/,
62132 /* 187436 */ GIR_MakeTempReg, /*TempRegID*//* 231(*/0xE7, 0x01/*)*/, /*TypeID*/GILLT_s32,
62133 /* 187440 */ GIR_BuildMI, /*InsnID*//* 232(*/0xE8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62134 /* 187445 */ GIR_AddTempRegister, /*InsnID*//* 232(*/0xE8, 0x01/*)*/, /*TempRegID*//* 231(*/0xE7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62135 /* 187452 */ GIR_AddImm, /*InsnID*//* 232(*/0xE8, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62136 /* 187463 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 232(*/0xE8, 0x01/*)*/,
62137 /* 187466 */ GIR_MakeTempReg, /*TempRegID*//* 230(*/0xE6, 0x01/*)*/, /*TypeID*/GILLT_s32,
62138 /* 187470 */ GIR_BuildMI, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62139 /* 187475 */ GIR_AddTempRegister, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, /*TempRegID*//* 230(*/0xE6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62140 /* 187482 */ GIR_AddSimpleTempRegister, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, /*TempRegID*//* 231(*/0xE7, 0x01/*)*/,
62141 /* 187487 */ GIR_AddImm, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62142 /* 187498 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 231(*/0xE7, 0x01/*)*/,
62143 /* 187501 */ GIR_MakeTempReg, /*TempRegID*//* 229(*/0xE5, 0x01/*)*/, /*TypeID*/GILLT_s64,
62144 /* 187505 */ GIR_BuildMI, /*InsnID*//* 230(*/0xE6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62145 /* 187510 */ GIR_AddTempRegister, /*InsnID*//* 230(*/0xE6, 0x01/*)*/, /*TempRegID*//* 229(*/0xE5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62146 /* 187517 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 230(*/0xE6, 0x01/*)*/,
62147 /* 187520 */ GIR_MakeTempReg, /*TempRegID*//* 228(*/0xE4, 0x01/*)*/, /*TypeID*/GILLT_s64,
62148 /* 187524 */ GIR_BuildMI, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62149 /* 187529 */ GIR_AddTempRegister, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*TempRegID*//* 228(*/0xE4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62150 /* 187536 */ GIR_AddSimpleTempRegister, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*TempRegID*//* 229(*/0xE5, 0x01/*)*/,
62151 /* 187541 */ GIR_AddSimpleTempRegister, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*TempRegID*//* 230(*/0xE6, 0x01/*)*/,
62152 /* 187546 */ GIR_AddImm8, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Imm*/1,
62153 /* 187550 */ GIR_ConstrainOperandRC, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62154 /* 187556 */ GIR_ConstrainOperandRC, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62155 /* 187562 */ GIR_ConstrainOperandRC, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62156 /* 187568 */ GIR_MakeTempReg, /*TempRegID*//* 227(*/0xE3, 0x01/*)*/, /*TypeID*/GILLT_s64,
62157 /* 187572 */ GIR_BuildMI, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62158 /* 187577 */ GIR_AddTempRegister, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*TempRegID*//* 227(*/0xE3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62159 /* 187584 */ GIR_AddSimpleTempRegister, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*TempRegID*//* 228(*/0xE4, 0x01/*)*/,
62160 /* 187589 */ GIR_AddImm8, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*Imm*/32,
62161 /* 187593 */ GIR_AddImm8, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*Imm*/31,
62162 /* 187597 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 228(*/0xE4, 0x01/*)*/,
62163 /* 187600 */ GIR_MakeTempReg, /*TempRegID*//* 226(*/0xE2, 0x01/*)*/, /*TypeID*/GILLT_s64,
62164 /* 187604 */ GIR_BuildMI, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62165 /* 187609 */ GIR_AddTempRegister, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, /*TempRegID*//* 226(*/0xE2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62166 /* 187616 */ GIR_AddSimpleTempRegister, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, /*TempRegID*//* 227(*/0xE3, 0x01/*)*/,
62167 /* 187621 */ GIR_AddImm, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62168 /* 187632 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 227(*/0xE3, 0x01/*)*/,
62169 /* 187635 */ GIR_MakeTempReg, /*TempRegID*//* 225(*/0xE1, 0x01/*)*/, /*TypeID*/GILLT_s64,
62170 /* 187639 */ GIR_BuildMI, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62171 /* 187644 */ GIR_AddTempRegister, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, /*TempRegID*//* 225(*/0xE1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62172 /* 187651 */ GIR_AddSimpleTempRegister, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, /*TempRegID*//* 226(*/0xE2, 0x01/*)*/,
62173 /* 187656 */ GIR_AddImm, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62174 /* 187667 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 226(*/0xE2, 0x01/*)*/,
62175 /* 187670 */ GIR_MakeTempReg, /*TempRegID*//* 224(*/0xE0, 0x01/*)*/, /*TypeID*/GILLT_s64,
62176 /* 187674 */ GIR_BuildMI, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62177 /* 187679 */ GIR_AddTempRegister, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, /*TempRegID*//* 224(*/0xE0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62178 /* 187686 */ GIR_Copy, /*NewInsnID*//* 225(*/0xE1, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62179 /* 187691 */ GIR_AddImm8, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, /*Imm*/1,
62180 /* 187695 */ GIR_AddImm8, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, /*Imm*/62,
62181 /* 187699 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 225(*/0xE1, 0x01/*)*/,
62182 /* 187702 */ GIR_MakeTempReg, /*TempRegID*//* 223(*/0xDF, 0x01/*)*/, /*TypeID*/GILLT_s64,
62183 /* 187706 */ GIR_BuildMI, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62184 /* 187711 */ GIR_AddTempRegister, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, /*TempRegID*//* 223(*/0xDF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62185 /* 187718 */ GIR_AddSimpleTempRegister, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, /*TempRegID*//* 224(*/0xE0, 0x01/*)*/,
62186 /* 187723 */ GIR_AddSimpleTempRegister, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, /*TempRegID*//* 225(*/0xE1, 0x01/*)*/,
62187 /* 187728 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 224(*/0xE0, 0x01/*)*/,
62188 /* 187731 */ GIR_MakeTempReg, /*TempRegID*//* 222(*/0xDE, 0x01/*)*/, /*TypeID*/GILLT_s32,
62189 /* 187735 */ GIR_BuildMI, /*InsnID*//* 223(*/0xDF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62190 /* 187740 */ GIR_AddTempRegister, /*InsnID*//* 223(*/0xDF, 0x01/*)*/, /*TempRegID*//* 222(*/0xDE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62191 /* 187747 */ GIR_AddImm, /*InsnID*//* 223(*/0xDF, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62192 /* 187758 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 223(*/0xDF, 0x01/*)*/,
62193 /* 187761 */ GIR_MakeTempReg, /*TempRegID*//* 221(*/0xDD, 0x01/*)*/, /*TypeID*/GILLT_s32,
62194 /* 187765 */ GIR_BuildMI, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62195 /* 187770 */ GIR_AddTempRegister, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, /*TempRegID*//* 221(*/0xDD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62196 /* 187777 */ GIR_AddSimpleTempRegister, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, /*TempRegID*//* 222(*/0xDE, 0x01/*)*/,
62197 /* 187782 */ GIR_AddImm, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62198 /* 187793 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 222(*/0xDE, 0x01/*)*/,
62199 /* 187796 */ GIR_MakeTempReg, /*TempRegID*//* 220(*/0xDC, 0x01/*)*/, /*TypeID*/GILLT_s64,
62200 /* 187800 */ GIR_BuildMI, /*InsnID*//* 221(*/0xDD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62201 /* 187805 */ GIR_AddTempRegister, /*InsnID*//* 221(*/0xDD, 0x01/*)*/, /*TempRegID*//* 220(*/0xDC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62202 /* 187812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 221(*/0xDD, 0x01/*)*/,
62203 /* 187815 */ GIR_MakeTempReg, /*TempRegID*//* 219(*/0xDB, 0x01/*)*/, /*TypeID*/GILLT_s64,
62204 /* 187819 */ GIR_BuildMI, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62205 /* 187824 */ GIR_AddTempRegister, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*TempRegID*//* 219(*/0xDB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62206 /* 187831 */ GIR_AddSimpleTempRegister, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*TempRegID*//* 220(*/0xDC, 0x01/*)*/,
62207 /* 187836 */ GIR_AddSimpleTempRegister, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*TempRegID*//* 221(*/0xDD, 0x01/*)*/,
62208 /* 187841 */ GIR_AddImm8, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Imm*/1,
62209 /* 187845 */ GIR_ConstrainOperandRC, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62210 /* 187851 */ GIR_ConstrainOperandRC, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62211 /* 187857 */ GIR_ConstrainOperandRC, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62212 /* 187863 */ GIR_MakeTempReg, /*TempRegID*//* 218(*/0xDA, 0x01/*)*/, /*TypeID*/GILLT_s64,
62213 /* 187867 */ GIR_BuildMI, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62214 /* 187872 */ GIR_AddTempRegister, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*TempRegID*//* 218(*/0xDA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62215 /* 187879 */ GIR_AddSimpleTempRegister, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*TempRegID*//* 219(*/0xDB, 0x01/*)*/,
62216 /* 187884 */ GIR_AddImm8, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*Imm*/32,
62217 /* 187888 */ GIR_AddImm8, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*Imm*/31,
62218 /* 187892 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 219(*/0xDB, 0x01/*)*/,
62219 /* 187895 */ GIR_MakeTempReg, /*TempRegID*//* 217(*/0xD9, 0x01/*)*/, /*TypeID*/GILLT_s64,
62220 /* 187899 */ GIR_BuildMI, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62221 /* 187904 */ GIR_AddTempRegister, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, /*TempRegID*//* 217(*/0xD9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62222 /* 187911 */ GIR_AddSimpleTempRegister, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, /*TempRegID*//* 218(*/0xDA, 0x01/*)*/,
62223 /* 187916 */ GIR_AddImm, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62224 /* 187927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 218(*/0xDA, 0x01/*)*/,
62225 /* 187930 */ GIR_MakeTempReg, /*TempRegID*//* 216(*/0xD8, 0x01/*)*/, /*TypeID*/GILLT_s64,
62226 /* 187934 */ GIR_BuildMI, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62227 /* 187939 */ GIR_AddTempRegister, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, /*TempRegID*//* 216(*/0xD8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62228 /* 187946 */ GIR_AddSimpleTempRegister, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, /*TempRegID*//* 217(*/0xD9, 0x01/*)*/,
62229 /* 187951 */ GIR_AddImm, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62230 /* 187962 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 217(*/0xD9, 0x01/*)*/,
62231 /* 187965 */ GIR_MakeTempReg, /*TempRegID*//* 215(*/0xD7, 0x01/*)*/, /*TypeID*/GILLT_s64,
62232 /* 187969 */ GIR_BuildMI, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
62233 /* 187974 */ GIR_AddTempRegister, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, /*TempRegID*//* 215(*/0xD7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62234 /* 187981 */ GIR_Copy, /*NewInsnID*//* 216(*/0xD8, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62235 /* 187986 */ GIR_AddImm8, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, /*Imm*/63,
62236 /* 187990 */ GIR_AddImm8, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, /*Imm*/1,
62237 /* 187994 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 216(*/0xD8, 0x01/*)*/,
62238 /* 187997 */ GIR_MakeTempReg, /*TempRegID*//* 214(*/0xD6, 0x01/*)*/, /*TypeID*/GILLT_s64,
62239 /* 188001 */ GIR_BuildMI, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62240 /* 188006 */ GIR_AddTempRegister, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, /*TempRegID*//* 214(*/0xD6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62241 /* 188013 */ GIR_AddSimpleTempRegister, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, /*TempRegID*//* 215(*/0xD7, 0x01/*)*/,
62242 /* 188018 */ GIR_AddSimpleTempRegister, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, /*TempRegID*//* 216(*/0xD8, 0x01/*)*/,
62243 /* 188023 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 215(*/0xD7, 0x01/*)*/,
62244 /* 188026 */ GIR_MakeTempReg, /*TempRegID*//* 213(*/0xD5, 0x01/*)*/, /*TypeID*/GILLT_s64,
62245 /* 188030 */ GIR_BuildMI, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
62246 /* 188035 */ GIR_AddTempRegister, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, /*TempRegID*//* 213(*/0xD5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62247 /* 188042 */ GIR_AddSimpleTempRegister, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, /*TempRegID*//* 214(*/0xD6, 0x01/*)*/,
62248 /* 188047 */ GIR_AddSimpleTempRegister, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, /*TempRegID*//* 223(*/0xDF, 0x01/*)*/,
62249 /* 188052 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 214(*/0xD6, 0x01/*)*/,
62250 /* 188055 */ GIR_MakeTempReg, /*TempRegID*//* 212(*/0xD4, 0x01/*)*/, /*TypeID*/GILLT_s64,
62251 /* 188059 */ GIR_BuildMI, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
62252 /* 188064 */ GIR_AddTempRegister, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*TempRegID*//* 212(*/0xD4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62253 /* 188071 */ GIR_AddSimpleTempRegister, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*TempRegID*//* 213(*/0xD5, 0x01/*)*/,
62254 /* 188076 */ GIR_AddImm8, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*Imm*/62,
62255 /* 188080 */ GIR_AddImm8, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*Imm*/2,
62256 /* 188084 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 213(*/0xD5, 0x01/*)*/,
62257 /* 188087 */ GIR_MakeTempReg, /*TempRegID*//* 211(*/0xD3, 0x01/*)*/, /*TypeID*/GILLT_s64,
62258 /* 188091 */ GIR_BuildMI, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62259 /* 188096 */ GIR_AddTempRegister, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, /*TempRegID*//* 211(*/0xD3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62260 /* 188103 */ GIR_AddSimpleTempRegister, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, /*TempRegID*//* 212(*/0xD4, 0x01/*)*/,
62261 /* 188108 */ GIR_AddSimpleTempRegister, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, /*TempRegID*//* 232(*/0xE8, 0x01/*)*/,
62262 /* 188113 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 212(*/0xD4, 0x01/*)*/,
62263 /* 188116 */ GIR_MakeTempReg, /*TempRegID*//* 210(*/0xD2, 0x01/*)*/, /*TypeID*/GILLT_s64,
62264 /* 188120 */ GIR_BuildMI, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
62265 /* 188125 */ GIR_AddTempRegister, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, /*TempRegID*//* 210(*/0xD2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62266 /* 188132 */ GIR_AddSimpleTempRegister, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, /*TempRegID*//* 211(*/0xD3, 0x01/*)*/,
62267 /* 188137 */ GIR_AddSimpleTempRegister, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, /*TempRegID*//* 239(*/0xEF, 0x01/*)*/,
62268 /* 188142 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 211(*/0xD3, 0x01/*)*/,
62269 /* 188145 */ GIR_MakeTempReg, /*TempRegID*//* 209(*/0xD1, 0x01/*)*/, /*TypeID*/GILLT_s64,
62270 /* 188149 */ GIR_BuildMI, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62271 /* 188154 */ GIR_AddTempRegister, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*TempRegID*//* 209(*/0xD1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62272 /* 188161 */ GIR_AddSimpleTempRegister, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*TempRegID*//* 210(*/0xD2, 0x01/*)*/,
62273 /* 188166 */ GIR_AddImm8, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*Imm*/4,
62274 /* 188170 */ GIR_AddImm8, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*Imm*/59,
62275 /* 188174 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 210(*/0xD2, 0x01/*)*/,
62276 /* 188177 */ GIR_MakeTempReg, /*TempRegID*//* 208(*/0xD0, 0x01/*)*/, /*TypeID*/GILLT_s64,
62277 /* 188181 */ GIR_BuildMI, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62278 /* 188186 */ GIR_AddTempRegister, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, /*TempRegID*//* 208(*/0xD0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62279 /* 188193 */ GIR_AddSimpleTempRegister, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, /*TempRegID*//* 209(*/0xD1, 0x01/*)*/,
62280 /* 188198 */ GIR_AddSimpleTempRegister, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, /*TempRegID*//* 267(*/0x8B, 0x02/*)*/,
62281 /* 188203 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 209(*/0xD1, 0x01/*)*/,
62282 /* 188206 */ GIR_MakeTempReg, /*TempRegID*//* 207(*/0xCF, 0x01/*)*/, /*TypeID*/GILLT_s32,
62283 /* 188210 */ GIR_BuildMI, /*InsnID*//* 208(*/0xD0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62284 /* 188215 */ GIR_AddTempRegister, /*InsnID*//* 208(*/0xD0, 0x01/*)*/, /*TempRegID*//* 207(*/0xCF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62285 /* 188222 */ GIR_AddImm, /*InsnID*//* 208(*/0xD0, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855),
62286 /* 188233 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 208(*/0xD0, 0x01/*)*/,
62287 /* 188236 */ GIR_MakeTempReg, /*TempRegID*//* 206(*/0xCE, 0x01/*)*/, /*TypeID*/GILLT_s32,
62288 /* 188240 */ GIR_BuildMI, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62289 /* 188245 */ GIR_AddTempRegister, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, /*TempRegID*//* 206(*/0xCE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62290 /* 188252 */ GIR_AddSimpleTempRegister, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, /*TempRegID*//* 207(*/0xCF, 0x01/*)*/,
62291 /* 188257 */ GIR_AddImm, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855),
62292 /* 188268 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 207(*/0xCF, 0x01/*)*/,
62293 /* 188271 */ GIR_MakeTempReg, /*TempRegID*//* 205(*/0xCD, 0x01/*)*/, /*TypeID*/GILLT_s64,
62294 /* 188275 */ GIR_BuildMI, /*InsnID*//* 206(*/0xCE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62295 /* 188280 */ GIR_AddTempRegister, /*InsnID*//* 206(*/0xCE, 0x01/*)*/, /*TempRegID*//* 205(*/0xCD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62296 /* 188287 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 206(*/0xCE, 0x01/*)*/,
62297 /* 188290 */ GIR_MakeTempReg, /*TempRegID*//* 204(*/0xCC, 0x01/*)*/, /*TypeID*/GILLT_s64,
62298 /* 188294 */ GIR_BuildMI, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62299 /* 188299 */ GIR_AddTempRegister, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*TempRegID*//* 204(*/0xCC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62300 /* 188306 */ GIR_AddSimpleTempRegister, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*TempRegID*//* 205(*/0xCD, 0x01/*)*/,
62301 /* 188311 */ GIR_AddSimpleTempRegister, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*TempRegID*//* 206(*/0xCE, 0x01/*)*/,
62302 /* 188316 */ GIR_AddImm8, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Imm*/1,
62303 /* 188320 */ GIR_ConstrainOperandRC, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62304 /* 188326 */ GIR_ConstrainOperandRC, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62305 /* 188332 */ GIR_ConstrainOperandRC, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62306 /* 188338 */ GIR_MakeTempReg, /*TempRegID*//* 203(*/0xCB, 0x01/*)*/, /*TypeID*/GILLT_s64,
62307 /* 188342 */ GIR_BuildMI, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62308 /* 188347 */ GIR_AddTempRegister, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*TempRegID*//* 203(*/0xCB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62309 /* 188354 */ GIR_AddSimpleTempRegister, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*TempRegID*//* 204(*/0xCC, 0x01/*)*/,
62310 /* 188359 */ GIR_AddImm8, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*Imm*/32,
62311 /* 188363 */ GIR_AddImm8, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*Imm*/31,
62312 /* 188367 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 204(*/0xCC, 0x01/*)*/,
62313 /* 188370 */ GIR_MakeTempReg, /*TempRegID*//* 202(*/0xCA, 0x01/*)*/, /*TypeID*/GILLT_s64,
62314 /* 188374 */ GIR_BuildMI, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62315 /* 188379 */ GIR_AddTempRegister, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, /*TempRegID*//* 202(*/0xCA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62316 /* 188386 */ GIR_AddSimpleTempRegister, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, /*TempRegID*//* 203(*/0xCB, 0x01/*)*/,
62317 /* 188391 */ GIR_AddImm, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855),
62318 /* 188402 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 203(*/0xCB, 0x01/*)*/,
62319 /* 188405 */ GIR_MakeTempReg, /*TempRegID*//* 201(*/0xC9, 0x01/*)*/, /*TypeID*/GILLT_s64,
62320 /* 188409 */ GIR_BuildMI, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62321 /* 188414 */ GIR_AddTempRegister, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, /*TempRegID*//* 201(*/0xC9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62322 /* 188421 */ GIR_AddSimpleTempRegister, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, /*TempRegID*//* 202(*/0xCA, 0x01/*)*/,
62323 /* 188426 */ GIR_AddImm, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855),
62324 /* 188437 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 202(*/0xCA, 0x01/*)*/,
62325 /* 188440 */ GIR_MakeTempReg, /*TempRegID*//* 200(*/0xC8, 0x01/*)*/, /*TypeID*/GILLT_s32,
62326 /* 188444 */ GIR_BuildMI, /*InsnID*//* 201(*/0xC9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62327 /* 188449 */ GIR_AddTempRegister, /*InsnID*//* 201(*/0xC9, 0x01/*)*/, /*TempRegID*//* 200(*/0xC8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62328 /* 188456 */ GIR_AddImm, /*InsnID*//* 201(*/0xC9, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
62329 /* 188467 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 201(*/0xC9, 0x01/*)*/,
62330 /* 188470 */ GIR_MakeTempReg, /*TempRegID*//* 199(*/0xC7, 0x01/*)*/, /*TypeID*/GILLT_s32,
62331 /* 188474 */ GIR_BuildMI, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62332 /* 188479 */ GIR_AddTempRegister, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, /*TempRegID*//* 199(*/0xC7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62333 /* 188486 */ GIR_AddSimpleTempRegister, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, /*TempRegID*//* 200(*/0xC8, 0x01/*)*/,
62334 /* 188491 */ GIR_AddImm, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
62335 /* 188502 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 200(*/0xC8, 0x01/*)*/,
62336 /* 188505 */ GIR_MakeTempReg, /*TempRegID*//* 198(*/0xC6, 0x01/*)*/, /*TypeID*/GILLT_s64,
62337 /* 188509 */ GIR_BuildMI, /*InsnID*//* 199(*/0xC7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62338 /* 188514 */ GIR_AddTempRegister, /*InsnID*//* 199(*/0xC7, 0x01/*)*/, /*TempRegID*//* 198(*/0xC6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62339 /* 188521 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 199(*/0xC7, 0x01/*)*/,
62340 /* 188524 */ GIR_MakeTempReg, /*TempRegID*//* 197(*/0xC5, 0x01/*)*/, /*TypeID*/GILLT_s64,
62341 /* 188528 */ GIR_BuildMI, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62342 /* 188533 */ GIR_AddTempRegister, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*TempRegID*//* 197(*/0xC5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62343 /* 188540 */ GIR_AddSimpleTempRegister, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*TempRegID*//* 198(*/0xC6, 0x01/*)*/,
62344 /* 188545 */ GIR_AddSimpleTempRegister, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*TempRegID*//* 199(*/0xC7, 0x01/*)*/,
62345 /* 188550 */ GIR_AddImm8, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Imm*/1,
62346 /* 188554 */ GIR_ConstrainOperandRC, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62347 /* 188560 */ GIR_ConstrainOperandRC, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62348 /* 188566 */ GIR_ConstrainOperandRC, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62349 /* 188572 */ GIR_MakeTempReg, /*TempRegID*//* 196(*/0xC4, 0x01/*)*/, /*TypeID*/GILLT_s64,
62350 /* 188576 */ GIR_BuildMI, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62351 /* 188581 */ GIR_AddTempRegister, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*TempRegID*//* 196(*/0xC4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62352 /* 188588 */ GIR_AddSimpleTempRegister, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*TempRegID*//* 197(*/0xC5, 0x01/*)*/,
62353 /* 188593 */ GIR_AddImm8, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*Imm*/32,
62354 /* 188597 */ GIR_AddImm8, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*Imm*/31,
62355 /* 188601 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 197(*/0xC5, 0x01/*)*/,
62356 /* 188604 */ GIR_MakeTempReg, /*TempRegID*//* 195(*/0xC3, 0x01/*)*/, /*TypeID*/GILLT_s64,
62357 /* 188608 */ GIR_BuildMI, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62358 /* 188613 */ GIR_AddTempRegister, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, /*TempRegID*//* 195(*/0xC3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62359 /* 188620 */ GIR_AddSimpleTempRegister, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, /*TempRegID*//* 196(*/0xC4, 0x01/*)*/,
62360 /* 188625 */ GIR_AddImm, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
62361 /* 188636 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 196(*/0xC4, 0x01/*)*/,
62362 /* 188639 */ GIR_MakeTempReg, /*TempRegID*//* 194(*/0xC2, 0x01/*)*/, /*TypeID*/GILLT_s64,
62363 /* 188643 */ GIR_BuildMI, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62364 /* 188648 */ GIR_AddTempRegister, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, /*TempRegID*//* 194(*/0xC2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62365 /* 188655 */ GIR_AddSimpleTempRegister, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, /*TempRegID*//* 195(*/0xC3, 0x01/*)*/,
62366 /* 188660 */ GIR_AddImm, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428),
62367 /* 188671 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 195(*/0xC3, 0x01/*)*/,
62368 /* 188674 */ GIR_MakeTempReg, /*TempRegID*//* 193(*/0xC1, 0x01/*)*/, /*TypeID*/GILLT_s32,
62369 /* 188678 */ GIR_BuildMI, /*InsnID*//* 194(*/0xC2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62370 /* 188683 */ GIR_AddTempRegister, /*InsnID*//* 194(*/0xC2, 0x01/*)*/, /*TempRegID*//* 193(*/0xC1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62371 /* 188690 */ GIR_AddImm, /*InsnID*//* 194(*/0xC2, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62372 /* 188701 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 194(*/0xC2, 0x01/*)*/,
62373 /* 188704 */ GIR_MakeTempReg, /*TempRegID*//* 192(*/0xC0, 0x01/*)*/, /*TypeID*/GILLT_s32,
62374 /* 188708 */ GIR_BuildMI, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62375 /* 188713 */ GIR_AddTempRegister, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, /*TempRegID*//* 192(*/0xC0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62376 /* 188720 */ GIR_AddSimpleTempRegister, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, /*TempRegID*//* 193(*/0xC1, 0x01/*)*/,
62377 /* 188725 */ GIR_AddImm, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62378 /* 188736 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 193(*/0xC1, 0x01/*)*/,
62379 /* 188739 */ GIR_MakeTempReg, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, /*TypeID*/GILLT_s64,
62380 /* 188743 */ GIR_BuildMI, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62381 /* 188748 */ GIR_AddTempRegister, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62382 /* 188755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 192(*/0xC0, 0x01/*)*/,
62383 /* 188758 */ GIR_MakeTempReg, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TypeID*/GILLT_s64,
62384 /* 188762 */ GIR_BuildMI, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62385 /* 188767 */ GIR_AddTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62386 /* 188774 */ GIR_AddSimpleTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/,
62387 /* 188779 */ GIR_AddSimpleTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 192(*/0xC0, 0x01/*)*/,
62388 /* 188784 */ GIR_AddImm8, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Imm*/1,
62389 /* 188788 */ GIR_ConstrainOperandRC, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62390 /* 188794 */ GIR_ConstrainOperandRC, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62391 /* 188800 */ GIR_ConstrainOperandRC, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62392 /* 188806 */ GIR_MakeTempReg, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TypeID*/GILLT_s64,
62393 /* 188810 */ GIR_BuildMI, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62394 /* 188815 */ GIR_AddTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62395 /* 188822 */ GIR_AddSimpleTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/,
62396 /* 188827 */ GIR_AddImm8, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Imm*/32,
62397 /* 188831 */ GIR_AddImm8, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Imm*/31,
62398 /* 188835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 190(*/0xBE, 0x01/*)*/,
62399 /* 188838 */ GIR_MakeTempReg, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TypeID*/GILLT_s64,
62400 /* 188842 */ GIR_BuildMI, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62401 /* 188847 */ GIR_AddTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62402 /* 188854 */ GIR_AddSimpleTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/,
62403 /* 188859 */ GIR_AddImm, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62404 /* 188870 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 189(*/0xBD, 0x01/*)*/,
62405 /* 188873 */ GIR_MakeTempReg, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TypeID*/GILLT_s64,
62406 /* 188877 */ GIR_BuildMI, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62407 /* 188882 */ GIR_AddTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62408 /* 188889 */ GIR_AddSimpleTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/,
62409 /* 188894 */ GIR_AddImm, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62410 /* 188905 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 188(*/0xBC, 0x01/*)*/,
62411 /* 188908 */ GIR_MakeTempReg, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TypeID*/GILLT_s64,
62412 /* 188912 */ GIR_BuildMI, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62413 /* 188917 */ GIR_AddTempRegister, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62414 /* 188924 */ GIR_Copy, /*NewInsnID*//* 187(*/0xBB, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62415 /* 188929 */ GIR_AddImm8, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Imm*/1,
62416 /* 188933 */ GIR_AddImm8, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Imm*/62,
62417 /* 188937 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 187(*/0xBB, 0x01/*)*/,
62418 /* 188940 */ GIR_MakeTempReg, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TypeID*/GILLT_s64,
62419 /* 188944 */ GIR_BuildMI, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62420 /* 188949 */ GIR_AddTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62421 /* 188956 */ GIR_AddSimpleTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/,
62422 /* 188961 */ GIR_AddSimpleTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/,
62423 /* 188966 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 186(*/0xBA, 0x01/*)*/,
62424 /* 188969 */ GIR_MakeTempReg, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TypeID*/GILLT_s32,
62425 /* 188973 */ GIR_BuildMI, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62426 /* 188978 */ GIR_AddTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62427 /* 188985 */ GIR_AddImm, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62428 /* 188996 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 185(*/0xB9, 0x01/*)*/,
62429 /* 188999 */ GIR_MakeTempReg, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TypeID*/GILLT_s32,
62430 /* 189003 */ GIR_BuildMI, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62431 /* 189008 */ GIR_AddTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62432 /* 189015 */ GIR_AddSimpleTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/,
62433 /* 189020 */ GIR_AddImm, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62434 /* 189031 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 184(*/0xB8, 0x01/*)*/,
62435 /* 189034 */ GIR_MakeTempReg, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TypeID*/GILLT_s64,
62436 /* 189038 */ GIR_BuildMI, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62437 /* 189043 */ GIR_AddTempRegister, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62438 /* 189050 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 183(*/0xB7, 0x01/*)*/,
62439 /* 189053 */ GIR_MakeTempReg, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TypeID*/GILLT_s64,
62440 /* 189057 */ GIR_BuildMI, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62441 /* 189062 */ GIR_AddTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62442 /* 189069 */ GIR_AddSimpleTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/,
62443 /* 189074 */ GIR_AddSimpleTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/,
62444 /* 189079 */ GIR_AddImm8, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/1,
62445 /* 189083 */ GIR_ConstrainOperandRC, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62446 /* 189089 */ GIR_ConstrainOperandRC, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62447 /* 189095 */ GIR_ConstrainOperandRC, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62448 /* 189101 */ GIR_MakeTempReg, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TypeID*/GILLT_s64,
62449 /* 189105 */ GIR_BuildMI, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62450 /* 189110 */ GIR_AddTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62451 /* 189117 */ GIR_AddSimpleTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/,
62452 /* 189122 */ GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/32,
62453 /* 189126 */ GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/31,
62454 /* 189130 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 181(*/0xB5, 0x01/*)*/,
62455 /* 189133 */ GIR_MakeTempReg, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TypeID*/GILLT_s64,
62456 /* 189137 */ GIR_BuildMI, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62457 /* 189142 */ GIR_AddTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62458 /* 189149 */ GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/,
62459 /* 189154 */ GIR_AddImm, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62460 /* 189165 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 180(*/0xB4, 0x01/*)*/,
62461 /* 189168 */ GIR_MakeTempReg, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TypeID*/GILLT_s64,
62462 /* 189172 */ GIR_BuildMI, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62463 /* 189177 */ GIR_AddTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62464 /* 189184 */ GIR_AddSimpleTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/,
62465 /* 189189 */ GIR_AddImm, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62466 /* 189200 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 179(*/0xB3, 0x01/*)*/,
62467 /* 189203 */ GIR_MakeTempReg, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TypeID*/GILLT_s64,
62468 /* 189207 */ GIR_BuildMI, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
62469 /* 189212 */ GIR_AddTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62470 /* 189219 */ GIR_Copy, /*NewInsnID*//* 178(*/0xB2, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62471 /* 189224 */ GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/63,
62472 /* 189228 */ GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/1,
62473 /* 189232 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 178(*/0xB2, 0x01/*)*/,
62474 /* 189235 */ GIR_MakeTempReg, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TypeID*/GILLT_s64,
62475 /* 189239 */ GIR_BuildMI, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62476 /* 189244 */ GIR_AddTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62477 /* 189251 */ GIR_AddSimpleTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/,
62478 /* 189256 */ GIR_AddSimpleTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/,
62479 /* 189261 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 177(*/0xB1, 0x01/*)*/,
62480 /* 189264 */ GIR_MakeTempReg, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TypeID*/GILLT_s64,
62481 /* 189268 */ GIR_BuildMI, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
62482 /* 189273 */ GIR_AddTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62483 /* 189280 */ GIR_AddSimpleTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/,
62484 /* 189285 */ GIR_AddSimpleTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/,
62485 /* 189290 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 176(*/0xB0, 0x01/*)*/,
62486 /* 189293 */ GIR_MakeTempReg, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TypeID*/GILLT_s64,
62487 /* 189297 */ GIR_BuildMI, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62488 /* 189302 */ GIR_AddTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62489 /* 189309 */ GIR_AddSimpleTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/,
62490 /* 189314 */ GIR_AddImm8, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Imm*/2,
62491 /* 189318 */ GIR_AddImm8, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Imm*/61,
62492 /* 189322 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 175(*/0xAF, 0x01/*)*/,
62493 /* 189325 */ GIR_MakeTempReg, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TypeID*/GILLT_s64,
62494 /* 189329 */ GIR_BuildMI, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62495 /* 189334 */ GIR_AddTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62496 /* 189341 */ GIR_AddSimpleTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/,
62497 /* 189346 */ GIR_AddSimpleTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 194(*/0xC2, 0x01/*)*/,
62498 /* 189351 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 174(*/0xAE, 0x01/*)*/,
62499 /* 189354 */ GIR_MakeTempReg, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TypeID*/GILLT_s32,
62500 /* 189358 */ GIR_BuildMI, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62501 /* 189363 */ GIR_AddTempRegister, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62502 /* 189370 */ GIR_AddImm, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
62503 /* 189381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 173(*/0xAD, 0x01/*)*/,
62504 /* 189384 */ GIR_MakeTempReg, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TypeID*/GILLT_s32,
62505 /* 189388 */ GIR_BuildMI, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62506 /* 189393 */ GIR_AddTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62507 /* 189400 */ GIR_AddSimpleTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/,
62508 /* 189405 */ GIR_AddImm, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
62509 /* 189416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 172(*/0xAC, 0x01/*)*/,
62510 /* 189419 */ GIR_MakeTempReg, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TypeID*/GILLT_s64,
62511 /* 189423 */ GIR_BuildMI, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62512 /* 189428 */ GIR_AddTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62513 /* 189435 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 171(*/0xAB, 0x01/*)*/,
62514 /* 189438 */ GIR_MakeTempReg, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TypeID*/GILLT_s64,
62515 /* 189442 */ GIR_BuildMI, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62516 /* 189447 */ GIR_AddTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62517 /* 189454 */ GIR_AddSimpleTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/,
62518 /* 189459 */ GIR_AddSimpleTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/,
62519 /* 189464 */ GIR_AddImm8, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Imm*/1,
62520 /* 189468 */ GIR_ConstrainOperandRC, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62521 /* 189474 */ GIR_ConstrainOperandRC, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62522 /* 189480 */ GIR_ConstrainOperandRC, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62523 /* 189486 */ GIR_MakeTempReg, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TypeID*/GILLT_s64,
62524 /* 189490 */ GIR_BuildMI, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62525 /* 189495 */ GIR_AddTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62526 /* 189502 */ GIR_AddSimpleTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/,
62527 /* 189507 */ GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/32,
62528 /* 189511 */ GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/31,
62529 /* 189515 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 169(*/0xA9, 0x01/*)*/,
62530 /* 189518 */ GIR_MakeTempReg, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TypeID*/GILLT_s64,
62531 /* 189522 */ GIR_BuildMI, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62532 /* 189527 */ GIR_AddTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62533 /* 189534 */ GIR_AddSimpleTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/,
62534 /* 189539 */ GIR_AddImm, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
62535 /* 189550 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 168(*/0xA8, 0x01/*)*/,
62536 /* 189553 */ GIR_MakeTempReg, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TypeID*/GILLT_s64,
62537 /* 189557 */ GIR_BuildMI, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62538 /* 189562 */ GIR_AddTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62539 /* 189569 */ GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/,
62540 /* 189574 */ GIR_AddImm, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107),
62541 /* 189585 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 167(*/0xA7, 0x01/*)*/,
62542 /* 189588 */ GIR_MakeTempReg, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TypeID*/GILLT_s32,
62543 /* 189592 */ GIR_BuildMI, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62544 /* 189597 */ GIR_AddTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62545 /* 189604 */ GIR_AddImm, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62546 /* 189615 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 166(*/0xA6, 0x01/*)*/,
62547 /* 189618 */ GIR_MakeTempReg, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TypeID*/GILLT_s32,
62548 /* 189622 */ GIR_BuildMI, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62549 /* 189627 */ GIR_AddTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62550 /* 189634 */ GIR_AddSimpleTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/,
62551 /* 189639 */ GIR_AddImm, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62552 /* 189650 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 165(*/0xA5, 0x01/*)*/,
62553 /* 189653 */ GIR_MakeTempReg, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TypeID*/GILLT_s64,
62554 /* 189657 */ GIR_BuildMI, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62555 /* 189662 */ GIR_AddTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62556 /* 189669 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 164(*/0xA4, 0x01/*)*/,
62557 /* 189672 */ GIR_MakeTempReg, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TypeID*/GILLT_s64,
62558 /* 189676 */ GIR_BuildMI, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62559 /* 189681 */ GIR_AddTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62560 /* 189688 */ GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/,
62561 /* 189693 */ GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/,
62562 /* 189698 */ GIR_AddImm8, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Imm*/1,
62563 /* 189702 */ GIR_ConstrainOperandRC, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62564 /* 189708 */ GIR_ConstrainOperandRC, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62565 /* 189714 */ GIR_ConstrainOperandRC, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62566 /* 189720 */ GIR_MakeTempReg, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TypeID*/GILLT_s64,
62567 /* 189724 */ GIR_BuildMI, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62568 /* 189729 */ GIR_AddTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62569 /* 189736 */ GIR_AddSimpleTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/,
62570 /* 189741 */ GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/32,
62571 /* 189745 */ GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/31,
62572 /* 189749 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 162(*/0xA2, 0x01/*)*/,
62573 /* 189752 */ GIR_MakeTempReg, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TypeID*/GILLT_s64,
62574 /* 189756 */ GIR_BuildMI, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62575 /* 189761 */ GIR_AddTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62576 /* 189768 */ GIR_AddSimpleTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/,
62577 /* 189773 */ GIR_AddImm, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62578 /* 189784 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 161(*/0xA1, 0x01/*)*/,
62579 /* 189787 */ GIR_MakeTempReg, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TypeID*/GILLT_s64,
62580 /* 189791 */ GIR_BuildMI, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62581 /* 189796 */ GIR_AddTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62582 /* 189803 */ GIR_AddSimpleTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/,
62583 /* 189808 */ GIR_AddImm, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690),
62584 /* 189819 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 160(*/0xA0, 0x01/*)*/,
62585 /* 189822 */ GIR_MakeTempReg, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TypeID*/GILLT_s64,
62586 /* 189826 */ GIR_BuildMI, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62587 /* 189831 */ GIR_AddTempRegister, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62588 /* 189838 */ GIR_Copy, /*NewInsnID*//* 159(*/0x9F, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62589 /* 189843 */ GIR_AddImm8, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Imm*/1,
62590 /* 189847 */ GIR_AddImm8, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Imm*/62,
62591 /* 189851 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 159(*/0x9F, 0x01/*)*/,
62592 /* 189854 */ GIR_MakeTempReg, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TypeID*/GILLT_s64,
62593 /* 189858 */ GIR_BuildMI, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62594 /* 189863 */ GIR_AddTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62595 /* 189870 */ GIR_AddSimpleTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/,
62596 /* 189875 */ GIR_AddSimpleTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/,
62597 /* 189880 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 158(*/0x9E, 0x01/*)*/,
62598 /* 189883 */ GIR_MakeTempReg, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TypeID*/GILLT_s32,
62599 /* 189887 */ GIR_BuildMI, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62600 /* 189892 */ GIR_AddTempRegister, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62601 /* 189899 */ GIR_AddImm, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62602 /* 189910 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 157(*/0x9D, 0x01/*)*/,
62603 /* 189913 */ GIR_MakeTempReg, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TypeID*/GILLT_s32,
62604 /* 189917 */ GIR_BuildMI, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62605 /* 189922 */ GIR_AddTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62606 /* 189929 */ GIR_AddSimpleTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/,
62607 /* 189934 */ GIR_AddImm, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62608 /* 189945 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 156(*/0x9C, 0x01/*)*/,
62609 /* 189948 */ GIR_MakeTempReg, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TypeID*/GILLT_s64,
62610 /* 189952 */ GIR_BuildMI, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62611 /* 189957 */ GIR_AddTempRegister, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62612 /* 189964 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 155(*/0x9B, 0x01/*)*/,
62613 /* 189967 */ GIR_MakeTempReg, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TypeID*/GILLT_s64,
62614 /* 189971 */ GIR_BuildMI, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62615 /* 189976 */ GIR_AddTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62616 /* 189983 */ GIR_AddSimpleTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/,
62617 /* 189988 */ GIR_AddSimpleTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/,
62618 /* 189993 */ GIR_AddImm8, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Imm*/1,
62619 /* 189997 */ GIR_ConstrainOperandRC, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62620 /* 190003 */ GIR_ConstrainOperandRC, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62621 /* 190009 */ GIR_ConstrainOperandRC, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62622 /* 190015 */ GIR_MakeTempReg, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TypeID*/GILLT_s64,
62623 /* 190019 */ GIR_BuildMI, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62624 /* 190024 */ GIR_AddTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62625 /* 190031 */ GIR_AddSimpleTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/,
62626 /* 190036 */ GIR_AddImm8, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Imm*/32,
62627 /* 190040 */ GIR_AddImm8, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Imm*/31,
62628 /* 190044 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 153(*/0x99, 0x01/*)*/,
62629 /* 190047 */ GIR_MakeTempReg, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TypeID*/GILLT_s64,
62630 /* 190051 */ GIR_BuildMI, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62631 /* 190056 */ GIR_AddTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62632 /* 190063 */ GIR_AddSimpleTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/,
62633 /* 190068 */ GIR_AddImm, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62634 /* 190079 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 152(*/0x98, 0x01/*)*/,
62635 /* 190082 */ GIR_MakeTempReg, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TypeID*/GILLT_s64,
62636 /* 190086 */ GIR_BuildMI, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62637 /* 190091 */ GIR_AddTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62638 /* 190098 */ GIR_AddSimpleTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/,
62639 /* 190103 */ GIR_AddImm, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845),
62640 /* 190114 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 151(*/0x97, 0x01/*)*/,
62641 /* 190117 */ GIR_MakeTempReg, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TypeID*/GILLT_s64,
62642 /* 190121 */ GIR_BuildMI, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
62643 /* 190126 */ GIR_AddTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62644 /* 190133 */ GIR_Copy, /*NewInsnID*//* 150(*/0x96, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62645 /* 190138 */ GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/63,
62646 /* 190142 */ GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/1,
62647 /* 190146 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 150(*/0x96, 0x01/*)*/,
62648 /* 190149 */ GIR_MakeTempReg, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TypeID*/GILLT_s64,
62649 /* 190153 */ GIR_BuildMI, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62650 /* 190158 */ GIR_AddTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62651 /* 190165 */ GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/,
62652 /* 190170 */ GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/,
62653 /* 190175 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 149(*/0x95, 0x01/*)*/,
62654 /* 190178 */ GIR_MakeTempReg, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TypeID*/GILLT_s64,
62655 /* 190182 */ GIR_BuildMI, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
62656 /* 190187 */ GIR_AddTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62657 /* 190194 */ GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/,
62658 /* 190199 */ GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/,
62659 /* 190204 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 148(*/0x94, 0x01/*)*/,
62660 /* 190207 */ GIR_MakeTempReg, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TypeID*/GILLT_s64,
62661 /* 190211 */ GIR_BuildMI, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
62662 /* 190216 */ GIR_AddTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62663 /* 190223 */ GIR_AddSimpleTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/,
62664 /* 190228 */ GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/62,
62665 /* 190232 */ GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/2,
62666 /* 190236 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 147(*/0x93, 0x01/*)*/,
62667 /* 190239 */ GIR_MakeTempReg, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TypeID*/GILLT_s64,
62668 /* 190243 */ GIR_BuildMI, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62669 /* 190248 */ GIR_AddTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62670 /* 190255 */ GIR_AddSimpleTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/,
62671 /* 190260 */ GIR_AddSimpleTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/,
62672 /* 190265 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 146(*/0x92, 0x01/*)*/,
62673 /* 190268 */ GIR_MakeTempReg, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TypeID*/GILLT_s64,
62674 /* 190272 */ GIR_BuildMI, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
62675 /* 190277 */ GIR_AddTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62676 /* 190284 */ GIR_AddSimpleTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/,
62677 /* 190289 */ GIR_AddSimpleTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/,
62678 /* 190294 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 145(*/0x91, 0x01/*)*/,
62679 /* 190297 */ GIR_MakeTempReg, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TypeID*/GILLT_s64,
62680 /* 190301 */ GIR_BuildMI, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
62681 /* 190306 */ GIR_AddTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62682 /* 190313 */ GIR_AddSimpleTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/,
62683 /* 190318 */ GIR_AddImm8, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Imm*/60,
62684 /* 190322 */ GIR_AddImm8, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Imm*/4,
62685 /* 190326 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 144(*/0x90, 0x01/*)*/,
62686 /* 190329 */ GIR_MakeTempReg, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TypeID*/GILLT_s64,
62687 /* 190333 */ GIR_BuildMI, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62688 /* 190338 */ GIR_AddTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62689 /* 190345 */ GIR_AddSimpleTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/,
62690 /* 190350 */ GIR_AddSimpleTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 201(*/0xC9, 0x01/*)*/,
62691 /* 190355 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 143(*/0x8F, 0x01/*)*/,
62692 /* 190358 */ GIR_MakeTempReg, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TypeID*/GILLT_s64,
62693 /* 190362 */ GIR_BuildMI, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
62694 /* 190367 */ GIR_AddTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62695 /* 190374 */ GIR_AddSimpleTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/,
62696 /* 190379 */ GIR_AddSimpleTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 208(*/0xD0, 0x01/*)*/,
62697 /* 190384 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 142(*/0x8E, 0x01/*)*/,
62698 /* 190387 */ GIR_MakeTempReg, /*TempRegID*//* 407(*/0x97, 0x03/*)*/, /*TypeID*/GILLT_s32,
62699 /* 190391 */ GIR_BuildMI, /*InsnID*//* 408(*/0x98, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62700 /* 190396 */ GIR_AddTempRegister, /*InsnID*//* 408(*/0x98, 0x03/*)*/, /*TempRegID*//* 407(*/0x97, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62701 /* 190403 */ GIR_AddImm, /*InsnID*//* 408(*/0x98, 0x03/*)*/, /*Imm*/GIMT_Encode8(61680),
62702 /* 190414 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 408(*/0x98, 0x03/*)*/,
62703 /* 190417 */ GIR_MakeTempReg, /*TempRegID*//* 406(*/0x96, 0x03/*)*/, /*TypeID*/GILLT_s32,
62704 /* 190421 */ GIR_BuildMI, /*InsnID*//* 407(*/0x97, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62705 /* 190426 */ GIR_AddTempRegister, /*InsnID*//* 407(*/0x97, 0x03/*)*/, /*TempRegID*//* 406(*/0x96, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62706 /* 190433 */ GIR_AddSimpleTempRegister, /*InsnID*//* 407(*/0x97, 0x03/*)*/, /*TempRegID*//* 407(*/0x97, 0x03/*)*/,
62707 /* 190438 */ GIR_AddImm, /*InsnID*//* 407(*/0x97, 0x03/*)*/, /*Imm*/GIMT_Encode8(61680),
62708 /* 190449 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 407(*/0x97, 0x03/*)*/,
62709 /* 190452 */ GIR_MakeTempReg, /*TempRegID*//* 405(*/0x95, 0x03/*)*/, /*TypeID*/GILLT_s64,
62710 /* 190456 */ GIR_BuildMI, /*InsnID*//* 406(*/0x96, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62711 /* 190461 */ GIR_AddTempRegister, /*InsnID*//* 406(*/0x96, 0x03/*)*/, /*TempRegID*//* 405(*/0x95, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62712 /* 190468 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 406(*/0x96, 0x03/*)*/,
62713 /* 190471 */ GIR_MakeTempReg, /*TempRegID*//* 404(*/0x94, 0x03/*)*/, /*TypeID*/GILLT_s64,
62714 /* 190475 */ GIR_BuildMI, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62715 /* 190480 */ GIR_AddTempRegister, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*TempRegID*//* 404(*/0x94, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62716 /* 190487 */ GIR_AddSimpleTempRegister, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*TempRegID*//* 405(*/0x95, 0x03/*)*/,
62717 /* 190492 */ GIR_AddSimpleTempRegister, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*TempRegID*//* 406(*/0x96, 0x03/*)*/,
62718 /* 190497 */ GIR_AddImm8, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Imm*/1,
62719 /* 190501 */ GIR_ConstrainOperandRC, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62720 /* 190507 */ GIR_ConstrainOperandRC, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62721 /* 190513 */ GIR_ConstrainOperandRC, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62722 /* 190519 */ GIR_MakeTempReg, /*TempRegID*//* 403(*/0x93, 0x03/*)*/, /*TypeID*/GILLT_s64,
62723 /* 190523 */ GIR_BuildMI, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62724 /* 190528 */ GIR_AddTempRegister, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*TempRegID*//* 403(*/0x93, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62725 /* 190535 */ GIR_AddSimpleTempRegister, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*TempRegID*//* 404(*/0x94, 0x03/*)*/,
62726 /* 190540 */ GIR_AddImm8, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*Imm*/32,
62727 /* 190544 */ GIR_AddImm8, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*Imm*/31,
62728 /* 190548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 404(*/0x94, 0x03/*)*/,
62729 /* 190551 */ GIR_MakeTempReg, /*TempRegID*//* 402(*/0x92, 0x03/*)*/, /*TypeID*/GILLT_s64,
62730 /* 190555 */ GIR_BuildMI, /*InsnID*//* 403(*/0x93, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62731 /* 190560 */ GIR_AddTempRegister, /*InsnID*//* 403(*/0x93, 0x03/*)*/, /*TempRegID*//* 402(*/0x92, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62732 /* 190567 */ GIR_AddSimpleTempRegister, /*InsnID*//* 403(*/0x93, 0x03/*)*/, /*TempRegID*//* 403(*/0x93, 0x03/*)*/,
62733 /* 190572 */ GIR_AddImm, /*InsnID*//* 403(*/0x93, 0x03/*)*/, /*Imm*/GIMT_Encode8(61680),
62734 /* 190583 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 403(*/0x93, 0x03/*)*/,
62735 /* 190586 */ GIR_MakeTempReg, /*TempRegID*//* 401(*/0x91, 0x03/*)*/, /*TypeID*/GILLT_s64,
62736 /* 190590 */ GIR_BuildMI, /*InsnID*//* 402(*/0x92, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62737 /* 190595 */ GIR_AddTempRegister, /*InsnID*//* 402(*/0x92, 0x03/*)*/, /*TempRegID*//* 401(*/0x91, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62738 /* 190602 */ GIR_AddSimpleTempRegister, /*InsnID*//* 402(*/0x92, 0x03/*)*/, /*TempRegID*//* 402(*/0x92, 0x03/*)*/,
62739 /* 190607 */ GIR_AddImm, /*InsnID*//* 402(*/0x92, 0x03/*)*/, /*Imm*/GIMT_Encode8(61680),
62740 /* 190618 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 402(*/0x92, 0x03/*)*/,
62741 /* 190621 */ GIR_MakeTempReg, /*TempRegID*//* 400(*/0x90, 0x03/*)*/, /*TypeID*/GILLT_s32,
62742 /* 190625 */ GIR_BuildMI, /*InsnID*//* 401(*/0x91, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62743 /* 190630 */ GIR_AddTempRegister, /*InsnID*//* 401(*/0x91, 0x03/*)*/, /*TempRegID*//* 400(*/0x90, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62744 /* 190637 */ GIR_AddImm, /*InsnID*//* 401(*/0x91, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428),
62745 /* 190648 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 401(*/0x91, 0x03/*)*/,
62746 /* 190651 */ GIR_MakeTempReg, /*TempRegID*//* 399(*/0x8F, 0x03/*)*/, /*TypeID*/GILLT_s32,
62747 /* 190655 */ GIR_BuildMI, /*InsnID*//* 400(*/0x90, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62748 /* 190660 */ GIR_AddTempRegister, /*InsnID*//* 400(*/0x90, 0x03/*)*/, /*TempRegID*//* 399(*/0x8F, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62749 /* 190667 */ GIR_AddSimpleTempRegister, /*InsnID*//* 400(*/0x90, 0x03/*)*/, /*TempRegID*//* 400(*/0x90, 0x03/*)*/,
62750 /* 190672 */ GIR_AddImm, /*InsnID*//* 400(*/0x90, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428),
62751 /* 190683 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 400(*/0x90, 0x03/*)*/,
62752 /* 190686 */ GIR_MakeTempReg, /*TempRegID*//* 398(*/0x8E, 0x03/*)*/, /*TypeID*/GILLT_s64,
62753 /* 190690 */ GIR_BuildMI, /*InsnID*//* 399(*/0x8F, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62754 /* 190695 */ GIR_AddTempRegister, /*InsnID*//* 399(*/0x8F, 0x03/*)*/, /*TempRegID*//* 398(*/0x8E, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62755 /* 190702 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 399(*/0x8F, 0x03/*)*/,
62756 /* 190705 */ GIR_MakeTempReg, /*TempRegID*//* 397(*/0x8D, 0x03/*)*/, /*TypeID*/GILLT_s64,
62757 /* 190709 */ GIR_BuildMI, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62758 /* 190714 */ GIR_AddTempRegister, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*TempRegID*//* 397(*/0x8D, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62759 /* 190721 */ GIR_AddSimpleTempRegister, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*TempRegID*//* 398(*/0x8E, 0x03/*)*/,
62760 /* 190726 */ GIR_AddSimpleTempRegister, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*TempRegID*//* 399(*/0x8F, 0x03/*)*/,
62761 /* 190731 */ GIR_AddImm8, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Imm*/1,
62762 /* 190735 */ GIR_ConstrainOperandRC, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62763 /* 190741 */ GIR_ConstrainOperandRC, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62764 /* 190747 */ GIR_ConstrainOperandRC, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62765 /* 190753 */ GIR_MakeTempReg, /*TempRegID*//* 396(*/0x8C, 0x03/*)*/, /*TypeID*/GILLT_s64,
62766 /* 190757 */ GIR_BuildMI, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62767 /* 190762 */ GIR_AddTempRegister, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*TempRegID*//* 396(*/0x8C, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62768 /* 190769 */ GIR_AddSimpleTempRegister, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*TempRegID*//* 397(*/0x8D, 0x03/*)*/,
62769 /* 190774 */ GIR_AddImm8, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*Imm*/32,
62770 /* 190778 */ GIR_AddImm8, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*Imm*/31,
62771 /* 190782 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 397(*/0x8D, 0x03/*)*/,
62772 /* 190785 */ GIR_MakeTempReg, /*TempRegID*//* 395(*/0x8B, 0x03/*)*/, /*TypeID*/GILLT_s64,
62773 /* 190789 */ GIR_BuildMI, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62774 /* 190794 */ GIR_AddTempRegister, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, /*TempRegID*//* 395(*/0x8B, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62775 /* 190801 */ GIR_AddSimpleTempRegister, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, /*TempRegID*//* 396(*/0x8C, 0x03/*)*/,
62776 /* 190806 */ GIR_AddImm, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428),
62777 /* 190817 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 396(*/0x8C, 0x03/*)*/,
62778 /* 190820 */ GIR_MakeTempReg, /*TempRegID*//* 394(*/0x8A, 0x03/*)*/, /*TypeID*/GILLT_s64,
62779 /* 190824 */ GIR_BuildMI, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62780 /* 190829 */ GIR_AddTempRegister, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, /*TempRegID*//* 394(*/0x8A, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62781 /* 190836 */ GIR_AddSimpleTempRegister, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, /*TempRegID*//* 395(*/0x8B, 0x03/*)*/,
62782 /* 190841 */ GIR_AddImm, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428),
62783 /* 190852 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 395(*/0x8B, 0x03/*)*/,
62784 /* 190855 */ GIR_MakeTempReg, /*TempRegID*//* 393(*/0x89, 0x03/*)*/, /*TypeID*/GILLT_s32,
62785 /* 190859 */ GIR_BuildMI, /*InsnID*//* 394(*/0x8A, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62786 /* 190864 */ GIR_AddTempRegister, /*InsnID*//* 394(*/0x8A, 0x03/*)*/, /*TempRegID*//* 393(*/0x89, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62787 /* 190871 */ GIR_AddImm, /*InsnID*//* 394(*/0x8A, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
62788 /* 190882 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 394(*/0x8A, 0x03/*)*/,
62789 /* 190885 */ GIR_MakeTempReg, /*TempRegID*//* 392(*/0x88, 0x03/*)*/, /*TypeID*/GILLT_s32,
62790 /* 190889 */ GIR_BuildMI, /*InsnID*//* 393(*/0x89, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62791 /* 190894 */ GIR_AddTempRegister, /*InsnID*//* 393(*/0x89, 0x03/*)*/, /*TempRegID*//* 392(*/0x88, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62792 /* 190901 */ GIR_AddSimpleTempRegister, /*InsnID*//* 393(*/0x89, 0x03/*)*/, /*TempRegID*//* 393(*/0x89, 0x03/*)*/,
62793 /* 190906 */ GIR_AddImm, /*InsnID*//* 393(*/0x89, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
62794 /* 190917 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 393(*/0x89, 0x03/*)*/,
62795 /* 190920 */ GIR_MakeTempReg, /*TempRegID*//* 391(*/0x87, 0x03/*)*/, /*TypeID*/GILLT_s64,
62796 /* 190924 */ GIR_BuildMI, /*InsnID*//* 392(*/0x88, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62797 /* 190929 */ GIR_AddTempRegister, /*InsnID*//* 392(*/0x88, 0x03/*)*/, /*TempRegID*//* 391(*/0x87, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62798 /* 190936 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 392(*/0x88, 0x03/*)*/,
62799 /* 190939 */ GIR_MakeTempReg, /*TempRegID*//* 390(*/0x86, 0x03/*)*/, /*TypeID*/GILLT_s64,
62800 /* 190943 */ GIR_BuildMI, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62801 /* 190948 */ GIR_AddTempRegister, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*TempRegID*//* 390(*/0x86, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62802 /* 190955 */ GIR_AddSimpleTempRegister, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*TempRegID*//* 391(*/0x87, 0x03/*)*/,
62803 /* 190960 */ GIR_AddSimpleTempRegister, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*TempRegID*//* 392(*/0x88, 0x03/*)*/,
62804 /* 190965 */ GIR_AddImm8, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Imm*/1,
62805 /* 190969 */ GIR_ConstrainOperandRC, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62806 /* 190975 */ GIR_ConstrainOperandRC, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62807 /* 190981 */ GIR_ConstrainOperandRC, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62808 /* 190987 */ GIR_MakeTempReg, /*TempRegID*//* 389(*/0x85, 0x03/*)*/, /*TypeID*/GILLT_s64,
62809 /* 190991 */ GIR_BuildMI, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62810 /* 190996 */ GIR_AddTempRegister, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*TempRegID*//* 389(*/0x85, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62811 /* 191003 */ GIR_AddSimpleTempRegister, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*TempRegID*//* 390(*/0x86, 0x03/*)*/,
62812 /* 191008 */ GIR_AddImm8, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*Imm*/32,
62813 /* 191012 */ GIR_AddImm8, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*Imm*/31,
62814 /* 191016 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 390(*/0x86, 0x03/*)*/,
62815 /* 191019 */ GIR_MakeTempReg, /*TempRegID*//* 388(*/0x84, 0x03/*)*/, /*TypeID*/GILLT_s64,
62816 /* 191023 */ GIR_BuildMI, /*InsnID*//* 389(*/0x85, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62817 /* 191028 */ GIR_AddTempRegister, /*InsnID*//* 389(*/0x85, 0x03/*)*/, /*TempRegID*//* 388(*/0x84, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62818 /* 191035 */ GIR_AddSimpleTempRegister, /*InsnID*//* 389(*/0x85, 0x03/*)*/, /*TempRegID*//* 389(*/0x85, 0x03/*)*/,
62819 /* 191040 */ GIR_AddImm, /*InsnID*//* 389(*/0x85, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
62820 /* 191051 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 389(*/0x85, 0x03/*)*/,
62821 /* 191054 */ GIR_MakeTempReg, /*TempRegID*//* 387(*/0x83, 0x03/*)*/, /*TypeID*/GILLT_s64,
62822 /* 191058 */ GIR_BuildMI, /*InsnID*//* 388(*/0x84, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62823 /* 191063 */ GIR_AddTempRegister, /*InsnID*//* 388(*/0x84, 0x03/*)*/, /*TempRegID*//* 387(*/0x83, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62824 /* 191070 */ GIR_AddSimpleTempRegister, /*InsnID*//* 388(*/0x84, 0x03/*)*/, /*TempRegID*//* 388(*/0x84, 0x03/*)*/,
62825 /* 191075 */ GIR_AddImm, /*InsnID*//* 388(*/0x84, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
62826 /* 191086 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 388(*/0x84, 0x03/*)*/,
62827 /* 191089 */ GIR_MakeTempReg, /*TempRegID*//* 386(*/0x82, 0x03/*)*/, /*TypeID*/GILLT_s64,
62828 /* 191093 */ GIR_BuildMI, /*InsnID*//* 387(*/0x83, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62829 /* 191098 */ GIR_AddTempRegister, /*InsnID*//* 387(*/0x83, 0x03/*)*/, /*TempRegID*//* 386(*/0x82, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62830 /* 191105 */ GIR_Copy, /*NewInsnID*//* 387(*/0x83, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62831 /* 191110 */ GIR_AddImm8, /*InsnID*//* 387(*/0x83, 0x03/*)*/, /*Imm*/1,
62832 /* 191114 */ GIR_AddImm8, /*InsnID*//* 387(*/0x83, 0x03/*)*/, /*Imm*/62,
62833 /* 191118 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 387(*/0x83, 0x03/*)*/,
62834 /* 191121 */ GIR_MakeTempReg, /*TempRegID*//* 385(*/0x81, 0x03/*)*/, /*TypeID*/GILLT_s64,
62835 /* 191125 */ GIR_BuildMI, /*InsnID*//* 386(*/0x82, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62836 /* 191130 */ GIR_AddTempRegister, /*InsnID*//* 386(*/0x82, 0x03/*)*/, /*TempRegID*//* 385(*/0x81, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62837 /* 191137 */ GIR_AddSimpleTempRegister, /*InsnID*//* 386(*/0x82, 0x03/*)*/, /*TempRegID*//* 386(*/0x82, 0x03/*)*/,
62838 /* 191142 */ GIR_AddSimpleTempRegister, /*InsnID*//* 386(*/0x82, 0x03/*)*/, /*TempRegID*//* 387(*/0x83, 0x03/*)*/,
62839 /* 191147 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 386(*/0x82, 0x03/*)*/,
62840 /* 191150 */ GIR_MakeTempReg, /*TempRegID*//* 384(*/0x80, 0x03/*)*/, /*TypeID*/GILLT_s32,
62841 /* 191154 */ GIR_BuildMI, /*InsnID*//* 385(*/0x81, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62842 /* 191159 */ GIR_AddTempRegister, /*InsnID*//* 385(*/0x81, 0x03/*)*/, /*TempRegID*//* 384(*/0x80, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62843 /* 191166 */ GIR_AddImm, /*InsnID*//* 385(*/0x81, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
62844 /* 191177 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 385(*/0x81, 0x03/*)*/,
62845 /* 191180 */ GIR_MakeTempReg, /*TempRegID*//* 383(*/0xFF, 0x02/*)*/, /*TypeID*/GILLT_s32,
62846 /* 191184 */ GIR_BuildMI, /*InsnID*//* 384(*/0x80, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62847 /* 191189 */ GIR_AddTempRegister, /*InsnID*//* 384(*/0x80, 0x03/*)*/, /*TempRegID*//* 383(*/0xFF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62848 /* 191196 */ GIR_AddSimpleTempRegister, /*InsnID*//* 384(*/0x80, 0x03/*)*/, /*TempRegID*//* 384(*/0x80, 0x03/*)*/,
62849 /* 191201 */ GIR_AddImm, /*InsnID*//* 384(*/0x80, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
62850 /* 191212 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 384(*/0x80, 0x03/*)*/,
62851 /* 191215 */ GIR_MakeTempReg, /*TempRegID*//* 382(*/0xFE, 0x02/*)*/, /*TypeID*/GILLT_s64,
62852 /* 191219 */ GIR_BuildMI, /*InsnID*//* 383(*/0xFF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62853 /* 191224 */ GIR_AddTempRegister, /*InsnID*//* 383(*/0xFF, 0x02/*)*/, /*TempRegID*//* 382(*/0xFE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62854 /* 191231 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 383(*/0xFF, 0x02/*)*/,
62855 /* 191234 */ GIR_MakeTempReg, /*TempRegID*//* 381(*/0xFD, 0x02/*)*/, /*TypeID*/GILLT_s64,
62856 /* 191238 */ GIR_BuildMI, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62857 /* 191243 */ GIR_AddTempRegister, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*TempRegID*//* 381(*/0xFD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62858 /* 191250 */ GIR_AddSimpleTempRegister, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*TempRegID*//* 382(*/0xFE, 0x02/*)*/,
62859 /* 191255 */ GIR_AddSimpleTempRegister, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*TempRegID*//* 383(*/0xFF, 0x02/*)*/,
62860 /* 191260 */ GIR_AddImm8, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Imm*/1,
62861 /* 191264 */ GIR_ConstrainOperandRC, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62862 /* 191270 */ GIR_ConstrainOperandRC, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62863 /* 191276 */ GIR_ConstrainOperandRC, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62864 /* 191282 */ GIR_MakeTempReg, /*TempRegID*//* 380(*/0xFC, 0x02/*)*/, /*TypeID*/GILLT_s64,
62865 /* 191286 */ GIR_BuildMI, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62866 /* 191291 */ GIR_AddTempRegister, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*TempRegID*//* 380(*/0xFC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62867 /* 191298 */ GIR_AddSimpleTempRegister, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*TempRegID*//* 381(*/0xFD, 0x02/*)*/,
62868 /* 191303 */ GIR_AddImm8, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*Imm*/32,
62869 /* 191307 */ GIR_AddImm8, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*Imm*/31,
62870 /* 191311 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 381(*/0xFD, 0x02/*)*/,
62871 /* 191314 */ GIR_MakeTempReg, /*TempRegID*//* 379(*/0xFB, 0x02/*)*/, /*TypeID*/GILLT_s64,
62872 /* 191318 */ GIR_BuildMI, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62873 /* 191323 */ GIR_AddTempRegister, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, /*TempRegID*//* 379(*/0xFB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62874 /* 191330 */ GIR_AddSimpleTempRegister, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, /*TempRegID*//* 380(*/0xFC, 0x02/*)*/,
62875 /* 191335 */ GIR_AddImm, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
62876 /* 191346 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 380(*/0xFC, 0x02/*)*/,
62877 /* 191349 */ GIR_MakeTempReg, /*TempRegID*//* 378(*/0xFA, 0x02/*)*/, /*TypeID*/GILLT_s64,
62878 /* 191353 */ GIR_BuildMI, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62879 /* 191358 */ GIR_AddTempRegister, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, /*TempRegID*//* 378(*/0xFA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62880 /* 191365 */ GIR_AddSimpleTempRegister, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, /*TempRegID*//* 379(*/0xFB, 0x02/*)*/,
62881 /* 191370 */ GIR_AddImm, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
62882 /* 191381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 379(*/0xFB, 0x02/*)*/,
62883 /* 191384 */ GIR_MakeTempReg, /*TempRegID*//* 377(*/0xF9, 0x02/*)*/, /*TypeID*/GILLT_s64,
62884 /* 191388 */ GIR_BuildMI, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
62885 /* 191393 */ GIR_AddTempRegister, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, /*TempRegID*//* 377(*/0xF9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62886 /* 191400 */ GIR_Copy, /*NewInsnID*//* 378(*/0xFA, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
62887 /* 191405 */ GIR_AddImm8, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, /*Imm*/63,
62888 /* 191409 */ GIR_AddImm8, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, /*Imm*/1,
62889 /* 191413 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 378(*/0xFA, 0x02/*)*/,
62890 /* 191416 */ GIR_MakeTempReg, /*TempRegID*//* 376(*/0xF8, 0x02/*)*/, /*TypeID*/GILLT_s64,
62891 /* 191420 */ GIR_BuildMI, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62892 /* 191425 */ GIR_AddTempRegister, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, /*TempRegID*//* 376(*/0xF8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62893 /* 191432 */ GIR_AddSimpleTempRegister, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, /*TempRegID*//* 377(*/0xF9, 0x02/*)*/,
62894 /* 191437 */ GIR_AddSimpleTempRegister, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, /*TempRegID*//* 378(*/0xFA, 0x02/*)*/,
62895 /* 191442 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 377(*/0xF9, 0x02/*)*/,
62896 /* 191445 */ GIR_MakeTempReg, /*TempRegID*//* 375(*/0xF7, 0x02/*)*/, /*TypeID*/GILLT_s64,
62897 /* 191449 */ GIR_BuildMI, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
62898 /* 191454 */ GIR_AddTempRegister, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, /*TempRegID*//* 375(*/0xF7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62899 /* 191461 */ GIR_AddSimpleTempRegister, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, /*TempRegID*//* 376(*/0xF8, 0x02/*)*/,
62900 /* 191466 */ GIR_AddSimpleTempRegister, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, /*TempRegID*//* 385(*/0x81, 0x03/*)*/,
62901 /* 191471 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 376(*/0xF8, 0x02/*)*/,
62902 /* 191474 */ GIR_MakeTempReg, /*TempRegID*//* 374(*/0xF6, 0x02/*)*/, /*TypeID*/GILLT_s64,
62903 /* 191478 */ GIR_BuildMI, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62904 /* 191483 */ GIR_AddTempRegister, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*TempRegID*//* 374(*/0xF6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62905 /* 191490 */ GIR_AddSimpleTempRegister, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*TempRegID*//* 375(*/0xF7, 0x02/*)*/,
62906 /* 191495 */ GIR_AddImm8, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*Imm*/2,
62907 /* 191499 */ GIR_AddImm8, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*Imm*/61,
62908 /* 191503 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 375(*/0xF7, 0x02/*)*/,
62909 /* 191506 */ GIR_MakeTempReg, /*TempRegID*//* 373(*/0xF5, 0x02/*)*/, /*TypeID*/GILLT_s64,
62910 /* 191510 */ GIR_BuildMI, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
62911 /* 191515 */ GIR_AddTempRegister, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, /*TempRegID*//* 373(*/0xF5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62912 /* 191522 */ GIR_AddSimpleTempRegister, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, /*TempRegID*//* 374(*/0xF6, 0x02/*)*/,
62913 /* 191527 */ GIR_AddSimpleTempRegister, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, /*TempRegID*//* 394(*/0x8A, 0x03/*)*/,
62914 /* 191532 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 374(*/0xF6, 0x02/*)*/,
62915 /* 191535 */ GIR_MakeTempReg, /*TempRegID*//* 372(*/0xF4, 0x02/*)*/, /*TypeID*/GILLT_s32,
62916 /* 191539 */ GIR_BuildMI, /*InsnID*//* 373(*/0xF5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62917 /* 191544 */ GIR_AddTempRegister, /*InsnID*//* 373(*/0xF5, 0x02/*)*/, /*TempRegID*//* 372(*/0xF4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62918 /* 191551 */ GIR_AddImm, /*InsnID*//* 373(*/0xF5, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107),
62919 /* 191562 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 373(*/0xF5, 0x02/*)*/,
62920 /* 191565 */ GIR_MakeTempReg, /*TempRegID*//* 371(*/0xF3, 0x02/*)*/, /*TypeID*/GILLT_s32,
62921 /* 191569 */ GIR_BuildMI, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62922 /* 191574 */ GIR_AddTempRegister, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, /*TempRegID*//* 371(*/0xF3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62923 /* 191581 */ GIR_AddSimpleTempRegister, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, /*TempRegID*//* 372(*/0xF4, 0x02/*)*/,
62924 /* 191586 */ GIR_AddImm, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107),
62925 /* 191597 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 372(*/0xF4, 0x02/*)*/,
62926 /* 191600 */ GIR_MakeTempReg, /*TempRegID*//* 370(*/0xF2, 0x02/*)*/, /*TypeID*/GILLT_s64,
62927 /* 191604 */ GIR_BuildMI, /*InsnID*//* 371(*/0xF3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62928 /* 191609 */ GIR_AddTempRegister, /*InsnID*//* 371(*/0xF3, 0x02/*)*/, /*TempRegID*//* 370(*/0xF2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62929 /* 191616 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 371(*/0xF3, 0x02/*)*/,
62930 /* 191619 */ GIR_MakeTempReg, /*TempRegID*//* 369(*/0xF1, 0x02/*)*/, /*TypeID*/GILLT_s64,
62931 /* 191623 */ GIR_BuildMI, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62932 /* 191628 */ GIR_AddTempRegister, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*TempRegID*//* 369(*/0xF1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62933 /* 191635 */ GIR_AddSimpleTempRegister, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*TempRegID*//* 370(*/0xF2, 0x02/*)*/,
62934 /* 191640 */ GIR_AddSimpleTempRegister, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*TempRegID*//* 371(*/0xF3, 0x02/*)*/,
62935 /* 191645 */ GIR_AddImm8, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Imm*/1,
62936 /* 191649 */ GIR_ConstrainOperandRC, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62937 /* 191655 */ GIR_ConstrainOperandRC, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62938 /* 191661 */ GIR_ConstrainOperandRC, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62939 /* 191667 */ GIR_MakeTempReg, /*TempRegID*//* 368(*/0xF0, 0x02/*)*/, /*TypeID*/GILLT_s64,
62940 /* 191671 */ GIR_BuildMI, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62941 /* 191676 */ GIR_AddTempRegister, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*TempRegID*//* 368(*/0xF0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62942 /* 191683 */ GIR_AddSimpleTempRegister, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*TempRegID*//* 369(*/0xF1, 0x02/*)*/,
62943 /* 191688 */ GIR_AddImm8, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*Imm*/32,
62944 /* 191692 */ GIR_AddImm8, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*Imm*/31,
62945 /* 191696 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 369(*/0xF1, 0x02/*)*/,
62946 /* 191699 */ GIR_MakeTempReg, /*TempRegID*//* 367(*/0xEF, 0x02/*)*/, /*TypeID*/GILLT_s64,
62947 /* 191703 */ GIR_BuildMI, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62948 /* 191708 */ GIR_AddTempRegister, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, /*TempRegID*//* 367(*/0xEF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62949 /* 191715 */ GIR_AddSimpleTempRegister, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, /*TempRegID*//* 368(*/0xF0, 0x02/*)*/,
62950 /* 191720 */ GIR_AddImm, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107),
62951 /* 191731 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 368(*/0xF0, 0x02/*)*/,
62952 /* 191734 */ GIR_MakeTempReg, /*TempRegID*//* 366(*/0xEE, 0x02/*)*/, /*TypeID*/GILLT_s64,
62953 /* 191738 */ GIR_BuildMI, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62954 /* 191743 */ GIR_AddTempRegister, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, /*TempRegID*//* 366(*/0xEE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62955 /* 191750 */ GIR_AddSimpleTempRegister, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, /*TempRegID*//* 367(*/0xEF, 0x02/*)*/,
62956 /* 191755 */ GIR_AddImm, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107),
62957 /* 191766 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 367(*/0xEF, 0x02/*)*/,
62958 /* 191769 */ GIR_MakeTempReg, /*TempRegID*//* 365(*/0xED, 0x02/*)*/, /*TypeID*/GILLT_s32,
62959 /* 191773 */ GIR_BuildMI, /*InsnID*//* 366(*/0xEE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
62960 /* 191778 */ GIR_AddTempRegister, /*InsnID*//* 366(*/0xEE, 0x02/*)*/, /*TempRegID*//* 365(*/0xED, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62961 /* 191785 */ GIR_AddImm, /*InsnID*//* 366(*/0xEE, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
62962 /* 191796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 366(*/0xEE, 0x02/*)*/,
62963 /* 191799 */ GIR_MakeTempReg, /*TempRegID*//* 364(*/0xEC, 0x02/*)*/, /*TypeID*/GILLT_s32,
62964 /* 191803 */ GIR_BuildMI, /*InsnID*//* 365(*/0xED, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
62965 /* 191808 */ GIR_AddTempRegister, /*InsnID*//* 365(*/0xED, 0x02/*)*/, /*TempRegID*//* 364(*/0xEC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62966 /* 191815 */ GIR_AddSimpleTempRegister, /*InsnID*//* 365(*/0xED, 0x02/*)*/, /*TempRegID*//* 365(*/0xED, 0x02/*)*/,
62967 /* 191820 */ GIR_AddImm, /*InsnID*//* 365(*/0xED, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
62968 /* 191831 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 365(*/0xED, 0x02/*)*/,
62969 /* 191834 */ GIR_MakeTempReg, /*TempRegID*//* 363(*/0xEB, 0x02/*)*/, /*TypeID*/GILLT_s64,
62970 /* 191838 */ GIR_BuildMI, /*InsnID*//* 364(*/0xEC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
62971 /* 191843 */ GIR_AddTempRegister, /*InsnID*//* 364(*/0xEC, 0x02/*)*/, /*TempRegID*//* 363(*/0xEB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62972 /* 191850 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 364(*/0xEC, 0x02/*)*/,
62973 /* 191853 */ GIR_MakeTempReg, /*TempRegID*//* 362(*/0xEA, 0x02/*)*/, /*TypeID*/GILLT_s64,
62974 /* 191857 */ GIR_BuildMI, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
62975 /* 191862 */ GIR_AddTempRegister, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*TempRegID*//* 362(*/0xEA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62976 /* 191869 */ GIR_AddSimpleTempRegister, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*TempRegID*//* 363(*/0xEB, 0x02/*)*/,
62977 /* 191874 */ GIR_AddSimpleTempRegister, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*TempRegID*//* 364(*/0xEC, 0x02/*)*/,
62978 /* 191879 */ GIR_AddImm8, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Imm*/1,
62979 /* 191883 */ GIR_ConstrainOperandRC, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
62980 /* 191889 */ GIR_ConstrainOperandRC, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
62981 /* 191895 */ GIR_ConstrainOperandRC, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
62982 /* 191901 */ GIR_MakeTempReg, /*TempRegID*//* 361(*/0xE9, 0x02/*)*/, /*TypeID*/GILLT_s64,
62983 /* 191905 */ GIR_BuildMI, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
62984 /* 191910 */ GIR_AddTempRegister, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*TempRegID*//* 361(*/0xE9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62985 /* 191917 */ GIR_AddSimpleTempRegister, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*TempRegID*//* 362(*/0xEA, 0x02/*)*/,
62986 /* 191922 */ GIR_AddImm8, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*Imm*/32,
62987 /* 191926 */ GIR_AddImm8, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*Imm*/31,
62988 /* 191930 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 362(*/0xEA, 0x02/*)*/,
62989 /* 191933 */ GIR_MakeTempReg, /*TempRegID*//* 360(*/0xE8, 0x02/*)*/, /*TypeID*/GILLT_s64,
62990 /* 191937 */ GIR_BuildMI, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
62991 /* 191942 */ GIR_AddTempRegister, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, /*TempRegID*//* 360(*/0xE8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62992 /* 191949 */ GIR_AddSimpleTempRegister, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, /*TempRegID*//* 361(*/0xE9, 0x02/*)*/,
62993 /* 191954 */ GIR_AddImm, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
62994 /* 191965 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 361(*/0xE9, 0x02/*)*/,
62995 /* 191968 */ GIR_MakeTempReg, /*TempRegID*//* 359(*/0xE7, 0x02/*)*/, /*TypeID*/GILLT_s64,
62996 /* 191972 */ GIR_BuildMI, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
62997 /* 191977 */ GIR_AddTempRegister, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, /*TempRegID*//* 359(*/0xE7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
62998 /* 191984 */ GIR_AddSimpleTempRegister, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, /*TempRegID*//* 360(*/0xE8, 0x02/*)*/,
62999 /* 191989 */ GIR_AddImm, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63000 /* 192000 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 360(*/0xE8, 0x02/*)*/,
63001 /* 192003 */ GIR_MakeTempReg, /*TempRegID*//* 358(*/0xE6, 0x02/*)*/, /*TypeID*/GILLT_s64,
63002 /* 192007 */ GIR_BuildMI, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63003 /* 192012 */ GIR_AddTempRegister, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, /*TempRegID*//* 358(*/0xE6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63004 /* 192019 */ GIR_Copy, /*NewInsnID*//* 359(*/0xE7, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63005 /* 192024 */ GIR_AddImm8, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, /*Imm*/1,
63006 /* 192028 */ GIR_AddImm8, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, /*Imm*/62,
63007 /* 192032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 359(*/0xE7, 0x02/*)*/,
63008 /* 192035 */ GIR_MakeTempReg, /*TempRegID*//* 357(*/0xE5, 0x02/*)*/, /*TypeID*/GILLT_s64,
63009 /* 192039 */ GIR_BuildMI, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63010 /* 192044 */ GIR_AddTempRegister, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, /*TempRegID*//* 357(*/0xE5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63011 /* 192051 */ GIR_AddSimpleTempRegister, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, /*TempRegID*//* 358(*/0xE6, 0x02/*)*/,
63012 /* 192056 */ GIR_AddSimpleTempRegister, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, /*TempRegID*//* 359(*/0xE7, 0x02/*)*/,
63013 /* 192061 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 358(*/0xE6, 0x02/*)*/,
63014 /* 192064 */ GIR_MakeTempReg, /*TempRegID*//* 356(*/0xE4, 0x02/*)*/, /*TypeID*/GILLT_s32,
63015 /* 192068 */ GIR_BuildMI, /*InsnID*//* 357(*/0xE5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63016 /* 192073 */ GIR_AddTempRegister, /*InsnID*//* 357(*/0xE5, 0x02/*)*/, /*TempRegID*//* 356(*/0xE4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63017 /* 192080 */ GIR_AddImm, /*InsnID*//* 357(*/0xE5, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63018 /* 192091 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 357(*/0xE5, 0x02/*)*/,
63019 /* 192094 */ GIR_MakeTempReg, /*TempRegID*//* 355(*/0xE3, 0x02/*)*/, /*TypeID*/GILLT_s32,
63020 /* 192098 */ GIR_BuildMI, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63021 /* 192103 */ GIR_AddTempRegister, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, /*TempRegID*//* 355(*/0xE3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63022 /* 192110 */ GIR_AddSimpleTempRegister, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, /*TempRegID*//* 356(*/0xE4, 0x02/*)*/,
63023 /* 192115 */ GIR_AddImm, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63024 /* 192126 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 356(*/0xE4, 0x02/*)*/,
63025 /* 192129 */ GIR_MakeTempReg, /*TempRegID*//* 354(*/0xE2, 0x02/*)*/, /*TypeID*/GILLT_s64,
63026 /* 192133 */ GIR_BuildMI, /*InsnID*//* 355(*/0xE3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63027 /* 192138 */ GIR_AddTempRegister, /*InsnID*//* 355(*/0xE3, 0x02/*)*/, /*TempRegID*//* 354(*/0xE2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63028 /* 192145 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 355(*/0xE3, 0x02/*)*/,
63029 /* 192148 */ GIR_MakeTempReg, /*TempRegID*//* 353(*/0xE1, 0x02/*)*/, /*TypeID*/GILLT_s64,
63030 /* 192152 */ GIR_BuildMI, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63031 /* 192157 */ GIR_AddTempRegister, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*TempRegID*//* 353(*/0xE1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63032 /* 192164 */ GIR_AddSimpleTempRegister, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*TempRegID*//* 354(*/0xE2, 0x02/*)*/,
63033 /* 192169 */ GIR_AddSimpleTempRegister, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*TempRegID*//* 355(*/0xE3, 0x02/*)*/,
63034 /* 192174 */ GIR_AddImm8, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Imm*/1,
63035 /* 192178 */ GIR_ConstrainOperandRC, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63036 /* 192184 */ GIR_ConstrainOperandRC, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63037 /* 192190 */ GIR_ConstrainOperandRC, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63038 /* 192196 */ GIR_MakeTempReg, /*TempRegID*//* 352(*/0xE0, 0x02/*)*/, /*TypeID*/GILLT_s64,
63039 /* 192200 */ GIR_BuildMI, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63040 /* 192205 */ GIR_AddTempRegister, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*TempRegID*//* 352(*/0xE0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63041 /* 192212 */ GIR_AddSimpleTempRegister, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*TempRegID*//* 353(*/0xE1, 0x02/*)*/,
63042 /* 192217 */ GIR_AddImm8, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*Imm*/32,
63043 /* 192221 */ GIR_AddImm8, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*Imm*/31,
63044 /* 192225 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 353(*/0xE1, 0x02/*)*/,
63045 /* 192228 */ GIR_MakeTempReg, /*TempRegID*//* 351(*/0xDF, 0x02/*)*/, /*TypeID*/GILLT_s64,
63046 /* 192232 */ GIR_BuildMI, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63047 /* 192237 */ GIR_AddTempRegister, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, /*TempRegID*//* 351(*/0xDF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63048 /* 192244 */ GIR_AddSimpleTempRegister, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, /*TempRegID*//* 352(*/0xE0, 0x02/*)*/,
63049 /* 192249 */ GIR_AddImm, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63050 /* 192260 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 352(*/0xE0, 0x02/*)*/,
63051 /* 192263 */ GIR_MakeTempReg, /*TempRegID*//* 350(*/0xDE, 0x02/*)*/, /*TypeID*/GILLT_s64,
63052 /* 192267 */ GIR_BuildMI, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63053 /* 192272 */ GIR_AddTempRegister, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, /*TempRegID*//* 350(*/0xDE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63054 /* 192279 */ GIR_AddSimpleTempRegister, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, /*TempRegID*//* 351(*/0xDF, 0x02/*)*/,
63055 /* 192284 */ GIR_AddImm, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63056 /* 192295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 351(*/0xDF, 0x02/*)*/,
63057 /* 192298 */ GIR_MakeTempReg, /*TempRegID*//* 349(*/0xDD, 0x02/*)*/, /*TypeID*/GILLT_s64,
63058 /* 192302 */ GIR_BuildMI, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63059 /* 192307 */ GIR_AddTempRegister, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, /*TempRegID*//* 349(*/0xDD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63060 /* 192314 */ GIR_Copy, /*NewInsnID*//* 350(*/0xDE, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63061 /* 192319 */ GIR_AddImm8, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, /*Imm*/63,
63062 /* 192323 */ GIR_AddImm8, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, /*Imm*/1,
63063 /* 192327 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 350(*/0xDE, 0x02/*)*/,
63064 /* 192330 */ GIR_MakeTempReg, /*TempRegID*//* 348(*/0xDC, 0x02/*)*/, /*TypeID*/GILLT_s64,
63065 /* 192334 */ GIR_BuildMI, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63066 /* 192339 */ GIR_AddTempRegister, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, /*TempRegID*//* 348(*/0xDC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63067 /* 192346 */ GIR_AddSimpleTempRegister, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, /*TempRegID*//* 349(*/0xDD, 0x02/*)*/,
63068 /* 192351 */ GIR_AddSimpleTempRegister, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, /*TempRegID*//* 350(*/0xDE, 0x02/*)*/,
63069 /* 192356 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 349(*/0xDD, 0x02/*)*/,
63070 /* 192359 */ GIR_MakeTempReg, /*TempRegID*//* 347(*/0xDB, 0x02/*)*/, /*TypeID*/GILLT_s64,
63071 /* 192363 */ GIR_BuildMI, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63072 /* 192368 */ GIR_AddTempRegister, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, /*TempRegID*//* 347(*/0xDB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63073 /* 192375 */ GIR_AddSimpleTempRegister, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, /*TempRegID*//* 348(*/0xDC, 0x02/*)*/,
63074 /* 192380 */ GIR_AddSimpleTempRegister, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, /*TempRegID*//* 357(*/0xE5, 0x02/*)*/,
63075 /* 192385 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 348(*/0xDC, 0x02/*)*/,
63076 /* 192388 */ GIR_MakeTempReg, /*TempRegID*//* 346(*/0xDA, 0x02/*)*/, /*TypeID*/GILLT_s64,
63077 /* 192392 */ GIR_BuildMI, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63078 /* 192397 */ GIR_AddTempRegister, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*TempRegID*//* 346(*/0xDA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63079 /* 192404 */ GIR_AddSimpleTempRegister, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*TempRegID*//* 347(*/0xDB, 0x02/*)*/,
63080 /* 192409 */ GIR_AddImm8, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*Imm*/62,
63081 /* 192413 */ GIR_AddImm8, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*Imm*/2,
63082 /* 192417 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 347(*/0xDB, 0x02/*)*/,
63083 /* 192420 */ GIR_MakeTempReg, /*TempRegID*//* 345(*/0xD9, 0x02/*)*/, /*TypeID*/GILLT_s64,
63084 /* 192424 */ GIR_BuildMI, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63085 /* 192429 */ GIR_AddTempRegister, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, /*TempRegID*//* 345(*/0xD9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63086 /* 192436 */ GIR_AddSimpleTempRegister, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, /*TempRegID*//* 346(*/0xDA, 0x02/*)*/,
63087 /* 192441 */ GIR_AddSimpleTempRegister, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, /*TempRegID*//* 366(*/0xEE, 0x02/*)*/,
63088 /* 192446 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 346(*/0xDA, 0x02/*)*/,
63089 /* 192449 */ GIR_MakeTempReg, /*TempRegID*//* 344(*/0xD8, 0x02/*)*/, /*TypeID*/GILLT_s64,
63090 /* 192453 */ GIR_BuildMI, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63091 /* 192458 */ GIR_AddTempRegister, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, /*TempRegID*//* 344(*/0xD8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63092 /* 192465 */ GIR_AddSimpleTempRegister, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, /*TempRegID*//* 345(*/0xD9, 0x02/*)*/,
63093 /* 192470 */ GIR_AddSimpleTempRegister, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, /*TempRegID*//* 373(*/0xF5, 0x02/*)*/,
63094 /* 192475 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 345(*/0xD9, 0x02/*)*/,
63095 /* 192478 */ GIR_MakeTempReg, /*TempRegID*//* 343(*/0xD7, 0x02/*)*/, /*TypeID*/GILLT_s64,
63096 /* 192482 */ GIR_BuildMI, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63097 /* 192487 */ GIR_AddTempRegister, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*TempRegID*//* 343(*/0xD7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63098 /* 192494 */ GIR_AddSimpleTempRegister, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*TempRegID*//* 344(*/0xD8, 0x02/*)*/,
63099 /* 192499 */ GIR_AddImm8, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*Imm*/4,
63100 /* 192503 */ GIR_AddImm8, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*Imm*/59,
63101 /* 192507 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 344(*/0xD8, 0x02/*)*/,
63102 /* 192510 */ GIR_MakeTempReg, /*TempRegID*//* 342(*/0xD6, 0x02/*)*/, /*TypeID*/GILLT_s64,
63103 /* 192514 */ GIR_BuildMI, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63104 /* 192519 */ GIR_AddTempRegister, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, /*TempRegID*//* 342(*/0xD6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63105 /* 192526 */ GIR_AddSimpleTempRegister, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, /*TempRegID*//* 343(*/0xD7, 0x02/*)*/,
63106 /* 192531 */ GIR_AddSimpleTempRegister, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, /*TempRegID*//* 401(*/0x91, 0x03/*)*/,
63107 /* 192536 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 343(*/0xD7, 0x02/*)*/,
63108 /* 192539 */ GIR_MakeTempReg, /*TempRegID*//* 341(*/0xD5, 0x02/*)*/, /*TypeID*/GILLT_s32,
63109 /* 192543 */ GIR_BuildMI, /*InsnID*//* 342(*/0xD6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63110 /* 192548 */ GIR_AddTempRegister, /*InsnID*//* 342(*/0xD6, 0x02/*)*/, /*TempRegID*//* 341(*/0xD5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63111 /* 192555 */ GIR_AddImm, /*InsnID*//* 342(*/0xD6, 0x02/*)*/, /*Imm*/GIMT_Encode8(3855),
63112 /* 192566 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 342(*/0xD6, 0x02/*)*/,
63113 /* 192569 */ GIR_MakeTempReg, /*TempRegID*//* 340(*/0xD4, 0x02/*)*/, /*TypeID*/GILLT_s32,
63114 /* 192573 */ GIR_BuildMI, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63115 /* 192578 */ GIR_AddTempRegister, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, /*TempRegID*//* 340(*/0xD4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63116 /* 192585 */ GIR_AddSimpleTempRegister, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, /*TempRegID*//* 341(*/0xD5, 0x02/*)*/,
63117 /* 192590 */ GIR_AddImm, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, /*Imm*/GIMT_Encode8(3855),
63118 /* 192601 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 341(*/0xD5, 0x02/*)*/,
63119 /* 192604 */ GIR_MakeTempReg, /*TempRegID*//* 339(*/0xD3, 0x02/*)*/, /*TypeID*/GILLT_s64,
63120 /* 192608 */ GIR_BuildMI, /*InsnID*//* 340(*/0xD4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63121 /* 192613 */ GIR_AddTempRegister, /*InsnID*//* 340(*/0xD4, 0x02/*)*/, /*TempRegID*//* 339(*/0xD3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63122 /* 192620 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 340(*/0xD4, 0x02/*)*/,
63123 /* 192623 */ GIR_MakeTempReg, /*TempRegID*//* 338(*/0xD2, 0x02/*)*/, /*TypeID*/GILLT_s64,
63124 /* 192627 */ GIR_BuildMI, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63125 /* 192632 */ GIR_AddTempRegister, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*TempRegID*//* 338(*/0xD2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63126 /* 192639 */ GIR_AddSimpleTempRegister, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*TempRegID*//* 339(*/0xD3, 0x02/*)*/,
63127 /* 192644 */ GIR_AddSimpleTempRegister, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*TempRegID*//* 340(*/0xD4, 0x02/*)*/,
63128 /* 192649 */ GIR_AddImm8, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Imm*/1,
63129 /* 192653 */ GIR_ConstrainOperandRC, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63130 /* 192659 */ GIR_ConstrainOperandRC, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63131 /* 192665 */ GIR_ConstrainOperandRC, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63132 /* 192671 */ GIR_MakeTempReg, /*TempRegID*//* 337(*/0xD1, 0x02/*)*/, /*TypeID*/GILLT_s64,
63133 /* 192675 */ GIR_BuildMI, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63134 /* 192680 */ GIR_AddTempRegister, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*TempRegID*//* 337(*/0xD1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63135 /* 192687 */ GIR_AddSimpleTempRegister, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*TempRegID*//* 338(*/0xD2, 0x02/*)*/,
63136 /* 192692 */ GIR_AddImm8, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*Imm*/32,
63137 /* 192696 */ GIR_AddImm8, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*Imm*/31,
63138 /* 192700 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 338(*/0xD2, 0x02/*)*/,
63139 /* 192703 */ GIR_MakeTempReg, /*TempRegID*//* 336(*/0xD0, 0x02/*)*/, /*TypeID*/GILLT_s64,
63140 /* 192707 */ GIR_BuildMI, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63141 /* 192712 */ GIR_AddTempRegister, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, /*TempRegID*//* 336(*/0xD0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63142 /* 192719 */ GIR_AddSimpleTempRegister, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, /*TempRegID*//* 337(*/0xD1, 0x02/*)*/,
63143 /* 192724 */ GIR_AddImm, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, /*Imm*/GIMT_Encode8(3855),
63144 /* 192735 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 337(*/0xD1, 0x02/*)*/,
63145 /* 192738 */ GIR_MakeTempReg, /*TempRegID*//* 335(*/0xCF, 0x02/*)*/, /*TypeID*/GILLT_s64,
63146 /* 192742 */ GIR_BuildMI, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63147 /* 192747 */ GIR_AddTempRegister, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, /*TempRegID*//* 335(*/0xCF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63148 /* 192754 */ GIR_AddSimpleTempRegister, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, /*TempRegID*//* 336(*/0xD0, 0x02/*)*/,
63149 /* 192759 */ GIR_AddImm, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, /*Imm*/GIMT_Encode8(3855),
63150 /* 192770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 336(*/0xD0, 0x02/*)*/,
63151 /* 192773 */ GIR_MakeTempReg, /*TempRegID*//* 334(*/0xCE, 0x02/*)*/, /*TypeID*/GILLT_s32,
63152 /* 192777 */ GIR_BuildMI, /*InsnID*//* 335(*/0xCF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63153 /* 192782 */ GIR_AddTempRegister, /*InsnID*//* 335(*/0xCF, 0x02/*)*/, /*TempRegID*//* 334(*/0xCE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63154 /* 192789 */ GIR_AddImm, /*InsnID*//* 335(*/0xCF, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428),
63155 /* 192800 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 335(*/0xCF, 0x02/*)*/,
63156 /* 192803 */ GIR_MakeTempReg, /*TempRegID*//* 333(*/0xCD, 0x02/*)*/, /*TypeID*/GILLT_s32,
63157 /* 192807 */ GIR_BuildMI, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63158 /* 192812 */ GIR_AddTempRegister, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, /*TempRegID*//* 333(*/0xCD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63159 /* 192819 */ GIR_AddSimpleTempRegister, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, /*TempRegID*//* 334(*/0xCE, 0x02/*)*/,
63160 /* 192824 */ GIR_AddImm, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428),
63161 /* 192835 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 334(*/0xCE, 0x02/*)*/,
63162 /* 192838 */ GIR_MakeTempReg, /*TempRegID*//* 332(*/0xCC, 0x02/*)*/, /*TypeID*/GILLT_s64,
63163 /* 192842 */ GIR_BuildMI, /*InsnID*//* 333(*/0xCD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63164 /* 192847 */ GIR_AddTempRegister, /*InsnID*//* 333(*/0xCD, 0x02/*)*/, /*TempRegID*//* 332(*/0xCC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63165 /* 192854 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 333(*/0xCD, 0x02/*)*/,
63166 /* 192857 */ GIR_MakeTempReg, /*TempRegID*//* 331(*/0xCB, 0x02/*)*/, /*TypeID*/GILLT_s64,
63167 /* 192861 */ GIR_BuildMI, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63168 /* 192866 */ GIR_AddTempRegister, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*TempRegID*//* 331(*/0xCB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63169 /* 192873 */ GIR_AddSimpleTempRegister, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*TempRegID*//* 332(*/0xCC, 0x02/*)*/,
63170 /* 192878 */ GIR_AddSimpleTempRegister, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*TempRegID*//* 333(*/0xCD, 0x02/*)*/,
63171 /* 192883 */ GIR_AddImm8, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Imm*/1,
63172 /* 192887 */ GIR_ConstrainOperandRC, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63173 /* 192893 */ GIR_ConstrainOperandRC, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63174 /* 192899 */ GIR_ConstrainOperandRC, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63175 /* 192905 */ GIR_MakeTempReg, /*TempRegID*//* 330(*/0xCA, 0x02/*)*/, /*TypeID*/GILLT_s64,
63176 /* 192909 */ GIR_BuildMI, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63177 /* 192914 */ GIR_AddTempRegister, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*TempRegID*//* 330(*/0xCA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63178 /* 192921 */ GIR_AddSimpleTempRegister, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*TempRegID*//* 331(*/0xCB, 0x02/*)*/,
63179 /* 192926 */ GIR_AddImm8, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*Imm*/32,
63180 /* 192930 */ GIR_AddImm8, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*Imm*/31,
63181 /* 192934 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 331(*/0xCB, 0x02/*)*/,
63182 /* 192937 */ GIR_MakeTempReg, /*TempRegID*//* 329(*/0xC9, 0x02/*)*/, /*TypeID*/GILLT_s64,
63183 /* 192941 */ GIR_BuildMI, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63184 /* 192946 */ GIR_AddTempRegister, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, /*TempRegID*//* 329(*/0xC9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63185 /* 192953 */ GIR_AddSimpleTempRegister, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, /*TempRegID*//* 330(*/0xCA, 0x02/*)*/,
63186 /* 192958 */ GIR_AddImm, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428),
63187 /* 192969 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 330(*/0xCA, 0x02/*)*/,
63188 /* 192972 */ GIR_MakeTempReg, /*TempRegID*//* 328(*/0xC8, 0x02/*)*/, /*TypeID*/GILLT_s64,
63189 /* 192976 */ GIR_BuildMI, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63190 /* 192981 */ GIR_AddTempRegister, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, /*TempRegID*//* 328(*/0xC8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63191 /* 192988 */ GIR_AddSimpleTempRegister, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, /*TempRegID*//* 329(*/0xC9, 0x02/*)*/,
63192 /* 192993 */ GIR_AddImm, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428),
63193 /* 193004 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 329(*/0xC9, 0x02/*)*/,
63194 /* 193007 */ GIR_MakeTempReg, /*TempRegID*//* 327(*/0xC7, 0x02/*)*/, /*TypeID*/GILLT_s32,
63195 /* 193011 */ GIR_BuildMI, /*InsnID*//* 328(*/0xC8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63196 /* 193016 */ GIR_AddTempRegister, /*InsnID*//* 328(*/0xC8, 0x02/*)*/, /*TempRegID*//* 327(*/0xC7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63197 /* 193023 */ GIR_AddImm, /*InsnID*//* 328(*/0xC8, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63198 /* 193034 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 328(*/0xC8, 0x02/*)*/,
63199 /* 193037 */ GIR_MakeTempReg, /*TempRegID*//* 326(*/0xC6, 0x02/*)*/, /*TypeID*/GILLT_s32,
63200 /* 193041 */ GIR_BuildMI, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63201 /* 193046 */ GIR_AddTempRegister, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, /*TempRegID*//* 326(*/0xC6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63202 /* 193053 */ GIR_AddSimpleTempRegister, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, /*TempRegID*//* 327(*/0xC7, 0x02/*)*/,
63203 /* 193058 */ GIR_AddImm, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63204 /* 193069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 327(*/0xC7, 0x02/*)*/,
63205 /* 193072 */ GIR_MakeTempReg, /*TempRegID*//* 325(*/0xC5, 0x02/*)*/, /*TypeID*/GILLT_s64,
63206 /* 193076 */ GIR_BuildMI, /*InsnID*//* 326(*/0xC6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63207 /* 193081 */ GIR_AddTempRegister, /*InsnID*//* 326(*/0xC6, 0x02/*)*/, /*TempRegID*//* 325(*/0xC5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63208 /* 193088 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 326(*/0xC6, 0x02/*)*/,
63209 /* 193091 */ GIR_MakeTempReg, /*TempRegID*//* 324(*/0xC4, 0x02/*)*/, /*TypeID*/GILLT_s64,
63210 /* 193095 */ GIR_BuildMI, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63211 /* 193100 */ GIR_AddTempRegister, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*TempRegID*//* 324(*/0xC4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63212 /* 193107 */ GIR_AddSimpleTempRegister, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*TempRegID*//* 325(*/0xC5, 0x02/*)*/,
63213 /* 193112 */ GIR_AddSimpleTempRegister, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*TempRegID*//* 326(*/0xC6, 0x02/*)*/,
63214 /* 193117 */ GIR_AddImm8, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Imm*/1,
63215 /* 193121 */ GIR_ConstrainOperandRC, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63216 /* 193127 */ GIR_ConstrainOperandRC, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63217 /* 193133 */ GIR_ConstrainOperandRC, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63218 /* 193139 */ GIR_MakeTempReg, /*TempRegID*//* 323(*/0xC3, 0x02/*)*/, /*TypeID*/GILLT_s64,
63219 /* 193143 */ GIR_BuildMI, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63220 /* 193148 */ GIR_AddTempRegister, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*TempRegID*//* 323(*/0xC3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63221 /* 193155 */ GIR_AddSimpleTempRegister, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*TempRegID*//* 324(*/0xC4, 0x02/*)*/,
63222 /* 193160 */ GIR_AddImm8, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*Imm*/32,
63223 /* 193164 */ GIR_AddImm8, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*Imm*/31,
63224 /* 193168 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 324(*/0xC4, 0x02/*)*/,
63225 /* 193171 */ GIR_MakeTempReg, /*TempRegID*//* 322(*/0xC2, 0x02/*)*/, /*TypeID*/GILLT_s64,
63226 /* 193175 */ GIR_BuildMI, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63227 /* 193180 */ GIR_AddTempRegister, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, /*TempRegID*//* 322(*/0xC2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63228 /* 193187 */ GIR_AddSimpleTempRegister, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, /*TempRegID*//* 323(*/0xC3, 0x02/*)*/,
63229 /* 193192 */ GIR_AddImm, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63230 /* 193203 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 323(*/0xC3, 0x02/*)*/,
63231 /* 193206 */ GIR_MakeTempReg, /*TempRegID*//* 321(*/0xC1, 0x02/*)*/, /*TypeID*/GILLT_s64,
63232 /* 193210 */ GIR_BuildMI, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63233 /* 193215 */ GIR_AddTempRegister, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, /*TempRegID*//* 321(*/0xC1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63234 /* 193222 */ GIR_AddSimpleTempRegister, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, /*TempRegID*//* 322(*/0xC2, 0x02/*)*/,
63235 /* 193227 */ GIR_AddImm, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63236 /* 193238 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 322(*/0xC2, 0x02/*)*/,
63237 /* 193241 */ GIR_MakeTempReg, /*TempRegID*//* 320(*/0xC0, 0x02/*)*/, /*TypeID*/GILLT_s64,
63238 /* 193245 */ GIR_BuildMI, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63239 /* 193250 */ GIR_AddTempRegister, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, /*TempRegID*//* 320(*/0xC0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63240 /* 193257 */ GIR_Copy, /*NewInsnID*//* 321(*/0xC1, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63241 /* 193262 */ GIR_AddImm8, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, /*Imm*/1,
63242 /* 193266 */ GIR_AddImm8, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, /*Imm*/62,
63243 /* 193270 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 321(*/0xC1, 0x02/*)*/,
63244 /* 193273 */ GIR_MakeTempReg, /*TempRegID*//* 319(*/0xBF, 0x02/*)*/, /*TypeID*/GILLT_s64,
63245 /* 193277 */ GIR_BuildMI, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63246 /* 193282 */ GIR_AddTempRegister, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, /*TempRegID*//* 319(*/0xBF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63247 /* 193289 */ GIR_AddSimpleTempRegister, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, /*TempRegID*//* 320(*/0xC0, 0x02/*)*/,
63248 /* 193294 */ GIR_AddSimpleTempRegister, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, /*TempRegID*//* 321(*/0xC1, 0x02/*)*/,
63249 /* 193299 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 320(*/0xC0, 0x02/*)*/,
63250 /* 193302 */ GIR_MakeTempReg, /*TempRegID*//* 318(*/0xBE, 0x02/*)*/, /*TypeID*/GILLT_s32,
63251 /* 193306 */ GIR_BuildMI, /*InsnID*//* 319(*/0xBF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63252 /* 193311 */ GIR_AddTempRegister, /*InsnID*//* 319(*/0xBF, 0x02/*)*/, /*TempRegID*//* 318(*/0xBE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63253 /* 193318 */ GIR_AddImm, /*InsnID*//* 319(*/0xBF, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63254 /* 193329 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 319(*/0xBF, 0x02/*)*/,
63255 /* 193332 */ GIR_MakeTempReg, /*TempRegID*//* 317(*/0xBD, 0x02/*)*/, /*TypeID*/GILLT_s32,
63256 /* 193336 */ GIR_BuildMI, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63257 /* 193341 */ GIR_AddTempRegister, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, /*TempRegID*//* 317(*/0xBD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63258 /* 193348 */ GIR_AddSimpleTempRegister, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, /*TempRegID*//* 318(*/0xBE, 0x02/*)*/,
63259 /* 193353 */ GIR_AddImm, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63260 /* 193364 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 318(*/0xBE, 0x02/*)*/,
63261 /* 193367 */ GIR_MakeTempReg, /*TempRegID*//* 316(*/0xBC, 0x02/*)*/, /*TypeID*/GILLT_s64,
63262 /* 193371 */ GIR_BuildMI, /*InsnID*//* 317(*/0xBD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63263 /* 193376 */ GIR_AddTempRegister, /*InsnID*//* 317(*/0xBD, 0x02/*)*/, /*TempRegID*//* 316(*/0xBC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63264 /* 193383 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 317(*/0xBD, 0x02/*)*/,
63265 /* 193386 */ GIR_MakeTempReg, /*TempRegID*//* 315(*/0xBB, 0x02/*)*/, /*TypeID*/GILLT_s64,
63266 /* 193390 */ GIR_BuildMI, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63267 /* 193395 */ GIR_AddTempRegister, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*TempRegID*//* 315(*/0xBB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63268 /* 193402 */ GIR_AddSimpleTempRegister, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*TempRegID*//* 316(*/0xBC, 0x02/*)*/,
63269 /* 193407 */ GIR_AddSimpleTempRegister, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*TempRegID*//* 317(*/0xBD, 0x02/*)*/,
63270 /* 193412 */ GIR_AddImm8, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Imm*/1,
63271 /* 193416 */ GIR_ConstrainOperandRC, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63272 /* 193422 */ GIR_ConstrainOperandRC, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63273 /* 193428 */ GIR_ConstrainOperandRC, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63274 /* 193434 */ GIR_MakeTempReg, /*TempRegID*//* 314(*/0xBA, 0x02/*)*/, /*TypeID*/GILLT_s64,
63275 /* 193438 */ GIR_BuildMI, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63276 /* 193443 */ GIR_AddTempRegister, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*TempRegID*//* 314(*/0xBA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63277 /* 193450 */ GIR_AddSimpleTempRegister, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*TempRegID*//* 315(*/0xBB, 0x02/*)*/,
63278 /* 193455 */ GIR_AddImm8, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*Imm*/32,
63279 /* 193459 */ GIR_AddImm8, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*Imm*/31,
63280 /* 193463 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 315(*/0xBB, 0x02/*)*/,
63281 /* 193466 */ GIR_MakeTempReg, /*TempRegID*//* 313(*/0xB9, 0x02/*)*/, /*TypeID*/GILLT_s64,
63282 /* 193470 */ GIR_BuildMI, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63283 /* 193475 */ GIR_AddTempRegister, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, /*TempRegID*//* 313(*/0xB9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63284 /* 193482 */ GIR_AddSimpleTempRegister, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, /*TempRegID*//* 314(*/0xBA, 0x02/*)*/,
63285 /* 193487 */ GIR_AddImm, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63286 /* 193498 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 314(*/0xBA, 0x02/*)*/,
63287 /* 193501 */ GIR_MakeTempReg, /*TempRegID*//* 312(*/0xB8, 0x02/*)*/, /*TypeID*/GILLT_s64,
63288 /* 193505 */ GIR_BuildMI, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63289 /* 193510 */ GIR_AddTempRegister, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, /*TempRegID*//* 312(*/0xB8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63290 /* 193517 */ GIR_AddSimpleTempRegister, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, /*TempRegID*//* 313(*/0xB9, 0x02/*)*/,
63291 /* 193522 */ GIR_AddImm, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63292 /* 193533 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 313(*/0xB9, 0x02/*)*/,
63293 /* 193536 */ GIR_MakeTempReg, /*TempRegID*//* 311(*/0xB7, 0x02/*)*/, /*TypeID*/GILLT_s64,
63294 /* 193540 */ GIR_BuildMI, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63295 /* 193545 */ GIR_AddTempRegister, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, /*TempRegID*//* 311(*/0xB7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63296 /* 193552 */ GIR_Copy, /*NewInsnID*//* 312(*/0xB8, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63297 /* 193557 */ GIR_AddImm8, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, /*Imm*/63,
63298 /* 193561 */ GIR_AddImm8, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, /*Imm*/1,
63299 /* 193565 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 312(*/0xB8, 0x02/*)*/,
63300 /* 193568 */ GIR_MakeTempReg, /*TempRegID*//* 310(*/0xB6, 0x02/*)*/, /*TypeID*/GILLT_s64,
63301 /* 193572 */ GIR_BuildMI, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63302 /* 193577 */ GIR_AddTempRegister, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, /*TempRegID*//* 310(*/0xB6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63303 /* 193584 */ GIR_AddSimpleTempRegister, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, /*TempRegID*//* 311(*/0xB7, 0x02/*)*/,
63304 /* 193589 */ GIR_AddSimpleTempRegister, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, /*TempRegID*//* 312(*/0xB8, 0x02/*)*/,
63305 /* 193594 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 311(*/0xB7, 0x02/*)*/,
63306 /* 193597 */ GIR_MakeTempReg, /*TempRegID*//* 309(*/0xB5, 0x02/*)*/, /*TypeID*/GILLT_s64,
63307 /* 193601 */ GIR_BuildMI, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63308 /* 193606 */ GIR_AddTempRegister, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, /*TempRegID*//* 309(*/0xB5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63309 /* 193613 */ GIR_AddSimpleTempRegister, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, /*TempRegID*//* 310(*/0xB6, 0x02/*)*/,
63310 /* 193618 */ GIR_AddSimpleTempRegister, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, /*TempRegID*//* 319(*/0xBF, 0x02/*)*/,
63311 /* 193623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 310(*/0xB6, 0x02/*)*/,
63312 /* 193626 */ GIR_MakeTempReg, /*TempRegID*//* 308(*/0xB4, 0x02/*)*/, /*TypeID*/GILLT_s64,
63313 /* 193630 */ GIR_BuildMI, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63314 /* 193635 */ GIR_AddTempRegister, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*TempRegID*//* 308(*/0xB4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63315 /* 193642 */ GIR_AddSimpleTempRegister, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*TempRegID*//* 309(*/0xB5, 0x02/*)*/,
63316 /* 193647 */ GIR_AddImm8, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*Imm*/2,
63317 /* 193651 */ GIR_AddImm8, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*Imm*/61,
63318 /* 193655 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 309(*/0xB5, 0x02/*)*/,
63319 /* 193658 */ GIR_MakeTempReg, /*TempRegID*//* 307(*/0xB3, 0x02/*)*/, /*TypeID*/GILLT_s64,
63320 /* 193662 */ GIR_BuildMI, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63321 /* 193667 */ GIR_AddTempRegister, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, /*TempRegID*//* 307(*/0xB3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63322 /* 193674 */ GIR_AddSimpleTempRegister, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, /*TempRegID*//* 308(*/0xB4, 0x02/*)*/,
63323 /* 193679 */ GIR_AddSimpleTempRegister, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, /*TempRegID*//* 328(*/0xC8, 0x02/*)*/,
63324 /* 193684 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 308(*/0xB4, 0x02/*)*/,
63325 /* 193687 */ GIR_MakeTempReg, /*TempRegID*//* 306(*/0xB2, 0x02/*)*/, /*TypeID*/GILLT_s32,
63326 /* 193691 */ GIR_BuildMI, /*InsnID*//* 307(*/0xB3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63327 /* 193696 */ GIR_AddTempRegister, /*InsnID*//* 307(*/0xB3, 0x02/*)*/, /*TempRegID*//* 306(*/0xB2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63328 /* 193703 */ GIR_AddImm, /*InsnID*//* 307(*/0xB3, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107),
63329 /* 193714 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 307(*/0xB3, 0x02/*)*/,
63330 /* 193717 */ GIR_MakeTempReg, /*TempRegID*//* 305(*/0xB1, 0x02/*)*/, /*TypeID*/GILLT_s32,
63331 /* 193721 */ GIR_BuildMI, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63332 /* 193726 */ GIR_AddTempRegister, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, /*TempRegID*//* 305(*/0xB1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63333 /* 193733 */ GIR_AddSimpleTempRegister, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, /*TempRegID*//* 306(*/0xB2, 0x02/*)*/,
63334 /* 193738 */ GIR_AddImm, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107),
63335 /* 193749 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 306(*/0xB2, 0x02/*)*/,
63336 /* 193752 */ GIR_MakeTempReg, /*TempRegID*//* 304(*/0xB0, 0x02/*)*/, /*TypeID*/GILLT_s64,
63337 /* 193756 */ GIR_BuildMI, /*InsnID*//* 305(*/0xB1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63338 /* 193761 */ GIR_AddTempRegister, /*InsnID*//* 305(*/0xB1, 0x02/*)*/, /*TempRegID*//* 304(*/0xB0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63339 /* 193768 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 305(*/0xB1, 0x02/*)*/,
63340 /* 193771 */ GIR_MakeTempReg, /*TempRegID*//* 303(*/0xAF, 0x02/*)*/, /*TypeID*/GILLT_s64,
63341 /* 193775 */ GIR_BuildMI, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63342 /* 193780 */ GIR_AddTempRegister, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*TempRegID*//* 303(*/0xAF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63343 /* 193787 */ GIR_AddSimpleTempRegister, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*TempRegID*//* 304(*/0xB0, 0x02/*)*/,
63344 /* 193792 */ GIR_AddSimpleTempRegister, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*TempRegID*//* 305(*/0xB1, 0x02/*)*/,
63345 /* 193797 */ GIR_AddImm8, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Imm*/1,
63346 /* 193801 */ GIR_ConstrainOperandRC, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63347 /* 193807 */ GIR_ConstrainOperandRC, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63348 /* 193813 */ GIR_ConstrainOperandRC, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63349 /* 193819 */ GIR_MakeTempReg, /*TempRegID*//* 302(*/0xAE, 0x02/*)*/, /*TypeID*/GILLT_s64,
63350 /* 193823 */ GIR_BuildMI, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63351 /* 193828 */ GIR_AddTempRegister, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*TempRegID*//* 302(*/0xAE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63352 /* 193835 */ GIR_AddSimpleTempRegister, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*TempRegID*//* 303(*/0xAF, 0x02/*)*/,
63353 /* 193840 */ GIR_AddImm8, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*Imm*/32,
63354 /* 193844 */ GIR_AddImm8, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*Imm*/31,
63355 /* 193848 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 303(*/0xAF, 0x02/*)*/,
63356 /* 193851 */ GIR_MakeTempReg, /*TempRegID*//* 301(*/0xAD, 0x02/*)*/, /*TypeID*/GILLT_s64,
63357 /* 193855 */ GIR_BuildMI, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63358 /* 193860 */ GIR_AddTempRegister, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, /*TempRegID*//* 301(*/0xAD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63359 /* 193867 */ GIR_AddSimpleTempRegister, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, /*TempRegID*//* 302(*/0xAE, 0x02/*)*/,
63360 /* 193872 */ GIR_AddImm, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107),
63361 /* 193883 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 302(*/0xAE, 0x02/*)*/,
63362 /* 193886 */ GIR_MakeTempReg, /*TempRegID*//* 300(*/0xAC, 0x02/*)*/, /*TypeID*/GILLT_s64,
63363 /* 193890 */ GIR_BuildMI, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63364 /* 193895 */ GIR_AddTempRegister, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, /*TempRegID*//* 300(*/0xAC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63365 /* 193902 */ GIR_AddSimpleTempRegister, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, /*TempRegID*//* 301(*/0xAD, 0x02/*)*/,
63366 /* 193907 */ GIR_AddImm, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107),
63367 /* 193918 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 301(*/0xAD, 0x02/*)*/,
63368 /* 193921 */ GIR_MakeTempReg, /*TempRegID*//* 299(*/0xAB, 0x02/*)*/, /*TypeID*/GILLT_s32,
63369 /* 193925 */ GIR_BuildMI, /*InsnID*//* 300(*/0xAC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63370 /* 193930 */ GIR_AddTempRegister, /*InsnID*//* 300(*/0xAC, 0x02/*)*/, /*TempRegID*//* 299(*/0xAB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63371 /* 193937 */ GIR_AddImm, /*InsnID*//* 300(*/0xAC, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63372 /* 193948 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 300(*/0xAC, 0x02/*)*/,
63373 /* 193951 */ GIR_MakeTempReg, /*TempRegID*//* 298(*/0xAA, 0x02/*)*/, /*TypeID*/GILLT_s32,
63374 /* 193955 */ GIR_BuildMI, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63375 /* 193960 */ GIR_AddTempRegister, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, /*TempRegID*//* 298(*/0xAA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63376 /* 193967 */ GIR_AddSimpleTempRegister, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, /*TempRegID*//* 299(*/0xAB, 0x02/*)*/,
63377 /* 193972 */ GIR_AddImm, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63378 /* 193983 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 299(*/0xAB, 0x02/*)*/,
63379 /* 193986 */ GIR_MakeTempReg, /*TempRegID*//* 297(*/0xA9, 0x02/*)*/, /*TypeID*/GILLT_s64,
63380 /* 193990 */ GIR_BuildMI, /*InsnID*//* 298(*/0xAA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63381 /* 193995 */ GIR_AddTempRegister, /*InsnID*//* 298(*/0xAA, 0x02/*)*/, /*TempRegID*//* 297(*/0xA9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63382 /* 194002 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 298(*/0xAA, 0x02/*)*/,
63383 /* 194005 */ GIR_MakeTempReg, /*TempRegID*//* 296(*/0xA8, 0x02/*)*/, /*TypeID*/GILLT_s64,
63384 /* 194009 */ GIR_BuildMI, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63385 /* 194014 */ GIR_AddTempRegister, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*TempRegID*//* 296(*/0xA8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63386 /* 194021 */ GIR_AddSimpleTempRegister, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*TempRegID*//* 297(*/0xA9, 0x02/*)*/,
63387 /* 194026 */ GIR_AddSimpleTempRegister, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*TempRegID*//* 298(*/0xAA, 0x02/*)*/,
63388 /* 194031 */ GIR_AddImm8, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Imm*/1,
63389 /* 194035 */ GIR_ConstrainOperandRC, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63390 /* 194041 */ GIR_ConstrainOperandRC, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63391 /* 194047 */ GIR_ConstrainOperandRC, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63392 /* 194053 */ GIR_MakeTempReg, /*TempRegID*//* 295(*/0xA7, 0x02/*)*/, /*TypeID*/GILLT_s64,
63393 /* 194057 */ GIR_BuildMI, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63394 /* 194062 */ GIR_AddTempRegister, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*TempRegID*//* 295(*/0xA7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63395 /* 194069 */ GIR_AddSimpleTempRegister, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*TempRegID*//* 296(*/0xA8, 0x02/*)*/,
63396 /* 194074 */ GIR_AddImm8, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*Imm*/32,
63397 /* 194078 */ GIR_AddImm8, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*Imm*/31,
63398 /* 194082 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 296(*/0xA8, 0x02/*)*/,
63399 /* 194085 */ GIR_MakeTempReg, /*TempRegID*//* 294(*/0xA6, 0x02/*)*/, /*TypeID*/GILLT_s64,
63400 /* 194089 */ GIR_BuildMI, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63401 /* 194094 */ GIR_AddTempRegister, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, /*TempRegID*//* 294(*/0xA6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63402 /* 194101 */ GIR_AddSimpleTempRegister, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, /*TempRegID*//* 295(*/0xA7, 0x02/*)*/,
63403 /* 194106 */ GIR_AddImm, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63404 /* 194117 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 295(*/0xA7, 0x02/*)*/,
63405 /* 194120 */ GIR_MakeTempReg, /*TempRegID*//* 293(*/0xA5, 0x02/*)*/, /*TypeID*/GILLT_s64,
63406 /* 194124 */ GIR_BuildMI, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63407 /* 194129 */ GIR_AddTempRegister, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, /*TempRegID*//* 293(*/0xA5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63408 /* 194136 */ GIR_AddSimpleTempRegister, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, /*TempRegID*//* 294(*/0xA6, 0x02/*)*/,
63409 /* 194141 */ GIR_AddImm, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690),
63410 /* 194152 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 294(*/0xA6, 0x02/*)*/,
63411 /* 194155 */ GIR_MakeTempReg, /*TempRegID*//* 292(*/0xA4, 0x02/*)*/, /*TypeID*/GILLT_s64,
63412 /* 194159 */ GIR_BuildMI, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63413 /* 194164 */ GIR_AddTempRegister, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, /*TempRegID*//* 292(*/0xA4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63414 /* 194171 */ GIR_Copy, /*NewInsnID*//* 293(*/0xA5, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63415 /* 194176 */ GIR_AddImm8, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, /*Imm*/1,
63416 /* 194180 */ GIR_AddImm8, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, /*Imm*/62,
63417 /* 194184 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 293(*/0xA5, 0x02/*)*/,
63418 /* 194187 */ GIR_MakeTempReg, /*TempRegID*//* 291(*/0xA3, 0x02/*)*/, /*TypeID*/GILLT_s64,
63419 /* 194191 */ GIR_BuildMI, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63420 /* 194196 */ GIR_AddTempRegister, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, /*TempRegID*//* 291(*/0xA3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63421 /* 194203 */ GIR_AddSimpleTempRegister, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, /*TempRegID*//* 292(*/0xA4, 0x02/*)*/,
63422 /* 194208 */ GIR_AddSimpleTempRegister, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, /*TempRegID*//* 293(*/0xA5, 0x02/*)*/,
63423 /* 194213 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 292(*/0xA4, 0x02/*)*/,
63424 /* 194216 */ GIR_MakeTempReg, /*TempRegID*//* 290(*/0xA2, 0x02/*)*/, /*TypeID*/GILLT_s32,
63425 /* 194220 */ GIR_BuildMI, /*InsnID*//* 291(*/0xA3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63426 /* 194225 */ GIR_AddTempRegister, /*InsnID*//* 291(*/0xA3, 0x02/*)*/, /*TempRegID*//* 290(*/0xA2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63427 /* 194232 */ GIR_AddImm, /*InsnID*//* 291(*/0xA3, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63428 /* 194243 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 291(*/0xA3, 0x02/*)*/,
63429 /* 194246 */ GIR_MakeTempReg, /*TempRegID*//* 289(*/0xA1, 0x02/*)*/, /*TypeID*/GILLT_s32,
63430 /* 194250 */ GIR_BuildMI, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63431 /* 194255 */ GIR_AddTempRegister, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, /*TempRegID*//* 289(*/0xA1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63432 /* 194262 */ GIR_AddSimpleTempRegister, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, /*TempRegID*//* 290(*/0xA2, 0x02/*)*/,
63433 /* 194267 */ GIR_AddImm, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63434 /* 194278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 290(*/0xA2, 0x02/*)*/,
63435 /* 194281 */ GIR_MakeTempReg, /*TempRegID*//* 288(*/0xA0, 0x02/*)*/, /*TypeID*/GILLT_s64,
63436 /* 194285 */ GIR_BuildMI, /*InsnID*//* 289(*/0xA1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63437 /* 194290 */ GIR_AddTempRegister, /*InsnID*//* 289(*/0xA1, 0x02/*)*/, /*TempRegID*//* 288(*/0xA0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63438 /* 194297 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 289(*/0xA1, 0x02/*)*/,
63439 /* 194300 */ GIR_MakeTempReg, /*TempRegID*//* 287(*/0x9F, 0x02/*)*/, /*TypeID*/GILLT_s64,
63440 /* 194304 */ GIR_BuildMI, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63441 /* 194309 */ GIR_AddTempRegister, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*TempRegID*//* 287(*/0x9F, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63442 /* 194316 */ GIR_AddSimpleTempRegister, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*TempRegID*//* 288(*/0xA0, 0x02/*)*/,
63443 /* 194321 */ GIR_AddSimpleTempRegister, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*TempRegID*//* 289(*/0xA1, 0x02/*)*/,
63444 /* 194326 */ GIR_AddImm8, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Imm*/1,
63445 /* 194330 */ GIR_ConstrainOperandRC, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63446 /* 194336 */ GIR_ConstrainOperandRC, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63447 /* 194342 */ GIR_ConstrainOperandRC, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63448 /* 194348 */ GIR_MakeTempReg, /*TempRegID*//* 286(*/0x9E, 0x02/*)*/, /*TypeID*/GILLT_s64,
63449 /* 194352 */ GIR_BuildMI, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63450 /* 194357 */ GIR_AddTempRegister, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*TempRegID*//* 286(*/0x9E, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63451 /* 194364 */ GIR_AddSimpleTempRegister, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*TempRegID*//* 287(*/0x9F, 0x02/*)*/,
63452 /* 194369 */ GIR_AddImm8, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*Imm*/32,
63453 /* 194373 */ GIR_AddImm8, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*Imm*/31,
63454 /* 194377 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 287(*/0x9F, 0x02/*)*/,
63455 /* 194380 */ GIR_MakeTempReg, /*TempRegID*//* 285(*/0x9D, 0x02/*)*/, /*TypeID*/GILLT_s64,
63456 /* 194384 */ GIR_BuildMI, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63457 /* 194389 */ GIR_AddTempRegister, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, /*TempRegID*//* 285(*/0x9D, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63458 /* 194396 */ GIR_AddSimpleTempRegister, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, /*TempRegID*//* 286(*/0x9E, 0x02/*)*/,
63459 /* 194401 */ GIR_AddImm, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63460 /* 194412 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 286(*/0x9E, 0x02/*)*/,
63461 /* 194415 */ GIR_MakeTempReg, /*TempRegID*//* 284(*/0x9C, 0x02/*)*/, /*TypeID*/GILLT_s64,
63462 /* 194419 */ GIR_BuildMI, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63463 /* 194424 */ GIR_AddTempRegister, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, /*TempRegID*//* 284(*/0x9C, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63464 /* 194431 */ GIR_AddSimpleTempRegister, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, /*TempRegID*//* 285(*/0x9D, 0x02/*)*/,
63465 /* 194436 */ GIR_AddImm, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845),
63466 /* 194447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 285(*/0x9D, 0x02/*)*/,
63467 /* 194450 */ GIR_MakeTempReg, /*TempRegID*//* 283(*/0x9B, 0x02/*)*/, /*TypeID*/GILLT_s64,
63468 /* 194454 */ GIR_BuildMI, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63469 /* 194459 */ GIR_AddTempRegister, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, /*TempRegID*//* 283(*/0x9B, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63470 /* 194466 */ GIR_Copy, /*NewInsnID*//* 284(*/0x9C, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63471 /* 194471 */ GIR_AddImm8, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, /*Imm*/63,
63472 /* 194475 */ GIR_AddImm8, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, /*Imm*/1,
63473 /* 194479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 284(*/0x9C, 0x02/*)*/,
63474 /* 194482 */ GIR_MakeTempReg, /*TempRegID*//* 282(*/0x9A, 0x02/*)*/, /*TypeID*/GILLT_s64,
63475 /* 194486 */ GIR_BuildMI, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63476 /* 194491 */ GIR_AddTempRegister, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, /*TempRegID*//* 282(*/0x9A, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63477 /* 194498 */ GIR_AddSimpleTempRegister, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, /*TempRegID*//* 283(*/0x9B, 0x02/*)*/,
63478 /* 194503 */ GIR_AddSimpleTempRegister, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, /*TempRegID*//* 284(*/0x9C, 0x02/*)*/,
63479 /* 194508 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 283(*/0x9B, 0x02/*)*/,
63480 /* 194511 */ GIR_MakeTempReg, /*TempRegID*//* 281(*/0x99, 0x02/*)*/, /*TypeID*/GILLT_s64,
63481 /* 194515 */ GIR_BuildMI, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63482 /* 194520 */ GIR_AddTempRegister, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, /*TempRegID*//* 281(*/0x99, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63483 /* 194527 */ GIR_AddSimpleTempRegister, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, /*TempRegID*//* 282(*/0x9A, 0x02/*)*/,
63484 /* 194532 */ GIR_AddSimpleTempRegister, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, /*TempRegID*//* 291(*/0xA3, 0x02/*)*/,
63485 /* 194537 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 282(*/0x9A, 0x02/*)*/,
63486 /* 194540 */ GIR_MakeTempReg, /*TempRegID*//* 280(*/0x98, 0x02/*)*/, /*TypeID*/GILLT_s64,
63487 /* 194544 */ GIR_BuildMI, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63488 /* 194549 */ GIR_AddTempRegister, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*TempRegID*//* 280(*/0x98, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63489 /* 194556 */ GIR_AddSimpleTempRegister, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*TempRegID*//* 281(*/0x99, 0x02/*)*/,
63490 /* 194561 */ GIR_AddImm8, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*Imm*/62,
63491 /* 194565 */ GIR_AddImm8, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*Imm*/2,
63492 /* 194569 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 281(*/0x99, 0x02/*)*/,
63493 /* 194572 */ GIR_MakeTempReg, /*TempRegID*//* 279(*/0x97, 0x02/*)*/, /*TypeID*/GILLT_s64,
63494 /* 194576 */ GIR_BuildMI, /*InsnID*//* 280(*/0x98, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63495 /* 194581 */ GIR_AddTempRegister, /*InsnID*//* 280(*/0x98, 0x02/*)*/, /*TempRegID*//* 279(*/0x97, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63496 /* 194588 */ GIR_AddSimpleTempRegister, /*InsnID*//* 280(*/0x98, 0x02/*)*/, /*TempRegID*//* 280(*/0x98, 0x02/*)*/,
63497 /* 194593 */ GIR_AddSimpleTempRegister, /*InsnID*//* 280(*/0x98, 0x02/*)*/, /*TempRegID*//* 300(*/0xAC, 0x02/*)*/,
63498 /* 194598 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 280(*/0x98, 0x02/*)*/,
63499 /* 194601 */ GIR_MakeTempReg, /*TempRegID*//* 278(*/0x96, 0x02/*)*/, /*TypeID*/GILLT_s64,
63500 /* 194605 */ GIR_BuildMI, /*InsnID*//* 279(*/0x97, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63501 /* 194610 */ GIR_AddTempRegister, /*InsnID*//* 279(*/0x97, 0x02/*)*/, /*TempRegID*//* 278(*/0x96, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63502 /* 194617 */ GIR_AddSimpleTempRegister, /*InsnID*//* 279(*/0x97, 0x02/*)*/, /*TempRegID*//* 279(*/0x97, 0x02/*)*/,
63503 /* 194622 */ GIR_AddSimpleTempRegister, /*InsnID*//* 279(*/0x97, 0x02/*)*/, /*TempRegID*//* 307(*/0xB3, 0x02/*)*/,
63504 /* 194627 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 279(*/0x97, 0x02/*)*/,
63505 /* 194630 */ GIR_MakeTempReg, /*TempRegID*//* 277(*/0x95, 0x02/*)*/, /*TypeID*/GILLT_s64,
63506 /* 194634 */ GIR_BuildMI, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63507 /* 194639 */ GIR_AddTempRegister, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*TempRegID*//* 277(*/0x95, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63508 /* 194646 */ GIR_AddSimpleTempRegister, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*TempRegID*//* 278(*/0x96, 0x02/*)*/,
63509 /* 194651 */ GIR_AddImm8, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*Imm*/60,
63510 /* 194655 */ GIR_AddImm8, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*Imm*/4,
63511 /* 194659 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 278(*/0x96, 0x02/*)*/,
63512 /* 194662 */ GIR_MakeTempReg, /*TempRegID*//* 276(*/0x94, 0x02/*)*/, /*TypeID*/GILLT_s64,
63513 /* 194666 */ GIR_BuildMI, /*InsnID*//* 277(*/0x95, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63514 /* 194671 */ GIR_AddTempRegister, /*InsnID*//* 277(*/0x95, 0x02/*)*/, /*TempRegID*//* 276(*/0x94, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63515 /* 194678 */ GIR_AddSimpleTempRegister, /*InsnID*//* 277(*/0x95, 0x02/*)*/, /*TempRegID*//* 277(*/0x95, 0x02/*)*/,
63516 /* 194683 */ GIR_AddSimpleTempRegister, /*InsnID*//* 277(*/0x95, 0x02/*)*/, /*TempRegID*//* 335(*/0xCF, 0x02/*)*/,
63517 /* 194688 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 277(*/0x95, 0x02/*)*/,
63518 /* 194691 */ GIR_MakeTempReg, /*TempRegID*//* 275(*/0x93, 0x02/*)*/, /*TypeID*/GILLT_s64,
63519 /* 194695 */ GIR_BuildMI, /*InsnID*//* 276(*/0x94, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63520 /* 194700 */ GIR_AddTempRegister, /*InsnID*//* 276(*/0x94, 0x02/*)*/, /*TempRegID*//* 275(*/0x93, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63521 /* 194707 */ GIR_AddSimpleTempRegister, /*InsnID*//* 276(*/0x94, 0x02/*)*/, /*TempRegID*//* 276(*/0x94, 0x02/*)*/,
63522 /* 194712 */ GIR_AddSimpleTempRegister, /*InsnID*//* 276(*/0x94, 0x02/*)*/, /*TempRegID*//* 342(*/0xD6, 0x02/*)*/,
63523 /* 194717 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 276(*/0x94, 0x02/*)*/,
63524 /* 194720 */ GIR_MakeTempReg, /*TempRegID*//* 547(*/0xA3, 0x04/*)*/, /*TypeID*/GILLT_s32,
63525 /* 194724 */ GIR_BuildMI, /*InsnID*//* 548(*/0xA4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63526 /* 194729 */ GIR_AddTempRegister, /*InsnID*//* 548(*/0xA4, 0x04/*)*/, /*TempRegID*//* 547(*/0xA3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63527 /* 194736 */ GIR_AddImm, /*InsnID*//* 548(*/0xA4, 0x04/*)*/, /*Imm*/GIMT_Encode8(61680),
63528 /* 194747 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 548(*/0xA4, 0x04/*)*/,
63529 /* 194750 */ GIR_MakeTempReg, /*TempRegID*//* 546(*/0xA2, 0x04/*)*/, /*TypeID*/GILLT_s32,
63530 /* 194754 */ GIR_BuildMI, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63531 /* 194759 */ GIR_AddTempRegister, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, /*TempRegID*//* 546(*/0xA2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63532 /* 194766 */ GIR_AddSimpleTempRegister, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, /*TempRegID*//* 547(*/0xA3, 0x04/*)*/,
63533 /* 194771 */ GIR_AddImm, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, /*Imm*/GIMT_Encode8(61680),
63534 /* 194782 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 547(*/0xA3, 0x04/*)*/,
63535 /* 194785 */ GIR_MakeTempReg, /*TempRegID*//* 545(*/0xA1, 0x04/*)*/, /*TypeID*/GILLT_s64,
63536 /* 194789 */ GIR_BuildMI, /*InsnID*//* 546(*/0xA2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63537 /* 194794 */ GIR_AddTempRegister, /*InsnID*//* 546(*/0xA2, 0x04/*)*/, /*TempRegID*//* 545(*/0xA1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63538 /* 194801 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 546(*/0xA2, 0x04/*)*/,
63539 /* 194804 */ GIR_MakeTempReg, /*TempRegID*//* 544(*/0xA0, 0x04/*)*/, /*TypeID*/GILLT_s64,
63540 /* 194808 */ GIR_BuildMI, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63541 /* 194813 */ GIR_AddTempRegister, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*TempRegID*//* 544(*/0xA0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63542 /* 194820 */ GIR_AddSimpleTempRegister, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*TempRegID*//* 545(*/0xA1, 0x04/*)*/,
63543 /* 194825 */ GIR_AddSimpleTempRegister, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*TempRegID*//* 546(*/0xA2, 0x04/*)*/,
63544 /* 194830 */ GIR_AddImm8, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Imm*/1,
63545 /* 194834 */ GIR_ConstrainOperandRC, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63546 /* 194840 */ GIR_ConstrainOperandRC, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63547 /* 194846 */ GIR_ConstrainOperandRC, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63548 /* 194852 */ GIR_MakeTempReg, /*TempRegID*//* 543(*/0x9F, 0x04/*)*/, /*TypeID*/GILLT_s64,
63549 /* 194856 */ GIR_BuildMI, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63550 /* 194861 */ GIR_AddTempRegister, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*TempRegID*//* 543(*/0x9F, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63551 /* 194868 */ GIR_AddSimpleTempRegister, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*TempRegID*//* 544(*/0xA0, 0x04/*)*/,
63552 /* 194873 */ GIR_AddImm8, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*Imm*/32,
63553 /* 194877 */ GIR_AddImm8, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*Imm*/31,
63554 /* 194881 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 544(*/0xA0, 0x04/*)*/,
63555 /* 194884 */ GIR_MakeTempReg, /*TempRegID*//* 542(*/0x9E, 0x04/*)*/, /*TypeID*/GILLT_s64,
63556 /* 194888 */ GIR_BuildMI, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63557 /* 194893 */ GIR_AddTempRegister, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, /*TempRegID*//* 542(*/0x9E, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63558 /* 194900 */ GIR_AddSimpleTempRegister, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, /*TempRegID*//* 543(*/0x9F, 0x04/*)*/,
63559 /* 194905 */ GIR_AddImm, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, /*Imm*/GIMT_Encode8(61680),
63560 /* 194916 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 543(*/0x9F, 0x04/*)*/,
63561 /* 194919 */ GIR_MakeTempReg, /*TempRegID*//* 541(*/0x9D, 0x04/*)*/, /*TypeID*/GILLT_s64,
63562 /* 194923 */ GIR_BuildMI, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63563 /* 194928 */ GIR_AddTempRegister, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, /*TempRegID*//* 541(*/0x9D, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63564 /* 194935 */ GIR_AddSimpleTempRegister, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, /*TempRegID*//* 542(*/0x9E, 0x04/*)*/,
63565 /* 194940 */ GIR_AddImm, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, /*Imm*/GIMT_Encode8(61680),
63566 /* 194951 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 542(*/0x9E, 0x04/*)*/,
63567 /* 194954 */ GIR_MakeTempReg, /*TempRegID*//* 540(*/0x9C, 0x04/*)*/, /*TypeID*/GILLT_s32,
63568 /* 194958 */ GIR_BuildMI, /*InsnID*//* 541(*/0x9D, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63569 /* 194963 */ GIR_AddTempRegister, /*InsnID*//* 541(*/0x9D, 0x04/*)*/, /*TempRegID*//* 540(*/0x9C, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63570 /* 194970 */ GIR_AddImm, /*InsnID*//* 541(*/0x9D, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428),
63571 /* 194981 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 541(*/0x9D, 0x04/*)*/,
63572 /* 194984 */ GIR_MakeTempReg, /*TempRegID*//* 539(*/0x9B, 0x04/*)*/, /*TypeID*/GILLT_s32,
63573 /* 194988 */ GIR_BuildMI, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63574 /* 194993 */ GIR_AddTempRegister, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, /*TempRegID*//* 539(*/0x9B, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63575 /* 195000 */ GIR_AddSimpleTempRegister, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, /*TempRegID*//* 540(*/0x9C, 0x04/*)*/,
63576 /* 195005 */ GIR_AddImm, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428),
63577 /* 195016 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 540(*/0x9C, 0x04/*)*/,
63578 /* 195019 */ GIR_MakeTempReg, /*TempRegID*//* 538(*/0x9A, 0x04/*)*/, /*TypeID*/GILLT_s64,
63579 /* 195023 */ GIR_BuildMI, /*InsnID*//* 539(*/0x9B, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63580 /* 195028 */ GIR_AddTempRegister, /*InsnID*//* 539(*/0x9B, 0x04/*)*/, /*TempRegID*//* 538(*/0x9A, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63581 /* 195035 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 539(*/0x9B, 0x04/*)*/,
63582 /* 195038 */ GIR_MakeTempReg, /*TempRegID*//* 537(*/0x99, 0x04/*)*/, /*TypeID*/GILLT_s64,
63583 /* 195042 */ GIR_BuildMI, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63584 /* 195047 */ GIR_AddTempRegister, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*TempRegID*//* 537(*/0x99, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63585 /* 195054 */ GIR_AddSimpleTempRegister, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*TempRegID*//* 538(*/0x9A, 0x04/*)*/,
63586 /* 195059 */ GIR_AddSimpleTempRegister, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*TempRegID*//* 539(*/0x9B, 0x04/*)*/,
63587 /* 195064 */ GIR_AddImm8, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Imm*/1,
63588 /* 195068 */ GIR_ConstrainOperandRC, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63589 /* 195074 */ GIR_ConstrainOperandRC, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63590 /* 195080 */ GIR_ConstrainOperandRC, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63591 /* 195086 */ GIR_MakeTempReg, /*TempRegID*//* 536(*/0x98, 0x04/*)*/, /*TypeID*/GILLT_s64,
63592 /* 195090 */ GIR_BuildMI, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63593 /* 195095 */ GIR_AddTempRegister, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*TempRegID*//* 536(*/0x98, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63594 /* 195102 */ GIR_AddSimpleTempRegister, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*TempRegID*//* 537(*/0x99, 0x04/*)*/,
63595 /* 195107 */ GIR_AddImm8, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*Imm*/32,
63596 /* 195111 */ GIR_AddImm8, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*Imm*/31,
63597 /* 195115 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 537(*/0x99, 0x04/*)*/,
63598 /* 195118 */ GIR_MakeTempReg, /*TempRegID*//* 535(*/0x97, 0x04/*)*/, /*TypeID*/GILLT_s64,
63599 /* 195122 */ GIR_BuildMI, /*InsnID*//* 536(*/0x98, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63600 /* 195127 */ GIR_AddTempRegister, /*InsnID*//* 536(*/0x98, 0x04/*)*/, /*TempRegID*//* 535(*/0x97, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63601 /* 195134 */ GIR_AddSimpleTempRegister, /*InsnID*//* 536(*/0x98, 0x04/*)*/, /*TempRegID*//* 536(*/0x98, 0x04/*)*/,
63602 /* 195139 */ GIR_AddImm, /*InsnID*//* 536(*/0x98, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428),
63603 /* 195150 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 536(*/0x98, 0x04/*)*/,
63604 /* 195153 */ GIR_MakeTempReg, /*TempRegID*//* 534(*/0x96, 0x04/*)*/, /*TypeID*/GILLT_s64,
63605 /* 195157 */ GIR_BuildMI, /*InsnID*//* 535(*/0x97, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63606 /* 195162 */ GIR_AddTempRegister, /*InsnID*//* 535(*/0x97, 0x04/*)*/, /*TempRegID*//* 534(*/0x96, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63607 /* 195169 */ GIR_AddSimpleTempRegister, /*InsnID*//* 535(*/0x97, 0x04/*)*/, /*TempRegID*//* 535(*/0x97, 0x04/*)*/,
63608 /* 195174 */ GIR_AddImm, /*InsnID*//* 535(*/0x97, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428),
63609 /* 195185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 535(*/0x97, 0x04/*)*/,
63610 /* 195188 */ GIR_MakeTempReg, /*TempRegID*//* 533(*/0x95, 0x04/*)*/, /*TypeID*/GILLT_s32,
63611 /* 195192 */ GIR_BuildMI, /*InsnID*//* 534(*/0x96, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63612 /* 195197 */ GIR_AddTempRegister, /*InsnID*//* 534(*/0x96, 0x04/*)*/, /*TempRegID*//* 533(*/0x95, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63613 /* 195204 */ GIR_AddImm, /*InsnID*//* 534(*/0x96, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
63614 /* 195215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 534(*/0x96, 0x04/*)*/,
63615 /* 195218 */ GIR_MakeTempReg, /*TempRegID*//* 532(*/0x94, 0x04/*)*/, /*TypeID*/GILLT_s32,
63616 /* 195222 */ GIR_BuildMI, /*InsnID*//* 533(*/0x95, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63617 /* 195227 */ GIR_AddTempRegister, /*InsnID*//* 533(*/0x95, 0x04/*)*/, /*TempRegID*//* 532(*/0x94, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63618 /* 195234 */ GIR_AddSimpleTempRegister, /*InsnID*//* 533(*/0x95, 0x04/*)*/, /*TempRegID*//* 533(*/0x95, 0x04/*)*/,
63619 /* 195239 */ GIR_AddImm, /*InsnID*//* 533(*/0x95, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
63620 /* 195250 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 533(*/0x95, 0x04/*)*/,
63621 /* 195253 */ GIR_MakeTempReg, /*TempRegID*//* 531(*/0x93, 0x04/*)*/, /*TypeID*/GILLT_s64,
63622 /* 195257 */ GIR_BuildMI, /*InsnID*//* 532(*/0x94, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63623 /* 195262 */ GIR_AddTempRegister, /*InsnID*//* 532(*/0x94, 0x04/*)*/, /*TempRegID*//* 531(*/0x93, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63624 /* 195269 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 532(*/0x94, 0x04/*)*/,
63625 /* 195272 */ GIR_MakeTempReg, /*TempRegID*//* 530(*/0x92, 0x04/*)*/, /*TypeID*/GILLT_s64,
63626 /* 195276 */ GIR_BuildMI, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63627 /* 195281 */ GIR_AddTempRegister, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*TempRegID*//* 530(*/0x92, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63628 /* 195288 */ GIR_AddSimpleTempRegister, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*TempRegID*//* 531(*/0x93, 0x04/*)*/,
63629 /* 195293 */ GIR_AddSimpleTempRegister, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*TempRegID*//* 532(*/0x94, 0x04/*)*/,
63630 /* 195298 */ GIR_AddImm8, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Imm*/1,
63631 /* 195302 */ GIR_ConstrainOperandRC, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63632 /* 195308 */ GIR_ConstrainOperandRC, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63633 /* 195314 */ GIR_ConstrainOperandRC, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63634 /* 195320 */ GIR_MakeTempReg, /*TempRegID*//* 529(*/0x91, 0x04/*)*/, /*TypeID*/GILLT_s64,
63635 /* 195324 */ GIR_BuildMI, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63636 /* 195329 */ GIR_AddTempRegister, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*TempRegID*//* 529(*/0x91, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63637 /* 195336 */ GIR_AddSimpleTempRegister, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*TempRegID*//* 530(*/0x92, 0x04/*)*/,
63638 /* 195341 */ GIR_AddImm8, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*Imm*/32,
63639 /* 195345 */ GIR_AddImm8, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*Imm*/31,
63640 /* 195349 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 530(*/0x92, 0x04/*)*/,
63641 /* 195352 */ GIR_MakeTempReg, /*TempRegID*//* 528(*/0x90, 0x04/*)*/, /*TypeID*/GILLT_s64,
63642 /* 195356 */ GIR_BuildMI, /*InsnID*//* 529(*/0x91, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63643 /* 195361 */ GIR_AddTempRegister, /*InsnID*//* 529(*/0x91, 0x04/*)*/, /*TempRegID*//* 528(*/0x90, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63644 /* 195368 */ GIR_AddSimpleTempRegister, /*InsnID*//* 529(*/0x91, 0x04/*)*/, /*TempRegID*//* 529(*/0x91, 0x04/*)*/,
63645 /* 195373 */ GIR_AddImm, /*InsnID*//* 529(*/0x91, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
63646 /* 195384 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 529(*/0x91, 0x04/*)*/,
63647 /* 195387 */ GIR_MakeTempReg, /*TempRegID*//* 527(*/0x8F, 0x04/*)*/, /*TypeID*/GILLT_s64,
63648 /* 195391 */ GIR_BuildMI, /*InsnID*//* 528(*/0x90, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63649 /* 195396 */ GIR_AddTempRegister, /*InsnID*//* 528(*/0x90, 0x04/*)*/, /*TempRegID*//* 527(*/0x8F, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63650 /* 195403 */ GIR_AddSimpleTempRegister, /*InsnID*//* 528(*/0x90, 0x04/*)*/, /*TempRegID*//* 528(*/0x90, 0x04/*)*/,
63651 /* 195408 */ GIR_AddImm, /*InsnID*//* 528(*/0x90, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
63652 /* 195419 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 528(*/0x90, 0x04/*)*/,
63653 /* 195422 */ GIR_MakeTempReg, /*TempRegID*//* 526(*/0x8E, 0x04/*)*/, /*TypeID*/GILLT_s64,
63654 /* 195426 */ GIR_BuildMI, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63655 /* 195431 */ GIR_AddTempRegister, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, /*TempRegID*//* 526(*/0x8E, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63656 /* 195438 */ GIR_Copy, /*NewInsnID*//* 527(*/0x8F, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63657 /* 195443 */ GIR_AddImm8, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, /*Imm*/1,
63658 /* 195447 */ GIR_AddImm8, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, /*Imm*/62,
63659 /* 195451 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 527(*/0x8F, 0x04/*)*/,
63660 /* 195454 */ GIR_MakeTempReg, /*TempRegID*//* 525(*/0x8D, 0x04/*)*/, /*TypeID*/GILLT_s64,
63661 /* 195458 */ GIR_BuildMI, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63662 /* 195463 */ GIR_AddTempRegister, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, /*TempRegID*//* 525(*/0x8D, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63663 /* 195470 */ GIR_AddSimpleTempRegister, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, /*TempRegID*//* 526(*/0x8E, 0x04/*)*/,
63664 /* 195475 */ GIR_AddSimpleTempRegister, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, /*TempRegID*//* 527(*/0x8F, 0x04/*)*/,
63665 /* 195480 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 526(*/0x8E, 0x04/*)*/,
63666 /* 195483 */ GIR_MakeTempReg, /*TempRegID*//* 524(*/0x8C, 0x04/*)*/, /*TypeID*/GILLT_s32,
63667 /* 195487 */ GIR_BuildMI, /*InsnID*//* 525(*/0x8D, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63668 /* 195492 */ GIR_AddTempRegister, /*InsnID*//* 525(*/0x8D, 0x04/*)*/, /*TempRegID*//* 524(*/0x8C, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63669 /* 195499 */ GIR_AddImm, /*InsnID*//* 525(*/0x8D, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
63670 /* 195510 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 525(*/0x8D, 0x04/*)*/,
63671 /* 195513 */ GIR_MakeTempReg, /*TempRegID*//* 523(*/0x8B, 0x04/*)*/, /*TypeID*/GILLT_s32,
63672 /* 195517 */ GIR_BuildMI, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63673 /* 195522 */ GIR_AddTempRegister, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, /*TempRegID*//* 523(*/0x8B, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63674 /* 195529 */ GIR_AddSimpleTempRegister, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, /*TempRegID*//* 524(*/0x8C, 0x04/*)*/,
63675 /* 195534 */ GIR_AddImm, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
63676 /* 195545 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 524(*/0x8C, 0x04/*)*/,
63677 /* 195548 */ GIR_MakeTempReg, /*TempRegID*//* 522(*/0x8A, 0x04/*)*/, /*TypeID*/GILLT_s64,
63678 /* 195552 */ GIR_BuildMI, /*InsnID*//* 523(*/0x8B, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63679 /* 195557 */ GIR_AddTempRegister, /*InsnID*//* 523(*/0x8B, 0x04/*)*/, /*TempRegID*//* 522(*/0x8A, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63680 /* 195564 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 523(*/0x8B, 0x04/*)*/,
63681 /* 195567 */ GIR_MakeTempReg, /*TempRegID*//* 521(*/0x89, 0x04/*)*/, /*TypeID*/GILLT_s64,
63682 /* 195571 */ GIR_BuildMI, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63683 /* 195576 */ GIR_AddTempRegister, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*TempRegID*//* 521(*/0x89, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63684 /* 195583 */ GIR_AddSimpleTempRegister, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*TempRegID*//* 522(*/0x8A, 0x04/*)*/,
63685 /* 195588 */ GIR_AddSimpleTempRegister, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*TempRegID*//* 523(*/0x8B, 0x04/*)*/,
63686 /* 195593 */ GIR_AddImm8, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Imm*/1,
63687 /* 195597 */ GIR_ConstrainOperandRC, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63688 /* 195603 */ GIR_ConstrainOperandRC, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63689 /* 195609 */ GIR_ConstrainOperandRC, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63690 /* 195615 */ GIR_MakeTempReg, /*TempRegID*//* 520(*/0x88, 0x04/*)*/, /*TypeID*/GILLT_s64,
63691 /* 195619 */ GIR_BuildMI, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63692 /* 195624 */ GIR_AddTempRegister, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*TempRegID*//* 520(*/0x88, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63693 /* 195631 */ GIR_AddSimpleTempRegister, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*TempRegID*//* 521(*/0x89, 0x04/*)*/,
63694 /* 195636 */ GIR_AddImm8, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*Imm*/32,
63695 /* 195640 */ GIR_AddImm8, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*Imm*/31,
63696 /* 195644 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 521(*/0x89, 0x04/*)*/,
63697 /* 195647 */ GIR_MakeTempReg, /*TempRegID*//* 519(*/0x87, 0x04/*)*/, /*TypeID*/GILLT_s64,
63698 /* 195651 */ GIR_BuildMI, /*InsnID*//* 520(*/0x88, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63699 /* 195656 */ GIR_AddTempRegister, /*InsnID*//* 520(*/0x88, 0x04/*)*/, /*TempRegID*//* 519(*/0x87, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63700 /* 195663 */ GIR_AddSimpleTempRegister, /*InsnID*//* 520(*/0x88, 0x04/*)*/, /*TempRegID*//* 520(*/0x88, 0x04/*)*/,
63701 /* 195668 */ GIR_AddImm, /*InsnID*//* 520(*/0x88, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
63702 /* 195679 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 520(*/0x88, 0x04/*)*/,
63703 /* 195682 */ GIR_MakeTempReg, /*TempRegID*//* 518(*/0x86, 0x04/*)*/, /*TypeID*/GILLT_s64,
63704 /* 195686 */ GIR_BuildMI, /*InsnID*//* 519(*/0x87, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63705 /* 195691 */ GIR_AddTempRegister, /*InsnID*//* 519(*/0x87, 0x04/*)*/, /*TempRegID*//* 518(*/0x86, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63706 /* 195698 */ GIR_AddSimpleTempRegister, /*InsnID*//* 519(*/0x87, 0x04/*)*/, /*TempRegID*//* 519(*/0x87, 0x04/*)*/,
63707 /* 195703 */ GIR_AddImm, /*InsnID*//* 519(*/0x87, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
63708 /* 195714 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 519(*/0x87, 0x04/*)*/,
63709 /* 195717 */ GIR_MakeTempReg, /*TempRegID*//* 517(*/0x85, 0x04/*)*/, /*TypeID*/GILLT_s64,
63710 /* 195721 */ GIR_BuildMI, /*InsnID*//* 518(*/0x86, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63711 /* 195726 */ GIR_AddTempRegister, /*InsnID*//* 518(*/0x86, 0x04/*)*/, /*TempRegID*//* 517(*/0x85, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63712 /* 195733 */ GIR_Copy, /*NewInsnID*//* 518(*/0x86, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63713 /* 195738 */ GIR_AddImm8, /*InsnID*//* 518(*/0x86, 0x04/*)*/, /*Imm*/63,
63714 /* 195742 */ GIR_AddImm8, /*InsnID*//* 518(*/0x86, 0x04/*)*/, /*Imm*/1,
63715 /* 195746 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 518(*/0x86, 0x04/*)*/,
63716 /* 195749 */ GIR_MakeTempReg, /*TempRegID*//* 516(*/0x84, 0x04/*)*/, /*TypeID*/GILLT_s64,
63717 /* 195753 */ GIR_BuildMI, /*InsnID*//* 517(*/0x85, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63718 /* 195758 */ GIR_AddTempRegister, /*InsnID*//* 517(*/0x85, 0x04/*)*/, /*TempRegID*//* 516(*/0x84, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63719 /* 195765 */ GIR_AddSimpleTempRegister, /*InsnID*//* 517(*/0x85, 0x04/*)*/, /*TempRegID*//* 517(*/0x85, 0x04/*)*/,
63720 /* 195770 */ GIR_AddSimpleTempRegister, /*InsnID*//* 517(*/0x85, 0x04/*)*/, /*TempRegID*//* 518(*/0x86, 0x04/*)*/,
63721 /* 195775 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 517(*/0x85, 0x04/*)*/,
63722 /* 195778 */ GIR_MakeTempReg, /*TempRegID*//* 515(*/0x83, 0x04/*)*/, /*TypeID*/GILLT_s64,
63723 /* 195782 */ GIR_BuildMI, /*InsnID*//* 516(*/0x84, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63724 /* 195787 */ GIR_AddTempRegister, /*InsnID*//* 516(*/0x84, 0x04/*)*/, /*TempRegID*//* 515(*/0x83, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63725 /* 195794 */ GIR_AddSimpleTempRegister, /*InsnID*//* 516(*/0x84, 0x04/*)*/, /*TempRegID*//* 516(*/0x84, 0x04/*)*/,
63726 /* 195799 */ GIR_AddSimpleTempRegister, /*InsnID*//* 516(*/0x84, 0x04/*)*/, /*TempRegID*//* 525(*/0x8D, 0x04/*)*/,
63727 /* 195804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 516(*/0x84, 0x04/*)*/,
63728 /* 195807 */ GIR_MakeTempReg, /*TempRegID*//* 514(*/0x82, 0x04/*)*/, /*TypeID*/GILLT_s64,
63729 /* 195811 */ GIR_BuildMI, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63730 /* 195816 */ GIR_AddTempRegister, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*TempRegID*//* 514(*/0x82, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63731 /* 195823 */ GIR_AddSimpleTempRegister, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*TempRegID*//* 515(*/0x83, 0x04/*)*/,
63732 /* 195828 */ GIR_AddImm8, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*Imm*/2,
63733 /* 195832 */ GIR_AddImm8, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*Imm*/61,
63734 /* 195836 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 515(*/0x83, 0x04/*)*/,
63735 /* 195839 */ GIR_MakeTempReg, /*TempRegID*//* 513(*/0x81, 0x04/*)*/, /*TypeID*/GILLT_s64,
63736 /* 195843 */ GIR_BuildMI, /*InsnID*//* 514(*/0x82, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63737 /* 195848 */ GIR_AddTempRegister, /*InsnID*//* 514(*/0x82, 0x04/*)*/, /*TempRegID*//* 513(*/0x81, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63738 /* 195855 */ GIR_AddSimpleTempRegister, /*InsnID*//* 514(*/0x82, 0x04/*)*/, /*TempRegID*//* 514(*/0x82, 0x04/*)*/,
63739 /* 195860 */ GIR_AddSimpleTempRegister, /*InsnID*//* 514(*/0x82, 0x04/*)*/, /*TempRegID*//* 534(*/0x96, 0x04/*)*/,
63740 /* 195865 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 514(*/0x82, 0x04/*)*/,
63741 /* 195868 */ GIR_MakeTempReg, /*TempRegID*//* 512(*/0x80, 0x04/*)*/, /*TypeID*/GILLT_s32,
63742 /* 195872 */ GIR_BuildMI, /*InsnID*//* 513(*/0x81, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63743 /* 195877 */ GIR_AddTempRegister, /*InsnID*//* 513(*/0x81, 0x04/*)*/, /*TempRegID*//* 512(*/0x80, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63744 /* 195884 */ GIR_AddImm, /*InsnID*//* 513(*/0x81, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107),
63745 /* 195895 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 513(*/0x81, 0x04/*)*/,
63746 /* 195898 */ GIR_MakeTempReg, /*TempRegID*//* 511(*/0xFF, 0x03/*)*/, /*TypeID*/GILLT_s32,
63747 /* 195902 */ GIR_BuildMI, /*InsnID*//* 512(*/0x80, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63748 /* 195907 */ GIR_AddTempRegister, /*InsnID*//* 512(*/0x80, 0x04/*)*/, /*TempRegID*//* 511(*/0xFF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63749 /* 195914 */ GIR_AddSimpleTempRegister, /*InsnID*//* 512(*/0x80, 0x04/*)*/, /*TempRegID*//* 512(*/0x80, 0x04/*)*/,
63750 /* 195919 */ GIR_AddImm, /*InsnID*//* 512(*/0x80, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107),
63751 /* 195930 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 512(*/0x80, 0x04/*)*/,
63752 /* 195933 */ GIR_MakeTempReg, /*TempRegID*//* 510(*/0xFE, 0x03/*)*/, /*TypeID*/GILLT_s64,
63753 /* 195937 */ GIR_BuildMI, /*InsnID*//* 511(*/0xFF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63754 /* 195942 */ GIR_AddTempRegister, /*InsnID*//* 511(*/0xFF, 0x03/*)*/, /*TempRegID*//* 510(*/0xFE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63755 /* 195949 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 511(*/0xFF, 0x03/*)*/,
63756 /* 195952 */ GIR_MakeTempReg, /*TempRegID*//* 509(*/0xFD, 0x03/*)*/, /*TypeID*/GILLT_s64,
63757 /* 195956 */ GIR_BuildMI, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63758 /* 195961 */ GIR_AddTempRegister, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*TempRegID*//* 509(*/0xFD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63759 /* 195968 */ GIR_AddSimpleTempRegister, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*TempRegID*//* 510(*/0xFE, 0x03/*)*/,
63760 /* 195973 */ GIR_AddSimpleTempRegister, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*TempRegID*//* 511(*/0xFF, 0x03/*)*/,
63761 /* 195978 */ GIR_AddImm8, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Imm*/1,
63762 /* 195982 */ GIR_ConstrainOperandRC, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63763 /* 195988 */ GIR_ConstrainOperandRC, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63764 /* 195994 */ GIR_ConstrainOperandRC, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63765 /* 196000 */ GIR_MakeTempReg, /*TempRegID*//* 508(*/0xFC, 0x03/*)*/, /*TypeID*/GILLT_s64,
63766 /* 196004 */ GIR_BuildMI, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63767 /* 196009 */ GIR_AddTempRegister, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*TempRegID*//* 508(*/0xFC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63768 /* 196016 */ GIR_AddSimpleTempRegister, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*TempRegID*//* 509(*/0xFD, 0x03/*)*/,
63769 /* 196021 */ GIR_AddImm8, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*Imm*/32,
63770 /* 196025 */ GIR_AddImm8, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*Imm*/31,
63771 /* 196029 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 509(*/0xFD, 0x03/*)*/,
63772 /* 196032 */ GIR_MakeTempReg, /*TempRegID*//* 507(*/0xFB, 0x03/*)*/, /*TypeID*/GILLT_s64,
63773 /* 196036 */ GIR_BuildMI, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63774 /* 196041 */ GIR_AddTempRegister, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, /*TempRegID*//* 507(*/0xFB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63775 /* 196048 */ GIR_AddSimpleTempRegister, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, /*TempRegID*//* 508(*/0xFC, 0x03/*)*/,
63776 /* 196053 */ GIR_AddImm, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107),
63777 /* 196064 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 508(*/0xFC, 0x03/*)*/,
63778 /* 196067 */ GIR_MakeTempReg, /*TempRegID*//* 506(*/0xFA, 0x03/*)*/, /*TypeID*/GILLT_s64,
63779 /* 196071 */ GIR_BuildMI, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63780 /* 196076 */ GIR_AddTempRegister, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, /*TempRegID*//* 506(*/0xFA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63781 /* 196083 */ GIR_AddSimpleTempRegister, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, /*TempRegID*//* 507(*/0xFB, 0x03/*)*/,
63782 /* 196088 */ GIR_AddImm, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107),
63783 /* 196099 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 507(*/0xFB, 0x03/*)*/,
63784 /* 196102 */ GIR_MakeTempReg, /*TempRegID*//* 505(*/0xF9, 0x03/*)*/, /*TypeID*/GILLT_s32,
63785 /* 196106 */ GIR_BuildMI, /*InsnID*//* 506(*/0xFA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63786 /* 196111 */ GIR_AddTempRegister, /*InsnID*//* 506(*/0xFA, 0x03/*)*/, /*TempRegID*//* 505(*/0xF9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63787 /* 196118 */ GIR_AddImm, /*InsnID*//* 506(*/0xFA, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
63788 /* 196129 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 506(*/0xFA, 0x03/*)*/,
63789 /* 196132 */ GIR_MakeTempReg, /*TempRegID*//* 504(*/0xF8, 0x03/*)*/, /*TypeID*/GILLT_s32,
63790 /* 196136 */ GIR_BuildMI, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63791 /* 196141 */ GIR_AddTempRegister, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, /*TempRegID*//* 504(*/0xF8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63792 /* 196148 */ GIR_AddSimpleTempRegister, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, /*TempRegID*//* 505(*/0xF9, 0x03/*)*/,
63793 /* 196153 */ GIR_AddImm, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
63794 /* 196164 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 505(*/0xF9, 0x03/*)*/,
63795 /* 196167 */ GIR_MakeTempReg, /*TempRegID*//* 503(*/0xF7, 0x03/*)*/, /*TypeID*/GILLT_s64,
63796 /* 196171 */ GIR_BuildMI, /*InsnID*//* 504(*/0xF8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63797 /* 196176 */ GIR_AddTempRegister, /*InsnID*//* 504(*/0xF8, 0x03/*)*/, /*TempRegID*//* 503(*/0xF7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63798 /* 196183 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 504(*/0xF8, 0x03/*)*/,
63799 /* 196186 */ GIR_MakeTempReg, /*TempRegID*//* 502(*/0xF6, 0x03/*)*/, /*TypeID*/GILLT_s64,
63800 /* 196190 */ GIR_BuildMI, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63801 /* 196195 */ GIR_AddTempRegister, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*TempRegID*//* 502(*/0xF6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63802 /* 196202 */ GIR_AddSimpleTempRegister, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*TempRegID*//* 503(*/0xF7, 0x03/*)*/,
63803 /* 196207 */ GIR_AddSimpleTempRegister, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*TempRegID*//* 504(*/0xF8, 0x03/*)*/,
63804 /* 196212 */ GIR_AddImm8, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Imm*/1,
63805 /* 196216 */ GIR_ConstrainOperandRC, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63806 /* 196222 */ GIR_ConstrainOperandRC, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63807 /* 196228 */ GIR_ConstrainOperandRC, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63808 /* 196234 */ GIR_MakeTempReg, /*TempRegID*//* 501(*/0xF5, 0x03/*)*/, /*TypeID*/GILLT_s64,
63809 /* 196238 */ GIR_BuildMI, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63810 /* 196243 */ GIR_AddTempRegister, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*TempRegID*//* 501(*/0xF5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63811 /* 196250 */ GIR_AddSimpleTempRegister, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*TempRegID*//* 502(*/0xF6, 0x03/*)*/,
63812 /* 196255 */ GIR_AddImm8, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*Imm*/32,
63813 /* 196259 */ GIR_AddImm8, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*Imm*/31,
63814 /* 196263 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 502(*/0xF6, 0x03/*)*/,
63815 /* 196266 */ GIR_MakeTempReg, /*TempRegID*//* 500(*/0xF4, 0x03/*)*/, /*TypeID*/GILLT_s64,
63816 /* 196270 */ GIR_BuildMI, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63817 /* 196275 */ GIR_AddTempRegister, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, /*TempRegID*//* 500(*/0xF4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63818 /* 196282 */ GIR_AddSimpleTempRegister, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, /*TempRegID*//* 501(*/0xF5, 0x03/*)*/,
63819 /* 196287 */ GIR_AddImm, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
63820 /* 196298 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 501(*/0xF5, 0x03/*)*/,
63821 /* 196301 */ GIR_MakeTempReg, /*TempRegID*//* 499(*/0xF3, 0x03/*)*/, /*TypeID*/GILLT_s64,
63822 /* 196305 */ GIR_BuildMI, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63823 /* 196310 */ GIR_AddTempRegister, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, /*TempRegID*//* 499(*/0xF3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63824 /* 196317 */ GIR_AddSimpleTempRegister, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, /*TempRegID*//* 500(*/0xF4, 0x03/*)*/,
63825 /* 196322 */ GIR_AddImm, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
63826 /* 196333 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 500(*/0xF4, 0x03/*)*/,
63827 /* 196336 */ GIR_MakeTempReg, /*TempRegID*//* 498(*/0xF2, 0x03/*)*/, /*TypeID*/GILLT_s64,
63828 /* 196340 */ GIR_BuildMI, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63829 /* 196345 */ GIR_AddTempRegister, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, /*TempRegID*//* 498(*/0xF2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63830 /* 196352 */ GIR_Copy, /*NewInsnID*//* 499(*/0xF3, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63831 /* 196357 */ GIR_AddImm8, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, /*Imm*/1,
63832 /* 196361 */ GIR_AddImm8, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, /*Imm*/62,
63833 /* 196365 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 499(*/0xF3, 0x03/*)*/,
63834 /* 196368 */ GIR_MakeTempReg, /*TempRegID*//* 497(*/0xF1, 0x03/*)*/, /*TypeID*/GILLT_s64,
63835 /* 196372 */ GIR_BuildMI, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63836 /* 196377 */ GIR_AddTempRegister, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, /*TempRegID*//* 497(*/0xF1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63837 /* 196384 */ GIR_AddSimpleTempRegister, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, /*TempRegID*//* 498(*/0xF2, 0x03/*)*/,
63838 /* 196389 */ GIR_AddSimpleTempRegister, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, /*TempRegID*//* 499(*/0xF3, 0x03/*)*/,
63839 /* 196394 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 498(*/0xF2, 0x03/*)*/,
63840 /* 196397 */ GIR_MakeTempReg, /*TempRegID*//* 496(*/0xF0, 0x03/*)*/, /*TypeID*/GILLT_s32,
63841 /* 196401 */ GIR_BuildMI, /*InsnID*//* 497(*/0xF1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63842 /* 196406 */ GIR_AddTempRegister, /*InsnID*//* 497(*/0xF1, 0x03/*)*/, /*TempRegID*//* 496(*/0xF0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63843 /* 196413 */ GIR_AddImm, /*InsnID*//* 497(*/0xF1, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
63844 /* 196424 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 497(*/0xF1, 0x03/*)*/,
63845 /* 196427 */ GIR_MakeTempReg, /*TempRegID*//* 495(*/0xEF, 0x03/*)*/, /*TypeID*/GILLT_s32,
63846 /* 196431 */ GIR_BuildMI, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63847 /* 196436 */ GIR_AddTempRegister, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, /*TempRegID*//* 495(*/0xEF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63848 /* 196443 */ GIR_AddSimpleTempRegister, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, /*TempRegID*//* 496(*/0xF0, 0x03/*)*/,
63849 /* 196448 */ GIR_AddImm, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
63850 /* 196459 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 496(*/0xF0, 0x03/*)*/,
63851 /* 196462 */ GIR_MakeTempReg, /*TempRegID*//* 494(*/0xEE, 0x03/*)*/, /*TypeID*/GILLT_s64,
63852 /* 196466 */ GIR_BuildMI, /*InsnID*//* 495(*/0xEF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63853 /* 196471 */ GIR_AddTempRegister, /*InsnID*//* 495(*/0xEF, 0x03/*)*/, /*TempRegID*//* 494(*/0xEE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63854 /* 196478 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 495(*/0xEF, 0x03/*)*/,
63855 /* 196481 */ GIR_MakeTempReg, /*TempRegID*//* 493(*/0xED, 0x03/*)*/, /*TypeID*/GILLT_s64,
63856 /* 196485 */ GIR_BuildMI, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63857 /* 196490 */ GIR_AddTempRegister, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*TempRegID*//* 493(*/0xED, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63858 /* 196497 */ GIR_AddSimpleTempRegister, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*TempRegID*//* 494(*/0xEE, 0x03/*)*/,
63859 /* 196502 */ GIR_AddSimpleTempRegister, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*TempRegID*//* 495(*/0xEF, 0x03/*)*/,
63860 /* 196507 */ GIR_AddImm8, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Imm*/1,
63861 /* 196511 */ GIR_ConstrainOperandRC, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63862 /* 196517 */ GIR_ConstrainOperandRC, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63863 /* 196523 */ GIR_ConstrainOperandRC, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63864 /* 196529 */ GIR_MakeTempReg, /*TempRegID*//* 492(*/0xEC, 0x03/*)*/, /*TypeID*/GILLT_s64,
63865 /* 196533 */ GIR_BuildMI, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63866 /* 196538 */ GIR_AddTempRegister, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*TempRegID*//* 492(*/0xEC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63867 /* 196545 */ GIR_AddSimpleTempRegister, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*TempRegID*//* 493(*/0xED, 0x03/*)*/,
63868 /* 196550 */ GIR_AddImm8, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*Imm*/32,
63869 /* 196554 */ GIR_AddImm8, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*Imm*/31,
63870 /* 196558 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 493(*/0xED, 0x03/*)*/,
63871 /* 196561 */ GIR_MakeTempReg, /*TempRegID*//* 491(*/0xEB, 0x03/*)*/, /*TypeID*/GILLT_s64,
63872 /* 196565 */ GIR_BuildMI, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63873 /* 196570 */ GIR_AddTempRegister, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, /*TempRegID*//* 491(*/0xEB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63874 /* 196577 */ GIR_AddSimpleTempRegister, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, /*TempRegID*//* 492(*/0xEC, 0x03/*)*/,
63875 /* 196582 */ GIR_AddImm, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
63876 /* 196593 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 492(*/0xEC, 0x03/*)*/,
63877 /* 196596 */ GIR_MakeTempReg, /*TempRegID*//* 490(*/0xEA, 0x03/*)*/, /*TypeID*/GILLT_s64,
63878 /* 196600 */ GIR_BuildMI, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63879 /* 196605 */ GIR_AddTempRegister, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, /*TempRegID*//* 490(*/0xEA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63880 /* 196612 */ GIR_AddSimpleTempRegister, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, /*TempRegID*//* 491(*/0xEB, 0x03/*)*/,
63881 /* 196617 */ GIR_AddImm, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
63882 /* 196628 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 491(*/0xEB, 0x03/*)*/,
63883 /* 196631 */ GIR_MakeTempReg, /*TempRegID*//* 489(*/0xE9, 0x03/*)*/, /*TypeID*/GILLT_s64,
63884 /* 196635 */ GIR_BuildMI, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63885 /* 196640 */ GIR_AddTempRegister, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, /*TempRegID*//* 489(*/0xE9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63886 /* 196647 */ GIR_Copy, /*NewInsnID*//* 490(*/0xEA, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
63887 /* 196652 */ GIR_AddImm8, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, /*Imm*/63,
63888 /* 196656 */ GIR_AddImm8, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, /*Imm*/1,
63889 /* 196660 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 490(*/0xEA, 0x03/*)*/,
63890 /* 196663 */ GIR_MakeTempReg, /*TempRegID*//* 488(*/0xE8, 0x03/*)*/, /*TypeID*/GILLT_s64,
63891 /* 196667 */ GIR_BuildMI, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63892 /* 196672 */ GIR_AddTempRegister, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, /*TempRegID*//* 488(*/0xE8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63893 /* 196679 */ GIR_AddSimpleTempRegister, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, /*TempRegID*//* 489(*/0xE9, 0x03/*)*/,
63894 /* 196684 */ GIR_AddSimpleTempRegister, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, /*TempRegID*//* 490(*/0xEA, 0x03/*)*/,
63895 /* 196689 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 489(*/0xE9, 0x03/*)*/,
63896 /* 196692 */ GIR_MakeTempReg, /*TempRegID*//* 487(*/0xE7, 0x03/*)*/, /*TypeID*/GILLT_s64,
63897 /* 196696 */ GIR_BuildMI, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63898 /* 196701 */ GIR_AddTempRegister, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, /*TempRegID*//* 487(*/0xE7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63899 /* 196708 */ GIR_AddSimpleTempRegister, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, /*TempRegID*//* 488(*/0xE8, 0x03/*)*/,
63900 /* 196713 */ GIR_AddSimpleTempRegister, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, /*TempRegID*//* 497(*/0xF1, 0x03/*)*/,
63901 /* 196718 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 488(*/0xE8, 0x03/*)*/,
63902 /* 196721 */ GIR_MakeTempReg, /*TempRegID*//* 486(*/0xE6, 0x03/*)*/, /*TypeID*/GILLT_s64,
63903 /* 196725 */ GIR_BuildMI, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
63904 /* 196730 */ GIR_AddTempRegister, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*TempRegID*//* 486(*/0xE6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63905 /* 196737 */ GIR_AddSimpleTempRegister, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*TempRegID*//* 487(*/0xE7, 0x03/*)*/,
63906 /* 196742 */ GIR_AddImm8, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*Imm*/62,
63907 /* 196746 */ GIR_AddImm8, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*Imm*/2,
63908 /* 196750 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 487(*/0xE7, 0x03/*)*/,
63909 /* 196753 */ GIR_MakeTempReg, /*TempRegID*//* 485(*/0xE5, 0x03/*)*/, /*TypeID*/GILLT_s64,
63910 /* 196757 */ GIR_BuildMI, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63911 /* 196762 */ GIR_AddTempRegister, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, /*TempRegID*//* 485(*/0xE5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63912 /* 196769 */ GIR_AddSimpleTempRegister, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, /*TempRegID*//* 486(*/0xE6, 0x03/*)*/,
63913 /* 196774 */ GIR_AddSimpleTempRegister, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, /*TempRegID*//* 506(*/0xFA, 0x03/*)*/,
63914 /* 196779 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 486(*/0xE6, 0x03/*)*/,
63915 /* 196782 */ GIR_MakeTempReg, /*TempRegID*//* 484(*/0xE4, 0x03/*)*/, /*TypeID*/GILLT_s64,
63916 /* 196786 */ GIR_BuildMI, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
63917 /* 196791 */ GIR_AddTempRegister, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, /*TempRegID*//* 484(*/0xE4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63918 /* 196798 */ GIR_AddSimpleTempRegister, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, /*TempRegID*//* 485(*/0xE5, 0x03/*)*/,
63919 /* 196803 */ GIR_AddSimpleTempRegister, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, /*TempRegID*//* 513(*/0x81, 0x04/*)*/,
63920 /* 196808 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 485(*/0xE5, 0x03/*)*/,
63921 /* 196811 */ GIR_MakeTempReg, /*TempRegID*//* 483(*/0xE3, 0x03/*)*/, /*TypeID*/GILLT_s64,
63922 /* 196815 */ GIR_BuildMI, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63923 /* 196820 */ GIR_AddTempRegister, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*TempRegID*//* 483(*/0xE3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63924 /* 196827 */ GIR_AddSimpleTempRegister, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*TempRegID*//* 484(*/0xE4, 0x03/*)*/,
63925 /* 196832 */ GIR_AddImm8, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*Imm*/4,
63926 /* 196836 */ GIR_AddImm8, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*Imm*/59,
63927 /* 196840 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 484(*/0xE4, 0x03/*)*/,
63928 /* 196843 */ GIR_MakeTempReg, /*TempRegID*//* 482(*/0xE2, 0x03/*)*/, /*TypeID*/GILLT_s64,
63929 /* 196847 */ GIR_BuildMI, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
63930 /* 196852 */ GIR_AddTempRegister, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, /*TempRegID*//* 482(*/0xE2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63931 /* 196859 */ GIR_AddSimpleTempRegister, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, /*TempRegID*//* 483(*/0xE3, 0x03/*)*/,
63932 /* 196864 */ GIR_AddSimpleTempRegister, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, /*TempRegID*//* 541(*/0x9D, 0x04/*)*/,
63933 /* 196869 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 483(*/0xE3, 0x03/*)*/,
63934 /* 196872 */ GIR_MakeTempReg, /*TempRegID*//* 481(*/0xE1, 0x03/*)*/, /*TypeID*/GILLT_s32,
63935 /* 196876 */ GIR_BuildMI, /*InsnID*//* 482(*/0xE2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63936 /* 196881 */ GIR_AddTempRegister, /*InsnID*//* 482(*/0xE2, 0x03/*)*/, /*TempRegID*//* 481(*/0xE1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63937 /* 196888 */ GIR_AddImm, /*InsnID*//* 482(*/0xE2, 0x03/*)*/, /*Imm*/GIMT_Encode8(3855),
63938 /* 196899 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 482(*/0xE2, 0x03/*)*/,
63939 /* 196902 */ GIR_MakeTempReg, /*TempRegID*//* 480(*/0xE0, 0x03/*)*/, /*TypeID*/GILLT_s32,
63940 /* 196906 */ GIR_BuildMI, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63941 /* 196911 */ GIR_AddTempRegister, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, /*TempRegID*//* 480(*/0xE0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63942 /* 196918 */ GIR_AddSimpleTempRegister, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, /*TempRegID*//* 481(*/0xE1, 0x03/*)*/,
63943 /* 196923 */ GIR_AddImm, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, /*Imm*/GIMT_Encode8(3855),
63944 /* 196934 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 481(*/0xE1, 0x03/*)*/,
63945 /* 196937 */ GIR_MakeTempReg, /*TempRegID*//* 479(*/0xDF, 0x03/*)*/, /*TypeID*/GILLT_s64,
63946 /* 196941 */ GIR_BuildMI, /*InsnID*//* 480(*/0xE0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63947 /* 196946 */ GIR_AddTempRegister, /*InsnID*//* 480(*/0xE0, 0x03/*)*/, /*TempRegID*//* 479(*/0xDF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63948 /* 196953 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 480(*/0xE0, 0x03/*)*/,
63949 /* 196956 */ GIR_MakeTempReg, /*TempRegID*//* 478(*/0xDE, 0x03/*)*/, /*TypeID*/GILLT_s64,
63950 /* 196960 */ GIR_BuildMI, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63951 /* 196965 */ GIR_AddTempRegister, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*TempRegID*//* 478(*/0xDE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63952 /* 196972 */ GIR_AddSimpleTempRegister, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*TempRegID*//* 479(*/0xDF, 0x03/*)*/,
63953 /* 196977 */ GIR_AddSimpleTempRegister, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*TempRegID*//* 480(*/0xE0, 0x03/*)*/,
63954 /* 196982 */ GIR_AddImm8, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Imm*/1,
63955 /* 196986 */ GIR_ConstrainOperandRC, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63956 /* 196992 */ GIR_ConstrainOperandRC, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
63957 /* 196998 */ GIR_ConstrainOperandRC, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
63958 /* 197004 */ GIR_MakeTempReg, /*TempRegID*//* 477(*/0xDD, 0x03/*)*/, /*TypeID*/GILLT_s64,
63959 /* 197008 */ GIR_BuildMI, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
63960 /* 197013 */ GIR_AddTempRegister, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*TempRegID*//* 477(*/0xDD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63961 /* 197020 */ GIR_AddSimpleTempRegister, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*TempRegID*//* 478(*/0xDE, 0x03/*)*/,
63962 /* 197025 */ GIR_AddImm8, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*Imm*/32,
63963 /* 197029 */ GIR_AddImm8, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*Imm*/31,
63964 /* 197033 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 478(*/0xDE, 0x03/*)*/,
63965 /* 197036 */ GIR_MakeTempReg, /*TempRegID*//* 476(*/0xDC, 0x03/*)*/, /*TypeID*/GILLT_s64,
63966 /* 197040 */ GIR_BuildMI, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
63967 /* 197045 */ GIR_AddTempRegister, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, /*TempRegID*//* 476(*/0xDC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63968 /* 197052 */ GIR_AddSimpleTempRegister, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, /*TempRegID*//* 477(*/0xDD, 0x03/*)*/,
63969 /* 197057 */ GIR_AddImm, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, /*Imm*/GIMT_Encode8(3855),
63970 /* 197068 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 477(*/0xDD, 0x03/*)*/,
63971 /* 197071 */ GIR_MakeTempReg, /*TempRegID*//* 475(*/0xDB, 0x03/*)*/, /*TypeID*/GILLT_s64,
63972 /* 197075 */ GIR_BuildMI, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
63973 /* 197080 */ GIR_AddTempRegister, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, /*TempRegID*//* 475(*/0xDB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63974 /* 197087 */ GIR_AddSimpleTempRegister, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, /*TempRegID*//* 476(*/0xDC, 0x03/*)*/,
63975 /* 197092 */ GIR_AddImm, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, /*Imm*/GIMT_Encode8(3855),
63976 /* 197103 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 476(*/0xDC, 0x03/*)*/,
63977 /* 197106 */ GIR_MakeTempReg, /*TempRegID*//* 474(*/0xDA, 0x03/*)*/, /*TypeID*/GILLT_s32,
63978 /* 197110 */ GIR_BuildMI, /*InsnID*//* 475(*/0xDB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
63979 /* 197115 */ GIR_AddTempRegister, /*InsnID*//* 475(*/0xDB, 0x03/*)*/, /*TempRegID*//* 474(*/0xDA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63980 /* 197122 */ GIR_AddImm, /*InsnID*//* 475(*/0xDB, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428),
63981 /* 197133 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 475(*/0xDB, 0x03/*)*/,
63982 /* 197136 */ GIR_MakeTempReg, /*TempRegID*//* 473(*/0xD9, 0x03/*)*/, /*TypeID*/GILLT_s32,
63983 /* 197140 */ GIR_BuildMI, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
63984 /* 197145 */ GIR_AddTempRegister, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, /*TempRegID*//* 473(*/0xD9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63985 /* 197152 */ GIR_AddSimpleTempRegister, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, /*TempRegID*//* 474(*/0xDA, 0x03/*)*/,
63986 /* 197157 */ GIR_AddImm, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428),
63987 /* 197168 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 474(*/0xDA, 0x03/*)*/,
63988 /* 197171 */ GIR_MakeTempReg, /*TempRegID*//* 472(*/0xD8, 0x03/*)*/, /*TypeID*/GILLT_s64,
63989 /* 197175 */ GIR_BuildMI, /*InsnID*//* 473(*/0xD9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
63990 /* 197180 */ GIR_AddTempRegister, /*InsnID*//* 473(*/0xD9, 0x03/*)*/, /*TempRegID*//* 472(*/0xD8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63991 /* 197187 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 473(*/0xD9, 0x03/*)*/,
63992 /* 197190 */ GIR_MakeTempReg, /*TempRegID*//* 471(*/0xD7, 0x03/*)*/, /*TypeID*/GILLT_s64,
63993 /* 197194 */ GIR_BuildMI, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
63994 /* 197199 */ GIR_AddTempRegister, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*TempRegID*//* 471(*/0xD7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
63995 /* 197206 */ GIR_AddSimpleTempRegister, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*TempRegID*//* 472(*/0xD8, 0x03/*)*/,
63996 /* 197211 */ GIR_AddSimpleTempRegister, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*TempRegID*//* 473(*/0xD9, 0x03/*)*/,
63997 /* 197216 */ GIR_AddImm8, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Imm*/1,
63998 /* 197220 */ GIR_ConstrainOperandRC, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
63999 /* 197226 */ GIR_ConstrainOperandRC, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64000 /* 197232 */ GIR_ConstrainOperandRC, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64001 /* 197238 */ GIR_MakeTempReg, /*TempRegID*//* 470(*/0xD6, 0x03/*)*/, /*TypeID*/GILLT_s64,
64002 /* 197242 */ GIR_BuildMI, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64003 /* 197247 */ GIR_AddTempRegister, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*TempRegID*//* 470(*/0xD6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64004 /* 197254 */ GIR_AddSimpleTempRegister, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*TempRegID*//* 471(*/0xD7, 0x03/*)*/,
64005 /* 197259 */ GIR_AddImm8, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*Imm*/32,
64006 /* 197263 */ GIR_AddImm8, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*Imm*/31,
64007 /* 197267 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 471(*/0xD7, 0x03/*)*/,
64008 /* 197270 */ GIR_MakeTempReg, /*TempRegID*//* 469(*/0xD5, 0x03/*)*/, /*TypeID*/GILLT_s64,
64009 /* 197274 */ GIR_BuildMI, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64010 /* 197279 */ GIR_AddTempRegister, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, /*TempRegID*//* 469(*/0xD5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64011 /* 197286 */ GIR_AddSimpleTempRegister, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, /*TempRegID*//* 470(*/0xD6, 0x03/*)*/,
64012 /* 197291 */ GIR_AddImm, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428),
64013 /* 197302 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 470(*/0xD6, 0x03/*)*/,
64014 /* 197305 */ GIR_MakeTempReg, /*TempRegID*//* 468(*/0xD4, 0x03/*)*/, /*TypeID*/GILLT_s64,
64015 /* 197309 */ GIR_BuildMI, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64016 /* 197314 */ GIR_AddTempRegister, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, /*TempRegID*//* 468(*/0xD4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64017 /* 197321 */ GIR_AddSimpleTempRegister, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, /*TempRegID*//* 469(*/0xD5, 0x03/*)*/,
64018 /* 197326 */ GIR_AddImm, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428),
64019 /* 197337 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 469(*/0xD5, 0x03/*)*/,
64020 /* 197340 */ GIR_MakeTempReg, /*TempRegID*//* 467(*/0xD3, 0x03/*)*/, /*TypeID*/GILLT_s32,
64021 /* 197344 */ GIR_BuildMI, /*InsnID*//* 468(*/0xD4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64022 /* 197349 */ GIR_AddTempRegister, /*InsnID*//* 468(*/0xD4, 0x03/*)*/, /*TempRegID*//* 467(*/0xD3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64023 /* 197356 */ GIR_AddImm, /*InsnID*//* 468(*/0xD4, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
64024 /* 197367 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 468(*/0xD4, 0x03/*)*/,
64025 /* 197370 */ GIR_MakeTempReg, /*TempRegID*//* 466(*/0xD2, 0x03/*)*/, /*TypeID*/GILLT_s32,
64026 /* 197374 */ GIR_BuildMI, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64027 /* 197379 */ GIR_AddTempRegister, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, /*TempRegID*//* 466(*/0xD2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64028 /* 197386 */ GIR_AddSimpleTempRegister, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, /*TempRegID*//* 467(*/0xD3, 0x03/*)*/,
64029 /* 197391 */ GIR_AddImm, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
64030 /* 197402 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 467(*/0xD3, 0x03/*)*/,
64031 /* 197405 */ GIR_MakeTempReg, /*TempRegID*//* 465(*/0xD1, 0x03/*)*/, /*TypeID*/GILLT_s64,
64032 /* 197409 */ GIR_BuildMI, /*InsnID*//* 466(*/0xD2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64033 /* 197414 */ GIR_AddTempRegister, /*InsnID*//* 466(*/0xD2, 0x03/*)*/, /*TempRegID*//* 465(*/0xD1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64034 /* 197421 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 466(*/0xD2, 0x03/*)*/,
64035 /* 197424 */ GIR_MakeTempReg, /*TempRegID*//* 464(*/0xD0, 0x03/*)*/, /*TypeID*/GILLT_s64,
64036 /* 197428 */ GIR_BuildMI, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64037 /* 197433 */ GIR_AddTempRegister, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*TempRegID*//* 464(*/0xD0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64038 /* 197440 */ GIR_AddSimpleTempRegister, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*TempRegID*//* 465(*/0xD1, 0x03/*)*/,
64039 /* 197445 */ GIR_AddSimpleTempRegister, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*TempRegID*//* 466(*/0xD2, 0x03/*)*/,
64040 /* 197450 */ GIR_AddImm8, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Imm*/1,
64041 /* 197454 */ GIR_ConstrainOperandRC, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64042 /* 197460 */ GIR_ConstrainOperandRC, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64043 /* 197466 */ GIR_ConstrainOperandRC, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64044 /* 197472 */ GIR_MakeTempReg, /*TempRegID*//* 463(*/0xCF, 0x03/*)*/, /*TypeID*/GILLT_s64,
64045 /* 197476 */ GIR_BuildMI, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64046 /* 197481 */ GIR_AddTempRegister, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*TempRegID*//* 463(*/0xCF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64047 /* 197488 */ GIR_AddSimpleTempRegister, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*TempRegID*//* 464(*/0xD0, 0x03/*)*/,
64048 /* 197493 */ GIR_AddImm8, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*Imm*/32,
64049 /* 197497 */ GIR_AddImm8, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*Imm*/31,
64050 /* 197501 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 464(*/0xD0, 0x03/*)*/,
64051 /* 197504 */ GIR_MakeTempReg, /*TempRegID*//* 462(*/0xCE, 0x03/*)*/, /*TypeID*/GILLT_s64,
64052 /* 197508 */ GIR_BuildMI, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64053 /* 197513 */ GIR_AddTempRegister, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, /*TempRegID*//* 462(*/0xCE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64054 /* 197520 */ GIR_AddSimpleTempRegister, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, /*TempRegID*//* 463(*/0xCF, 0x03/*)*/,
64055 /* 197525 */ GIR_AddImm, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
64056 /* 197536 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 463(*/0xCF, 0x03/*)*/,
64057 /* 197539 */ GIR_MakeTempReg, /*TempRegID*//* 461(*/0xCD, 0x03/*)*/, /*TypeID*/GILLT_s64,
64058 /* 197543 */ GIR_BuildMI, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64059 /* 197548 */ GIR_AddTempRegister, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, /*TempRegID*//* 461(*/0xCD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64060 /* 197555 */ GIR_AddSimpleTempRegister, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, /*TempRegID*//* 462(*/0xCE, 0x03/*)*/,
64061 /* 197560 */ GIR_AddImm, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
64062 /* 197571 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 462(*/0xCE, 0x03/*)*/,
64063 /* 197574 */ GIR_MakeTempReg, /*TempRegID*//* 460(*/0xCC, 0x03/*)*/, /*TypeID*/GILLT_s64,
64064 /* 197578 */ GIR_BuildMI, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64065 /* 197583 */ GIR_AddTempRegister, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, /*TempRegID*//* 460(*/0xCC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64066 /* 197590 */ GIR_Copy, /*NewInsnID*//* 461(*/0xCD, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64067 /* 197595 */ GIR_AddImm8, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, /*Imm*/1,
64068 /* 197599 */ GIR_AddImm8, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, /*Imm*/62,
64069 /* 197603 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 461(*/0xCD, 0x03/*)*/,
64070 /* 197606 */ GIR_MakeTempReg, /*TempRegID*//* 459(*/0xCB, 0x03/*)*/, /*TypeID*/GILLT_s64,
64071 /* 197610 */ GIR_BuildMI, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64072 /* 197615 */ GIR_AddTempRegister, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, /*TempRegID*//* 459(*/0xCB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64073 /* 197622 */ GIR_AddSimpleTempRegister, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, /*TempRegID*//* 460(*/0xCC, 0x03/*)*/,
64074 /* 197627 */ GIR_AddSimpleTempRegister, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, /*TempRegID*//* 461(*/0xCD, 0x03/*)*/,
64075 /* 197632 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 460(*/0xCC, 0x03/*)*/,
64076 /* 197635 */ GIR_MakeTempReg, /*TempRegID*//* 458(*/0xCA, 0x03/*)*/, /*TypeID*/GILLT_s32,
64077 /* 197639 */ GIR_BuildMI, /*InsnID*//* 459(*/0xCB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64078 /* 197644 */ GIR_AddTempRegister, /*InsnID*//* 459(*/0xCB, 0x03/*)*/, /*TempRegID*//* 458(*/0xCA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64079 /* 197651 */ GIR_AddImm, /*InsnID*//* 459(*/0xCB, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
64080 /* 197662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 459(*/0xCB, 0x03/*)*/,
64081 /* 197665 */ GIR_MakeTempReg, /*TempRegID*//* 457(*/0xC9, 0x03/*)*/, /*TypeID*/GILLT_s32,
64082 /* 197669 */ GIR_BuildMI, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64083 /* 197674 */ GIR_AddTempRegister, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, /*TempRegID*//* 457(*/0xC9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64084 /* 197681 */ GIR_AddSimpleTempRegister, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, /*TempRegID*//* 458(*/0xCA, 0x03/*)*/,
64085 /* 197686 */ GIR_AddImm, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
64086 /* 197697 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 458(*/0xCA, 0x03/*)*/,
64087 /* 197700 */ GIR_MakeTempReg, /*TempRegID*//* 456(*/0xC8, 0x03/*)*/, /*TypeID*/GILLT_s64,
64088 /* 197704 */ GIR_BuildMI, /*InsnID*//* 457(*/0xC9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64089 /* 197709 */ GIR_AddTempRegister, /*InsnID*//* 457(*/0xC9, 0x03/*)*/, /*TempRegID*//* 456(*/0xC8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64090 /* 197716 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 457(*/0xC9, 0x03/*)*/,
64091 /* 197719 */ GIR_MakeTempReg, /*TempRegID*//* 455(*/0xC7, 0x03/*)*/, /*TypeID*/GILLT_s64,
64092 /* 197723 */ GIR_BuildMI, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64093 /* 197728 */ GIR_AddTempRegister, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*TempRegID*//* 455(*/0xC7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64094 /* 197735 */ GIR_AddSimpleTempRegister, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*TempRegID*//* 456(*/0xC8, 0x03/*)*/,
64095 /* 197740 */ GIR_AddSimpleTempRegister, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*TempRegID*//* 457(*/0xC9, 0x03/*)*/,
64096 /* 197745 */ GIR_AddImm8, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Imm*/1,
64097 /* 197749 */ GIR_ConstrainOperandRC, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64098 /* 197755 */ GIR_ConstrainOperandRC, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64099 /* 197761 */ GIR_ConstrainOperandRC, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64100 /* 197767 */ GIR_MakeTempReg, /*TempRegID*//* 454(*/0xC6, 0x03/*)*/, /*TypeID*/GILLT_s64,
64101 /* 197771 */ GIR_BuildMI, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64102 /* 197776 */ GIR_AddTempRegister, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*TempRegID*//* 454(*/0xC6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64103 /* 197783 */ GIR_AddSimpleTempRegister, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*TempRegID*//* 455(*/0xC7, 0x03/*)*/,
64104 /* 197788 */ GIR_AddImm8, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*Imm*/32,
64105 /* 197792 */ GIR_AddImm8, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*Imm*/31,
64106 /* 197796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 455(*/0xC7, 0x03/*)*/,
64107 /* 197799 */ GIR_MakeTempReg, /*TempRegID*//* 453(*/0xC5, 0x03/*)*/, /*TypeID*/GILLT_s64,
64108 /* 197803 */ GIR_BuildMI, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64109 /* 197808 */ GIR_AddTempRegister, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, /*TempRegID*//* 453(*/0xC5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64110 /* 197815 */ GIR_AddSimpleTempRegister, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, /*TempRegID*//* 454(*/0xC6, 0x03/*)*/,
64111 /* 197820 */ GIR_AddImm, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
64112 /* 197831 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 454(*/0xC6, 0x03/*)*/,
64113 /* 197834 */ GIR_MakeTempReg, /*TempRegID*//* 452(*/0xC4, 0x03/*)*/, /*TypeID*/GILLT_s64,
64114 /* 197838 */ GIR_BuildMI, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64115 /* 197843 */ GIR_AddTempRegister, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, /*TempRegID*//* 452(*/0xC4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64116 /* 197850 */ GIR_AddSimpleTempRegister, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, /*TempRegID*//* 453(*/0xC5, 0x03/*)*/,
64117 /* 197855 */ GIR_AddImm, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
64118 /* 197866 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 453(*/0xC5, 0x03/*)*/,
64119 /* 197869 */ GIR_MakeTempReg, /*TempRegID*//* 451(*/0xC3, 0x03/*)*/, /*TypeID*/GILLT_s64,
64120 /* 197873 */ GIR_BuildMI, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64121 /* 197878 */ GIR_AddTempRegister, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, /*TempRegID*//* 451(*/0xC3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64122 /* 197885 */ GIR_Copy, /*NewInsnID*//* 452(*/0xC4, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64123 /* 197890 */ GIR_AddImm8, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, /*Imm*/63,
64124 /* 197894 */ GIR_AddImm8, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, /*Imm*/1,
64125 /* 197898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 452(*/0xC4, 0x03/*)*/,
64126 /* 197901 */ GIR_MakeTempReg, /*TempRegID*//* 450(*/0xC2, 0x03/*)*/, /*TypeID*/GILLT_s64,
64127 /* 197905 */ GIR_BuildMI, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64128 /* 197910 */ GIR_AddTempRegister, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, /*TempRegID*//* 450(*/0xC2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64129 /* 197917 */ GIR_AddSimpleTempRegister, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, /*TempRegID*//* 451(*/0xC3, 0x03/*)*/,
64130 /* 197922 */ GIR_AddSimpleTempRegister, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, /*TempRegID*//* 452(*/0xC4, 0x03/*)*/,
64131 /* 197927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 451(*/0xC3, 0x03/*)*/,
64132 /* 197930 */ GIR_MakeTempReg, /*TempRegID*//* 449(*/0xC1, 0x03/*)*/, /*TypeID*/GILLT_s64,
64133 /* 197934 */ GIR_BuildMI, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
64134 /* 197939 */ GIR_AddTempRegister, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, /*TempRegID*//* 449(*/0xC1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64135 /* 197946 */ GIR_AddSimpleTempRegister, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, /*TempRegID*//* 450(*/0xC2, 0x03/*)*/,
64136 /* 197951 */ GIR_AddSimpleTempRegister, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, /*TempRegID*//* 459(*/0xCB, 0x03/*)*/,
64137 /* 197956 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 450(*/0xC2, 0x03/*)*/,
64138 /* 197959 */ GIR_MakeTempReg, /*TempRegID*//* 448(*/0xC0, 0x03/*)*/, /*TypeID*/GILLT_s64,
64139 /* 197963 */ GIR_BuildMI, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64140 /* 197968 */ GIR_AddTempRegister, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*TempRegID*//* 448(*/0xC0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64141 /* 197975 */ GIR_AddSimpleTempRegister, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*TempRegID*//* 449(*/0xC1, 0x03/*)*/,
64142 /* 197980 */ GIR_AddImm8, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*Imm*/2,
64143 /* 197984 */ GIR_AddImm8, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*Imm*/61,
64144 /* 197988 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 449(*/0xC1, 0x03/*)*/,
64145 /* 197991 */ GIR_MakeTempReg, /*TempRegID*//* 447(*/0xBF, 0x03/*)*/, /*TypeID*/GILLT_s64,
64146 /* 197995 */ GIR_BuildMI, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64147 /* 198000 */ GIR_AddTempRegister, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, /*TempRegID*//* 447(*/0xBF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64148 /* 198007 */ GIR_AddSimpleTempRegister, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, /*TempRegID*//* 448(*/0xC0, 0x03/*)*/,
64149 /* 198012 */ GIR_AddSimpleTempRegister, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, /*TempRegID*//* 468(*/0xD4, 0x03/*)*/,
64150 /* 198017 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 448(*/0xC0, 0x03/*)*/,
64151 /* 198020 */ GIR_MakeTempReg, /*TempRegID*//* 446(*/0xBE, 0x03/*)*/, /*TypeID*/GILLT_s32,
64152 /* 198024 */ GIR_BuildMI, /*InsnID*//* 447(*/0xBF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64153 /* 198029 */ GIR_AddTempRegister, /*InsnID*//* 447(*/0xBF, 0x03/*)*/, /*TempRegID*//* 446(*/0xBE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64154 /* 198036 */ GIR_AddImm, /*InsnID*//* 447(*/0xBF, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107),
64155 /* 198047 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 447(*/0xBF, 0x03/*)*/,
64156 /* 198050 */ GIR_MakeTempReg, /*TempRegID*//* 445(*/0xBD, 0x03/*)*/, /*TypeID*/GILLT_s32,
64157 /* 198054 */ GIR_BuildMI, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64158 /* 198059 */ GIR_AddTempRegister, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, /*TempRegID*//* 445(*/0xBD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64159 /* 198066 */ GIR_AddSimpleTempRegister, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, /*TempRegID*//* 446(*/0xBE, 0x03/*)*/,
64160 /* 198071 */ GIR_AddImm, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107),
64161 /* 198082 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 446(*/0xBE, 0x03/*)*/,
64162 /* 198085 */ GIR_MakeTempReg, /*TempRegID*//* 444(*/0xBC, 0x03/*)*/, /*TypeID*/GILLT_s64,
64163 /* 198089 */ GIR_BuildMI, /*InsnID*//* 445(*/0xBD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64164 /* 198094 */ GIR_AddTempRegister, /*InsnID*//* 445(*/0xBD, 0x03/*)*/, /*TempRegID*//* 444(*/0xBC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64165 /* 198101 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 445(*/0xBD, 0x03/*)*/,
64166 /* 198104 */ GIR_MakeTempReg, /*TempRegID*//* 443(*/0xBB, 0x03/*)*/, /*TypeID*/GILLT_s64,
64167 /* 198108 */ GIR_BuildMI, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64168 /* 198113 */ GIR_AddTempRegister, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*TempRegID*//* 443(*/0xBB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64169 /* 198120 */ GIR_AddSimpleTempRegister, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*TempRegID*//* 444(*/0xBC, 0x03/*)*/,
64170 /* 198125 */ GIR_AddSimpleTempRegister, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*TempRegID*//* 445(*/0xBD, 0x03/*)*/,
64171 /* 198130 */ GIR_AddImm8, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Imm*/1,
64172 /* 198134 */ GIR_ConstrainOperandRC, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64173 /* 198140 */ GIR_ConstrainOperandRC, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64174 /* 198146 */ GIR_ConstrainOperandRC, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64175 /* 198152 */ GIR_MakeTempReg, /*TempRegID*//* 442(*/0xBA, 0x03/*)*/, /*TypeID*/GILLT_s64,
64176 /* 198156 */ GIR_BuildMI, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64177 /* 198161 */ GIR_AddTempRegister, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*TempRegID*//* 442(*/0xBA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64178 /* 198168 */ GIR_AddSimpleTempRegister, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*TempRegID*//* 443(*/0xBB, 0x03/*)*/,
64179 /* 198173 */ GIR_AddImm8, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*Imm*/32,
64180 /* 198177 */ GIR_AddImm8, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*Imm*/31,
64181 /* 198181 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 443(*/0xBB, 0x03/*)*/,
64182 /* 198184 */ GIR_MakeTempReg, /*TempRegID*//* 441(*/0xB9, 0x03/*)*/, /*TypeID*/GILLT_s64,
64183 /* 198188 */ GIR_BuildMI, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64184 /* 198193 */ GIR_AddTempRegister, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, /*TempRegID*//* 441(*/0xB9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64185 /* 198200 */ GIR_AddSimpleTempRegister, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, /*TempRegID*//* 442(*/0xBA, 0x03/*)*/,
64186 /* 198205 */ GIR_AddImm, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107),
64187 /* 198216 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 442(*/0xBA, 0x03/*)*/,
64188 /* 198219 */ GIR_MakeTempReg, /*TempRegID*//* 440(*/0xB8, 0x03/*)*/, /*TypeID*/GILLT_s64,
64189 /* 198223 */ GIR_BuildMI, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64190 /* 198228 */ GIR_AddTempRegister, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, /*TempRegID*//* 440(*/0xB8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64191 /* 198235 */ GIR_AddSimpleTempRegister, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, /*TempRegID*//* 441(*/0xB9, 0x03/*)*/,
64192 /* 198240 */ GIR_AddImm, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107),
64193 /* 198251 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 441(*/0xB9, 0x03/*)*/,
64194 /* 198254 */ GIR_MakeTempReg, /*TempRegID*//* 439(*/0xB7, 0x03/*)*/, /*TypeID*/GILLT_s32,
64195 /* 198258 */ GIR_BuildMI, /*InsnID*//* 440(*/0xB8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64196 /* 198263 */ GIR_AddTempRegister, /*InsnID*//* 440(*/0xB8, 0x03/*)*/, /*TempRegID*//* 439(*/0xB7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64197 /* 198270 */ GIR_AddImm, /*InsnID*//* 440(*/0xB8, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
64198 /* 198281 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 440(*/0xB8, 0x03/*)*/,
64199 /* 198284 */ GIR_MakeTempReg, /*TempRegID*//* 438(*/0xB6, 0x03/*)*/, /*TypeID*/GILLT_s32,
64200 /* 198288 */ GIR_BuildMI, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64201 /* 198293 */ GIR_AddTempRegister, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, /*TempRegID*//* 438(*/0xB6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64202 /* 198300 */ GIR_AddSimpleTempRegister, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, /*TempRegID*//* 439(*/0xB7, 0x03/*)*/,
64203 /* 198305 */ GIR_AddImm, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
64204 /* 198316 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 439(*/0xB7, 0x03/*)*/,
64205 /* 198319 */ GIR_MakeTempReg, /*TempRegID*//* 437(*/0xB5, 0x03/*)*/, /*TypeID*/GILLT_s64,
64206 /* 198323 */ GIR_BuildMI, /*InsnID*//* 438(*/0xB6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64207 /* 198328 */ GIR_AddTempRegister, /*InsnID*//* 438(*/0xB6, 0x03/*)*/, /*TempRegID*//* 437(*/0xB5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64208 /* 198335 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 438(*/0xB6, 0x03/*)*/,
64209 /* 198338 */ GIR_MakeTempReg, /*TempRegID*//* 436(*/0xB4, 0x03/*)*/, /*TypeID*/GILLT_s64,
64210 /* 198342 */ GIR_BuildMI, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64211 /* 198347 */ GIR_AddTempRegister, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*TempRegID*//* 436(*/0xB4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64212 /* 198354 */ GIR_AddSimpleTempRegister, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*TempRegID*//* 437(*/0xB5, 0x03/*)*/,
64213 /* 198359 */ GIR_AddSimpleTempRegister, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*TempRegID*//* 438(*/0xB6, 0x03/*)*/,
64214 /* 198364 */ GIR_AddImm8, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Imm*/1,
64215 /* 198368 */ GIR_ConstrainOperandRC, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64216 /* 198374 */ GIR_ConstrainOperandRC, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64217 /* 198380 */ GIR_ConstrainOperandRC, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64218 /* 198386 */ GIR_MakeTempReg, /*TempRegID*//* 435(*/0xB3, 0x03/*)*/, /*TypeID*/GILLT_s64,
64219 /* 198390 */ GIR_BuildMI, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64220 /* 198395 */ GIR_AddTempRegister, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*TempRegID*//* 435(*/0xB3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64221 /* 198402 */ GIR_AddSimpleTempRegister, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*TempRegID*//* 436(*/0xB4, 0x03/*)*/,
64222 /* 198407 */ GIR_AddImm8, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*Imm*/32,
64223 /* 198411 */ GIR_AddImm8, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*Imm*/31,
64224 /* 198415 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 436(*/0xB4, 0x03/*)*/,
64225 /* 198418 */ GIR_MakeTempReg, /*TempRegID*//* 434(*/0xB2, 0x03/*)*/, /*TypeID*/GILLT_s64,
64226 /* 198422 */ GIR_BuildMI, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64227 /* 198427 */ GIR_AddTempRegister, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, /*TempRegID*//* 434(*/0xB2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64228 /* 198434 */ GIR_AddSimpleTempRegister, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, /*TempRegID*//* 435(*/0xB3, 0x03/*)*/,
64229 /* 198439 */ GIR_AddImm, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
64230 /* 198450 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 435(*/0xB3, 0x03/*)*/,
64231 /* 198453 */ GIR_MakeTempReg, /*TempRegID*//* 433(*/0xB1, 0x03/*)*/, /*TypeID*/GILLT_s64,
64232 /* 198457 */ GIR_BuildMI, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64233 /* 198462 */ GIR_AddTempRegister, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, /*TempRegID*//* 433(*/0xB1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64234 /* 198469 */ GIR_AddSimpleTempRegister, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, /*TempRegID*//* 434(*/0xB2, 0x03/*)*/,
64235 /* 198474 */ GIR_AddImm, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690),
64236 /* 198485 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 434(*/0xB2, 0x03/*)*/,
64237 /* 198488 */ GIR_MakeTempReg, /*TempRegID*//* 432(*/0xB0, 0x03/*)*/, /*TypeID*/GILLT_s64,
64238 /* 198492 */ GIR_BuildMI, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64239 /* 198497 */ GIR_AddTempRegister, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, /*TempRegID*//* 432(*/0xB0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64240 /* 198504 */ GIR_Copy, /*NewInsnID*//* 433(*/0xB1, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64241 /* 198509 */ GIR_AddImm8, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, /*Imm*/1,
64242 /* 198513 */ GIR_AddImm8, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, /*Imm*/62,
64243 /* 198517 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 433(*/0xB1, 0x03/*)*/,
64244 /* 198520 */ GIR_MakeTempReg, /*TempRegID*//* 431(*/0xAF, 0x03/*)*/, /*TypeID*/GILLT_s64,
64245 /* 198524 */ GIR_BuildMI, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64246 /* 198529 */ GIR_AddTempRegister, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, /*TempRegID*//* 431(*/0xAF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64247 /* 198536 */ GIR_AddSimpleTempRegister, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, /*TempRegID*//* 432(*/0xB0, 0x03/*)*/,
64248 /* 198541 */ GIR_AddSimpleTempRegister, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, /*TempRegID*//* 433(*/0xB1, 0x03/*)*/,
64249 /* 198546 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 432(*/0xB0, 0x03/*)*/,
64250 /* 198549 */ GIR_MakeTempReg, /*TempRegID*//* 430(*/0xAE, 0x03/*)*/, /*TypeID*/GILLT_s32,
64251 /* 198553 */ GIR_BuildMI, /*InsnID*//* 431(*/0xAF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64252 /* 198558 */ GIR_AddTempRegister, /*InsnID*//* 431(*/0xAF, 0x03/*)*/, /*TempRegID*//* 430(*/0xAE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64253 /* 198565 */ GIR_AddImm, /*InsnID*//* 431(*/0xAF, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
64254 /* 198576 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 431(*/0xAF, 0x03/*)*/,
64255 /* 198579 */ GIR_MakeTempReg, /*TempRegID*//* 429(*/0xAD, 0x03/*)*/, /*TypeID*/GILLT_s32,
64256 /* 198583 */ GIR_BuildMI, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64257 /* 198588 */ GIR_AddTempRegister, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, /*TempRegID*//* 429(*/0xAD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64258 /* 198595 */ GIR_AddSimpleTempRegister, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, /*TempRegID*//* 430(*/0xAE, 0x03/*)*/,
64259 /* 198600 */ GIR_AddImm, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
64260 /* 198611 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 430(*/0xAE, 0x03/*)*/,
64261 /* 198614 */ GIR_MakeTempReg, /*TempRegID*//* 428(*/0xAC, 0x03/*)*/, /*TypeID*/GILLT_s64,
64262 /* 198618 */ GIR_BuildMI, /*InsnID*//* 429(*/0xAD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64263 /* 198623 */ GIR_AddTempRegister, /*InsnID*//* 429(*/0xAD, 0x03/*)*/, /*TempRegID*//* 428(*/0xAC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64264 /* 198630 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 429(*/0xAD, 0x03/*)*/,
64265 /* 198633 */ GIR_MakeTempReg, /*TempRegID*//* 427(*/0xAB, 0x03/*)*/, /*TypeID*/GILLT_s64,
64266 /* 198637 */ GIR_BuildMI, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64267 /* 198642 */ GIR_AddTempRegister, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*TempRegID*//* 427(*/0xAB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64268 /* 198649 */ GIR_AddSimpleTempRegister, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*TempRegID*//* 428(*/0xAC, 0x03/*)*/,
64269 /* 198654 */ GIR_AddSimpleTempRegister, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*TempRegID*//* 429(*/0xAD, 0x03/*)*/,
64270 /* 198659 */ GIR_AddImm8, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Imm*/1,
64271 /* 198663 */ GIR_ConstrainOperandRC, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64272 /* 198669 */ GIR_ConstrainOperandRC, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64273 /* 198675 */ GIR_ConstrainOperandRC, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64274 /* 198681 */ GIR_MakeTempReg, /*TempRegID*//* 426(*/0xAA, 0x03/*)*/, /*TypeID*/GILLT_s64,
64275 /* 198685 */ GIR_BuildMI, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64276 /* 198690 */ GIR_AddTempRegister, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*TempRegID*//* 426(*/0xAA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64277 /* 198697 */ GIR_AddSimpleTempRegister, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*TempRegID*//* 427(*/0xAB, 0x03/*)*/,
64278 /* 198702 */ GIR_AddImm8, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*Imm*/32,
64279 /* 198706 */ GIR_AddImm8, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*Imm*/31,
64280 /* 198710 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 427(*/0xAB, 0x03/*)*/,
64281 /* 198713 */ GIR_MakeTempReg, /*TempRegID*//* 425(*/0xA9, 0x03/*)*/, /*TypeID*/GILLT_s64,
64282 /* 198717 */ GIR_BuildMI, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64283 /* 198722 */ GIR_AddTempRegister, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, /*TempRegID*//* 425(*/0xA9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64284 /* 198729 */ GIR_AddSimpleTempRegister, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, /*TempRegID*//* 426(*/0xAA, 0x03/*)*/,
64285 /* 198734 */ GIR_AddImm, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
64286 /* 198745 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 426(*/0xAA, 0x03/*)*/,
64287 /* 198748 */ GIR_MakeTempReg, /*TempRegID*//* 424(*/0xA8, 0x03/*)*/, /*TypeID*/GILLT_s64,
64288 /* 198752 */ GIR_BuildMI, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64289 /* 198757 */ GIR_AddTempRegister, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, /*TempRegID*//* 424(*/0xA8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64290 /* 198764 */ GIR_AddSimpleTempRegister, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, /*TempRegID*//* 425(*/0xA9, 0x03/*)*/,
64291 /* 198769 */ GIR_AddImm, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845),
64292 /* 198780 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 425(*/0xA9, 0x03/*)*/,
64293 /* 198783 */ GIR_MakeTempReg, /*TempRegID*//* 423(*/0xA7, 0x03/*)*/, /*TypeID*/GILLT_s64,
64294 /* 198787 */ GIR_BuildMI, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64295 /* 198792 */ GIR_AddTempRegister, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, /*TempRegID*//* 423(*/0xA7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64296 /* 198799 */ GIR_Copy, /*NewInsnID*//* 424(*/0xA8, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64297 /* 198804 */ GIR_AddImm8, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, /*Imm*/63,
64298 /* 198808 */ GIR_AddImm8, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, /*Imm*/1,
64299 /* 198812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 424(*/0xA8, 0x03/*)*/,
64300 /* 198815 */ GIR_MakeTempReg, /*TempRegID*//* 422(*/0xA6, 0x03/*)*/, /*TypeID*/GILLT_s64,
64301 /* 198819 */ GIR_BuildMI, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64302 /* 198824 */ GIR_AddTempRegister, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, /*TempRegID*//* 422(*/0xA6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64303 /* 198831 */ GIR_AddSimpleTempRegister, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, /*TempRegID*//* 423(*/0xA7, 0x03/*)*/,
64304 /* 198836 */ GIR_AddSimpleTempRegister, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, /*TempRegID*//* 424(*/0xA8, 0x03/*)*/,
64305 /* 198841 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 423(*/0xA7, 0x03/*)*/,
64306 /* 198844 */ GIR_MakeTempReg, /*TempRegID*//* 421(*/0xA5, 0x03/*)*/, /*TypeID*/GILLT_s64,
64307 /* 198848 */ GIR_BuildMI, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
64308 /* 198853 */ GIR_AddTempRegister, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, /*TempRegID*//* 421(*/0xA5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64309 /* 198860 */ GIR_AddSimpleTempRegister, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, /*TempRegID*//* 422(*/0xA6, 0x03/*)*/,
64310 /* 198865 */ GIR_AddSimpleTempRegister, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, /*TempRegID*//* 431(*/0xAF, 0x03/*)*/,
64311 /* 198870 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 422(*/0xA6, 0x03/*)*/,
64312 /* 198873 */ GIR_MakeTempReg, /*TempRegID*//* 420(*/0xA4, 0x03/*)*/, /*TypeID*/GILLT_s64,
64313 /* 198877 */ GIR_BuildMI, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64314 /* 198882 */ GIR_AddTempRegister, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*TempRegID*//* 420(*/0xA4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64315 /* 198889 */ GIR_AddSimpleTempRegister, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*TempRegID*//* 421(*/0xA5, 0x03/*)*/,
64316 /* 198894 */ GIR_AddImm8, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*Imm*/62,
64317 /* 198898 */ GIR_AddImm8, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*Imm*/2,
64318 /* 198902 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 421(*/0xA5, 0x03/*)*/,
64319 /* 198905 */ GIR_MakeTempReg, /*TempRegID*//* 419(*/0xA3, 0x03/*)*/, /*TypeID*/GILLT_s64,
64320 /* 198909 */ GIR_BuildMI, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64321 /* 198914 */ GIR_AddTempRegister, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, /*TempRegID*//* 419(*/0xA3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64322 /* 198921 */ GIR_AddSimpleTempRegister, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, /*TempRegID*//* 420(*/0xA4, 0x03/*)*/,
64323 /* 198926 */ GIR_AddSimpleTempRegister, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, /*TempRegID*//* 440(*/0xB8, 0x03/*)*/,
64324 /* 198931 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 420(*/0xA4, 0x03/*)*/,
64325 /* 198934 */ GIR_MakeTempReg, /*TempRegID*//* 418(*/0xA2, 0x03/*)*/, /*TypeID*/GILLT_s64,
64326 /* 198938 */ GIR_BuildMI, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
64327 /* 198943 */ GIR_AddTempRegister, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, /*TempRegID*//* 418(*/0xA2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64328 /* 198950 */ GIR_AddSimpleTempRegister, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, /*TempRegID*//* 419(*/0xA3, 0x03/*)*/,
64329 /* 198955 */ GIR_AddSimpleTempRegister, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, /*TempRegID*//* 447(*/0xBF, 0x03/*)*/,
64330 /* 198960 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 419(*/0xA3, 0x03/*)*/,
64331 /* 198963 */ GIR_MakeTempReg, /*TempRegID*//* 417(*/0xA1, 0x03/*)*/, /*TypeID*/GILLT_s64,
64332 /* 198967 */ GIR_BuildMI, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64333 /* 198972 */ GIR_AddTempRegister, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*TempRegID*//* 417(*/0xA1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64334 /* 198979 */ GIR_AddSimpleTempRegister, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*TempRegID*//* 418(*/0xA2, 0x03/*)*/,
64335 /* 198984 */ GIR_AddImm8, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*Imm*/60,
64336 /* 198988 */ GIR_AddImm8, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*Imm*/4,
64337 /* 198992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 418(*/0xA2, 0x03/*)*/,
64338 /* 198995 */ GIR_MakeTempReg, /*TempRegID*//* 416(*/0xA0, 0x03/*)*/, /*TypeID*/GILLT_s64,
64339 /* 198999 */ GIR_BuildMI, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64340 /* 199004 */ GIR_AddTempRegister, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, /*TempRegID*//* 416(*/0xA0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64341 /* 199011 */ GIR_AddSimpleTempRegister, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, /*TempRegID*//* 417(*/0xA1, 0x03/*)*/,
64342 /* 199016 */ GIR_AddSimpleTempRegister, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, /*TempRegID*//* 475(*/0xDB, 0x03/*)*/,
64343 /* 199021 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 417(*/0xA1, 0x03/*)*/,
64344 /* 199024 */ GIR_MakeTempReg, /*TempRegID*//* 415(*/0x9F, 0x03/*)*/, /*TypeID*/GILLT_s64,
64345 /* 199028 */ GIR_BuildMI, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
64346 /* 199033 */ GIR_AddTempRegister, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, /*TempRegID*//* 415(*/0x9F, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64347 /* 199040 */ GIR_AddSimpleTempRegister, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, /*TempRegID*//* 416(*/0xA0, 0x03/*)*/,
64348 /* 199045 */ GIR_AddSimpleTempRegister, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, /*TempRegID*//* 482(*/0xE2, 0x03/*)*/,
64349 /* 199050 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 416(*/0xA0, 0x03/*)*/,
64350 /* 199053 */ GIR_MakeTempReg, /*TempRegID*//* 414(*/0x9E, 0x03/*)*/, /*TypeID*/GILLT_s64,
64351 /* 199057 */ GIR_BuildMI, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64352 /* 199062 */ GIR_AddTempRegister, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*TempRegID*//* 414(*/0x9E, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64353 /* 199069 */ GIR_AddSimpleTempRegister, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*TempRegID*//* 415(*/0x9F, 0x03/*)*/,
64354 /* 199074 */ GIR_AddImm8, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*Imm*/32,
64355 /* 199078 */ GIR_AddImm8, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*Imm*/32,
64356 /* 199082 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 415(*/0x9F, 0x03/*)*/,
64357 /* 199085 */ GIR_MakeTempReg, /*TempRegID*//* 682(*/0xAA, 0x05/*)*/, /*TypeID*/GILLT_s32,
64358 /* 199089 */ GIR_BuildMI, /*InsnID*//* 683(*/0xAB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64359 /* 199094 */ GIR_AddTempRegister, /*InsnID*//* 683(*/0xAB, 0x05/*)*/, /*TempRegID*//* 682(*/0xAA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64360 /* 199101 */ GIR_AddImm, /*InsnID*//* 683(*/0xAB, 0x05/*)*/, /*Imm*/GIMT_Encode8(61680),
64361 /* 199112 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 683(*/0xAB, 0x05/*)*/,
64362 /* 199115 */ GIR_MakeTempReg, /*TempRegID*//* 681(*/0xA9, 0x05/*)*/, /*TypeID*/GILLT_s32,
64363 /* 199119 */ GIR_BuildMI, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64364 /* 199124 */ GIR_AddTempRegister, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, /*TempRegID*//* 681(*/0xA9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64365 /* 199131 */ GIR_AddSimpleTempRegister, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, /*TempRegID*//* 682(*/0xAA, 0x05/*)*/,
64366 /* 199136 */ GIR_AddImm, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, /*Imm*/GIMT_Encode8(61680),
64367 /* 199147 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 682(*/0xAA, 0x05/*)*/,
64368 /* 199150 */ GIR_MakeTempReg, /*TempRegID*//* 680(*/0xA8, 0x05/*)*/, /*TypeID*/GILLT_s64,
64369 /* 199154 */ GIR_BuildMI, /*InsnID*//* 681(*/0xA9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64370 /* 199159 */ GIR_AddTempRegister, /*InsnID*//* 681(*/0xA9, 0x05/*)*/, /*TempRegID*//* 680(*/0xA8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64371 /* 199166 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 681(*/0xA9, 0x05/*)*/,
64372 /* 199169 */ GIR_MakeTempReg, /*TempRegID*//* 679(*/0xA7, 0x05/*)*/, /*TypeID*/GILLT_s64,
64373 /* 199173 */ GIR_BuildMI, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64374 /* 199178 */ GIR_AddTempRegister, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*TempRegID*//* 679(*/0xA7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64375 /* 199185 */ GIR_AddSimpleTempRegister, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*TempRegID*//* 680(*/0xA8, 0x05/*)*/,
64376 /* 199190 */ GIR_AddSimpleTempRegister, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*TempRegID*//* 681(*/0xA9, 0x05/*)*/,
64377 /* 199195 */ GIR_AddImm8, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Imm*/1,
64378 /* 199199 */ GIR_ConstrainOperandRC, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64379 /* 199205 */ GIR_ConstrainOperandRC, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64380 /* 199211 */ GIR_ConstrainOperandRC, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64381 /* 199217 */ GIR_MakeTempReg, /*TempRegID*//* 678(*/0xA6, 0x05/*)*/, /*TypeID*/GILLT_s64,
64382 /* 199221 */ GIR_BuildMI, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64383 /* 199226 */ GIR_AddTempRegister, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*TempRegID*//* 678(*/0xA6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64384 /* 199233 */ GIR_AddSimpleTempRegister, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*TempRegID*//* 679(*/0xA7, 0x05/*)*/,
64385 /* 199238 */ GIR_AddImm8, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*Imm*/32,
64386 /* 199242 */ GIR_AddImm8, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*Imm*/31,
64387 /* 199246 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 679(*/0xA7, 0x05/*)*/,
64388 /* 199249 */ GIR_MakeTempReg, /*TempRegID*//* 677(*/0xA5, 0x05/*)*/, /*TypeID*/GILLT_s64,
64389 /* 199253 */ GIR_BuildMI, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64390 /* 199258 */ GIR_AddTempRegister, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, /*TempRegID*//* 677(*/0xA5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64391 /* 199265 */ GIR_AddSimpleTempRegister, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, /*TempRegID*//* 678(*/0xA6, 0x05/*)*/,
64392 /* 199270 */ GIR_AddImm, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, /*Imm*/GIMT_Encode8(61680),
64393 /* 199281 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 678(*/0xA6, 0x05/*)*/,
64394 /* 199284 */ GIR_MakeTempReg, /*TempRegID*//* 676(*/0xA4, 0x05/*)*/, /*TypeID*/GILLT_s64,
64395 /* 199288 */ GIR_BuildMI, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64396 /* 199293 */ GIR_AddTempRegister, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, /*TempRegID*//* 676(*/0xA4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64397 /* 199300 */ GIR_AddSimpleTempRegister, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, /*TempRegID*//* 677(*/0xA5, 0x05/*)*/,
64398 /* 199305 */ GIR_AddImm, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, /*Imm*/GIMT_Encode8(61680),
64399 /* 199316 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 677(*/0xA5, 0x05/*)*/,
64400 /* 199319 */ GIR_MakeTempReg, /*TempRegID*//* 675(*/0xA3, 0x05/*)*/, /*TypeID*/GILLT_s32,
64401 /* 199323 */ GIR_BuildMI, /*InsnID*//* 676(*/0xA4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64402 /* 199328 */ GIR_AddTempRegister, /*InsnID*//* 676(*/0xA4, 0x05/*)*/, /*TempRegID*//* 675(*/0xA3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64403 /* 199335 */ GIR_AddImm, /*InsnID*//* 676(*/0xA4, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428),
64404 /* 199346 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 676(*/0xA4, 0x05/*)*/,
64405 /* 199349 */ GIR_MakeTempReg, /*TempRegID*//* 674(*/0xA2, 0x05/*)*/, /*TypeID*/GILLT_s32,
64406 /* 199353 */ GIR_BuildMI, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64407 /* 199358 */ GIR_AddTempRegister, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, /*TempRegID*//* 674(*/0xA2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64408 /* 199365 */ GIR_AddSimpleTempRegister, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, /*TempRegID*//* 675(*/0xA3, 0x05/*)*/,
64409 /* 199370 */ GIR_AddImm, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428),
64410 /* 199381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 675(*/0xA3, 0x05/*)*/,
64411 /* 199384 */ GIR_MakeTempReg, /*TempRegID*//* 673(*/0xA1, 0x05/*)*/, /*TypeID*/GILLT_s64,
64412 /* 199388 */ GIR_BuildMI, /*InsnID*//* 674(*/0xA2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64413 /* 199393 */ GIR_AddTempRegister, /*InsnID*//* 674(*/0xA2, 0x05/*)*/, /*TempRegID*//* 673(*/0xA1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64414 /* 199400 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 674(*/0xA2, 0x05/*)*/,
64415 /* 199403 */ GIR_MakeTempReg, /*TempRegID*//* 672(*/0xA0, 0x05/*)*/, /*TypeID*/GILLT_s64,
64416 /* 199407 */ GIR_BuildMI, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64417 /* 199412 */ GIR_AddTempRegister, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*TempRegID*//* 672(*/0xA0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64418 /* 199419 */ GIR_AddSimpleTempRegister, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*TempRegID*//* 673(*/0xA1, 0x05/*)*/,
64419 /* 199424 */ GIR_AddSimpleTempRegister, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*TempRegID*//* 674(*/0xA2, 0x05/*)*/,
64420 /* 199429 */ GIR_AddImm8, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Imm*/1,
64421 /* 199433 */ GIR_ConstrainOperandRC, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64422 /* 199439 */ GIR_ConstrainOperandRC, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64423 /* 199445 */ GIR_ConstrainOperandRC, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64424 /* 199451 */ GIR_MakeTempReg, /*TempRegID*//* 671(*/0x9F, 0x05/*)*/, /*TypeID*/GILLT_s64,
64425 /* 199455 */ GIR_BuildMI, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64426 /* 199460 */ GIR_AddTempRegister, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*TempRegID*//* 671(*/0x9F, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64427 /* 199467 */ GIR_AddSimpleTempRegister, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*TempRegID*//* 672(*/0xA0, 0x05/*)*/,
64428 /* 199472 */ GIR_AddImm8, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*Imm*/32,
64429 /* 199476 */ GIR_AddImm8, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*Imm*/31,
64430 /* 199480 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 672(*/0xA0, 0x05/*)*/,
64431 /* 199483 */ GIR_MakeTempReg, /*TempRegID*//* 670(*/0x9E, 0x05/*)*/, /*TypeID*/GILLT_s64,
64432 /* 199487 */ GIR_BuildMI, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64433 /* 199492 */ GIR_AddTempRegister, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, /*TempRegID*//* 670(*/0x9E, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64434 /* 199499 */ GIR_AddSimpleTempRegister, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, /*TempRegID*//* 671(*/0x9F, 0x05/*)*/,
64435 /* 199504 */ GIR_AddImm, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428),
64436 /* 199515 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 671(*/0x9F, 0x05/*)*/,
64437 /* 199518 */ GIR_MakeTempReg, /*TempRegID*//* 669(*/0x9D, 0x05/*)*/, /*TypeID*/GILLT_s64,
64438 /* 199522 */ GIR_BuildMI, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64439 /* 199527 */ GIR_AddTempRegister, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, /*TempRegID*//* 669(*/0x9D, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64440 /* 199534 */ GIR_AddSimpleTempRegister, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, /*TempRegID*//* 670(*/0x9E, 0x05/*)*/,
64441 /* 199539 */ GIR_AddImm, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428),
64442 /* 199550 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 670(*/0x9E, 0x05/*)*/,
64443 /* 199553 */ GIR_MakeTempReg, /*TempRegID*//* 668(*/0x9C, 0x05/*)*/, /*TypeID*/GILLT_s32,
64444 /* 199557 */ GIR_BuildMI, /*InsnID*//* 669(*/0x9D, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64445 /* 199562 */ GIR_AddTempRegister, /*InsnID*//* 669(*/0x9D, 0x05/*)*/, /*TempRegID*//* 668(*/0x9C, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64446 /* 199569 */ GIR_AddImm, /*InsnID*//* 669(*/0x9D, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
64447 /* 199580 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 669(*/0x9D, 0x05/*)*/,
64448 /* 199583 */ GIR_MakeTempReg, /*TempRegID*//* 667(*/0x9B, 0x05/*)*/, /*TypeID*/GILLT_s32,
64449 /* 199587 */ GIR_BuildMI, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64450 /* 199592 */ GIR_AddTempRegister, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, /*TempRegID*//* 667(*/0x9B, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64451 /* 199599 */ GIR_AddSimpleTempRegister, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, /*TempRegID*//* 668(*/0x9C, 0x05/*)*/,
64452 /* 199604 */ GIR_AddImm, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
64453 /* 199615 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 668(*/0x9C, 0x05/*)*/,
64454 /* 199618 */ GIR_MakeTempReg, /*TempRegID*//* 666(*/0x9A, 0x05/*)*/, /*TypeID*/GILLT_s64,
64455 /* 199622 */ GIR_BuildMI, /*InsnID*//* 667(*/0x9B, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64456 /* 199627 */ GIR_AddTempRegister, /*InsnID*//* 667(*/0x9B, 0x05/*)*/, /*TempRegID*//* 666(*/0x9A, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64457 /* 199634 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 667(*/0x9B, 0x05/*)*/,
64458 /* 199637 */ GIR_MakeTempReg, /*TempRegID*//* 665(*/0x99, 0x05/*)*/, /*TypeID*/GILLT_s64,
64459 /* 199641 */ GIR_BuildMI, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64460 /* 199646 */ GIR_AddTempRegister, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*TempRegID*//* 665(*/0x99, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64461 /* 199653 */ GIR_AddSimpleTempRegister, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*TempRegID*//* 666(*/0x9A, 0x05/*)*/,
64462 /* 199658 */ GIR_AddSimpleTempRegister, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*TempRegID*//* 667(*/0x9B, 0x05/*)*/,
64463 /* 199663 */ GIR_AddImm8, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Imm*/1,
64464 /* 199667 */ GIR_ConstrainOperandRC, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64465 /* 199673 */ GIR_ConstrainOperandRC, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64466 /* 199679 */ GIR_ConstrainOperandRC, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64467 /* 199685 */ GIR_MakeTempReg, /*TempRegID*//* 664(*/0x98, 0x05/*)*/, /*TypeID*/GILLT_s64,
64468 /* 199689 */ GIR_BuildMI, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64469 /* 199694 */ GIR_AddTempRegister, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*TempRegID*//* 664(*/0x98, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64470 /* 199701 */ GIR_AddSimpleTempRegister, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*TempRegID*//* 665(*/0x99, 0x05/*)*/,
64471 /* 199706 */ GIR_AddImm8, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*Imm*/32,
64472 /* 199710 */ GIR_AddImm8, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*Imm*/31,
64473 /* 199714 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 665(*/0x99, 0x05/*)*/,
64474 /* 199717 */ GIR_MakeTempReg, /*TempRegID*//* 663(*/0x97, 0x05/*)*/, /*TypeID*/GILLT_s64,
64475 /* 199721 */ GIR_BuildMI, /*InsnID*//* 664(*/0x98, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64476 /* 199726 */ GIR_AddTempRegister, /*InsnID*//* 664(*/0x98, 0x05/*)*/, /*TempRegID*//* 663(*/0x97, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64477 /* 199733 */ GIR_AddSimpleTempRegister, /*InsnID*//* 664(*/0x98, 0x05/*)*/, /*TempRegID*//* 664(*/0x98, 0x05/*)*/,
64478 /* 199738 */ GIR_AddImm, /*InsnID*//* 664(*/0x98, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
64479 /* 199749 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 664(*/0x98, 0x05/*)*/,
64480 /* 199752 */ GIR_MakeTempReg, /*TempRegID*//* 662(*/0x96, 0x05/*)*/, /*TypeID*/GILLT_s64,
64481 /* 199756 */ GIR_BuildMI, /*InsnID*//* 663(*/0x97, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64482 /* 199761 */ GIR_AddTempRegister, /*InsnID*//* 663(*/0x97, 0x05/*)*/, /*TempRegID*//* 662(*/0x96, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64483 /* 199768 */ GIR_AddSimpleTempRegister, /*InsnID*//* 663(*/0x97, 0x05/*)*/, /*TempRegID*//* 663(*/0x97, 0x05/*)*/,
64484 /* 199773 */ GIR_AddImm, /*InsnID*//* 663(*/0x97, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
64485 /* 199784 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 663(*/0x97, 0x05/*)*/,
64486 /* 199787 */ GIR_MakeTempReg, /*TempRegID*//* 661(*/0x95, 0x05/*)*/, /*TypeID*/GILLT_s64,
64487 /* 199791 */ GIR_BuildMI, /*InsnID*//* 662(*/0x96, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64488 /* 199796 */ GIR_AddTempRegister, /*InsnID*//* 662(*/0x96, 0x05/*)*/, /*TempRegID*//* 661(*/0x95, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64489 /* 199803 */ GIR_Copy, /*NewInsnID*//* 662(*/0x96, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64490 /* 199808 */ GIR_AddImm8, /*InsnID*//* 662(*/0x96, 0x05/*)*/, /*Imm*/1,
64491 /* 199812 */ GIR_AddImm8, /*InsnID*//* 662(*/0x96, 0x05/*)*/, /*Imm*/62,
64492 /* 199816 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 662(*/0x96, 0x05/*)*/,
64493 /* 199819 */ GIR_MakeTempReg, /*TempRegID*//* 660(*/0x94, 0x05/*)*/, /*TypeID*/GILLT_s64,
64494 /* 199823 */ GIR_BuildMI, /*InsnID*//* 661(*/0x95, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64495 /* 199828 */ GIR_AddTempRegister, /*InsnID*//* 661(*/0x95, 0x05/*)*/, /*TempRegID*//* 660(*/0x94, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64496 /* 199835 */ GIR_AddSimpleTempRegister, /*InsnID*//* 661(*/0x95, 0x05/*)*/, /*TempRegID*//* 661(*/0x95, 0x05/*)*/,
64497 /* 199840 */ GIR_AddSimpleTempRegister, /*InsnID*//* 661(*/0x95, 0x05/*)*/, /*TempRegID*//* 662(*/0x96, 0x05/*)*/,
64498 /* 199845 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 661(*/0x95, 0x05/*)*/,
64499 /* 199848 */ GIR_MakeTempReg, /*TempRegID*//* 659(*/0x93, 0x05/*)*/, /*TypeID*/GILLT_s32,
64500 /* 199852 */ GIR_BuildMI, /*InsnID*//* 660(*/0x94, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64501 /* 199857 */ GIR_AddTempRegister, /*InsnID*//* 660(*/0x94, 0x05/*)*/, /*TempRegID*//* 659(*/0x93, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64502 /* 199864 */ GIR_AddImm, /*InsnID*//* 660(*/0x94, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
64503 /* 199875 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 660(*/0x94, 0x05/*)*/,
64504 /* 199878 */ GIR_MakeTempReg, /*TempRegID*//* 658(*/0x92, 0x05/*)*/, /*TypeID*/GILLT_s32,
64505 /* 199882 */ GIR_BuildMI, /*InsnID*//* 659(*/0x93, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64506 /* 199887 */ GIR_AddTempRegister, /*InsnID*//* 659(*/0x93, 0x05/*)*/, /*TempRegID*//* 658(*/0x92, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64507 /* 199894 */ GIR_AddSimpleTempRegister, /*InsnID*//* 659(*/0x93, 0x05/*)*/, /*TempRegID*//* 659(*/0x93, 0x05/*)*/,
64508 /* 199899 */ GIR_AddImm, /*InsnID*//* 659(*/0x93, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
64509 /* 199910 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 659(*/0x93, 0x05/*)*/,
64510 /* 199913 */ GIR_MakeTempReg, /*TempRegID*//* 657(*/0x91, 0x05/*)*/, /*TypeID*/GILLT_s64,
64511 /* 199917 */ GIR_BuildMI, /*InsnID*//* 658(*/0x92, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64512 /* 199922 */ GIR_AddTempRegister, /*InsnID*//* 658(*/0x92, 0x05/*)*/, /*TempRegID*//* 657(*/0x91, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64513 /* 199929 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 658(*/0x92, 0x05/*)*/,
64514 /* 199932 */ GIR_MakeTempReg, /*TempRegID*//* 656(*/0x90, 0x05/*)*/, /*TypeID*/GILLT_s64,
64515 /* 199936 */ GIR_BuildMI, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64516 /* 199941 */ GIR_AddTempRegister, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*TempRegID*//* 656(*/0x90, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64517 /* 199948 */ GIR_AddSimpleTempRegister, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*TempRegID*//* 657(*/0x91, 0x05/*)*/,
64518 /* 199953 */ GIR_AddSimpleTempRegister, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*TempRegID*//* 658(*/0x92, 0x05/*)*/,
64519 /* 199958 */ GIR_AddImm8, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Imm*/1,
64520 /* 199962 */ GIR_ConstrainOperandRC, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64521 /* 199968 */ GIR_ConstrainOperandRC, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64522 /* 199974 */ GIR_ConstrainOperandRC, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64523 /* 199980 */ GIR_MakeTempReg, /*TempRegID*//* 655(*/0x8F, 0x05/*)*/, /*TypeID*/GILLT_s64,
64524 /* 199984 */ GIR_BuildMI, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64525 /* 199989 */ GIR_AddTempRegister, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*TempRegID*//* 655(*/0x8F, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64526 /* 199996 */ GIR_AddSimpleTempRegister, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*TempRegID*//* 656(*/0x90, 0x05/*)*/,
64527 /* 200001 */ GIR_AddImm8, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*Imm*/32,
64528 /* 200005 */ GIR_AddImm8, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*Imm*/31,
64529 /* 200009 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 656(*/0x90, 0x05/*)*/,
64530 /* 200012 */ GIR_MakeTempReg, /*TempRegID*//* 654(*/0x8E, 0x05/*)*/, /*TypeID*/GILLT_s64,
64531 /* 200016 */ GIR_BuildMI, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64532 /* 200021 */ GIR_AddTempRegister, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, /*TempRegID*//* 654(*/0x8E, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64533 /* 200028 */ GIR_AddSimpleTempRegister, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, /*TempRegID*//* 655(*/0x8F, 0x05/*)*/,
64534 /* 200033 */ GIR_AddImm, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
64535 /* 200044 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 655(*/0x8F, 0x05/*)*/,
64536 /* 200047 */ GIR_MakeTempReg, /*TempRegID*//* 653(*/0x8D, 0x05/*)*/, /*TypeID*/GILLT_s64,
64537 /* 200051 */ GIR_BuildMI, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64538 /* 200056 */ GIR_AddTempRegister, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, /*TempRegID*//* 653(*/0x8D, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64539 /* 200063 */ GIR_AddSimpleTempRegister, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, /*TempRegID*//* 654(*/0x8E, 0x05/*)*/,
64540 /* 200068 */ GIR_AddImm, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
64541 /* 200079 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 654(*/0x8E, 0x05/*)*/,
64542 /* 200082 */ GIR_MakeTempReg, /*TempRegID*//* 652(*/0x8C, 0x05/*)*/, /*TypeID*/GILLT_s64,
64543 /* 200086 */ GIR_BuildMI, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64544 /* 200091 */ GIR_AddTempRegister, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, /*TempRegID*//* 652(*/0x8C, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64545 /* 200098 */ GIR_Copy, /*NewInsnID*//* 653(*/0x8D, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64546 /* 200103 */ GIR_AddImm8, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, /*Imm*/63,
64547 /* 200107 */ GIR_AddImm8, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, /*Imm*/1,
64548 /* 200111 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 653(*/0x8D, 0x05/*)*/,
64549 /* 200114 */ GIR_MakeTempReg, /*TempRegID*//* 651(*/0x8B, 0x05/*)*/, /*TypeID*/GILLT_s64,
64550 /* 200118 */ GIR_BuildMI, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64551 /* 200123 */ GIR_AddTempRegister, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, /*TempRegID*//* 651(*/0x8B, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64552 /* 200130 */ GIR_AddSimpleTempRegister, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, /*TempRegID*//* 652(*/0x8C, 0x05/*)*/,
64553 /* 200135 */ GIR_AddSimpleTempRegister, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, /*TempRegID*//* 653(*/0x8D, 0x05/*)*/,
64554 /* 200140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 652(*/0x8C, 0x05/*)*/,
64555 /* 200143 */ GIR_MakeTempReg, /*TempRegID*//* 650(*/0x8A, 0x05/*)*/, /*TypeID*/GILLT_s64,
64556 /* 200147 */ GIR_BuildMI, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
64557 /* 200152 */ GIR_AddTempRegister, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, /*TempRegID*//* 650(*/0x8A, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64558 /* 200159 */ GIR_AddSimpleTempRegister, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, /*TempRegID*//* 651(*/0x8B, 0x05/*)*/,
64559 /* 200164 */ GIR_AddSimpleTempRegister, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, /*TempRegID*//* 660(*/0x94, 0x05/*)*/,
64560 /* 200169 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 651(*/0x8B, 0x05/*)*/,
64561 /* 200172 */ GIR_MakeTempReg, /*TempRegID*//* 649(*/0x89, 0x05/*)*/, /*TypeID*/GILLT_s64,
64562 /* 200176 */ GIR_BuildMI, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64563 /* 200181 */ GIR_AddTempRegister, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*TempRegID*//* 649(*/0x89, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64564 /* 200188 */ GIR_AddSimpleTempRegister, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*TempRegID*//* 650(*/0x8A, 0x05/*)*/,
64565 /* 200193 */ GIR_AddImm8, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*Imm*/2,
64566 /* 200197 */ GIR_AddImm8, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*Imm*/61,
64567 /* 200201 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 650(*/0x8A, 0x05/*)*/,
64568 /* 200204 */ GIR_MakeTempReg, /*TempRegID*//* 648(*/0x88, 0x05/*)*/, /*TypeID*/GILLT_s64,
64569 /* 200208 */ GIR_BuildMI, /*InsnID*//* 649(*/0x89, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64570 /* 200213 */ GIR_AddTempRegister, /*InsnID*//* 649(*/0x89, 0x05/*)*/, /*TempRegID*//* 648(*/0x88, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64571 /* 200220 */ GIR_AddSimpleTempRegister, /*InsnID*//* 649(*/0x89, 0x05/*)*/, /*TempRegID*//* 649(*/0x89, 0x05/*)*/,
64572 /* 200225 */ GIR_AddSimpleTempRegister, /*InsnID*//* 649(*/0x89, 0x05/*)*/, /*TempRegID*//* 669(*/0x9D, 0x05/*)*/,
64573 /* 200230 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 649(*/0x89, 0x05/*)*/,
64574 /* 200233 */ GIR_MakeTempReg, /*TempRegID*//* 647(*/0x87, 0x05/*)*/, /*TypeID*/GILLT_s32,
64575 /* 200237 */ GIR_BuildMI, /*InsnID*//* 648(*/0x88, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64576 /* 200242 */ GIR_AddTempRegister, /*InsnID*//* 648(*/0x88, 0x05/*)*/, /*TempRegID*//* 647(*/0x87, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64577 /* 200249 */ GIR_AddImm, /*InsnID*//* 648(*/0x88, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107),
64578 /* 200260 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 648(*/0x88, 0x05/*)*/,
64579 /* 200263 */ GIR_MakeTempReg, /*TempRegID*//* 646(*/0x86, 0x05/*)*/, /*TypeID*/GILLT_s32,
64580 /* 200267 */ GIR_BuildMI, /*InsnID*//* 647(*/0x87, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64581 /* 200272 */ GIR_AddTempRegister, /*InsnID*//* 647(*/0x87, 0x05/*)*/, /*TempRegID*//* 646(*/0x86, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64582 /* 200279 */ GIR_AddSimpleTempRegister, /*InsnID*//* 647(*/0x87, 0x05/*)*/, /*TempRegID*//* 647(*/0x87, 0x05/*)*/,
64583 /* 200284 */ GIR_AddImm, /*InsnID*//* 647(*/0x87, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107),
64584 /* 200295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 647(*/0x87, 0x05/*)*/,
64585 /* 200298 */ GIR_MakeTempReg, /*TempRegID*//* 645(*/0x85, 0x05/*)*/, /*TypeID*/GILLT_s64,
64586 /* 200302 */ GIR_BuildMI, /*InsnID*//* 646(*/0x86, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64587 /* 200307 */ GIR_AddTempRegister, /*InsnID*//* 646(*/0x86, 0x05/*)*/, /*TempRegID*//* 645(*/0x85, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64588 /* 200314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 646(*/0x86, 0x05/*)*/,
64589 /* 200317 */ GIR_MakeTempReg, /*TempRegID*//* 644(*/0x84, 0x05/*)*/, /*TypeID*/GILLT_s64,
64590 /* 200321 */ GIR_BuildMI, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64591 /* 200326 */ GIR_AddTempRegister, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*TempRegID*//* 644(*/0x84, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64592 /* 200333 */ GIR_AddSimpleTempRegister, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*TempRegID*//* 645(*/0x85, 0x05/*)*/,
64593 /* 200338 */ GIR_AddSimpleTempRegister, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*TempRegID*//* 646(*/0x86, 0x05/*)*/,
64594 /* 200343 */ GIR_AddImm8, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Imm*/1,
64595 /* 200347 */ GIR_ConstrainOperandRC, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64596 /* 200353 */ GIR_ConstrainOperandRC, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64597 /* 200359 */ GIR_ConstrainOperandRC, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64598 /* 200365 */ GIR_MakeTempReg, /*TempRegID*//* 643(*/0x83, 0x05/*)*/, /*TypeID*/GILLT_s64,
64599 /* 200369 */ GIR_BuildMI, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64600 /* 200374 */ GIR_AddTempRegister, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*TempRegID*//* 643(*/0x83, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64601 /* 200381 */ GIR_AddSimpleTempRegister, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*TempRegID*//* 644(*/0x84, 0x05/*)*/,
64602 /* 200386 */ GIR_AddImm8, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*Imm*/32,
64603 /* 200390 */ GIR_AddImm8, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*Imm*/31,
64604 /* 200394 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 644(*/0x84, 0x05/*)*/,
64605 /* 200397 */ GIR_MakeTempReg, /*TempRegID*//* 642(*/0x82, 0x05/*)*/, /*TypeID*/GILLT_s64,
64606 /* 200401 */ GIR_BuildMI, /*InsnID*//* 643(*/0x83, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64607 /* 200406 */ GIR_AddTempRegister, /*InsnID*//* 643(*/0x83, 0x05/*)*/, /*TempRegID*//* 642(*/0x82, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64608 /* 200413 */ GIR_AddSimpleTempRegister, /*InsnID*//* 643(*/0x83, 0x05/*)*/, /*TempRegID*//* 643(*/0x83, 0x05/*)*/,
64609 /* 200418 */ GIR_AddImm, /*InsnID*//* 643(*/0x83, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107),
64610 /* 200429 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 643(*/0x83, 0x05/*)*/,
64611 /* 200432 */ GIR_MakeTempReg, /*TempRegID*//* 641(*/0x81, 0x05/*)*/, /*TypeID*/GILLT_s64,
64612 /* 200436 */ GIR_BuildMI, /*InsnID*//* 642(*/0x82, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64613 /* 200441 */ GIR_AddTempRegister, /*InsnID*//* 642(*/0x82, 0x05/*)*/, /*TempRegID*//* 641(*/0x81, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64614 /* 200448 */ GIR_AddSimpleTempRegister, /*InsnID*//* 642(*/0x82, 0x05/*)*/, /*TempRegID*//* 642(*/0x82, 0x05/*)*/,
64615 /* 200453 */ GIR_AddImm, /*InsnID*//* 642(*/0x82, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107),
64616 /* 200464 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 642(*/0x82, 0x05/*)*/,
64617 /* 200467 */ GIR_MakeTempReg, /*TempRegID*//* 640(*/0x80, 0x05/*)*/, /*TypeID*/GILLT_s32,
64618 /* 200471 */ GIR_BuildMI, /*InsnID*//* 641(*/0x81, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64619 /* 200476 */ GIR_AddTempRegister, /*InsnID*//* 641(*/0x81, 0x05/*)*/, /*TempRegID*//* 640(*/0x80, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64620 /* 200483 */ GIR_AddImm, /*InsnID*//* 641(*/0x81, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
64621 /* 200494 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 641(*/0x81, 0x05/*)*/,
64622 /* 200497 */ GIR_MakeTempReg, /*TempRegID*//* 639(*/0xFF, 0x04/*)*/, /*TypeID*/GILLT_s32,
64623 /* 200501 */ GIR_BuildMI, /*InsnID*//* 640(*/0x80, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64624 /* 200506 */ GIR_AddTempRegister, /*InsnID*//* 640(*/0x80, 0x05/*)*/, /*TempRegID*//* 639(*/0xFF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64625 /* 200513 */ GIR_AddSimpleTempRegister, /*InsnID*//* 640(*/0x80, 0x05/*)*/, /*TempRegID*//* 640(*/0x80, 0x05/*)*/,
64626 /* 200518 */ GIR_AddImm, /*InsnID*//* 640(*/0x80, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
64627 /* 200529 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 640(*/0x80, 0x05/*)*/,
64628 /* 200532 */ GIR_MakeTempReg, /*TempRegID*//* 638(*/0xFE, 0x04/*)*/, /*TypeID*/GILLT_s64,
64629 /* 200536 */ GIR_BuildMI, /*InsnID*//* 639(*/0xFF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64630 /* 200541 */ GIR_AddTempRegister, /*InsnID*//* 639(*/0xFF, 0x04/*)*/, /*TempRegID*//* 638(*/0xFE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64631 /* 200548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 639(*/0xFF, 0x04/*)*/,
64632 /* 200551 */ GIR_MakeTempReg, /*TempRegID*//* 637(*/0xFD, 0x04/*)*/, /*TypeID*/GILLT_s64,
64633 /* 200555 */ GIR_BuildMI, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64634 /* 200560 */ GIR_AddTempRegister, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*TempRegID*//* 637(*/0xFD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64635 /* 200567 */ GIR_AddSimpleTempRegister, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*TempRegID*//* 638(*/0xFE, 0x04/*)*/,
64636 /* 200572 */ GIR_AddSimpleTempRegister, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*TempRegID*//* 639(*/0xFF, 0x04/*)*/,
64637 /* 200577 */ GIR_AddImm8, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Imm*/1,
64638 /* 200581 */ GIR_ConstrainOperandRC, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64639 /* 200587 */ GIR_ConstrainOperandRC, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64640 /* 200593 */ GIR_ConstrainOperandRC, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64641 /* 200599 */ GIR_MakeTempReg, /*TempRegID*//* 636(*/0xFC, 0x04/*)*/, /*TypeID*/GILLT_s64,
64642 /* 200603 */ GIR_BuildMI, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64643 /* 200608 */ GIR_AddTempRegister, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*TempRegID*//* 636(*/0xFC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64644 /* 200615 */ GIR_AddSimpleTempRegister, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*TempRegID*//* 637(*/0xFD, 0x04/*)*/,
64645 /* 200620 */ GIR_AddImm8, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*Imm*/32,
64646 /* 200624 */ GIR_AddImm8, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*Imm*/31,
64647 /* 200628 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 637(*/0xFD, 0x04/*)*/,
64648 /* 200631 */ GIR_MakeTempReg, /*TempRegID*//* 635(*/0xFB, 0x04/*)*/, /*TypeID*/GILLT_s64,
64649 /* 200635 */ GIR_BuildMI, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64650 /* 200640 */ GIR_AddTempRegister, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, /*TempRegID*//* 635(*/0xFB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64651 /* 200647 */ GIR_AddSimpleTempRegister, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, /*TempRegID*//* 636(*/0xFC, 0x04/*)*/,
64652 /* 200652 */ GIR_AddImm, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
64653 /* 200663 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 636(*/0xFC, 0x04/*)*/,
64654 /* 200666 */ GIR_MakeTempReg, /*TempRegID*//* 634(*/0xFA, 0x04/*)*/, /*TypeID*/GILLT_s64,
64655 /* 200670 */ GIR_BuildMI, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64656 /* 200675 */ GIR_AddTempRegister, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, /*TempRegID*//* 634(*/0xFA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64657 /* 200682 */ GIR_AddSimpleTempRegister, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, /*TempRegID*//* 635(*/0xFB, 0x04/*)*/,
64658 /* 200687 */ GIR_AddImm, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
64659 /* 200698 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 635(*/0xFB, 0x04/*)*/,
64660 /* 200701 */ GIR_MakeTempReg, /*TempRegID*//* 633(*/0xF9, 0x04/*)*/, /*TypeID*/GILLT_s64,
64661 /* 200705 */ GIR_BuildMI, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64662 /* 200710 */ GIR_AddTempRegister, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, /*TempRegID*//* 633(*/0xF9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64663 /* 200717 */ GIR_Copy, /*NewInsnID*//* 634(*/0xFA, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64664 /* 200722 */ GIR_AddImm8, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, /*Imm*/1,
64665 /* 200726 */ GIR_AddImm8, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, /*Imm*/62,
64666 /* 200730 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 634(*/0xFA, 0x04/*)*/,
64667 /* 200733 */ GIR_MakeTempReg, /*TempRegID*//* 632(*/0xF8, 0x04/*)*/, /*TypeID*/GILLT_s64,
64668 /* 200737 */ GIR_BuildMI, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64669 /* 200742 */ GIR_AddTempRegister, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, /*TempRegID*//* 632(*/0xF8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64670 /* 200749 */ GIR_AddSimpleTempRegister, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, /*TempRegID*//* 633(*/0xF9, 0x04/*)*/,
64671 /* 200754 */ GIR_AddSimpleTempRegister, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, /*TempRegID*//* 634(*/0xFA, 0x04/*)*/,
64672 /* 200759 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 633(*/0xF9, 0x04/*)*/,
64673 /* 200762 */ GIR_MakeTempReg, /*TempRegID*//* 631(*/0xF7, 0x04/*)*/, /*TypeID*/GILLT_s32,
64674 /* 200766 */ GIR_BuildMI, /*InsnID*//* 632(*/0xF8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64675 /* 200771 */ GIR_AddTempRegister, /*InsnID*//* 632(*/0xF8, 0x04/*)*/, /*TempRegID*//* 631(*/0xF7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64676 /* 200778 */ GIR_AddImm, /*InsnID*//* 632(*/0xF8, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
64677 /* 200789 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 632(*/0xF8, 0x04/*)*/,
64678 /* 200792 */ GIR_MakeTempReg, /*TempRegID*//* 630(*/0xF6, 0x04/*)*/, /*TypeID*/GILLT_s32,
64679 /* 200796 */ GIR_BuildMI, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64680 /* 200801 */ GIR_AddTempRegister, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, /*TempRegID*//* 630(*/0xF6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64681 /* 200808 */ GIR_AddSimpleTempRegister, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, /*TempRegID*//* 631(*/0xF7, 0x04/*)*/,
64682 /* 200813 */ GIR_AddImm, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
64683 /* 200824 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 631(*/0xF7, 0x04/*)*/,
64684 /* 200827 */ GIR_MakeTempReg, /*TempRegID*//* 629(*/0xF5, 0x04/*)*/, /*TypeID*/GILLT_s64,
64685 /* 200831 */ GIR_BuildMI, /*InsnID*//* 630(*/0xF6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64686 /* 200836 */ GIR_AddTempRegister, /*InsnID*//* 630(*/0xF6, 0x04/*)*/, /*TempRegID*//* 629(*/0xF5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64687 /* 200843 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 630(*/0xF6, 0x04/*)*/,
64688 /* 200846 */ GIR_MakeTempReg, /*TempRegID*//* 628(*/0xF4, 0x04/*)*/, /*TypeID*/GILLT_s64,
64689 /* 200850 */ GIR_BuildMI, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64690 /* 200855 */ GIR_AddTempRegister, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*TempRegID*//* 628(*/0xF4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64691 /* 200862 */ GIR_AddSimpleTempRegister, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*TempRegID*//* 629(*/0xF5, 0x04/*)*/,
64692 /* 200867 */ GIR_AddSimpleTempRegister, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*TempRegID*//* 630(*/0xF6, 0x04/*)*/,
64693 /* 200872 */ GIR_AddImm8, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Imm*/1,
64694 /* 200876 */ GIR_ConstrainOperandRC, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64695 /* 200882 */ GIR_ConstrainOperandRC, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64696 /* 200888 */ GIR_ConstrainOperandRC, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64697 /* 200894 */ GIR_MakeTempReg, /*TempRegID*//* 627(*/0xF3, 0x04/*)*/, /*TypeID*/GILLT_s64,
64698 /* 200898 */ GIR_BuildMI, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64699 /* 200903 */ GIR_AddTempRegister, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*TempRegID*//* 627(*/0xF3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64700 /* 200910 */ GIR_AddSimpleTempRegister, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*TempRegID*//* 628(*/0xF4, 0x04/*)*/,
64701 /* 200915 */ GIR_AddImm8, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*Imm*/32,
64702 /* 200919 */ GIR_AddImm8, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*Imm*/31,
64703 /* 200923 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 628(*/0xF4, 0x04/*)*/,
64704 /* 200926 */ GIR_MakeTempReg, /*TempRegID*//* 626(*/0xF2, 0x04/*)*/, /*TypeID*/GILLT_s64,
64705 /* 200930 */ GIR_BuildMI, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64706 /* 200935 */ GIR_AddTempRegister, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, /*TempRegID*//* 626(*/0xF2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64707 /* 200942 */ GIR_AddSimpleTempRegister, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, /*TempRegID*//* 627(*/0xF3, 0x04/*)*/,
64708 /* 200947 */ GIR_AddImm, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
64709 /* 200958 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 627(*/0xF3, 0x04/*)*/,
64710 /* 200961 */ GIR_MakeTempReg, /*TempRegID*//* 625(*/0xF1, 0x04/*)*/, /*TypeID*/GILLT_s64,
64711 /* 200965 */ GIR_BuildMI, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64712 /* 200970 */ GIR_AddTempRegister, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, /*TempRegID*//* 625(*/0xF1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64713 /* 200977 */ GIR_AddSimpleTempRegister, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, /*TempRegID*//* 626(*/0xF2, 0x04/*)*/,
64714 /* 200982 */ GIR_AddImm, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
64715 /* 200993 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 626(*/0xF2, 0x04/*)*/,
64716 /* 200996 */ GIR_MakeTempReg, /*TempRegID*//* 624(*/0xF0, 0x04/*)*/, /*TypeID*/GILLT_s64,
64717 /* 201000 */ GIR_BuildMI, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64718 /* 201005 */ GIR_AddTempRegister, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, /*TempRegID*//* 624(*/0xF0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64719 /* 201012 */ GIR_Copy, /*NewInsnID*//* 625(*/0xF1, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64720 /* 201017 */ GIR_AddImm8, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, /*Imm*/63,
64721 /* 201021 */ GIR_AddImm8, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, /*Imm*/1,
64722 /* 201025 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 625(*/0xF1, 0x04/*)*/,
64723 /* 201028 */ GIR_MakeTempReg, /*TempRegID*//* 623(*/0xEF, 0x04/*)*/, /*TypeID*/GILLT_s64,
64724 /* 201032 */ GIR_BuildMI, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64725 /* 201037 */ GIR_AddTempRegister, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, /*TempRegID*//* 623(*/0xEF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64726 /* 201044 */ GIR_AddSimpleTempRegister, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, /*TempRegID*//* 624(*/0xF0, 0x04/*)*/,
64727 /* 201049 */ GIR_AddSimpleTempRegister, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, /*TempRegID*//* 625(*/0xF1, 0x04/*)*/,
64728 /* 201054 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 624(*/0xF0, 0x04/*)*/,
64729 /* 201057 */ GIR_MakeTempReg, /*TempRegID*//* 622(*/0xEE, 0x04/*)*/, /*TypeID*/GILLT_s64,
64730 /* 201061 */ GIR_BuildMI, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
64731 /* 201066 */ GIR_AddTempRegister, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, /*TempRegID*//* 622(*/0xEE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64732 /* 201073 */ GIR_AddSimpleTempRegister, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, /*TempRegID*//* 623(*/0xEF, 0x04/*)*/,
64733 /* 201078 */ GIR_AddSimpleTempRegister, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, /*TempRegID*//* 632(*/0xF8, 0x04/*)*/,
64734 /* 201083 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 623(*/0xEF, 0x04/*)*/,
64735 /* 201086 */ GIR_MakeTempReg, /*TempRegID*//* 621(*/0xED, 0x04/*)*/, /*TypeID*/GILLT_s64,
64736 /* 201090 */ GIR_BuildMI, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64737 /* 201095 */ GIR_AddTempRegister, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*TempRegID*//* 621(*/0xED, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64738 /* 201102 */ GIR_AddSimpleTempRegister, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*TempRegID*//* 622(*/0xEE, 0x04/*)*/,
64739 /* 201107 */ GIR_AddImm8, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*Imm*/62,
64740 /* 201111 */ GIR_AddImm8, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*Imm*/2,
64741 /* 201115 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 622(*/0xEE, 0x04/*)*/,
64742 /* 201118 */ GIR_MakeTempReg, /*TempRegID*//* 620(*/0xEC, 0x04/*)*/, /*TypeID*/GILLT_s64,
64743 /* 201122 */ GIR_BuildMI, /*InsnID*//* 621(*/0xED, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64744 /* 201127 */ GIR_AddTempRegister, /*InsnID*//* 621(*/0xED, 0x04/*)*/, /*TempRegID*//* 620(*/0xEC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64745 /* 201134 */ GIR_AddSimpleTempRegister, /*InsnID*//* 621(*/0xED, 0x04/*)*/, /*TempRegID*//* 621(*/0xED, 0x04/*)*/,
64746 /* 201139 */ GIR_AddSimpleTempRegister, /*InsnID*//* 621(*/0xED, 0x04/*)*/, /*TempRegID*//* 641(*/0x81, 0x05/*)*/,
64747 /* 201144 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 621(*/0xED, 0x04/*)*/,
64748 /* 201147 */ GIR_MakeTempReg, /*TempRegID*//* 619(*/0xEB, 0x04/*)*/, /*TypeID*/GILLT_s64,
64749 /* 201151 */ GIR_BuildMI, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
64750 /* 201156 */ GIR_AddTempRegister, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, /*TempRegID*//* 619(*/0xEB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64751 /* 201163 */ GIR_AddSimpleTempRegister, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, /*TempRegID*//* 620(*/0xEC, 0x04/*)*/,
64752 /* 201168 */ GIR_AddSimpleTempRegister, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, /*TempRegID*//* 648(*/0x88, 0x05/*)*/,
64753 /* 201173 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 620(*/0xEC, 0x04/*)*/,
64754 /* 201176 */ GIR_MakeTempReg, /*TempRegID*//* 618(*/0xEA, 0x04/*)*/, /*TypeID*/GILLT_s64,
64755 /* 201180 */ GIR_BuildMI, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64756 /* 201185 */ GIR_AddTempRegister, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*TempRegID*//* 618(*/0xEA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64757 /* 201192 */ GIR_AddSimpleTempRegister, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*TempRegID*//* 619(*/0xEB, 0x04/*)*/,
64758 /* 201197 */ GIR_AddImm8, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*Imm*/4,
64759 /* 201201 */ GIR_AddImm8, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*Imm*/59,
64760 /* 201205 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 619(*/0xEB, 0x04/*)*/,
64761 /* 201208 */ GIR_MakeTempReg, /*TempRegID*//* 617(*/0xE9, 0x04/*)*/, /*TypeID*/GILLT_s64,
64762 /* 201212 */ GIR_BuildMI, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64763 /* 201217 */ GIR_AddTempRegister, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, /*TempRegID*//* 617(*/0xE9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64764 /* 201224 */ GIR_AddSimpleTempRegister, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, /*TempRegID*//* 618(*/0xEA, 0x04/*)*/,
64765 /* 201229 */ GIR_AddSimpleTempRegister, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, /*TempRegID*//* 676(*/0xA4, 0x05/*)*/,
64766 /* 201234 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 618(*/0xEA, 0x04/*)*/,
64767 /* 201237 */ GIR_MakeTempReg, /*TempRegID*//* 616(*/0xE8, 0x04/*)*/, /*TypeID*/GILLT_s32,
64768 /* 201241 */ GIR_BuildMI, /*InsnID*//* 617(*/0xE9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64769 /* 201246 */ GIR_AddTempRegister, /*InsnID*//* 617(*/0xE9, 0x04/*)*/, /*TempRegID*//* 616(*/0xE8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64770 /* 201253 */ GIR_AddImm, /*InsnID*//* 617(*/0xE9, 0x04/*)*/, /*Imm*/GIMT_Encode8(3855),
64771 /* 201264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 617(*/0xE9, 0x04/*)*/,
64772 /* 201267 */ GIR_MakeTempReg, /*TempRegID*//* 615(*/0xE7, 0x04/*)*/, /*TypeID*/GILLT_s32,
64773 /* 201271 */ GIR_BuildMI, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64774 /* 201276 */ GIR_AddTempRegister, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, /*TempRegID*//* 615(*/0xE7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64775 /* 201283 */ GIR_AddSimpleTempRegister, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, /*TempRegID*//* 616(*/0xE8, 0x04/*)*/,
64776 /* 201288 */ GIR_AddImm, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, /*Imm*/GIMT_Encode8(3855),
64777 /* 201299 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 616(*/0xE8, 0x04/*)*/,
64778 /* 201302 */ GIR_MakeTempReg, /*TempRegID*//* 614(*/0xE6, 0x04/*)*/, /*TypeID*/GILLT_s64,
64779 /* 201306 */ GIR_BuildMI, /*InsnID*//* 615(*/0xE7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64780 /* 201311 */ GIR_AddTempRegister, /*InsnID*//* 615(*/0xE7, 0x04/*)*/, /*TempRegID*//* 614(*/0xE6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64781 /* 201318 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 615(*/0xE7, 0x04/*)*/,
64782 /* 201321 */ GIR_MakeTempReg, /*TempRegID*//* 613(*/0xE5, 0x04/*)*/, /*TypeID*/GILLT_s64,
64783 /* 201325 */ GIR_BuildMI, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64784 /* 201330 */ GIR_AddTempRegister, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*TempRegID*//* 613(*/0xE5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64785 /* 201337 */ GIR_AddSimpleTempRegister, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*TempRegID*//* 614(*/0xE6, 0x04/*)*/,
64786 /* 201342 */ GIR_AddSimpleTempRegister, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*TempRegID*//* 615(*/0xE7, 0x04/*)*/,
64787 /* 201347 */ GIR_AddImm8, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Imm*/1,
64788 /* 201351 */ GIR_ConstrainOperandRC, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64789 /* 201357 */ GIR_ConstrainOperandRC, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64790 /* 201363 */ GIR_ConstrainOperandRC, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64791 /* 201369 */ GIR_MakeTempReg, /*TempRegID*//* 612(*/0xE4, 0x04/*)*/, /*TypeID*/GILLT_s64,
64792 /* 201373 */ GIR_BuildMI, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64793 /* 201378 */ GIR_AddTempRegister, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*TempRegID*//* 612(*/0xE4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64794 /* 201385 */ GIR_AddSimpleTempRegister, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*TempRegID*//* 613(*/0xE5, 0x04/*)*/,
64795 /* 201390 */ GIR_AddImm8, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*Imm*/32,
64796 /* 201394 */ GIR_AddImm8, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*Imm*/31,
64797 /* 201398 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 613(*/0xE5, 0x04/*)*/,
64798 /* 201401 */ GIR_MakeTempReg, /*TempRegID*//* 611(*/0xE3, 0x04/*)*/, /*TypeID*/GILLT_s64,
64799 /* 201405 */ GIR_BuildMI, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64800 /* 201410 */ GIR_AddTempRegister, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, /*TempRegID*//* 611(*/0xE3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64801 /* 201417 */ GIR_AddSimpleTempRegister, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, /*TempRegID*//* 612(*/0xE4, 0x04/*)*/,
64802 /* 201422 */ GIR_AddImm, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, /*Imm*/GIMT_Encode8(3855),
64803 /* 201433 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 612(*/0xE4, 0x04/*)*/,
64804 /* 201436 */ GIR_MakeTempReg, /*TempRegID*//* 610(*/0xE2, 0x04/*)*/, /*TypeID*/GILLT_s64,
64805 /* 201440 */ GIR_BuildMI, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64806 /* 201445 */ GIR_AddTempRegister, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, /*TempRegID*//* 610(*/0xE2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64807 /* 201452 */ GIR_AddSimpleTempRegister, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, /*TempRegID*//* 611(*/0xE3, 0x04/*)*/,
64808 /* 201457 */ GIR_AddImm, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, /*Imm*/GIMT_Encode8(3855),
64809 /* 201468 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 611(*/0xE3, 0x04/*)*/,
64810 /* 201471 */ GIR_MakeTempReg, /*TempRegID*//* 609(*/0xE1, 0x04/*)*/, /*TypeID*/GILLT_s32,
64811 /* 201475 */ GIR_BuildMI, /*InsnID*//* 610(*/0xE2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64812 /* 201480 */ GIR_AddTempRegister, /*InsnID*//* 610(*/0xE2, 0x04/*)*/, /*TempRegID*//* 609(*/0xE1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64813 /* 201487 */ GIR_AddImm, /*InsnID*//* 610(*/0xE2, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428),
64814 /* 201498 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 610(*/0xE2, 0x04/*)*/,
64815 /* 201501 */ GIR_MakeTempReg, /*TempRegID*//* 608(*/0xE0, 0x04/*)*/, /*TypeID*/GILLT_s32,
64816 /* 201505 */ GIR_BuildMI, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64817 /* 201510 */ GIR_AddTempRegister, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, /*TempRegID*//* 608(*/0xE0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64818 /* 201517 */ GIR_AddSimpleTempRegister, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, /*TempRegID*//* 609(*/0xE1, 0x04/*)*/,
64819 /* 201522 */ GIR_AddImm, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428),
64820 /* 201533 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 609(*/0xE1, 0x04/*)*/,
64821 /* 201536 */ GIR_MakeTempReg, /*TempRegID*//* 607(*/0xDF, 0x04/*)*/, /*TypeID*/GILLT_s64,
64822 /* 201540 */ GIR_BuildMI, /*InsnID*//* 608(*/0xE0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64823 /* 201545 */ GIR_AddTempRegister, /*InsnID*//* 608(*/0xE0, 0x04/*)*/, /*TempRegID*//* 607(*/0xDF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64824 /* 201552 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 608(*/0xE0, 0x04/*)*/,
64825 /* 201555 */ GIR_MakeTempReg, /*TempRegID*//* 606(*/0xDE, 0x04/*)*/, /*TypeID*/GILLT_s64,
64826 /* 201559 */ GIR_BuildMI, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64827 /* 201564 */ GIR_AddTempRegister, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*TempRegID*//* 606(*/0xDE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64828 /* 201571 */ GIR_AddSimpleTempRegister, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*TempRegID*//* 607(*/0xDF, 0x04/*)*/,
64829 /* 201576 */ GIR_AddSimpleTempRegister, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*TempRegID*//* 608(*/0xE0, 0x04/*)*/,
64830 /* 201581 */ GIR_AddImm8, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Imm*/1,
64831 /* 201585 */ GIR_ConstrainOperandRC, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64832 /* 201591 */ GIR_ConstrainOperandRC, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64833 /* 201597 */ GIR_ConstrainOperandRC, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64834 /* 201603 */ GIR_MakeTempReg, /*TempRegID*//* 605(*/0xDD, 0x04/*)*/, /*TypeID*/GILLT_s64,
64835 /* 201607 */ GIR_BuildMI, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64836 /* 201612 */ GIR_AddTempRegister, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*TempRegID*//* 605(*/0xDD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64837 /* 201619 */ GIR_AddSimpleTempRegister, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*TempRegID*//* 606(*/0xDE, 0x04/*)*/,
64838 /* 201624 */ GIR_AddImm8, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*Imm*/32,
64839 /* 201628 */ GIR_AddImm8, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*Imm*/31,
64840 /* 201632 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 606(*/0xDE, 0x04/*)*/,
64841 /* 201635 */ GIR_MakeTempReg, /*TempRegID*//* 604(*/0xDC, 0x04/*)*/, /*TypeID*/GILLT_s64,
64842 /* 201639 */ GIR_BuildMI, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64843 /* 201644 */ GIR_AddTempRegister, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, /*TempRegID*//* 604(*/0xDC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64844 /* 201651 */ GIR_AddSimpleTempRegister, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, /*TempRegID*//* 605(*/0xDD, 0x04/*)*/,
64845 /* 201656 */ GIR_AddImm, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428),
64846 /* 201667 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 605(*/0xDD, 0x04/*)*/,
64847 /* 201670 */ GIR_MakeTempReg, /*TempRegID*//* 603(*/0xDB, 0x04/*)*/, /*TypeID*/GILLT_s64,
64848 /* 201674 */ GIR_BuildMI, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64849 /* 201679 */ GIR_AddTempRegister, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, /*TempRegID*//* 603(*/0xDB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64850 /* 201686 */ GIR_AddSimpleTempRegister, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, /*TempRegID*//* 604(*/0xDC, 0x04/*)*/,
64851 /* 201691 */ GIR_AddImm, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428),
64852 /* 201702 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 604(*/0xDC, 0x04/*)*/,
64853 /* 201705 */ GIR_MakeTempReg, /*TempRegID*//* 602(*/0xDA, 0x04/*)*/, /*TypeID*/GILLT_s32,
64854 /* 201709 */ GIR_BuildMI, /*InsnID*//* 603(*/0xDB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64855 /* 201714 */ GIR_AddTempRegister, /*InsnID*//* 603(*/0xDB, 0x04/*)*/, /*TempRegID*//* 602(*/0xDA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64856 /* 201721 */ GIR_AddImm, /*InsnID*//* 603(*/0xDB, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
64857 /* 201732 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 603(*/0xDB, 0x04/*)*/,
64858 /* 201735 */ GIR_MakeTempReg, /*TempRegID*//* 601(*/0xD9, 0x04/*)*/, /*TypeID*/GILLT_s32,
64859 /* 201739 */ GIR_BuildMI, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64860 /* 201744 */ GIR_AddTempRegister, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, /*TempRegID*//* 601(*/0xD9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64861 /* 201751 */ GIR_AddSimpleTempRegister, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, /*TempRegID*//* 602(*/0xDA, 0x04/*)*/,
64862 /* 201756 */ GIR_AddImm, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
64863 /* 201767 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 602(*/0xDA, 0x04/*)*/,
64864 /* 201770 */ GIR_MakeTempReg, /*TempRegID*//* 600(*/0xD8, 0x04/*)*/, /*TypeID*/GILLT_s64,
64865 /* 201774 */ GIR_BuildMI, /*InsnID*//* 601(*/0xD9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64866 /* 201779 */ GIR_AddTempRegister, /*InsnID*//* 601(*/0xD9, 0x04/*)*/, /*TempRegID*//* 600(*/0xD8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64867 /* 201786 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 601(*/0xD9, 0x04/*)*/,
64868 /* 201789 */ GIR_MakeTempReg, /*TempRegID*//* 599(*/0xD7, 0x04/*)*/, /*TypeID*/GILLT_s64,
64869 /* 201793 */ GIR_BuildMI, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64870 /* 201798 */ GIR_AddTempRegister, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*TempRegID*//* 599(*/0xD7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64871 /* 201805 */ GIR_AddSimpleTempRegister, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*TempRegID*//* 600(*/0xD8, 0x04/*)*/,
64872 /* 201810 */ GIR_AddSimpleTempRegister, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*TempRegID*//* 601(*/0xD9, 0x04/*)*/,
64873 /* 201815 */ GIR_AddImm8, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Imm*/1,
64874 /* 201819 */ GIR_ConstrainOperandRC, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64875 /* 201825 */ GIR_ConstrainOperandRC, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64876 /* 201831 */ GIR_ConstrainOperandRC, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64877 /* 201837 */ GIR_MakeTempReg, /*TempRegID*//* 598(*/0xD6, 0x04/*)*/, /*TypeID*/GILLT_s64,
64878 /* 201841 */ GIR_BuildMI, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64879 /* 201846 */ GIR_AddTempRegister, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*TempRegID*//* 598(*/0xD6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64880 /* 201853 */ GIR_AddSimpleTempRegister, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*TempRegID*//* 599(*/0xD7, 0x04/*)*/,
64881 /* 201858 */ GIR_AddImm8, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*Imm*/32,
64882 /* 201862 */ GIR_AddImm8, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*Imm*/31,
64883 /* 201866 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 599(*/0xD7, 0x04/*)*/,
64884 /* 201869 */ GIR_MakeTempReg, /*TempRegID*//* 597(*/0xD5, 0x04/*)*/, /*TypeID*/GILLT_s64,
64885 /* 201873 */ GIR_BuildMI, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64886 /* 201878 */ GIR_AddTempRegister, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, /*TempRegID*//* 597(*/0xD5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64887 /* 201885 */ GIR_AddSimpleTempRegister, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, /*TempRegID*//* 598(*/0xD6, 0x04/*)*/,
64888 /* 201890 */ GIR_AddImm, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
64889 /* 201901 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 598(*/0xD6, 0x04/*)*/,
64890 /* 201904 */ GIR_MakeTempReg, /*TempRegID*//* 596(*/0xD4, 0x04/*)*/, /*TypeID*/GILLT_s64,
64891 /* 201908 */ GIR_BuildMI, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64892 /* 201913 */ GIR_AddTempRegister, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, /*TempRegID*//* 596(*/0xD4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64893 /* 201920 */ GIR_AddSimpleTempRegister, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, /*TempRegID*//* 597(*/0xD5, 0x04/*)*/,
64894 /* 201925 */ GIR_AddImm, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
64895 /* 201936 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 597(*/0xD5, 0x04/*)*/,
64896 /* 201939 */ GIR_MakeTempReg, /*TempRegID*//* 595(*/0xD3, 0x04/*)*/, /*TypeID*/GILLT_s64,
64897 /* 201943 */ GIR_BuildMI, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64898 /* 201948 */ GIR_AddTempRegister, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, /*TempRegID*//* 595(*/0xD3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64899 /* 201955 */ GIR_Copy, /*NewInsnID*//* 596(*/0xD4, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64900 /* 201960 */ GIR_AddImm8, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, /*Imm*/1,
64901 /* 201964 */ GIR_AddImm8, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, /*Imm*/62,
64902 /* 201968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 596(*/0xD4, 0x04/*)*/,
64903 /* 201971 */ GIR_MakeTempReg, /*TempRegID*//* 594(*/0xD2, 0x04/*)*/, /*TypeID*/GILLT_s64,
64904 /* 201975 */ GIR_BuildMI, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64905 /* 201980 */ GIR_AddTempRegister, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, /*TempRegID*//* 594(*/0xD2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64906 /* 201987 */ GIR_AddSimpleTempRegister, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, /*TempRegID*//* 595(*/0xD3, 0x04/*)*/,
64907 /* 201992 */ GIR_AddSimpleTempRegister, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, /*TempRegID*//* 596(*/0xD4, 0x04/*)*/,
64908 /* 201997 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 595(*/0xD3, 0x04/*)*/,
64909 /* 202000 */ GIR_MakeTempReg, /*TempRegID*//* 593(*/0xD1, 0x04/*)*/, /*TypeID*/GILLT_s32,
64910 /* 202004 */ GIR_BuildMI, /*InsnID*//* 594(*/0xD2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64911 /* 202009 */ GIR_AddTempRegister, /*InsnID*//* 594(*/0xD2, 0x04/*)*/, /*TempRegID*//* 593(*/0xD1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64912 /* 202016 */ GIR_AddImm, /*InsnID*//* 594(*/0xD2, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
64913 /* 202027 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 594(*/0xD2, 0x04/*)*/,
64914 /* 202030 */ GIR_MakeTempReg, /*TempRegID*//* 592(*/0xD0, 0x04/*)*/, /*TypeID*/GILLT_s32,
64915 /* 202034 */ GIR_BuildMI, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64916 /* 202039 */ GIR_AddTempRegister, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, /*TempRegID*//* 592(*/0xD0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64917 /* 202046 */ GIR_AddSimpleTempRegister, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, /*TempRegID*//* 593(*/0xD1, 0x04/*)*/,
64918 /* 202051 */ GIR_AddImm, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
64919 /* 202062 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 593(*/0xD1, 0x04/*)*/,
64920 /* 202065 */ GIR_MakeTempReg, /*TempRegID*//* 591(*/0xCF, 0x04/*)*/, /*TypeID*/GILLT_s64,
64921 /* 202069 */ GIR_BuildMI, /*InsnID*//* 592(*/0xD0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64922 /* 202074 */ GIR_AddTempRegister, /*InsnID*//* 592(*/0xD0, 0x04/*)*/, /*TempRegID*//* 591(*/0xCF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64923 /* 202081 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 592(*/0xD0, 0x04/*)*/,
64924 /* 202084 */ GIR_MakeTempReg, /*TempRegID*//* 590(*/0xCE, 0x04/*)*/, /*TypeID*/GILLT_s64,
64925 /* 202088 */ GIR_BuildMI, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
64926 /* 202093 */ GIR_AddTempRegister, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*TempRegID*//* 590(*/0xCE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64927 /* 202100 */ GIR_AddSimpleTempRegister, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*TempRegID*//* 591(*/0xCF, 0x04/*)*/,
64928 /* 202105 */ GIR_AddSimpleTempRegister, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*TempRegID*//* 592(*/0xD0, 0x04/*)*/,
64929 /* 202110 */ GIR_AddImm8, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Imm*/1,
64930 /* 202114 */ GIR_ConstrainOperandRC, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
64931 /* 202120 */ GIR_ConstrainOperandRC, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
64932 /* 202126 */ GIR_ConstrainOperandRC, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
64933 /* 202132 */ GIR_MakeTempReg, /*TempRegID*//* 589(*/0xCD, 0x04/*)*/, /*TypeID*/GILLT_s64,
64934 /* 202136 */ GIR_BuildMI, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64935 /* 202141 */ GIR_AddTempRegister, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*TempRegID*//* 589(*/0xCD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64936 /* 202148 */ GIR_AddSimpleTempRegister, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*TempRegID*//* 590(*/0xCE, 0x04/*)*/,
64937 /* 202153 */ GIR_AddImm8, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*Imm*/32,
64938 /* 202157 */ GIR_AddImm8, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*Imm*/31,
64939 /* 202161 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 590(*/0xCE, 0x04/*)*/,
64940 /* 202164 */ GIR_MakeTempReg, /*TempRegID*//* 588(*/0xCC, 0x04/*)*/, /*TypeID*/GILLT_s64,
64941 /* 202168 */ GIR_BuildMI, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
64942 /* 202173 */ GIR_AddTempRegister, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, /*TempRegID*//* 588(*/0xCC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64943 /* 202180 */ GIR_AddSimpleTempRegister, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, /*TempRegID*//* 589(*/0xCD, 0x04/*)*/,
64944 /* 202185 */ GIR_AddImm, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
64945 /* 202196 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 589(*/0xCD, 0x04/*)*/,
64946 /* 202199 */ GIR_MakeTempReg, /*TempRegID*//* 587(*/0xCB, 0x04/*)*/, /*TypeID*/GILLT_s64,
64947 /* 202203 */ GIR_BuildMI, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
64948 /* 202208 */ GIR_AddTempRegister, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, /*TempRegID*//* 587(*/0xCB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64949 /* 202215 */ GIR_AddSimpleTempRegister, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, /*TempRegID*//* 588(*/0xCC, 0x04/*)*/,
64950 /* 202220 */ GIR_AddImm, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
64951 /* 202231 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 588(*/0xCC, 0x04/*)*/,
64952 /* 202234 */ GIR_MakeTempReg, /*TempRegID*//* 586(*/0xCA, 0x04/*)*/, /*TypeID*/GILLT_s64,
64953 /* 202238 */ GIR_BuildMI, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
64954 /* 202243 */ GIR_AddTempRegister, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, /*TempRegID*//* 586(*/0xCA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64955 /* 202250 */ GIR_Copy, /*NewInsnID*//* 587(*/0xCB, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
64956 /* 202255 */ GIR_AddImm8, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, /*Imm*/63,
64957 /* 202259 */ GIR_AddImm8, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, /*Imm*/1,
64958 /* 202263 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 587(*/0xCB, 0x04/*)*/,
64959 /* 202266 */ GIR_MakeTempReg, /*TempRegID*//* 585(*/0xC9, 0x04/*)*/, /*TypeID*/GILLT_s64,
64960 /* 202270 */ GIR_BuildMI, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64961 /* 202275 */ GIR_AddTempRegister, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, /*TempRegID*//* 585(*/0xC9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64962 /* 202282 */ GIR_AddSimpleTempRegister, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, /*TempRegID*//* 586(*/0xCA, 0x04/*)*/,
64963 /* 202287 */ GIR_AddSimpleTempRegister, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, /*TempRegID*//* 587(*/0xCB, 0x04/*)*/,
64964 /* 202292 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 586(*/0xCA, 0x04/*)*/,
64965 /* 202295 */ GIR_MakeTempReg, /*TempRegID*//* 584(*/0xC8, 0x04/*)*/, /*TypeID*/GILLT_s64,
64966 /* 202299 */ GIR_BuildMI, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
64967 /* 202304 */ GIR_AddTempRegister, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, /*TempRegID*//* 584(*/0xC8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64968 /* 202311 */ GIR_AddSimpleTempRegister, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, /*TempRegID*//* 585(*/0xC9, 0x04/*)*/,
64969 /* 202316 */ GIR_AddSimpleTempRegister, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, /*TempRegID*//* 594(*/0xD2, 0x04/*)*/,
64970 /* 202321 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 585(*/0xC9, 0x04/*)*/,
64971 /* 202324 */ GIR_MakeTempReg, /*TempRegID*//* 583(*/0xC7, 0x04/*)*/, /*TypeID*/GILLT_s64,
64972 /* 202328 */ GIR_BuildMI, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
64973 /* 202333 */ GIR_AddTempRegister, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*TempRegID*//* 583(*/0xC7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64974 /* 202340 */ GIR_AddSimpleTempRegister, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*TempRegID*//* 584(*/0xC8, 0x04/*)*/,
64975 /* 202345 */ GIR_AddImm8, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*Imm*/2,
64976 /* 202349 */ GIR_AddImm8, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*Imm*/61,
64977 /* 202353 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 584(*/0xC8, 0x04/*)*/,
64978 /* 202356 */ GIR_MakeTempReg, /*TempRegID*//* 582(*/0xC6, 0x04/*)*/, /*TypeID*/GILLT_s64,
64979 /* 202360 */ GIR_BuildMI, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
64980 /* 202365 */ GIR_AddTempRegister, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, /*TempRegID*//* 582(*/0xC6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64981 /* 202372 */ GIR_AddSimpleTempRegister, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, /*TempRegID*//* 583(*/0xC7, 0x04/*)*/,
64982 /* 202377 */ GIR_AddSimpleTempRegister, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, /*TempRegID*//* 603(*/0xDB, 0x04/*)*/,
64983 /* 202382 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 583(*/0xC7, 0x04/*)*/,
64984 /* 202385 */ GIR_MakeTempReg, /*TempRegID*//* 581(*/0xC5, 0x04/*)*/, /*TypeID*/GILLT_s32,
64985 /* 202389 */ GIR_BuildMI, /*InsnID*//* 582(*/0xC6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
64986 /* 202394 */ GIR_AddTempRegister, /*InsnID*//* 582(*/0xC6, 0x04/*)*/, /*TempRegID*//* 581(*/0xC5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64987 /* 202401 */ GIR_AddImm, /*InsnID*//* 582(*/0xC6, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107),
64988 /* 202412 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 582(*/0xC6, 0x04/*)*/,
64989 /* 202415 */ GIR_MakeTempReg, /*TempRegID*//* 580(*/0xC4, 0x04/*)*/, /*TypeID*/GILLT_s32,
64990 /* 202419 */ GIR_BuildMI, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
64991 /* 202424 */ GIR_AddTempRegister, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, /*TempRegID*//* 580(*/0xC4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64992 /* 202431 */ GIR_AddSimpleTempRegister, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, /*TempRegID*//* 581(*/0xC5, 0x04/*)*/,
64993 /* 202436 */ GIR_AddImm, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107),
64994 /* 202447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 581(*/0xC5, 0x04/*)*/,
64995 /* 202450 */ GIR_MakeTempReg, /*TempRegID*//* 579(*/0xC3, 0x04/*)*/, /*TypeID*/GILLT_s64,
64996 /* 202454 */ GIR_BuildMI, /*InsnID*//* 580(*/0xC4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
64997 /* 202459 */ GIR_AddTempRegister, /*InsnID*//* 580(*/0xC4, 0x04/*)*/, /*TempRegID*//* 579(*/0xC3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
64998 /* 202466 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 580(*/0xC4, 0x04/*)*/,
64999 /* 202469 */ GIR_MakeTempReg, /*TempRegID*//* 578(*/0xC2, 0x04/*)*/, /*TypeID*/GILLT_s64,
65000 /* 202473 */ GIR_BuildMI, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65001 /* 202478 */ GIR_AddTempRegister, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*TempRegID*//* 578(*/0xC2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65002 /* 202485 */ GIR_AddSimpleTempRegister, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*TempRegID*//* 579(*/0xC3, 0x04/*)*/,
65003 /* 202490 */ GIR_AddSimpleTempRegister, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*TempRegID*//* 580(*/0xC4, 0x04/*)*/,
65004 /* 202495 */ GIR_AddImm8, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Imm*/1,
65005 /* 202499 */ GIR_ConstrainOperandRC, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65006 /* 202505 */ GIR_ConstrainOperandRC, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65007 /* 202511 */ GIR_ConstrainOperandRC, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65008 /* 202517 */ GIR_MakeTempReg, /*TempRegID*//* 577(*/0xC1, 0x04/*)*/, /*TypeID*/GILLT_s64,
65009 /* 202521 */ GIR_BuildMI, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65010 /* 202526 */ GIR_AddTempRegister, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*TempRegID*//* 577(*/0xC1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65011 /* 202533 */ GIR_AddSimpleTempRegister, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*TempRegID*//* 578(*/0xC2, 0x04/*)*/,
65012 /* 202538 */ GIR_AddImm8, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*Imm*/32,
65013 /* 202542 */ GIR_AddImm8, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*Imm*/31,
65014 /* 202546 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 578(*/0xC2, 0x04/*)*/,
65015 /* 202549 */ GIR_MakeTempReg, /*TempRegID*//* 576(*/0xC0, 0x04/*)*/, /*TypeID*/GILLT_s64,
65016 /* 202553 */ GIR_BuildMI, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65017 /* 202558 */ GIR_AddTempRegister, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, /*TempRegID*//* 576(*/0xC0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65018 /* 202565 */ GIR_AddSimpleTempRegister, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, /*TempRegID*//* 577(*/0xC1, 0x04/*)*/,
65019 /* 202570 */ GIR_AddImm, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107),
65020 /* 202581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 577(*/0xC1, 0x04/*)*/,
65021 /* 202584 */ GIR_MakeTempReg, /*TempRegID*//* 575(*/0xBF, 0x04/*)*/, /*TypeID*/GILLT_s64,
65022 /* 202588 */ GIR_BuildMI, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65023 /* 202593 */ GIR_AddTempRegister, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, /*TempRegID*//* 575(*/0xBF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65024 /* 202600 */ GIR_AddSimpleTempRegister, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, /*TempRegID*//* 576(*/0xC0, 0x04/*)*/,
65025 /* 202605 */ GIR_AddImm, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107),
65026 /* 202616 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 576(*/0xC0, 0x04/*)*/,
65027 /* 202619 */ GIR_MakeTempReg, /*TempRegID*//* 574(*/0xBE, 0x04/*)*/, /*TypeID*/GILLT_s32,
65028 /* 202623 */ GIR_BuildMI, /*InsnID*//* 575(*/0xBF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65029 /* 202628 */ GIR_AddTempRegister, /*InsnID*//* 575(*/0xBF, 0x04/*)*/, /*TempRegID*//* 574(*/0xBE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65030 /* 202635 */ GIR_AddImm, /*InsnID*//* 575(*/0xBF, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
65031 /* 202646 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 575(*/0xBF, 0x04/*)*/,
65032 /* 202649 */ GIR_MakeTempReg, /*TempRegID*//* 573(*/0xBD, 0x04/*)*/, /*TypeID*/GILLT_s32,
65033 /* 202653 */ GIR_BuildMI, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65034 /* 202658 */ GIR_AddTempRegister, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, /*TempRegID*//* 573(*/0xBD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65035 /* 202665 */ GIR_AddSimpleTempRegister, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, /*TempRegID*//* 574(*/0xBE, 0x04/*)*/,
65036 /* 202670 */ GIR_AddImm, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
65037 /* 202681 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 574(*/0xBE, 0x04/*)*/,
65038 /* 202684 */ GIR_MakeTempReg, /*TempRegID*//* 572(*/0xBC, 0x04/*)*/, /*TypeID*/GILLT_s64,
65039 /* 202688 */ GIR_BuildMI, /*InsnID*//* 573(*/0xBD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65040 /* 202693 */ GIR_AddTempRegister, /*InsnID*//* 573(*/0xBD, 0x04/*)*/, /*TempRegID*//* 572(*/0xBC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65041 /* 202700 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 573(*/0xBD, 0x04/*)*/,
65042 /* 202703 */ GIR_MakeTempReg, /*TempRegID*//* 571(*/0xBB, 0x04/*)*/, /*TypeID*/GILLT_s64,
65043 /* 202707 */ GIR_BuildMI, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65044 /* 202712 */ GIR_AddTempRegister, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*TempRegID*//* 571(*/0xBB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65045 /* 202719 */ GIR_AddSimpleTempRegister, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*TempRegID*//* 572(*/0xBC, 0x04/*)*/,
65046 /* 202724 */ GIR_AddSimpleTempRegister, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*TempRegID*//* 573(*/0xBD, 0x04/*)*/,
65047 /* 202729 */ GIR_AddImm8, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Imm*/1,
65048 /* 202733 */ GIR_ConstrainOperandRC, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65049 /* 202739 */ GIR_ConstrainOperandRC, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65050 /* 202745 */ GIR_ConstrainOperandRC, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65051 /* 202751 */ GIR_MakeTempReg, /*TempRegID*//* 570(*/0xBA, 0x04/*)*/, /*TypeID*/GILLT_s64,
65052 /* 202755 */ GIR_BuildMI, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65053 /* 202760 */ GIR_AddTempRegister, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*TempRegID*//* 570(*/0xBA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65054 /* 202767 */ GIR_AddSimpleTempRegister, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*TempRegID*//* 571(*/0xBB, 0x04/*)*/,
65055 /* 202772 */ GIR_AddImm8, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*Imm*/32,
65056 /* 202776 */ GIR_AddImm8, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*Imm*/31,
65057 /* 202780 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 571(*/0xBB, 0x04/*)*/,
65058 /* 202783 */ GIR_MakeTempReg, /*TempRegID*//* 569(*/0xB9, 0x04/*)*/, /*TypeID*/GILLT_s64,
65059 /* 202787 */ GIR_BuildMI, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65060 /* 202792 */ GIR_AddTempRegister, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, /*TempRegID*//* 569(*/0xB9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65061 /* 202799 */ GIR_AddSimpleTempRegister, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, /*TempRegID*//* 570(*/0xBA, 0x04/*)*/,
65062 /* 202804 */ GIR_AddImm, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
65063 /* 202815 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 570(*/0xBA, 0x04/*)*/,
65064 /* 202818 */ GIR_MakeTempReg, /*TempRegID*//* 568(*/0xB8, 0x04/*)*/, /*TypeID*/GILLT_s64,
65065 /* 202822 */ GIR_BuildMI, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65066 /* 202827 */ GIR_AddTempRegister, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, /*TempRegID*//* 568(*/0xB8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65067 /* 202834 */ GIR_AddSimpleTempRegister, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, /*TempRegID*//* 569(*/0xB9, 0x04/*)*/,
65068 /* 202839 */ GIR_AddImm, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690),
65069 /* 202850 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 569(*/0xB9, 0x04/*)*/,
65070 /* 202853 */ GIR_MakeTempReg, /*TempRegID*//* 567(*/0xB7, 0x04/*)*/, /*TypeID*/GILLT_s64,
65071 /* 202857 */ GIR_BuildMI, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65072 /* 202862 */ GIR_AddTempRegister, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, /*TempRegID*//* 567(*/0xB7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65073 /* 202869 */ GIR_Copy, /*NewInsnID*//* 568(*/0xB8, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65074 /* 202874 */ GIR_AddImm8, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, /*Imm*/1,
65075 /* 202878 */ GIR_AddImm8, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, /*Imm*/62,
65076 /* 202882 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 568(*/0xB8, 0x04/*)*/,
65077 /* 202885 */ GIR_MakeTempReg, /*TempRegID*//* 566(*/0xB6, 0x04/*)*/, /*TypeID*/GILLT_s64,
65078 /* 202889 */ GIR_BuildMI, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65079 /* 202894 */ GIR_AddTempRegister, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, /*TempRegID*//* 566(*/0xB6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65080 /* 202901 */ GIR_AddSimpleTempRegister, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, /*TempRegID*//* 567(*/0xB7, 0x04/*)*/,
65081 /* 202906 */ GIR_AddSimpleTempRegister, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, /*TempRegID*//* 568(*/0xB8, 0x04/*)*/,
65082 /* 202911 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 567(*/0xB7, 0x04/*)*/,
65083 /* 202914 */ GIR_MakeTempReg, /*TempRegID*//* 565(*/0xB5, 0x04/*)*/, /*TypeID*/GILLT_s32,
65084 /* 202918 */ GIR_BuildMI, /*InsnID*//* 566(*/0xB6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65085 /* 202923 */ GIR_AddTempRegister, /*InsnID*//* 566(*/0xB6, 0x04/*)*/, /*TempRegID*//* 565(*/0xB5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65086 /* 202930 */ GIR_AddImm, /*InsnID*//* 566(*/0xB6, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
65087 /* 202941 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 566(*/0xB6, 0x04/*)*/,
65088 /* 202944 */ GIR_MakeTempReg, /*TempRegID*//* 564(*/0xB4, 0x04/*)*/, /*TypeID*/GILLT_s32,
65089 /* 202948 */ GIR_BuildMI, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65090 /* 202953 */ GIR_AddTempRegister, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, /*TempRegID*//* 564(*/0xB4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65091 /* 202960 */ GIR_AddSimpleTempRegister, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, /*TempRegID*//* 565(*/0xB5, 0x04/*)*/,
65092 /* 202965 */ GIR_AddImm, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
65093 /* 202976 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 565(*/0xB5, 0x04/*)*/,
65094 /* 202979 */ GIR_MakeTempReg, /*TempRegID*//* 563(*/0xB3, 0x04/*)*/, /*TypeID*/GILLT_s64,
65095 /* 202983 */ GIR_BuildMI, /*InsnID*//* 564(*/0xB4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65096 /* 202988 */ GIR_AddTempRegister, /*InsnID*//* 564(*/0xB4, 0x04/*)*/, /*TempRegID*//* 563(*/0xB3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65097 /* 202995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 564(*/0xB4, 0x04/*)*/,
65098 /* 202998 */ GIR_MakeTempReg, /*TempRegID*//* 562(*/0xB2, 0x04/*)*/, /*TypeID*/GILLT_s64,
65099 /* 203002 */ GIR_BuildMI, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65100 /* 203007 */ GIR_AddTempRegister, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*TempRegID*//* 562(*/0xB2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65101 /* 203014 */ GIR_AddSimpleTempRegister, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*TempRegID*//* 563(*/0xB3, 0x04/*)*/,
65102 /* 203019 */ GIR_AddSimpleTempRegister, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*TempRegID*//* 564(*/0xB4, 0x04/*)*/,
65103 /* 203024 */ GIR_AddImm8, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Imm*/1,
65104 /* 203028 */ GIR_ConstrainOperandRC, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65105 /* 203034 */ GIR_ConstrainOperandRC, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65106 /* 203040 */ GIR_ConstrainOperandRC, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65107 /* 203046 */ GIR_MakeTempReg, /*TempRegID*//* 561(*/0xB1, 0x04/*)*/, /*TypeID*/GILLT_s64,
65108 /* 203050 */ GIR_BuildMI, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65109 /* 203055 */ GIR_AddTempRegister, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*TempRegID*//* 561(*/0xB1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65110 /* 203062 */ GIR_AddSimpleTempRegister, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*TempRegID*//* 562(*/0xB2, 0x04/*)*/,
65111 /* 203067 */ GIR_AddImm8, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*Imm*/32,
65112 /* 203071 */ GIR_AddImm8, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*Imm*/31,
65113 /* 203075 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 562(*/0xB2, 0x04/*)*/,
65114 /* 203078 */ GIR_MakeTempReg, /*TempRegID*//* 560(*/0xB0, 0x04/*)*/, /*TypeID*/GILLT_s64,
65115 /* 203082 */ GIR_BuildMI, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65116 /* 203087 */ GIR_AddTempRegister, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, /*TempRegID*//* 560(*/0xB0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65117 /* 203094 */ GIR_AddSimpleTempRegister, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, /*TempRegID*//* 561(*/0xB1, 0x04/*)*/,
65118 /* 203099 */ GIR_AddImm, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
65119 /* 203110 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 561(*/0xB1, 0x04/*)*/,
65120 /* 203113 */ GIR_MakeTempReg, /*TempRegID*//* 559(*/0xAF, 0x04/*)*/, /*TypeID*/GILLT_s64,
65121 /* 203117 */ GIR_BuildMI, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65122 /* 203122 */ GIR_AddTempRegister, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, /*TempRegID*//* 559(*/0xAF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65123 /* 203129 */ GIR_AddSimpleTempRegister, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, /*TempRegID*//* 560(*/0xB0, 0x04/*)*/,
65124 /* 203134 */ GIR_AddImm, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845),
65125 /* 203145 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 560(*/0xB0, 0x04/*)*/,
65126 /* 203148 */ GIR_MakeTempReg, /*TempRegID*//* 558(*/0xAE, 0x04/*)*/, /*TypeID*/GILLT_s64,
65127 /* 203152 */ GIR_BuildMI, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65128 /* 203157 */ GIR_AddTempRegister, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, /*TempRegID*//* 558(*/0xAE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65129 /* 203164 */ GIR_Copy, /*NewInsnID*//* 559(*/0xAF, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65130 /* 203169 */ GIR_AddImm8, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, /*Imm*/63,
65131 /* 203173 */ GIR_AddImm8, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, /*Imm*/1,
65132 /* 203177 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 559(*/0xAF, 0x04/*)*/,
65133 /* 203180 */ GIR_MakeTempReg, /*TempRegID*//* 557(*/0xAD, 0x04/*)*/, /*TypeID*/GILLT_s64,
65134 /* 203184 */ GIR_BuildMI, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65135 /* 203189 */ GIR_AddTempRegister, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, /*TempRegID*//* 557(*/0xAD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65136 /* 203196 */ GIR_AddSimpleTempRegister, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, /*TempRegID*//* 558(*/0xAE, 0x04/*)*/,
65137 /* 203201 */ GIR_AddSimpleTempRegister, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, /*TempRegID*//* 559(*/0xAF, 0x04/*)*/,
65138 /* 203206 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 558(*/0xAE, 0x04/*)*/,
65139 /* 203209 */ GIR_MakeTempReg, /*TempRegID*//* 556(*/0xAC, 0x04/*)*/, /*TypeID*/GILLT_s64,
65140 /* 203213 */ GIR_BuildMI, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65141 /* 203218 */ GIR_AddTempRegister, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, /*TempRegID*//* 556(*/0xAC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65142 /* 203225 */ GIR_AddSimpleTempRegister, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, /*TempRegID*//* 557(*/0xAD, 0x04/*)*/,
65143 /* 203230 */ GIR_AddSimpleTempRegister, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, /*TempRegID*//* 566(*/0xB6, 0x04/*)*/,
65144 /* 203235 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 557(*/0xAD, 0x04/*)*/,
65145 /* 203238 */ GIR_MakeTempReg, /*TempRegID*//* 555(*/0xAB, 0x04/*)*/, /*TypeID*/GILLT_s64,
65146 /* 203242 */ GIR_BuildMI, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65147 /* 203247 */ GIR_AddTempRegister, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*TempRegID*//* 555(*/0xAB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65148 /* 203254 */ GIR_AddSimpleTempRegister, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*TempRegID*//* 556(*/0xAC, 0x04/*)*/,
65149 /* 203259 */ GIR_AddImm8, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*Imm*/62,
65150 /* 203263 */ GIR_AddImm8, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*Imm*/2,
65151 /* 203267 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 556(*/0xAC, 0x04/*)*/,
65152 /* 203270 */ GIR_MakeTempReg, /*TempRegID*//* 554(*/0xAA, 0x04/*)*/, /*TypeID*/GILLT_s64,
65153 /* 203274 */ GIR_BuildMI, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65154 /* 203279 */ GIR_AddTempRegister, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, /*TempRegID*//* 554(*/0xAA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65155 /* 203286 */ GIR_AddSimpleTempRegister, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, /*TempRegID*//* 555(*/0xAB, 0x04/*)*/,
65156 /* 203291 */ GIR_AddSimpleTempRegister, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, /*TempRegID*//* 575(*/0xBF, 0x04/*)*/,
65157 /* 203296 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 555(*/0xAB, 0x04/*)*/,
65158 /* 203299 */ GIR_MakeTempReg, /*TempRegID*//* 553(*/0xA9, 0x04/*)*/, /*TypeID*/GILLT_s64,
65159 /* 203303 */ GIR_BuildMI, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65160 /* 203308 */ GIR_AddTempRegister, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, /*TempRegID*//* 553(*/0xA9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65161 /* 203315 */ GIR_AddSimpleTempRegister, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, /*TempRegID*//* 554(*/0xAA, 0x04/*)*/,
65162 /* 203320 */ GIR_AddSimpleTempRegister, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, /*TempRegID*//* 582(*/0xC6, 0x04/*)*/,
65163 /* 203325 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 554(*/0xAA, 0x04/*)*/,
65164 /* 203328 */ GIR_MakeTempReg, /*TempRegID*//* 552(*/0xA8, 0x04/*)*/, /*TypeID*/GILLT_s64,
65165 /* 203332 */ GIR_BuildMI, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65166 /* 203337 */ GIR_AddTempRegister, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*TempRegID*//* 552(*/0xA8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65167 /* 203344 */ GIR_AddSimpleTempRegister, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*TempRegID*//* 553(*/0xA9, 0x04/*)*/,
65168 /* 203349 */ GIR_AddImm8, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*Imm*/60,
65169 /* 203353 */ GIR_AddImm8, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*Imm*/4,
65170 /* 203357 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 553(*/0xA9, 0x04/*)*/,
65171 /* 203360 */ GIR_MakeTempReg, /*TempRegID*//* 551(*/0xA7, 0x04/*)*/, /*TypeID*/GILLT_s64,
65172 /* 203364 */ GIR_BuildMI, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65173 /* 203369 */ GIR_AddTempRegister, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, /*TempRegID*//* 551(*/0xA7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65174 /* 203376 */ GIR_AddSimpleTempRegister, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, /*TempRegID*//* 552(*/0xA8, 0x04/*)*/,
65175 /* 203381 */ GIR_AddSimpleTempRegister, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, /*TempRegID*//* 610(*/0xE2, 0x04/*)*/,
65176 /* 203386 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 552(*/0xA8, 0x04/*)*/,
65177 /* 203389 */ GIR_MakeTempReg, /*TempRegID*//* 550(*/0xA6, 0x04/*)*/, /*TypeID*/GILLT_s64,
65178 /* 203393 */ GIR_BuildMI, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65179 /* 203398 */ GIR_AddTempRegister, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, /*TempRegID*//* 550(*/0xA6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65180 /* 203405 */ GIR_AddSimpleTempRegister, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, /*TempRegID*//* 551(*/0xA7, 0x04/*)*/,
65181 /* 203410 */ GIR_AddSimpleTempRegister, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, /*TempRegID*//* 617(*/0xE9, 0x04/*)*/,
65182 /* 203415 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 551(*/0xA7, 0x04/*)*/,
65183 /* 203418 */ GIR_MakeTempReg, /*TempRegID*//* 549(*/0xA5, 0x04/*)*/, /*TypeID*/GILLT_s64,
65184 /* 203422 */ GIR_BuildMI, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65185 /* 203427 */ GIR_AddTempRegister, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*TempRegID*//* 549(*/0xA5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65186 /* 203434 */ GIR_AddSimpleTempRegister, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*TempRegID*//* 550(*/0xA6, 0x04/*)*/,
65187 /* 203439 */ GIR_AddImm8, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*Imm*/32,
65188 /* 203443 */ GIR_AddImm8, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*Imm*/32,
65189 /* 203447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 550(*/0xA6, 0x04/*)*/,
65190 /* 203450 */ GIR_MakeTempReg, /*TempRegID*//* 817(*/0xB1, 0x06/*)*/, /*TypeID*/GILLT_s32,
65191 /* 203454 */ GIR_BuildMI, /*InsnID*//* 818(*/0xB2, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65192 /* 203459 */ GIR_AddTempRegister, /*InsnID*//* 818(*/0xB2, 0x06/*)*/, /*TempRegID*//* 817(*/0xB1, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65193 /* 203466 */ GIR_AddImm, /*InsnID*//* 818(*/0xB2, 0x06/*)*/, /*Imm*/GIMT_Encode8(61680),
65194 /* 203477 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 818(*/0xB2, 0x06/*)*/,
65195 /* 203480 */ GIR_MakeTempReg, /*TempRegID*//* 816(*/0xB0, 0x06/*)*/, /*TypeID*/GILLT_s32,
65196 /* 203484 */ GIR_BuildMI, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65197 /* 203489 */ GIR_AddTempRegister, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, /*TempRegID*//* 816(*/0xB0, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65198 /* 203496 */ GIR_AddSimpleTempRegister, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, /*TempRegID*//* 817(*/0xB1, 0x06/*)*/,
65199 /* 203501 */ GIR_AddImm, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, /*Imm*/GIMT_Encode8(61680),
65200 /* 203512 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 817(*/0xB1, 0x06/*)*/,
65201 /* 203515 */ GIR_MakeTempReg, /*TempRegID*//* 815(*/0xAF, 0x06/*)*/, /*TypeID*/GILLT_s64,
65202 /* 203519 */ GIR_BuildMI, /*InsnID*//* 816(*/0xB0, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65203 /* 203524 */ GIR_AddTempRegister, /*InsnID*//* 816(*/0xB0, 0x06/*)*/, /*TempRegID*//* 815(*/0xAF, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65204 /* 203531 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 816(*/0xB0, 0x06/*)*/,
65205 /* 203534 */ GIR_MakeTempReg, /*TempRegID*//* 814(*/0xAE, 0x06/*)*/, /*TypeID*/GILLT_s64,
65206 /* 203538 */ GIR_BuildMI, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65207 /* 203543 */ GIR_AddTempRegister, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*TempRegID*//* 814(*/0xAE, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65208 /* 203550 */ GIR_AddSimpleTempRegister, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*TempRegID*//* 815(*/0xAF, 0x06/*)*/,
65209 /* 203555 */ GIR_AddSimpleTempRegister, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*TempRegID*//* 816(*/0xB0, 0x06/*)*/,
65210 /* 203560 */ GIR_AddImm8, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Imm*/1,
65211 /* 203564 */ GIR_ConstrainOperandRC, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65212 /* 203570 */ GIR_ConstrainOperandRC, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65213 /* 203576 */ GIR_ConstrainOperandRC, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65214 /* 203582 */ GIR_MakeTempReg, /*TempRegID*//* 813(*/0xAD, 0x06/*)*/, /*TypeID*/GILLT_s64,
65215 /* 203586 */ GIR_BuildMI, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65216 /* 203591 */ GIR_AddTempRegister, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*TempRegID*//* 813(*/0xAD, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65217 /* 203598 */ GIR_AddSimpleTempRegister, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*TempRegID*//* 814(*/0xAE, 0x06/*)*/,
65218 /* 203603 */ GIR_AddImm8, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*Imm*/32,
65219 /* 203607 */ GIR_AddImm8, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*Imm*/31,
65220 /* 203611 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 814(*/0xAE, 0x06/*)*/,
65221 /* 203614 */ GIR_MakeTempReg, /*TempRegID*//* 812(*/0xAC, 0x06/*)*/, /*TypeID*/GILLT_s64,
65222 /* 203618 */ GIR_BuildMI, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65223 /* 203623 */ GIR_AddTempRegister, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, /*TempRegID*//* 812(*/0xAC, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65224 /* 203630 */ GIR_AddSimpleTempRegister, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, /*TempRegID*//* 813(*/0xAD, 0x06/*)*/,
65225 /* 203635 */ GIR_AddImm, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, /*Imm*/GIMT_Encode8(61680),
65226 /* 203646 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 813(*/0xAD, 0x06/*)*/,
65227 /* 203649 */ GIR_MakeTempReg, /*TempRegID*//* 811(*/0xAB, 0x06/*)*/, /*TypeID*/GILLT_s64,
65228 /* 203653 */ GIR_BuildMI, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65229 /* 203658 */ GIR_AddTempRegister, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, /*TempRegID*//* 811(*/0xAB, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65230 /* 203665 */ GIR_AddSimpleTempRegister, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, /*TempRegID*//* 812(*/0xAC, 0x06/*)*/,
65231 /* 203670 */ GIR_AddImm, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, /*Imm*/GIMT_Encode8(61680),
65232 /* 203681 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 812(*/0xAC, 0x06/*)*/,
65233 /* 203684 */ GIR_MakeTempReg, /*TempRegID*//* 810(*/0xAA, 0x06/*)*/, /*TypeID*/GILLT_s32,
65234 /* 203688 */ GIR_BuildMI, /*InsnID*//* 811(*/0xAB, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65235 /* 203693 */ GIR_AddTempRegister, /*InsnID*//* 811(*/0xAB, 0x06/*)*/, /*TempRegID*//* 810(*/0xAA, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65236 /* 203700 */ GIR_AddImm, /*InsnID*//* 811(*/0xAB, 0x06/*)*/, /*Imm*/GIMT_Encode8(52428),
65237 /* 203711 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 811(*/0xAB, 0x06/*)*/,
65238 /* 203714 */ GIR_MakeTempReg, /*TempRegID*//* 809(*/0xA9, 0x06/*)*/, /*TypeID*/GILLT_s32,
65239 /* 203718 */ GIR_BuildMI, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65240 /* 203723 */ GIR_AddTempRegister, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, /*TempRegID*//* 809(*/0xA9, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65241 /* 203730 */ GIR_AddSimpleTempRegister, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, /*TempRegID*//* 810(*/0xAA, 0x06/*)*/,
65242 /* 203735 */ GIR_AddImm, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, /*Imm*/GIMT_Encode8(52428),
65243 /* 203746 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 810(*/0xAA, 0x06/*)*/,
65244 /* 203749 */ GIR_MakeTempReg, /*TempRegID*//* 808(*/0xA8, 0x06/*)*/, /*TypeID*/GILLT_s64,
65245 /* 203753 */ GIR_BuildMI, /*InsnID*//* 809(*/0xA9, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65246 /* 203758 */ GIR_AddTempRegister, /*InsnID*//* 809(*/0xA9, 0x06/*)*/, /*TempRegID*//* 808(*/0xA8, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65247 /* 203765 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 809(*/0xA9, 0x06/*)*/,
65248 /* 203768 */ GIR_MakeTempReg, /*TempRegID*//* 807(*/0xA7, 0x06/*)*/, /*TypeID*/GILLT_s64,
65249 /* 203772 */ GIR_BuildMI, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65250 /* 203777 */ GIR_AddTempRegister, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*TempRegID*//* 807(*/0xA7, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65251 /* 203784 */ GIR_AddSimpleTempRegister, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*TempRegID*//* 808(*/0xA8, 0x06/*)*/,
65252 /* 203789 */ GIR_AddSimpleTempRegister, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*TempRegID*//* 809(*/0xA9, 0x06/*)*/,
65253 /* 203794 */ GIR_AddImm8, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Imm*/1,
65254 /* 203798 */ GIR_ConstrainOperandRC, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65255 /* 203804 */ GIR_ConstrainOperandRC, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65256 /* 203810 */ GIR_ConstrainOperandRC, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65257 /* 203816 */ GIR_MakeTempReg, /*TempRegID*//* 806(*/0xA6, 0x06/*)*/, /*TypeID*/GILLT_s64,
65258 /* 203820 */ GIR_BuildMI, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65259 /* 203825 */ GIR_AddTempRegister, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*TempRegID*//* 806(*/0xA6, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65260 /* 203832 */ GIR_AddSimpleTempRegister, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*TempRegID*//* 807(*/0xA7, 0x06/*)*/,
65261 /* 203837 */ GIR_AddImm8, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*Imm*/32,
65262 /* 203841 */ GIR_AddImm8, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*Imm*/31,
65263 /* 203845 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 807(*/0xA7, 0x06/*)*/,
65264 /* 203848 */ GIR_MakeTempReg, /*TempRegID*//* 805(*/0xA5, 0x06/*)*/, /*TypeID*/GILLT_s64,
65265 /* 203852 */ GIR_BuildMI, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65266 /* 203857 */ GIR_AddTempRegister, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, /*TempRegID*//* 805(*/0xA5, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65267 /* 203864 */ GIR_AddSimpleTempRegister, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, /*TempRegID*//* 806(*/0xA6, 0x06/*)*/,
65268 /* 203869 */ GIR_AddImm, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, /*Imm*/GIMT_Encode8(52428),
65269 /* 203880 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 806(*/0xA6, 0x06/*)*/,
65270 /* 203883 */ GIR_MakeTempReg, /*TempRegID*//* 804(*/0xA4, 0x06/*)*/, /*TypeID*/GILLT_s64,
65271 /* 203887 */ GIR_BuildMI, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65272 /* 203892 */ GIR_AddTempRegister, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, /*TempRegID*//* 804(*/0xA4, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65273 /* 203899 */ GIR_AddSimpleTempRegister, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, /*TempRegID*//* 805(*/0xA5, 0x06/*)*/,
65274 /* 203904 */ GIR_AddImm, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, /*Imm*/GIMT_Encode8(52428),
65275 /* 203915 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 805(*/0xA5, 0x06/*)*/,
65276 /* 203918 */ GIR_MakeTempReg, /*TempRegID*//* 803(*/0xA3, 0x06/*)*/, /*TypeID*/GILLT_s32,
65277 /* 203922 */ GIR_BuildMI, /*InsnID*//* 804(*/0xA4, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65278 /* 203927 */ GIR_AddTempRegister, /*InsnID*//* 804(*/0xA4, 0x06/*)*/, /*TempRegID*//* 803(*/0xA3, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65279 /* 203934 */ GIR_AddImm, /*InsnID*//* 804(*/0xA4, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690),
65280 /* 203945 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 804(*/0xA4, 0x06/*)*/,
65281 /* 203948 */ GIR_MakeTempReg, /*TempRegID*//* 802(*/0xA2, 0x06/*)*/, /*TypeID*/GILLT_s32,
65282 /* 203952 */ GIR_BuildMI, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65283 /* 203957 */ GIR_AddTempRegister, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, /*TempRegID*//* 802(*/0xA2, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65284 /* 203964 */ GIR_AddSimpleTempRegister, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, /*TempRegID*//* 803(*/0xA3, 0x06/*)*/,
65285 /* 203969 */ GIR_AddImm, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690),
65286 /* 203980 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 803(*/0xA3, 0x06/*)*/,
65287 /* 203983 */ GIR_MakeTempReg, /*TempRegID*//* 801(*/0xA1, 0x06/*)*/, /*TypeID*/GILLT_s64,
65288 /* 203987 */ GIR_BuildMI, /*InsnID*//* 802(*/0xA2, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65289 /* 203992 */ GIR_AddTempRegister, /*InsnID*//* 802(*/0xA2, 0x06/*)*/, /*TempRegID*//* 801(*/0xA1, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65290 /* 203999 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 802(*/0xA2, 0x06/*)*/,
65291 /* 204002 */ GIR_MakeTempReg, /*TempRegID*//* 800(*/0xA0, 0x06/*)*/, /*TypeID*/GILLT_s64,
65292 /* 204006 */ GIR_BuildMI, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65293 /* 204011 */ GIR_AddTempRegister, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*TempRegID*//* 800(*/0xA0, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65294 /* 204018 */ GIR_AddSimpleTempRegister, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*TempRegID*//* 801(*/0xA1, 0x06/*)*/,
65295 /* 204023 */ GIR_AddSimpleTempRegister, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*TempRegID*//* 802(*/0xA2, 0x06/*)*/,
65296 /* 204028 */ GIR_AddImm8, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Imm*/1,
65297 /* 204032 */ GIR_ConstrainOperandRC, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65298 /* 204038 */ GIR_ConstrainOperandRC, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65299 /* 204044 */ GIR_ConstrainOperandRC, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65300 /* 204050 */ GIR_MakeTempReg, /*TempRegID*//* 799(*/0x9F, 0x06/*)*/, /*TypeID*/GILLT_s64,
65301 /* 204054 */ GIR_BuildMI, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65302 /* 204059 */ GIR_AddTempRegister, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*TempRegID*//* 799(*/0x9F, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65303 /* 204066 */ GIR_AddSimpleTempRegister, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*TempRegID*//* 800(*/0xA0, 0x06/*)*/,
65304 /* 204071 */ GIR_AddImm8, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*Imm*/32,
65305 /* 204075 */ GIR_AddImm8, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*Imm*/31,
65306 /* 204079 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 800(*/0xA0, 0x06/*)*/,
65307 /* 204082 */ GIR_MakeTempReg, /*TempRegID*//* 798(*/0x9E, 0x06/*)*/, /*TypeID*/GILLT_s64,
65308 /* 204086 */ GIR_BuildMI, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65309 /* 204091 */ GIR_AddTempRegister, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, /*TempRegID*//* 798(*/0x9E, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65310 /* 204098 */ GIR_AddSimpleTempRegister, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, /*TempRegID*//* 799(*/0x9F, 0x06/*)*/,
65311 /* 204103 */ GIR_AddImm, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690),
65312 /* 204114 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 799(*/0x9F, 0x06/*)*/,
65313 /* 204117 */ GIR_MakeTempReg, /*TempRegID*//* 797(*/0x9D, 0x06/*)*/, /*TypeID*/GILLT_s64,
65314 /* 204121 */ GIR_BuildMI, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65315 /* 204126 */ GIR_AddTempRegister, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, /*TempRegID*//* 797(*/0x9D, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65316 /* 204133 */ GIR_AddSimpleTempRegister, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, /*TempRegID*//* 798(*/0x9E, 0x06/*)*/,
65317 /* 204138 */ GIR_AddImm, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690),
65318 /* 204149 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 798(*/0x9E, 0x06/*)*/,
65319 /* 204152 */ GIR_MakeTempReg, /*TempRegID*//* 796(*/0x9C, 0x06/*)*/, /*TypeID*/GILLT_s64,
65320 /* 204156 */ GIR_BuildMI, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65321 /* 204161 */ GIR_AddTempRegister, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, /*TempRegID*//* 796(*/0x9C, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65322 /* 204168 */ GIR_Copy, /*NewInsnID*//* 797(*/0x9D, 0x06/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65323 /* 204173 */ GIR_AddImm8, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, /*Imm*/1,
65324 /* 204177 */ GIR_AddImm8, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, /*Imm*/62,
65325 /* 204181 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 797(*/0x9D, 0x06/*)*/,
65326 /* 204184 */ GIR_MakeTempReg, /*TempRegID*//* 795(*/0x9B, 0x06/*)*/, /*TypeID*/GILLT_s64,
65327 /* 204188 */ GIR_BuildMI, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65328 /* 204193 */ GIR_AddTempRegister, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, /*TempRegID*//* 795(*/0x9B, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65329 /* 204200 */ GIR_AddSimpleTempRegister, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, /*TempRegID*//* 796(*/0x9C, 0x06/*)*/,
65330 /* 204205 */ GIR_AddSimpleTempRegister, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, /*TempRegID*//* 797(*/0x9D, 0x06/*)*/,
65331 /* 204210 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 796(*/0x9C, 0x06/*)*/,
65332 /* 204213 */ GIR_MakeTempReg, /*TempRegID*//* 794(*/0x9A, 0x06/*)*/, /*TypeID*/GILLT_s32,
65333 /* 204217 */ GIR_BuildMI, /*InsnID*//* 795(*/0x9B, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65334 /* 204222 */ GIR_AddTempRegister, /*InsnID*//* 795(*/0x9B, 0x06/*)*/, /*TempRegID*//* 794(*/0x9A, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65335 /* 204229 */ GIR_AddImm, /*InsnID*//* 795(*/0x9B, 0x06/*)*/, /*Imm*/GIMT_Encode8(21845),
65336 /* 204240 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 795(*/0x9B, 0x06/*)*/,
65337 /* 204243 */ GIR_MakeTempReg, /*TempRegID*//* 793(*/0x99, 0x06/*)*/, /*TypeID*/GILLT_s32,
65338 /* 204247 */ GIR_BuildMI, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65339 /* 204252 */ GIR_AddTempRegister, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, /*TempRegID*//* 793(*/0x99, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65340 /* 204259 */ GIR_AddSimpleTempRegister, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, /*TempRegID*//* 794(*/0x9A, 0x06/*)*/,
65341 /* 204264 */ GIR_AddImm, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, /*Imm*/GIMT_Encode8(21845),
65342 /* 204275 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 794(*/0x9A, 0x06/*)*/,
65343 /* 204278 */ GIR_MakeTempReg, /*TempRegID*//* 792(*/0x98, 0x06/*)*/, /*TypeID*/GILLT_s64,
65344 /* 204282 */ GIR_BuildMI, /*InsnID*//* 793(*/0x99, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65345 /* 204287 */ GIR_AddTempRegister, /*InsnID*//* 793(*/0x99, 0x06/*)*/, /*TempRegID*//* 792(*/0x98, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65346 /* 204294 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 793(*/0x99, 0x06/*)*/,
65347 /* 204297 */ GIR_MakeTempReg, /*TempRegID*//* 791(*/0x97, 0x06/*)*/, /*TypeID*/GILLT_s64,
65348 /* 204301 */ GIR_BuildMI, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65349 /* 204306 */ GIR_AddTempRegister, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*TempRegID*//* 791(*/0x97, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65350 /* 204313 */ GIR_AddSimpleTempRegister, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*TempRegID*//* 792(*/0x98, 0x06/*)*/,
65351 /* 204318 */ GIR_AddSimpleTempRegister, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*TempRegID*//* 793(*/0x99, 0x06/*)*/,
65352 /* 204323 */ GIR_AddImm8, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Imm*/1,
65353 /* 204327 */ GIR_ConstrainOperandRC, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65354 /* 204333 */ GIR_ConstrainOperandRC, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65355 /* 204339 */ GIR_ConstrainOperandRC, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65356 /* 204345 */ GIR_MakeTempReg, /*TempRegID*//* 790(*/0x96, 0x06/*)*/, /*TypeID*/GILLT_s64,
65357 /* 204349 */ GIR_BuildMI, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65358 /* 204354 */ GIR_AddTempRegister, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*TempRegID*//* 790(*/0x96, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65359 /* 204361 */ GIR_AddSimpleTempRegister, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*TempRegID*//* 791(*/0x97, 0x06/*)*/,
65360 /* 204366 */ GIR_AddImm8, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*Imm*/32,
65361 /* 204370 */ GIR_AddImm8, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*Imm*/31,
65362 /* 204374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 791(*/0x97, 0x06/*)*/,
65363 /* 204377 */ GIR_MakeTempReg, /*TempRegID*//* 789(*/0x95, 0x06/*)*/, /*TypeID*/GILLT_s64,
65364 /* 204381 */ GIR_BuildMI, /*InsnID*//* 790(*/0x96, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65365 /* 204386 */ GIR_AddTempRegister, /*InsnID*//* 790(*/0x96, 0x06/*)*/, /*TempRegID*//* 789(*/0x95, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65366 /* 204393 */ GIR_AddSimpleTempRegister, /*InsnID*//* 790(*/0x96, 0x06/*)*/, /*TempRegID*//* 790(*/0x96, 0x06/*)*/,
65367 /* 204398 */ GIR_AddImm, /*InsnID*//* 790(*/0x96, 0x06/*)*/, /*Imm*/GIMT_Encode8(21845),
65368 /* 204409 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 790(*/0x96, 0x06/*)*/,
65369 /* 204412 */ GIR_MakeTempReg, /*TempRegID*//* 788(*/0x94, 0x06/*)*/, /*TypeID*/GILLT_s64,
65370 /* 204416 */ GIR_BuildMI, /*InsnID*//* 789(*/0x95, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65371 /* 204421 */ GIR_AddTempRegister, /*InsnID*//* 789(*/0x95, 0x06/*)*/, /*TempRegID*//* 788(*/0x94, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65372 /* 204428 */ GIR_AddSimpleTempRegister, /*InsnID*//* 789(*/0x95, 0x06/*)*/, /*TempRegID*//* 789(*/0x95, 0x06/*)*/,
65373 /* 204433 */ GIR_AddImm, /*InsnID*//* 789(*/0x95, 0x06/*)*/, /*Imm*/GIMT_Encode8(21845),
65374 /* 204444 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 789(*/0x95, 0x06/*)*/,
65375 /* 204447 */ GIR_MakeTempReg, /*TempRegID*//* 787(*/0x93, 0x06/*)*/, /*TypeID*/GILLT_s64,
65376 /* 204451 */ GIR_BuildMI, /*InsnID*//* 788(*/0x94, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65377 /* 204456 */ GIR_AddTempRegister, /*InsnID*//* 788(*/0x94, 0x06/*)*/, /*TempRegID*//* 787(*/0x93, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65378 /* 204463 */ GIR_Copy, /*NewInsnID*//* 788(*/0x94, 0x06/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65379 /* 204468 */ GIR_AddImm8, /*InsnID*//* 788(*/0x94, 0x06/*)*/, /*Imm*/63,
65380 /* 204472 */ GIR_AddImm8, /*InsnID*//* 788(*/0x94, 0x06/*)*/, /*Imm*/1,
65381 /* 204476 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 788(*/0x94, 0x06/*)*/,
65382 /* 204479 */ GIR_MakeTempReg, /*TempRegID*//* 786(*/0x92, 0x06/*)*/, /*TypeID*/GILLT_s64,
65383 /* 204483 */ GIR_BuildMI, /*InsnID*//* 787(*/0x93, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65384 /* 204488 */ GIR_AddTempRegister, /*InsnID*//* 787(*/0x93, 0x06/*)*/, /*TempRegID*//* 786(*/0x92, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65385 /* 204495 */ GIR_AddSimpleTempRegister, /*InsnID*//* 787(*/0x93, 0x06/*)*/, /*TempRegID*//* 787(*/0x93, 0x06/*)*/,
65386 /* 204500 */ GIR_AddSimpleTempRegister, /*InsnID*//* 787(*/0x93, 0x06/*)*/, /*TempRegID*//* 788(*/0x94, 0x06/*)*/,
65387 /* 204505 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 787(*/0x93, 0x06/*)*/,
65388 /* 204508 */ GIR_MakeTempReg, /*TempRegID*//* 785(*/0x91, 0x06/*)*/, /*TypeID*/GILLT_s64,
65389 /* 204512 */ GIR_BuildMI, /*InsnID*//* 786(*/0x92, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65390 /* 204517 */ GIR_AddTempRegister, /*InsnID*//* 786(*/0x92, 0x06/*)*/, /*TempRegID*//* 785(*/0x91, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65391 /* 204524 */ GIR_AddSimpleTempRegister, /*InsnID*//* 786(*/0x92, 0x06/*)*/, /*TempRegID*//* 786(*/0x92, 0x06/*)*/,
65392 /* 204529 */ GIR_AddSimpleTempRegister, /*InsnID*//* 786(*/0x92, 0x06/*)*/, /*TempRegID*//* 795(*/0x9B, 0x06/*)*/,
65393 /* 204534 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 786(*/0x92, 0x06/*)*/,
65394 /* 204537 */ GIR_MakeTempReg, /*TempRegID*//* 784(*/0x90, 0x06/*)*/, /*TypeID*/GILLT_s64,
65395 /* 204541 */ GIR_BuildMI, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65396 /* 204546 */ GIR_AddTempRegister, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*TempRegID*//* 784(*/0x90, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65397 /* 204553 */ GIR_AddSimpleTempRegister, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*TempRegID*//* 785(*/0x91, 0x06/*)*/,
65398 /* 204558 */ GIR_AddImm8, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*Imm*/2,
65399 /* 204562 */ GIR_AddImm8, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*Imm*/61,
65400 /* 204566 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 785(*/0x91, 0x06/*)*/,
65401 /* 204569 */ GIR_MakeTempReg, /*TempRegID*//* 783(*/0x8F, 0x06/*)*/, /*TypeID*/GILLT_s64,
65402 /* 204573 */ GIR_BuildMI, /*InsnID*//* 784(*/0x90, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65403 /* 204578 */ GIR_AddTempRegister, /*InsnID*//* 784(*/0x90, 0x06/*)*/, /*TempRegID*//* 783(*/0x8F, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65404 /* 204585 */ GIR_AddSimpleTempRegister, /*InsnID*//* 784(*/0x90, 0x06/*)*/, /*TempRegID*//* 784(*/0x90, 0x06/*)*/,
65405 /* 204590 */ GIR_AddSimpleTempRegister, /*InsnID*//* 784(*/0x90, 0x06/*)*/, /*TempRegID*//* 804(*/0xA4, 0x06/*)*/,
65406 /* 204595 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 784(*/0x90, 0x06/*)*/,
65407 /* 204598 */ GIR_MakeTempReg, /*TempRegID*//* 782(*/0x8E, 0x06/*)*/, /*TypeID*/GILLT_s32,
65408 /* 204602 */ GIR_BuildMI, /*InsnID*//* 783(*/0x8F, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65409 /* 204607 */ GIR_AddTempRegister, /*InsnID*//* 783(*/0x8F, 0x06/*)*/, /*TempRegID*//* 782(*/0x8E, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65410 /* 204614 */ GIR_AddImm, /*InsnID*//* 783(*/0x8F, 0x06/*)*/, /*Imm*/GIMT_Encode8(13107),
65411 /* 204625 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 783(*/0x8F, 0x06/*)*/,
65412 /* 204628 */ GIR_MakeTempReg, /*TempRegID*//* 781(*/0x8D, 0x06/*)*/, /*TypeID*/GILLT_s32,
65413 /* 204632 */ GIR_BuildMI, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65414 /* 204637 */ GIR_AddTempRegister, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, /*TempRegID*//* 781(*/0x8D, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65415 /* 204644 */ GIR_AddSimpleTempRegister, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, /*TempRegID*//* 782(*/0x8E, 0x06/*)*/,
65416 /* 204649 */ GIR_AddImm, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, /*Imm*/GIMT_Encode8(13107),
65417 /* 204660 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 782(*/0x8E, 0x06/*)*/,
65418 /* 204663 */ GIR_MakeTempReg, /*TempRegID*//* 780(*/0x8C, 0x06/*)*/, /*TypeID*/GILLT_s64,
65419 /* 204667 */ GIR_BuildMI, /*InsnID*//* 781(*/0x8D, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65420 /* 204672 */ GIR_AddTempRegister, /*InsnID*//* 781(*/0x8D, 0x06/*)*/, /*TempRegID*//* 780(*/0x8C, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65421 /* 204679 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 781(*/0x8D, 0x06/*)*/,
65422 /* 204682 */ GIR_MakeTempReg, /*TempRegID*//* 779(*/0x8B, 0x06/*)*/, /*TypeID*/GILLT_s64,
65423 /* 204686 */ GIR_BuildMI, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65424 /* 204691 */ GIR_AddTempRegister, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*TempRegID*//* 779(*/0x8B, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65425 /* 204698 */ GIR_AddSimpleTempRegister, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*TempRegID*//* 780(*/0x8C, 0x06/*)*/,
65426 /* 204703 */ GIR_AddSimpleTempRegister, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*TempRegID*//* 781(*/0x8D, 0x06/*)*/,
65427 /* 204708 */ GIR_AddImm8, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Imm*/1,
65428 /* 204712 */ GIR_ConstrainOperandRC, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65429 /* 204718 */ GIR_ConstrainOperandRC, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65430 /* 204724 */ GIR_ConstrainOperandRC, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65431 /* 204730 */ GIR_MakeTempReg, /*TempRegID*//* 778(*/0x8A, 0x06/*)*/, /*TypeID*/GILLT_s64,
65432 /* 204734 */ GIR_BuildMI, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65433 /* 204739 */ GIR_AddTempRegister, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*TempRegID*//* 778(*/0x8A, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65434 /* 204746 */ GIR_AddSimpleTempRegister, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*TempRegID*//* 779(*/0x8B, 0x06/*)*/,
65435 /* 204751 */ GIR_AddImm8, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*Imm*/32,
65436 /* 204755 */ GIR_AddImm8, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*Imm*/31,
65437 /* 204759 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 779(*/0x8B, 0x06/*)*/,
65438 /* 204762 */ GIR_MakeTempReg, /*TempRegID*//* 777(*/0x89, 0x06/*)*/, /*TypeID*/GILLT_s64,
65439 /* 204766 */ GIR_BuildMI, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65440 /* 204771 */ GIR_AddTempRegister, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, /*TempRegID*//* 777(*/0x89, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65441 /* 204778 */ GIR_AddSimpleTempRegister, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, /*TempRegID*//* 778(*/0x8A, 0x06/*)*/,
65442 /* 204783 */ GIR_AddImm, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, /*Imm*/GIMT_Encode8(13107),
65443 /* 204794 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 778(*/0x8A, 0x06/*)*/,
65444 /* 204797 */ GIR_MakeTempReg, /*TempRegID*//* 776(*/0x88, 0x06/*)*/, /*TypeID*/GILLT_s64,
65445 /* 204801 */ GIR_BuildMI, /*InsnID*//* 777(*/0x89, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65446 /* 204806 */ GIR_AddTempRegister, /*InsnID*//* 777(*/0x89, 0x06/*)*/, /*TempRegID*//* 776(*/0x88, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65447 /* 204813 */ GIR_AddSimpleTempRegister, /*InsnID*//* 777(*/0x89, 0x06/*)*/, /*TempRegID*//* 777(*/0x89, 0x06/*)*/,
65448 /* 204818 */ GIR_AddImm, /*InsnID*//* 777(*/0x89, 0x06/*)*/, /*Imm*/GIMT_Encode8(13107),
65449 /* 204829 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 777(*/0x89, 0x06/*)*/,
65450 /* 204832 */ GIR_MakeTempReg, /*TempRegID*//* 775(*/0x87, 0x06/*)*/, /*TypeID*/GILLT_s32,
65451 /* 204836 */ GIR_BuildMI, /*InsnID*//* 776(*/0x88, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65452 /* 204841 */ GIR_AddTempRegister, /*InsnID*//* 776(*/0x88, 0x06/*)*/, /*TempRegID*//* 775(*/0x87, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65453 /* 204848 */ GIR_AddImm, /*InsnID*//* 776(*/0x88, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690),
65454 /* 204859 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 776(*/0x88, 0x06/*)*/,
65455 /* 204862 */ GIR_MakeTempReg, /*TempRegID*//* 774(*/0x86, 0x06/*)*/, /*TypeID*/GILLT_s32,
65456 /* 204866 */ GIR_BuildMI, /*InsnID*//* 775(*/0x87, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65457 /* 204871 */ GIR_AddTempRegister, /*InsnID*//* 775(*/0x87, 0x06/*)*/, /*TempRegID*//* 774(*/0x86, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65458 /* 204878 */ GIR_AddSimpleTempRegister, /*InsnID*//* 775(*/0x87, 0x06/*)*/, /*TempRegID*//* 775(*/0x87, 0x06/*)*/,
65459 /* 204883 */ GIR_AddImm, /*InsnID*//* 775(*/0x87, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690),
65460 /* 204894 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 775(*/0x87, 0x06/*)*/,
65461 /* 204897 */ GIR_MakeTempReg, /*TempRegID*//* 773(*/0x85, 0x06/*)*/, /*TypeID*/GILLT_s64,
65462 /* 204901 */ GIR_BuildMI, /*InsnID*//* 774(*/0x86, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65463 /* 204906 */ GIR_AddTempRegister, /*InsnID*//* 774(*/0x86, 0x06/*)*/, /*TempRegID*//* 773(*/0x85, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65464 /* 204913 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 774(*/0x86, 0x06/*)*/,
65465 /* 204916 */ GIR_MakeTempReg, /*TempRegID*//* 772(*/0x84, 0x06/*)*/, /*TypeID*/GILLT_s64,
65466 /* 204920 */ GIR_BuildMI, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65467 /* 204925 */ GIR_AddTempRegister, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*TempRegID*//* 772(*/0x84, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65468 /* 204932 */ GIR_AddSimpleTempRegister, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*TempRegID*//* 773(*/0x85, 0x06/*)*/,
65469 /* 204937 */ GIR_AddSimpleTempRegister, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*TempRegID*//* 774(*/0x86, 0x06/*)*/,
65470 /* 204942 */ GIR_AddImm8, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Imm*/1,
65471 /* 204946 */ GIR_ConstrainOperandRC, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65472 /* 204952 */ GIR_ConstrainOperandRC, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65473 /* 204958 */ GIR_ConstrainOperandRC, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65474 /* 204964 */ GIR_MakeTempReg, /*TempRegID*//* 771(*/0x83, 0x06/*)*/, /*TypeID*/GILLT_s64,
65475 /* 204968 */ GIR_BuildMI, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65476 /* 204973 */ GIR_AddTempRegister, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*TempRegID*//* 771(*/0x83, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65477 /* 204980 */ GIR_AddSimpleTempRegister, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*TempRegID*//* 772(*/0x84, 0x06/*)*/,
65478 /* 204985 */ GIR_AddImm8, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*Imm*/32,
65479 /* 204989 */ GIR_AddImm8, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*Imm*/31,
65480 /* 204993 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 772(*/0x84, 0x06/*)*/,
65481 /* 204996 */ GIR_MakeTempReg, /*TempRegID*//* 770(*/0x82, 0x06/*)*/, /*TypeID*/GILLT_s64,
65482 /* 205000 */ GIR_BuildMI, /*InsnID*//* 771(*/0x83, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65483 /* 205005 */ GIR_AddTempRegister, /*InsnID*//* 771(*/0x83, 0x06/*)*/, /*TempRegID*//* 770(*/0x82, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65484 /* 205012 */ GIR_AddSimpleTempRegister, /*InsnID*//* 771(*/0x83, 0x06/*)*/, /*TempRegID*//* 771(*/0x83, 0x06/*)*/,
65485 /* 205017 */ GIR_AddImm, /*InsnID*//* 771(*/0x83, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690),
65486 /* 205028 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 771(*/0x83, 0x06/*)*/,
65487 /* 205031 */ GIR_MakeTempReg, /*TempRegID*//* 769(*/0x81, 0x06/*)*/, /*TypeID*/GILLT_s64,
65488 /* 205035 */ GIR_BuildMI, /*InsnID*//* 770(*/0x82, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65489 /* 205040 */ GIR_AddTempRegister, /*InsnID*//* 770(*/0x82, 0x06/*)*/, /*TempRegID*//* 769(*/0x81, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65490 /* 205047 */ GIR_AddSimpleTempRegister, /*InsnID*//* 770(*/0x82, 0x06/*)*/, /*TempRegID*//* 770(*/0x82, 0x06/*)*/,
65491 /* 205052 */ GIR_AddImm, /*InsnID*//* 770(*/0x82, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690),
65492 /* 205063 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 770(*/0x82, 0x06/*)*/,
65493 /* 205066 */ GIR_MakeTempReg, /*TempRegID*//* 768(*/0x80, 0x06/*)*/, /*TypeID*/GILLT_s64,
65494 /* 205070 */ GIR_BuildMI, /*InsnID*//* 769(*/0x81, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65495 /* 205075 */ GIR_AddTempRegister, /*InsnID*//* 769(*/0x81, 0x06/*)*/, /*TempRegID*//* 768(*/0x80, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65496 /* 205082 */ GIR_Copy, /*NewInsnID*//* 769(*/0x81, 0x06/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65497 /* 205087 */ GIR_AddImm8, /*InsnID*//* 769(*/0x81, 0x06/*)*/, /*Imm*/1,
65498 /* 205091 */ GIR_AddImm8, /*InsnID*//* 769(*/0x81, 0x06/*)*/, /*Imm*/62,
65499 /* 205095 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 769(*/0x81, 0x06/*)*/,
65500 /* 205098 */ GIR_MakeTempReg, /*TempRegID*//* 767(*/0xFF, 0x05/*)*/, /*TypeID*/GILLT_s64,
65501 /* 205102 */ GIR_BuildMI, /*InsnID*//* 768(*/0x80, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65502 /* 205107 */ GIR_AddTempRegister, /*InsnID*//* 768(*/0x80, 0x06/*)*/, /*TempRegID*//* 767(*/0xFF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65503 /* 205114 */ GIR_AddSimpleTempRegister, /*InsnID*//* 768(*/0x80, 0x06/*)*/, /*TempRegID*//* 768(*/0x80, 0x06/*)*/,
65504 /* 205119 */ GIR_AddSimpleTempRegister, /*InsnID*//* 768(*/0x80, 0x06/*)*/, /*TempRegID*//* 769(*/0x81, 0x06/*)*/,
65505 /* 205124 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 768(*/0x80, 0x06/*)*/,
65506 /* 205127 */ GIR_MakeTempReg, /*TempRegID*//* 766(*/0xFE, 0x05/*)*/, /*TypeID*/GILLT_s32,
65507 /* 205131 */ GIR_BuildMI, /*InsnID*//* 767(*/0xFF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65508 /* 205136 */ GIR_AddTempRegister, /*InsnID*//* 767(*/0xFF, 0x05/*)*/, /*TempRegID*//* 766(*/0xFE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65509 /* 205143 */ GIR_AddImm, /*InsnID*//* 767(*/0xFF, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65510 /* 205154 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 767(*/0xFF, 0x05/*)*/,
65511 /* 205157 */ GIR_MakeTempReg, /*TempRegID*//* 765(*/0xFD, 0x05/*)*/, /*TypeID*/GILLT_s32,
65512 /* 205161 */ GIR_BuildMI, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65513 /* 205166 */ GIR_AddTempRegister, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, /*TempRegID*//* 765(*/0xFD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65514 /* 205173 */ GIR_AddSimpleTempRegister, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, /*TempRegID*//* 766(*/0xFE, 0x05/*)*/,
65515 /* 205178 */ GIR_AddImm, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65516 /* 205189 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 766(*/0xFE, 0x05/*)*/,
65517 /* 205192 */ GIR_MakeTempReg, /*TempRegID*//* 764(*/0xFC, 0x05/*)*/, /*TypeID*/GILLT_s64,
65518 /* 205196 */ GIR_BuildMI, /*InsnID*//* 765(*/0xFD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65519 /* 205201 */ GIR_AddTempRegister, /*InsnID*//* 765(*/0xFD, 0x05/*)*/, /*TempRegID*//* 764(*/0xFC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65520 /* 205208 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 765(*/0xFD, 0x05/*)*/,
65521 /* 205211 */ GIR_MakeTempReg, /*TempRegID*//* 763(*/0xFB, 0x05/*)*/, /*TypeID*/GILLT_s64,
65522 /* 205215 */ GIR_BuildMI, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65523 /* 205220 */ GIR_AddTempRegister, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*TempRegID*//* 763(*/0xFB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65524 /* 205227 */ GIR_AddSimpleTempRegister, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*TempRegID*//* 764(*/0xFC, 0x05/*)*/,
65525 /* 205232 */ GIR_AddSimpleTempRegister, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*TempRegID*//* 765(*/0xFD, 0x05/*)*/,
65526 /* 205237 */ GIR_AddImm8, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Imm*/1,
65527 /* 205241 */ GIR_ConstrainOperandRC, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65528 /* 205247 */ GIR_ConstrainOperandRC, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65529 /* 205253 */ GIR_ConstrainOperandRC, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65530 /* 205259 */ GIR_MakeTempReg, /*TempRegID*//* 762(*/0xFA, 0x05/*)*/, /*TypeID*/GILLT_s64,
65531 /* 205263 */ GIR_BuildMI, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65532 /* 205268 */ GIR_AddTempRegister, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*TempRegID*//* 762(*/0xFA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65533 /* 205275 */ GIR_AddSimpleTempRegister, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*TempRegID*//* 763(*/0xFB, 0x05/*)*/,
65534 /* 205280 */ GIR_AddImm8, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*Imm*/32,
65535 /* 205284 */ GIR_AddImm8, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*Imm*/31,
65536 /* 205288 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 763(*/0xFB, 0x05/*)*/,
65537 /* 205291 */ GIR_MakeTempReg, /*TempRegID*//* 761(*/0xF9, 0x05/*)*/, /*TypeID*/GILLT_s64,
65538 /* 205295 */ GIR_BuildMI, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65539 /* 205300 */ GIR_AddTempRegister, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, /*TempRegID*//* 761(*/0xF9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65540 /* 205307 */ GIR_AddSimpleTempRegister, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, /*TempRegID*//* 762(*/0xFA, 0x05/*)*/,
65541 /* 205312 */ GIR_AddImm, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65542 /* 205323 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 762(*/0xFA, 0x05/*)*/,
65543 /* 205326 */ GIR_MakeTempReg, /*TempRegID*//* 760(*/0xF8, 0x05/*)*/, /*TypeID*/GILLT_s64,
65544 /* 205330 */ GIR_BuildMI, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65545 /* 205335 */ GIR_AddTempRegister, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, /*TempRegID*//* 760(*/0xF8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65546 /* 205342 */ GIR_AddSimpleTempRegister, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, /*TempRegID*//* 761(*/0xF9, 0x05/*)*/,
65547 /* 205347 */ GIR_AddImm, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65548 /* 205358 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 761(*/0xF9, 0x05/*)*/,
65549 /* 205361 */ GIR_MakeTempReg, /*TempRegID*//* 759(*/0xF7, 0x05/*)*/, /*TypeID*/GILLT_s64,
65550 /* 205365 */ GIR_BuildMI, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65551 /* 205370 */ GIR_AddTempRegister, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, /*TempRegID*//* 759(*/0xF7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65552 /* 205377 */ GIR_Copy, /*NewInsnID*//* 760(*/0xF8, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65553 /* 205382 */ GIR_AddImm8, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, /*Imm*/63,
65554 /* 205386 */ GIR_AddImm8, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, /*Imm*/1,
65555 /* 205390 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 760(*/0xF8, 0x05/*)*/,
65556 /* 205393 */ GIR_MakeTempReg, /*TempRegID*//* 758(*/0xF6, 0x05/*)*/, /*TypeID*/GILLT_s64,
65557 /* 205397 */ GIR_BuildMI, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65558 /* 205402 */ GIR_AddTempRegister, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, /*TempRegID*//* 758(*/0xF6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65559 /* 205409 */ GIR_AddSimpleTempRegister, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, /*TempRegID*//* 759(*/0xF7, 0x05/*)*/,
65560 /* 205414 */ GIR_AddSimpleTempRegister, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, /*TempRegID*//* 760(*/0xF8, 0x05/*)*/,
65561 /* 205419 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 759(*/0xF7, 0x05/*)*/,
65562 /* 205422 */ GIR_MakeTempReg, /*TempRegID*//* 757(*/0xF5, 0x05/*)*/, /*TypeID*/GILLT_s64,
65563 /* 205426 */ GIR_BuildMI, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65564 /* 205431 */ GIR_AddTempRegister, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, /*TempRegID*//* 757(*/0xF5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65565 /* 205438 */ GIR_AddSimpleTempRegister, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, /*TempRegID*//* 758(*/0xF6, 0x05/*)*/,
65566 /* 205443 */ GIR_AddSimpleTempRegister, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, /*TempRegID*//* 767(*/0xFF, 0x05/*)*/,
65567 /* 205448 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 758(*/0xF6, 0x05/*)*/,
65568 /* 205451 */ GIR_MakeTempReg, /*TempRegID*//* 756(*/0xF4, 0x05/*)*/, /*TypeID*/GILLT_s64,
65569 /* 205455 */ GIR_BuildMI, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65570 /* 205460 */ GIR_AddTempRegister, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*TempRegID*//* 756(*/0xF4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65571 /* 205467 */ GIR_AddSimpleTempRegister, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*TempRegID*//* 757(*/0xF5, 0x05/*)*/,
65572 /* 205472 */ GIR_AddImm8, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*Imm*/62,
65573 /* 205476 */ GIR_AddImm8, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*Imm*/2,
65574 /* 205480 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 757(*/0xF5, 0x05/*)*/,
65575 /* 205483 */ GIR_MakeTempReg, /*TempRegID*//* 755(*/0xF3, 0x05/*)*/, /*TypeID*/GILLT_s64,
65576 /* 205487 */ GIR_BuildMI, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65577 /* 205492 */ GIR_AddTempRegister, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, /*TempRegID*//* 755(*/0xF3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65578 /* 205499 */ GIR_AddSimpleTempRegister, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, /*TempRegID*//* 756(*/0xF4, 0x05/*)*/,
65579 /* 205504 */ GIR_AddSimpleTempRegister, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, /*TempRegID*//* 776(*/0x88, 0x06/*)*/,
65580 /* 205509 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 756(*/0xF4, 0x05/*)*/,
65581 /* 205512 */ GIR_MakeTempReg, /*TempRegID*//* 754(*/0xF2, 0x05/*)*/, /*TypeID*/GILLT_s64,
65582 /* 205516 */ GIR_BuildMI, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65583 /* 205521 */ GIR_AddTempRegister, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, /*TempRegID*//* 754(*/0xF2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65584 /* 205528 */ GIR_AddSimpleTempRegister, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, /*TempRegID*//* 755(*/0xF3, 0x05/*)*/,
65585 /* 205533 */ GIR_AddSimpleTempRegister, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, /*TempRegID*//* 783(*/0x8F, 0x06/*)*/,
65586 /* 205538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 755(*/0xF3, 0x05/*)*/,
65587 /* 205541 */ GIR_MakeTempReg, /*TempRegID*//* 753(*/0xF1, 0x05/*)*/, /*TypeID*/GILLT_s64,
65588 /* 205545 */ GIR_BuildMI, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65589 /* 205550 */ GIR_AddTempRegister, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*TempRegID*//* 753(*/0xF1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65590 /* 205557 */ GIR_AddSimpleTempRegister, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*TempRegID*//* 754(*/0xF2, 0x05/*)*/,
65591 /* 205562 */ GIR_AddImm8, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*Imm*/4,
65592 /* 205566 */ GIR_AddImm8, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*Imm*/59,
65593 /* 205570 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 754(*/0xF2, 0x05/*)*/,
65594 /* 205573 */ GIR_MakeTempReg, /*TempRegID*//* 752(*/0xF0, 0x05/*)*/, /*TypeID*/GILLT_s64,
65595 /* 205577 */ GIR_BuildMI, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65596 /* 205582 */ GIR_AddTempRegister, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, /*TempRegID*//* 752(*/0xF0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65597 /* 205589 */ GIR_AddSimpleTempRegister, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, /*TempRegID*//* 753(*/0xF1, 0x05/*)*/,
65598 /* 205594 */ GIR_AddSimpleTempRegister, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, /*TempRegID*//* 811(*/0xAB, 0x06/*)*/,
65599 /* 205599 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 753(*/0xF1, 0x05/*)*/,
65600 /* 205602 */ GIR_MakeTempReg, /*TempRegID*//* 751(*/0xEF, 0x05/*)*/, /*TypeID*/GILLT_s32,
65601 /* 205606 */ GIR_BuildMI, /*InsnID*//* 752(*/0xF0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65602 /* 205611 */ GIR_AddTempRegister, /*InsnID*//* 752(*/0xF0, 0x05/*)*/, /*TempRegID*//* 751(*/0xEF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65603 /* 205618 */ GIR_AddImm, /*InsnID*//* 752(*/0xF0, 0x05/*)*/, /*Imm*/GIMT_Encode8(3855),
65604 /* 205629 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 752(*/0xF0, 0x05/*)*/,
65605 /* 205632 */ GIR_MakeTempReg, /*TempRegID*//* 750(*/0xEE, 0x05/*)*/, /*TypeID*/GILLT_s32,
65606 /* 205636 */ GIR_BuildMI, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65607 /* 205641 */ GIR_AddTempRegister, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, /*TempRegID*//* 750(*/0xEE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65608 /* 205648 */ GIR_AddSimpleTempRegister, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, /*TempRegID*//* 751(*/0xEF, 0x05/*)*/,
65609 /* 205653 */ GIR_AddImm, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, /*Imm*/GIMT_Encode8(3855),
65610 /* 205664 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 751(*/0xEF, 0x05/*)*/,
65611 /* 205667 */ GIR_MakeTempReg, /*TempRegID*//* 749(*/0xED, 0x05/*)*/, /*TypeID*/GILLT_s64,
65612 /* 205671 */ GIR_BuildMI, /*InsnID*//* 750(*/0xEE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65613 /* 205676 */ GIR_AddTempRegister, /*InsnID*//* 750(*/0xEE, 0x05/*)*/, /*TempRegID*//* 749(*/0xED, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65614 /* 205683 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 750(*/0xEE, 0x05/*)*/,
65615 /* 205686 */ GIR_MakeTempReg, /*TempRegID*//* 748(*/0xEC, 0x05/*)*/, /*TypeID*/GILLT_s64,
65616 /* 205690 */ GIR_BuildMI, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65617 /* 205695 */ GIR_AddTempRegister, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*TempRegID*//* 748(*/0xEC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65618 /* 205702 */ GIR_AddSimpleTempRegister, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*TempRegID*//* 749(*/0xED, 0x05/*)*/,
65619 /* 205707 */ GIR_AddSimpleTempRegister, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*TempRegID*//* 750(*/0xEE, 0x05/*)*/,
65620 /* 205712 */ GIR_AddImm8, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Imm*/1,
65621 /* 205716 */ GIR_ConstrainOperandRC, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65622 /* 205722 */ GIR_ConstrainOperandRC, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65623 /* 205728 */ GIR_ConstrainOperandRC, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65624 /* 205734 */ GIR_MakeTempReg, /*TempRegID*//* 747(*/0xEB, 0x05/*)*/, /*TypeID*/GILLT_s64,
65625 /* 205738 */ GIR_BuildMI, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65626 /* 205743 */ GIR_AddTempRegister, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*TempRegID*//* 747(*/0xEB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65627 /* 205750 */ GIR_AddSimpleTempRegister, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*TempRegID*//* 748(*/0xEC, 0x05/*)*/,
65628 /* 205755 */ GIR_AddImm8, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*Imm*/32,
65629 /* 205759 */ GIR_AddImm8, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*Imm*/31,
65630 /* 205763 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 748(*/0xEC, 0x05/*)*/,
65631 /* 205766 */ GIR_MakeTempReg, /*TempRegID*//* 746(*/0xEA, 0x05/*)*/, /*TypeID*/GILLT_s64,
65632 /* 205770 */ GIR_BuildMI, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65633 /* 205775 */ GIR_AddTempRegister, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, /*TempRegID*//* 746(*/0xEA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65634 /* 205782 */ GIR_AddSimpleTempRegister, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, /*TempRegID*//* 747(*/0xEB, 0x05/*)*/,
65635 /* 205787 */ GIR_AddImm, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, /*Imm*/GIMT_Encode8(3855),
65636 /* 205798 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 747(*/0xEB, 0x05/*)*/,
65637 /* 205801 */ GIR_MakeTempReg, /*TempRegID*//* 745(*/0xE9, 0x05/*)*/, /*TypeID*/GILLT_s64,
65638 /* 205805 */ GIR_BuildMI, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65639 /* 205810 */ GIR_AddTempRegister, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, /*TempRegID*//* 745(*/0xE9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65640 /* 205817 */ GIR_AddSimpleTempRegister, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, /*TempRegID*//* 746(*/0xEA, 0x05/*)*/,
65641 /* 205822 */ GIR_AddImm, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, /*Imm*/GIMT_Encode8(3855),
65642 /* 205833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 746(*/0xEA, 0x05/*)*/,
65643 /* 205836 */ GIR_MakeTempReg, /*TempRegID*//* 744(*/0xE8, 0x05/*)*/, /*TypeID*/GILLT_s32,
65644 /* 205840 */ GIR_BuildMI, /*InsnID*//* 745(*/0xE9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65645 /* 205845 */ GIR_AddTempRegister, /*InsnID*//* 745(*/0xE9, 0x05/*)*/, /*TempRegID*//* 744(*/0xE8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65646 /* 205852 */ GIR_AddImm, /*InsnID*//* 745(*/0xE9, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428),
65647 /* 205863 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 745(*/0xE9, 0x05/*)*/,
65648 /* 205866 */ GIR_MakeTempReg, /*TempRegID*//* 743(*/0xE7, 0x05/*)*/, /*TypeID*/GILLT_s32,
65649 /* 205870 */ GIR_BuildMI, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65650 /* 205875 */ GIR_AddTempRegister, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, /*TempRegID*//* 743(*/0xE7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65651 /* 205882 */ GIR_AddSimpleTempRegister, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, /*TempRegID*//* 744(*/0xE8, 0x05/*)*/,
65652 /* 205887 */ GIR_AddImm, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428),
65653 /* 205898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 744(*/0xE8, 0x05/*)*/,
65654 /* 205901 */ GIR_MakeTempReg, /*TempRegID*//* 742(*/0xE6, 0x05/*)*/, /*TypeID*/GILLT_s64,
65655 /* 205905 */ GIR_BuildMI, /*InsnID*//* 743(*/0xE7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65656 /* 205910 */ GIR_AddTempRegister, /*InsnID*//* 743(*/0xE7, 0x05/*)*/, /*TempRegID*//* 742(*/0xE6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65657 /* 205917 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 743(*/0xE7, 0x05/*)*/,
65658 /* 205920 */ GIR_MakeTempReg, /*TempRegID*//* 741(*/0xE5, 0x05/*)*/, /*TypeID*/GILLT_s64,
65659 /* 205924 */ GIR_BuildMI, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65660 /* 205929 */ GIR_AddTempRegister, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*TempRegID*//* 741(*/0xE5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65661 /* 205936 */ GIR_AddSimpleTempRegister, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*TempRegID*//* 742(*/0xE6, 0x05/*)*/,
65662 /* 205941 */ GIR_AddSimpleTempRegister, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*TempRegID*//* 743(*/0xE7, 0x05/*)*/,
65663 /* 205946 */ GIR_AddImm8, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Imm*/1,
65664 /* 205950 */ GIR_ConstrainOperandRC, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65665 /* 205956 */ GIR_ConstrainOperandRC, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65666 /* 205962 */ GIR_ConstrainOperandRC, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65667 /* 205968 */ GIR_MakeTempReg, /*TempRegID*//* 740(*/0xE4, 0x05/*)*/, /*TypeID*/GILLT_s64,
65668 /* 205972 */ GIR_BuildMI, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65669 /* 205977 */ GIR_AddTempRegister, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*TempRegID*//* 740(*/0xE4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65670 /* 205984 */ GIR_AddSimpleTempRegister, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*TempRegID*//* 741(*/0xE5, 0x05/*)*/,
65671 /* 205989 */ GIR_AddImm8, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*Imm*/32,
65672 /* 205993 */ GIR_AddImm8, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*Imm*/31,
65673 /* 205997 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 741(*/0xE5, 0x05/*)*/,
65674 /* 206000 */ GIR_MakeTempReg, /*TempRegID*//* 739(*/0xE3, 0x05/*)*/, /*TypeID*/GILLT_s64,
65675 /* 206004 */ GIR_BuildMI, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65676 /* 206009 */ GIR_AddTempRegister, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, /*TempRegID*//* 739(*/0xE3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65677 /* 206016 */ GIR_AddSimpleTempRegister, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, /*TempRegID*//* 740(*/0xE4, 0x05/*)*/,
65678 /* 206021 */ GIR_AddImm, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428),
65679 /* 206032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 740(*/0xE4, 0x05/*)*/,
65680 /* 206035 */ GIR_MakeTempReg, /*TempRegID*//* 738(*/0xE2, 0x05/*)*/, /*TypeID*/GILLT_s64,
65681 /* 206039 */ GIR_BuildMI, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65682 /* 206044 */ GIR_AddTempRegister, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, /*TempRegID*//* 738(*/0xE2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65683 /* 206051 */ GIR_AddSimpleTempRegister, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, /*TempRegID*//* 739(*/0xE3, 0x05/*)*/,
65684 /* 206056 */ GIR_AddImm, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428),
65685 /* 206067 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 739(*/0xE3, 0x05/*)*/,
65686 /* 206070 */ GIR_MakeTempReg, /*TempRegID*//* 737(*/0xE1, 0x05/*)*/, /*TypeID*/GILLT_s32,
65687 /* 206074 */ GIR_BuildMI, /*InsnID*//* 738(*/0xE2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65688 /* 206079 */ GIR_AddTempRegister, /*InsnID*//* 738(*/0xE2, 0x05/*)*/, /*TempRegID*//* 737(*/0xE1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65689 /* 206086 */ GIR_AddImm, /*InsnID*//* 738(*/0xE2, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
65690 /* 206097 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 738(*/0xE2, 0x05/*)*/,
65691 /* 206100 */ GIR_MakeTempReg, /*TempRegID*//* 736(*/0xE0, 0x05/*)*/, /*TypeID*/GILLT_s32,
65692 /* 206104 */ GIR_BuildMI, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65693 /* 206109 */ GIR_AddTempRegister, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, /*TempRegID*//* 736(*/0xE0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65694 /* 206116 */ GIR_AddSimpleTempRegister, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, /*TempRegID*//* 737(*/0xE1, 0x05/*)*/,
65695 /* 206121 */ GIR_AddImm, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
65696 /* 206132 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 737(*/0xE1, 0x05/*)*/,
65697 /* 206135 */ GIR_MakeTempReg, /*TempRegID*//* 735(*/0xDF, 0x05/*)*/, /*TypeID*/GILLT_s64,
65698 /* 206139 */ GIR_BuildMI, /*InsnID*//* 736(*/0xE0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65699 /* 206144 */ GIR_AddTempRegister, /*InsnID*//* 736(*/0xE0, 0x05/*)*/, /*TempRegID*//* 735(*/0xDF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65700 /* 206151 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 736(*/0xE0, 0x05/*)*/,
65701 /* 206154 */ GIR_MakeTempReg, /*TempRegID*//* 734(*/0xDE, 0x05/*)*/, /*TypeID*/GILLT_s64,
65702 /* 206158 */ GIR_BuildMI, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65703 /* 206163 */ GIR_AddTempRegister, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*TempRegID*//* 734(*/0xDE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65704 /* 206170 */ GIR_AddSimpleTempRegister, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*TempRegID*//* 735(*/0xDF, 0x05/*)*/,
65705 /* 206175 */ GIR_AddSimpleTempRegister, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*TempRegID*//* 736(*/0xE0, 0x05/*)*/,
65706 /* 206180 */ GIR_AddImm8, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Imm*/1,
65707 /* 206184 */ GIR_ConstrainOperandRC, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65708 /* 206190 */ GIR_ConstrainOperandRC, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65709 /* 206196 */ GIR_ConstrainOperandRC, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65710 /* 206202 */ GIR_MakeTempReg, /*TempRegID*//* 733(*/0xDD, 0x05/*)*/, /*TypeID*/GILLT_s64,
65711 /* 206206 */ GIR_BuildMI, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65712 /* 206211 */ GIR_AddTempRegister, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*TempRegID*//* 733(*/0xDD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65713 /* 206218 */ GIR_AddSimpleTempRegister, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*TempRegID*//* 734(*/0xDE, 0x05/*)*/,
65714 /* 206223 */ GIR_AddImm8, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*Imm*/32,
65715 /* 206227 */ GIR_AddImm8, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*Imm*/31,
65716 /* 206231 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 734(*/0xDE, 0x05/*)*/,
65717 /* 206234 */ GIR_MakeTempReg, /*TempRegID*//* 732(*/0xDC, 0x05/*)*/, /*TypeID*/GILLT_s64,
65718 /* 206238 */ GIR_BuildMI, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65719 /* 206243 */ GIR_AddTempRegister, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, /*TempRegID*//* 732(*/0xDC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65720 /* 206250 */ GIR_AddSimpleTempRegister, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, /*TempRegID*//* 733(*/0xDD, 0x05/*)*/,
65721 /* 206255 */ GIR_AddImm, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
65722 /* 206266 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 733(*/0xDD, 0x05/*)*/,
65723 /* 206269 */ GIR_MakeTempReg, /*TempRegID*//* 731(*/0xDB, 0x05/*)*/, /*TypeID*/GILLT_s64,
65724 /* 206273 */ GIR_BuildMI, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65725 /* 206278 */ GIR_AddTempRegister, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, /*TempRegID*//* 731(*/0xDB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65726 /* 206285 */ GIR_AddSimpleTempRegister, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, /*TempRegID*//* 732(*/0xDC, 0x05/*)*/,
65727 /* 206290 */ GIR_AddImm, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
65728 /* 206301 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 732(*/0xDC, 0x05/*)*/,
65729 /* 206304 */ GIR_MakeTempReg, /*TempRegID*//* 730(*/0xDA, 0x05/*)*/, /*TypeID*/GILLT_s64,
65730 /* 206308 */ GIR_BuildMI, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65731 /* 206313 */ GIR_AddTempRegister, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, /*TempRegID*//* 730(*/0xDA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65732 /* 206320 */ GIR_Copy, /*NewInsnID*//* 731(*/0xDB, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65733 /* 206325 */ GIR_AddImm8, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, /*Imm*/1,
65734 /* 206329 */ GIR_AddImm8, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, /*Imm*/62,
65735 /* 206333 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 731(*/0xDB, 0x05/*)*/,
65736 /* 206336 */ GIR_MakeTempReg, /*TempRegID*//* 729(*/0xD9, 0x05/*)*/, /*TypeID*/GILLT_s64,
65737 /* 206340 */ GIR_BuildMI, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65738 /* 206345 */ GIR_AddTempRegister, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, /*TempRegID*//* 729(*/0xD9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65739 /* 206352 */ GIR_AddSimpleTempRegister, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, /*TempRegID*//* 730(*/0xDA, 0x05/*)*/,
65740 /* 206357 */ GIR_AddSimpleTempRegister, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, /*TempRegID*//* 731(*/0xDB, 0x05/*)*/,
65741 /* 206362 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 730(*/0xDA, 0x05/*)*/,
65742 /* 206365 */ GIR_MakeTempReg, /*TempRegID*//* 728(*/0xD8, 0x05/*)*/, /*TypeID*/GILLT_s32,
65743 /* 206369 */ GIR_BuildMI, /*InsnID*//* 729(*/0xD9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65744 /* 206374 */ GIR_AddTempRegister, /*InsnID*//* 729(*/0xD9, 0x05/*)*/, /*TempRegID*//* 728(*/0xD8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65745 /* 206381 */ GIR_AddImm, /*InsnID*//* 729(*/0xD9, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65746 /* 206392 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 729(*/0xD9, 0x05/*)*/,
65747 /* 206395 */ GIR_MakeTempReg, /*TempRegID*//* 727(*/0xD7, 0x05/*)*/, /*TypeID*/GILLT_s32,
65748 /* 206399 */ GIR_BuildMI, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65749 /* 206404 */ GIR_AddTempRegister, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, /*TempRegID*//* 727(*/0xD7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65750 /* 206411 */ GIR_AddSimpleTempRegister, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, /*TempRegID*//* 728(*/0xD8, 0x05/*)*/,
65751 /* 206416 */ GIR_AddImm, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65752 /* 206427 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 728(*/0xD8, 0x05/*)*/,
65753 /* 206430 */ GIR_MakeTempReg, /*TempRegID*//* 726(*/0xD6, 0x05/*)*/, /*TypeID*/GILLT_s64,
65754 /* 206434 */ GIR_BuildMI, /*InsnID*//* 727(*/0xD7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65755 /* 206439 */ GIR_AddTempRegister, /*InsnID*//* 727(*/0xD7, 0x05/*)*/, /*TempRegID*//* 726(*/0xD6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65756 /* 206446 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 727(*/0xD7, 0x05/*)*/,
65757 /* 206449 */ GIR_MakeTempReg, /*TempRegID*//* 725(*/0xD5, 0x05/*)*/, /*TypeID*/GILLT_s64,
65758 /* 206453 */ GIR_BuildMI, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65759 /* 206458 */ GIR_AddTempRegister, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*TempRegID*//* 725(*/0xD5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65760 /* 206465 */ GIR_AddSimpleTempRegister, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*TempRegID*//* 726(*/0xD6, 0x05/*)*/,
65761 /* 206470 */ GIR_AddSimpleTempRegister, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*TempRegID*//* 727(*/0xD7, 0x05/*)*/,
65762 /* 206475 */ GIR_AddImm8, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Imm*/1,
65763 /* 206479 */ GIR_ConstrainOperandRC, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65764 /* 206485 */ GIR_ConstrainOperandRC, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65765 /* 206491 */ GIR_ConstrainOperandRC, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65766 /* 206497 */ GIR_MakeTempReg, /*TempRegID*//* 724(*/0xD4, 0x05/*)*/, /*TypeID*/GILLT_s64,
65767 /* 206501 */ GIR_BuildMI, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65768 /* 206506 */ GIR_AddTempRegister, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*TempRegID*//* 724(*/0xD4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65769 /* 206513 */ GIR_AddSimpleTempRegister, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*TempRegID*//* 725(*/0xD5, 0x05/*)*/,
65770 /* 206518 */ GIR_AddImm8, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*Imm*/32,
65771 /* 206522 */ GIR_AddImm8, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*Imm*/31,
65772 /* 206526 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 725(*/0xD5, 0x05/*)*/,
65773 /* 206529 */ GIR_MakeTempReg, /*TempRegID*//* 723(*/0xD3, 0x05/*)*/, /*TypeID*/GILLT_s64,
65774 /* 206533 */ GIR_BuildMI, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65775 /* 206538 */ GIR_AddTempRegister, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, /*TempRegID*//* 723(*/0xD3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65776 /* 206545 */ GIR_AddSimpleTempRegister, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, /*TempRegID*//* 724(*/0xD4, 0x05/*)*/,
65777 /* 206550 */ GIR_AddImm, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65778 /* 206561 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 724(*/0xD4, 0x05/*)*/,
65779 /* 206564 */ GIR_MakeTempReg, /*TempRegID*//* 722(*/0xD2, 0x05/*)*/, /*TypeID*/GILLT_s64,
65780 /* 206568 */ GIR_BuildMI, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65781 /* 206573 */ GIR_AddTempRegister, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, /*TempRegID*//* 722(*/0xD2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65782 /* 206580 */ GIR_AddSimpleTempRegister, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, /*TempRegID*//* 723(*/0xD3, 0x05/*)*/,
65783 /* 206585 */ GIR_AddImm, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65784 /* 206596 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 723(*/0xD3, 0x05/*)*/,
65785 /* 206599 */ GIR_MakeTempReg, /*TempRegID*//* 721(*/0xD1, 0x05/*)*/, /*TypeID*/GILLT_s64,
65786 /* 206603 */ GIR_BuildMI, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65787 /* 206608 */ GIR_AddTempRegister, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, /*TempRegID*//* 721(*/0xD1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65788 /* 206615 */ GIR_Copy, /*NewInsnID*//* 722(*/0xD2, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65789 /* 206620 */ GIR_AddImm8, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, /*Imm*/63,
65790 /* 206624 */ GIR_AddImm8, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, /*Imm*/1,
65791 /* 206628 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 722(*/0xD2, 0x05/*)*/,
65792 /* 206631 */ GIR_MakeTempReg, /*TempRegID*//* 720(*/0xD0, 0x05/*)*/, /*TypeID*/GILLT_s64,
65793 /* 206635 */ GIR_BuildMI, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65794 /* 206640 */ GIR_AddTempRegister, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, /*TempRegID*//* 720(*/0xD0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65795 /* 206647 */ GIR_AddSimpleTempRegister, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, /*TempRegID*//* 721(*/0xD1, 0x05/*)*/,
65796 /* 206652 */ GIR_AddSimpleTempRegister, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, /*TempRegID*//* 722(*/0xD2, 0x05/*)*/,
65797 /* 206657 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 721(*/0xD1, 0x05/*)*/,
65798 /* 206660 */ GIR_MakeTempReg, /*TempRegID*//* 719(*/0xCF, 0x05/*)*/, /*TypeID*/GILLT_s64,
65799 /* 206664 */ GIR_BuildMI, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65800 /* 206669 */ GIR_AddTempRegister, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, /*TempRegID*//* 719(*/0xCF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65801 /* 206676 */ GIR_AddSimpleTempRegister, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, /*TempRegID*//* 720(*/0xD0, 0x05/*)*/,
65802 /* 206681 */ GIR_AddSimpleTempRegister, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, /*TempRegID*//* 729(*/0xD9, 0x05/*)*/,
65803 /* 206686 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 720(*/0xD0, 0x05/*)*/,
65804 /* 206689 */ GIR_MakeTempReg, /*TempRegID*//* 718(*/0xCE, 0x05/*)*/, /*TypeID*/GILLT_s64,
65805 /* 206693 */ GIR_BuildMI, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65806 /* 206698 */ GIR_AddTempRegister, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*TempRegID*//* 718(*/0xCE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65807 /* 206705 */ GIR_AddSimpleTempRegister, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*TempRegID*//* 719(*/0xCF, 0x05/*)*/,
65808 /* 206710 */ GIR_AddImm8, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*Imm*/2,
65809 /* 206714 */ GIR_AddImm8, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*Imm*/61,
65810 /* 206718 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 719(*/0xCF, 0x05/*)*/,
65811 /* 206721 */ GIR_MakeTempReg, /*TempRegID*//* 717(*/0xCD, 0x05/*)*/, /*TypeID*/GILLT_s64,
65812 /* 206725 */ GIR_BuildMI, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65813 /* 206730 */ GIR_AddTempRegister, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, /*TempRegID*//* 717(*/0xCD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65814 /* 206737 */ GIR_AddSimpleTempRegister, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, /*TempRegID*//* 718(*/0xCE, 0x05/*)*/,
65815 /* 206742 */ GIR_AddSimpleTempRegister, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, /*TempRegID*//* 738(*/0xE2, 0x05/*)*/,
65816 /* 206747 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 718(*/0xCE, 0x05/*)*/,
65817 /* 206750 */ GIR_MakeTempReg, /*TempRegID*//* 716(*/0xCC, 0x05/*)*/, /*TypeID*/GILLT_s32,
65818 /* 206754 */ GIR_BuildMI, /*InsnID*//* 717(*/0xCD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65819 /* 206759 */ GIR_AddTempRegister, /*InsnID*//* 717(*/0xCD, 0x05/*)*/, /*TempRegID*//* 716(*/0xCC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65820 /* 206766 */ GIR_AddImm, /*InsnID*//* 717(*/0xCD, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107),
65821 /* 206777 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 717(*/0xCD, 0x05/*)*/,
65822 /* 206780 */ GIR_MakeTempReg, /*TempRegID*//* 715(*/0xCB, 0x05/*)*/, /*TypeID*/GILLT_s32,
65823 /* 206784 */ GIR_BuildMI, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65824 /* 206789 */ GIR_AddTempRegister, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, /*TempRegID*//* 715(*/0xCB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65825 /* 206796 */ GIR_AddSimpleTempRegister, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, /*TempRegID*//* 716(*/0xCC, 0x05/*)*/,
65826 /* 206801 */ GIR_AddImm, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107),
65827 /* 206812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 716(*/0xCC, 0x05/*)*/,
65828 /* 206815 */ GIR_MakeTempReg, /*TempRegID*//* 714(*/0xCA, 0x05/*)*/, /*TypeID*/GILLT_s64,
65829 /* 206819 */ GIR_BuildMI, /*InsnID*//* 715(*/0xCB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65830 /* 206824 */ GIR_AddTempRegister, /*InsnID*//* 715(*/0xCB, 0x05/*)*/, /*TempRegID*//* 714(*/0xCA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65831 /* 206831 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 715(*/0xCB, 0x05/*)*/,
65832 /* 206834 */ GIR_MakeTempReg, /*TempRegID*//* 713(*/0xC9, 0x05/*)*/, /*TypeID*/GILLT_s64,
65833 /* 206838 */ GIR_BuildMI, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65834 /* 206843 */ GIR_AddTempRegister, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*TempRegID*//* 713(*/0xC9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65835 /* 206850 */ GIR_AddSimpleTempRegister, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*TempRegID*//* 714(*/0xCA, 0x05/*)*/,
65836 /* 206855 */ GIR_AddSimpleTempRegister, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*TempRegID*//* 715(*/0xCB, 0x05/*)*/,
65837 /* 206860 */ GIR_AddImm8, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Imm*/1,
65838 /* 206864 */ GIR_ConstrainOperandRC, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65839 /* 206870 */ GIR_ConstrainOperandRC, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65840 /* 206876 */ GIR_ConstrainOperandRC, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65841 /* 206882 */ GIR_MakeTempReg, /*TempRegID*//* 712(*/0xC8, 0x05/*)*/, /*TypeID*/GILLT_s64,
65842 /* 206886 */ GIR_BuildMI, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65843 /* 206891 */ GIR_AddTempRegister, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*TempRegID*//* 712(*/0xC8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65844 /* 206898 */ GIR_AddSimpleTempRegister, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*TempRegID*//* 713(*/0xC9, 0x05/*)*/,
65845 /* 206903 */ GIR_AddImm8, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*Imm*/32,
65846 /* 206907 */ GIR_AddImm8, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*Imm*/31,
65847 /* 206911 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 713(*/0xC9, 0x05/*)*/,
65848 /* 206914 */ GIR_MakeTempReg, /*TempRegID*//* 711(*/0xC7, 0x05/*)*/, /*TypeID*/GILLT_s64,
65849 /* 206918 */ GIR_BuildMI, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65850 /* 206923 */ GIR_AddTempRegister, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, /*TempRegID*//* 711(*/0xC7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65851 /* 206930 */ GIR_AddSimpleTempRegister, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, /*TempRegID*//* 712(*/0xC8, 0x05/*)*/,
65852 /* 206935 */ GIR_AddImm, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107),
65853 /* 206946 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 712(*/0xC8, 0x05/*)*/,
65854 /* 206949 */ GIR_MakeTempReg, /*TempRegID*//* 710(*/0xC6, 0x05/*)*/, /*TypeID*/GILLT_s64,
65855 /* 206953 */ GIR_BuildMI, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65856 /* 206958 */ GIR_AddTempRegister, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, /*TempRegID*//* 710(*/0xC6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65857 /* 206965 */ GIR_AddSimpleTempRegister, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, /*TempRegID*//* 711(*/0xC7, 0x05/*)*/,
65858 /* 206970 */ GIR_AddImm, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107),
65859 /* 206981 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 711(*/0xC7, 0x05/*)*/,
65860 /* 206984 */ GIR_MakeTempReg, /*TempRegID*//* 709(*/0xC5, 0x05/*)*/, /*TypeID*/GILLT_s32,
65861 /* 206988 */ GIR_BuildMI, /*InsnID*//* 710(*/0xC6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65862 /* 206993 */ GIR_AddTempRegister, /*InsnID*//* 710(*/0xC6, 0x05/*)*/, /*TempRegID*//* 709(*/0xC5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65863 /* 207000 */ GIR_AddImm, /*InsnID*//* 710(*/0xC6, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
65864 /* 207011 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 710(*/0xC6, 0x05/*)*/,
65865 /* 207014 */ GIR_MakeTempReg, /*TempRegID*//* 708(*/0xC4, 0x05/*)*/, /*TypeID*/GILLT_s32,
65866 /* 207018 */ GIR_BuildMI, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65867 /* 207023 */ GIR_AddTempRegister, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, /*TempRegID*//* 708(*/0xC4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65868 /* 207030 */ GIR_AddSimpleTempRegister, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, /*TempRegID*//* 709(*/0xC5, 0x05/*)*/,
65869 /* 207035 */ GIR_AddImm, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
65870 /* 207046 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 709(*/0xC5, 0x05/*)*/,
65871 /* 207049 */ GIR_MakeTempReg, /*TempRegID*//* 707(*/0xC3, 0x05/*)*/, /*TypeID*/GILLT_s64,
65872 /* 207053 */ GIR_BuildMI, /*InsnID*//* 708(*/0xC4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65873 /* 207058 */ GIR_AddTempRegister, /*InsnID*//* 708(*/0xC4, 0x05/*)*/, /*TempRegID*//* 707(*/0xC3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65874 /* 207065 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 708(*/0xC4, 0x05/*)*/,
65875 /* 207068 */ GIR_MakeTempReg, /*TempRegID*//* 706(*/0xC2, 0x05/*)*/, /*TypeID*/GILLT_s64,
65876 /* 207072 */ GIR_BuildMI, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65877 /* 207077 */ GIR_AddTempRegister, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*TempRegID*//* 706(*/0xC2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65878 /* 207084 */ GIR_AddSimpleTempRegister, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*TempRegID*//* 707(*/0xC3, 0x05/*)*/,
65879 /* 207089 */ GIR_AddSimpleTempRegister, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*TempRegID*//* 708(*/0xC4, 0x05/*)*/,
65880 /* 207094 */ GIR_AddImm8, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Imm*/1,
65881 /* 207098 */ GIR_ConstrainOperandRC, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65882 /* 207104 */ GIR_ConstrainOperandRC, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65883 /* 207110 */ GIR_ConstrainOperandRC, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65884 /* 207116 */ GIR_MakeTempReg, /*TempRegID*//* 705(*/0xC1, 0x05/*)*/, /*TypeID*/GILLT_s64,
65885 /* 207120 */ GIR_BuildMI, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65886 /* 207125 */ GIR_AddTempRegister, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*TempRegID*//* 705(*/0xC1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65887 /* 207132 */ GIR_AddSimpleTempRegister, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*TempRegID*//* 706(*/0xC2, 0x05/*)*/,
65888 /* 207137 */ GIR_AddImm8, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*Imm*/32,
65889 /* 207141 */ GIR_AddImm8, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*Imm*/31,
65890 /* 207145 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 706(*/0xC2, 0x05/*)*/,
65891 /* 207148 */ GIR_MakeTempReg, /*TempRegID*//* 704(*/0xC0, 0x05/*)*/, /*TypeID*/GILLT_s64,
65892 /* 207152 */ GIR_BuildMI, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65893 /* 207157 */ GIR_AddTempRegister, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, /*TempRegID*//* 704(*/0xC0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65894 /* 207164 */ GIR_AddSimpleTempRegister, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, /*TempRegID*//* 705(*/0xC1, 0x05/*)*/,
65895 /* 207169 */ GIR_AddImm, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
65896 /* 207180 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 705(*/0xC1, 0x05/*)*/,
65897 /* 207183 */ GIR_MakeTempReg, /*TempRegID*//* 703(*/0xBF, 0x05/*)*/, /*TypeID*/GILLT_s64,
65898 /* 207187 */ GIR_BuildMI, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65899 /* 207192 */ GIR_AddTempRegister, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, /*TempRegID*//* 703(*/0xBF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65900 /* 207199 */ GIR_AddSimpleTempRegister, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, /*TempRegID*//* 704(*/0xC0, 0x05/*)*/,
65901 /* 207204 */ GIR_AddImm, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690),
65902 /* 207215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 704(*/0xC0, 0x05/*)*/,
65903 /* 207218 */ GIR_MakeTempReg, /*TempRegID*//* 702(*/0xBE, 0x05/*)*/, /*TypeID*/GILLT_s64,
65904 /* 207222 */ GIR_BuildMI, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65905 /* 207227 */ GIR_AddTempRegister, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, /*TempRegID*//* 702(*/0xBE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65906 /* 207234 */ GIR_Copy, /*NewInsnID*//* 703(*/0xBF, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65907 /* 207239 */ GIR_AddImm8, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, /*Imm*/1,
65908 /* 207243 */ GIR_AddImm8, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, /*Imm*/62,
65909 /* 207247 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 703(*/0xBF, 0x05/*)*/,
65910 /* 207250 */ GIR_MakeTempReg, /*TempRegID*//* 701(*/0xBD, 0x05/*)*/, /*TypeID*/GILLT_s64,
65911 /* 207254 */ GIR_BuildMI, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65912 /* 207259 */ GIR_AddTempRegister, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, /*TempRegID*//* 701(*/0xBD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65913 /* 207266 */ GIR_AddSimpleTempRegister, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, /*TempRegID*//* 702(*/0xBE, 0x05/*)*/,
65914 /* 207271 */ GIR_AddSimpleTempRegister, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, /*TempRegID*//* 703(*/0xBF, 0x05/*)*/,
65915 /* 207276 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 702(*/0xBE, 0x05/*)*/,
65916 /* 207279 */ GIR_MakeTempReg, /*TempRegID*//* 700(*/0xBC, 0x05/*)*/, /*TypeID*/GILLT_s32,
65917 /* 207283 */ GIR_BuildMI, /*InsnID*//* 701(*/0xBD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS),
65918 /* 207288 */ GIR_AddTempRegister, /*InsnID*//* 701(*/0xBD, 0x05/*)*/, /*TempRegID*//* 700(*/0xBC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65919 /* 207295 */ GIR_AddImm, /*InsnID*//* 701(*/0xBD, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65920 /* 207306 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 701(*/0xBD, 0x05/*)*/,
65921 /* 207309 */ GIR_MakeTempReg, /*TempRegID*//* 699(*/0xBB, 0x05/*)*/, /*TypeID*/GILLT_s32,
65922 /* 207313 */ GIR_BuildMI, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI),
65923 /* 207318 */ GIR_AddTempRegister, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, /*TempRegID*//* 699(*/0xBB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65924 /* 207325 */ GIR_AddSimpleTempRegister, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, /*TempRegID*//* 700(*/0xBC, 0x05/*)*/,
65925 /* 207330 */ GIR_AddImm, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65926 /* 207341 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 700(*/0xBC, 0x05/*)*/,
65927 /* 207344 */ GIR_MakeTempReg, /*TempRegID*//* 698(*/0xBA, 0x05/*)*/, /*TypeID*/GILLT_s64,
65928 /* 207348 */ GIR_BuildMI, /*InsnID*//* 699(*/0xBB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
65929 /* 207353 */ GIR_AddTempRegister, /*InsnID*//* 699(*/0xBB, 0x05/*)*/, /*TempRegID*//* 698(*/0xBA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65930 /* 207360 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 699(*/0xBB, 0x05/*)*/,
65931 /* 207363 */ GIR_MakeTempReg, /*TempRegID*//* 697(*/0xB9, 0x05/*)*/, /*TypeID*/GILLT_s64,
65932 /* 207367 */ GIR_BuildMI, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
65933 /* 207372 */ GIR_AddTempRegister, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*TempRegID*//* 697(*/0xB9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65934 /* 207379 */ GIR_AddSimpleTempRegister, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*TempRegID*//* 698(*/0xBA, 0x05/*)*/,
65935 /* 207384 */ GIR_AddSimpleTempRegister, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*TempRegID*//* 699(*/0xBB, 0x05/*)*/,
65936 /* 207389 */ GIR_AddImm8, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Imm*/1,
65937 /* 207393 */ GIR_ConstrainOperandRC, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
65938 /* 207399 */ GIR_ConstrainOperandRC, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
65939 /* 207405 */ GIR_ConstrainOperandRC, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
65940 /* 207411 */ GIR_MakeTempReg, /*TempRegID*//* 696(*/0xB8, 0x05/*)*/, /*TypeID*/GILLT_s64,
65941 /* 207415 */ GIR_BuildMI, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
65942 /* 207420 */ GIR_AddTempRegister, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*TempRegID*//* 696(*/0xB8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65943 /* 207427 */ GIR_AddSimpleTempRegister, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*TempRegID*//* 697(*/0xB9, 0x05/*)*/,
65944 /* 207432 */ GIR_AddImm8, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*Imm*/32,
65945 /* 207436 */ GIR_AddImm8, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*Imm*/31,
65946 /* 207440 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 697(*/0xB9, 0x05/*)*/,
65947 /* 207443 */ GIR_MakeTempReg, /*TempRegID*//* 695(*/0xB7, 0x05/*)*/, /*TypeID*/GILLT_s64,
65948 /* 207447 */ GIR_BuildMI, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8),
65949 /* 207452 */ GIR_AddTempRegister, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, /*TempRegID*//* 695(*/0xB7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65950 /* 207459 */ GIR_AddSimpleTempRegister, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, /*TempRegID*//* 696(*/0xB8, 0x05/*)*/,
65951 /* 207464 */ GIR_AddImm, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65952 /* 207475 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 696(*/0xB8, 0x05/*)*/,
65953 /* 207478 */ GIR_MakeTempReg, /*TempRegID*//* 694(*/0xB6, 0x05/*)*/, /*TypeID*/GILLT_s64,
65954 /* 207482 */ GIR_BuildMI, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8),
65955 /* 207487 */ GIR_AddTempRegister, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, /*TempRegID*//* 694(*/0xB6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65956 /* 207494 */ GIR_AddSimpleTempRegister, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, /*TempRegID*//* 695(*/0xB7, 0x05/*)*/,
65957 /* 207499 */ GIR_AddImm, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845),
65958 /* 207510 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 695(*/0xB7, 0x05/*)*/,
65959 /* 207513 */ GIR_MakeTempReg, /*TempRegID*//* 693(*/0xB5, 0x05/*)*/, /*TypeID*/GILLT_s64,
65960 /* 207517 */ GIR_BuildMI, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65961 /* 207522 */ GIR_AddTempRegister, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, /*TempRegID*//* 693(*/0xB5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65962 /* 207529 */ GIR_Copy, /*NewInsnID*//* 694(*/0xB6, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A
65963 /* 207534 */ GIR_AddImm8, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, /*Imm*/63,
65964 /* 207538 */ GIR_AddImm8, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, /*Imm*/1,
65965 /* 207542 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 694(*/0xB6, 0x05/*)*/,
65966 /* 207545 */ GIR_MakeTempReg, /*TempRegID*//* 692(*/0xB4, 0x05/*)*/, /*TypeID*/GILLT_s64,
65967 /* 207549 */ GIR_BuildMI, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65968 /* 207554 */ GIR_AddTempRegister, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, /*TempRegID*//* 692(*/0xB4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65969 /* 207561 */ GIR_AddSimpleTempRegister, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, /*TempRegID*//* 693(*/0xB5, 0x05/*)*/,
65970 /* 207566 */ GIR_AddSimpleTempRegister, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, /*TempRegID*//* 694(*/0xB6, 0x05/*)*/,
65971 /* 207571 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 693(*/0xB5, 0x05/*)*/,
65972 /* 207574 */ GIR_MakeTempReg, /*TempRegID*//* 691(*/0xB3, 0x05/*)*/, /*TypeID*/GILLT_s64,
65973 /* 207578 */ GIR_BuildMI, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65974 /* 207583 */ GIR_AddTempRegister, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, /*TempRegID*//* 691(*/0xB3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65975 /* 207590 */ GIR_AddSimpleTempRegister, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, /*TempRegID*//* 692(*/0xB4, 0x05/*)*/,
65976 /* 207595 */ GIR_AddSimpleTempRegister, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, /*TempRegID*//* 701(*/0xBD, 0x05/*)*/,
65977 /* 207600 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 692(*/0xB4, 0x05/*)*/,
65978 /* 207603 */ GIR_MakeTempReg, /*TempRegID*//* 690(*/0xB2, 0x05/*)*/, /*TypeID*/GILLT_s64,
65979 /* 207607 */ GIR_BuildMI, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65980 /* 207612 */ GIR_AddTempRegister, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*TempRegID*//* 690(*/0xB2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65981 /* 207619 */ GIR_AddSimpleTempRegister, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*TempRegID*//* 691(*/0xB3, 0x05/*)*/,
65982 /* 207624 */ GIR_AddImm8, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*Imm*/62,
65983 /* 207628 */ GIR_AddImm8, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*Imm*/2,
65984 /* 207632 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 691(*/0xB3, 0x05/*)*/,
65985 /* 207635 */ GIR_MakeTempReg, /*TempRegID*//* 689(*/0xB1, 0x05/*)*/, /*TypeID*/GILLT_s64,
65986 /* 207639 */ GIR_BuildMI, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
65987 /* 207644 */ GIR_AddTempRegister, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, /*TempRegID*//* 689(*/0xB1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65988 /* 207651 */ GIR_AddSimpleTempRegister, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, /*TempRegID*//* 690(*/0xB2, 0x05/*)*/,
65989 /* 207656 */ GIR_AddSimpleTempRegister, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, /*TempRegID*//* 710(*/0xC6, 0x05/*)*/,
65990 /* 207661 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 690(*/0xB2, 0x05/*)*/,
65991 /* 207664 */ GIR_MakeTempReg, /*TempRegID*//* 688(*/0xB0, 0x05/*)*/, /*TypeID*/GILLT_s64,
65992 /* 207668 */ GIR_BuildMI, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
65993 /* 207673 */ GIR_AddTempRegister, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, /*TempRegID*//* 688(*/0xB0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
65994 /* 207680 */ GIR_AddSimpleTempRegister, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, /*TempRegID*//* 689(*/0xB1, 0x05/*)*/,
65995 /* 207685 */ GIR_AddSimpleTempRegister, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, /*TempRegID*//* 717(*/0xCD, 0x05/*)*/,
65996 /* 207690 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 689(*/0xB1, 0x05/*)*/,
65997 /* 207693 */ GIR_MakeTempReg, /*TempRegID*//* 687(*/0xAF, 0x05/*)*/, /*TypeID*/GILLT_s64,
65998 /* 207697 */ GIR_BuildMI, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
65999 /* 207702 */ GIR_AddTempRegister, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*TempRegID*//* 687(*/0xAF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66000 /* 207709 */ GIR_AddSimpleTempRegister, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*TempRegID*//* 688(*/0xB0, 0x05/*)*/,
66001 /* 207714 */ GIR_AddImm8, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*Imm*/60,
66002 /* 207718 */ GIR_AddImm8, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*Imm*/4,
66003 /* 207722 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 688(*/0xB0, 0x05/*)*/,
66004 /* 207725 */ GIR_MakeTempReg, /*TempRegID*//* 686(*/0xAE, 0x05/*)*/, /*TypeID*/GILLT_s64,
66005 /* 207729 */ GIR_BuildMI, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8),
66006 /* 207734 */ GIR_AddTempRegister, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, /*TempRegID*//* 686(*/0xAE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66007 /* 207741 */ GIR_AddSimpleTempRegister, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, /*TempRegID*//* 687(*/0xAF, 0x05/*)*/,
66008 /* 207746 */ GIR_AddSimpleTempRegister, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, /*TempRegID*//* 745(*/0xE9, 0x05/*)*/,
66009 /* 207751 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 687(*/0xAF, 0x05/*)*/,
66010 /* 207754 */ GIR_MakeTempReg, /*TempRegID*//* 685(*/0xAD, 0x05/*)*/, /*TypeID*/GILLT_s64,
66011 /* 207758 */ GIR_BuildMI, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8),
66012 /* 207763 */ GIR_AddTempRegister, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, /*TempRegID*//* 685(*/0xAD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66013 /* 207770 */ GIR_AddSimpleTempRegister, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, /*TempRegID*//* 686(*/0xAE, 0x05/*)*/,
66014 /* 207775 */ GIR_AddSimpleTempRegister, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, /*TempRegID*//* 752(*/0xF0, 0x05/*)*/,
66015 /* 207780 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 686(*/0xAE, 0x05/*)*/,
66016 /* 207783 */ GIR_MakeTempReg, /*TempRegID*//* 684(*/0xAC, 0x05/*)*/, /*TypeID*/GILLT_s64,
66017 /* 207787 */ GIR_BuildMI, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL),
66018 /* 207792 */ GIR_AddTempRegister, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*TempRegID*//* 684(*/0xAC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66019 /* 207799 */ GIR_AddSimpleTempRegister, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*TempRegID*//* 685(*/0xAD, 0x05/*)*/,
66020 /* 207804 */ GIR_AddImm8, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*Imm*/32,
66021 /* 207808 */ GIR_AddImm8, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*Imm*/32,
66022 /* 207812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 685(*/0xAD, 0x05/*)*/,
66023 /* 207815 */ GIR_MakeTempReg, /*TempRegID*//* 683(*/0xAB, 0x05/*)*/, /*TypeID*/GILLT_s32,
66024 /* 207819 */ GIR_BuildMI, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66025 /* 207824 */ GIR_AddTempRegister, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*TempRegID*//* 683(*/0xAB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66026 /* 207831 */ GIR_AddTempSubRegister, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*TempRegID*//* 684(*/0xAC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
66027 /* 207840 */ GIR_ConstrainOperandRC, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
66028 /* 207846 */ GIR_ConstrainOperandRC, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
66029 /* 207852 */ GIR_MakeTempReg, /*TempRegID*//* 548(*/0xA4, 0x04/*)*/, /*TypeID*/GILLT_s32,
66030 /* 207856 */ GIR_BuildMI, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66031 /* 207861 */ GIR_AddTempRegister, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*TempRegID*//* 548(*/0xA4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66032 /* 207868 */ GIR_AddTempSubRegister, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*TempRegID*//* 549(*/0xA5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
66033 /* 207877 */ GIR_ConstrainOperandRC, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
66034 /* 207883 */ GIR_ConstrainOperandRC, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
66035 /* 207889 */ GIR_MakeTempReg, /*TempRegID*//* 413(*/0x9D, 0x03/*)*/, /*TypeID*/GILLT_s32,
66036 /* 207893 */ GIR_BuildMI, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66037 /* 207898 */ GIR_AddTempRegister, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*TempRegID*//* 413(*/0x9D, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66038 /* 207905 */ GIR_AddTempSubRegister, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*TempRegID*//* 414(*/0x9E, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
66039 /* 207914 */ GIR_ConstrainOperandRC, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
66040 /* 207920 */ GIR_ConstrainOperandRC, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
66041 /* 207926 */ GIR_MakeTempReg, /*TempRegID*//* 412(*/0x9C, 0x03/*)*/, /*TypeID*/GILLT_s32,
66042 /* 207930 */ GIR_BuildMI, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
66043 /* 207935 */ GIR_AddTempRegister, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*TempRegID*//* 412(*/0x9C, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66044 /* 207942 */ GIR_AddSimpleTempRegister, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*TempRegID*//* 413(*/0x9D, 0x03/*)*/,
66045 /* 207947 */ GIR_AddImm8, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*Imm*/24,
66046 /* 207951 */ GIR_AddImm8, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*Imm*/0,
66047 /* 207955 */ GIR_AddImm8, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*Imm*/31,
66048 /* 207959 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 413(*/0x9D, 0x03/*)*/,
66049 /* 207962 */ GIR_MakeTempReg, /*TempRegID*//* 411(*/0x9B, 0x03/*)*/, /*TypeID*/GILLT_s32,
66050 /* 207966 */ GIR_BuildMI, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWIMI),
66051 /* 207971 */ GIR_AddTempRegister, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*TempRegID*//* 411(*/0x9B, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66052 /* 207978 */ GIR_AddSimpleTempRegister, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*TempRegID*//* 412(*/0x9C, 0x03/*)*/,
66053 /* 207983 */ GIR_AddSimpleTempRegister, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*TempRegID*//* 548(*/0xA4, 0x04/*)*/,
66054 /* 207988 */ GIR_AddImm8, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*Imm*/8,
66055 /* 207992 */ GIR_AddImm8, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*Imm*/8,
66056 /* 207996 */ GIR_AddImm8, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*Imm*/15,
66057 /* 208000 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 412(*/0x9C, 0x03/*)*/,
66058 /* 208003 */ GIR_MakeTempReg, /*TempRegID*//* 410(*/0x9A, 0x03/*)*/, /*TypeID*/GILLT_s32,
66059 /* 208007 */ GIR_BuildMI, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWIMI),
66060 /* 208012 */ GIR_AddTempRegister, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*TempRegID*//* 410(*/0x9A, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66061 /* 208019 */ GIR_AddSimpleTempRegister, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*TempRegID*//* 411(*/0x9B, 0x03/*)*/,
66062 /* 208024 */ GIR_AddSimpleTempRegister, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*TempRegID*//* 683(*/0xAB, 0x05/*)*/,
66063 /* 208029 */ GIR_AddImm8, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*Imm*/8,
66064 /* 208033 */ GIR_AddImm8, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*Imm*/24,
66065 /* 208037 */ GIR_AddImm8, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*Imm*/31,
66066 /* 208041 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 411(*/0x9B, 0x03/*)*/,
66067 /* 208044 */ GIR_MakeTempReg, /*TempRegID*//* 409(*/0x99, 0x03/*)*/, /*TypeID*/GILLT_s64,
66068 /* 208048 */ GIR_BuildMI, /*InsnID*//* 410(*/0x9A, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
66069 /* 208053 */ GIR_AddTempRegister, /*InsnID*//* 410(*/0x9A, 0x03/*)*/, /*TempRegID*//* 409(*/0x99, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66070 /* 208060 */ GIR_ConstrainSelectedInstOperands, /*InsnID*//* 410(*/0x9A, 0x03/*)*/,
66071 /* 208063 */ GIR_MakeTempReg, /*TempRegID*//* 408(*/0x98, 0x03/*)*/, /*TypeID*/GILLT_s64,
66072 /* 208067 */ GIR_BuildMI, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
66073 /* 208072 */ GIR_AddTempRegister, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*TempRegID*//* 408(*/0x98, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66074 /* 208079 */ GIR_AddSimpleTempRegister, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*TempRegID*//* 409(*/0x99, 0x03/*)*/,
66075 /* 208084 */ GIR_AddSimpleTempRegister, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*TempRegID*//* 410(*/0x9A, 0x03/*)*/,
66076 /* 208089 */ GIR_AddImm8, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Imm*/1,
66077 /* 208093 */ GIR_ConstrainOperandRC, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
66078 /* 208099 */ GIR_ConstrainOperandRC, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
66079 /* 208105 */ GIR_ConstrainOperandRC, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
66080 /* 208111 */ GIR_MakeTempReg, /*TempRegID*//* 274(*/0x92, 0x02/*)*/, /*TypeID*/GILLT_s32,
66081 /* 208115 */ GIR_BuildMI, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66082 /* 208120 */ GIR_AddTempRegister, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*TempRegID*//* 274(*/0x92, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66083 /* 208127 */ GIR_AddTempSubRegister, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*TempRegID*//* 275(*/0x93, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
66084 /* 208136 */ GIR_ConstrainOperandRC, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
66085 /* 208142 */ GIR_ConstrainOperandRC, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
66086 /* 208148 */ GIR_MakeTempReg, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TypeID*/GILLT_s32,
66087 /* 208152 */ GIR_BuildMI, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66088 /* 208157 */ GIR_AddTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66089 /* 208164 */ GIR_AddTempSubRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
66090 /* 208173 */ GIR_ConstrainOperandRC, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
66091 /* 208179 */ GIR_ConstrainOperandRC, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
66092 /* 208185 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
66093 /* 208188 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66094 /* 208192 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66095 /* 208197 */ GIR_AddTempSubRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32),
66096 /* 208204 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID),
66097 /* 208209 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
66098 /* 208214 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
66099 /* 208217 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(PPC::RLWINM),
66100 /* 208221 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66101 /* 208226 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
66102 /* 208229 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/24,
66103 /* 208232 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/0,
66104 /* 208235 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/31,
66105 /* 208238 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
66106 /* 208240 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
66107 /* 208243 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(PPC::RLWIMI),
66108 /* 208247 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66109 /* 208252 */ GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
66110 /* 208255 */ GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/,
66111 /* 208259 */ GIR_AddImm8, /*InsnID*/5, /*Imm*/8,
66112 /* 208262 */ GIR_AddImm8, /*InsnID*/5, /*Imm*/8,
66113 /* 208265 */ GIR_AddImm8, /*InsnID*/5, /*Imm*/15,
66114 /* 208268 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
66115 /* 208270 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
66116 /* 208273 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::RLWIMI),
66117 /* 208277 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66118 /* 208282 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
66119 /* 208285 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*//* 274(*/0x92, 0x02/*)*/,
66120 /* 208289 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/8,
66121 /* 208292 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/24,
66122 /* 208295 */ GIR_AddImm8, /*InsnID*/4, /*Imm*/31,
66123 /* 208298 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
66124 /* 208300 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
66125 /* 208303 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
66126 /* 208307 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66127 /* 208312 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
66128 /* 208314 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
66129 /* 208317 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
66130 /* 208321 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66131 /* 208326 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
66132 /* 208329 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
66133 /* 208332 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
66134 /* 208335 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID),
66135 /* 208340 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID),
66136 /* 208345 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID),
66137 /* 208350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
66138 /* 208353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICR),
66139 /* 208357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66140 /* 208362 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
66141 /* 208365 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
66142 /* 208368 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
66143 /* 208371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
66144 /* 208373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::OR8),
66145 /* 208376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA]
66146 /* 208378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
66147 /* 208381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*//* 408(*/0x98, 0x03/*)*/,
66148 /* 208385 */ GIR_RootConstrainSelectedInstOperands,
66149 /* 208386 */ // GIR_Coverage, 4891,
66150 /* 208386 */ GIR_EraseRootFromParent_Done,
66151 /* 208387 */ // Label 2770: @208387
66152 /* 208387 */ GIM_Reject,
66153 /* 208388 */ // Label 2766: @208388
66154 /* 208388 */ GIM_Reject,
66155 /* 208389 */ // Label 71: @208389
66156 /* 208389 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2776*/ GIMT_Encode4(208663),
66157 /* 208400 */ /*GILLT_s32*//*Label 2771*/ GIMT_Encode4(208420),
66158 /* 208404 */ /*GILLT_s64*//*Label 2772*/ GIMT_Encode4(208513),
66159 /* 208408 */ /*GILLT_s128*//*Label 2773*/ GIMT_Encode4(208561),
66160 /* 208412 */ /*GILLT_v2s64*//*Label 2774*/ GIMT_Encode4(208592),
66161 /* 208416 */ /*GILLT_v4s32*//*Label 2775*/ GIMT_Encode4(208615),
66162 /* 208420 */ // Label 2771: @208420
66163 /* 208420 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(208512),
66164 /* 208425 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
66165 /* 208428 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(208492), // Rule ID 1711 //
66166 /* 208433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66167 /* 208436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
66168 /* 208440 */ // (fceil:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
66169 /* 208440 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
66170 /* 208443 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66171 /* 208447 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66172 /* 208452 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
66173 /* 208456 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
66174 /* 208461 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
66175 /* 208464 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIP),
66176 /* 208468 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66177 /* 208473 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
66178 /* 208476 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
66179 /* 208478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66180 /* 208481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66181 /* 208483 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
66182 /* 208486 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
66183 /* 208491 */ // GIR_Coverage, 1711,
66184 /* 208491 */ GIR_EraseRootFromParent_Done,
66185 /* 208492 */ // Label 2778: @208492
66186 /* 208492 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(208511), // Rule ID 146 //
66187 /* 208497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66188 /* 208500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
66189 /* 208504 */ // (fceil:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRIPS:{ *:[f32] } f32:{ *:[f32] }:$RB)
66190 /* 208504 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIPS),
66191 /* 208509 */ GIR_RootConstrainSelectedInstOperands,
66192 /* 208510 */ // GIR_Coverage, 146,
66193 /* 208510 */ GIR_Done,
66194 /* 208511 */ // Label 2779: @208511
66195 /* 208511 */ GIM_Reject,
66196 /* 208512 */ // Label 2777: @208512
66197 /* 208512 */ GIM_Reject,
66198 /* 208513 */ // Label 2772: @208513
66199 /* 208513 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(208560),
66200 /* 208518 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
66201 /* 208521 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(208540), // Rule ID 913 //
66202 /* 208526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66203 /* 208529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
66204 /* 208533 */ // (fceil:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIP:{ *:[f64] } f64:{ *:[f64] }:$XB)
66205 /* 208533 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIP),
66206 /* 208538 */ GIR_RootConstrainSelectedInstOperands,
66207 /* 208539 */ // GIR_Coverage, 913,
66208 /* 208539 */ GIR_Done,
66209 /* 208540 */ // Label 2781: @208540
66210 /* 208540 */ GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(208559), // Rule ID 144 //
66211 /* 208545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66212 /* 208548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
66213 /* 208552 */ // (fceil:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIPD:{ *:[f64] } f64:{ *:[f64] }:$RB)
66214 /* 208552 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIPD),
66215 /* 208557 */ GIR_RootConstrainSelectedInstOperands,
66216 /* 208558 */ // GIR_Coverage, 144,
66217 /* 208558 */ GIR_Done,
66218 /* 208559 */ // Label 2782: @208559
66219 /* 208559 */ GIM_Reject,
66220 /* 208560 */ // Label 2780: @208560
66221 /* 208560 */ GIM_Reject,
66222 /* 208561 */ // Label 2773: @208561
66223 /* 208561 */ GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(208591), // Rule ID 2166 //
66224 /* 208566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
66225 /* 208569 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
66226 /* 208572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66227 /* 208576 */ // (fceil:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 1:{ *:[i32] }, ?:{ *:[f128] }:$vB, 2:{ *:[i32] })
66228 /* 208576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI),
66229 /* 208579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT]
66230 /* 208581 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
66231 /* 208584 */ GIR_RootToRootCopy, /*OpIdx*/1, // vB
66232 /* 208586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
66233 /* 208589 */ GIR_RootConstrainSelectedInstOperands,
66234 /* 208590 */ // GIR_Coverage, 2166,
66235 /* 208590 */ GIR_EraseRootFromParent_Done,
66236 /* 208591 */ // Label 2783: @208591
66237 /* 208591 */ GIM_Reject,
66238 /* 208592 */ // Label 2774: @208592
66239 /* 208592 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(208614), // Rule ID 921 //
66240 /* 208597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66241 /* 208600 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
66242 /* 208603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66243 /* 208607 */ // (fceil:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
66244 /* 208607 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIP),
66245 /* 208612 */ GIR_RootConstrainSelectedInstOperands,
66246 /* 208613 */ // GIR_Coverage, 921,
66247 /* 208613 */ GIR_Done,
66248 /* 208614 */ // Label 2784: @208614
66249 /* 208614 */ GIM_Reject,
66250 /* 208615 */ // Label 2775: @208615
66251 /* 208615 */ GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(208662),
66252 /* 208620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
66253 /* 208623 */ GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(208642), // Rule ID 929 //
66254 /* 208628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66255 /* 208631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66256 /* 208635 */ // (fceil:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
66257 /* 208635 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIP),
66258 /* 208640 */ GIR_RootConstrainSelectedInstOperands,
66259 /* 208641 */ // GIR_Coverage, 929,
66260 /* 208641 */ GIR_Done,
66261 /* 208642 */ // Label 2786: @208642
66262 /* 208642 */ GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(208661), // Rule ID 1420 //
66263 /* 208647 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
66264 /* 208650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66265 /* 208654 */ // (fceil:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIP:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA)
66266 /* 208654 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIP),
66267 /* 208659 */ GIR_RootConstrainSelectedInstOperands,
66268 /* 208660 */ // GIR_Coverage, 1420,
66269 /* 208660 */ GIR_Done,
66270 /* 208661 */ // Label 2787: @208661
66271 /* 208661 */ GIM_Reject,
66272 /* 208662 */ // Label 2785: @208662
66273 /* 208662 */ GIM_Reject,
66274 /* 208663 */ // Label 2776: @208663
66275 /* 208663 */ GIM_Reject,
66276 /* 208664 */ // Label 72: @208664
66277 /* 208664 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2793*/ GIMT_Encode4(208880),
66278 /* 208675 */ /*GILLT_s32*//*Label 2788*/ GIMT_Encode4(208695),
66279 /* 208679 */ /*GILLT_s64*//*Label 2789*/ GIMT_Encode4(208747),
66280 /* 208683 */ /*GILLT_s128*//*Label 2790*/ GIMT_Encode4(208803),
66281 /* 208687 */ /*GILLT_v2s64*//*Label 2791*/ GIMT_Encode4(208826),
66282 /* 208691 */ /*GILLT_v4s32*//*Label 2792*/ GIMT_Encode4(208853),
66283 /* 208695 */ // Label 2788: @208695
66284 /* 208695 */ GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(208746),
66285 /* 208700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
66286 /* 208703 */ GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(208722), // Rule ID 964 //
66287 /* 208708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
66288 /* 208711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
66289 /* 208715 */ // (fsqrt:{ *:[f32] } f32:{ *:[f32] }:$XB) => (XSSQRTSP:{ *:[f32] } f32:{ *:[f32] }:$XB)
66290 /* 208715 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTSP),
66291 /* 208720 */ GIR_RootConstrainSelectedInstOperands,
66292 /* 208721 */ // GIR_Coverage, 964,
66293 /* 208721 */ GIR_Done,
66294 /* 208722 */ // Label 2795: @208722
66295 /* 208722 */ GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(208745), // Rule ID 162 //
66296 /* 208727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66297 /* 208730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
66298 /* 208734 */ // (fsqrt:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FSQRTS:{ *:[f32] } f32:{ *:[f32] }:$RB)
66299 /* 208734 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSQRTS),
66300 /* 208739 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66301 /* 208743 */ GIR_RootConstrainSelectedInstOperands,
66302 /* 208744 */ // GIR_Coverage, 162,
66303 /* 208744 */ GIR_Done,
66304 /* 208745 */ // Label 2796: @208745
66305 /* 208745 */ GIM_Reject,
66306 /* 208746 */ // Label 2794: @208746
66307 /* 208746 */ GIM_Reject,
66308 /* 208747 */ // Label 2789: @208747
66309 /* 208747 */ GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(208802),
66310 /* 208752 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
66311 /* 208755 */ GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(208778), // Rule ID 813 //
66312 /* 208760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66313 /* 208763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
66314 /* 208767 */ // (fsqrt:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSSQRTDP:{ *:[f64] } f64:{ *:[f64] }:$XB)
66315 /* 208767 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTDP),
66316 /* 208772 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66317 /* 208776 */ GIR_RootConstrainSelectedInstOperands,
66318 /* 208777 */ // GIR_Coverage, 813,
66319 /* 208777 */ GIR_Done,
66320 /* 208778 */ // Label 2798: @208778
66321 /* 208778 */ GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(208801), // Rule ID 160 //
66322 /* 208783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66323 /* 208786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
66324 /* 208790 */ // (fsqrt:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FSQRT:{ *:[f64] } f64:{ *:[f64] }:$RB)
66325 /* 208790 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSQRT),
66326 /* 208795 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66327 /* 208799 */ GIR_RootConstrainSelectedInstOperands,
66328 /* 208800 */ // GIR_Coverage, 160,
66329 /* 208800 */ GIR_Done,
66330 /* 208801 */ // Label 2799: @208801
66331 /* 208801 */ GIM_Reject,
66332 /* 208802 */ // Label 2797: @208802
66333 /* 208802 */ GIM_Reject,
66334 /* 208803 */ // Label 2790: @208803
66335 /* 208803 */ GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(208825), // Rule ID 996 //
66336 /* 208808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
66337 /* 208811 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
66338 /* 208814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66339 /* 208818 */ // (fsqrt:{ *:[f128] } f128:{ *:[f128] }:$RB) => (XSSQRTQP:{ *:[f128] } f128:{ *:[f128] }:$RB)
66340 /* 208818 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTQP),
66341 /* 208823 */ GIR_RootConstrainSelectedInstOperands,
66342 /* 208824 */ // GIR_Coverage, 996,
66343 /* 208824 */ GIR_Done,
66344 /* 208825 */ // Label 2800: @208825
66345 /* 208825 */ GIM_Reject,
66346 /* 208826 */ // Label 2791: @208826
66347 /* 208826 */ GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(208852), // Rule ID 824 //
66348 /* 208831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66349 /* 208834 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
66350 /* 208837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66351 /* 208841 */ // (fsqrt:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVSQRTDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
66352 /* 208841 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSQRTDP),
66353 /* 208846 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66354 /* 208850 */ GIR_RootConstrainSelectedInstOperands,
66355 /* 208851 */ // GIR_Coverage, 824,
66356 /* 208851 */ GIR_Done,
66357 /* 208852 */ // Label 2801: @208852
66358 /* 208852 */ GIM_Reject,
66359 /* 208853 */ // Label 2792: @208853
66360 /* 208853 */ GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(208879), // Rule ID 826 //
66361 /* 208858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66362 /* 208861 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
66363 /* 208864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66364 /* 208868 */ // (fsqrt:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVSQRTSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
66365 /* 208868 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSQRTSP),
66366 /* 208873 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66367 /* 208877 */ GIR_RootConstrainSelectedInstOperands,
66368 /* 208878 */ // GIR_Coverage, 826,
66369 /* 208878 */ GIR_Done,
66370 /* 208879 */ // Label 2802: @208879
66371 /* 208879 */ GIM_Reject,
66372 /* 208880 */ // Label 2793: @208880
66373 /* 208880 */ GIM_Reject,
66374 /* 208881 */ // Label 73: @208881
66375 /* 208881 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2808*/ GIMT_Encode4(209155),
66376 /* 208892 */ /*GILLT_s32*//*Label 2803*/ GIMT_Encode4(208912),
66377 /* 208896 */ /*GILLT_s64*//*Label 2804*/ GIMT_Encode4(209005),
66378 /* 208900 */ /*GILLT_s128*//*Label 2805*/ GIMT_Encode4(209053),
66379 /* 208904 */ /*GILLT_v2s64*//*Label 2806*/ GIMT_Encode4(209084),
66380 /* 208908 */ /*GILLT_v4s32*//*Label 2807*/ GIMT_Encode4(209107),
66381 /* 208912 */ // Label 2803: @208912
66382 /* 208912 */ GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(209004),
66383 /* 208917 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
66384 /* 208920 */ GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(208984), // Rule ID 1709 //
66385 /* 208925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66386 /* 208928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
66387 /* 208932 */ // (ffloor:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIM:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
66388 /* 208932 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
66389 /* 208935 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66390 /* 208939 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66391 /* 208944 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
66392 /* 208948 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
66393 /* 208953 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
66394 /* 208956 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIM),
66395 /* 208960 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66396 /* 208965 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
66397 /* 208968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
66398 /* 208970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66399 /* 208973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66400 /* 208975 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
66401 /* 208978 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
66402 /* 208983 */ // GIR_Coverage, 1709,
66403 /* 208983 */ GIR_EraseRootFromParent_Done,
66404 /* 208984 */ // Label 2810: @208984
66405 /* 208984 */ GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(209003), // Rule ID 154 //
66406 /* 208989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66407 /* 208992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
66408 /* 208996 */ // (ffloor:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRIMS:{ *:[f32] } f32:{ *:[f32] }:$RB)
66409 /* 208996 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIMS),
66410 /* 209001 */ GIR_RootConstrainSelectedInstOperands,
66411 /* 209002 */ // GIR_Coverage, 154,
66412 /* 209002 */ GIR_Done,
66413 /* 209003 */ // Label 2811: @209003
66414 /* 209003 */ GIM_Reject,
66415 /* 209004 */ // Label 2809: @209004
66416 /* 209004 */ GIM_Reject,
66417 /* 209005 */ // Label 2804: @209005
66418 /* 209005 */ GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(209052),
66419 /* 209010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
66420 /* 209013 */ GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(209032), // Rule ID 911 //
66421 /* 209018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66422 /* 209021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
66423 /* 209025 */ // (ffloor:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIM:{ *:[f64] } f64:{ *:[f64] }:$XB)
66424 /* 209025 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIM),
66425 /* 209030 */ GIR_RootConstrainSelectedInstOperands,
66426 /* 209031 */ // GIR_Coverage, 911,
66427 /* 209031 */ GIR_Done,
66428 /* 209032 */ // Label 2813: @209032
66429 /* 209032 */ GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(209051), // Rule ID 152 //
66430 /* 209037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66431 /* 209040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
66432 /* 209044 */ // (ffloor:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIMD:{ *:[f64] } f64:{ *:[f64] }:$RB)
66433 /* 209044 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIMD),
66434 /* 209049 */ GIR_RootConstrainSelectedInstOperands,
66435 /* 209050 */ // GIR_Coverage, 152,
66436 /* 209050 */ GIR_Done,
66437 /* 209051 */ // Label 2814: @209051
66438 /* 209051 */ GIM_Reject,
66439 /* 209052 */ // Label 2812: @209052
66440 /* 209052 */ GIM_Reject,
66441 /* 209053 */ // Label 2805: @209053
66442 /* 209053 */ GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(209083), // Rule ID 2168 //
66443 /* 209058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
66444 /* 209061 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
66445 /* 209064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66446 /* 209068 */ // (ffloor:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 1:{ *:[i32] }, ?:{ *:[f128] }:$vB, 3:{ *:[i32] })
66447 /* 209068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI),
66448 /* 209071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT]
66449 /* 209073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
66450 /* 209076 */ GIR_RootToRootCopy, /*OpIdx*/1, // vB
66451 /* 209078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
66452 /* 209081 */ GIR_RootConstrainSelectedInstOperands,
66453 /* 209082 */ // GIR_Coverage, 2168,
66454 /* 209082 */ GIR_EraseRootFromParent_Done,
66455 /* 209083 */ // Label 2815: @209083
66456 /* 209083 */ GIM_Reject,
66457 /* 209084 */ // Label 2806: @209084
66458 /* 209084 */ GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(209106), // Rule ID 919 //
66459 /* 209089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66460 /* 209092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
66461 /* 209095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66462 /* 209099 */ // (ffloor:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIM:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
66463 /* 209099 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIM),
66464 /* 209104 */ GIR_RootConstrainSelectedInstOperands,
66465 /* 209105 */ // GIR_Coverage, 919,
66466 /* 209105 */ GIR_Done,
66467 /* 209106 */ // Label 2816: @209106
66468 /* 209106 */ GIM_Reject,
66469 /* 209107 */ // Label 2807: @209107
66470 /* 209107 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(209154),
66471 /* 209112 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
66472 /* 209115 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(209134), // Rule ID 927 //
66473 /* 209120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66474 /* 209123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66475 /* 209127 */ // (ffloor:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIM:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
66476 /* 209127 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIM),
66477 /* 209132 */ GIR_RootConstrainSelectedInstOperands,
66478 /* 209133 */ // GIR_Coverage, 927,
66479 /* 209133 */ GIR_Done,
66480 /* 209134 */ // Label 2818: @209134
66481 /* 209134 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(209153), // Rule ID 1419 //
66482 /* 209139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
66483 /* 209142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66484 /* 209146 */ // (ffloor:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIM:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA)
66485 /* 209146 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIM),
66486 /* 209151 */ GIR_RootConstrainSelectedInstOperands,
66487 /* 209152 */ // GIR_Coverage, 1419,
66488 /* 209152 */ GIR_Done,
66489 /* 209153 */ // Label 2819: @209153
66490 /* 209153 */ GIM_Reject,
66491 /* 209154 */ // Label 2817: @209154
66492 /* 209154 */ GIM_Reject,
66493 /* 209155 */ // Label 2808: @209155
66494 /* 209155 */ GIM_Reject,
66495 /* 209156 */ // Label 74: @209156
66496 /* 209156 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2825*/ GIMT_Encode4(209367),
66497 /* 209167 */ /*GILLT_s32*//*Label 2820*/ GIMT_Encode4(209187),
66498 /* 209171 */ /*GILLT_s64*//*Label 2821*/ GIMT_Encode4(209255),
66499 /* 209175 */ /*GILLT_s128*//*Label 2822*/ GIMT_Encode4(209282),
66500 /* 209179 */ /*GILLT_v2s64*//*Label 2823*/ GIMT_Encode4(209313),
66501 /* 209183 */ /*GILLT_v4s32*//*Label 2824*/ GIMT_Encode4(209340),
66502 /* 209187 */ // Label 2820: @209187
66503 /* 209187 */ GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(209254), // Rule ID 1715 //
66504 /* 209192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66505 /* 209195 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
66506 /* 209198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
66507 /* 209202 */ // (frint:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIC:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
66508 /* 209202 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
66509 /* 209205 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66510 /* 209209 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66511 /* 209214 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
66512 /* 209218 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
66513 /* 209223 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
66514 /* 209226 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIC),
66515 /* 209230 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66516 /* 209235 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
66517 /* 209238 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
66518 /* 209240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66519 /* 209243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66520 /* 209245 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
66521 /* 209248 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
66522 /* 209253 */ // GIR_Coverage, 1715,
66523 /* 209253 */ GIR_EraseRootFromParent_Done,
66524 /* 209254 */ // Label 2826: @209254
66525 /* 209254 */ GIM_Reject,
66526 /* 209255 */ // Label 2821: @209255
66527 /* 209255 */ GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(209281), // Rule ID 1719 //
66528 /* 209260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66529 /* 209263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
66530 /* 209266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
66531 /* 209270 */ // (frint:{ *:[f64] } f64:{ *:[f64] }:$S) => (XSRDPIC:{ *:[f64] } ?:{ *:[f64] }:$S)
66532 /* 209270 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIC),
66533 /* 209275 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66534 /* 209279 */ GIR_RootConstrainSelectedInstOperands,
66535 /* 209280 */ // GIR_Coverage, 1719,
66536 /* 209280 */ GIR_Done,
66537 /* 209281 */ // Label 2827: @209281
66538 /* 209281 */ GIM_Reject,
66539 /* 209282 */ // Label 2822: @209282
66540 /* 209282 */ GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(209312), // Rule ID 2170 //
66541 /* 209287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
66542 /* 209290 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
66543 /* 209293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66544 /* 209297 */ // (frint:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPIX:{ *:[f128] } 0:{ *:[i32] }, ?:{ *:[f128] }:$vB, 3:{ *:[i32] })
66545 /* 209297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPIX),
66546 /* 209300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT]
66547 /* 209302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
66548 /* 209305 */ GIR_RootToRootCopy, /*OpIdx*/1, // vB
66549 /* 209307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
66550 /* 209310 */ GIR_RootConstrainSelectedInstOperands,
66551 /* 209311 */ // GIR_Coverage, 2170,
66552 /* 209311 */ GIR_EraseRootFromParent_Done,
66553 /* 209312 */ // Label 2828: @209312
66554 /* 209312 */ GIM_Reject,
66555 /* 209313 */ // Label 2823: @209313
66556 /* 209313 */ GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(209339), // Rule ID 1721 //
66557 /* 209318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66558 /* 209321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
66559 /* 209324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66560 /* 209328 */ // (frint:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$S) => (XVRDPIC:{ *:[v2f64] } ?:{ *:[v2f64] }:$S)
66561 /* 209328 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIC),
66562 /* 209333 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66563 /* 209337 */ GIR_RootConstrainSelectedInstOperands,
66564 /* 209338 */ // GIR_Coverage, 1721,
66565 /* 209338 */ GIR_Done,
66566 /* 209339 */ // Label 2829: @209339
66567 /* 209339 */ GIM_Reject,
66568 /* 209340 */ // Label 2824: @209340
66569 /* 209340 */ GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(209366), // Rule ID 1717 //
66570 /* 209345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66571 /* 209348 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
66572 /* 209351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66573 /* 209355 */ // (frint:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$S) => (XVRSPIC:{ *:[v4f32] } ?:{ *:[v4f32] }:$S)
66574 /* 209355 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIC),
66575 /* 209360 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66576 /* 209364 */ GIR_RootConstrainSelectedInstOperands,
66577 /* 209365 */ // GIR_Coverage, 1717,
66578 /* 209365 */ GIR_Done,
66579 /* 209366 */ // Label 2830: @209366
66580 /* 209366 */ GIM_Reject,
66581 /* 209367 */ // Label 2825: @209367
66582 /* 209367 */ GIM_Reject,
66583 /* 209368 */ // Label 75: @209368
66584 /* 209368 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2836*/ GIMT_Encode4(209604),
66585 /* 209379 */ /*GILLT_s32*//*Label 2831*/ GIMT_Encode4(209399),
66586 /* 209383 */ /*GILLT_s64*//*Label 2832*/ GIMT_Encode4(209467),
66587 /* 209387 */ /*GILLT_s128*//*Label 2833*/ GIMT_Encode4(209494),
66588 /* 209391 */ /*GILLT_v2s64*//*Label 2834*/ GIMT_Encode4(209525),
66589 /* 209395 */ /*GILLT_v4s32*//*Label 2835*/ GIMT_Encode4(209552),
66590 /* 209399 */ // Label 2831: @209399
66591 /* 209399 */ GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(209466), // Rule ID 1722 //
66592 /* 209404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66593 /* 209407 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
66594 /* 209410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
66595 /* 209414 */ // (fnearbyint:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIC:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] })
66596 /* 209414 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
66597 /* 209417 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66598 /* 209421 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66599 /* 209426 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S
66600 /* 209430 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID),
66601 /* 209435 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
66602 /* 209438 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIC),
66603 /* 209442 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
66604 /* 209447 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
66605 /* 209450 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
66606 /* 209452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
66607 /* 209455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66608 /* 209457 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
66609 /* 209460 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID),
66610 /* 209465 */ // GIR_Coverage, 1722,
66611 /* 209465 */ GIR_EraseRootFromParent_Done,
66612 /* 209466 */ // Label 2837: @209466
66613 /* 209466 */ GIM_Reject,
66614 /* 209467 */ // Label 2832: @209467
66615 /* 209467 */ GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(209493), // Rule ID 1723 //
66616 /* 209472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66617 /* 209475 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
66618 /* 209478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
66619 /* 209482 */ // (fnearbyint:{ *:[f64] } f64:{ *:[f64] }:$S) => (XSRDPIC:{ *:[f64] } ?:{ *:[f64] }:$S)
66620 /* 209482 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIC),
66621 /* 209487 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66622 /* 209491 */ GIR_RootConstrainSelectedInstOperands,
66623 /* 209492 */ // GIR_Coverage, 1723,
66624 /* 209492 */ GIR_Done,
66625 /* 209493 */ // Label 2838: @209493
66626 /* 209493 */ GIM_Reject,
66627 /* 209494 */ // Label 2833: @209494
66628 /* 209494 */ GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(209524), // Rule ID 2160 //
66629 /* 209499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
66630 /* 209502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
66631 /* 209505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66632 /* 209509 */ // (fnearbyint:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 0:{ *:[i32] }, ?:{ *:[f128] }:$vB, 3:{ *:[i32] })
66633 /* 209509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI),
66634 /* 209512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT]
66635 /* 209514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
66636 /* 209517 */ GIR_RootToRootCopy, /*OpIdx*/1, // vB
66637 /* 209519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
66638 /* 209522 */ GIR_RootConstrainSelectedInstOperands,
66639 /* 209523 */ // GIR_Coverage, 2160,
66640 /* 209523 */ GIR_EraseRootFromParent_Done,
66641 /* 209524 */ // Label 2839: @209524
66642 /* 209524 */ GIM_Reject,
66643 /* 209525 */ // Label 2834: @209525
66644 /* 209525 */ GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(209551), // Rule ID 1724 //
66645 /* 209530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66646 /* 209533 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
66647 /* 209536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66648 /* 209540 */ // (fnearbyint:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$S) => (XVRDPIC:{ *:[v2f64] } ?:{ *:[v2f64] }:$S)
66649 /* 209540 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIC),
66650 /* 209545 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66651 /* 209549 */ GIR_RootConstrainSelectedInstOperands,
66652 /* 209550 */ // GIR_Coverage, 1724,
66653 /* 209550 */ GIR_Done,
66654 /* 209551 */ // Label 2840: @209551
66655 /* 209551 */ GIM_Reject,
66656 /* 209552 */ // Label 2835: @209552
66657 /* 209552 */ GIM_Try, /*On fail goto*//*Label 2841*/ GIMT_Encode4(209603),
66658 /* 209557 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
66659 /* 209560 */ GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(209583), // Rule ID 1725 //
66660 /* 209565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66661 /* 209568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66662 /* 209572 */ // (fnearbyint:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$S) => (XVRSPIC:{ *:[v4f32] } ?:{ *:[v4f32] }:$S)
66663 /* 209572 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIC),
66664 /* 209577 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66665 /* 209581 */ GIR_RootConstrainSelectedInstOperands,
66666 /* 209582 */ // GIR_Coverage, 1725,
66667 /* 209582 */ GIR_Done,
66668 /* 209583 */ // Label 2842: @209583
66669 /* 209583 */ GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(209602), // Rule ID 1422 //
66670 /* 209588 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec),
66671 /* 209591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66672 /* 209595 */ // (fnearbyint:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIN:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA)
66673 /* 209595 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIN),
66674 /* 209600 */ GIR_RootConstrainSelectedInstOperands,
66675 /* 209601 */ // GIR_Coverage, 1422,
66676 /* 209601 */ GIR_Done,
66677 /* 209602 */ // Label 2843: @209602
66678 /* 209602 */ GIM_Reject,
66679 /* 209603 */ // Label 2841: @209603
66680 /* 209603 */ GIM_Reject,
66681 /* 209604 */ // Label 2836: @209604
66682 /* 209604 */ GIM_Reject,
66683 /* 209605 */ // Label 76: @209605
66684 /* 209605 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2849*/ GIMT_Encode4(209874),
66685 /* 209616 */ /*GILLT_s32*//*Label 2844*/ GIMT_Encode4(209636),
66686 /* 209620 */ /*GILLT_s64*//*Label 2845*/ GIMT_Encode4(209710),
66687 /* 209624 */ /*GILLT_s128*//*Label 2846*/ GIMT_Encode4(209788),
66688 /* 209628 */ /*GILLT_v2s64*//*Label 2847*/ GIMT_Encode4(209814),
66689 /* 209632 */ /*GILLT_v4s32*//*Label 2848*/ GIMT_Encode4(209844),
66690 /* 209636 */ // Label 2844: @209636
66691 /* 209636 */ GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(209709),
66692 /* 209641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
66693 /* 209644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
66694 /* 209647 */ GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(209666), // Rule ID 952 //
66695 /* 209652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
66696 /* 209655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
66697 /* 209659 */ // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSADDSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
66698 /* 209659 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDSP),
66699 /* 209664 */ GIR_RootConstrainSelectedInstOperands,
66700 /* 209665 */ // GIR_Coverage, 952,
66701 /* 209665 */ GIR_Done,
66702 /* 209666 */ // Label 2851: @209666
66703 /* 209666 */ GIM_Try, /*On fail goto*//*Label 2852*/ GIMT_Encode4(209689), // Rule ID 238 //
66704 /* 209671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66705 /* 209674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
66706 /* 209678 */ // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB)
66707 /* 209678 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FADDS),
66708 /* 209683 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66709 /* 209687 */ GIR_RootConstrainSelectedInstOperands,
66710 /* 209688 */ // GIR_Coverage, 238,
66711 /* 209688 */ GIR_Done,
66712 /* 209689 */ // Label 2852: @209689
66713 /* 209689 */ GIM_Try, /*On fail goto*//*Label 2853*/ GIMT_Encode4(209708), // Rule ID 582 //
66714 /* 209694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
66715 /* 209697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
66716 /* 209701 */ // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSADD:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
66717 /* 209701 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSADD),
66718 /* 209706 */ GIR_RootConstrainSelectedInstOperands,
66719 /* 209707 */ // GIR_Coverage, 582,
66720 /* 209707 */ GIR_Done,
66721 /* 209708 */ // Label 2853: @209708
66722 /* 209708 */ GIM_Reject,
66723 /* 209709 */ // Label 2850: @209709
66724 /* 209709 */ GIM_Reject,
66725 /* 209710 */ // Label 2845: @209710
66726 /* 209710 */ GIM_Try, /*On fail goto*//*Label 2854*/ GIMT_Encode4(209787),
66727 /* 209715 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
66728 /* 209718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
66729 /* 209721 */ GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(209744), // Rule ID 769 //
66730 /* 209726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66731 /* 209729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
66732 /* 209733 */ // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSADDDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
66733 /* 209733 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDDP),
66734 /* 209738 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66735 /* 209742 */ GIR_RootConstrainSelectedInstOperands,
66736 /* 209743 */ // GIR_Coverage, 769,
66737 /* 209743 */ GIR_Done,
66738 /* 209744 */ // Label 2855: @209744
66739 /* 209744 */ GIM_Try, /*On fail goto*//*Label 2856*/ GIMT_Encode4(209767), // Rule ID 236 //
66740 /* 209749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66741 /* 209752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
66742 /* 209756 */ // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB)
66743 /* 209756 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FADD),
66744 /* 209761 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66745 /* 209765 */ GIR_RootConstrainSelectedInstOperands,
66746 /* 209766 */ // GIR_Coverage, 236,
66747 /* 209766 */ GIR_Done,
66748 /* 209767 */ // Label 2856: @209767
66749 /* 209767 */ GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(209786), // Rule ID 561 //
66750 /* 209772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
66751 /* 209775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
66752 /* 209779 */ // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDADD:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
66753 /* 209779 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDADD),
66754 /* 209784 */ GIR_RootConstrainSelectedInstOperands,
66755 /* 209785 */ // GIR_Coverage, 561,
66756 /* 209785 */ GIR_Done,
66757 /* 209786 */ // Label 2857: @209786
66758 /* 209786 */ GIM_Reject,
66759 /* 209787 */ // Label 2854: @209787
66760 /* 209787 */ GIM_Reject,
66761 /* 209788 */ // Label 2846: @209788
66762 /* 209788 */ GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(209813), // Rule ID 987 //
66763 /* 209793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
66764 /* 209796 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
66765 /* 209799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
66766 /* 209802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66767 /* 209806 */ // (strict_fadd:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSADDQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
66768 /* 209806 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDQP),
66769 /* 209811 */ GIR_RootConstrainSelectedInstOperands,
66770 /* 209812 */ // GIR_Coverage, 987,
66771 /* 209812 */ GIR_Done,
66772 /* 209813 */ // Label 2858: @209813
66773 /* 209813 */ GIM_Reject,
66774 /* 209814 */ // Label 2847: @209814
66775 /* 209814 */ GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(209843), // Rule ID 773 //
66776 /* 209819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66777 /* 209822 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
66778 /* 209825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
66779 /* 209828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66780 /* 209832 */ // (strict_fadd:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVADDDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
66781 /* 209832 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVADDDP),
66782 /* 209837 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66783 /* 209841 */ GIR_RootConstrainSelectedInstOperands,
66784 /* 209842 */ // GIR_Coverage, 773,
66785 /* 209842 */ GIR_Done,
66786 /* 209843 */ // Label 2859: @209843
66787 /* 209843 */ GIM_Reject,
66788 /* 209844 */ // Label 2848: @209844
66789 /* 209844 */ GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(209873), // Rule ID 775 //
66790 /* 209849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66791 /* 209852 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
66792 /* 209855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
66793 /* 209858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66794 /* 209862 */ // (strict_fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVADDSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
66795 /* 209862 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVADDSP),
66796 /* 209867 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66797 /* 209871 */ GIR_RootConstrainSelectedInstOperands,
66798 /* 209872 */ // GIR_Coverage, 775,
66799 /* 209872 */ GIR_Done,
66800 /* 209873 */ // Label 2860: @209873
66801 /* 209873 */ GIM_Reject,
66802 /* 209874 */ // Label 2849: @209874
66803 /* 209874 */ GIM_Reject,
66804 /* 209875 */ // Label 77: @209875
66805 /* 209875 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2866*/ GIMT_Encode4(210144),
66806 /* 209886 */ /*GILLT_s32*//*Label 2861*/ GIMT_Encode4(209906),
66807 /* 209890 */ /*GILLT_s64*//*Label 2862*/ GIMT_Encode4(209980),
66808 /* 209894 */ /*GILLT_s128*//*Label 2863*/ GIMT_Encode4(210058),
66809 /* 209898 */ /*GILLT_v2s64*//*Label 2864*/ GIMT_Encode4(210084),
66810 /* 209902 */ /*GILLT_v4s32*//*Label 2865*/ GIMT_Encode4(210114),
66811 /* 209906 */ // Label 2861: @209906
66812 /* 209906 */ GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(209979),
66813 /* 209911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
66814 /* 209914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
66815 /* 209917 */ GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(209936), // Rule ID 956 //
66816 /* 209922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
66817 /* 209925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
66818 /* 209929 */ // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSSUBSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
66819 /* 209929 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBSP),
66820 /* 209934 */ GIR_RootConstrainSelectedInstOperands,
66821 /* 209935 */ // GIR_Coverage, 956,
66822 /* 209935 */ GIR_Done,
66823 /* 209936 */ // Label 2868: @209936
66824 /* 209936 */ GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(209959), // Rule ID 250 //
66825 /* 209941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66826 /* 209944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
66827 /* 209948 */ // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB)
66828 /* 209948 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSUBS),
66829 /* 209953 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66830 /* 209957 */ GIR_RootConstrainSelectedInstOperands,
66831 /* 209958 */ // GIR_Coverage, 250,
66832 /* 209958 */ GIR_Done,
66833 /* 209959 */ // Label 2869: @209959
66834 /* 209959 */ GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(209978), // Rule ID 600 //
66835 /* 209964 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
66836 /* 209967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
66837 /* 209971 */ // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSSUB:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
66838 /* 209971 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSSUB),
66839 /* 209976 */ GIR_RootConstrainSelectedInstOperands,
66840 /* 209977 */ // GIR_Coverage, 600,
66841 /* 209977 */ GIR_Done,
66842 /* 209978 */ // Label 2870: @209978
66843 /* 209978 */ GIM_Reject,
66844 /* 209979 */ // Label 2867: @209979
66845 /* 209979 */ GIM_Reject,
66846 /* 209980 */ // Label 2862: @209980
66847 /* 209980 */ GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(210057),
66848 /* 209985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
66849 /* 209988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
66850 /* 209991 */ GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(210014), // Rule ID 781 //
66851 /* 209996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66852 /* 209999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
66853 /* 210003 */ // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSSUBDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
66854 /* 210003 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBDP),
66855 /* 210008 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66856 /* 210012 */ GIR_RootConstrainSelectedInstOperands,
66857 /* 210013 */ // GIR_Coverage, 781,
66858 /* 210013 */ GIR_Done,
66859 /* 210014 */ // Label 2872: @210014
66860 /* 210014 */ GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(210037), // Rule ID 248 //
66861 /* 210019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66862 /* 210022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
66863 /* 210026 */ // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB)
66864 /* 210026 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSUB),
66865 /* 210031 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66866 /* 210035 */ GIR_RootConstrainSelectedInstOperands,
66867 /* 210036 */ // GIR_Coverage, 248,
66868 /* 210036 */ GIR_Done,
66869 /* 210037 */ // Label 2873: @210037
66870 /* 210037 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(210056), // Rule ID 579 //
66871 /* 210042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
66872 /* 210045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
66873 /* 210049 */ // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDSUB:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
66874 /* 210049 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDSUB),
66875 /* 210054 */ GIR_RootConstrainSelectedInstOperands,
66876 /* 210055 */ // GIR_Coverage, 579,
66877 /* 210055 */ GIR_Done,
66878 /* 210056 */ // Label 2874: @210056
66879 /* 210056 */ GIM_Reject,
66880 /* 210057 */ // Label 2871: @210057
66881 /* 210057 */ GIM_Reject,
66882 /* 210058 */ // Label 2863: @210058
66883 /* 210058 */ GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(210083), // Rule ID 991 //
66884 /* 210063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
66885 /* 210066 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
66886 /* 210069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
66887 /* 210072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
66888 /* 210076 */ // (strict_fsub:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
66889 /* 210076 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBQP),
66890 /* 210081 */ GIR_RootConstrainSelectedInstOperands,
66891 /* 210082 */ // GIR_Coverage, 991,
66892 /* 210082 */ GIR_Done,
66893 /* 210083 */ // Label 2875: @210083
66894 /* 210083 */ GIM_Reject,
66895 /* 210084 */ // Label 2864: @210084
66896 /* 210084 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(210113), // Rule ID 783 //
66897 /* 210089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66898 /* 210092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
66899 /* 210095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
66900 /* 210098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66901 /* 210102 */ // (strict_fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVSUBDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
66902 /* 210102 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSUBDP),
66903 /* 210107 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66904 /* 210111 */ GIR_RootConstrainSelectedInstOperands,
66905 /* 210112 */ // GIR_Coverage, 783,
66906 /* 210112 */ GIR_Done,
66907 /* 210113 */ // Label 2876: @210113
66908 /* 210113 */ GIM_Reject,
66909 /* 210114 */ // Label 2865: @210114
66910 /* 210114 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(210143), // Rule ID 785 //
66911 /* 210119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66912 /* 210122 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
66913 /* 210125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
66914 /* 210128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
66915 /* 210132 */ // (strict_fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVSUBSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
66916 /* 210132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSUBSP),
66917 /* 210137 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66918 /* 210141 */ GIR_RootConstrainSelectedInstOperands,
66919 /* 210142 */ // GIR_Coverage, 785,
66920 /* 210142 */ GIR_Done,
66921 /* 210143 */ // Label 2877: @210143
66922 /* 210143 */ GIM_Reject,
66923 /* 210144 */ // Label 2866: @210144
66924 /* 210144 */ GIM_Reject,
66925 /* 210145 */ // Label 78: @210145
66926 /* 210145 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2883*/ GIMT_Encode4(210414),
66927 /* 210156 */ /*GILLT_s32*//*Label 2878*/ GIMT_Encode4(210176),
66928 /* 210160 */ /*GILLT_s64*//*Label 2879*/ GIMT_Encode4(210250),
66929 /* 210164 */ /*GILLT_s128*//*Label 2880*/ GIMT_Encode4(210328),
66930 /* 210168 */ /*GILLT_v2s64*//*Label 2881*/ GIMT_Encode4(210354),
66931 /* 210172 */ /*GILLT_v4s32*//*Label 2882*/ GIMT_Encode4(210384),
66932 /* 210176 */ // Label 2878: @210176
66933 /* 210176 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(210249),
66934 /* 210181 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
66935 /* 210184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
66936 /* 210187 */ GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(210206), // Rule ID 954 //
66937 /* 210192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
66938 /* 210195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
66939 /* 210199 */ // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSMULSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
66940 /* 210199 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULSP),
66941 /* 210204 */ GIR_RootConstrainSelectedInstOperands,
66942 /* 210205 */ // GIR_Coverage, 954,
66943 /* 210205 */ GIR_Done,
66944 /* 210206 */ // Label 2885: @210206
66945 /* 210206 */ GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(210229), // Rule ID 246 //
66946 /* 210211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66947 /* 210214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
66948 /* 210218 */ // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) => (FMULS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC)
66949 /* 210218 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMULS),
66950 /* 210223 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66951 /* 210227 */ GIR_RootConstrainSelectedInstOperands,
66952 /* 210228 */ // GIR_Coverage, 246,
66953 /* 210228 */ GIR_Done,
66954 /* 210229 */ // Label 2886: @210229
66955 /* 210229 */ GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(210248), // Rule ID 596 //
66956 /* 210234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
66957 /* 210237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
66958 /* 210241 */ // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSMUL:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
66959 /* 210241 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSMUL),
66960 /* 210246 */ GIR_RootConstrainSelectedInstOperands,
66961 /* 210247 */ // GIR_Coverage, 596,
66962 /* 210247 */ GIR_Done,
66963 /* 210248 */ // Label 2887: @210248
66964 /* 210248 */ GIM_Reject,
66965 /* 210249 */ // Label 2884: @210249
66966 /* 210249 */ GIM_Reject,
66967 /* 210250 */ // Label 2879: @210250
66968 /* 210250 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(210327),
66969 /* 210255 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
66970 /* 210258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
66971 /* 210261 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(210284), // Rule ID 771 //
66972 /* 210266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
66973 /* 210269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
66974 /* 210273 */ // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSMULDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
66975 /* 210273 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULDP),
66976 /* 210278 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66977 /* 210282 */ GIR_RootConstrainSelectedInstOperands,
66978 /* 210283 */ // GIR_Coverage, 771,
66979 /* 210283 */ GIR_Done,
66980 /* 210284 */ // Label 2889: @210284
66981 /* 210284 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(210307), // Rule ID 244 //
66982 /* 210289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
66983 /* 210292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
66984 /* 210296 */ // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) => (FMUL:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC)
66985 /* 210296 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMUL),
66986 /* 210301 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
66987 /* 210305 */ GIR_RootConstrainSelectedInstOperands,
66988 /* 210306 */ // GIR_Coverage, 244,
66989 /* 210306 */ GIR_Done,
66990 /* 210307 */ // Label 2890: @210307
66991 /* 210307 */ GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(210326), // Rule ID 575 //
66992 /* 210312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
66993 /* 210315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
66994 /* 210319 */ // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDMUL:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
66995 /* 210319 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDMUL),
66996 /* 210324 */ GIR_RootConstrainSelectedInstOperands,
66997 /* 210325 */ // GIR_Coverage, 575,
66998 /* 210325 */ GIR_Done,
66999 /* 210326 */ // Label 2891: @210326
67000 /* 210326 */ GIM_Reject,
67001 /* 210327 */ // Label 2888: @210327
67002 /* 210327 */ GIM_Reject,
67003 /* 210328 */ // Label 2880: @210328
67004 /* 210328 */ GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(210353), // Rule ID 989 //
67005 /* 210333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
67006 /* 210336 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
67007 /* 210339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
67008 /* 210342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
67009 /* 210346 */ // (strict_fmul:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSMULQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
67010 /* 210346 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULQP),
67011 /* 210351 */ GIR_RootConstrainSelectedInstOperands,
67012 /* 210352 */ // GIR_Coverage, 989,
67013 /* 210352 */ GIR_Done,
67014 /* 210353 */ // Label 2892: @210353
67015 /* 210353 */ GIM_Reject,
67016 /* 210354 */ // Label 2881: @210354
67017 /* 210354 */ GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(210383), // Rule ID 777 //
67018 /* 210359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67019 /* 210362 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
67020 /* 210365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
67021 /* 210368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
67022 /* 210372 */ // (strict_fmul:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVMULDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
67023 /* 210372 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMULDP),
67024 /* 210377 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67025 /* 210381 */ GIR_RootConstrainSelectedInstOperands,
67026 /* 210382 */ // GIR_Coverage, 777,
67027 /* 210382 */ GIR_Done,
67028 /* 210383 */ // Label 2893: @210383
67029 /* 210383 */ GIM_Reject,
67030 /* 210384 */ // Label 2882: @210384
67031 /* 210384 */ GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(210413), // Rule ID 779 //
67032 /* 210389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67033 /* 210392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
67034 /* 210395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
67035 /* 210398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
67036 /* 210402 */ // (strict_fmul:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVMULSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
67037 /* 210402 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMULSP),
67038 /* 210407 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67039 /* 210411 */ GIR_RootConstrainSelectedInstOperands,
67040 /* 210412 */ // GIR_Coverage, 779,
67041 /* 210412 */ GIR_Done,
67042 /* 210413 */ // Label 2894: @210413
67043 /* 210413 */ GIM_Reject,
67044 /* 210414 */ // Label 2883: @210414
67045 /* 210414 */ GIM_Reject,
67046 /* 210415 */ // Label 79: @210415
67047 /* 210415 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2900*/ GIMT_Encode4(210684),
67048 /* 210426 */ /*GILLT_s32*//*Label 2895*/ GIMT_Encode4(210446),
67049 /* 210430 */ /*GILLT_s64*//*Label 2896*/ GIMT_Encode4(210520),
67050 /* 210434 */ /*GILLT_s128*//*Label 2897*/ GIMT_Encode4(210598),
67051 /* 210438 */ /*GILLT_v2s64*//*Label 2898*/ GIMT_Encode4(210624),
67052 /* 210442 */ /*GILLT_v4s32*//*Label 2899*/ GIMT_Encode4(210654),
67053 /* 210446 */ // Label 2895: @210446
67054 /* 210446 */ GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(210519),
67055 /* 210451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
67056 /* 210454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
67057 /* 210457 */ GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(210476), // Rule ID 958 //
67058 /* 210462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
67059 /* 210465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
67060 /* 210469 */ // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSDIVSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
67061 /* 210469 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVSP),
67062 /* 210474 */ GIR_RootConstrainSelectedInstOperands,
67063 /* 210475 */ // GIR_Coverage, 958,
67064 /* 210475 */ GIR_Done,
67065 /* 210476 */ // Label 2902: @210476
67066 /* 210476 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(210499), // Rule ID 242 //
67067 /* 210481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
67068 /* 210484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
67069 /* 210488 */ // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FDIVS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB)
67070 /* 210488 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FDIVS),
67071 /* 210493 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67072 /* 210497 */ GIR_RootConstrainSelectedInstOperands,
67073 /* 210498 */ // GIR_Coverage, 242,
67074 /* 210498 */ GIR_Done,
67075 /* 210499 */ // Label 2903: @210499
67076 /* 210499 */ GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(210518), // Rule ID 594 //
67077 /* 210504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
67078 /* 210507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID),
67079 /* 210511 */ // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSDIV:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB)
67080 /* 210511 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSDIV),
67081 /* 210516 */ GIR_RootConstrainSelectedInstOperands,
67082 /* 210517 */ // GIR_Coverage, 594,
67083 /* 210517 */ GIR_Done,
67084 /* 210518 */ // Label 2904: @210518
67085 /* 210518 */ GIM_Reject,
67086 /* 210519 */ // Label 2901: @210519
67087 /* 210519 */ GIM_Reject,
67088 /* 210520 */ // Label 2896: @210520
67089 /* 210520 */ GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(210597),
67090 /* 210525 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
67091 /* 210528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
67092 /* 210531 */ GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(210554), // Rule ID 810 //
67093 /* 210536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67094 /* 210539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
67095 /* 210543 */ // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSDIVDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
67096 /* 210543 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVDP),
67097 /* 210548 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67098 /* 210552 */ GIR_RootConstrainSelectedInstOperands,
67099 /* 210553 */ // GIR_Coverage, 810,
67100 /* 210553 */ GIR_Done,
67101 /* 210554 */ // Label 2906: @210554
67102 /* 210554 */ GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(210577), // Rule ID 240 //
67103 /* 210559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
67104 /* 210562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
67105 /* 210566 */ // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FDIV:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB)
67106 /* 210566 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FDIV),
67107 /* 210571 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67108 /* 210575 */ GIR_RootConstrainSelectedInstOperands,
67109 /* 210576 */ // GIR_Coverage, 240,
67110 /* 210576 */ GIR_Done,
67111 /* 210577 */ // Label 2907: @210577
67112 /* 210577 */ GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(210596), // Rule ID 573 //
67113 /* 210582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE),
67114 /* 210585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID),
67115 /* 210589 */ // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDDIV:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB)
67116 /* 210589 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDDIV),
67117 /* 210594 */ GIR_RootConstrainSelectedInstOperands,
67118 /* 210595 */ // GIR_Coverage, 573,
67119 /* 210595 */ GIR_Done,
67120 /* 210596 */ // Label 2908: @210596
67121 /* 210596 */ GIM_Reject,
67122 /* 210597 */ // Label 2905: @210597
67123 /* 210597 */ GIM_Reject,
67124 /* 210598 */ // Label 2897: @210598
67125 /* 210598 */ GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(210623), // Rule ID 993 //
67126 /* 210603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
67127 /* 210606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
67128 /* 210609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
67129 /* 210612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
67130 /* 210616 */ // (strict_fdiv:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSDIVQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
67131 /* 210616 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVQP),
67132 /* 210621 */ GIR_RootConstrainSelectedInstOperands,
67133 /* 210622 */ // GIR_Coverage, 993,
67134 /* 210622 */ GIR_Done,
67135 /* 210623 */ // Label 2909: @210623
67136 /* 210623 */ GIM_Reject,
67137 /* 210624 */ // Label 2898: @210624
67138 /* 210624 */ GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(210653), // Rule ID 819 //
67139 /* 210629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67140 /* 210632 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
67141 /* 210635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
67142 /* 210638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
67143 /* 210642 */ // (strict_fdiv:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVDIVDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
67144 /* 210642 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVDIVDP),
67145 /* 210647 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67146 /* 210651 */ GIR_RootConstrainSelectedInstOperands,
67147 /* 210652 */ // GIR_Coverage, 819,
67148 /* 210652 */ GIR_Done,
67149 /* 210653 */ // Label 2910: @210653
67150 /* 210653 */ GIM_Reject,
67151 /* 210654 */ // Label 2899: @210654
67152 /* 210654 */ GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(210683), // Rule ID 821 //
67153 /* 210659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67154 /* 210662 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
67155 /* 210665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
67156 /* 210668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
67157 /* 210672 */ // (strict_fdiv:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVDIVSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
67158 /* 210672 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVDIVSP),
67159 /* 210677 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67160 /* 210681 */ GIR_RootConstrainSelectedInstOperands,
67161 /* 210682 */ // GIR_Coverage, 821,
67162 /* 210682 */ GIR_Done,
67163 /* 210683 */ // Label 2911: @210683
67164 /* 210683 */ GIM_Reject,
67165 /* 210684 */ // Label 2900: @210684
67166 /* 210684 */ GIM_Reject,
67167 /* 210685 */ // Label 80: @210685
67168 /* 210685 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2917*/ GIMT_Encode4(211242),
67169 /* 210696 */ /*GILLT_s32*//*Label 2912*/ GIMT_Encode4(210716),
67170 /* 210700 */ /*GILLT_s64*//*Label 2913*/ GIMT_Encode4(210862),
67171 /* 210704 */ /*GILLT_s128*//*Label 2914*/ GIMT_Encode4(211008),
67172 /* 210708 */ /*GILLT_v2s64*//*Label 2915*/ GIMT_Encode4(211086),
67173 /* 210712 */ /*GILLT_v4s32*//*Label 2916*/ GIMT_Encode4(211164),
67174 /* 210716 */ // Label 2912: @210716
67175 /* 210716 */ GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(210861),
67176 /* 210721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
67177 /* 210724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
67178 /* 210727 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
67179 /* 210730 */ GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(210771), // Rule ID 968 //
67180 /* 210735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
67181 /* 210738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
67182 /* 210742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
67183 /* 210746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
67184 /* 210750 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
67185 /* 210754 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
67186 /* 210756 */ // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi)) => (XSMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
67187 /* 210756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBASP),
67188 /* 210759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
67189 /* 210761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi
67190 /* 210765 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
67191 /* 210767 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
67192 /* 210769 */ GIR_RootConstrainSelectedInstOperands,
67193 /* 210770 */ // GIR_Coverage, 968,
67194 /* 210770 */ GIR_EraseRootFromParent_Done,
67195 /* 210771 */ // Label 2919: @210771
67196 /* 210771 */ GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(210796), // Rule ID 966 //
67197 /* 210776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
67198 /* 210779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
67199 /* 210783 */ // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi) => (XSMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB)
67200 /* 210783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDASP),
67201 /* 210786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
67202 /* 210788 */ GIR_RootToRootCopy, /*OpIdx*/3, // XTi
67203 /* 210790 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
67204 /* 210792 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
67205 /* 210794 */ GIR_RootConstrainSelectedInstOperands,
67206 /* 210795 */ // GIR_Coverage, 966,
67207 /* 210795 */ GIR_EraseRootFromParent_Done,
67208 /* 210796 */ // Label 2920: @210796
67209 /* 210796 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(210837), // Rule ID 224 //
67210 /* 210801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
67211 /* 210804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
67212 /* 210808 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
67213 /* 210812 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
67214 /* 210816 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
67215 /* 210820 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
67216 /* 210822 */ // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB)) => (FMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)
67217 /* 210822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUBS),
67218 /* 210825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
67219 /* 210827 */ GIR_RootToRootCopy, /*OpIdx*/1, // FRA
67220 /* 210829 */ GIR_RootToRootCopy, /*OpIdx*/2, // FRC
67221 /* 210831 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB
67222 /* 210835 */ GIR_RootConstrainSelectedInstOperands,
67223 /* 210836 */ // GIR_Coverage, 224,
67224 /* 210836 */ GIR_EraseRootFromParent_Done,
67225 /* 210837 */ // Label 2921: @210837
67226 /* 210837 */ GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(210860), // Rule ID 220 //
67227 /* 210842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
67228 /* 210845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
67229 /* 210849 */ // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) => (FMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)
67230 /* 210849 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMADDS),
67231 /* 210854 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67232 /* 210858 */ GIR_RootConstrainSelectedInstOperands,
67233 /* 210859 */ // GIR_Coverage, 220,
67234 /* 210859 */ GIR_Done,
67235 /* 210860 */ // Label 2922: @210860
67236 /* 210860 */ GIM_Reject,
67237 /* 210861 */ // Label 2918: @210861
67238 /* 210861 */ GIM_Reject,
67239 /* 210862 */ // Label 2913: @210862
67240 /* 210862 */ GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(211007),
67241 /* 210867 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
67242 /* 210870 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
67243 /* 210873 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
67244 /* 210876 */ GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(210917), // Rule ID 789 //
67245 /* 210881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67246 /* 210884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
67247 /* 210888 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
67248 /* 210892 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
67249 /* 210896 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
67250 /* 210900 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
67251 /* 210902 */ // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi)) => (XSMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
67252 /* 210902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBADP),
67253 /* 210905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
67254 /* 210907 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi
67255 /* 210911 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
67256 /* 210913 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
67257 /* 210915 */ GIR_RootConstrainSelectedInstOperands,
67258 /* 210916 */ // GIR_Coverage, 789,
67259 /* 210916 */ GIR_EraseRootFromParent_Done,
67260 /* 210917 */ // Label 2924: @210917
67261 /* 210917 */ GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(210942), // Rule ID 787 //
67262 /* 210922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67263 /* 210925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
67264 /* 210929 */ // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi) => (XSMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB)
67265 /* 210929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDADP),
67266 /* 210932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
67267 /* 210934 */ GIR_RootToRootCopy, /*OpIdx*/3, // XTi
67268 /* 210936 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
67269 /* 210938 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
67270 /* 210940 */ GIR_RootConstrainSelectedInstOperands,
67271 /* 210941 */ // GIR_Coverage, 787,
67272 /* 210941 */ GIR_EraseRootFromParent_Done,
67273 /* 210942 */ // Label 2925: @210942
67274 /* 210942 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(210983), // Rule ID 222 //
67275 /* 210947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
67276 /* 210950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
67277 /* 210954 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
67278 /* 210958 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
67279 /* 210962 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
67280 /* 210966 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
67281 /* 210968 */ // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB)) => (FMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)
67282 /* 210968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUB),
67283 /* 210971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT]
67284 /* 210973 */ GIR_RootToRootCopy, /*OpIdx*/1, // FRA
67285 /* 210975 */ GIR_RootToRootCopy, /*OpIdx*/2, // FRC
67286 /* 210977 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB
67287 /* 210981 */ GIR_RootConstrainSelectedInstOperands,
67288 /* 210982 */ // GIR_Coverage, 222,
67289 /* 210982 */ GIR_EraseRootFromParent_Done,
67290 /* 210983 */ // Label 2926: @210983
67291 /* 210983 */ GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(211006), // Rule ID 218 //
67292 /* 210988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
67293 /* 210991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
67294 /* 210995 */ // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) => (FMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)
67295 /* 210995 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMADD),
67296 /* 211000 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67297 /* 211004 */ GIR_RootConstrainSelectedInstOperands,
67298 /* 211005 */ // GIR_Coverage, 218,
67299 /* 211005 */ GIR_Done,
67300 /* 211006 */ // Label 2927: @211006
67301 /* 211006 */ GIM_Reject,
67302 /* 211007 */ // Label 2923: @211007
67303 /* 211007 */ GIM_Reject,
67304 /* 211008 */ // Label 2914: @211008
67305 /* 211008 */ GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(211085),
67306 /* 211013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
67307 /* 211016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128,
67308 /* 211019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128,
67309 /* 211022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
67310 /* 211026 */ GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(211063), // Rule ID 999 //
67311 /* 211031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
67312 /* 211034 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
67313 /* 211038 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
67314 /* 211042 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128,
67315 /* 211046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
67316 /* 211048 */ // (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi)) => (XSMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
67317 /* 211048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBQP),
67318 /* 211051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
67319 /* 211053 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RSTi
67320 /* 211057 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
67321 /* 211059 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
67322 /* 211061 */ GIR_RootConstrainSelectedInstOperands,
67323 /* 211062 */ // GIR_Coverage, 999,
67324 /* 211062 */ GIR_EraseRootFromParent_Done,
67325 /* 211063 */ // Label 2929: @211063
67326 /* 211063 */ GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(211084), // Rule ID 997 //
67327 /* 211068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
67328 /* 211071 */ // (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi) => (XSMADDQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB)
67329 /* 211071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDQP),
67330 /* 211074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST]
67331 /* 211076 */ GIR_RootToRootCopy, /*OpIdx*/3, // RSTi
67332 /* 211078 */ GIR_RootToRootCopy, /*OpIdx*/1, // RA
67333 /* 211080 */ GIR_RootToRootCopy, /*OpIdx*/2, // RB
67334 /* 211082 */ GIR_RootConstrainSelectedInstOperands,
67335 /* 211083 */ // GIR_Coverage, 997,
67336 /* 211083 */ GIR_EraseRootFromParent_Done,
67337 /* 211084 */ // Label 2930: @211084
67338 /* 211084 */ GIM_Reject,
67339 /* 211085 */ // Label 2928: @211085
67340 /* 211085 */ GIM_Reject,
67341 /* 211086 */ // Label 2915: @211086
67342 /* 211086 */ GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(211163),
67343 /* 211091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
67344 /* 211094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
67345 /* 211097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
67346 /* 211100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
67347 /* 211104 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(211141), // Rule ID 799 //
67348 /* 211109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67349 /* 211112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
67350 /* 211116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
67351 /* 211120 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
67352 /* 211124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
67353 /* 211126 */ // (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi)) => (XVMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
67354 /* 211126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMSUBADP),
67355 /* 211129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
67356 /* 211131 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi
67357 /* 211135 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
67358 /* 211137 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
67359 /* 211139 */ GIR_RootConstrainSelectedInstOperands,
67360 /* 211140 */ // GIR_Coverage, 799,
67361 /* 211140 */ GIR_EraseRootFromParent_Done,
67362 /* 211141 */ // Label 2932: @211141
67363 /* 211141 */ GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(211162), // Rule ID 795 //
67364 /* 211146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67365 /* 211149 */ // (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi) => (XVMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB)
67366 /* 211149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMADDADP),
67367 /* 211152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
67368 /* 211154 */ GIR_RootToRootCopy, /*OpIdx*/3, // XTi
67369 /* 211156 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
67370 /* 211158 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
67371 /* 211160 */ GIR_RootConstrainSelectedInstOperands,
67372 /* 211161 */ // GIR_Coverage, 795,
67373 /* 211161 */ GIR_EraseRootFromParent_Done,
67374 /* 211162 */ // Label 2933: @211162
67375 /* 211162 */ GIM_Reject,
67376 /* 211163 */ // Label 2931: @211163
67377 /* 211163 */ GIM_Reject,
67378 /* 211164 */ // Label 2916: @211164
67379 /* 211164 */ GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(211241),
67380 /* 211169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
67381 /* 211172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
67382 /* 211175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
67383 /* 211178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
67384 /* 211182 */ GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(211219), // Rule ID 801 //
67385 /* 211187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67386 /* 211190 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
67387 /* 211194 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
67388 /* 211198 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
67389 /* 211202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
67390 /* 211204 */ // (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi)) => (XVMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
67391 /* 211204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMSUBASP),
67392 /* 211207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
67393 /* 211209 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi
67394 /* 211213 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
67395 /* 211215 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
67396 /* 211217 */ GIR_RootConstrainSelectedInstOperands,
67397 /* 211218 */ // GIR_Coverage, 801,
67398 /* 211218 */ GIR_EraseRootFromParent_Done,
67399 /* 211219 */ // Label 2935: @211219
67400 /* 211219 */ GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(211240), // Rule ID 797 //
67401 /* 211224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67402 /* 211227 */ // (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi) => (XVMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB)
67403 /* 211227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMADDASP),
67404 /* 211230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT]
67405 /* 211232 */ GIR_RootToRootCopy, /*OpIdx*/3, // XTi
67406 /* 211234 */ GIR_RootToRootCopy, /*OpIdx*/1, // XA
67407 /* 211236 */ GIR_RootToRootCopy, /*OpIdx*/2, // XB
67408 /* 211238 */ GIR_RootConstrainSelectedInstOperands,
67409 /* 211239 */ // GIR_Coverage, 797,
67410 /* 211239 */ GIR_EraseRootFromParent_Done,
67411 /* 211240 */ // Label 2936: @211240
67412 /* 211240 */ GIM_Reject,
67413 /* 211241 */ // Label 2934: @211241
67414 /* 211241 */ GIM_Reject,
67415 /* 211242 */ // Label 2917: @211242
67416 /* 211242 */ GIM_Reject,
67417 /* 211243 */ // Label 81: @211243
67418 /* 211243 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 2942*/ GIMT_Encode4(211459),
67419 /* 211254 */ /*GILLT_s32*//*Label 2937*/ GIMT_Encode4(211274),
67420 /* 211258 */ /*GILLT_s64*//*Label 2938*/ GIMT_Encode4(211326),
67421 /* 211262 */ /*GILLT_s128*//*Label 2939*/ GIMT_Encode4(211382),
67422 /* 211266 */ /*GILLT_v2s64*//*Label 2940*/ GIMT_Encode4(211405),
67423 /* 211270 */ /*GILLT_v4s32*//*Label 2941*/ GIMT_Encode4(211432),
67424 /* 211274 */ // Label 2937: @211274
67425 /* 211274 */ GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(211325),
67426 /* 211279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
67427 /* 211282 */ GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(211301), // Rule ID 963 //
67428 /* 211287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX),
67429 /* 211290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID),
67430 /* 211294 */ // (strict_fsqrt:{ *:[f32] } f32:{ *:[f32] }:$XB) => (XSSQRTSP:{ *:[f32] } f32:{ *:[f32] }:$XB)
67431 /* 211294 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTSP),
67432 /* 211299 */ GIR_RootConstrainSelectedInstOperands,
67433 /* 211300 */ // GIR_Coverage, 963,
67434 /* 211300 */ GIR_Done,
67435 /* 211301 */ // Label 2944: @211301
67436 /* 211301 */ GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(211324), // Rule ID 161 //
67437 /* 211306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
67438 /* 211309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID),
67439 /* 211313 */ // (strict_fsqrt:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FSQRTS:{ *:[f32] } f32:{ *:[f32] }:$RB)
67440 /* 211313 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSQRTS),
67441 /* 211318 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67442 /* 211322 */ GIR_RootConstrainSelectedInstOperands,
67443 /* 211323 */ // GIR_Coverage, 161,
67444 /* 211323 */ GIR_Done,
67445 /* 211324 */ // Label 2945: @211324
67446 /* 211324 */ GIM_Reject,
67447 /* 211325 */ // Label 2943: @211325
67448 /* 211325 */ GIM_Reject,
67449 /* 211326 */ // Label 2938: @211326
67450 /* 211326 */ GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(211381),
67451 /* 211331 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
67452 /* 211334 */ GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(211357), // Rule ID 812 //
67453 /* 211339 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67454 /* 211342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID),
67455 /* 211346 */ // (strict_fsqrt:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSSQRTDP:{ *:[f64] } f64:{ *:[f64] }:$XB)
67456 /* 211346 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTDP),
67457 /* 211351 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67458 /* 211355 */ GIR_RootConstrainSelectedInstOperands,
67459 /* 211356 */ // GIR_Coverage, 812,
67460 /* 211356 */ GIR_Done,
67461 /* 211357 */ // Label 2947: @211357
67462 /* 211357 */ GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(211380), // Rule ID 159 //
67463 /* 211362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU),
67464 /* 211365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID),
67465 /* 211369 */ // (strict_fsqrt:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FSQRT:{ *:[f64] } f64:{ *:[f64] }:$RB)
67466 /* 211369 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSQRT),
67467 /* 211374 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67468 /* 211378 */ GIR_RootConstrainSelectedInstOperands,
67469 /* 211379 */ // GIR_Coverage, 159,
67470 /* 211379 */ GIR_Done,
67471 /* 211380 */ // Label 2948: @211380
67472 /* 211380 */ GIM_Reject,
67473 /* 211381 */ // Label 2946: @211381
67474 /* 211381 */ GIM_Reject,
67475 /* 211382 */ // Label 2939: @211382
67476 /* 211382 */ GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(211404), // Rule ID 995 //
67477 /* 211387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX),
67478 /* 211390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
67479 /* 211393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID),
67480 /* 211397 */ // (strict_fsqrt:{ *:[f128] } f128:{ *:[f128] }:$RB) => (XSSQRTQP:{ *:[f128] } f128:{ *:[f128] }:$RB)
67481 /* 211397 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTQP),
67482 /* 211402 */ GIR_RootConstrainSelectedInstOperands,
67483 /* 211403 */ // GIR_Coverage, 995,
67484 /* 211403 */ GIR_Done,
67485 /* 211404 */ // Label 2949: @211404
67486 /* 211404 */ GIM_Reject,
67487 /* 211405 */ // Label 2940: @211405
67488 /* 211405 */ GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(211431), // Rule ID 823 //
67489 /* 211410 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67490 /* 211413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
67491 /* 211416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
67492 /* 211420 */ // (strict_fsqrt:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVSQRTDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)
67493 /* 211420 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSQRTDP),
67494 /* 211425 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67495 /* 211429 */ GIR_RootConstrainSelectedInstOperands,
67496 /* 211430 */ // GIR_Coverage, 823,
67497 /* 211430 */ GIR_Done,
67498 /* 211431 */ // Label 2950: @211431
67499 /* 211431 */ GIM_Reject,
67500 /* 211432 */ // Label 2941: @211432
67501 /* 211432 */ GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(211458), // Rule ID 825 //
67502 /* 211437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX),
67503 /* 211440 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
67504 /* 211443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID),
67505 /* 211447 */ // (strict_fsqrt:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVSQRTSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)
67506 /* 211447 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSQRTSP),
67507 /* 211452 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM),
67508 /* 211456 */ GIR_RootConstrainSelectedInstOperands,
67509 /* 211457 */ // GIR_Coverage, 825,
67510 /* 211457 */ GIR_Done,
67511 /* 211458 */ // Label 2951: @211458
67512 /* 211458 */ GIM_Reject,
67513 /* 211459 */ // Label 2942: @211459
67514 /* 211459 */ GIM_Reject,
67515 /* 211460 */ // Label 82: @211460
67516 /* 211460 */ GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(211472), // Rule ID 72 //
67517 /* 211465 */ // (trap) => (TRAP)
67518 /* 211465 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::TRAP),
67519 /* 211470 */ GIR_RootConstrainSelectedInstOperands,
67520 /* 211471 */ // GIR_Coverage, 72,
67521 /* 211471 */ GIR_Done,
67522 /* 211472 */ // Label 2952: @211472
67523 /* 211472 */ GIM_Reject,
67524 /* 211473 */ // Label 83: @211473
67525 /* 211473 */ GIM_Reject,
67526 /* 211474 */ }; // Size: 211474 bytes
67527 return MatchTable0;
67528}
67529#undef GIMT_Encode2
67530#undef GIMT_Encode4
67531#undef GIMT_Encode8
67532
67533#endif // ifdef GET_GLOBALISEL_IMPL
67534
67535#ifdef GET_GLOBALISEL_PREDICATES_DECL
67536PredicateBitset AvailableModuleFeatures;
67537mutable PredicateBitset AvailableFunctionFeatures;
67538PredicateBitset getAvailableFeatures() const {
67539 return AvailableModuleFeatures | AvailableFunctionFeatures;
67540}
67541PredicateBitset
67542computeAvailableModuleFeatures(const PPCSubtarget *Subtarget) const;
67543PredicateBitset
67544computeAvailableFunctionFeatures(const PPCSubtarget *Subtarget,
67545 const MachineFunction *MF) const;
67546void setupGeneratedPerFunctionState(MachineFunction &MF) override;
67547#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
67548#ifdef GET_GLOBALISEL_PREDICATES_INIT
67549AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
67550AvailableFunctionFeatures()
67551#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
67552