1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::PPC {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 ATOMIC_CMP_SWAP_I128 = 310,
324 ATOMIC_LOAD_ADD_I128 = 311,
325 ATOMIC_LOAD_AND_I128 = 312,
326 ATOMIC_LOAD_NAND_I128 = 313,
327 ATOMIC_LOAD_OR_I128 = 314,
328 ATOMIC_LOAD_SUB_I128 = 315,
329 ATOMIC_LOAD_XOR_I128 = 316,
330 ATOMIC_SWAP_I128 = 317,
331 BUILD_QUADWORD = 318,
332 BUILD_UACC = 319,
333 CFENCE = 320,
334 CFENCE8 = 321,
335 CLRLSLDI = 322,
336 CLRLSLDI_rec = 323,
337 CLRLSLWI = 324,
338 CLRLSLWI_rec = 325,
339 CLRRDI = 326,
340 CLRRDI_rec = 327,
341 CLRRWI = 328,
342 CLRRWI_rec = 329,
343 DCBFL = 330,
344 DCBFLP = 331,
345 DCBFPS = 332,
346 DCBFx = 333,
347 DCBSTPS = 334,
348 DCBTCT = 335,
349 DCBTDS = 336,
350 DCBTSTCT = 337,
351 DCBTSTDS = 338,
352 DCBTSTT = 339,
353 DCBTSTx = 340,
354 DCBTT = 341,
355 DCBTx = 342,
356 DFLOADf32 = 343,
357 DFLOADf64 = 344,
358 DFSTOREf32 = 345,
359 DFSTOREf64 = 346,
360 EXTLDI = 347,
361 EXTLDI_rec = 348,
362 EXTLWI = 349,
363 EXTLWI_rec = 350,
364 EXTRDI = 351,
365 EXTRDI_rec = 352,
366 EXTRWI = 353,
367 EXTRWI_rec = 354,
368 INSLWI = 355,
369 INSLWI_rec = 356,
370 INSRDI = 357,
371 INSRDI_rec = 358,
372 INSRWI = 359,
373 INSRWI_rec = 360,
374 KILL_PAIR = 361,
375 LAx = 362,
376 LIWAX = 363,
377 LIWZX = 364,
378 PPCLdFixedAddr = 365,
379 PSUBI = 366,
380 RLWIMIbm = 367,
381 RLWIMIbm_rec = 368,
382 RLWINMbm = 369,
383 RLWINMbm_rec = 370,
384 RLWNMbm = 371,
385 RLWNMbm_rec = 372,
386 ROTRDI = 373,
387 ROTRDI_rec = 374,
388 ROTRWI = 375,
389 ROTRWI_rec = 376,
390 SLDI = 377,
391 SLDI_rec = 378,
392 SLWI = 379,
393 SLWI_rec = 380,
394 SPILLTOVSR_LD = 381,
395 SPILLTOVSR_LDX = 382,
396 SPILLTOVSR_ST = 383,
397 SPILLTOVSR_STX = 384,
398 SRDI = 385,
399 SRDI_rec = 386,
400 SRWI = 387,
401 SRWI_rec = 388,
402 STIWX = 389,
403 SUBI = 390,
404 SUBIC = 391,
405 SUBIC_rec = 392,
406 SUBIS = 393,
407 SUBPCIS = 394,
408 XFLOADf32 = 395,
409 XFLOADf64 = 396,
410 XFSTOREf32 = 397,
411 XFSTOREf64 = 398,
412 ADD4 = 399,
413 ADD4O = 400,
414 ADD4O_rec = 401,
415 ADD4TLS = 402,
416 ADD4_rec = 403,
417 ADD8 = 404,
418 ADD8O = 405,
419 ADD8O_rec = 406,
420 ADD8TLS = 407,
421 ADD8TLS_ = 408,
422 ADD8_rec = 409,
423 ADDC = 410,
424 ADDC8 = 411,
425 ADDC8O = 412,
426 ADDC8O_rec = 413,
427 ADDC8_rec = 414,
428 ADDCO = 415,
429 ADDCO_rec = 416,
430 ADDC_rec = 417,
431 ADDE = 418,
432 ADDE8 = 419,
433 ADDE8O = 420,
434 ADDE8O_rec = 421,
435 ADDE8_rec = 422,
436 ADDEO = 423,
437 ADDEO_rec = 424,
438 ADDEX = 425,
439 ADDEX8 = 426,
440 ADDE_rec = 427,
441 ADDG6S = 428,
442 ADDG6S8 = 429,
443 ADDI = 430,
444 ADDI8 = 431,
445 ADDIC = 432,
446 ADDIC8 = 433,
447 ADDIC_rec = 434,
448 ADDIS = 435,
449 ADDIS8 = 436,
450 ADDISdtprelHA = 437,
451 ADDISdtprelHA32 = 438,
452 ADDISgotTprelHA = 439,
453 ADDIStlsgdHA = 440,
454 ADDIStlsldHA = 441,
455 ADDIStocHA = 442,
456 ADDIStocHA8 = 443,
457 ADDIdtprelL = 444,
458 ADDIdtprelL32 = 445,
459 ADDItlsgdL = 446,
460 ADDItlsgdL32 = 447,
461 ADDItlsgdLADDR = 448,
462 ADDItlsgdLADDR32 = 449,
463 ADDItlsldL = 450,
464 ADDItlsldL32 = 451,
465 ADDItlsldLADDR = 452,
466 ADDItlsldLADDR32 = 453,
467 ADDItoc = 454,
468 ADDItoc8 = 455,
469 ADDItocL = 456,
470 ADDItocL8 = 457,
471 ADDME = 458,
472 ADDME8 = 459,
473 ADDME8O = 460,
474 ADDME8O_rec = 461,
475 ADDME8_rec = 462,
476 ADDMEO = 463,
477 ADDMEO_rec = 464,
478 ADDME_rec = 465,
479 ADDPCIS = 466,
480 ADDZE = 467,
481 ADDZE8 = 468,
482 ADDZE8O = 469,
483 ADDZE8O_rec = 470,
484 ADDZE8_rec = 471,
485 ADDZEO = 472,
486 ADDZEO_rec = 473,
487 ADDZE_rec = 474,
488 ADJCALLSTACKDOWN = 475,
489 ADJCALLSTACKUP = 476,
490 AND = 477,
491 AND8 = 478,
492 AND8_rec = 479,
493 ANDC = 480,
494 ANDC8 = 481,
495 ANDC8_rec = 482,
496 ANDC_rec = 483,
497 ANDI8_rec = 484,
498 ANDIS8_rec = 485,
499 ANDIS_rec = 486,
500 ANDI_rec = 487,
501 ANDI_rec_1_EQ_BIT = 488,
502 ANDI_rec_1_EQ_BIT8 = 489,
503 ANDI_rec_1_GT_BIT = 490,
504 ANDI_rec_1_GT_BIT8 = 491,
505 AND_rec = 492,
506 ATOMIC_CMP_SWAP_I16 = 493,
507 ATOMIC_CMP_SWAP_I32 = 494,
508 ATOMIC_CMP_SWAP_I64 = 495,
509 ATOMIC_CMP_SWAP_I8 = 496,
510 ATOMIC_LOAD_ADD_I16 = 497,
511 ATOMIC_LOAD_ADD_I32 = 498,
512 ATOMIC_LOAD_ADD_I64 = 499,
513 ATOMIC_LOAD_ADD_I8 = 500,
514 ATOMIC_LOAD_AND_I16 = 501,
515 ATOMIC_LOAD_AND_I32 = 502,
516 ATOMIC_LOAD_AND_I64 = 503,
517 ATOMIC_LOAD_AND_I8 = 504,
518 ATOMIC_LOAD_MAX_I16 = 505,
519 ATOMIC_LOAD_MAX_I32 = 506,
520 ATOMIC_LOAD_MAX_I64 = 507,
521 ATOMIC_LOAD_MAX_I8 = 508,
522 ATOMIC_LOAD_MIN_I16 = 509,
523 ATOMIC_LOAD_MIN_I32 = 510,
524 ATOMIC_LOAD_MIN_I64 = 511,
525 ATOMIC_LOAD_MIN_I8 = 512,
526 ATOMIC_LOAD_NAND_I16 = 513,
527 ATOMIC_LOAD_NAND_I32 = 514,
528 ATOMIC_LOAD_NAND_I64 = 515,
529 ATOMIC_LOAD_NAND_I8 = 516,
530 ATOMIC_LOAD_OR_I16 = 517,
531 ATOMIC_LOAD_OR_I32 = 518,
532 ATOMIC_LOAD_OR_I64 = 519,
533 ATOMIC_LOAD_OR_I8 = 520,
534 ATOMIC_LOAD_SUB_I16 = 521,
535 ATOMIC_LOAD_SUB_I32 = 522,
536 ATOMIC_LOAD_SUB_I64 = 523,
537 ATOMIC_LOAD_SUB_I8 = 524,
538 ATOMIC_LOAD_UMAX_I16 = 525,
539 ATOMIC_LOAD_UMAX_I32 = 526,
540 ATOMIC_LOAD_UMAX_I64 = 527,
541 ATOMIC_LOAD_UMAX_I8 = 528,
542 ATOMIC_LOAD_UMIN_I16 = 529,
543 ATOMIC_LOAD_UMIN_I32 = 530,
544 ATOMIC_LOAD_UMIN_I64 = 531,
545 ATOMIC_LOAD_UMIN_I8 = 532,
546 ATOMIC_LOAD_XOR_I16 = 533,
547 ATOMIC_LOAD_XOR_I32 = 534,
548 ATOMIC_LOAD_XOR_I64 = 535,
549 ATOMIC_LOAD_XOR_I8 = 536,
550 ATOMIC_SWAP_I16 = 537,
551 ATOMIC_SWAP_I32 = 538,
552 ATOMIC_SWAP_I64 = 539,
553 ATOMIC_SWAP_I8 = 540,
554 ATTN = 541,
555 B = 542,
556 BA = 543,
557 BC = 544,
558 BCC = 545,
559 BCCA = 546,
560 BCCCTR = 547,
561 BCCCTR8 = 548,
562 BCCCTRL = 549,
563 BCCCTRL8 = 550,
564 BCCL = 551,
565 BCCLA = 552,
566 BCCLR = 553,
567 BCCLRL = 554,
568 BCCTR = 555,
569 BCCTR8 = 556,
570 BCCTR8n = 557,
571 BCCTRL = 558,
572 BCCTRL8 = 559,
573 BCCTRL8n = 560,
574 BCCTRLn = 561,
575 BCCTRn = 562,
576 BCDADD_rec = 563,
577 BCDCFN_rec = 564,
578 BCDCFSQ_rec = 565,
579 BCDCFZ_rec = 566,
580 BCDCPSGN_rec = 567,
581 BCDCTN_rec = 568,
582 BCDCTSQ_rec = 569,
583 BCDCTZ_rec = 570,
584 BCDSETSGN_rec = 571,
585 BCDSR_rec = 572,
586 BCDSUB_rec = 573,
587 BCDS_rec = 574,
588 BCDTRUNC_rec = 575,
589 BCDUS_rec = 576,
590 BCDUTRUNC_rec = 577,
591 BCL = 578,
592 BCLR = 579,
593 BCLRL = 580,
594 BCLRLn = 581,
595 BCLRn = 582,
596 BCLalways = 583,
597 BCLn = 584,
598 BCTR = 585,
599 BCTR8 = 586,
600 BCTRL = 587,
601 BCTRL8 = 588,
602 BCTRL8_LDinto_toc = 589,
603 BCTRL8_LDinto_toc_RM = 590,
604 BCTRL8_RM = 591,
605 BCTRL_LWZinto_toc = 592,
606 BCTRL_LWZinto_toc_RM = 593,
607 BCTRL_RM = 594,
608 BCn = 595,
609 BDNZ = 596,
610 BDNZ8 = 597,
611 BDNZA = 598,
612 BDNZAm = 599,
613 BDNZAp = 600,
614 BDNZL = 601,
615 BDNZLA = 602,
616 BDNZLAm = 603,
617 BDNZLAp = 604,
618 BDNZLR = 605,
619 BDNZLR8 = 606,
620 BDNZLRL = 607,
621 BDNZLRLm = 608,
622 BDNZLRLp = 609,
623 BDNZLRm = 610,
624 BDNZLRp = 611,
625 BDNZLm = 612,
626 BDNZLp = 613,
627 BDNZm = 614,
628 BDNZp = 615,
629 BDZ = 616,
630 BDZ8 = 617,
631 BDZA = 618,
632 BDZAm = 619,
633 BDZAp = 620,
634 BDZL = 621,
635 BDZLA = 622,
636 BDZLAm = 623,
637 BDZLAp = 624,
638 BDZLR = 625,
639 BDZLR8 = 626,
640 BDZLRL = 627,
641 BDZLRLm = 628,
642 BDZLRLp = 629,
643 BDZLRm = 630,
644 BDZLRp = 631,
645 BDZLm = 632,
646 BDZLp = 633,
647 BDZm = 634,
648 BDZp = 635,
649 BL = 636,
650 BL8 = 637,
651 BL8_NOP = 638,
652 BL8_NOP_RM = 639,
653 BL8_NOP_TLS = 640,
654 BL8_NOTOC = 641,
655 BL8_NOTOC_RM = 642,
656 BL8_NOTOC_TLS = 643,
657 BL8_RM = 644,
658 BL8_TLS = 645,
659 BL8_TLS_ = 646,
660 BLA = 647,
661 BLA8 = 648,
662 BLA8_NOP = 649,
663 BLA8_NOP_RM = 650,
664 BLA8_RM = 651,
665 BLA_RM = 652,
666 BLR = 653,
667 BLR8 = 654,
668 BLRL = 655,
669 BL_NOP = 656,
670 BL_NOP_RM = 657,
671 BL_RM = 658,
672 BL_TLS = 659,
673 BPERMD = 660,
674 BRD = 661,
675 BRH = 662,
676 BRH8 = 663,
677 BRINC = 664,
678 BRW = 665,
679 BRW8 = 666,
680 CBCDTD = 667,
681 CBCDTD8 = 668,
682 CDTBCD = 669,
683 CDTBCD8 = 670,
684 CFUGED = 671,
685 CLRBHRB = 672,
686 CMPB = 673,
687 CMPB8 = 674,
688 CMPD = 675,
689 CMPDI = 676,
690 CMPEQB = 677,
691 CMPLD = 678,
692 CMPLDI = 679,
693 CMPLW = 680,
694 CMPLWI = 681,
695 CMPRB = 682,
696 CMPRB8 = 683,
697 CMPW = 684,
698 CMPWI = 685,
699 CNTLZD = 686,
700 CNTLZDM = 687,
701 CNTLZD_rec = 688,
702 CNTLZW = 689,
703 CNTLZW8 = 690,
704 CNTLZW8_rec = 691,
705 CNTLZW_rec = 692,
706 CNTTZD = 693,
707 CNTTZDM = 694,
708 CNTTZD_rec = 695,
709 CNTTZW = 696,
710 CNTTZW8 = 697,
711 CNTTZW8_rec = 698,
712 CNTTZW_rec = 699,
713 CP_ABORT = 700,
714 CP_COPY = 701,
715 CP_COPY8 = 702,
716 CP_PASTE8_rec = 703,
717 CP_PASTE_rec = 704,
718 CR6SET = 705,
719 CR6UNSET = 706,
720 CRAND = 707,
721 CRANDC = 708,
722 CREQV = 709,
723 CRNAND = 710,
724 CRNOR = 711,
725 CRNOT = 712,
726 CROR = 713,
727 CRORC = 714,
728 CRSET = 715,
729 CRUNSET = 716,
730 CRXOR = 717,
731 CTRL_DEP = 718,
732 DADD = 719,
733 DADDQ = 720,
734 DADDQ_rec = 721,
735 DADD_rec = 722,
736 DARN = 723,
737 DCBA = 724,
738 DCBF = 725,
739 DCBFEP = 726,
740 DCBI = 727,
741 DCBST = 728,
742 DCBSTEP = 729,
743 DCBT = 730,
744 DCBTEP = 731,
745 DCBTST = 732,
746 DCBTSTEP = 733,
747 DCBZ = 734,
748 DCBZEP = 735,
749 DCBZL = 736,
750 DCBZLEP = 737,
751 DCCCI = 738,
752 DCFFIX = 739,
753 DCFFIXQ = 740,
754 DCFFIXQQ = 741,
755 DCFFIXQ_rec = 742,
756 DCFFIX_rec = 743,
757 DCMPO = 744,
758 DCMPOQ = 745,
759 DCMPU = 746,
760 DCMPUQ = 747,
761 DCTDP = 748,
762 DCTDP_rec = 749,
763 DCTFIX = 750,
764 DCTFIXQ = 751,
765 DCTFIXQQ = 752,
766 DCTFIXQ_rec = 753,
767 DCTFIX_rec = 754,
768 DCTQPQ = 755,
769 DCTQPQ_rec = 756,
770 DDEDPD = 757,
771 DDEDPDQ = 758,
772 DDEDPDQ_rec = 759,
773 DDEDPD_rec = 760,
774 DDIV = 761,
775 DDIVQ = 762,
776 DDIVQ_rec = 763,
777 DDIV_rec = 764,
778 DENBCD = 765,
779 DENBCDQ = 766,
780 DENBCDQ_rec = 767,
781 DENBCD_rec = 768,
782 DIEX = 769,
783 DIEXQ = 770,
784 DIEXQ_rec = 771,
785 DIEX_rec = 772,
786 DIVD = 773,
787 DIVDE = 774,
788 DIVDEO = 775,
789 DIVDEO_rec = 776,
790 DIVDEU = 777,
791 DIVDEUO = 778,
792 DIVDEUO_rec = 779,
793 DIVDEU_rec = 780,
794 DIVDE_rec = 781,
795 DIVDO = 782,
796 DIVDO_rec = 783,
797 DIVDU = 784,
798 DIVDUO = 785,
799 DIVDUO_rec = 786,
800 DIVDU_rec = 787,
801 DIVD_rec = 788,
802 DIVW = 789,
803 DIVWE = 790,
804 DIVWEO = 791,
805 DIVWEO_rec = 792,
806 DIVWEU = 793,
807 DIVWEUO = 794,
808 DIVWEUO_rec = 795,
809 DIVWEU_rec = 796,
810 DIVWE_rec = 797,
811 DIVWO = 798,
812 DIVWO_rec = 799,
813 DIVWU = 800,
814 DIVWUO = 801,
815 DIVWUO_rec = 802,
816 DIVWU_rec = 803,
817 DIVW_rec = 804,
818 DMMR = 805,
819 DMSETDMRZ = 806,
820 DMSHA2HASH = 807,
821 DMSHA3HASH = 808,
822 DMUL = 809,
823 DMULQ = 810,
824 DMULQ_rec = 811,
825 DMUL_rec = 812,
826 DMXOR = 813,
827 DMXVBF16GERX2 = 814,
828 DMXVBF16GERX2NN = 815,
829 DMXVBF16GERX2NP = 816,
830 DMXVBF16GERX2PN = 817,
831 DMXVBF16GERX2PP = 818,
832 DMXVF16GERX2 = 819,
833 DMXVF16GERX2NN = 820,
834 DMXVF16GERX2NP = 821,
835 DMXVF16GERX2PN = 822,
836 DMXVF16GERX2PP = 823,
837 DMXVI8GERX4 = 824,
838 DMXVI8GERX4PP = 825,
839 DMXVI8GERX4SPP = 826,
840 DMXXEXTFDMR256 = 827,
841 DMXXEXTFDMR512 = 828,
842 DMXXEXTFDMR512_HI = 829,
843 DMXXINSTDMR256 = 830,
844 DMXXINSTDMR512 = 831,
845 DMXXINSTDMR512_HI = 832,
846 DMXXSETACCZ = 833,
847 DMXXSHAPAD = 834,
848 DQUA = 835,
849 DQUAI = 836,
850 DQUAIQ = 837,
851 DQUAIQ_rec = 838,
852 DQUAI_rec = 839,
853 DQUAQ = 840,
854 DQUAQ_rec = 841,
855 DQUA_rec = 842,
856 DRDPQ = 843,
857 DRDPQ_rec = 844,
858 DRINTN = 845,
859 DRINTNQ = 846,
860 DRINTNQ_rec = 847,
861 DRINTN_rec = 848,
862 DRINTX = 849,
863 DRINTXQ = 850,
864 DRINTXQ_rec = 851,
865 DRINTX_rec = 852,
866 DRRND = 853,
867 DRRNDQ = 854,
868 DRRNDQ_rec = 855,
869 DRRND_rec = 856,
870 DRSP = 857,
871 DRSP_rec = 858,
872 DSCLI = 859,
873 DSCLIQ = 860,
874 DSCLIQ_rec = 861,
875 DSCLI_rec = 862,
876 DSCRI = 863,
877 DSCRIQ = 864,
878 DSCRIQ_rec = 865,
879 DSCRI_rec = 866,
880 DSS = 867,
881 DSSALL = 868,
882 DST = 869,
883 DST64 = 870,
884 DSTST = 871,
885 DSTST64 = 872,
886 DSTSTT = 873,
887 DSTSTT64 = 874,
888 DSTT = 875,
889 DSTT64 = 876,
890 DSUB = 877,
891 DSUBQ = 878,
892 DSUBQ_rec = 879,
893 DSUB_rec = 880,
894 DTSTDC = 881,
895 DTSTDCQ = 882,
896 DTSTDG = 883,
897 DTSTDGQ = 884,
898 DTSTEX = 885,
899 DTSTEXQ = 886,
900 DTSTSF = 887,
901 DTSTSFI = 888,
902 DTSTSFIQ = 889,
903 DTSTSFQ = 890,
904 DXEX = 891,
905 DXEXQ = 892,
906 DXEXQ_rec = 893,
907 DXEX_rec = 894,
908 DYNALLOC = 895,
909 DYNALLOC8 = 896,
910 DYNAREAOFFSET = 897,
911 DYNAREAOFFSET8 = 898,
912 DecreaseCTR8loop = 899,
913 DecreaseCTRloop = 900,
914 EFDABS = 901,
915 EFDADD = 902,
916 EFDCFS = 903,
917 EFDCFSF = 904,
918 EFDCFSI = 905,
919 EFDCFSID = 906,
920 EFDCFUF = 907,
921 EFDCFUI = 908,
922 EFDCFUID = 909,
923 EFDCMPEQ = 910,
924 EFDCMPGT = 911,
925 EFDCMPLT = 912,
926 EFDCTSF = 913,
927 EFDCTSI = 914,
928 EFDCTSIDZ = 915,
929 EFDCTSIZ = 916,
930 EFDCTUF = 917,
931 EFDCTUI = 918,
932 EFDCTUIDZ = 919,
933 EFDCTUIZ = 920,
934 EFDDIV = 921,
935 EFDMUL = 922,
936 EFDNABS = 923,
937 EFDNEG = 924,
938 EFDSUB = 925,
939 EFDTSTEQ = 926,
940 EFDTSTGT = 927,
941 EFDTSTLT = 928,
942 EFSABS = 929,
943 EFSADD = 930,
944 EFSCFD = 931,
945 EFSCFSF = 932,
946 EFSCFSI = 933,
947 EFSCFUF = 934,
948 EFSCFUI = 935,
949 EFSCMPEQ = 936,
950 EFSCMPGT = 937,
951 EFSCMPLT = 938,
952 EFSCTSF = 939,
953 EFSCTSI = 940,
954 EFSCTSIZ = 941,
955 EFSCTUF = 942,
956 EFSCTUI = 943,
957 EFSCTUIZ = 944,
958 EFSDIV = 945,
959 EFSMUL = 946,
960 EFSNABS = 947,
961 EFSNEG = 948,
962 EFSSUB = 949,
963 EFSTSTEQ = 950,
964 EFSTSTGT = 951,
965 EFSTSTLT = 952,
966 EH_SjLj_LongJmp32 = 953,
967 EH_SjLj_LongJmp64 = 954,
968 EH_SjLj_SetJmp32 = 955,
969 EH_SjLj_SetJmp64 = 956,
970 EH_SjLj_Setup = 957,
971 EQV = 958,
972 EQV8 = 959,
973 EQV8_rec = 960,
974 EQV_rec = 961,
975 EVABS = 962,
976 EVADDIW = 963,
977 EVADDSMIAAW = 964,
978 EVADDSSIAAW = 965,
979 EVADDUMIAAW = 966,
980 EVADDUSIAAW = 967,
981 EVADDW = 968,
982 EVAND = 969,
983 EVANDC = 970,
984 EVCMPEQ = 971,
985 EVCMPGTS = 972,
986 EVCMPGTU = 973,
987 EVCMPLTS = 974,
988 EVCMPLTU = 975,
989 EVCNTLSW = 976,
990 EVCNTLZW = 977,
991 EVDIVWS = 978,
992 EVDIVWU = 979,
993 EVEQV = 980,
994 EVEXTSB = 981,
995 EVEXTSH = 982,
996 EVFSABS = 983,
997 EVFSADD = 984,
998 EVFSCFSF = 985,
999 EVFSCFSI = 986,
1000 EVFSCFUF = 987,
1001 EVFSCFUI = 988,
1002 EVFSCMPEQ = 989,
1003 EVFSCMPGT = 990,
1004 EVFSCMPLT = 991,
1005 EVFSCTSF = 992,
1006 EVFSCTSI = 993,
1007 EVFSCTSIZ = 994,
1008 EVFSCTUF = 995,
1009 EVFSCTUI = 996,
1010 EVFSCTUIZ = 997,
1011 EVFSDIV = 998,
1012 EVFSMUL = 999,
1013 EVFSNABS = 1000,
1014 EVFSNEG = 1001,
1015 EVFSSUB = 1002,
1016 EVFSTSTEQ = 1003,
1017 EVFSTSTGT = 1004,
1018 EVFSTSTLT = 1005,
1019 EVLDD = 1006,
1020 EVLDDX = 1007,
1021 EVLDH = 1008,
1022 EVLDHX = 1009,
1023 EVLDW = 1010,
1024 EVLDWX = 1011,
1025 EVLHHESPLAT = 1012,
1026 EVLHHESPLATX = 1013,
1027 EVLHHOSSPLAT = 1014,
1028 EVLHHOSSPLATX = 1015,
1029 EVLHHOUSPLAT = 1016,
1030 EVLHHOUSPLATX = 1017,
1031 EVLWHE = 1018,
1032 EVLWHEX = 1019,
1033 EVLWHOS = 1020,
1034 EVLWHOSX = 1021,
1035 EVLWHOU = 1022,
1036 EVLWHOUX = 1023,
1037 EVLWHSPLAT = 1024,
1038 EVLWHSPLATX = 1025,
1039 EVLWWSPLAT = 1026,
1040 EVLWWSPLATX = 1027,
1041 EVMERGEHI = 1028,
1042 EVMERGEHILO = 1029,
1043 EVMERGELO = 1030,
1044 EVMERGELOHI = 1031,
1045 EVMHEGSMFAA = 1032,
1046 EVMHEGSMFAN = 1033,
1047 EVMHEGSMIAA = 1034,
1048 EVMHEGSMIAN = 1035,
1049 EVMHEGUMIAA = 1036,
1050 EVMHEGUMIAN = 1037,
1051 EVMHESMF = 1038,
1052 EVMHESMFA = 1039,
1053 EVMHESMFAAW = 1040,
1054 EVMHESMFANW = 1041,
1055 EVMHESMI = 1042,
1056 EVMHESMIA = 1043,
1057 EVMHESMIAAW = 1044,
1058 EVMHESMIANW = 1045,
1059 EVMHESSF = 1046,
1060 EVMHESSFA = 1047,
1061 EVMHESSFAAW = 1048,
1062 EVMHESSFANW = 1049,
1063 EVMHESSIAAW = 1050,
1064 EVMHESSIANW = 1051,
1065 EVMHEUMI = 1052,
1066 EVMHEUMIA = 1053,
1067 EVMHEUMIAAW = 1054,
1068 EVMHEUMIANW = 1055,
1069 EVMHEUSIAAW = 1056,
1070 EVMHEUSIANW = 1057,
1071 EVMHOGSMFAA = 1058,
1072 EVMHOGSMFAN = 1059,
1073 EVMHOGSMIAA = 1060,
1074 EVMHOGSMIAN = 1061,
1075 EVMHOGUMIAA = 1062,
1076 EVMHOGUMIAN = 1063,
1077 EVMHOSMF = 1064,
1078 EVMHOSMFA = 1065,
1079 EVMHOSMFAAW = 1066,
1080 EVMHOSMFANW = 1067,
1081 EVMHOSMI = 1068,
1082 EVMHOSMIA = 1069,
1083 EVMHOSMIAAW = 1070,
1084 EVMHOSMIANW = 1071,
1085 EVMHOSSF = 1072,
1086 EVMHOSSFA = 1073,
1087 EVMHOSSFAAW = 1074,
1088 EVMHOSSFANW = 1075,
1089 EVMHOSSIAAW = 1076,
1090 EVMHOSSIANW = 1077,
1091 EVMHOUMI = 1078,
1092 EVMHOUMIA = 1079,
1093 EVMHOUMIAAW = 1080,
1094 EVMHOUMIANW = 1081,
1095 EVMHOUSIAAW = 1082,
1096 EVMHOUSIANW = 1083,
1097 EVMRA = 1084,
1098 EVMWHSMF = 1085,
1099 EVMWHSMFA = 1086,
1100 EVMWHSMI = 1087,
1101 EVMWHSMIA = 1088,
1102 EVMWHSSF = 1089,
1103 EVMWHSSFA = 1090,
1104 EVMWHUMI = 1091,
1105 EVMWHUMIA = 1092,
1106 EVMWLSMIAAW = 1093,
1107 EVMWLSMIANW = 1094,
1108 EVMWLSSIAAW = 1095,
1109 EVMWLSSIANW = 1096,
1110 EVMWLUMI = 1097,
1111 EVMWLUMIA = 1098,
1112 EVMWLUMIAAW = 1099,
1113 EVMWLUMIANW = 1100,
1114 EVMWLUSIAAW = 1101,
1115 EVMWLUSIANW = 1102,
1116 EVMWSMF = 1103,
1117 EVMWSMFA = 1104,
1118 EVMWSMFAA = 1105,
1119 EVMWSMFAN = 1106,
1120 EVMWSMI = 1107,
1121 EVMWSMIA = 1108,
1122 EVMWSMIAA = 1109,
1123 EVMWSMIAN = 1110,
1124 EVMWSSF = 1111,
1125 EVMWSSFA = 1112,
1126 EVMWSSFAA = 1113,
1127 EVMWSSFAN = 1114,
1128 EVMWUMI = 1115,
1129 EVMWUMIA = 1116,
1130 EVMWUMIAA = 1117,
1131 EVMWUMIAN = 1118,
1132 EVNAND = 1119,
1133 EVNEG = 1120,
1134 EVNOR = 1121,
1135 EVOR = 1122,
1136 EVORC = 1123,
1137 EVRLW = 1124,
1138 EVRLWI = 1125,
1139 EVRNDW = 1126,
1140 EVSEL = 1127,
1141 EVSLW = 1128,
1142 EVSLWI = 1129,
1143 EVSPLATFI = 1130,
1144 EVSPLATI = 1131,
1145 EVSRWIS = 1132,
1146 EVSRWIU = 1133,
1147 EVSRWS = 1134,
1148 EVSRWU = 1135,
1149 EVSTDD = 1136,
1150 EVSTDDX = 1137,
1151 EVSTDH = 1138,
1152 EVSTDHX = 1139,
1153 EVSTDW = 1140,
1154 EVSTDWX = 1141,
1155 EVSTWHE = 1142,
1156 EVSTWHEX = 1143,
1157 EVSTWHO = 1144,
1158 EVSTWHOX = 1145,
1159 EVSTWWE = 1146,
1160 EVSTWWEX = 1147,
1161 EVSTWWO = 1148,
1162 EVSTWWOX = 1149,
1163 EVSUBFSMIAAW = 1150,
1164 EVSUBFSSIAAW = 1151,
1165 EVSUBFUMIAAW = 1152,
1166 EVSUBFUSIAAW = 1153,
1167 EVSUBFW = 1154,
1168 EVSUBIFW = 1155,
1169 EVXOR = 1156,
1170 EXTSB = 1157,
1171 EXTSB8 = 1158,
1172 EXTSB8_32_64 = 1159,
1173 EXTSB8_rec = 1160,
1174 EXTSB_rec = 1161,
1175 EXTSH = 1162,
1176 EXTSH8 = 1163,
1177 EXTSH8_32_64 = 1164,
1178 EXTSH8_rec = 1165,
1179 EXTSH_rec = 1166,
1180 EXTSW = 1167,
1181 EXTSWSLI = 1168,
1182 EXTSWSLI_32_64 = 1169,
1183 EXTSWSLI_32_64_rec = 1170,
1184 EXTSWSLI_rec = 1171,
1185 EXTSW_32 = 1172,
1186 EXTSW_32_64 = 1173,
1187 EXTSW_32_64_rec = 1174,
1188 EXTSW_rec = 1175,
1189 EnforceIEIO = 1176,
1190 FABSD = 1177,
1191 FABSD_rec = 1178,
1192 FABSS = 1179,
1193 FABSS_rec = 1180,
1194 FADD = 1181,
1195 FADDS = 1182,
1196 FADDS_rec = 1183,
1197 FADD_rec = 1184,
1198 FADDrtz = 1185,
1199 FCFID = 1186,
1200 FCFIDS = 1187,
1201 FCFIDS_rec = 1188,
1202 FCFIDU = 1189,
1203 FCFIDUS = 1190,
1204 FCFIDUS_rec = 1191,
1205 FCFIDU_rec = 1192,
1206 FCFID_rec = 1193,
1207 FCMPOD = 1194,
1208 FCMPOS = 1195,
1209 FCMPUD = 1196,
1210 FCMPUS = 1197,
1211 FCPSGND = 1198,
1212 FCPSGND_rec = 1199,
1213 FCPSGNS = 1200,
1214 FCPSGNS_rec = 1201,
1215 FCTID = 1202,
1216 FCTIDU = 1203,
1217 FCTIDUZ = 1204,
1218 FCTIDUZ_rec = 1205,
1219 FCTIDU_rec = 1206,
1220 FCTIDZ = 1207,
1221 FCTIDZ_rec = 1208,
1222 FCTID_rec = 1209,
1223 FCTIW = 1210,
1224 FCTIWU = 1211,
1225 FCTIWUZ = 1212,
1226 FCTIWUZ_rec = 1213,
1227 FCTIWU_rec = 1214,
1228 FCTIWZ = 1215,
1229 FCTIWZ_rec = 1216,
1230 FCTIW_rec = 1217,
1231 FDIV = 1218,
1232 FDIVS = 1219,
1233 FDIVS_rec = 1220,
1234 FDIV_rec = 1221,
1235 FENCE = 1222,
1236 FMADD = 1223,
1237 FMADDS = 1224,
1238 FMADDS_rec = 1225,
1239 FMADD_rec = 1226,
1240 FMR = 1227,
1241 FMR_rec = 1228,
1242 FMSUB = 1229,
1243 FMSUBS = 1230,
1244 FMSUBS_rec = 1231,
1245 FMSUB_rec = 1232,
1246 FMUL = 1233,
1247 FMULS = 1234,
1248 FMULS_rec = 1235,
1249 FMUL_rec = 1236,
1250 FNABSD = 1237,
1251 FNABSD_rec = 1238,
1252 FNABSS = 1239,
1253 FNABSS_rec = 1240,
1254 FNEGD = 1241,
1255 FNEGD_rec = 1242,
1256 FNEGS = 1243,
1257 FNEGS_rec = 1244,
1258 FNMADD = 1245,
1259 FNMADDS = 1246,
1260 FNMADDS_rec = 1247,
1261 FNMADD_rec = 1248,
1262 FNMSUB = 1249,
1263 FNMSUBS = 1250,
1264 FNMSUBS_rec = 1251,
1265 FNMSUB_rec = 1252,
1266 FRE = 1253,
1267 FRES = 1254,
1268 FRES_rec = 1255,
1269 FRE_rec = 1256,
1270 FRIMD = 1257,
1271 FRIMD_rec = 1258,
1272 FRIMS = 1259,
1273 FRIMS_rec = 1260,
1274 FRIND = 1261,
1275 FRIND_rec = 1262,
1276 FRINS = 1263,
1277 FRINS_rec = 1264,
1278 FRIPD = 1265,
1279 FRIPD_rec = 1266,
1280 FRIPS = 1267,
1281 FRIPS_rec = 1268,
1282 FRIZD = 1269,
1283 FRIZD_rec = 1270,
1284 FRIZS = 1271,
1285 FRIZS_rec = 1272,
1286 FRSP = 1273,
1287 FRSP_rec = 1274,
1288 FRSQRTE = 1275,
1289 FRSQRTES = 1276,
1290 FRSQRTES_rec = 1277,
1291 FRSQRTE_rec = 1278,
1292 FSELD = 1279,
1293 FSELD_rec = 1280,
1294 FSELS = 1281,
1295 FSELS_rec = 1282,
1296 FSQRT = 1283,
1297 FSQRTS = 1284,
1298 FSQRTS_rec = 1285,
1299 FSQRT_rec = 1286,
1300 FSUB = 1287,
1301 FSUBS = 1288,
1302 FSUBS_rec = 1289,
1303 FSUB_rec = 1290,
1304 FTDIV = 1291,
1305 FTSQRT = 1292,
1306 GETtlsADDR = 1293,
1307 GETtlsADDR32 = 1294,
1308 GETtlsADDR32AIX = 1295,
1309 GETtlsADDR64AIX = 1296,
1310 GETtlsADDRPCREL = 1297,
1311 GETtlsMOD32AIX = 1298,
1312 GETtlsMOD64AIX = 1299,
1313 GETtlsTpointer32AIX = 1300,
1314 GETtlsldADDR = 1301,
1315 GETtlsldADDR32 = 1302,
1316 GETtlsldADDRPCREL = 1303,
1317 HASHCHK = 1304,
1318 HASHCHK8 = 1305,
1319 HASHCHKP = 1306,
1320 HASHCHKP8 = 1307,
1321 HASHST = 1308,
1322 HASHST8 = 1309,
1323 HASHSTP = 1310,
1324 HASHSTP8 = 1311,
1325 HRFID = 1312,
1326 ICBI = 1313,
1327 ICBIEP = 1314,
1328 ICBLC = 1315,
1329 ICBLQ = 1316,
1330 ICBT = 1317,
1331 ICBTLS = 1318,
1332 ICCCI = 1319,
1333 ISEL = 1320,
1334 ISEL8 = 1321,
1335 ISYNC = 1322,
1336 LA = 1323,
1337 LA8 = 1324,
1338 LBARX = 1325,
1339 LBARXL = 1326,
1340 LBEPX = 1327,
1341 LBZ = 1328,
1342 LBZ8 = 1329,
1343 LBZCIX = 1330,
1344 LBZU = 1331,
1345 LBZU8 = 1332,
1346 LBZUX = 1333,
1347 LBZUX8 = 1334,
1348 LBZX = 1335,
1349 LBZX8 = 1336,
1350 LBZXTLS = 1337,
1351 LBZXTLS_ = 1338,
1352 LBZXTLS_32 = 1339,
1353 LD = 1340,
1354 LDARX = 1341,
1355 LDARXL = 1342,
1356 LDAT = 1343,
1357 LDBRX = 1344,
1358 LDCIX = 1345,
1359 LDU = 1346,
1360 LDUX = 1347,
1361 LDX = 1348,
1362 LDXTLS = 1349,
1363 LDXTLS_ = 1350,
1364 LDgotTprelL = 1351,
1365 LDgotTprelL32 = 1352,
1366 LDtoc = 1353,
1367 LDtocBA = 1354,
1368 LDtocCPT = 1355,
1369 LDtocJTI = 1356,
1370 LDtocL = 1357,
1371 LFD = 1358,
1372 LFDEPX = 1359,
1373 LFDU = 1360,
1374 LFDUX = 1361,
1375 LFDX = 1362,
1376 LFDXTLS = 1363,
1377 LFDXTLS_ = 1364,
1378 LFIWAX = 1365,
1379 LFIWZX = 1366,
1380 LFS = 1367,
1381 LFSU = 1368,
1382 LFSUX = 1369,
1383 LFSX = 1370,
1384 LFSXTLS = 1371,
1385 LFSXTLS_ = 1372,
1386 LHA = 1373,
1387 LHA8 = 1374,
1388 LHARX = 1375,
1389 LHARXL = 1376,
1390 LHAU = 1377,
1391 LHAU8 = 1378,
1392 LHAUX = 1379,
1393 LHAUX8 = 1380,
1394 LHAX = 1381,
1395 LHAX8 = 1382,
1396 LHAXTLS = 1383,
1397 LHAXTLS_ = 1384,
1398 LHAXTLS_32 = 1385,
1399 LHBRX = 1386,
1400 LHBRX8 = 1387,
1401 LHEPX = 1388,
1402 LHZ = 1389,
1403 LHZ8 = 1390,
1404 LHZCIX = 1391,
1405 LHZU = 1392,
1406 LHZU8 = 1393,
1407 LHZUX = 1394,
1408 LHZUX8 = 1395,
1409 LHZX = 1396,
1410 LHZX8 = 1397,
1411 LHZXTLS = 1398,
1412 LHZXTLS_ = 1399,
1413 LHZXTLS_32 = 1400,
1414 LI = 1401,
1415 LI8 = 1402,
1416 LIS = 1403,
1417 LIS8 = 1404,
1418 LMW = 1405,
1419 LQ = 1406,
1420 LQARX = 1407,
1421 LQARXL = 1408,
1422 LQX_PSEUDO = 1409,
1423 LSWI = 1410,
1424 LVEBX = 1411,
1425 LVEHX = 1412,
1426 LVEWX = 1413,
1427 LVSL = 1414,
1428 LVSR = 1415,
1429 LVX = 1416,
1430 LVXL = 1417,
1431 LWA = 1418,
1432 LWARX = 1419,
1433 LWARXL = 1420,
1434 LWAT = 1421,
1435 LWAUX = 1422,
1436 LWAX = 1423,
1437 LWAXTLS = 1424,
1438 LWAXTLS_ = 1425,
1439 LWAXTLS_32 = 1426,
1440 LWAX_32 = 1427,
1441 LWA_32 = 1428,
1442 LWBRX = 1429,
1443 LWBRX8 = 1430,
1444 LWEPX = 1431,
1445 LWZ = 1432,
1446 LWZ8 = 1433,
1447 LWZCIX = 1434,
1448 LWZU = 1435,
1449 LWZU8 = 1436,
1450 LWZUX = 1437,
1451 LWZUX8 = 1438,
1452 LWZX = 1439,
1453 LWZX8 = 1440,
1454 LWZXTLS = 1441,
1455 LWZXTLS_ = 1442,
1456 LWZXTLS_32 = 1443,
1457 LWZtoc = 1444,
1458 LWZtocL = 1445,
1459 LXSD = 1446,
1460 LXSDX = 1447,
1461 LXSIBZX = 1448,
1462 LXSIHZX = 1449,
1463 LXSIWAX = 1450,
1464 LXSIWZX = 1451,
1465 LXSSP = 1452,
1466 LXSSPX = 1453,
1467 LXV = 1454,
1468 LXVB16X = 1455,
1469 LXVD2X = 1456,
1470 LXVDSX = 1457,
1471 LXVH8X = 1458,
1472 LXVKQ = 1459,
1473 LXVL = 1460,
1474 LXVLL = 1461,
1475 LXVP = 1462,
1476 LXVPRL = 1463,
1477 LXVPRLL = 1464,
1478 LXVPX = 1465,
1479 LXVRBX = 1466,
1480 LXVRDX = 1467,
1481 LXVRHX = 1468,
1482 LXVRL = 1469,
1483 LXVRLL = 1470,
1484 LXVRWX = 1471,
1485 LXVW4X = 1472,
1486 LXVWSX = 1473,
1487 LXVX = 1474,
1488 MADDHD = 1475,
1489 MADDHDU = 1476,
1490 MADDLD = 1477,
1491 MADDLD8 = 1478,
1492 MBAR = 1479,
1493 MCRF = 1480,
1494 MCRFS = 1481,
1495 MCRXRX = 1482,
1496 MFBHRBE = 1483,
1497 MFCR = 1484,
1498 MFCR8 = 1485,
1499 MFCTR = 1486,
1500 MFCTR8 = 1487,
1501 MFDCR = 1488,
1502 MFFS = 1489,
1503 MFFSCDRN = 1490,
1504 MFFSCDRNI = 1491,
1505 MFFSCE = 1492,
1506 MFFSCRN = 1493,
1507 MFFSCRNI = 1494,
1508 MFFSL = 1495,
1509 MFFS_rec = 1496,
1510 MFLR = 1497,
1511 MFLR8 = 1498,
1512 MFMSR = 1499,
1513 MFOCRF = 1500,
1514 MFOCRF8 = 1501,
1515 MFPMR = 1502,
1516 MFSPR = 1503,
1517 MFSPR8 = 1504,
1518 MFSR = 1505,
1519 MFSRIN = 1506,
1520 MFTB = 1507,
1521 MFTB8 = 1508,
1522 MFUDSCR = 1509,
1523 MFVRD = 1510,
1524 MFVRSAVE = 1511,
1525 MFVRSAVEv = 1512,
1526 MFVRWZ = 1513,
1527 MFVSCR = 1514,
1528 MFVSRD = 1515,
1529 MFVSRLD = 1516,
1530 MFVSRWZ = 1517,
1531 MODSD = 1518,
1532 MODSW = 1519,
1533 MODUD = 1520,
1534 MODUW = 1521,
1535 MSGSYNC = 1522,
1536 MSYNC = 1523,
1537 MTCRF = 1524,
1538 MTCRF8 = 1525,
1539 MTCTR = 1526,
1540 MTCTR8 = 1527,
1541 MTCTR8loop = 1528,
1542 MTCTRloop = 1529,
1543 MTDCR = 1530,
1544 MTFSB0 = 1531,
1545 MTFSB1 = 1532,
1546 MTFSF = 1533,
1547 MTFSFI = 1534,
1548 MTFSFI_rec = 1535,
1549 MTFSFIb = 1536,
1550 MTFSF_rec = 1537,
1551 MTFSFb = 1538,
1552 MTLR = 1539,
1553 MTLR8 = 1540,
1554 MTMSR = 1541,
1555 MTMSRD = 1542,
1556 MTOCRF = 1543,
1557 MTOCRF8 = 1544,
1558 MTPMR = 1545,
1559 MTSPR = 1546,
1560 MTSPR8 = 1547,
1561 MTSR = 1548,
1562 MTSRIN = 1549,
1563 MTUDSCR = 1550,
1564 MTVRD = 1551,
1565 MTVRSAVE = 1552,
1566 MTVRSAVEv = 1553,
1567 MTVRWA = 1554,
1568 MTVRWZ = 1555,
1569 MTVSCR = 1556,
1570 MTVSRBM = 1557,
1571 MTVSRBMI = 1558,
1572 MTVSRD = 1559,
1573 MTVSRDD = 1560,
1574 MTVSRDM = 1561,
1575 MTVSRHM = 1562,
1576 MTVSRQM = 1563,
1577 MTVSRWA = 1564,
1578 MTVSRWM = 1565,
1579 MTVSRWS = 1566,
1580 MTVSRWZ = 1567,
1581 MULHD = 1568,
1582 MULHDU = 1569,
1583 MULHDU_rec = 1570,
1584 MULHD_rec = 1571,
1585 MULHW = 1572,
1586 MULHWU = 1573,
1587 MULHWU_rec = 1574,
1588 MULHW_rec = 1575,
1589 MULLD = 1576,
1590 MULLDO = 1577,
1591 MULLDO_rec = 1578,
1592 MULLD_rec = 1579,
1593 MULLI = 1580,
1594 MULLI8 = 1581,
1595 MULLW = 1582,
1596 MULLWO = 1583,
1597 MULLWO_rec = 1584,
1598 MULLW_rec = 1585,
1599 MoveGOTtoLR = 1586,
1600 MovePCtoLR = 1587,
1601 MovePCtoLR8 = 1588,
1602 NAND = 1589,
1603 NAND8 = 1590,
1604 NAND8_rec = 1591,
1605 NAND_rec = 1592,
1606 NAP = 1593,
1607 NEG = 1594,
1608 NEG8 = 1595,
1609 NEG8O = 1596,
1610 NEG8O_rec = 1597,
1611 NEG8_rec = 1598,
1612 NEGO = 1599,
1613 NEGO_rec = 1600,
1614 NEG_rec = 1601,
1615 NOP = 1602,
1616 NOP_GT_PWR6 = 1603,
1617 NOP_GT_PWR7 = 1604,
1618 NOR = 1605,
1619 NOR8 = 1606,
1620 NOR8_rec = 1607,
1621 NOR_rec = 1608,
1622 OR = 1609,
1623 OR8 = 1610,
1624 OR8_rec = 1611,
1625 ORC = 1612,
1626 ORC8 = 1613,
1627 ORC8_rec = 1614,
1628 ORC_rec = 1615,
1629 ORI = 1616,
1630 ORI8 = 1617,
1631 ORIS = 1618,
1632 ORIS8 = 1619,
1633 OR_rec = 1620,
1634 PADDI = 1621,
1635 PADDI8 = 1622,
1636 PADDI8pc = 1623,
1637 PADDIdtprel = 1624,
1638 PADDIpc = 1625,
1639 PDEPD = 1626,
1640 PEXTD = 1627,
1641 PLA = 1628,
1642 PLA8 = 1629,
1643 PLA8pc = 1630,
1644 PLApc = 1631,
1645 PLBZ = 1632,
1646 PLBZ8 = 1633,
1647 PLBZ8nopc = 1634,
1648 PLBZ8onlypc = 1635,
1649 PLBZ8pc = 1636,
1650 PLBZnopc = 1637,
1651 PLBZonlypc = 1638,
1652 PLBZpc = 1639,
1653 PLD = 1640,
1654 PLDnopc = 1641,
1655 PLDonlypc = 1642,
1656 PLDpc = 1643,
1657 PLFD = 1644,
1658 PLFDnopc = 1645,
1659 PLFDonlypc = 1646,
1660 PLFDpc = 1647,
1661 PLFS = 1648,
1662 PLFSnopc = 1649,
1663 PLFSonlypc = 1650,
1664 PLFSpc = 1651,
1665 PLHA = 1652,
1666 PLHA8 = 1653,
1667 PLHA8nopc = 1654,
1668 PLHA8onlypc = 1655,
1669 PLHA8pc = 1656,
1670 PLHAnopc = 1657,
1671 PLHAonlypc = 1658,
1672 PLHApc = 1659,
1673 PLHZ = 1660,
1674 PLHZ8 = 1661,
1675 PLHZ8nopc = 1662,
1676 PLHZ8onlypc = 1663,
1677 PLHZ8pc = 1664,
1678 PLHZnopc = 1665,
1679 PLHZonlypc = 1666,
1680 PLHZpc = 1667,
1681 PLI = 1668,
1682 PLI8 = 1669,
1683 PLWA = 1670,
1684 PLWA8 = 1671,
1685 PLWA8nopc = 1672,
1686 PLWA8onlypc = 1673,
1687 PLWA8pc = 1674,
1688 PLWAnopc = 1675,
1689 PLWAonlypc = 1676,
1690 PLWApc = 1677,
1691 PLWZ = 1678,
1692 PLWZ8 = 1679,
1693 PLWZ8nopc = 1680,
1694 PLWZ8onlypc = 1681,
1695 PLWZ8pc = 1682,
1696 PLWZnopc = 1683,
1697 PLWZonlypc = 1684,
1698 PLWZpc = 1685,
1699 PLXSD = 1686,
1700 PLXSDnopc = 1687,
1701 PLXSDonlypc = 1688,
1702 PLXSDpc = 1689,
1703 PLXSSP = 1690,
1704 PLXSSPnopc = 1691,
1705 PLXSSPonlypc = 1692,
1706 PLXSSPpc = 1693,
1707 PLXV = 1694,
1708 PLXVP = 1695,
1709 PLXVPnopc = 1696,
1710 PLXVPonlypc = 1697,
1711 PLXVPpc = 1698,
1712 PLXVnopc = 1699,
1713 PLXVonlypc = 1700,
1714 PLXVpc = 1701,
1715 PMDMXVBF16GERX2 = 1702,
1716 PMDMXVBF16GERX2NN = 1703,
1717 PMDMXVBF16GERX2NP = 1704,
1718 PMDMXVBF16GERX2PN = 1705,
1719 PMDMXVBF16GERX2PP = 1706,
1720 PMDMXVF16GERX2 = 1707,
1721 PMDMXVF16GERX2NN = 1708,
1722 PMDMXVF16GERX2NP = 1709,
1723 PMDMXVF16GERX2PN = 1710,
1724 PMDMXVF16GERX2PP = 1711,
1725 PMDMXVI8GERX4 = 1712,
1726 PMDMXVI8GERX4PP = 1713,
1727 PMDMXVI8GERX4SPP = 1714,
1728 PMXVBF16GER2 = 1715,
1729 PMXVBF16GER2NN = 1716,
1730 PMXVBF16GER2NP = 1717,
1731 PMXVBF16GER2PN = 1718,
1732 PMXVBF16GER2PP = 1719,
1733 PMXVBF16GER2W = 1720,
1734 PMXVBF16GER2WNN = 1721,
1735 PMXVBF16GER2WNP = 1722,
1736 PMXVBF16GER2WPN = 1723,
1737 PMXVBF16GER2WPP = 1724,
1738 PMXVF16GER2 = 1725,
1739 PMXVF16GER2NN = 1726,
1740 PMXVF16GER2NP = 1727,
1741 PMXVF16GER2PN = 1728,
1742 PMXVF16GER2PP = 1729,
1743 PMXVF16GER2W = 1730,
1744 PMXVF16GER2WNN = 1731,
1745 PMXVF16GER2WNP = 1732,
1746 PMXVF16GER2WPN = 1733,
1747 PMXVF16GER2WPP = 1734,
1748 PMXVF32GER = 1735,
1749 PMXVF32GERNN = 1736,
1750 PMXVF32GERNP = 1737,
1751 PMXVF32GERPN = 1738,
1752 PMXVF32GERPP = 1739,
1753 PMXVF32GERW = 1740,
1754 PMXVF32GERWNN = 1741,
1755 PMXVF32GERWNP = 1742,
1756 PMXVF32GERWPN = 1743,
1757 PMXVF32GERWPP = 1744,
1758 PMXVF64GER = 1745,
1759 PMXVF64GERNN = 1746,
1760 PMXVF64GERNP = 1747,
1761 PMXVF64GERPN = 1748,
1762 PMXVF64GERPP = 1749,
1763 PMXVF64GERW = 1750,
1764 PMXVF64GERWNN = 1751,
1765 PMXVF64GERWNP = 1752,
1766 PMXVF64GERWPN = 1753,
1767 PMXVF64GERWPP = 1754,
1768 PMXVI16GER2 = 1755,
1769 PMXVI16GER2PP = 1756,
1770 PMXVI16GER2S = 1757,
1771 PMXVI16GER2SPP = 1758,
1772 PMXVI16GER2SW = 1759,
1773 PMXVI16GER2SWPP = 1760,
1774 PMXVI16GER2W = 1761,
1775 PMXVI16GER2WPP = 1762,
1776 PMXVI4GER8 = 1763,
1777 PMXVI4GER8PP = 1764,
1778 PMXVI4GER8W = 1765,
1779 PMXVI4GER8WPP = 1766,
1780 PMXVI8GER4 = 1767,
1781 PMXVI8GER4PP = 1768,
1782 PMXVI8GER4SPP = 1769,
1783 PMXVI8GER4W = 1770,
1784 PMXVI8GER4WPP = 1771,
1785 PMXVI8GER4WSPP = 1772,
1786 POPCNTB = 1773,
1787 POPCNTB8 = 1774,
1788 POPCNTD = 1775,
1789 POPCNTW = 1776,
1790 PPC32GOT = 1777,
1791 PPC32PICGOT = 1778,
1792 PREPARE_PROBED_ALLOCA_32 = 1779,
1793 PREPARE_PROBED_ALLOCA_64 = 1780,
1794 PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 = 1781,
1795 PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 = 1782,
1796 PROBED_ALLOCA_32 = 1783,
1797 PROBED_ALLOCA_64 = 1784,
1798 PROBED_STACKALLOC_32 = 1785,
1799 PROBED_STACKALLOC_64 = 1786,
1800 PSTB = 1787,
1801 PSTB8 = 1788,
1802 PSTB8nopc = 1789,
1803 PSTB8onlypc = 1790,
1804 PSTB8pc = 1791,
1805 PSTBnopc = 1792,
1806 PSTBonlypc = 1793,
1807 PSTBpc = 1794,
1808 PSTD = 1795,
1809 PSTDnopc = 1796,
1810 PSTDonlypc = 1797,
1811 PSTDpc = 1798,
1812 PSTFD = 1799,
1813 PSTFDnopc = 1800,
1814 PSTFDonlypc = 1801,
1815 PSTFDpc = 1802,
1816 PSTFS = 1803,
1817 PSTFSnopc = 1804,
1818 PSTFSonlypc = 1805,
1819 PSTFSpc = 1806,
1820 PSTH = 1807,
1821 PSTH8 = 1808,
1822 PSTH8nopc = 1809,
1823 PSTH8onlypc = 1810,
1824 PSTH8pc = 1811,
1825 PSTHnopc = 1812,
1826 PSTHonlypc = 1813,
1827 PSTHpc = 1814,
1828 PSTW = 1815,
1829 PSTW8 = 1816,
1830 PSTW8nopc = 1817,
1831 PSTW8onlypc = 1818,
1832 PSTW8pc = 1819,
1833 PSTWnopc = 1820,
1834 PSTWonlypc = 1821,
1835 PSTWpc = 1822,
1836 PSTXSD = 1823,
1837 PSTXSDnopc = 1824,
1838 PSTXSDonlypc = 1825,
1839 PSTXSDpc = 1826,
1840 PSTXSSP = 1827,
1841 PSTXSSPnopc = 1828,
1842 PSTXSSPonlypc = 1829,
1843 PSTXSSPpc = 1830,
1844 PSTXV = 1831,
1845 PSTXVP = 1832,
1846 PSTXVPnopc = 1833,
1847 PSTXVPonlypc = 1834,
1848 PSTXVPpc = 1835,
1849 PSTXVnopc = 1836,
1850 PSTXVonlypc = 1837,
1851 PSTXVpc = 1838,
1852 PseudoEIEIO = 1839,
1853 RESTORE_ACC = 1840,
1854 RESTORE_CR = 1841,
1855 RESTORE_CRBIT = 1842,
1856 RESTORE_DMR = 1843,
1857 RESTORE_DMRP = 1844,
1858 RESTORE_QUADWORD = 1845,
1859 RESTORE_UACC = 1846,
1860 RESTORE_WACC = 1847,
1861 RFCI = 1848,
1862 RFDI = 1849,
1863 RFEBB = 1850,
1864 RFI = 1851,
1865 RFID = 1852,
1866 RFMCI = 1853,
1867 RLDCL = 1854,
1868 RLDCL_rec = 1855,
1869 RLDCR = 1856,
1870 RLDCR_rec = 1857,
1871 RLDIC = 1858,
1872 RLDICL = 1859,
1873 RLDICL_32 = 1860,
1874 RLDICL_32_64 = 1861,
1875 RLDICL_32_rec = 1862,
1876 RLDICL_rec = 1863,
1877 RLDICR = 1864,
1878 RLDICR_32 = 1865,
1879 RLDICR_rec = 1866,
1880 RLDIC_rec = 1867,
1881 RLDIMI = 1868,
1882 RLDIMI_rec = 1869,
1883 RLWIMI = 1870,
1884 RLWIMI8 = 1871,
1885 RLWIMI8_rec = 1872,
1886 RLWIMI_rec = 1873,
1887 RLWINM = 1874,
1888 RLWINM8 = 1875,
1889 RLWINM8_rec = 1876,
1890 RLWINM_rec = 1877,
1891 RLWNM = 1878,
1892 RLWNM8 = 1879,
1893 RLWNM8_rec = 1880,
1894 RLWNM_rec = 1881,
1895 ReadTB = 1882,
1896 SC = 1883,
1897 SCV = 1884,
1898 SELECT_CC_F16 = 1885,
1899 SELECT_CC_F4 = 1886,
1900 SELECT_CC_F8 = 1887,
1901 SELECT_CC_I4 = 1888,
1902 SELECT_CC_I8 = 1889,
1903 SELECT_CC_SPE = 1890,
1904 SELECT_CC_SPE4 = 1891,
1905 SELECT_CC_VRRC = 1892,
1906 SELECT_CC_VSFRC = 1893,
1907 SELECT_CC_VSRC = 1894,
1908 SELECT_CC_VSSRC = 1895,
1909 SELECT_F16 = 1896,
1910 SELECT_F4 = 1897,
1911 SELECT_F8 = 1898,
1912 SELECT_I4 = 1899,
1913 SELECT_I8 = 1900,
1914 SELECT_SPE = 1901,
1915 SELECT_SPE4 = 1902,
1916 SELECT_VRRC = 1903,
1917 SELECT_VSFRC = 1904,
1918 SELECT_VSRC = 1905,
1919 SELECT_VSSRC = 1906,
1920 SETB = 1907,
1921 SETB8 = 1908,
1922 SETBC = 1909,
1923 SETBC8 = 1910,
1924 SETBCR = 1911,
1925 SETBCR8 = 1912,
1926 SETFLM = 1913,
1927 SETNBC = 1914,
1928 SETNBC8 = 1915,
1929 SETNBCR = 1916,
1930 SETNBCR8 = 1917,
1931 SETRND = 1918,
1932 SETRNDi = 1919,
1933 SLBFEE_rec = 1920,
1934 SLBIA = 1921,
1935 SLBIE = 1922,
1936 SLBIEG = 1923,
1937 SLBMFEE = 1924,
1938 SLBMFEV = 1925,
1939 SLBMTE = 1926,
1940 SLBSYNC = 1927,
1941 SLD = 1928,
1942 SLD_rec = 1929,
1943 SLW = 1930,
1944 SLW8 = 1931,
1945 SLW8_rec = 1932,
1946 SLW_rec = 1933,
1947 SPELWZ = 1934,
1948 SPELWZX = 1935,
1949 SPESTW = 1936,
1950 SPESTWX = 1937,
1951 SPILL_ACC = 1938,
1952 SPILL_CR = 1939,
1953 SPILL_CRBIT = 1940,
1954 SPILL_DMR = 1941,
1955 SPILL_DMRP = 1942,
1956 SPILL_QUADWORD = 1943,
1957 SPILL_UACC = 1944,
1958 SPILL_WACC = 1945,
1959 SPLIT_QUADWORD = 1946,
1960 SRAD = 1947,
1961 SRADI = 1948,
1962 SRADI_32 = 1949,
1963 SRADI_rec = 1950,
1964 SRAD_rec = 1951,
1965 SRAW = 1952,
1966 SRAW8 = 1953,
1967 SRAW8_rec = 1954,
1968 SRAWI = 1955,
1969 SRAWI8 = 1956,
1970 SRAWI8_rec = 1957,
1971 SRAWI_rec = 1958,
1972 SRAW_rec = 1959,
1973 SRD = 1960,
1974 SRD_rec = 1961,
1975 SRW = 1962,
1976 SRW8 = 1963,
1977 SRW8_rec = 1964,
1978 SRW_rec = 1965,
1979 STB = 1966,
1980 STB8 = 1967,
1981 STBCIX = 1968,
1982 STBCX = 1969,
1983 STBEPX = 1970,
1984 STBU = 1971,
1985 STBU8 = 1972,
1986 STBUX = 1973,
1987 STBUX8 = 1974,
1988 STBX = 1975,
1989 STBX8 = 1976,
1990 STBXTLS = 1977,
1991 STBXTLS_ = 1978,
1992 STBXTLS_32 = 1979,
1993 STD = 1980,
1994 STDAT = 1981,
1995 STDBRX = 1982,
1996 STDCIX = 1983,
1997 STDCX = 1984,
1998 STDU = 1985,
1999 STDUX = 1986,
2000 STDX = 1987,
2001 STDXTLS = 1988,
2002 STDXTLS_ = 1989,
2003 STFD = 1990,
2004 STFDEPX = 1991,
2005 STFDU = 1992,
2006 STFDUX = 1993,
2007 STFDX = 1994,
2008 STFDXTLS = 1995,
2009 STFDXTLS_ = 1996,
2010 STFIWX = 1997,
2011 STFS = 1998,
2012 STFSU = 1999,
2013 STFSUX = 2000,
2014 STFSX = 2001,
2015 STFSXTLS = 2002,
2016 STFSXTLS_ = 2003,
2017 STH = 2004,
2018 STH8 = 2005,
2019 STHBRX = 2006,
2020 STHCIX = 2007,
2021 STHCX = 2008,
2022 STHEPX = 2009,
2023 STHU = 2010,
2024 STHU8 = 2011,
2025 STHUX = 2012,
2026 STHUX8 = 2013,
2027 STHX = 2014,
2028 STHX8 = 2015,
2029 STHXTLS = 2016,
2030 STHXTLS_ = 2017,
2031 STHXTLS_32 = 2018,
2032 STMW = 2019,
2033 STOP = 2020,
2034 STQ = 2021,
2035 STQCX = 2022,
2036 STQX_PSEUDO = 2023,
2037 STSWI = 2024,
2038 STVEBX = 2025,
2039 STVEHX = 2026,
2040 STVEWX = 2027,
2041 STVX = 2028,
2042 STVXL = 2029,
2043 STW = 2030,
2044 STW8 = 2031,
2045 STWAT = 2032,
2046 STWBRX = 2033,
2047 STWCIX = 2034,
2048 STWCX = 2035,
2049 STWEPX = 2036,
2050 STWU = 2037,
2051 STWU8 = 2038,
2052 STWUX = 2039,
2053 STWUX8 = 2040,
2054 STWX = 2041,
2055 STWX8 = 2042,
2056 STWXTLS = 2043,
2057 STWXTLS_ = 2044,
2058 STWXTLS_32 = 2045,
2059 STXSD = 2046,
2060 STXSDX = 2047,
2061 STXSIBX = 2048,
2062 STXSIBXv = 2049,
2063 STXSIHX = 2050,
2064 STXSIHXv = 2051,
2065 STXSIWX = 2052,
2066 STXSSP = 2053,
2067 STXSSPX = 2054,
2068 STXV = 2055,
2069 STXVB16X = 2056,
2070 STXVD2X = 2057,
2071 STXVH8X = 2058,
2072 STXVL = 2059,
2073 STXVLL = 2060,
2074 STXVP = 2061,
2075 STXVPRL = 2062,
2076 STXVPRLL = 2063,
2077 STXVPX = 2064,
2078 STXVRBX = 2065,
2079 STXVRDX = 2066,
2080 STXVRHX = 2067,
2081 STXVRL = 2068,
2082 STXVRLL = 2069,
2083 STXVRWX = 2070,
2084 STXVW4X = 2071,
2085 STXVX = 2072,
2086 SUBF = 2073,
2087 SUBF8 = 2074,
2088 SUBF8O = 2075,
2089 SUBF8O_rec = 2076,
2090 SUBF8_rec = 2077,
2091 SUBFC = 2078,
2092 SUBFC8 = 2079,
2093 SUBFC8O = 2080,
2094 SUBFC8O_rec = 2081,
2095 SUBFC8_rec = 2082,
2096 SUBFCO = 2083,
2097 SUBFCO_rec = 2084,
2098 SUBFC_rec = 2085,
2099 SUBFE = 2086,
2100 SUBFE8 = 2087,
2101 SUBFE8O = 2088,
2102 SUBFE8O_rec = 2089,
2103 SUBFE8_rec = 2090,
2104 SUBFEO = 2091,
2105 SUBFEO_rec = 2092,
2106 SUBFE_rec = 2093,
2107 SUBFIC = 2094,
2108 SUBFIC8 = 2095,
2109 SUBFME = 2096,
2110 SUBFME8 = 2097,
2111 SUBFME8O = 2098,
2112 SUBFME8O_rec = 2099,
2113 SUBFME8_rec = 2100,
2114 SUBFMEO = 2101,
2115 SUBFMEO_rec = 2102,
2116 SUBFME_rec = 2103,
2117 SUBFO = 2104,
2118 SUBFO_rec = 2105,
2119 SUBFUS = 2106,
2120 SUBFUS_rec = 2107,
2121 SUBFZE = 2108,
2122 SUBFZE8 = 2109,
2123 SUBFZE8O = 2110,
2124 SUBFZE8O_rec = 2111,
2125 SUBFZE8_rec = 2112,
2126 SUBFZEO = 2113,
2127 SUBFZEO_rec = 2114,
2128 SUBFZE_rec = 2115,
2129 SUBF_rec = 2116,
2130 SYNC = 2117,
2131 SYNCP10 = 2118,
2132 TABORT = 2119,
2133 TABORTDC = 2120,
2134 TABORTDCI = 2121,
2135 TABORTWC = 2122,
2136 TABORTWCI = 2123,
2137 TAILB = 2124,
2138 TAILB8 = 2125,
2139 TAILBA = 2126,
2140 TAILBA8 = 2127,
2141 TAILBCTR = 2128,
2142 TAILBCTR8 = 2129,
2143 TBEGIN = 2130,
2144 TBEGIN_RET = 2131,
2145 TCHECK = 2132,
2146 TCHECK_RET = 2133,
2147 TCRETURNai = 2134,
2148 TCRETURNai8 = 2135,
2149 TCRETURNdi = 2136,
2150 TCRETURNdi8 = 2137,
2151 TCRETURNri = 2138,
2152 TCRETURNri8 = 2139,
2153 TD = 2140,
2154 TDI = 2141,
2155 TEND = 2142,
2156 TLBIA = 2143,
2157 TLBIE = 2144,
2158 TLBIEL = 2145,
2159 TLBILX = 2146,
2160 TLBIVAX = 2147,
2161 TLBLD = 2148,
2162 TLBLI = 2149,
2163 TLBRE = 2150,
2164 TLBRE2 = 2151,
2165 TLBSX = 2152,
2166 TLBSX2 = 2153,
2167 TLBSX2D = 2154,
2168 TLBSYNC = 2155,
2169 TLBWE = 2156,
2170 TLBWE2 = 2157,
2171 TLSGDAIX = 2158,
2172 TLSGDAIX8 = 2159,
2173 TLSLDAIX = 2160,
2174 TLSLDAIX8 = 2161,
2175 TRAP = 2162,
2176 TRECHKPT = 2163,
2177 TRECLAIM = 2164,
2178 TSR = 2165,
2179 TW = 2166,
2180 TWI = 2167,
2181 UNENCODED_NOP = 2168,
2182 UpdateGBR = 2169,
2183 VABSDUB = 2170,
2184 VABSDUH = 2171,
2185 VABSDUW = 2172,
2186 VADDCUQ = 2173,
2187 VADDCUW = 2174,
2188 VADDECUQ = 2175,
2189 VADDEUQM = 2176,
2190 VADDFP = 2177,
2191 VADDSBS = 2178,
2192 VADDSHS = 2179,
2193 VADDSWS = 2180,
2194 VADDUBM = 2181,
2195 VADDUBS = 2182,
2196 VADDUDM = 2183,
2197 VADDUHM = 2184,
2198 VADDUHS = 2185,
2199 VADDUQM = 2186,
2200 VADDUWM = 2187,
2201 VADDUWS = 2188,
2202 VAND = 2189,
2203 VANDC = 2190,
2204 VAVGSB = 2191,
2205 VAVGSH = 2192,
2206 VAVGSW = 2193,
2207 VAVGUB = 2194,
2208 VAVGUH = 2195,
2209 VAVGUW = 2196,
2210 VBPERMD = 2197,
2211 VBPERMQ = 2198,
2212 VCFSX = 2199,
2213 VCFSX_0 = 2200,
2214 VCFUGED = 2201,
2215 VCFUX = 2202,
2216 VCFUX_0 = 2203,
2217 VCIPHER = 2204,
2218 VCIPHERLAST = 2205,
2219 VCLRLB = 2206,
2220 VCLRRB = 2207,
2221 VCLZB = 2208,
2222 VCLZD = 2209,
2223 VCLZDM = 2210,
2224 VCLZH = 2211,
2225 VCLZLSBB = 2212,
2226 VCLZW = 2213,
2227 VCMPBFP = 2214,
2228 VCMPBFP_rec = 2215,
2229 VCMPEQFP = 2216,
2230 VCMPEQFP_rec = 2217,
2231 VCMPEQUB = 2218,
2232 VCMPEQUB_rec = 2219,
2233 VCMPEQUD = 2220,
2234 VCMPEQUD_rec = 2221,
2235 VCMPEQUH = 2222,
2236 VCMPEQUH_rec = 2223,
2237 VCMPEQUQ = 2224,
2238 VCMPEQUQ_rec = 2225,
2239 VCMPEQUW = 2226,
2240 VCMPEQUW_rec = 2227,
2241 VCMPGEFP = 2228,
2242 VCMPGEFP_rec = 2229,
2243 VCMPGTFP = 2230,
2244 VCMPGTFP_rec = 2231,
2245 VCMPGTSB = 2232,
2246 VCMPGTSB_rec = 2233,
2247 VCMPGTSD = 2234,
2248 VCMPGTSD_rec = 2235,
2249 VCMPGTSH = 2236,
2250 VCMPGTSH_rec = 2237,
2251 VCMPGTSQ = 2238,
2252 VCMPGTSQ_rec = 2239,
2253 VCMPGTSW = 2240,
2254 VCMPGTSW_rec = 2241,
2255 VCMPGTUB = 2242,
2256 VCMPGTUB_rec = 2243,
2257 VCMPGTUD = 2244,
2258 VCMPGTUD_rec = 2245,
2259 VCMPGTUH = 2246,
2260 VCMPGTUH_rec = 2247,
2261 VCMPGTUQ = 2248,
2262 VCMPGTUQ_rec = 2249,
2263 VCMPGTUW = 2250,
2264 VCMPGTUW_rec = 2251,
2265 VCMPNEB = 2252,
2266 VCMPNEB_rec = 2253,
2267 VCMPNEH = 2254,
2268 VCMPNEH_rec = 2255,
2269 VCMPNEW = 2256,
2270 VCMPNEW_rec = 2257,
2271 VCMPNEZB = 2258,
2272 VCMPNEZB_rec = 2259,
2273 VCMPNEZH = 2260,
2274 VCMPNEZH_rec = 2261,
2275 VCMPNEZW = 2262,
2276 VCMPNEZW_rec = 2263,
2277 VCMPSQ = 2264,
2278 VCMPUQ = 2265,
2279 VCNTMBB = 2266,
2280 VCNTMBD = 2267,
2281 VCNTMBH = 2268,
2282 VCNTMBW = 2269,
2283 VCTSXS = 2270,
2284 VCTSXS_0 = 2271,
2285 VCTUXS = 2272,
2286 VCTUXS_0 = 2273,
2287 VCTZB = 2274,
2288 VCTZD = 2275,
2289 VCTZDM = 2276,
2290 VCTZH = 2277,
2291 VCTZLSBB = 2278,
2292 VCTZW = 2279,
2293 VDIVESD = 2280,
2294 VDIVESQ = 2281,
2295 VDIVESW = 2282,
2296 VDIVEUD = 2283,
2297 VDIVEUQ = 2284,
2298 VDIVEUW = 2285,
2299 VDIVSD = 2286,
2300 VDIVSQ = 2287,
2301 VDIVSW = 2288,
2302 VDIVUD = 2289,
2303 VDIVUQ = 2290,
2304 VDIVUW = 2291,
2305 VEQV = 2292,
2306 VEXPANDBM = 2293,
2307 VEXPANDDM = 2294,
2308 VEXPANDHM = 2295,
2309 VEXPANDQM = 2296,
2310 VEXPANDWM = 2297,
2311 VEXPTEFP = 2298,
2312 VEXTDDVLX = 2299,
2313 VEXTDDVRX = 2300,
2314 VEXTDUBVLX = 2301,
2315 VEXTDUBVRX = 2302,
2316 VEXTDUHVLX = 2303,
2317 VEXTDUHVRX = 2304,
2318 VEXTDUWVLX = 2305,
2319 VEXTDUWVRX = 2306,
2320 VEXTRACTBM = 2307,
2321 VEXTRACTD = 2308,
2322 VEXTRACTDM = 2309,
2323 VEXTRACTHM = 2310,
2324 VEXTRACTQM = 2311,
2325 VEXTRACTUB = 2312,
2326 VEXTRACTUH = 2313,
2327 VEXTRACTUW = 2314,
2328 VEXTRACTWM = 2315,
2329 VEXTSB2D = 2316,
2330 VEXTSB2Ds = 2317,
2331 VEXTSB2W = 2318,
2332 VEXTSB2Ws = 2319,
2333 VEXTSD2Q = 2320,
2334 VEXTSH2D = 2321,
2335 VEXTSH2Ds = 2322,
2336 VEXTSH2W = 2323,
2337 VEXTSH2Ws = 2324,
2338 VEXTSW2D = 2325,
2339 VEXTSW2Ds = 2326,
2340 VEXTUBLX = 2327,
2341 VEXTUBRX = 2328,
2342 VEXTUHLX = 2329,
2343 VEXTUHRX = 2330,
2344 VEXTUWLX = 2331,
2345 VEXTUWRX = 2332,
2346 VGBBD = 2333,
2347 VGNB = 2334,
2348 VINSBLX = 2335,
2349 VINSBRX = 2336,
2350 VINSBVLX = 2337,
2351 VINSBVRX = 2338,
2352 VINSD = 2339,
2353 VINSDLX = 2340,
2354 VINSDRX = 2341,
2355 VINSERTB = 2342,
2356 VINSERTD = 2343,
2357 VINSERTH = 2344,
2358 VINSERTW = 2345,
2359 VINSHLX = 2346,
2360 VINSHRX = 2347,
2361 VINSHVLX = 2348,
2362 VINSHVRX = 2349,
2363 VINSW = 2350,
2364 VINSWLX = 2351,
2365 VINSWRX = 2352,
2366 VINSWVLX = 2353,
2367 VINSWVRX = 2354,
2368 VLOGEFP = 2355,
2369 VMADDFP = 2356,
2370 VMAXFP = 2357,
2371 VMAXSB = 2358,
2372 VMAXSD = 2359,
2373 VMAXSH = 2360,
2374 VMAXSW = 2361,
2375 VMAXUB = 2362,
2376 VMAXUD = 2363,
2377 VMAXUH = 2364,
2378 VMAXUW = 2365,
2379 VMHADDSHS = 2366,
2380 VMHRADDSHS = 2367,
2381 VMINFP = 2368,
2382 VMINSB = 2369,
2383 VMINSD = 2370,
2384 VMINSH = 2371,
2385 VMINSW = 2372,
2386 VMINUB = 2373,
2387 VMINUD = 2374,
2388 VMINUH = 2375,
2389 VMINUW = 2376,
2390 VMLADDUHM = 2377,
2391 VMODSD = 2378,
2392 VMODSQ = 2379,
2393 VMODSW = 2380,
2394 VMODUD = 2381,
2395 VMODUQ = 2382,
2396 VMODUW = 2383,
2397 VMRGEW = 2384,
2398 VMRGHB = 2385,
2399 VMRGHH = 2386,
2400 VMRGHW = 2387,
2401 VMRGLB = 2388,
2402 VMRGLH = 2389,
2403 VMRGLW = 2390,
2404 VMRGOW = 2391,
2405 VMSUMCUD = 2392,
2406 VMSUMMBM = 2393,
2407 VMSUMSHM = 2394,
2408 VMSUMSHS = 2395,
2409 VMSUMUBM = 2396,
2410 VMSUMUDM = 2397,
2411 VMSUMUHM = 2398,
2412 VMSUMUHS = 2399,
2413 VMUL10CUQ = 2400,
2414 VMUL10ECUQ = 2401,
2415 VMUL10EUQ = 2402,
2416 VMUL10UQ = 2403,
2417 VMULESB = 2404,
2418 VMULESD = 2405,
2419 VMULESH = 2406,
2420 VMULESW = 2407,
2421 VMULEUB = 2408,
2422 VMULEUD = 2409,
2423 VMULEUH = 2410,
2424 VMULEUW = 2411,
2425 VMULHSD = 2412,
2426 VMULHSW = 2413,
2427 VMULHUD = 2414,
2428 VMULHUW = 2415,
2429 VMULLD = 2416,
2430 VMULOSB = 2417,
2431 VMULOSD = 2418,
2432 VMULOSH = 2419,
2433 VMULOSW = 2420,
2434 VMULOUB = 2421,
2435 VMULOUD = 2422,
2436 VMULOUH = 2423,
2437 VMULOUW = 2424,
2438 VMULUWM = 2425,
2439 VNAND = 2426,
2440 VNCIPHER = 2427,
2441 VNCIPHERLAST = 2428,
2442 VNEGD = 2429,
2443 VNEGW = 2430,
2444 VNMSUBFP = 2431,
2445 VNOR = 2432,
2446 VOR = 2433,
2447 VORC = 2434,
2448 VPDEPD = 2435,
2449 VPERM = 2436,
2450 VPERMR = 2437,
2451 VPERMXOR = 2438,
2452 VPEXTD = 2439,
2453 VPKPX = 2440,
2454 VPKSDSS = 2441,
2455 VPKSDUS = 2442,
2456 VPKSHSS = 2443,
2457 VPKSHUS = 2444,
2458 VPKSWSS = 2445,
2459 VPKSWUS = 2446,
2460 VPKUDUM = 2447,
2461 VPKUDUS = 2448,
2462 VPKUHUM = 2449,
2463 VPKUHUS = 2450,
2464 VPKUWUM = 2451,
2465 VPKUWUS = 2452,
2466 VPMSUMB = 2453,
2467 VPMSUMD = 2454,
2468 VPMSUMH = 2455,
2469 VPMSUMW = 2456,
2470 VPOPCNTB = 2457,
2471 VPOPCNTD = 2458,
2472 VPOPCNTH = 2459,
2473 VPOPCNTW = 2460,
2474 VPRTYBD = 2461,
2475 VPRTYBQ = 2462,
2476 VPRTYBW = 2463,
2477 VREFP = 2464,
2478 VRFIM = 2465,
2479 VRFIN = 2466,
2480 VRFIP = 2467,
2481 VRFIZ = 2468,
2482 VRLB = 2469,
2483 VRLD = 2470,
2484 VRLDMI = 2471,
2485 VRLDNM = 2472,
2486 VRLH = 2473,
2487 VRLQ = 2474,
2488 VRLQMI = 2475,
2489 VRLQNM = 2476,
2490 VRLW = 2477,
2491 VRLWMI = 2478,
2492 VRLWNM = 2479,
2493 VRSQRTEFP = 2480,
2494 VSBOX = 2481,
2495 VSEL = 2482,
2496 VSHASIGMAD = 2483,
2497 VSHASIGMAW = 2484,
2498 VSL = 2485,
2499 VSLB = 2486,
2500 VSLD = 2487,
2501 VSLDBI = 2488,
2502 VSLDOI = 2489,
2503 VSLH = 2490,
2504 VSLO = 2491,
2505 VSLQ = 2492,
2506 VSLV = 2493,
2507 VSLW = 2494,
2508 VSPLTB = 2495,
2509 VSPLTBs = 2496,
2510 VSPLTH = 2497,
2511 VSPLTHs = 2498,
2512 VSPLTISB = 2499,
2513 VSPLTISH = 2500,
2514 VSPLTISW = 2501,
2515 VSPLTW = 2502,
2516 VSR = 2503,
2517 VSRAB = 2504,
2518 VSRAD = 2505,
2519 VSRAH = 2506,
2520 VSRAQ = 2507,
2521 VSRAW = 2508,
2522 VSRB = 2509,
2523 VSRD = 2510,
2524 VSRDBI = 2511,
2525 VSRH = 2512,
2526 VSRO = 2513,
2527 VSRQ = 2514,
2528 VSRV = 2515,
2529 VSRW = 2516,
2530 VSTRIBL = 2517,
2531 VSTRIBL_rec = 2518,
2532 VSTRIBR = 2519,
2533 VSTRIBR_rec = 2520,
2534 VSTRIHL = 2521,
2535 VSTRIHL_rec = 2522,
2536 VSTRIHR = 2523,
2537 VSTRIHR_rec = 2524,
2538 VSUBCUQ = 2525,
2539 VSUBCUW = 2526,
2540 VSUBECUQ = 2527,
2541 VSUBEUQM = 2528,
2542 VSUBFP = 2529,
2543 VSUBSBS = 2530,
2544 VSUBSHS = 2531,
2545 VSUBSWS = 2532,
2546 VSUBUBM = 2533,
2547 VSUBUBS = 2534,
2548 VSUBUDM = 2535,
2549 VSUBUHM = 2536,
2550 VSUBUHS = 2537,
2551 VSUBUQM = 2538,
2552 VSUBUWM = 2539,
2553 VSUBUWS = 2540,
2554 VSUM2SWS = 2541,
2555 VSUM4SBS = 2542,
2556 VSUM4SHS = 2543,
2557 VSUM4UBS = 2544,
2558 VSUMSWS = 2545,
2559 VUPKHPX = 2546,
2560 VUPKHSB = 2547,
2561 VUPKHSH = 2548,
2562 VUPKHSW = 2549,
2563 VUPKLPX = 2550,
2564 VUPKLSB = 2551,
2565 VUPKLSH = 2552,
2566 VUPKLSW = 2553,
2567 VXOR = 2554,
2568 V_SET0 = 2555,
2569 V_SET0B = 2556,
2570 V_SET0H = 2557,
2571 V_SETALLONES = 2558,
2572 V_SETALLONESB = 2559,
2573 V_SETALLONESH = 2560,
2574 WAIT = 2561,
2575 WAITP10 = 2562,
2576 WRTEE = 2563,
2577 WRTEEI = 2564,
2578 XOR = 2565,
2579 XOR8 = 2566,
2580 XOR8_rec = 2567,
2581 XORI = 2568,
2582 XORI8 = 2569,
2583 XORIS = 2570,
2584 XORIS8 = 2571,
2585 XOR_rec = 2572,
2586 XSABSDP = 2573,
2587 XSABSQP = 2574,
2588 XSADDDP = 2575,
2589 XSADDQP = 2576,
2590 XSADDQPO = 2577,
2591 XSADDSP = 2578,
2592 XSCMPEQDP = 2579,
2593 XSCMPEQQP = 2580,
2594 XSCMPEXPDP = 2581,
2595 XSCMPEXPQP = 2582,
2596 XSCMPGEDP = 2583,
2597 XSCMPGEQP = 2584,
2598 XSCMPGTDP = 2585,
2599 XSCMPGTQP = 2586,
2600 XSCMPODP = 2587,
2601 XSCMPOQP = 2588,
2602 XSCMPUDP = 2589,
2603 XSCMPUQP = 2590,
2604 XSCPSGNDP = 2591,
2605 XSCPSGNQP = 2592,
2606 XSCVDPHP = 2593,
2607 XSCVDPQP = 2594,
2608 XSCVDPSP = 2595,
2609 XSCVDPSPN = 2596,
2610 XSCVDPSXDS = 2597,
2611 XSCVDPSXDSs = 2598,
2612 XSCVDPSXWS = 2599,
2613 XSCVDPSXWSs = 2600,
2614 XSCVDPUXDS = 2601,
2615 XSCVDPUXDSs = 2602,
2616 XSCVDPUXWS = 2603,
2617 XSCVDPUXWSs = 2604,
2618 XSCVHPDP = 2605,
2619 XSCVQPDP = 2606,
2620 XSCVQPDPO = 2607,
2621 XSCVQPSDZ = 2608,
2622 XSCVQPSQZ = 2609,
2623 XSCVQPSWZ = 2610,
2624 XSCVQPUDZ = 2611,
2625 XSCVQPUQZ = 2612,
2626 XSCVQPUWZ = 2613,
2627 XSCVSDQP = 2614,
2628 XSCVSPDP = 2615,
2629 XSCVSPDPN = 2616,
2630 XSCVSQQP = 2617,
2631 XSCVSXDDP = 2618,
2632 XSCVSXDSP = 2619,
2633 XSCVUDQP = 2620,
2634 XSCVUQQP = 2621,
2635 XSCVUXDDP = 2622,
2636 XSCVUXDSP = 2623,
2637 XSDIVDP = 2624,
2638 XSDIVQP = 2625,
2639 XSDIVQPO = 2626,
2640 XSDIVSP = 2627,
2641 XSIEXPDP = 2628,
2642 XSIEXPQP = 2629,
2643 XSMADDADP = 2630,
2644 XSMADDASP = 2631,
2645 XSMADDMDP = 2632,
2646 XSMADDMSP = 2633,
2647 XSMADDQP = 2634,
2648 XSMADDQPO = 2635,
2649 XSMAXCDP = 2636,
2650 XSMAXCQP = 2637,
2651 XSMAXDP = 2638,
2652 XSMAXJDP = 2639,
2653 XSMINCDP = 2640,
2654 XSMINCQP = 2641,
2655 XSMINDP = 2642,
2656 XSMINJDP = 2643,
2657 XSMSUBADP = 2644,
2658 XSMSUBASP = 2645,
2659 XSMSUBMDP = 2646,
2660 XSMSUBMSP = 2647,
2661 XSMSUBQP = 2648,
2662 XSMSUBQPO = 2649,
2663 XSMULDP = 2650,
2664 XSMULQP = 2651,
2665 XSMULQPO = 2652,
2666 XSMULSP = 2653,
2667 XSNABSDP = 2654,
2668 XSNABSDPs = 2655,
2669 XSNABSQP = 2656,
2670 XSNEGDP = 2657,
2671 XSNEGQP = 2658,
2672 XSNMADDADP = 2659,
2673 XSNMADDASP = 2660,
2674 XSNMADDMDP = 2661,
2675 XSNMADDMSP = 2662,
2676 XSNMADDQP = 2663,
2677 XSNMADDQPO = 2664,
2678 XSNMSUBADP = 2665,
2679 XSNMSUBASP = 2666,
2680 XSNMSUBMDP = 2667,
2681 XSNMSUBMSP = 2668,
2682 XSNMSUBQP = 2669,
2683 XSNMSUBQPO = 2670,
2684 XSRDPI = 2671,
2685 XSRDPIC = 2672,
2686 XSRDPIM = 2673,
2687 XSRDPIP = 2674,
2688 XSRDPIZ = 2675,
2689 XSREDP = 2676,
2690 XSRESP = 2677,
2691 XSRQPI = 2678,
2692 XSRQPIX = 2679,
2693 XSRQPXP = 2680,
2694 XSRSP = 2681,
2695 XSRSQRTEDP = 2682,
2696 XSRSQRTESP = 2683,
2697 XSSQRTDP = 2684,
2698 XSSQRTQP = 2685,
2699 XSSQRTQPO = 2686,
2700 XSSQRTSP = 2687,
2701 XSSUBDP = 2688,
2702 XSSUBQP = 2689,
2703 XSSUBQPO = 2690,
2704 XSSUBSP = 2691,
2705 XSTDIVDP = 2692,
2706 XSTSQRTDP = 2693,
2707 XSTSTDCDP = 2694,
2708 XSTSTDCQP = 2695,
2709 XSTSTDCSP = 2696,
2710 XSXEXPDP = 2697,
2711 XSXEXPQP = 2698,
2712 XSXSIGDP = 2699,
2713 XSXSIGQP = 2700,
2714 XVABSDP = 2701,
2715 XVABSSP = 2702,
2716 XVADDDP = 2703,
2717 XVADDSP = 2704,
2718 XVBF16GER2 = 2705,
2719 XVBF16GER2NN = 2706,
2720 XVBF16GER2NP = 2707,
2721 XVBF16GER2PN = 2708,
2722 XVBF16GER2PP = 2709,
2723 XVBF16GER2W = 2710,
2724 XVBF16GER2WNN = 2711,
2725 XVBF16GER2WNP = 2712,
2726 XVBF16GER2WPN = 2713,
2727 XVBF16GER2WPP = 2714,
2728 XVCMPEQDP = 2715,
2729 XVCMPEQDP_rec = 2716,
2730 XVCMPEQSP = 2717,
2731 XVCMPEQSP_rec = 2718,
2732 XVCMPGEDP = 2719,
2733 XVCMPGEDP_rec = 2720,
2734 XVCMPGESP = 2721,
2735 XVCMPGESP_rec = 2722,
2736 XVCMPGTDP = 2723,
2737 XVCMPGTDP_rec = 2724,
2738 XVCMPGTSP = 2725,
2739 XVCMPGTSP_rec = 2726,
2740 XVCPSGNDP = 2727,
2741 XVCPSGNSP = 2728,
2742 XVCVBF16SPN = 2729,
2743 XVCVDPSP = 2730,
2744 XVCVDPSXDS = 2731,
2745 XVCVDPSXWS = 2732,
2746 XVCVDPUXDS = 2733,
2747 XVCVDPUXWS = 2734,
2748 XVCVHPSP = 2735,
2749 XVCVSPBF16 = 2736,
2750 XVCVSPDP = 2737,
2751 XVCVSPHP = 2738,
2752 XVCVSPSXDS = 2739,
2753 XVCVSPSXWS = 2740,
2754 XVCVSPUXDS = 2741,
2755 XVCVSPUXWS = 2742,
2756 XVCVSXDDP = 2743,
2757 XVCVSXDSP = 2744,
2758 XVCVSXWDP = 2745,
2759 XVCVSXWSP = 2746,
2760 XVCVUXDDP = 2747,
2761 XVCVUXDSP = 2748,
2762 XVCVUXWDP = 2749,
2763 XVCVUXWSP = 2750,
2764 XVDIVDP = 2751,
2765 XVDIVSP = 2752,
2766 XVF16GER2 = 2753,
2767 XVF16GER2NN = 2754,
2768 XVF16GER2NP = 2755,
2769 XVF16GER2PN = 2756,
2770 XVF16GER2PP = 2757,
2771 XVF16GER2W = 2758,
2772 XVF16GER2WNN = 2759,
2773 XVF16GER2WNP = 2760,
2774 XVF16GER2WPN = 2761,
2775 XVF16GER2WPP = 2762,
2776 XVF32GER = 2763,
2777 XVF32GERNN = 2764,
2778 XVF32GERNP = 2765,
2779 XVF32GERPN = 2766,
2780 XVF32GERPP = 2767,
2781 XVF32GERW = 2768,
2782 XVF32GERWNN = 2769,
2783 XVF32GERWNP = 2770,
2784 XVF32GERWPN = 2771,
2785 XVF32GERWPP = 2772,
2786 XVF64GER = 2773,
2787 XVF64GERNN = 2774,
2788 XVF64GERNP = 2775,
2789 XVF64GERPN = 2776,
2790 XVF64GERPP = 2777,
2791 XVF64GERW = 2778,
2792 XVF64GERWNN = 2779,
2793 XVF64GERWNP = 2780,
2794 XVF64GERWPN = 2781,
2795 XVF64GERWPP = 2782,
2796 XVI16GER2 = 2783,
2797 XVI16GER2PP = 2784,
2798 XVI16GER2S = 2785,
2799 XVI16GER2SPP = 2786,
2800 XVI16GER2SW = 2787,
2801 XVI16GER2SWPP = 2788,
2802 XVI16GER2W = 2789,
2803 XVI16GER2WPP = 2790,
2804 XVI4GER8 = 2791,
2805 XVI4GER8PP = 2792,
2806 XVI4GER8W = 2793,
2807 XVI4GER8WPP = 2794,
2808 XVI8GER4 = 2795,
2809 XVI8GER4PP = 2796,
2810 XVI8GER4SPP = 2797,
2811 XVI8GER4W = 2798,
2812 XVI8GER4WPP = 2799,
2813 XVI8GER4WSPP = 2800,
2814 XVIEXPDP = 2801,
2815 XVIEXPSP = 2802,
2816 XVMADDADP = 2803,
2817 XVMADDASP = 2804,
2818 XVMADDMDP = 2805,
2819 XVMADDMSP = 2806,
2820 XVMAXDP = 2807,
2821 XVMAXSP = 2808,
2822 XVMINDP = 2809,
2823 XVMINSP = 2810,
2824 XVMSUBADP = 2811,
2825 XVMSUBASP = 2812,
2826 XVMSUBMDP = 2813,
2827 XVMSUBMSP = 2814,
2828 XVMULDP = 2815,
2829 XVMULSP = 2816,
2830 XVNABSDP = 2817,
2831 XVNABSSP = 2818,
2832 XVNEGDP = 2819,
2833 XVNEGSP = 2820,
2834 XVNMADDADP = 2821,
2835 XVNMADDASP = 2822,
2836 XVNMADDMDP = 2823,
2837 XVNMADDMSP = 2824,
2838 XVNMSUBADP = 2825,
2839 XVNMSUBASP = 2826,
2840 XVNMSUBMDP = 2827,
2841 XVNMSUBMSP = 2828,
2842 XVRDPI = 2829,
2843 XVRDPIC = 2830,
2844 XVRDPIM = 2831,
2845 XVRDPIP = 2832,
2846 XVRDPIZ = 2833,
2847 XVREDP = 2834,
2848 XVRESP = 2835,
2849 XVRSPI = 2836,
2850 XVRSPIC = 2837,
2851 XVRSPIM = 2838,
2852 XVRSPIP = 2839,
2853 XVRSPIZ = 2840,
2854 XVRSQRTEDP = 2841,
2855 XVRSQRTESP = 2842,
2856 XVSQRTDP = 2843,
2857 XVSQRTSP = 2844,
2858 XVSUBDP = 2845,
2859 XVSUBSP = 2846,
2860 XVTDIVDP = 2847,
2861 XVTDIVSP = 2848,
2862 XVTLSBB = 2849,
2863 XVTSQRTDP = 2850,
2864 XVTSQRTSP = 2851,
2865 XVTSTDCDP = 2852,
2866 XVTSTDCSP = 2853,
2867 XVXEXPDP = 2854,
2868 XVXEXPSP = 2855,
2869 XVXSIGDP = 2856,
2870 XVXSIGSP = 2857,
2871 XXBLENDVB = 2858,
2872 XXBLENDVD = 2859,
2873 XXBLENDVH = 2860,
2874 XXBLENDVW = 2861,
2875 XXBRD = 2862,
2876 XXBRH = 2863,
2877 XXBRQ = 2864,
2878 XXBRW = 2865,
2879 XXEVAL = 2866,
2880 XXEXTRACTUW = 2867,
2881 XXGENPCVBM = 2868,
2882 XXGENPCVDM = 2869,
2883 XXGENPCVHM = 2870,
2884 XXGENPCVWM = 2871,
2885 XXINSERTW = 2872,
2886 XXLAND = 2873,
2887 XXLANDC = 2874,
2888 XXLEQV = 2875,
2889 XXLEQVOnes = 2876,
2890 XXLNAND = 2877,
2891 XXLNOR = 2878,
2892 XXLOR = 2879,
2893 XXLORC = 2880,
2894 XXLORf = 2881,
2895 XXLXOR = 2882,
2896 XXLXORdpz = 2883,
2897 XXLXORspz = 2884,
2898 XXLXORz = 2885,
2899 XXMFACC = 2886,
2900 XXMFACCW = 2887,
2901 XXMRGHW = 2888,
2902 XXMRGLW = 2889,
2903 XXMTACC = 2890,
2904 XXMTACCW = 2891,
2905 XXPERM = 2892,
2906 XXPERMDI = 2893,
2907 XXPERMDIs = 2894,
2908 XXPERMR = 2895,
2909 XXPERMX = 2896,
2910 XXSEL = 2897,
2911 XXSETACCZ = 2898,
2912 XXSLDWI = 2899,
2913 XXSLDWIs = 2900,
2914 XXSPLTI32DX = 2901,
2915 XXSPLTIB = 2902,
2916 XXSPLTIDP = 2903,
2917 XXSPLTIW = 2904,
2918 XXSPLTW = 2905,
2919 XXSPLTWs = 2906,
2920 gBC = 2907,
2921 gBCA = 2908,
2922 gBCAat = 2909,
2923 gBCCTR = 2910,
2924 gBCCTRL = 2911,
2925 gBCL = 2912,
2926 gBCLA = 2913,
2927 gBCLAat = 2914,
2928 gBCLR = 2915,
2929 gBCLRL = 2916,
2930 gBCLat = 2917,
2931 gBCat = 2918,
2932 INSTRUCTION_LIST_END = 2919
2933 };
2934
2935} // end namespace llvm::PPC
2936#endif // GET_INSTRINFO_ENUM
2937
2938#ifdef GET_INSTRINFO_SCHED_ENUM
2939#undef GET_INSTRINFO_SCHED_ENUM
2940namespace llvm::PPC::Sched {
2941
2942 enum {
2943 NoInstrModel = 0,
2944 IIC_LdStSync = 1,
2945 IIC_IntSimple = 2,
2946 IIC_IntGeneral = 3,
2947 IIC_BrB = 4,
2948 IIC_VecFP = 5,
2949 IIC_IntRotate = 6,
2950 IIC_IntCompare = 7,
2951 IIC_SprABORT = 8,
2952 IIC_LdStCOPY = 9,
2953 IIC_LdStPASTE = 10,
2954 IIC_BrCR = 11,
2955 IIC_FPGeneral = 12,
2956 IIC_LdStLD = 13,
2957 IIC_LdStDCBF = 14,
2958 IIC_LdStLoad = 15,
2959 IIC_FPCompare = 16,
2960 IIC_IntDivD = 17,
2961 IIC_IntDivW = 18,
2962 IIC_VecGeneral = 19,
2963 IIC_FPDGeneral = 20,
2964 IIC_FPAddSub = 21,
2965 IIC_FPDivD = 22,
2966 IIC_FPSGeneral = 23,
2967 IIC_VecComplex = 24,
2968 IIC_LdStStore = 25,
2969 IIC_IntRotateDI = 26,
2970 IIC_FPDivS = 27,
2971 IIC_FPFused = 28,
2972 IIC_FPSqrtD = 29,
2973 IIC_FPSqrtS = 30,
2974 IIC_LdStICBI = 31,
2975 IIC_IntISEL = 32,
2976 IIC_SprISYNC = 33,
2977 IIC_LdStLWARX = 34,
2978 IIC_LdStLoadUpd = 35,
2979 IIC_LdStLoadUpdX = 36,
2980 IIC_LdStLDARX = 37,
2981 IIC_LdStLDU = 38,
2982 IIC_LdStLDUX = 39,
2983 IIC_LdStLFD = 40,
2984 IIC_LdStLFDU = 41,
2985 IIC_LdStLFDUX = 42,
2986 IIC_LdStLHA = 43,
2987 IIC_LdStLHAU = 44,
2988 IIC_LdStLHAUX = 45,
2989 IIC_LdStLMW = 46,
2990 IIC_LdStLQ = 47,
2991 IIC_LdStLQARX = 48,
2992 IIC_LdStLWA = 49,
2993 IIC_IntMulHD = 50,
2994 IIC_BrMCR = 51,
2995 IIC_BrMCRX = 52,
2996 IIC_SprMFCR = 53,
2997 IIC_SprMFSPR = 54,
2998 IIC_IntMFFS = 55,
2999 IIC_SprMFMSR = 56,
3000 IIC_SprMFCRF = 57,
3001 IIC_SprMFPMR = 58,
3002 IIC_SprMFSR = 59,
3003 IIC_SprMFTB = 60,
3004 IIC_SprMSGSYNC = 61,
3005 IIC_SprMTSPR = 62,
3006 IIC_IntMTFSB0 = 63,
3007 IIC_SprMTMSR = 64,
3008 IIC_SprMTMSRD = 65,
3009 IIC_SprMTPMR = 66,
3010 IIC_SprMTSR = 67,
3011 IIC_IntMulHW = 68,
3012 IIC_IntMulHWU = 69,
3013 IIC_IntMulLI = 70,
3014 IIC_SprRFI = 71,
3015 IIC_IntRFID = 72,
3016 IIC_IntRotateD = 73,
3017 IIC_SprSLBFEE = 74,
3018 IIC_SprSLBIA = 75,
3019 IIC_SprSLBIE = 76,
3020 IIC_SprSLBIEG = 77,
3021 IIC_SprSLBMFEE = 78,
3022 IIC_SprSLBMFEV = 79,
3023 IIC_SprSLBMTE = 80,
3024 IIC_SprSLBSYNC = 81,
3025 IIC_IntShift = 82,
3026 IIC_LdStSTWCX = 83,
3027 IIC_LdStSTU = 84,
3028 IIC_LdStSTUX = 85,
3029 IIC_LdStSTD = 86,
3030 IIC_LdStSTDCX = 87,
3031 IIC_LdStSTFD = 88,
3032 IIC_LdStSTFDU = 89,
3033 IIC_SprSTOP = 90,
3034 IIC_LdStSTQ = 91,
3035 IIC_LdStSTQCX = 92,
3036 IIC_IntTrapD = 93,
3037 IIC_SprTLBIA = 94,
3038 IIC_SprTLBIE = 95,
3039 IIC_SprTLBIEL = 96,
3040 IIC_SprTLBSYNC = 97,
3041 IIC_IntTrapW = 98,
3042 IIC_VecFPCompare = 99,
3043 IIC_VecPerm = 100,
3044 B_BA_BL_BL8_BL8_NOP_BL8_NOP_RM_BL8_NOP_TLS_BL8_NOTOC_BL8_NOTOC_RM_BL8_NOTOC_TLS_BL8_RM_BL8_TLS_BL8_TLS__BLA_BLA8_BLA8_NOP_BLA8_NOP_RM_BLA8_RM_BLA_RM_BL_NOP_BL_NOP_RM_BL_RM_BL_TLS = 101,
3045 BDZLRLp_BDZLRm_BDZLRp_BDZLm_BDZLp_BDZm_BDZp_BDNZ_BDNZ8_BDNZA_BDNZAm_BDNZAp_BDNZL_BDNZLA_BDNZLAm_BDNZLAp_BDNZLR_BDNZLR8_BDNZLRL_BDNZLRLm_BDNZLRLp_BDNZLRm_BDNZLRp_BDNZLm_BDNZLp_BDNZm_BDNZp_BDZ_BDZ8_BDZA_BDZAm_BDZAp_BDZL_BDZLA_BDZLAm_BDZLAp_BDZLR_BDZLR8_BDZLRL_BDZLRLm_BLR_BLR8_BLRL_BCL_BCLR_BCLRL_BCLRLn_BCLRn_BCLalways_BCLn_BCTR_BCTR8_BCTRL_BCTRL8_BCTRL8_LDinto_toc_BCTRL8_LDinto_toc_RM_BCTRL8_RM_BCTRL_LWZinto_toc_BCTRL_LWZinto_toc_RM_BCTRL_RM_BCn_BC_BCC_BCCA_BCCCTR_BCCCTR8_BCCCTRL_BCCCTRL8_BCCL_BCCLA_BCCLR_BCCLRL_BCCTR_BCCTR8_BCCTR8n_BCCTRL_BCCTRL8_BCCTRL8n_BCCTRLn_BCCTRn_gBC_gBCA_gBCAat_gBCCTR_gBCCTRL_gBCL_gBCLA_gBCLAat_gBCLR_gBCLRL_gBCLat_gBCat = 102,
3046 MFCTR_MFCTR8_MFLR_MFLR8 = 103,
3047 MTLR_MTLR8_MTCTR_MTCTR8_MTCTR8loop_MTCTRloop = 104,
3048 MFCR_MFCR8 = 105,
3049 MCRF = 106,
3050 CR6SET_CR6UNSET_CRSET_CRUNSET_CRAND_CRANDC_CREQV_CRNAND_CRNOR_CRNOT_CROR_CRORC = 107,
3051 LMW = 108,
3052 LWARX_LWARXL = 109,
3053 LDARX_LDARXL = 110,
3054 LHBRX_LHBRX8_LWBRX_LWBRX8 = 111,
3055 MFSR_MFSRIN = 112,
3056 LFS_LFSX_LFSXTLS_LFSXTLS__LFD_LFDX_LFDXTLS_LFDXTLS__LXSDX_LXVD2X_LXVW4X_LXVDSX = 113,
3057 LFSU_LFDU = 114,
3058 LFSUX_LFDUX = 115,
3059 STXSDX_STXVD2X_STXVW4X = 116,
3060 LBARX_LHARX = 117,
3061 LBZCIX_LDBRX_LDCIX_LHZCIX_LSWI_LVEBX_LVEHX_LVEWX_LVSL_LVSR_LVX_LVXL_LWZCIX_STHCIX_STSWI_STWCIX = 118,
3062 LFIWAX_LFIWZX = 119,
3063 STFD_STFDX_STFIWX_STFS_STFSX = 120,
3064 STFDU_STFDUX_STFSU_STFSUX = 121,
3065 STVEBX_STVEHX_STVEWX_STVX_STVXL = 122,
3066 LHA_LHA8_LHAX_LHAX8_LWAX_LWAX_32 = 123,
3067 LWA_LWA_32 = 124,
3068 LHAU_LHAU8 = 125,
3069 LHAUX_LHAUX8_LWAUX = 126,
3070 STB_STB8_STH_STH8_STW_STW8_STBX_STBX8_STHX_STHX8_STWX_STWX8_STHBRX_STWBRX = 127,
3071 STD_STDX = 128,
3072 STMW = 129,
3073 STWCX = 130,
3074 STDCX = 131,
3075 STDU_STHU_STHU8_STBU_STBU8_STWU_STWU8 = 132,
3076 STDUX_STWUX_STWUX8_STHUX_STHUX8_STBUX_STBUX8 = 133,
3077 LWZU_LWZU8_LHZU_LHZU8_LBZU_LBZU8 = 134,
3078 LDU = 135,
3079 LWZUX_LWZUX8_LHZUX_LHZUX8_LBZUX_LBZUX8 = 136,
3080 LDUX = 137,
3081 ADDI_ADDI8_ADDIS_ADDIS8_LI_LI8_LIS_LIS8_ADD4_ADD4TLS_ADD4_rec_ADD8_ADD8TLS_ADD8TLS__ADD8_rec_ORI_ORI8_ORIS_ORIS8_XORI_XORI8_XORIS_XORIS8_XOR_XOR8_XOR8_rec_XOR_rec_NEG_NEG8_NEG8_rec_NEG_rec_NEG8O_NEGO_AND_AND8_AND_rec_AND8_rec_NAND_NAND8_NAND_rec_NAND8_rec_NOR_NOR8_NOR_rec_NOR8_rec_EQV_EQV8_EQV_rec_EQV8_rec_ANDC_ANDC8_ANDC_rec_ANDC8_rec_ORC_ORC8_ORC_rec_ORC8_rec = 138,
3082 SUBF8_SUBF8_rec_ADDIC_ADDIC8_SUBFIC_SUBFIC8_SUBFZE_SUBFZE8_ADDE_ADDE8_ADDME_ADDME8_SUBFME_SUBFME8_ANDI_rec_ANDIS_rec = 139,
3083 CMPD_CMPDI_CMPLD_CMPLDI_CMPLW_CMPLWI_CMPW_CMPWI = 140,
3084 EXTSB8_32_64_EXTSB8_rec_EXTSH8_32_64_EXTSH8_rec_EXTSW_32_EXTSW_32_64_EXTSW_32_64_rec_ADD4O_ADD8O_ADD8O_rec_ADD4O_rec_NEG8O_rec_NEGO_rec_EXTSB_EXTSB8_EXTSB_rec_EXTSH_EXTSH8_EXTSH_rec_EXTSW_EXTSW_rec = 141,
3085 POPCNTB_POPCNTB8_POPCNTD_POPCNTW_ANDI8_rec_ANDIS8_rec_ADDC_ADDC8_SUBFO_SUBF8O_SUBFC_SUBFC8_ADDIC_rec_ADDE8_rec_ADDE_rec_SUBFE8_rec_SUBFE_rec_ADDME8_rec_ADDME_rec_SUBFME8_rec_SUBFME_rec_ADDZE8_rec_ADDZE_rec_SUBFZE_rec_SUBFZE8_rec_SUBFO_rec_SUBF8O_rec_ADDE8O_ADDEO_SUBFE8O_SUBFEO_ADDME8O_ADDMEO_SUBFME8O_SUBFMEO_ADDZE8O_ADDZEO_SUBFZE8O_SUBFZEO_ADDE8O_rec_ADDEO_rec_ADDMEO_rec_ADDME8O_rec_SUBFMEO_rec_SUBFME8O_rec_ADDZEO_rec_ADDZE8O_rec_SUBFZEO_rec_SUBFZE8O_rec_ADDC8_rec_ADDC_rec_ADDCO_ADDCO_rec_ADDC8O_ADDC8O_rec_SUBFC8_rec_SUBFC_rec_SUBFCO_SUBFC8O_SUBFCO_rec_SUBFC8O_rec_RLWINM_RLWINM8_RLWINM_rec_RLWNM_RLWNM8_RLWNM_rec_RLWINM8_rec_RLWNM8_rec_SLW_SLW8_SLW_rec_SLW8_rec_SRW_SRW8_SRW_rec_SRW8_rec_SUBFE_SUBFE8_SUBFE8O_rec_SUBFEO_rec = 142,
3086 ADDPCIS = 143,
3087 SUBFUS_SUBFUS_rec = 144,
3088 RLDICL_RLDICL_rec_RLDICR_RLDICR_rec_RLDIC_RLDIC_rec_RLDIMI_RLDIMI_rec_RLDICL_32_RLDICL_32_64_RLDICL_32_rec_RLDICR_32_SRADI_SRADI_rec_SRADI_32 = 145,
3089 RLDCL_RLDCL_rec_RLDCR_RLDCR_rec_SLD_SLD_rec_SRD_SRD_rec_SRAD_SRAD_rec = 146,
3090 SRAWI_SRAWI_rec_SRAWI8_SRAWI8_rec_SRAW_SRAW_rec_SRAW8_SRAW8_rec = 147,
3091 CNTLZD_CNTLZDM_CNTLZD_rec_CNTLZW_CNTLZW8_CNTLZW8_rec_CNTLZW_rec_CNTTZD_CNTTZDM_CNTTZD_rec_CNTTZW_CNTTZW8_CNTTZW8_rec_CNTTZW_rec = 148,
3092 MULLI_MULLI8 = 149,
3093 MULLW_MULHW_MULHD_MULLWO_MULLW_rec_MULHD_rec_MULHW_rec_MULLWO_rec = 150,
3094 MULHWU_MULHDU_MULHDU_rec_MULHWU_rec = 151,
3095 MULLD_MULLDO_MULLD_rec_MULLDO_rec = 152,
3096 DIVDE_DIVDEO_DIVDEO_rec_DIVDEU_DIVDEUO_DIVDEUO_rec_DIVDEU_rec_DIVDE_rec = 153,
3097 DIVWE_DIVWEO_DIVWEO_rec_DIVWEU_DIVWEUO_DIVWEUO_rec_DIVWEU_rec_DIVWE_rec_DIVW_DIVWU_DIVWU_rec_DIVWO_DIVWO_rec_DIVWUO_DIVWUO_rec_DIVW_rec = 154,
3098 DIVD_DIVDU_DIVDO_DIVDO_rec_DIVDUO_DIVDUO_rec_DIVDU_rec_DIVD_rec = 155,
3099 FABSD_FABSD_rec_FABSS_FABSS_rec_FADDS_FADDS_rec_FMADDS_FMADDS_rec_FMR_FMR_rec_FMSUBS_FMSUBS_rec_FMULS_FMULS_rec_FNABSD_FNABSD_rec_FNABSS_FNABSS_rec_FNEGD_FNEGD_rec_FNEGS_FNEGS_rec_FNMADDS_FNMADDS_rec_FNMSUBS_FNMSUBS_rec_FSUBS_FSUBS_rec_FCFID_FCFIDS_FCFIDS_rec_FCFIDU_FCFIDUS_FCFIDUS_rec_FCFIDU_rec_FCFID_rec_FCTID_FCTIDU_FCTIDUZ_FCTIDUZ_rec_FCTIDU_rec_FCTIDZ_FCTIDZ_rec_FCTID_rec_FCTIW_FCTIWU_FCTIWUZ_FCTIWUZ_rec_FCTIWU_rec_FCTIWZ_FCTIWZ_rec_FCTIW_rec_FRE_FRES_rec_FRE_rec_FRSP_rec_FRSP_FRES_FRSQRTE_FRSQRTES_FRSQRTES_rec_FRSQRTE_rec_FSELD_FSELS_FSELD_rec_FSELS_rec_FCPSGND_FCPSGND_rec_FCPSGNS_FCPSGNS_rec_FRIMD_FRIMD_rec_FRIMS_FRIMS_rec_FRIND_FRIND_rec_FRINS_FRINS_rec_FRIPD_FRIPD_rec_FRIPS_FRIPS_rec_FRIZD_FRIZD_rec_FRIZS_FRIZS_rec = 156,
3100 FADD_FADD_rec_FSUB_FSUB_rec = 157,
3101 FMADD_FMADD_rec_FMSUB_FMSUB_rec_FMUL_FMUL_rec_FNMADD_FNMADD_rec_FNMSUB_FNMSUB_rec = 158,
3102 XSMADDADP_XSMADDASP_XSMADDMDP_XSMADDMSP_XSMSUBADP_XSMSUBASP_XSMSUBMDP_XSMSUBMSP_XSNMADDADP_XSNMADDASP_XSNMADDMDP_XSNMADDMSP_XSNMSUBADP_XSNMSUBASP_XSNMSUBMDP_XSNMSUBMSP_XSABSDP_XSADDDP_XSADDSP_XSMULDP_XSMULSP_XSNABSDP_XSNABSDPs_XSNEGDP_XSSUBDP_XSSUBSP_XSCPSGNDP_XSCVDPSP_XSCVDPSXDS_XSCVDPSXDSs_XSCVDPSXWS_XSCVDPSXWSs_XSCVDPUXDS_XSCVDPUXDSs_XSCVDPUXWS_XSCVDPUXWSs_XSCVSPDP_XSCVSXDDP_XSCVUXDDP_XSMAXDP_XSMINDP_XSRDPI_XSRDPIC_XSRDPIM_XSRDPIP_XSRDPIZ_XSREDP_XSRSQRTEDP = 159,
3103 FTDIV_FTSQRT_XSTDIVDP_XSTSQRTDP_XSCMPODP_XSCMPUDP = 160,
3104 XVADDDP_XVADDSP_XVMADDADP_XVMADDASP_XVMADDMDP_XVMADDMSP_XVMSUBADP_XVMSUBASP_XVMSUBMDP_XVMSUBMSP_XVNMADDADP_XVNMADDASP_XVNMADDMDP_XVNMADDMSP_XVNMSUBADP_XVNMSUBASP_XVNMSUBMDP_XVNMSUBMSP_XVSUBDP_XVSUBSP_XVABSDP_XVABSSP_XVMAXDP_XVMAXSP_XVMINDP_XVMINSP_XVMULDP_XVMULSP_XVNABSDP_XVNABSSP_XVNEGDP_XVNEGSP_XVCPSGNDP_XVCVDPSXDS_XVCVDPSXWS_XVCVDPUXDS_XVCVDPUXWS_XVCVSPSXDS_XVCVSPSXWS_XVCVSPUXDS_XVCVSPUXWS_XVCVSXDDP_XVCVSXWDP_XVCVUXDDP_XVCVUXWDP_XVRDPI_XVRDPIC_XVRDPIM_XVRDPIP_XVRDPIZ_XVREDP_XVRSPI_XVRSPIC_XVRSPIM_XVRSPIP_XVRSPIZ_XVRSQRTEDP = 161,
3105 XVCMPEQDP_XVCMPEQDP_rec_XVCMPGEDP_XVCMPGEDP_rec_XVCMPGTDP_XVCMPGTDP_rec = 162,
3106 XVTDIVDP_XVTSQRTDP = 163,
3107 VPKSHSS_VPKSHUS_VPKSWSS_VPKSWUS_VPKUHUM_VPKUHUS_VPKUWUM_VPKUWUS_VUPKHPX_VUPKHSB_VUPKHSH_VUPKLPX_VUPKLSB_VUPKLSH_VPERM_VSEL_VPKPX = 164,
3108 XXMRGHW_XXMRGLW_XXPERMDI_XXPERMDIs_XXSLDWI_XXSLDWIs_VSPLTB_VSPLTBs_VSPLTH_VSPLTHs_VSPLTISB_VSPLTISH_VSPLTISW_VSPLTW_XXSPLTW_XXSPLTWs_XXSEL = 165,
3109 VADDSBS_VADDSHS_VADDSWS_VADDUBS_VADDUHS_VADDUWS_VMAXSB_VMAXSH_VMAXSW_VMAXUB_VMAXUH_VMAXUW_VMINSB_VMINSH_VMINSW_VMINUB_VMINUH_VMINUW_VMRGHB_VMRGHH_VMRGHW_VMRGLB_VMRGLH_VMRGLW_XVRSQRTESP_XVRESP_XVCVSXDSP_XVCVSXWSP_XVCVUXDSP_XVCVUXWSP_XVCPSGNSP_XVCVDPSP_VADDCUW_VADDFP_VAND_VANDC_VAVGSB_VAVGSH_VAVGSW_VAVGUB_VAVGUH_VAVGUW_VCFSX_VCFUX_VCTSXS_VCTUXS_VEXPTEFP_VLOGEFP_VNOR_VOR_VMADDFP_VMHADDSHS_VMHRADDSHS_VMLADDUHM_VNMSUBFP_VMAXFP_VMINFP_VMSUMMBM_VMSUMSHM_VMSUMSHS_VMSUMUBM_VMSUMUDM_VMSUMUHM_VMSUMUHS_VMULESB_VMULESH_VMULEUB_VMULEUH_VMULOSB_VMULOSH_VMULOUB_VMULOUH_VREFP_VRFIM_VRFIN_VRFIP_VRFIZ_VRLB_VRLH_VRLW_VRSQRTEFP_VSR_VSRAB_VSRAH_VSRAW_VSRB_VSRH_VSRO_VSRW_VSUBCUW_VSL_VSLB_VSLDOI_VSLH_VSLO_VSLW_VSUBSBS_VSUBSHS_VSUBSWS_VSUBUBS_VSUBUHS_VSUBUWS_VSUM2SWS_VSUM4SBS_VSUM4SHS_VSUM4UBS_VSUMSWS_VXOR = 166,
3110 VADDUBM_VADDUHM_VADDUWM_XXLORf_XXLXORdpz_XXLXORspz_XXLXORz_VSUBFP_VSUBUBM_VSUBUHM_VSUBUWM_XXLAND_XXLANDC_XXLNOR_XXLOR_XXLXOR = 167,
3111 XVTDIVSP_XVTSQRTSP = 168,
3112 XVCMPEQSP_XVCMPEQSP_rec_XVCMPGESP_XVCMPGESP_rec_XVCMPGTSP_XVCMPGTSP_rec_VCMPBFP_VCMPBFP_rec_VCMPEQFP_VCMPEQFP_rec_VCMPEQUB_VCMPEQUB_rec_VCMPEQUH_VCMPEQUH_rec_VCMPEQUW_VCMPEQUW_rec_VCMPGEFP_VCMPGEFP_rec_VCMPGTFP_VCMPGTFP_rec_VCMPGTSB_VCMPGTSB_rec_VCMPGTSH_VCMPGTSH_rec_VCMPGTSW_VCMPGTSW_rec_VCMPGTUB_VCMPGTUB_rec_VCMPGTUH_VCMPGTUH_rec_VCMPGTUW_VCMPGTUW_rec = 169,
3113 FCMPOD_FCMPOS_FCMPUD_FCMPUS = 170,
3114 FDIVS_FDIVS_rec = 171,
3115 XSDIVDP = 172,
3116 FSQRTS_XSSQRTSP_FSQRTS_rec = 173,
3117 FDIV_FDIV_rec = 174,
3118 XSSQRTDP = 175,
3119 FSQRT_FSQRT_rec = 176,
3120 XVDIVSP = 177,
3121 XVSQRTSP = 178,
3122 XVDIVDP = 179,
3123 XVSQRTDP = 180,
3124 MFOCRF_MFOCRF8 = 181,
3125 VCIPHER_VCIPHERLAST_VNCIPHER_VNCIPHERLAST_VPMSUMB_VPMSUMD_VPMSUMH_VPMSUMW_VSBOX = 182,
3126 XSDIVSP = 183,
3127 FSQRTS_FSQRTS_rec = 184,
3128 MTFSFI_rec_MTFSF_rec_MTFSFI_MTFSFIb_MTFSF = 185,
3129 MTFSFb_MTFSB0_MTFSB1 = 186,
3130 XSMADDADP_XSMADDASP_XSMADDMDP_XSMADDMSP_XSMSUBADP_XSMSUBASP_XSMSUBMDP_XSMSUBMSP_XSNMADDADP_XSNMADDASP_XSNMADDMDP_XSNMADDMSP_XSNMSUBADP_XSNMSUBASP_XSNMSUBMDP_XSNMSUBMSP_XSABSDP_XSADDDP_XSADDSP_XSCPSGNDP_XSMULDP_XSMULSP_XSNABSDP_XSNABSDPs_XSNEGDP_XSREDP_XSRSQRTEDP_XSSUBDP_XSSUBSP_XSCVDPSXDS_XSCVDPSXDSs_XSCVDPSXWS_XSCVDPSXWSs_XSCVDPUXDS_XSCVDPUXDSs_XSCVDPUXWS_XSCVDPUXWSs_XSCVSXDDP_XSCVUXDDP_XSCVDPSP_XSCVSPDP_XSRDPI_XSRDPIC_XSRDPIM_XSRDPIP_XSRDPIZ = 187,
3131 XSRESP_XSRSQRTESP_XSCVSXDSP_XSCVUXDSP_XSCVDPSPN_XSCVSPDPN_XSRSP = 188,
3132 XVMADDASP_XVMADDMSP_XVMSUBASP_XVMSUBMSP_XVNMADDASP_XVNMADDMSP_XVNMSUBASP_XVNMSUBMSP_XVSUBSP_XVMULSP_XVNABSSP_XVNEGSP_XVABSSP_XVADDSP = 189,
3133 VRFIM_VRFIN_VRFIP_VRFIZ_XVRSQRTESP_VADDFP_VEXPTEFP_VLOGEFP_VMADDFP_VNMSUBFP_VREFP_VRSQRTEFP_XVCVSXWSP_XVCVUXWSP_XVRESP_XVCVDPSP_XVCVSXDSP_XVCVUXDSP_XVCPSGNSP = 190,
3134 VSUBFP = 191,
3135 XVRDPI_XVRDPIC_XVRDPIM_XVRDPIP_XVRDPIZ_XVRSPI_XVRSPIC_XVRSPIM_XVRSPIP_XVRSPIZ_XVCVSXDDP_XVCVSXWDP_XVCVUXDDP_XVCVUXWDP_XVCVDPSXDS_XVCVDPSXWS_XVCVDPUXDS_XVCVDPUXWS_XVCVSPSXDS_XVCVSPSXWS_XVCVSPUXDS_XVCVSPUXWS_XVABSDP_XVADDDP_XVCPSGNDP_XVMADDADP_XVMADDMDP_XVMSUBADP_XVMSUBMDP_XVMULDP_XVNABSDP_XVNEGDP_XVNMADDADP_XVNMADDMDP_XVNMSUBADP_XVNMSUBMDP_XVREDP_XVRSQRTEDP_XVSUBDP = 192,
3136 XVCVSPDP = 193,
3137 TDI_TD = 194,
3138 TWI_TW = 195,
3139 MTCRF_MTCRF8_MTOCRF_MTOCRF8 = 196,
3140 RLWIMI_RLWIMI8 = 197,
3141 AND_AND8_AND8_rec_ANDC_ANDC8_ANDC8_rec_ANDC_rec_AND_rec_EQV_EQV8_EQV8_rec_EQV_rec_NAND_NAND8_NAND8_rec_NAND_rec_NOR_NOR8_NOR8_rec_NOR_rec_ORC_ORC8_ORC8_rec_ORC_rec_ORI_ORI8_ORIS_ORIS8_XOR_XOR8_XOR8_rec_XORI_XORI8_XORIS_XORIS8_XOR_rec_ADD4_rec_ADD8_rec_NEG8_rec_NEG_rec = 198,
3142 ANDI8_rec_ANDIS8_rec_RLWINM_RLWINM8_RLWINM8_rec_RLWINM_rec_RLWNM_RLWNM8_RLWNM8_rec_RLWNM_rec_SLW_SLW8_SLW8_rec_SLW_rec_SRW_SRW8_SRW8_rec_SRW_rec_ADDC8O_ADDC8O_rec_ADDCO_ADDCO_rec_ADDE8O_ADDE8O_rec_ADDEO_ADDEO_rec_ADDME8O_ADDME8O_rec_ADDMEO_ADDMEO_rec_ADDZE8O_ADDZE8O_rec_ADDZEO_ADDZEO_rec_SUBF8O_SUBF8O_rec_SUBFC8O_SUBFC8O_rec_SUBFCO_SUBFCO_rec_SUBFE8O_SUBFE8O_rec_SUBFEO_SUBFEO_rec_SUBFME8O_SUBFME8O_rec_SUBFMEO_SUBFMEO_rec_SUBFO_SUBFO_rec_SUBFZE8O_SUBFZE8O_rec_SUBFZEO_SUBFZEO_rec_ADDE8_rec_ADDE_rec_ADDME8_rec_ADDME_rec_ADDZE8_rec_ADDZE_rec_SUBFE8_rec_SUBFE_rec_SUBFME8_rec_SUBFME_rec_SUBFZE8_rec_SUBFZE_rec_ADDIC_rec_ADDC_ADDC8_SUBFC_SUBFC8_ADDC_rec_ADDC8_rec_SUBFC_rec_SUBFC8_rec = 199,
3143 ANDIS_rec_ANDI_rec_SUBF8_rec = 200,
3144 OR_OR8_OR8_rec_OR_rec_NOP = 201,
3145 SLDI_SLDI_rec_SLWI_SLWI_rec_SRDI_SRDI_rec_SRWI_SRWI_rec_COPY = 202,
3146 SUBF_rec_ADDG6S_ADDG6S8_ADDZE_ADDZE8 = 203,
3147 RLWIMI8_rec_RLWIMI_rec = 204,
3148 CNTLZD_CNTLZD_rec_CNTLZW_CNTLZW8_CNTLZW8_rec_CNTLZW_rec = 205,
3149 POPCNTB_POPCNTB8_POPCNTD_POPCNTW = 206,
3150 ISEL_ISEL8 = 207,
3151 MFTB_MFTB8 = 208,
3152 DIVW_DIVWU = 209,
3153 DIVD_DIVDU = 210,
3154 DIVWE_DIVWEU = 211,
3155 LVEBX_LVEHX_LVEWX_LVX_LVXL = 212,
3156 LXVB16X_LXSIWZX = 213,
3157 DFLOADf64_XFLOADf64_LIWZX = 214,
3158 LQ = 215,
3159 STFDEPX_STFDXTLS_STFDXTLS__STFSXTLS_STFSXTLS__STXSIWX_STXSSP_STXSSPX = 216,
3160 STBXTLS_STBXTLS__STBXTLS_32_STHXTLS_STHXTLS__STHXTLS_32_STWXTLS_STWXTLS__STWXTLS_32_STBEPX_STDBRX_STHEPX_STWEPX = 217,
3161 STDXTLS_STDXTLS_ = 218,
3162 STBCIX_STDCIX = 219,
3163 STBCX_STHCX = 220,
3164 STHCIX_STSWI_STWCIX = 221,
3165 LBZ_LBZ8_LBZX_LBZX8_LBZXTLS_LBZXTLS__LBZXTLS_32_LHAXTLS_LHAXTLS__LHAXTLS_32_LHZ_LHZ8_LHZX_LHZX8_LHZXTLS_LHZXTLS__LHZXTLS_32_LWAXTLS_LWAXTLS__LWAXTLS_32_LWZ_LWZ8_LWZX_LWZX8_LWZXTLS_LWZXTLS__LWZXTLS_32 = 222,
3166 LD_LDX_LDXTLS_LDXTLS_ = 223,
3167 LBARXL_LHARXL = 224,
3168 LBEPX_LHEPX_LWEPX = 225,
3169 LFDEPX_LXSIWAX = 226,
3170 ADDIdtprelL_ADDIdtprelL32_ADDItlsgdL_ADDItlsgdL32_ADDItlsgdLADDR_ADDItlsgdLADDR32_ADDItoc_ADDItoc8_ADDItocL_ADDItocL8_ADDISdtprelHA_ADDISdtprelHA32_ADDISgotTprelHA_ADDIStlsgdHA_ADDIStocHA_ADDIStocHA8 = 227,
3171 SUBF = 228,
3172 VPKSDSS_VPKSDUS_VPKUDUM_VPKUDUS_VUPKHSW_VUPKLSW_VMRGEW_VMRGOW_VPERMXOR_VBPERMQ_VGBBD = 229,
3173 VMRGHB_VMRGHH_VMRGHW_VMRGLB_VMRGLH_VMRGLW_VSL_VSLDOI_VSLO_VSR_VSRO = 230,
3174 VADDSBS_VADDSHS_VADDSWS_VADDUBS_VADDUHS_VADDUWS_VSUBSBS_VSUBSHS_VSUBSWS_VSUBUBS_VSUBUHS_VSUBUWS_VRLB_VRLH_VRLW_VSLB_VSLH_VSLW_VSRAB_VSRAH_VSRAW_VSRB_VSRH_VSRW_VAVGSB_VAVGSH_VAVGSW_VAVGUB_VAVGUH_VAVGUW_VMAXSB_VMAXSH_VMAXSW_VMAXUB_VMAXUH_VMAXUW_VMINSB_VMINSH_VMINSW_VMINUB_VMINUH_VMINUW_VAND_VANDC_VNOR_VOR_VXOR_VMAXFP_VMINFP_VSUBCUW_VADDCUW = 231,
3175 VADDUDM_VSUBUDM_VSLD_VSRAD_VSRD_VEQV_VNAND_VORC_XXLEQV_XXLNAND_XXLORC_VCLZB_VCLZD_VCLZH_VCLZW_VPOPCNTB_VPOPCNTH_VPOPCNTW = 232,
3176 VRLD_VMAXSD_VMAXUD_VMINSD_VMINUD_VSHASIGMAD_VSHASIGMAW = 233,
3177 VCMPEQUD_VCMPEQUD_rec_VCMPGTSD_VCMPGTSD_rec_VCMPGTUD_VCMPGTUD_rec = 234,
3178 MFVSCR = 235,
3179 MTVSCR = 236,
3180 VADDCUQ_VADDECUQ_VADDEUQM_VSUBCUQ_VSUBECUQ_VSUBEUQM = 237,
3181 VADDUQM_VSUBUQM_VPOPCNTD = 238,
3182 VMSUMMBM_VMSUMSHM_VMSUMSHS_VMSUMUBM_VMSUMUHM_VMSUMUHS_VSUM2SWS_VSUM4SBS_VSUM4SHS_VSUM4UBS_VSUMSWS_VMULESB_VMULESH_VMULEUB_VMULEUH_VMULOSB_VMULOSH_VMULOUB_VMULOUH_VMHADDSHS_VMHRADDSHS_VMLADDUHM = 239,
3183 VMULESW_VMULEUW_VMULOSW_VMULOUW = 240,
3184 VMULUWM = 241,
3185 B_BA_BL_BL8_BL8_RM_BLA_BLA8_BLA8_RM_BLA_RM_BL_RM_BL8_NOP_BL8_NOP_RM_BL8_NOP_TLS_BL8_TLS_BL8_TLS__BLA8_NOP_BLA8_NOP_RM_BL_NOP_BL_NOP_RM_BL_TLS = 242,
3186 DTSTDC_DTSTDCQ_DTSTDG_DTSTDGQ_DTSTSF_DTSTSFQ_DCMPO_DCMPU_DTSTEX = 243,
3187 DXEX_DXEXQ_DXEXQ_rec_DXEX_rec_DDEDPD_DDEDPD_rec_DENBCD_DENBCD_rec_DIEX_DIEX_rec_DQUA_DQUA_rec_DRINTN_DRINTN_rec_DRINTX_DRINTX_rec_DRRND_DRRND_rec_DSCLI_DSCLI_rec_DSCRI_DSCRI_rec_DQUAI = 244,
3188 DADD_DADD_rec_DCTDP_DCTDP_rec_DSUB_DSUB_rec = 245,
3189 BCDADD_rec_BCDSUB_rec = 246,
3190 DRINTNQ_DRINTNQ_rec_DRINTXQ_DRINTXQ_rec_DRRNDQ_DRRNDQ_rec_DIEXQ_DIEXQ_rec_DQUAIQ_DQUAIQ_rec_DDEDPDQ_DDEDPDQ_rec_DENBCDQ_DENBCDQ_rec_DSCLIQ_DSCLIQ_rec_DSCRIQ_DSCRIQ_rec = 247,
3191 DCMPOQ_DCMPUQ_DTSTEXQ = 248,
3192 DCTQPQ_DCTQPQ_rec = 249,
3193 DADDQ_DADDQ_rec_DSUBQ_DSUBQ_rec = 250,
3194 DQUAQ_DQUAQ_rec = 251,
3195 DRSP_DRSP_rec_DCTFIX_DCTFIX_rec = 252,
3196 DCFFIX_DCFFIX_rec = 253,
3197 DCFFIXQ_DCFFIXQ_rec = 254,
3198 DMUL_DMUL_rec = 255,
3199 DMULQ_DMULQ_rec = 256,
3200 DDIV_DDIV_rec = 257,
3201 DDIVQ_DDIVQ_rec = 258,
3202 MFVRD_MFVSRD_MFVRWZ_MFVSRWZ_MTVRD_MTVSRD_MTVRWA_MTVSRWA_MTVRWZ_MTVSRWZ = 259,
3203 VADDUDM_VSLD_VSRD_VSUBUDM_VPOPCNTB_VPOPCNTH_VSRAD_VEQV_VNAND_VORC_XXLEQV_XXLNAND_XXLORC = 260,
3204 VAND_VANDC_VSLB_VSLH_VSLW_VSRB_VSRH_VSRW_VRLB_VRLH_VRLW_VSRAB_VSRAH_VSRAW_VNOR_VOR_VXOR = 261,
3205 VEXTSB2D_VEXTSB2Ds_VEXTSB2W_VEXTSB2Ws_VEXTSH2D_VEXTSH2Ds_VEXTSH2W_VEXTSH2Ws_VEXTSW2D_VEXTSW2Ds_MTVSRDD_VNEGD_VNEGW_XXLEQVOnes = 262,
3206 V_SET0_V_SET0B_V_SET0H_XVIEXPDP_XVIEXPSP_XVXEXPDP_XVXEXPSP_VRLDMI_VRLDNM_VRLWMI_VRLWNM_XSABSQP_XSCPSGNQP_XSIEXPQP_XSNABSQP_XSNEGQP_XSXEXPQP = 263,
3207 VRLD = 264,
3208 XVABSDP_XVNABSDP_XVCPSGNDP_XVNEGDP = 265,
3209 XVABSSP_XVNABSSP_XVNEGSP = 266,
3210 XVCPSGNSP = 267,
3211 VMRGEW_VMRGOW = 268,
3212 VSEL = 269,
3213 XXSEL = 270,
3214 TABORTDC_TABORTDCI_TABORTWC_TABORTWCI = 271,
3215 MTFSB0_MTFSB1 = 272,
3216 MFFSCDRN_MFFSCDRNI_MFFSCRN_MFFSCRNI = 273,
3217 CMPRB_CMPRB8_CMPEQB = 274,
3218 XSTSTDCDP_XSTSTDCSP = 275,
3219 FTDIV_FTSQRT = 276,
3220 XSMAXCDP_XSMAXJDP_XSMINCDP_XSMINJDP_XSXSIGDP = 277,
3221 XSCMPEQDP_XSCMPEXPDP_XSCMPGEDP_XSCMPGTDP = 278,
3222 CNTTZD_CNTTZD_rec_CNTTZW_CNTTZW8_CNTTZW8_rec_CNTTZW_rec = 279,
3223 POPCNTD_POPCNTW = 280,
3224 CMPB_CMPB8_SETB_SETB8_BPERMD = 281,
3225 XSCVSPDPN = 282,
3226 SLD_SRD_SRAD = 283,
3227 SRADI_SRADI_32_RLDIC = 284,
3228 EXTSWSLI_32_64_EXTSWSLI = 285,
3229 SUBFC_SUBFC8_SUBFC8O_SUBFCO_ANDI8_rec_ANDIS8_rec_ADDC_ADDC8_ADDC8O_ADDCO_ADDIC_rec_ADDE8O_ADDE8O_rec_ADDE8_rec_ADDEO_ADDEO_rec_ADDE_rec_ADDME8O_ADDME8O_rec_ADDME8_rec_ADDMEO_ADDMEO_rec_ADDME_rec_ADDZE8O_ADDZE8O_rec_ADDZE8_rec_ADDZEO_ADDZEO_rec_ADDZE_rec_SUBF8O_SUBF8O_rec_SUBFE8O_SUBFE8O_rec_SUBFE8_rec_SUBFEO_SUBFEO_rec_SUBFE_rec_SUBFME8O_SUBFME8O_rec_SUBFME8_rec_SUBFMEO_SUBFMEO_rec_SUBFME_rec_SUBFO_SUBFO_rec_SUBFZE8O_SUBFZE8O_rec_SUBFZE8_rec_SUBFZEO_SUBFZEO_rec_SUBFZE_rec = 286,
3230 ADDZE_ADDZE8_SUBF_rec = 287,
3231 ADDIStocHA_ADDIStocHA8_ADDItocL_ADDItocL8 = 288,
3232 LA_LA8 = 289,
3233 COPY = 290,
3234 MCRXRX = 291,
3235 XSNABSDP_XSNABSDPs_XSABSDP_XSNEGDP_XSCPSGNDP = 292,
3236 XSXEXPDP = 293,
3237 RFEBB = 294,
3238 TBEGIN_TRECHKPT = 295,
3239 WAIT = 296,
3240 RLDCL_RLDCR = 297,
3241 RLDICL_RLDICL_32_RLDICL_32_64_RLDICR_RLDICR_32_RLDIMI = 298,
3242 MTOCRF_MTOCRF8 = 299,
3243 SLW_SLW8_SRW_SRW8_RLWINM_RLWINM8_RLWNM_RLWNM8 = 300,
3244 FABSD_FABSS_FNABSD_FNABSS_FNEGD_FNEGS_FCPSGND_FCPSGNS_FMR = 301,
3245 SRAW_SRAW8_SRAWI_SRAWI8 = 302,
3246 XSIEXPDP = 303,
3247 CRXOR = 304,
3248 TRECLAIM_TSR_TABORT = 305,
3249 VCMPNEZB_VCMPNEZH_VCMPNEZW_VCMPNEB_VCMPNEH_VCMPNEW_VCMPNEB_rec_VCMPNEH_rec_VCMPNEW_rec_VCMPNEZB_rec_VCMPNEZH_rec_VCMPNEZW_rec = 306,
3250 VABSDUB_VABSDUH_VABSDUW_VCTZB_VCTZD_VCTZH_VCTZW_VPRTYBD_VPRTYBW = 307,
3251 VBPERMD_XVTSTDCDP_XVTSTDCSP_XVXSIGDP_XVXSIGSP = 308,
3252 VPOPCNTD = 309,
3253 VCTSXS_0_VCTUXS_0_XVCVHPSP_XVCVSPHP_VCFSX_0_VCFUX_0 = 310,
3254 MADDHD_MADDHDU_MADDLD_MADDLD8 = 311,
3255 MULHD_MULHW_MULLW_MULLWO = 312,
3256 MULHDU_MULHWU = 313,
3257 MULLD_MULLDO = 314,
3258 FRSP_FRIMD_FRIMS_FRIND_FRINS_FRIPD_FRIPS_FRIZD_FRIZS_FRE_FRES_FADDS_FMSUBS_FMADDS_FSUBS_FCFID_FCFIDS_FCFIDU_FCFIDUS_FCTID_FCTIDU_FCTIDUZ_FCTIDZ_FCTIW_FCTIWU_FCTIWUZ_FCTIWZ_FRSQRTE_FRSQRTES_FNMADDS_FNMSUBS_FSELD_FSELS_FMULS = 315,
3259 FADD_FSUB = 316,
3260 FMSUB_FMADD_FNMADD_FNMSUB_FMUL = 317,
3261 XSMADDADP_XSMADDASP_XSMADDMDP_XSMADDMSP_XSMSUBADP_XSMSUBASP_XSMSUBMDP_XSMSUBMSP_XSMULDP_XSMULSP_XSNMADDADP_XSNMADDASP_XSNMADDMDP_XSNMADDMSP_XSNMSUBADP_XSNMSUBASP_XSNMSUBMDP_XSNMSUBMSP = 318,
3262 FSELD_rec_FSELS_rec = 319,
3263 FRIMD_rec_FRIMS_rec_FRIND_rec_FRINS_rec_FRIPD_rec_FRIPS_rec_FRIZD_rec_FRIZS_rec_FRES_rec_FRE_rec_FADDS_rec_FSUBS_rec_FMSUBS_rec_FNMSUBS_rec_FMADDS_rec_FNMADDS_rec_FCFIDS_rec_FCFIDUS_rec_FCFIDU_rec_FCFID_rec_FCTIDUZ_rec_FCTIDU_rec_FCTIDZ_rec_FCTID_rec_FCTIWUZ_rec_FCTIWU_rec_FCTIWZ_rec_FCTIW_rec_FMULS_rec_FRSQRTES_rec_FRSQRTE_rec_FRSP_rec = 320,
3264 XSCVDPHP_XSCVHPDP = 321,
3265 LVSL_LVSR = 322,
3266 V_SETALLONES_V_SETALLONESB_V_SETALLONESH_VPERMR_VSLV_VSRV_XXBRD_XXBRH_XXBRQ_XXBRW_XXEXTRACTUW_XXINSERTW_VMUL10CUQ_VMUL10ECUQ_VMUL10EUQ_VMUL10UQ_XSTSTDCQP_XSXSIGQP_BCDCFN_rec_BCDCFZ_rec_BCDCPSGN_rec_BCDCTN_rec_BCDCTZ_rec_BCDSETSGN_rec_BCDS_rec_BCDTRUNC_rec_BCDUS_rec_BCDUTRUNC_rec = 323,
3267 VEXTRACTUB_VEXTRACTUH_VEXTRACTUW_VINSERTB_VINSERTD_VINSERTH_VINSERTW_MFVSRLD_MTVSRWS_VCLZLSBB_VCTZLSBB_VEXTRACTD_VEXTUBLX_VEXTUBRX_VEXTUHLX_VEXTUHRX_VEXTUWLX_VEXTUWRX_VPRTYBQ = 324,
3268 XXPERM_XXPERMR_XXSPLTIB = 325,
3269 XSCMPEXPQP_XSCMPOQP_XSCMPUQP = 326,
3270 BCDSR_rec_XSADDQP_XSADDQPO_XSCVDPQP_XSCVQPDP_XSCVQPDPO_XSCVQPSDZ_XSCVQPSWZ_XSCVQPUDZ_XSCVQPUWZ_XSCVSDQP_XSCVUDQP_XSRQPI_XSRQPIX_XSRQPXP_XSSUBQP_XSSUBQPO = 327,
3271 BCDCTSQ_rec = 328,
3272 XSMADDQP_XSMADDQPO_XSMSUBQP_XSMSUBQPO_XSMULQP_XSMULQPO_XSNMADDQP_XSNMADDQPO_XSNMSUBQP_XSNMSUBQPO = 329,
3273 BCDCFSQ_rec = 330,
3274 XSDIVQP_XSDIVQPO = 331,
3275 XSSQRTQP_XSSQRTQPO = 332,
3276 LXVL_LXVLL = 333,
3277 LXSIBZX_LXSIHZX_LXVWSX_LXV_LXVX_LXSD = 334,
3278 LXSDX_LXVD2X = 335,
3279 DCBF_DCBFEP_DCBST_DCBSTEP_DCBT_DCBTEP_DCBZ_DCBZEP_DCBZL_DCBZLEP_DCBTST_DCBTSTEP = 336,
3280 CP_COPY_CP_COPY8 = 337,
3281 ICBI_ICBIEP = 338,
3282 ICBT_ICBTLS_EnforceIEIO = 339,
3283 LBZ_LBZ8_LBZX_LBZX8_LBZXTLS_LBZXTLS__LBZXTLS_32_LHZ_LHZ8_LHZX_LHZX8_LHZXTLS_LHZXTLS__LHZXTLS_32_LWZ_LWZ8_LWZX_LWZX8_LWZXTLS_LWZXTLS__LWZXTLS_32 = 340,
3284 CP_ABORT = 341,
3285 DARN = 342,
3286 ISYNC = 343,
3287 MSGSYNC = 344,
3288 TLBSYNC = 345,
3289 SYNC = 346,
3290 LFIWZX = 347,
3291 LFDX_LFDXTLS_LFDXTLS__LFD = 348,
3292 SLBIA = 349,
3293 SLBIE = 350,
3294 SLBMFEE = 351,
3295 SLBMFEV = 352,
3296 SLBMTE = 353,
3297 TLBIEL = 354,
3298 LHZU_LHZU8_LWZU_LWZU8 = 355,
3299 LHZUX_LHZUX8_LWZUX_LWZUX8 = 356,
3300 TEND = 357,
3301 CP_PASTE8_rec_CP_PASTE_rec = 358,
3302 TCHECK = 359,
3303 LXSIWAX = 360,
3304 LIWAX = 361,
3305 LFSX_LFSXTLS_LFSXTLS__LFS = 362,
3306 LXSSP_LXSSPX = 363,
3307 XFLOADf32_DFLOADf32 = 364,
3308 LXVH8X = 365,
3309 STFDXTLS_STFDXTLS__STFSXTLS_STFSXTLS__STXSIWX_STXSSP_STXSSPX = 366,
3310 STXSD_STXSIBX_STXSIBXv_STXSIHX_STXSIHXv = 367,
3311 STXSDX = 368,
3312 DFSTOREf32_DFSTOREf64_XFSTOREf32_XFSTOREf64_STIWX = 369,
3313 STDBRX_STBXTLS_STBXTLS__STBXTLS_32_STHXTLS_STHXTLS__STHXTLS_32_STWXTLS_STWXTLS__STWXTLS_32 = 370,
3314 SLBIEG = 371,
3315 TLBIE = 372,
3316 STXV_STXVB16X_STXVH8X_STXVX = 373,
3317 STXVL_STXVLL = 374,
3318 MFVRSAVE_MFVRSAVEv_MTVRSAVE_MTVRSAVEv = 375,
3319 MFPMR = 376,
3320 MTPMR = 377,
3321 MFSPR_MFSPR8_MFUDSCR = 378,
3322 MFMSR = 379,
3323 MTMSR = 380,
3324 MTMSRD = 381,
3325 MTUDSCR_MTSPR_MTSPR8 = 382,
3326 DIVWO_DIVWUO = 383,
3327 MODSW = 384,
3328 DIVWEO_DIVWEUO = 385,
3329 DIVDO_DIVDUO = 386,
3330 MODSD_MODUD_MODUW = 387,
3331 DIVDE_DIVDEO_DIVDEU_DIVDEUO = 388,
3332 DIVWO_rec_DIVWUO_rec_DIVWU_rec_DIVW_rec = 389,
3333 ADDC8O_rec_ADDC8_rec_ADDCO_rec_ADDC_rec_SUBFC8O_rec_SUBFC8_rec_SUBFCO_rec_SUBFC_rec = 390,
3334 MCRFS = 391,
3335 RLDCL_rec_RLDCR_rec = 392,
3336 RLDICL_rec_RLDICR_rec_RLDICL_32_rec_RLDIMI_rec = 393,
3337 MFFS_MFFSCE_MFFSL_MFFS_rec = 394,
3338 EXTSWSLI_32_64_rec_EXTSWSLI_rec = 395,
3339 FDIV = 396,
3340 FSQRT = 397,
3341 FSQRTS = 398,
3342 FDIVS = 399,
3343 LFSU = 400,
3344 LFSUX = 401,
3345 TAILB_TAILB8_TAILBA_TAILBA8_TAILBCTR_TAILBCTR8_CTRL_DEP = 402,
3346 LDAT_LWAT = 403,
3347 STDAT_STWAT = 404,
3348 BRINC = 405,
3349 EVABS_EVEQV_EVNAND_EVNEG_EVADDIW_EVADDW_EVAND_EVANDC_EVCMPEQ_EVCMPGTS_EVCMPGTU_EVCMPLTS_EVCMPLTU_EVCNTLSW_EVCNTLZW_EVEXTSB_EVEXTSH_EVMERGEHI_EVMERGEHILO_EVMERGELO_EVMERGELOHI_EVNOR_EVOR_EVORC_EVXOR_EVRLW_EVRLWI_EVRNDW_EVSLW_EVSLWI_EVSPLATFI_EVSPLATI_EVSRWIS_EVSRWIU_EVSRWS_EVSRWU_EVSUBFW_EVSUBIFW = 406,
3350 EVMRA_EVADDSMIAAW_EVADDSSIAAW_EVADDUMIAAW_EVADDUSIAAW_EVDIVWS_EVDIVWU_EVMHEGSMFAA_EVMHEGSMFAN_EVMHEGSMIAA_EVMHEGSMIAN_EVMHEGUMIAA_EVMHEGUMIAN_EVMHESMF_EVMHESMFA_EVMHESMFAAW_EVMHESMFANW_EVMHESMI_EVMHESMIA_EVMHESMIAAW_EVMHESMIANW_EVMHESSF_EVMHESSFA_EVMHESSFAAW_EVMHESSFANW_EVMHESSIAAW_EVMHESSIANW_EVMHEUMI_EVMHEUMIA_EVMHEUMIAAW_EVMHEUMIANW_EVMHEUSIAAW_EVMHEUSIANW_EVMHOGSMFAA_EVMHOGSMFAN_EVMHOGSMIAA_EVMHOGSMIAN_EVMHOGUMIAA_EVMHOGUMIAN_EVMHOSMF_EVMHOSMFA_EVMHOSMFAAW_EVMHOSMFANW_EVMHOSMI_EVMHOSMIA_EVMHOSMIAAW_EVMHOSMIANW_EVMHOSSF_EVMHOSSFA_EVMHOSSFAAW_EVMHOSSFANW_EVMHOSSIAAW_EVMHOSSIANW_EVMHOUMI_EVMHOUMIA_EVMHOUMIAAW_EVMHOUMIANW_EVMHOUSIAAW_EVMHOUSIANW_EVMWHSMF_EVMWHSMFA_EVMWHSMI_EVMWHSMIA_EVMWHSSF_EVMWHSSFA_EVMWHUMI_EVMWHUMIA_EVMWLSMIAAW_EVMWLSMIANW_EVMWLSSIAAW_EVMWLSSIANW_EVMWLUMI_EVMWLUMIA_EVMWLUMIAAW_EVMWLUMIANW_EVMWLUSIAAW_EVMWLUSIANW_EVMWSMF_EVMWSMFA_EVMWSMFAA_EVMWSMFAN_EVMWSMI_EVMWSMIA_EVMWSMIAA_EVMWSMIAN_EVMWSSF_EVMWSSFA_EVMWSSFAA_EVMWSSFAN_EVMWUMI_EVMWUMIA_EVMWUMIAA_EVMWUMIAN_EVSUBFSMIAAW_EVSUBFSSIAAW_EVSUBFUMIAAW_EVSUBFUSIAAW = 407,
3351 EVLDD_EVLDDX_EVLDH_EVLDHX_EVLDW_EVLDWX_EVLHHESPLAT_EVLHHESPLATX_EVLHHOSSPLAT_EVLHHOSSPLATX_EVLHHOUSPLAT_EVLHHOUSPLATX_EVLWHE_EVLWHEX_EVLWHOS_EVLWHOSX_EVLWHOU_EVLWHOUX_EVLWHSPLAT_EVLWHSPLATX_EVLWWSPLAT_EVLWWSPLATX = 408,
3352 EVSTDD_EVSTDDX_EVSTDH_EVSTDHX_EVSTDW_EVSTDWX_EVSTWHE_EVSTWHEX_EVSTWHO_EVSTWHOX_EVSTWWE_EVSTWWEX_EVSTWWO_EVSTWWOX = 409,
3353 HRFID_ATTN_CLRBHRB_MFBHRBE_NAP_RFCI_RFDI_RFMCI_SC = 410,
3354 RFI = 411,
3355 RFID = 412,
3356 DSS_DSSALL_DST_DST64_DSTST_DSTST64_DSTSTT_DSTSTT64_DSTT_DSTT64_ICBLQ_TLBIVAX_TLBLD_TLBLI_TLBRE_TLBRE2_TLBSX_TLBSX2_TLBSX2D_TLBWE_TLBWE2_MBAR_TRAP_DCCCI_ICCCI = 413,
3357 ICBLC = 414,
3358 MTSR_MTSRIN = 415,
3359 MFDCR = 416,
3360 MTDCR = 417,
3361 NOP_GT_PWR6_NOP_GT_PWR7 = 418,
3362 TLBIA = 419,
3363 WRTEE_WRTEEI = 420,
3364 HASHCHK_HASHCHK8_HASHCHKP_HASHCHKP8_HASHST_HASHST8_HASHSTP_HASHSTP8_ADDEX_ADDEX8_CDTBCD_CDTBCD8_CBCDTD_CBCDTD8 = 421,
3365 MSYNC = 422,
3366 SLBSYNC = 423,
3367 SLBFEE_rec = 424,
3368 STOP = 425,
3369 DCBA_DCBI = 426,
3370 FCFID_FCFIDS_FCFIDU_FCFIDUS_FCTID_FCTIDU_FCTIDUZ_FCTIDZ_FCTIW_FCTIWU_FCTIWUZ_FCTIWZ_FRE_FRES_FRIMD_FRIMS_FRIND_FRINS_FRIPD_FRIPS_FRIZD_FRIZS_FRSP_FRSQRTE_FRSQRTES = 427,
3371 VCFSX_VCFUX_VCTSXS_VCTUXS = 428,
3372 VCFSX_0_VCFUX_0_VCTSXS_0_VCTUXS_0_XVCVSPHP = 429,
3373 VLOGEFP_VREFP_VRFIM_VRFIN_VRFIP_VRFIZ_VRSQRTEFP_XVCVDPSP_XVCVSXDSP_XVCVSXWSP_XVCVUXDSP_XVCVUXWSP_XVRESP_XVRSQRTESP = 430,
3374 XSCVDPHP = 431,
3375 XSCVDPSP_XSCVDPSXDS_XSCVDPSXDSs_XSCVDPSXWS_XSCVDPSXWSs_XSCVDPUXDS_XSCVDPUXDSs_XSCVDPUXWS_XSCVDPUXWSs_XSCVSPDP_XSCVSXDDP_XSCVUXDDP_XSRDPI_XSRDPIC_XSRDPIM_XSRDPIP_XSRDPIZ_XSREDP_XSRSQRTEDP = 432,
3376 XVCVDPSXDS_XVCVDPSXWS_XVCVDPUXDS_XVCVDPUXWS_XVCVSPSXDS_XVCVSPSXWS_XVCVSPUXDS_XVCVSPUXWS_XVCVSXDDP_XVCVSXWDP_XVCVUXDDP_XVCVUXWDP_XVRDPI_XVRDPIC_XVRDPIM_XVRDPIP_XVRDPIZ_XVREDP_XVRSPI_XVRSPIC_XVRSPIM_XVRSPIP_XVRSPIZ_XVRSQRTEDP = 433,
3377 XVCVSPBF16 = 434,
3378 FADDS_FMULS_FSUBS = 435,
3379 FMUL = 436,
3380 VADDFP = 437,
3381 XSMULDP_XSMULSP = 438,
3382 XVADDDP_XVMULDP_XVSUBDP = 439,
3383 XVADDSP_XVMULSP_XVSUBSP = 440,
3384 VMADDFP_VNMSUBFP = 441,
3385 FADDS_rec_FMULS_rec_FSUBS_rec = 442,
3386 FMUL_rec = 443,
3387 FCFID_rec_FCFIDS_rec_FCFIDU_rec_FCFIDUS_rec_FCTID_rec_FCTIDU_rec_FCTIDUZ_rec_FCTIDZ_rec_FCTIW_rec_FCTIWU_rec_FCTIWUZ_rec_FCTIWZ_rec_FRE_rec_FRES_rec_FRIMD_rec_FRIMS_rec_FRIND_rec_FRINS_rec_FRIPD_rec_FRIPS_rec_FRIZD_rec_FRIZS_rec_FRSP_rec_FRSQRTE_rec_FRSQRTES_rec = 444,
3388 BCC_BCCA_BCCCTR_BCCCTR8_BCCCTRL_BCCCTRL8_BCCL_BCCLA_BCCLR_BCCLRL_BCCTR_BCCTR8_BCCTR8n_BCCTRn_gBCCTR_BCCTRL_BCCTRL8_BCCTRL8n_BCCTRLn_gBCCTRL_BCLR_BCLRn_BDNZLR_BDNZLR8_BDNZLRm_BDNZLRp_BDZLR_BDZLR8_BDZLRm_BDZLRp_gBCLR_BCLRL_BCLRLn_BDNZLRL_BDNZLRLm_BDNZLRLp_BDZLRL_BDZLRLm_BDZLRLp_gBCLRL_BLR_BLR8_BLRL = 445,
3389 CTRL_DEP_TAILB_TAILB8_TAILBA_TAILBA8 = 446,
3390 VGNB = 447,
3391 VSBOX = 448,
3392 CFUGED_PDEPD_PEXTD = 449,
3393 VCFUGED_VCLZDM_VCTZDM_VPDEPD_VPEXTD = 450,
3394 XSCVDPQP_XSCVQPDP_XSCVQPDPO_XSCVQPSDZ_XSCVQPSWZ_XSCVQPUDZ_XSCVQPUWZ_XSCVSDQP_XSCVUDQP_XSRQPI_XSRQPIX_XSRQPXP = 451,
3395 XSCVQPSQZ_XSCVQPUQZ_XSCVSQQP_XSCVUQQP = 452,
3396 HASHST_HASHST8_HASHSTP_HASHSTP8 = 453,
3397 XSMULQP_XSMULQPO = 454,
3398 VDIVESQ_VDIVEUQ_VDIVSQ_VDIVUQ = 455,
3399 VMODSQ_VMODUQ = 456,
3400 VDIVSD_VDIVUD = 457,
3401 VMODSD_VMODUD = 458,
3402 VDIVSW_VDIVUW = 459,
3403 VMODSW_VMODUW = 460,
3404 VDIVESD_VDIVEUD = 461,
3405 VDIVESW_VDIVEUW = 462,
3406 BCDCFN_rec_BCDCFZ_rec_BCDCTN_rec_BCDCTZ_rec_BCDSETSGN_rec_VMUL10CUQ_VMUL10UQ_XSTSTDCQP_XSXSIGQP = 463,
3407 XXGENPCVBM = 464,
3408 BCDCPSGN_rec_BCDS_rec_BCDTRUNC_rec_BCDUS_rec_BCDUTRUNC_rec_VMUL10ECUQ_VMUL10EUQ = 465,
3409 VADDCUQ_VSUBCUQ = 466,
3410 XSCMPEQQP_XSCMPGEQP_XSCMPGTQP_XSMAXCQP_XSMINCQP = 467,
3411 MTVSRBMI = 468,
3412 CBCDTD_CBCDTD8_CDTBCD_CDTBCD8 = 469,
3413 FTSQRT = 470,
3414 MTVSRBM_MTVSRDM_MTVSRHM_MTVSRQM_MTVSRWM_VCNTMBB_VCNTMBD_VCNTMBH_VCNTMBW_VEXPANDBM_VEXPANDDM_VEXPANDHM_VEXPANDQM_VEXPANDWM_VEXTRACTBM_VEXTRACTDM_VEXTRACTHM_VEXTRACTQM_VEXTRACTWM_XVTLSBB = 471,
3415 RLDIC_rec = 472,
3416 RLDICL_32_rec_RLDICL_rec_RLDICR_rec = 473,
3417 RLWINM8_rec_RLWINM_rec = 474,
3418 VCTZB_VCTZD_VCTZH_VCTZW_VPRTYBD_VPRTYBW = 475,
3419 VPOPCNTB_VPOPCNTH = 476,
3420 VSHASIGMAD_VSHASIGMAW = 477,
3421 XSTSQRTDP = 478,
3422 XVTSQRTDP = 479,
3423 XVTSQRTSP = 480,
3424 XVTSTDCDP_XVTSTDCSP = 481,
3425 SLD_rec_SRD_rec = 482,
3426 TDI = 483,
3427 TWI = 484,
3428 VADDCUW_VADDSBS_VADDSHS_VADDSWS_VADDUBS_VADDUHS_VADDUWS_VAVGSB_VAVGSH_VAVGSW_VAVGUB_VAVGUH_VAVGUW_VMAXFP_VMINFP_VSUBCUW_VSUBSBS_VSUBSHS_VSUBSWS_VSUBUBS_VSUBUHS_VSUBUWS = 485,
3429 VCMPBFP_VCMPBFP_rec_VCMPEQFP_VCMPEQFP_rec_VCMPEQUB_rec_VCMPEQUH_rec_VCMPEQUW_rec_VCMPGEFP_VCMPGEFP_rec_VCMPGTFP_VCMPGTFP_rec_VCMPGTSB_rec_VCMPGTSH_rec_VCMPGTSW_rec_VCMPGTUB_rec_VCMPGTUH_rec_VCMPGTUW_rec_XVCMPEQSP_XVCMPEQSP_rec_XVCMPGESP_XVCMPGESP_rec_XVCMPGTSP_XVCMPGTSP_rec = 486,
3430 VCMPEQUD_rec_VCMPGTSD_rec_VCMPGTUD_rec = 487,
3431 VCMPEQUQ_VCMPEQUQ_rec_VCMPGTSQ_VCMPGTSQ_rec_VCMPGTUQ_VCMPGTUQ_rec = 488,
3432 VCMPNEB_rec_VCMPNEH_rec_VCMPNEW_rec_VCMPNEZB_rec_VCMPNEZH_rec_VCMPNEZW_rec = 489,
3433 VCMPSQ_VCMPUQ = 490,
3434 XSMAXCDP_XSMAXJDP_XSMINCDP_XSMINJDP = 491,
3435 TRAP = 492,
3436 SRAWI_rec_SRAWI8_rec = 493,
3437 VRLQ_VRLQNM_VSLQ_VSRAQ_VSRQ = 494,
3438 VRLQMI = 495,
3439 DSS_DSSALL = 496,
3440 WAITP10 = 497,
3441 ADDI_ADDI8_LI_LI8_ADDIS_ADDIS8_LIS_LIS8_NEG_NEG8_NEG8O_NEGO = 498,
3442 ADDIdtprelL32_ADDISdtprelHA32 = 499,
3443 ADDItlsldLADDR32 = 500,
3444 ADDIC_ADDIC8_ADDME_ADDME8_SUBFIC_SUBFIC8_SUBFME_SUBFME8_SUBFZE_SUBFZE8 = 501,
3445 ADDME8O_ADDMEO_ADDZE8O_ADDZEO_ANDI8_rec_ANDIS8_rec_SUBFME8O_SUBFMEO_SUBFZE8O_SUBFZEO = 502,
3446 ADDZE_ADDZE8 = 503,
3447 ANDI_rec_ANDIS_rec = 504,
3448 CMPDI_CMPWI_CMPLDI_CMPLWI = 505,
3449 EXTSB_EXTSB8_EXTSB8_32_64_EXTSB8_rec_EXTSB_rec_EXTSH_EXTSH8_EXTSH8_32_64_EXTSH8_rec_EXTSH_rec_EXTSW_EXTSW_32_EXTSW_32_64_EXTSW_32_64_rec_EXTSW_rec = 506,
3450 FABSD_FABSS_FMR_FNABSD_FNABSS_FNEGD_FNEGS = 507,
3451 NEG8_rec_NEG_rec_ORI_ORI8_ORIS_ORIS8_XORI_XORI8_XORIS_XORIS8 = 508,
3452 NOP = 509,
3453 RLDICL_RLDICL_32_RLDICL_32_64_RLDICR_RLDICR_32 = 510,
3454 RLWINM_RLWINM8 = 511,
3455 SETB_SETB8 = 512,
3456 SETBC_SETBC8_SETBCR_SETBCR8_SETNBC_SETNBC8_SETNBCR_SETNBCR8 = 513,
3457 SRAWI_SRAWI8 = 514,
3458 VEXTSB2D_VEXTSB2Ds_VEXTSB2W_VEXTSB2Ws_VEXTSH2D_VEXTSH2Ds_VEXTSH2W_VEXTSH2Ws_VEXTSW2D_VEXTSW2Ds_VNEGD_VNEGW = 515,
3459 VEXTSD2Q = 516,
3460 XSABSDP_XSNABSDP_XSNABSDPs_XSNEGDP = 517,
3461 XSABSQP_XSNABSQP_XSNEGQP_XSXEXPQP_XVXEXPDP_XVXEXPSP = 518,
3462 XVABSDP_XVNABSDP_XVNEGDP = 519,
3463 XVXSIGDP_XVXSIGSP = 520,
3464 ADDE8O_ADDEO_SUBFE8O_SUBFEO_SUBF8O_SUBFO = 521,
3465 ADDEX_ADDEX8 = 522,
3466 ADD4O_ADD8O = 523,
3467 CMPB_CMPB8 = 524,
3468 CRAND_CRANDC_CR6SET_CREQV_CRSET_CRNAND_CRNOR_CROR_CRORC_CR6UNSET_CRUNSET = 525,
3469 DST_DST64_DSTT_DSTT64_DSTST_DSTST64_DSTSTT_DSTSTT64 = 526,
3470 VRLDNM_VRLWNM_V_SET0_V_SET0B_V_SET0H_XSCPSGNQP_XSIEXPQP_XVIEXPDP_XVIEXPSP = 527,
3471 XXLEQVOnes = 528,
3472 MFFS_MFFS_rec_MFFSL = 529,
3473 MFFSCDRNI_MFFSCRNI = 530,
3474 MTFSB0 = 531,
3475 ADDIC_rec_ADDME8_rec_ADDME_rec_ADDME8O_rec_ADDMEO_rec_ADDZE8_rec_ADDZE_rec_ADDZE8O_rec_ADDZEO_rec_SUBFME8_rec_SUBFME_rec_SUBFME8O_rec_SUBFMEO_rec_SUBFZE8_rec_SUBFZE_rec_SUBFZE8O_rec_SUBFZEO_rec = 532,
3476 NEG8O_rec_NEGO_rec = 533,
3477 ADDE8_rec_ADDE_rec_ADDE8O_rec_ADDEO_rec_SUBFE8_rec_SUBFE_rec_SUBFE8O_rec_SUBFEO_rec_SUBF8O_rec_SUBFO_rec = 534,
3478 HRFID_SC = 535,
3479 MTFSFI_MTFSFIb_MTFSFI_rec = 536,
3480 FABSD_rec_FABSS_rec_FMR_rec_FNABSD_rec_FNABSS_rec_FNEGD_rec_FNEGS_rec = 537,
3481 ADDC8_rec_ADDC_rec_SUBFC8_rec_SUBFC_rec = 538,
3482 VSTRIBL_rec_VSTRIBR_rec_VSTRIHL_rec_VSTRIHR_rec = 539,
3483 LBZ_LBZ8_LHZ_LHZ8_LWZ_LWZ8 = 540,
3484 LD = 541,
3485 LDtoc_LDtocBA_LDtocCPT_LDtocJTI_LDtocL_SPILLTOVSR_LD_LWZtoc_LWZtocL = 542,
3486 DFLOADf32 = 543,
3487 DFLOADf64 = 544,
3488 LFD = 545,
3489 LHA_LHA8 = 546,
3490 LXSD_LXV = 547,
3491 DCBT_DCBTST = 548,
3492 ICBT = 549,
3493 LDBRX = 550,
3494 SPILLTOVSR_LDX = 551,
3495 LXVRBX_LXVRDX_LXVRHX_LXVRWX = 552,
3496 MTSR = 553,
3497 MTVRSAVE_MTVRSAVEv = 554,
3498 LBZCIX_LDCIX_LHZCIX_LWZCIX = 555,
3499 PLBZ_PLBZ8_PLBZ8pc_PLBZpc_PLD_PLDpc_PLFD_PLFDpc_PLFS_PLFSpc_PLHA_PLHA8_PLHA8pc_PLHApc_PLHZ_PLHZ8_PLHZ8pc_PLHZpc_PLWA_PLWA8_PLWA8pc_PLWApc_PLWZ_PLWZ8_PLWZ8pc_PLWZpc_PLXSD_PLXSDpc_PLXSSP_PLXSSPpc_PLXV_PLXVpc_PLXVP_PLXVPpc = 556,
3500 LFS = 557,
3501 LXSSP = 558,
3502 LXVP = 559,
3503 LXVPX = 560,
3504 MFSR = 561,
3505 MFTB8 = 562,
3506 XXSETACCZ = 563,
3507 XVBF16GER2_XVF16GER2_XVF32GER_XVF64GER_XVI16GER2_XVI16GER2S_XVI4GER8_XVI8GER4 = 564,
3508 XVBF16GER2NN_XVBF16GER2NP_XVBF16GER2PN_XVBF16GER2PP_XVF16GER2NN_XVF16GER2NP_XVF16GER2PN_XVF16GER2PP_XVF32GERNN_XVF32GERNP_XVF32GERPN_XVF32GERPP_XVF64GERNN_XVF64GERNP_XVF64GERPN_XVF64GERPP_XVI16GER2PP_XVI16GER2SPP_XVI4GER8PP_XVI8GER4PP = 565,
3509 XVI8GER4SPP = 566,
3510 PMXVBF16GER2_PMXVF16GER2_PMXVF32GER_PMXVF64GER_PMXVI16GER2_PMXVI16GER2S_PMXVI4GER8_PMXVI8GER4 = 567,
3511 PMXVBF16GER2NN_PMXVBF16GER2NP_PMXVBF16GER2PN_PMXVBF16GER2PP_PMXVF16GER2NN_PMXVF16GER2NP_PMXVF16GER2PN_PMXVF16GER2PP_PMXVF32GERNN_PMXVF32GERNP_PMXVF32GERPN_PMXVF32GERPP_PMXVF64GERNN_PMXVF64GERNP_PMXVF64GERPN_PMXVF64GERPP_PMXVI16GER2PP_PMXVI16GER2SPP_PMXVI4GER8PP_PMXVI8GER4PP = 568,
3512 PMXVI8GER4SPP = 569,
3513 XXMTACC = 570,
3514 XXMFACC = 571,
3515 VMULHSD_VMULHUD_VMULLD = 572,
3516 LXVKQ = 573,
3517 VSPLTISB_VSPLTISH_VSPLTISW = 574,
3518 V_SETALLONES_V_SETALLONESB_V_SETALLONESH = 575,
3519 XXSPLTIB = 576,
3520 BRD_BRH_BRH8_BRW_BRW8 = 577,
3521 MFVSRLD_MTVSRWS_VCLZLSBB_VCTZLSBB_VEXTRACTD_VEXTRACTUB_VEXTRACTUH_VEXTRACTUW_VINSERTD_VINSERTW_VPRTYBQ = 578,
3522 VGBBD_VUPKHSW_VUPKLSW = 579,
3523 VSPLTB_VSPLTBs_VSPLTH_VSPLTHs_VSPLTW_XXSPLTW_XXSPLTWs = 580,
3524 VSTRIBL_VSTRIBR_VSTRIHL_VSTRIHR_XXGENPCVDM_XXGENPCVHM_XXGENPCVWM = 581,
3525 VUPKHPX_VUPKHSB_VUPKHSH_VUPKLPX_VUPKLSB_VUPKLSH = 582,
3526 XVCVBF16SPN = 583,
3527 XXBRD_XXBRH_XXBRQ_XXBRW_XXEXTRACTUW = 584,
3528 VBPERMQ_VPKSDSS_VPKSDUS_VPKUDUM_VPKUDUS = 585,
3529 VCLRLB_VCLRRB_VINSD_VINSW_VSLDBI_VSRDBI = 586,
3530 VPKPX_VPKSHSS_VPKSHUS_VPKSWSS_VPKSWUS_VPKUHUM_VPKUHUS_VPKUWUM_VPKUWUS = 587,
3531 VSLV_VSRV_XXINSERTW = 588,
3532 VEXTDDVLX_VEXTDDVRX_VEXTDUBVLX_VEXTDUBVRX_VEXTDUHVLX_VEXTDUHVRX_VEXTDUWVLX_VEXTDUWVRX_VINSBLX_VINSBRX_VINSBVLX_VINSBVRX_VINSDLX_VINSDRX_VINSHLX_VINSHRX_VINSHVLX_VINSHVRX_VINSWLX_VINSWRX_VINSWVLX_VINSWVRX = 589,
3533 VSUMSWS = 590,
3534 XXSPLTIDP_XXSPLTIW = 591,
3535 XXSPLTI32DX = 592,
3536 XXBLENDVB_XXBLENDVD_XXBLENDVH_XXBLENDVW_XXEVAL = 593,
3537 XXPERMX = 594,
3538 PSTXVP_PSTXVPpc = 595,
3539 STB_STB8_STH_STH8_STW_STW8 = 596,
3540 SPILLTOVSR_ST = 597,
3541 STD = 598,
3542 DFSTOREf32_DFSTOREf64 = 599,
3543 STFD_STFS = 600,
3544 STFDU_STFSU = 601,
3545 STXSD = 602,
3546 STXSSP = 603,
3547 STXV = 604,
3548 DCBF_DCBST_DCBZ = 605,
3549 ICBI = 606,
3550 SPILLTOVSR_STX = 607,
3551 STIWX = 608,
3552 STXVRBX_STXVRDX_STXVRHX_STXVRWX = 609,
3553 EnforceIEIO = 610,
3554 STHCIX_STWCIX = 611,
3555 SYNCP10 = 612,
3556 PSTB_PSTB8_PSTB8pc_PSTBpc_PSTD_PSTDpc_PSTFD_PSTFDpc_PSTFS_PSTFSpc_PSTH_PSTH8_PSTH8pc_PSTHpc_PSTW_PSTW8_PSTW8pc_PSTWpc_PSTXSD_PSTXSDpc_PSTXSSP_PSTXSSPpc_PSTXV_PSTXVpc = 613,
3557 STXVP = 614,
3558 STXVPX = 615,
3559 ATTN_NAP = 616,
3560 DCBZL = 617,
3561 DCCCI_ICBLQ_ICCCI_TLBLD_TLBLI_TLBRE2_TLBSX2_TLBSX2D_TLBWE2 = 618,
3562 CLRBHRB_MFBHRBE = 619,
3563 PADDI_PADDI8_PADDI8pc_PADDIpc = 620,
3564 PLI_PLI8 = 621,
3565 VMULESB_VMULESH_VMULEUB_VMULEUH_VMULOSB_VMULOSH_VMULOUB_VMULOUH_VSUM2SWS_VSUM4SBS_VSUM4SHS_VSUM4UBS = 622,
3566 VMULESD_VMULEUD_VMULHSW_VMULHUW_VMULOSD_VMULOUD = 623,
3567 VMSUMCUD = 624,
3568 SCHED_LIST_END = 625
3569 };
3570} // end namespace llvm::PPC::Sched
3571#endif // GET_INSTRINFO_SCHED_ENUM
3572
3573#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
3574namespace llvm {
3575
3576struct PPCInstrTable {
3577 MCInstrDesc Insts[2919];
3578 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
3579 MCOperandInfo OperandInfo[1326];
3580 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
3581 MCPhysReg ImplicitOps[222];
3582};
3583
3584} // end namespace llvm
3585#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
3586
3587#ifdef GET_INSTRINFO_MC_DESC
3588#undef GET_INSTRINFO_MC_DESC
3589namespace llvm {
3590
3591static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
3592static constexpr unsigned PPCImpOpBase = sizeof PPCInstrTable::OperandInfo / (sizeof(MCPhysReg));
3593
3594extern const PPCInstrTable PPCDescs = {
3595 {
3596 { 2918, 4, 0, 4, 102, 2, 1, 1322, PPCImpOpBase + 109, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2918 = gBCat
3597 { 2917, 4, 0, 4, 102, 2, 2, 1322, PPCImpOpBase + 218, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2917 = gBCLat
3598 { 2916, 3, 0, 4, 445, 3, 2, 1319, PPCImpOpBase + 213, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2916 = gBCLRL
3599 { 2915, 3, 0, 4, 445, 3, 1, 1319, PPCImpOpBase + 112, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2915 = gBCLR
3600 { 2914, 4, 0, 4, 102, 2, 2, 1315, PPCImpOpBase + 218, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2914 = gBCLAat
3601 { 2913, 3, 0, 4, 102, 2, 2, 1312, PPCImpOpBase + 218, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2913 = gBCLA
3602 { 2912, 3, 0, 4, 102, 2, 2, 1309, PPCImpOpBase + 218, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2912 = gBCL
3603 { 2911, 3, 0, 4, 445, 3, 2, 1319, PPCImpOpBase + 213, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2911 = gBCCTRL
3604 { 2910, 3, 0, 4, 445, 3, 1, 1319, PPCImpOpBase + 112, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2910 = gBCCTR
3605 { 2909, 4, 0, 4, 102, 2, 1, 1315, PPCImpOpBase + 109, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2909 = gBCAat
3606 { 2908, 3, 0, 4, 102, 2, 1, 1312, PPCImpOpBase + 109, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2908 = gBCA
3607 { 2907, 3, 0, 4, 102, 2, 1, 1309, PPCImpOpBase + 109, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #2907 = gBC
3608 { 2906, 3, 1, 4, 580, 0, 0, 1298, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2906 = XXSPLTWs
3609 { 2905, 3, 1, 4, 580, 0, 0, 1306, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2905 = XXSPLTW
3610 { 2904, 2, 1, 8, 591, 0, 0, 651, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #2904 = XXSPLTIW
3611 { 2903, 2, 1, 8, 591, 0, 0, 651, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #2903 = XXSPLTIDP
3612 { 2902, 2, 1, 4, 576, 0, 0, 651, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2902 = XXSPLTIB
3613 { 2901, 4, 1, 8, 592, 0, 0, 1302, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #2901 = XXSPLTI32DX
3614 { 2900, 3, 1, 4, 165, 0, 0, 1298, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2900 = XXSLDWIs
3615 { 2899, 4, 1, 4, 165, 0, 0, 1294, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2899 = XXSLDWI
3616 { 2898, 1, 1, 4, 563, 0, 0, 1301, PPCImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2898 = XXSETACCZ
3617 { 2897, 4, 1, 4, 270, 0, 0, 1264, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2897 = XXSEL
3618 { 2896, 5, 1, 8, 594, 0, 0, 1268, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2896 = XXPERMX
3619 { 2895, 4, 1, 4, 325, 0, 0, 1290, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2895 = XXPERMR
3620 { 2894, 3, 1, 4, 165, 0, 0, 1298, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2894 = XXPERMDIs
3621 { 2893, 4, 1, 4, 165, 0, 0, 1294, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2893 = XXPERMDI
3622 { 2892, 4, 1, 4, 325, 0, 0, 1290, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2892 = XXPERM
3623 { 2891, 2, 1, 4, 19, 0, 0, 1288, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2891 = XXMTACCW
3624 { 2890, 2, 1, 4, 570, 0, 0, 1286, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2890 = XXMTACC
3625 { 2889, 3, 1, 4, 165, 0, 0, 1221, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2889 = XXMRGLW
3626 { 2888, 3, 1, 4, 165, 0, 0, 1221, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2888 = XXMRGHW
3627 { 2887, 2, 1, 4, 19, 0, 0, 1288, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2887 = XXMFACCW
3628 { 2886, 2, 1, 4, 571, 0, 0, 1286, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2886 = XXMFACC
3629 { 2885, 1, 1, 4, 167, 0, 0, 1283, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2885 = XXLXORz
3630 { 2884, 1, 1, 4, 167, 0, 0, 1285, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2884 = XXLXORspz
3631 { 2883, 1, 1, 4, 167, 0, 0, 1284, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2883 = XXLXORdpz
3632 { 2882, 3, 1, 4, 167, 0, 0, 1221, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2882 = XXLXOR
3633 { 2881, 3, 1, 4, 167, 0, 0, 1162, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2881 = XXLORf
3634 { 2880, 3, 1, 4, 260, 0, 0, 1221, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2880 = XXLORC
3635 { 2879, 3, 1, 4, 167, 0, 0, 1221, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2879 = XXLOR
3636 { 2878, 3, 1, 4, 167, 0, 0, 1221, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2878 = XXLNOR
3637 { 2877, 3, 1, 4, 260, 0, 0, 1221, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2877 = XXLNAND
3638 { 2876, 1, 1, 4, 528, 0, 0, 1283, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #2876 = XXLEQVOnes
3639 { 2875, 3, 1, 4, 260, 0, 0, 1221, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2875 = XXLEQV
3640 { 2874, 3, 1, 4, 167, 0, 0, 1221, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2874 = XXLANDC
3641 { 2873, 3, 1, 4, 167, 0, 0, 1221, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2873 = XXLAND
3642 { 2872, 4, 1, 4, 588, 0, 0, 1279, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2872 = XXINSERTW
3643 { 2871, 3, 1, 4, 581, 0, 0, 1276, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2871 = XXGENPCVWM
3644 { 2870, 3, 1, 4, 581, 0, 0, 1276, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2870 = XXGENPCVHM
3645 { 2869, 3, 1, 4, 581, 0, 0, 1276, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2869 = XXGENPCVDM
3646 { 2868, 3, 1, 4, 464, 0, 0, 1276, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2868 = XXGENPCVBM
3647 { 2867, 3, 1, 4, 584, 0, 0, 1273, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2867 = XXEXTRACTUW
3648 { 2866, 5, 1, 8, 593, 0, 0, 1268, PPCImpOpBase + 0, 0, 0x80ULL }, // Inst #2866 = XXEVAL
3649 { 2865, 2, 1, 4, 584, 0, 0, 1219, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2865 = XXBRW
3650 { 2864, 2, 1, 4, 584, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2864 = XXBRQ
3651 { 2863, 2, 1, 4, 584, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2863 = XXBRH
3652 { 2862, 2, 1, 4, 584, 0, 0, 1219, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2862 = XXBRD
3653 { 2861, 4, 1, 8, 593, 0, 0, 1264, PPCImpOpBase + 0, 0, 0x80ULL }, // Inst #2861 = XXBLENDVW
3654 { 2860, 4, 1, 8, 593, 0, 0, 1264, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2860 = XXBLENDVH
3655 { 2859, 4, 1, 8, 593, 0, 0, 1264, PPCImpOpBase + 0, 0, 0x80ULL }, // Inst #2859 = XXBLENDVD
3656 { 2858, 4, 1, 8, 593, 0, 0, 1264, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #2858 = XXBLENDVB
3657 { 2857, 2, 1, 4, 520, 0, 0, 1219, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2857 = XVXSIGSP
3658 { 2856, 2, 1, 4, 520, 0, 0, 1219, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2856 = XVXSIGDP
3659 { 2855, 2, 1, 4, 518, 0, 0, 1219, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2855 = XVXEXPSP
3660 { 2854, 2, 1, 4, 518, 0, 0, 1219, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2854 = XVXEXPDP
3661 { 2853, 3, 1, 4, 481, 0, 0, 1261, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2853 = XVTSTDCSP
3662 { 2852, 3, 1, 4, 481, 0, 0, 1261, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2852 = XVTSTDCDP
3663 { 2851, 2, 1, 4, 480, 1, 0, 1259, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2851 = XVTSQRTSP
3664 { 2850, 2, 1, 4, 479, 1, 0, 1259, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2850 = XVTSQRTDP
3665 { 2849, 2, 1, 4, 471, 0, 0, 1259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2849 = XVTLSBB
3666 { 2848, 3, 1, 4, 168, 1, 0, 1256, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2848 = XVTDIVSP
3667 { 2847, 3, 1, 4, 163, 1, 0, 1256, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2847 = XVTDIVDP
3668 { 2846, 3, 1, 4, 440, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2846 = XVSUBSP
3669 { 2845, 3, 1, 4, 439, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2845 = XVSUBDP
3670 { 2844, 2, 1, 4, 178, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2844 = XVSQRTSP
3671 { 2843, 2, 1, 4, 180, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2843 = XVSQRTDP
3672 { 2842, 2, 1, 4, 430, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2842 = XVRSQRTESP
3673 { 2841, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2841 = XVRSQRTEDP
3674 { 2840, 2, 1, 4, 433, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2840 = XVRSPIZ
3675 { 2839, 2, 1, 4, 433, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2839 = XVRSPIP
3676 { 2838, 2, 1, 4, 433, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2838 = XVRSPIM
3677 { 2837, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2837 = XVRSPIC
3678 { 2836, 2, 1, 4, 433, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2836 = XVRSPI
3679 { 2835, 2, 1, 4, 430, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2835 = XVRESP
3680 { 2834, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2834 = XVREDP
3681 { 2833, 2, 1, 4, 433, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2833 = XVRDPIZ
3682 { 2832, 2, 1, 4, 433, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2832 = XVRDPIP
3683 { 2831, 2, 1, 4, 433, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2831 = XVRDPIM
3684 { 2830, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2830 = XVRDPIC
3685 { 2829, 2, 1, 4, 433, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2829 = XVRDPI
3686 { 2828, 4, 1, 4, 189, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2828 = XVNMSUBMSP
3687 { 2827, 4, 1, 4, 192, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2827 = XVNMSUBMDP
3688 { 2826, 4, 1, 4, 189, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2826 = XVNMSUBASP
3689 { 2825, 4, 1, 4, 192, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2825 = XVNMSUBADP
3690 { 2824, 4, 1, 4, 189, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2824 = XVNMADDMSP
3691 { 2823, 4, 1, 4, 192, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2823 = XVNMADDMDP
3692 { 2822, 4, 1, 4, 189, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2822 = XVNMADDASP
3693 { 2821, 4, 1, 4, 192, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2821 = XVNMADDADP
3694 { 2820, 2, 1, 4, 266, 1, 0, 1219, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2820 = XVNEGSP
3695 { 2819, 2, 1, 4, 519, 1, 0, 1219, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2819 = XVNEGDP
3696 { 2818, 2, 1, 4, 266, 1, 0, 1219, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2818 = XVNABSSP
3697 { 2817, 2, 1, 4, 519, 1, 0, 1219, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2817 = XVNABSDP
3698 { 2816, 3, 1, 4, 440, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2816 = XVMULSP
3699 { 2815, 3, 1, 4, 439, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2815 = XVMULDP
3700 { 2814, 4, 1, 4, 189, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2814 = XVMSUBMSP
3701 { 2813, 4, 1, 4, 192, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2813 = XVMSUBMDP
3702 { 2812, 4, 1, 4, 189, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2812 = XVMSUBASP
3703 { 2811, 4, 1, 4, 192, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2811 = XVMSUBADP
3704 { 2810, 3, 1, 4, 161, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2810 = XVMINSP
3705 { 2809, 3, 1, 4, 161, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2809 = XVMINDP
3706 { 2808, 3, 1, 4, 161, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2808 = XVMAXSP
3707 { 2807, 3, 1, 4, 161, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2807 = XVMAXDP
3708 { 2806, 4, 1, 4, 189, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2806 = XVMADDMSP
3709 { 2805, 4, 1, 4, 192, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2805 = XVMADDMDP
3710 { 2804, 4, 1, 4, 189, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2804 = XVMADDASP
3711 { 2803, 4, 1, 4, 192, 1, 0, 1252, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2803 = XVMADDADP
3712 { 2802, 3, 1, 4, 527, 0, 0, 1221, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2802 = XVIEXPSP
3713 { 2801, 3, 1, 4, 527, 0, 0, 1221, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2801 = XVIEXPDP
3714 { 2800, 4, 1, 4, 19, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2800 = XVI8GER4WSPP
3715 { 2799, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2799 = XVI8GER4WPP
3716 { 2798, 3, 1, 4, 5, 0, 0, 1231, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2798 = XVI8GER4W
3717 { 2797, 4, 1, 4, 566, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2797 = XVI8GER4SPP
3718 { 2796, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2796 = XVI8GER4PP
3719 { 2795, 3, 1, 4, 564, 0, 0, 1224, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2795 = XVI8GER4
3720 { 2794, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2794 = XVI4GER8WPP
3721 { 2793, 3, 1, 4, 5, 0, 0, 1231, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2793 = XVI4GER8W
3722 { 2792, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2792 = XVI4GER8PP
3723 { 2791, 3, 1, 4, 564, 0, 0, 1224, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2791 = XVI4GER8
3724 { 2790, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2790 = XVI16GER2WPP
3725 { 2789, 3, 1, 4, 5, 0, 0, 1231, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2789 = XVI16GER2W
3726 { 2788, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2788 = XVI16GER2SWPP
3727 { 2787, 3, 1, 4, 5, 0, 0, 1231, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2787 = XVI16GER2SW
3728 { 2786, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2786 = XVI16GER2SPP
3729 { 2785, 3, 1, 4, 564, 0, 0, 1224, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2785 = XVI16GER2S
3730 { 2784, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2784 = XVI16GER2PP
3731 { 2783, 3, 1, 4, 564, 0, 0, 1224, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2783 = XVI16GER2
3732 { 2782, 4, 1, 4, 5, 0, 0, 1248, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2782 = XVF64GERWPP
3733 { 2781, 4, 1, 4, 5, 0, 0, 1248, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2781 = XVF64GERWPN
3734 { 2780, 4, 1, 4, 5, 0, 0, 1248, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2780 = XVF64GERWNP
3735 { 2779, 4, 1, 4, 5, 0, 0, 1248, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2779 = XVF64GERWNN
3736 { 2778, 3, 1, 4, 5, 0, 0, 1245, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2778 = XVF64GERW
3737 { 2777, 4, 1, 4, 565, 0, 0, 1241, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2777 = XVF64GERPP
3738 { 2776, 4, 1, 4, 565, 0, 0, 1241, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2776 = XVF64GERPN
3739 { 2775, 4, 1, 4, 565, 0, 0, 1241, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2775 = XVF64GERNP
3740 { 2774, 4, 1, 4, 565, 0, 0, 1241, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2774 = XVF64GERNN
3741 { 2773, 3, 1, 4, 564, 0, 0, 1238, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2773 = XVF64GER
3742 { 2772, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2772 = XVF32GERWPP
3743 { 2771, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2771 = XVF32GERWPN
3744 { 2770, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2770 = XVF32GERWNP
3745 { 2769, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2769 = XVF32GERWNN
3746 { 2768, 3, 1, 4, 5, 0, 0, 1231, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2768 = XVF32GERW
3747 { 2767, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2767 = XVF32GERPP
3748 { 2766, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2766 = XVF32GERPN
3749 { 2765, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2765 = XVF32GERNP
3750 { 2764, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2764 = XVF32GERNN
3751 { 2763, 3, 1, 4, 564, 0, 0, 1224, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2763 = XVF32GER
3752 { 2762, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2762 = XVF16GER2WPP
3753 { 2761, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2761 = XVF16GER2WPN
3754 { 2760, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2760 = XVF16GER2WNP
3755 { 2759, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2759 = XVF16GER2WNN
3756 { 2758, 3, 1, 4, 5, 0, 0, 1231, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2758 = XVF16GER2W
3757 { 2757, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2757 = XVF16GER2PP
3758 { 2756, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2756 = XVF16GER2PN
3759 { 2755, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2755 = XVF16GER2NP
3760 { 2754, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2754 = XVF16GER2NN
3761 { 2753, 3, 1, 4, 564, 0, 0, 1224, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2753 = XVF16GER2
3762 { 2752, 3, 1, 4, 177, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2752 = XVDIVSP
3763 { 2751, 3, 1, 4, 179, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2751 = XVDIVDP
3764 { 2750, 2, 1, 4, 430, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2750 = XVCVUXWSP
3765 { 2749, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2749 = XVCVUXWDP
3766 { 2748, 2, 1, 4, 430, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2748 = XVCVUXDSP
3767 { 2747, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2747 = XVCVUXDDP
3768 { 2746, 2, 1, 4, 430, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2746 = XVCVSXWSP
3769 { 2745, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2745 = XVCVSXWDP
3770 { 2744, 2, 1, 4, 430, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2744 = XVCVSXDSP
3771 { 2743, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2743 = XVCVSXDDP
3772 { 2742, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2742 = XVCVSPUXWS
3773 { 2741, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2741 = XVCVSPUXDS
3774 { 2740, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2740 = XVCVSPSXWS
3775 { 2739, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2739 = XVCVSPSXDS
3776 { 2738, 2, 1, 4, 429, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2738 = XVCVSPHP
3777 { 2737, 2, 1, 4, 193, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2737 = XVCVSPDP
3778 { 2736, 2, 1, 4, 434, 0, 0, 1219, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2736 = XVCVSPBF16
3779 { 2735, 2, 1, 4, 310, 0, 0, 1219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2735 = XVCVHPSP
3780 { 2734, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2734 = XVCVDPUXWS
3781 { 2733, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2733 = XVCVDPUXDS
3782 { 2732, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2732 = XVCVDPSXWS
3783 { 2731, 2, 1, 4, 433, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2731 = XVCVDPSXDS
3784 { 2730, 2, 1, 4, 430, 1, 0, 1219, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2730 = XVCVDPSP
3785 { 2729, 2, 1, 4, 583, 0, 0, 1219, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2729 = XVCVBF16SPN
3786 { 2728, 3, 1, 4, 267, 1, 0, 1221, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2728 = XVCPSGNSP
3787 { 2727, 3, 1, 4, 265, 1, 0, 1221, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2727 = XVCPSGNDP
3788 { 2726, 3, 1, 4, 486, 1, 1, 1221, PPCImpOpBase + 211, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2726 = XVCMPGTSP_rec
3789 { 2725, 3, 1, 4, 486, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2725 = XVCMPGTSP
3790 { 2724, 3, 1, 4, 162, 1, 1, 1221, PPCImpOpBase + 211, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2724 = XVCMPGTDP_rec
3791 { 2723, 3, 1, 4, 162, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2723 = XVCMPGTDP
3792 { 2722, 3, 1, 4, 486, 1, 1, 1221, PPCImpOpBase + 211, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2722 = XVCMPGESP_rec
3793 { 2721, 3, 1, 4, 486, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2721 = XVCMPGESP
3794 { 2720, 3, 1, 4, 162, 1, 1, 1221, PPCImpOpBase + 211, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2720 = XVCMPGEDP_rec
3795 { 2719, 3, 1, 4, 162, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2719 = XVCMPGEDP
3796 { 2718, 3, 1, 4, 486, 1, 1, 1221, PPCImpOpBase + 211, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2718 = XVCMPEQSP_rec
3797 { 2717, 3, 1, 4, 486, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2717 = XVCMPEQSP
3798 { 2716, 3, 1, 4, 162, 1, 1, 1221, PPCImpOpBase + 211, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2716 = XVCMPEQDP_rec
3799 { 2715, 3, 1, 4, 162, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2715 = XVCMPEQDP
3800 { 2714, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2714 = XVBF16GER2WPP
3801 { 2713, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2713 = XVBF16GER2WPN
3802 { 2712, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2712 = XVBF16GER2WNP
3803 { 2711, 4, 1, 4, 5, 0, 0, 1234, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2711 = XVBF16GER2WNN
3804 { 2710, 3, 1, 4, 5, 0, 0, 1231, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2710 = XVBF16GER2W
3805 { 2709, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2709 = XVBF16GER2PP
3806 { 2708, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2708 = XVBF16GER2PN
3807 { 2707, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2707 = XVBF16GER2NP
3808 { 2706, 4, 1, 4, 565, 0, 0, 1227, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2706 = XVBF16GER2NN
3809 { 2705, 3, 1, 4, 564, 0, 0, 1224, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2705 = XVBF16GER2
3810 { 2704, 3, 1, 4, 440, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2704 = XVADDSP
3811 { 2703, 3, 1, 4, 439, 1, 0, 1221, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2703 = XVADDDP
3812 { 2702, 2, 1, 4, 266, 1, 0, 1219, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2702 = XVABSSP
3813 { 2701, 2, 1, 4, 519, 1, 0, 1219, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2701 = XVABSDP
3814 { 2700, 2, 1, 4, 463, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2700 = XSXSIGQP
3815 { 2699, 2, 1, 4, 277, 0, 0, 693, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2699 = XSXSIGDP
3816 { 2698, 2, 1, 4, 518, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2698 = XSXEXPQP
3817 { 2697, 2, 1, 4, 293, 0, 0, 693, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2697 = XSXEXPDP
3818 { 2696, 3, 1, 4, 275, 0, 0, 1216, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2696 = XSTSTDCSP
3819 { 2695, 3, 1, 4, 463, 0, 0, 1213, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2695 = XSTSTDCQP
3820 { 2694, 3, 1, 4, 275, 0, 0, 1210, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2694 = XSTSTDCDP
3821 { 2693, 2, 1, 4, 478, 1, 0, 1208, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2693 = XSTSQRTDP
3822 { 2692, 3, 1, 4, 160, 1, 0, 1171, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2692 = XSTDIVDP
3823 { 2691, 3, 1, 4, 187, 0, 0, 1165, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2691 = XSSUBSP
3824 { 2690, 3, 1, 4, 327, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2690 = XSSUBQPO
3825 { 2689, 3, 1, 4, 327, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2689 = XSSUBQP
3826 { 2688, 3, 1, 4, 187, 1, 0, 1162, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2688 = XSSUBDP
3827 { 2687, 2, 1, 4, 173, 0, 0, 1178, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2687 = XSSQRTSP
3828 { 2686, 2, 1, 4, 332, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2686 = XSSQRTQPO
3829 { 2685, 2, 1, 4, 332, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2685 = XSSQRTQP
3830 { 2684, 2, 1, 4, 175, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2684 = XSSQRTDP
3831 { 2683, 2, 1, 4, 188, 0, 0, 1178, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2683 = XSRSQRTESP
3832 { 2682, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2682 = XSRSQRTEDP
3833 { 2681, 2, 1, 4, 188, 0, 0, 1184, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2681 = XSRSP
3834 { 2680, 4, 1, 4, 451, 0, 0, 1204, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2680 = XSRQPXP
3835 { 2679, 4, 1, 4, 451, 0, 0, 1204, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2679 = XSRQPIX
3836 { 2678, 4, 1, 4, 451, 0, 0, 1204, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2678 = XSRQPI
3837 { 2677, 2, 1, 4, 188, 0, 0, 1178, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2677 = XSRESP
3838 { 2676, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2676 = XSREDP
3839 { 2675, 2, 1, 4, 432, 0, 0, 1160, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2675 = XSRDPIZ
3840 { 2674, 2, 1, 4, 432, 0, 0, 1160, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2674 = XSRDPIP
3841 { 2673, 2, 1, 4, 432, 0, 0, 1160, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2673 = XSRDPIM
3842 { 2672, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2672 = XSRDPIC
3843 { 2671, 2, 1, 4, 432, 0, 0, 1160, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2671 = XSRDPI
3844 { 2670, 4, 1, 4, 329, 0, 0, 1200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2670 = XSNMSUBQPO
3845 { 2669, 4, 1, 4, 329, 0, 0, 1200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2669 = XSNMSUBQP
3846 { 2668, 4, 1, 4, 318, 0, 0, 1196, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2668 = XSNMSUBMSP
3847 { 2667, 4, 1, 4, 318, 1, 0, 1192, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2667 = XSNMSUBMDP
3848 { 2666, 4, 1, 4, 318, 0, 0, 1196, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2666 = XSNMSUBASP
3849 { 2665, 4, 1, 4, 318, 1, 0, 1192, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2665 = XSNMSUBADP
3850 { 2664, 4, 1, 4, 329, 0, 0, 1200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2664 = XSNMADDQPO
3851 { 2663, 4, 1, 4, 329, 0, 0, 1200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2663 = XSNMADDQP
3852 { 2662, 4, 1, 4, 318, 0, 0, 1196, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2662 = XSNMADDMSP
3853 { 2661, 4, 1, 4, 318, 1, 0, 1192, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2661 = XSNMADDMDP
3854 { 2660, 4, 1, 4, 318, 0, 0, 1196, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2660 = XSNMADDASP
3855 { 2659, 4, 1, 4, 318, 1, 0, 1192, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2659 = XSNMADDADP
3856 { 2658, 2, 1, 4, 518, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2658 = XSNEGQP
3857 { 2657, 2, 1, 4, 517, 1, 0, 1160, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2657 = XSNEGDP
3858 { 2656, 2, 1, 4, 518, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2656 = XSNABSQP
3859 { 2655, 2, 1, 4, 517, 1, 0, 1178, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2655 = XSNABSDPs
3860 { 2654, 2, 1, 4, 517, 1, 0, 1160, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2654 = XSNABSDP
3861 { 2653, 3, 1, 4, 438, 0, 0, 1165, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2653 = XSMULSP
3862 { 2652, 3, 1, 4, 454, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2652 = XSMULQPO
3863 { 2651, 3, 1, 4, 454, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2651 = XSMULQP
3864 { 2650, 3, 1, 4, 438, 1, 0, 1162, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2650 = XSMULDP
3865 { 2649, 4, 1, 4, 329, 0, 0, 1200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2649 = XSMSUBQPO
3866 { 2648, 4, 1, 4, 329, 0, 0, 1200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2648 = XSMSUBQP
3867 { 2647, 4, 1, 4, 318, 0, 0, 1196, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2647 = XSMSUBMSP
3868 { 2646, 4, 1, 4, 318, 1, 0, 1192, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2646 = XSMSUBMDP
3869 { 2645, 4, 1, 4, 318, 0, 0, 1196, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2645 = XSMSUBASP
3870 { 2644, 4, 1, 4, 318, 1, 0, 1192, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2644 = XSMSUBADP
3871 { 2643, 3, 1, 4, 491, 0, 0, 1168, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2643 = XSMINJDP
3872 { 2642, 3, 1, 4, 159, 1, 0, 1162, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2642 = XSMINDP
3873 { 2641, 3, 1, 4, 467, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2641 = XSMINCQP
3874 { 2640, 3, 1, 4, 491, 0, 0, 1162, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2640 = XSMINCDP
3875 { 2639, 3, 1, 4, 491, 0, 0, 1168, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2639 = XSMAXJDP
3876 { 2638, 3, 1, 4, 159, 1, 0, 1162, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2638 = XSMAXDP
3877 { 2637, 3, 1, 4, 467, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2637 = XSMAXCQP
3878 { 2636, 3, 1, 4, 491, 0, 0, 1162, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2636 = XSMAXCDP
3879 { 2635, 4, 1, 4, 329, 0, 0, 1200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2635 = XSMADDQPO
3880 { 2634, 4, 1, 4, 329, 0, 0, 1200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2634 = XSMADDQP
3881 { 2633, 4, 1, 4, 318, 0, 0, 1196, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2633 = XSMADDMSP
3882 { 2632, 4, 1, 4, 318, 1, 0, 1192, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2632 = XSMADDMDP
3883 { 2631, 4, 1, 4, 318, 0, 0, 1196, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2631 = XSMADDASP
3884 { 2630, 4, 1, 4, 318, 1, 0, 1192, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2630 = XSMADDADP
3885 { 2629, 3, 1, 4, 527, 0, 0, 1189, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2629 = XSIEXPQP
3886 { 2628, 3, 1, 4, 303, 0, 0, 1186, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2628 = XSIEXPDP
3887 { 2627, 3, 1, 4, 183, 0, 0, 1165, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2627 = XSDIVSP
3888 { 2626, 3, 1, 4, 331, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2626 = XSDIVQPO
3889 { 2625, 3, 1, 4, 331, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2625 = XSDIVQP
3890 { 2624, 3, 1, 4, 172, 1, 0, 1162, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2624 = XSDIVDP
3891 { 2623, 2, 1, 4, 188, 0, 0, 1184, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2623 = XSCVUXDSP
3892 { 2622, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2622 = XSCVUXDDP
3893 { 2621, 2, 1, 4, 452, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2621 = XSCVUQQP
3894 { 2620, 2, 1, 4, 451, 0, 0, 1174, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2620 = XSCVUDQP
3895 { 2619, 2, 1, 4, 188, 0, 0, 1184, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2619 = XSCVSXDSP
3896 { 2618, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2618 = XSCVSXDDP
3897 { 2617, 2, 1, 4, 452, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2617 = XSCVSQQP
3898 { 2616, 2, 1, 4, 282, 0, 0, 1182, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2616 = XSCVSPDPN
3899 { 2615, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2615 = XSCVSPDP
3900 { 2614, 2, 1, 4, 451, 0, 0, 1174, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2614 = XSCVSDQP
3901 { 2613, 2, 1, 4, 451, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2613 = XSCVQPUWZ
3902 { 2612, 2, 1, 4, 452, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2612 = XSCVQPUQZ
3903 { 2611, 2, 1, 4, 451, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2611 = XSCVQPUDZ
3904 { 2610, 2, 1, 4, 451, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2610 = XSCVQPSWZ
3905 { 2609, 2, 1, 4, 452, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2609 = XSCVQPSQZ
3906 { 2608, 2, 1, 4, 451, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2608 = XSCVQPSDZ
3907 { 2607, 2, 1, 4, 451, 0, 0, 1180, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2607 = XSCVQPDPO
3908 { 2606, 2, 1, 4, 451, 0, 0, 1180, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2606 = XSCVQPDP
3909 { 2605, 2, 1, 4, 321, 0, 0, 1160, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2605 = XSCVHPDP
3910 { 2604, 2, 1, 4, 432, 1, 0, 1178, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2604 = XSCVDPUXWSs
3911 { 2603, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2603 = XSCVDPUXWS
3912 { 2602, 2, 1, 4, 432, 1, 0, 1178, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2602 = XSCVDPUXDSs
3913 { 2601, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2601 = XSCVDPUXDS
3914 { 2600, 2, 1, 4, 432, 1, 0, 1178, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2600 = XSCVDPSXWSs
3915 { 2599, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2599 = XSCVDPSXWS
3916 { 2598, 2, 1, 4, 432, 1, 0, 1178, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2598 = XSCVDPSXDSs
3917 { 2597, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2597 = XSCVDPSXDS
3918 { 2596, 2, 1, 4, 188, 0, 0, 1176, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2596 = XSCVDPSPN
3919 { 2595, 2, 1, 4, 432, 1, 0, 1160, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2595 = XSCVDPSP
3920 { 2594, 2, 1, 4, 451, 0, 0, 1174, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2594 = XSCVDPQP
3921 { 2593, 2, 1, 4, 431, 0, 0, 1160, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2593 = XSCVDPHP
3922 { 2592, 3, 1, 4, 527, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2592 = XSCPSGNQP
3923 { 2591, 3, 1, 4, 292, 1, 0, 1162, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2591 = XSCPSGNDP
3924 { 2590, 3, 1, 4, 326, 0, 0, 1110, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2590 = XSCMPUQP
3925 { 2589, 3, 1, 4, 160, 1, 0, 1171, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2589 = XSCMPUDP
3926 { 2588, 3, 1, 4, 326, 0, 0, 1110, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2588 = XSCMPOQP
3927 { 2587, 3, 1, 4, 160, 1, 0, 1171, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #2587 = XSCMPODP
3928 { 2586, 3, 1, 4, 467, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2586 = XSCMPGTQP
3929 { 2585, 3, 1, 4, 278, 0, 0, 1168, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2585 = XSCMPGTDP
3930 { 2584, 3, 1, 4, 467, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2584 = XSCMPGEQP
3931 { 2583, 3, 1, 4, 278, 0, 0, 1168, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2583 = XSCMPGEDP
3932 { 2582, 3, 1, 4, 326, 0, 0, 1110, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2582 = XSCMPEXPQP
3933 { 2581, 3, 1, 4, 278, 0, 0, 1171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2581 = XSCMPEXPDP
3934 { 2580, 3, 1, 4, 467, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2580 = XSCMPEQQP
3935 { 2579, 3, 1, 4, 278, 0, 0, 1168, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2579 = XSCMPEQDP
3936 { 2578, 3, 1, 4, 187, 0, 0, 1165, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2578 = XSADDSP
3937 { 2577, 3, 1, 4, 327, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2577 = XSADDQPO
3938 { 2576, 3, 1, 4, 327, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2576 = XSADDQP
3939 { 2575, 3, 1, 4, 187, 1, 0, 1162, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2575 = XSADDDP
3940 { 2574, 2, 1, 4, 518, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2574 = XSABSQP
3941 { 2573, 2, 1, 4, 517, 1, 0, 1160, PPCImpOpBase + 134, 0, 0x0ULL }, // Inst #2573 = XSABSDP
3942 { 2572, 3, 1, 4, 198, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #2572 = XOR_rec
3943 { 2571, 3, 1, 4, 508, 0, 0, 181, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #2571 = XORIS8
3944 { 2570, 3, 1, 4, 508, 0, 0, 184, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #2570 = XORIS
3945 { 2569, 3, 1, 4, 508, 0, 0, 181, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #2569 = XORI8
3946 { 2568, 3, 1, 4, 508, 0, 0, 184, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #2568 = XORI
3947 { 2567, 3, 1, 4, 198, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #2567 = XOR8_rec
3948 { 2566, 3, 1, 4, 198, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #2566 = XOR8
3949 { 2565, 3, 1, 4, 198, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #2565 = XOR
3950 { 2564, 1, 0, 4, 420, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2564 = WRTEEI
3951 { 2563, 1, 0, 4, 420, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2563 = WRTEE
3952 { 2562, 2, 0, 4, 497, 0, 0, 21, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2562 = WAITP10
3953 { 2561, 1, 0, 4, 296, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2561 = WAIT
3954 { 2560, 1, 1, 4, 575, 0, 0, 692, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2560 = V_SETALLONESH
3955 { 2559, 1, 1, 4, 575, 0, 0, 692, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2559 = V_SETALLONESB
3956 { 2558, 1, 1, 4, 575, 0, 0, 692, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2558 = V_SETALLONES
3957 { 2557, 1, 1, 4, 527, 0, 0, 692, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2557 = V_SET0H
3958 { 2556, 1, 1, 4, 527, 0, 0, 692, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2556 = V_SET0B
3959 { 2555, 1, 1, 4, 527, 0, 0, 692, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL }, // Inst #2555 = V_SET0
3960 { 2554, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2554 = VXOR
3961 { 2553, 2, 1, 4, 579, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2553 = VUPKLSW
3962 { 2552, 2, 1, 4, 582, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2552 = VUPKLSH
3963 { 2551, 2, 1, 4, 582, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2551 = VUPKLSB
3964 { 2550, 2, 1, 4, 582, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2550 = VUPKLPX
3965 { 2549, 2, 1, 4, 579, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2549 = VUPKHSW
3966 { 2548, 2, 1, 4, 582, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2548 = VUPKHSH
3967 { 2547, 2, 1, 4, 582, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2547 = VUPKHSB
3968 { 2546, 2, 1, 4, 582, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2546 = VUPKHPX
3969 { 2545, 3, 1, 4, 590, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2545 = VSUMSWS
3970 { 2544, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2544 = VSUM4UBS
3971 { 2543, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2543 = VSUM4SHS
3972 { 2542, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2542 = VSUM4SBS
3973 { 2541, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2541 = VSUM2SWS
3974 { 2540, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2540 = VSUBUWS
3975 { 2539, 3, 1, 4, 167, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2539 = VSUBUWM
3976 { 2538, 3, 1, 4, 238, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2538 = VSUBUQM
3977 { 2537, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2537 = VSUBUHS
3978 { 2536, 3, 1, 4, 167, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2536 = VSUBUHM
3979 { 2535, 3, 1, 4, 260, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2535 = VSUBUDM
3980 { 2534, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2534 = VSUBUBS
3981 { 2533, 3, 1, 4, 167, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2533 = VSUBUBM
3982 { 2532, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2532 = VSUBSWS
3983 { 2531, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2531 = VSUBSHS
3984 { 2530, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2530 = VSUBSBS
3985 { 2529, 3, 1, 4, 191, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2529 = VSUBFP
3986 { 2528, 4, 1, 4, 237, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2528 = VSUBEUQM
3987 { 2527, 4, 1, 4, 237, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2527 = VSUBECUQ
3988 { 2526, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2526 = VSUBCUW
3989 { 2525, 3, 1, 4, 466, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2525 = VSUBCUQ
3990 { 2524, 2, 1, 4, 539, 0, 1, 307, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2524 = VSTRIHR_rec
3991 { 2523, 2, 1, 4, 581, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2523 = VSTRIHR
3992 { 2522, 2, 1, 4, 539, 0, 1, 307, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2522 = VSTRIHL_rec
3993 { 2521, 2, 1, 4, 581, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2521 = VSTRIHL
3994 { 2520, 2, 1, 4, 539, 0, 1, 307, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2520 = VSTRIBR_rec
3995 { 2519, 2, 1, 4, 581, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2519 = VSTRIBR
3996 { 2518, 2, 1, 4, 539, 0, 1, 307, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2518 = VSTRIBL_rec
3997 { 2517, 2, 1, 4, 581, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2517 = VSTRIBL
3998 { 2516, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2516 = VSRW
3999 { 2515, 3, 1, 4, 588, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2515 = VSRV
4000 { 2514, 3, 1, 4, 494, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2514 = VSRQ
4001 { 2513, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2513 = VSRO
4002 { 2512, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2512 = VSRH
4003 { 2511, 4, 1, 4, 586, 0, 0, 297, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2511 = VSRDBI
4004 { 2510, 3, 1, 4, 260, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2510 = VSRD
4005 { 2509, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2509 = VSRB
4006 { 2508, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2508 = VSRAW
4007 { 2507, 3, 1, 4, 494, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2507 = VSRAQ
4008 { 2506, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2506 = VSRAH
4009 { 2505, 3, 1, 4, 260, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2505 = VSRAD
4010 { 2504, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2504 = VSRAB
4011 { 2503, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2503 = VSR
4012 { 2502, 3, 1, 4, 580, 0, 0, 1102, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2502 = VSPLTW
4013 { 2501, 2, 1, 4, 574, 0, 0, 722, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2501 = VSPLTISW
4014 { 2500, 2, 1, 4, 574, 0, 0, 722, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2500 = VSPLTISH
4015 { 2499, 2, 1, 4, 574, 0, 0, 722, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2499 = VSPLTISB
4016 { 2498, 3, 1, 4, 580, 0, 0, 1157, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2498 = VSPLTHs
4017 { 2497, 3, 1, 4, 580, 0, 0, 1102, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2497 = VSPLTH
4018 { 2496, 3, 1, 4, 580, 0, 0, 1157, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2496 = VSPLTBs
4019 { 2495, 3, 1, 4, 580, 0, 0, 1102, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2495 = VSPLTB
4020 { 2494, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2494 = VSLW
4021 { 2493, 3, 1, 4, 588, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2493 = VSLV
4022 { 2492, 3, 1, 4, 494, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2492 = VSLQ
4023 { 2491, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2491 = VSLO
4024 { 2490, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2490 = VSLH
4025 { 2489, 4, 1, 4, 230, 0, 0, 297, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2489 = VSLDOI
4026 { 2488, 4, 1, 4, 586, 0, 0, 297, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2488 = VSLDBI
4027 { 2487, 3, 1, 4, 260, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2487 = VSLD
4028 { 2486, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2486 = VSLB
4029 { 2485, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2485 = VSL
4030 { 2484, 4, 1, 4, 477, 0, 0, 1153, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2484 = VSHASIGMAW
4031 { 2483, 4, 1, 4, 477, 0, 0, 1153, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2483 = VSHASIGMAD
4032 { 2482, 4, 1, 4, 269, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2482 = VSEL
4033 { 2481, 2, 1, 4, 448, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2481 = VSBOX
4034 { 2480, 2, 1, 4, 430, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2480 = VRSQRTEFP
4035 { 2479, 3, 1, 4, 527, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2479 = VRLWNM
4036 { 2478, 4, 1, 4, 263, 0, 0, 1149, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2478 = VRLWMI
4037 { 2477, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2477 = VRLW
4038 { 2476, 3, 1, 4, 494, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2476 = VRLQNM
4039 { 2475, 4, 1, 4, 495, 0, 0, 1149, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2475 = VRLQMI
4040 { 2474, 3, 1, 4, 494, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2474 = VRLQ
4041 { 2473, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2473 = VRLH
4042 { 2472, 3, 1, 4, 527, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2472 = VRLDNM
4043 { 2471, 4, 1, 4, 263, 0, 0, 1149, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2471 = VRLDMI
4044 { 2470, 3, 1, 4, 264, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2470 = VRLD
4045 { 2469, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2469 = VRLB
4046 { 2468, 2, 1, 4, 430, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2468 = VRFIZ
4047 { 2467, 2, 1, 4, 430, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2467 = VRFIP
4048 { 2466, 2, 1, 4, 430, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2466 = VRFIN
4049 { 2465, 2, 1, 4, 430, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2465 = VRFIM
4050 { 2464, 2, 1, 4, 430, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2464 = VREFP
4051 { 2463, 2, 1, 4, 475, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2463 = VPRTYBW
4052 { 2462, 2, 1, 4, 578, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2462 = VPRTYBQ
4053 { 2461, 2, 1, 4, 475, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2461 = VPRTYBD
4054 { 2460, 2, 1, 4, 232, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2460 = VPOPCNTW
4055 { 2459, 2, 1, 4, 476, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2459 = VPOPCNTH
4056 { 2458, 2, 1, 4, 309, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2458 = VPOPCNTD
4057 { 2457, 2, 1, 4, 476, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2457 = VPOPCNTB
4058 { 2456, 3, 1, 4, 182, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2456 = VPMSUMW
4059 { 2455, 3, 1, 4, 182, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2455 = VPMSUMH
4060 { 2454, 3, 1, 4, 182, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2454 = VPMSUMD
4061 { 2453, 3, 1, 4, 182, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2453 = VPMSUMB
4062 { 2452, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2452 = VPKUWUS
4063 { 2451, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2451 = VPKUWUM
4064 { 2450, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2450 = VPKUHUS
4065 { 2449, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2449 = VPKUHUM
4066 { 2448, 3, 1, 4, 585, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2448 = VPKUDUS
4067 { 2447, 3, 1, 4, 585, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2447 = VPKUDUM
4068 { 2446, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2446 = VPKSWUS
4069 { 2445, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2445 = VPKSWSS
4070 { 2444, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2444 = VPKSHUS
4071 { 2443, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2443 = VPKSHSS
4072 { 2442, 3, 1, 4, 585, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2442 = VPKSDUS
4073 { 2441, 3, 1, 4, 585, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2441 = VPKSDSS
4074 { 2440, 3, 1, 4, 587, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2440 = VPKPX
4075 { 2439, 3, 1, 4, 450, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2439 = VPEXTD
4076 { 2438, 4, 1, 4, 229, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2438 = VPERMXOR
4077 { 2437, 4, 1, 4, 323, 0, 0, 1098, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2437 = VPERMR
4078 { 2436, 4, 1, 4, 164, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2436 = VPERM
4079 { 2435, 3, 1, 4, 450, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2435 = VPDEPD
4080 { 2434, 3, 1, 4, 260, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2434 = VORC
4081 { 2433, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2433 = VOR
4082 { 2432, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2432 = VNOR
4083 { 2431, 4, 1, 4, 441, 0, 0, 1098, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2431 = VNMSUBFP
4084 { 2430, 2, 1, 4, 515, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2430 = VNEGW
4085 { 2429, 2, 1, 4, 515, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2429 = VNEGD
4086 { 2428, 3, 1, 4, 182, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2428 = VNCIPHERLAST
4087 { 2427, 3, 1, 4, 182, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2427 = VNCIPHER
4088 { 2426, 3, 1, 4, 260, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2426 = VNAND
4089 { 2425, 3, 1, 4, 241, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2425 = VMULUWM
4090 { 2424, 3, 1, 4, 240, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2424 = VMULOUW
4091 { 2423, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2423 = VMULOUH
4092 { 2422, 3, 1, 4, 623, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2422 = VMULOUD
4093 { 2421, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2421 = VMULOUB
4094 { 2420, 3, 1, 4, 240, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2420 = VMULOSW
4095 { 2419, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2419 = VMULOSH
4096 { 2418, 3, 1, 4, 623, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2418 = VMULOSD
4097 { 2417, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2417 = VMULOSB
4098 { 2416, 3, 1, 4, 572, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2416 = VMULLD
4099 { 2415, 3, 1, 4, 623, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2415 = VMULHUW
4100 { 2414, 3, 1, 4, 572, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2414 = VMULHUD
4101 { 2413, 3, 1, 4, 623, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2413 = VMULHSW
4102 { 2412, 3, 1, 4, 572, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2412 = VMULHSD
4103 { 2411, 3, 1, 4, 240, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2411 = VMULEUW
4104 { 2410, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2410 = VMULEUH
4105 { 2409, 3, 1, 4, 623, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2409 = VMULEUD
4106 { 2408, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2408 = VMULEUB
4107 { 2407, 3, 1, 4, 240, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2407 = VMULESW
4108 { 2406, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2406 = VMULESH
4109 { 2405, 3, 1, 4, 623, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2405 = VMULESD
4110 { 2404, 3, 1, 4, 622, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2404 = VMULESB
4111 { 2403, 2, 1, 4, 463, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2403 = VMUL10UQ
4112 { 2402, 3, 1, 4, 465, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2402 = VMUL10EUQ
4113 { 2401, 3, 1, 4, 465, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2401 = VMUL10ECUQ
4114 { 2400, 2, 1, 4, 463, 0, 0, 307, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2400 = VMUL10CUQ
4115 { 2399, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2399 = VMSUMUHS
4116 { 2398, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2398 = VMSUMUHM
4117 { 2397, 4, 1, 4, 166, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2397 = VMSUMUDM
4118 { 2396, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2396 = VMSUMUBM
4119 { 2395, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2395 = VMSUMSHS
4120 { 2394, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2394 = VMSUMSHM
4121 { 2393, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2393 = VMSUMMBM
4122 { 2392, 4, 1, 4, 624, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2392 = VMSUMCUD
4123 { 2391, 3, 1, 4, 268, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2391 = VMRGOW
4124 { 2390, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2390 = VMRGLW
4125 { 2389, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2389 = VMRGLH
4126 { 2388, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2388 = VMRGLB
4127 { 2387, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2387 = VMRGHW
4128 { 2386, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2386 = VMRGHH
4129 { 2385, 3, 1, 4, 230, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2385 = VMRGHB
4130 { 2384, 3, 1, 4, 268, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2384 = VMRGEW
4131 { 2383, 3, 1, 4, 460, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2383 = VMODUW
4132 { 2382, 3, 1, 4, 456, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2382 = VMODUQ
4133 { 2381, 3, 1, 4, 458, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2381 = VMODUD
4134 { 2380, 3, 1, 4, 460, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2380 = VMODSW
4135 { 2379, 3, 1, 4, 456, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2379 = VMODSQ
4136 { 2378, 3, 1, 4, 458, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2378 = VMODSD
4137 { 2377, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2377 = VMLADDUHM
4138 { 2376, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2376 = VMINUW
4139 { 2375, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2375 = VMINUH
4140 { 2374, 3, 1, 4, 233, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2374 = VMINUD
4141 { 2373, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2373 = VMINUB
4142 { 2372, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2372 = VMINSW
4143 { 2371, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2371 = VMINSH
4144 { 2370, 3, 1, 4, 233, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2370 = VMINSD
4145 { 2369, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2369 = VMINSB
4146 { 2368, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2368 = VMINFP
4147 { 2367, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2367 = VMHRADDSHS
4148 { 2366, 4, 1, 4, 239, 0, 0, 1098, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL }, // Inst #2366 = VMHADDSHS
4149 { 2365, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2365 = VMAXUW
4150 { 2364, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2364 = VMAXUH
4151 { 2363, 3, 1, 4, 233, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2363 = VMAXUD
4152 { 2362, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2362 = VMAXUB
4153 { 2361, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2361 = VMAXSW
4154 { 2360, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2360 = VMAXSH
4155 { 2359, 3, 1, 4, 233, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2359 = VMAXSD
4156 { 2358, 3, 1, 4, 231, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2358 = VMAXSB
4157 { 2357, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2357 = VMAXFP
4158 { 2356, 4, 1, 4, 441, 0, 0, 1098, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2356 = VMADDFP
4159 { 2355, 2, 1, 4, 430, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2355 = VLOGEFP
4160 { 2354, 4, 1, 4, 589, 0, 0, 1129, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2354 = VINSWVRX
4161 { 2353, 4, 1, 4, 589, 0, 0, 1129, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2353 = VINSWVLX
4162 { 2352, 4, 1, 4, 589, 0, 0, 1125, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2352 = VINSWRX
4163 { 2351, 4, 1, 4, 589, 0, 0, 1125, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2351 = VINSWLX
4164 { 2350, 4, 1, 4, 586, 0, 0, 1145, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2350 = VINSW
4165 { 2349, 4, 1, 4, 589, 0, 0, 1129, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2349 = VINSHVRX
4166 { 2348, 4, 1, 4, 589, 0, 0, 1129, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2348 = VINSHVLX
4167 { 2347, 4, 1, 4, 589, 0, 0, 1125, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2347 = VINSHRX
4168 { 2346, 4, 1, 4, 589, 0, 0, 1125, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2346 = VINSHLX
4169 { 2345, 3, 1, 4, 578, 0, 0, 1102, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2345 = VINSERTW
4170 { 2344, 4, 1, 4, 324, 0, 0, 1141, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2344 = VINSERTH
4171 { 2343, 3, 1, 4, 578, 0, 0, 1102, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2343 = VINSERTD
4172 { 2342, 4, 1, 4, 324, 0, 0, 1141, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2342 = VINSERTB
4173 { 2341, 4, 1, 4, 589, 0, 0, 1137, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2341 = VINSDRX
4174 { 2340, 4, 1, 4, 589, 0, 0, 1137, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2340 = VINSDLX
4175 { 2339, 4, 1, 4, 586, 0, 0, 1133, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2339 = VINSD
4176 { 2338, 4, 1, 4, 589, 0, 0, 1129, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2338 = VINSBVRX
4177 { 2337, 4, 1, 4, 589, 0, 0, 1129, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2337 = VINSBVLX
4178 { 2336, 4, 1, 4, 589, 0, 0, 1125, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2336 = VINSBRX
4179 { 2335, 4, 1, 4, 589, 0, 0, 1125, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2335 = VINSBLX
4180 { 2334, 3, 1, 4, 447, 0, 0, 1113, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2334 = VGNB
4181 { 2333, 2, 1, 4, 579, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2333 = VGBBD
4182 { 2332, 3, 1, 4, 324, 0, 0, 1122, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2332 = VEXTUWRX
4183 { 2331, 3, 1, 4, 324, 0, 0, 1122, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2331 = VEXTUWLX
4184 { 2330, 3, 1, 4, 324, 0, 0, 1122, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2330 = VEXTUHRX
4185 { 2329, 3, 1, 4, 324, 0, 0, 1122, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2329 = VEXTUHLX
4186 { 2328, 3, 1, 4, 324, 0, 0, 1122, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2328 = VEXTUBRX
4187 { 2327, 3, 1, 4, 324, 0, 0, 1122, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2327 = VEXTUBLX
4188 { 2326, 2, 1, 4, 515, 0, 0, 1120, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2326 = VEXTSW2Ds
4189 { 2325, 2, 1, 4, 515, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2325 = VEXTSW2D
4190 { 2324, 2, 1, 4, 515, 0, 0, 1120, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2324 = VEXTSH2Ws
4191 { 2323, 2, 1, 4, 515, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2323 = VEXTSH2W
4192 { 2322, 2, 1, 4, 515, 0, 0, 1120, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2322 = VEXTSH2Ds
4193 { 2321, 2, 1, 4, 515, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2321 = VEXTSH2D
4194 { 2320, 2, 1, 4, 516, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2320 = VEXTSD2Q
4195 { 2319, 2, 1, 4, 515, 0, 0, 1120, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2319 = VEXTSB2Ws
4196 { 2318, 2, 1, 4, 515, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2318 = VEXTSB2W
4197 { 2317, 2, 1, 4, 515, 0, 0, 1120, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2317 = VEXTSB2Ds
4198 { 2316, 2, 1, 4, 515, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2316 = VEXTSB2D
4199 { 2315, 2, 1, 4, 471, 0, 0, 1108, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2315 = VEXTRACTWM
4200 { 2314, 3, 1, 4, 578, 0, 0, 1102, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2314 = VEXTRACTUW
4201 { 2313, 3, 1, 4, 578, 0, 0, 1102, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2313 = VEXTRACTUH
4202 { 2312, 3, 1, 4, 578, 0, 0, 1102, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2312 = VEXTRACTUB
4203 { 2311, 2, 1, 4, 471, 0, 0, 1108, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2311 = VEXTRACTQM
4204 { 2310, 2, 1, 4, 471, 0, 0, 1108, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2310 = VEXTRACTHM
4205 { 2309, 2, 1, 4, 471, 0, 0, 1108, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2309 = VEXTRACTDM
4206 { 2308, 3, 1, 4, 578, 0, 0, 1102, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2308 = VEXTRACTD
4207 { 2307, 2, 1, 4, 471, 0, 0, 1108, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #2307 = VEXTRACTBM
4208 { 2306, 4, 1, 4, 589, 0, 0, 1116, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2306 = VEXTDUWVRX
4209 { 2305, 4, 1, 4, 589, 0, 0, 1116, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2305 = VEXTDUWVLX
4210 { 2304, 4, 1, 4, 589, 0, 0, 1116, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2304 = VEXTDUHVRX
4211 { 2303, 4, 1, 4, 589, 0, 0, 1116, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2303 = VEXTDUHVLX
4212 { 2302, 4, 1, 4, 589, 0, 0, 1116, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2302 = VEXTDUBVRX
4213 { 2301, 4, 1, 4, 589, 0, 0, 1116, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2301 = VEXTDUBVLX
4214 { 2300, 4, 1, 4, 589, 0, 0, 1116, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2300 = VEXTDDVRX
4215 { 2299, 4, 1, 4, 589, 0, 0, 1116, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2299 = VEXTDDVLX
4216 { 2298, 2, 1, 4, 190, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2298 = VEXPTEFP
4217 { 2297, 2, 1, 4, 471, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2297 = VEXPANDWM
4218 { 2296, 2, 1, 4, 471, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2296 = VEXPANDQM
4219 { 2295, 2, 1, 4, 471, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2295 = VEXPANDHM
4220 { 2294, 2, 1, 4, 471, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2294 = VEXPANDDM
4221 { 2293, 2, 1, 4, 471, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2293 = VEXPANDBM
4222 { 2292, 3, 1, 4, 260, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2292 = VEQV
4223 { 2291, 3, 1, 4, 459, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2291 = VDIVUW
4224 { 2290, 3, 1, 4, 455, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2290 = VDIVUQ
4225 { 2289, 3, 1, 4, 457, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2289 = VDIVUD
4226 { 2288, 3, 1, 4, 459, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2288 = VDIVSW
4227 { 2287, 3, 1, 4, 455, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2287 = VDIVSQ
4228 { 2286, 3, 1, 4, 457, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2286 = VDIVSD
4229 { 2285, 3, 1, 4, 462, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2285 = VDIVEUW
4230 { 2284, 3, 1, 4, 455, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2284 = VDIVEUQ
4231 { 2283, 3, 1, 4, 461, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2283 = VDIVEUD
4232 { 2282, 3, 1, 4, 462, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2282 = VDIVESW
4233 { 2281, 3, 1, 4, 455, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2281 = VDIVESQ
4234 { 2280, 3, 1, 4, 461, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2280 = VDIVESD
4235 { 2279, 2, 1, 4, 475, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2279 = VCTZW
4236 { 2278, 2, 1, 4, 578, 0, 0, 1108, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2278 = VCTZLSBB
4237 { 2277, 2, 1, 4, 475, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2277 = VCTZH
4238 { 2276, 3, 1, 4, 450, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2276 = VCTZDM
4239 { 2275, 2, 1, 4, 475, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2275 = VCTZD
4240 { 2274, 2, 1, 4, 475, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2274 = VCTZB
4241 { 2273, 2, 1, 4, 429, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2273 = VCTUXS_0
4242 { 2272, 3, 1, 4, 428, 0, 0, 1102, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2272 = VCTUXS
4243 { 2271, 2, 1, 4, 429, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2271 = VCTSXS_0
4244 { 2270, 3, 1, 4, 428, 0, 0, 1102, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2270 = VCTSXS
4245 { 2269, 3, 1, 4, 471, 0, 0, 1113, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2269 = VCNTMBW
4246 { 2268, 3, 1, 4, 471, 0, 0, 1113, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2268 = VCNTMBH
4247 { 2267, 3, 1, 4, 471, 0, 0, 1113, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2267 = VCNTMBD
4248 { 2266, 3, 1, 4, 471, 0, 0, 1113, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2266 = VCNTMBB
4249 { 2265, 3, 1, 4, 490, 0, 0, 1110, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2265 = VCMPUQ
4250 { 2264, 3, 1, 4, 490, 0, 0, 1110, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2264 = VCMPSQ
4251 { 2263, 3, 1, 4, 489, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2263 = VCMPNEZW_rec
4252 { 2262, 3, 1, 4, 306, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2262 = VCMPNEZW
4253 { 2261, 3, 1, 4, 489, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2261 = VCMPNEZH_rec
4254 { 2260, 3, 1, 4, 306, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2260 = VCMPNEZH
4255 { 2259, 3, 1, 4, 489, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2259 = VCMPNEZB_rec
4256 { 2258, 3, 1, 4, 306, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2258 = VCMPNEZB
4257 { 2257, 3, 1, 4, 489, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2257 = VCMPNEW_rec
4258 { 2256, 3, 1, 4, 306, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2256 = VCMPNEW
4259 { 2255, 3, 1, 4, 489, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2255 = VCMPNEH_rec
4260 { 2254, 3, 1, 4, 306, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2254 = VCMPNEH
4261 { 2253, 3, 1, 4, 489, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2253 = VCMPNEB_rec
4262 { 2252, 3, 1, 4, 306, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2252 = VCMPNEB
4263 { 2251, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2251 = VCMPGTUW_rec
4264 { 2250, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2250 = VCMPGTUW
4265 { 2249, 3, 1, 4, 488, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2249 = VCMPGTUQ_rec
4266 { 2248, 3, 1, 4, 488, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2248 = VCMPGTUQ
4267 { 2247, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2247 = VCMPGTUH_rec
4268 { 2246, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2246 = VCMPGTUH
4269 { 2245, 3, 1, 4, 487, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2245 = VCMPGTUD_rec
4270 { 2244, 3, 1, 4, 234, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2244 = VCMPGTUD
4271 { 2243, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2243 = VCMPGTUB_rec
4272 { 2242, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2242 = VCMPGTUB
4273 { 2241, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2241 = VCMPGTSW_rec
4274 { 2240, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2240 = VCMPGTSW
4275 { 2239, 3, 1, 4, 488, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2239 = VCMPGTSQ_rec
4276 { 2238, 3, 1, 4, 488, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2238 = VCMPGTSQ
4277 { 2237, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2237 = VCMPGTSH_rec
4278 { 2236, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2236 = VCMPGTSH
4279 { 2235, 3, 1, 4, 487, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2235 = VCMPGTSD_rec
4280 { 2234, 3, 1, 4, 234, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2234 = VCMPGTSD
4281 { 2233, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2233 = VCMPGTSB_rec
4282 { 2232, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2232 = VCMPGTSB
4283 { 2231, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2231 = VCMPGTFP_rec
4284 { 2230, 3, 1, 4, 486, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2230 = VCMPGTFP
4285 { 2229, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2229 = VCMPGEFP_rec
4286 { 2228, 3, 1, 4, 486, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2228 = VCMPGEFP
4287 { 2227, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2227 = VCMPEQUW_rec
4288 { 2226, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2226 = VCMPEQUW
4289 { 2225, 3, 1, 4, 488, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2225 = VCMPEQUQ_rec
4290 { 2224, 3, 1, 4, 488, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2224 = VCMPEQUQ
4291 { 2223, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2223 = VCMPEQUH_rec
4292 { 2222, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2222 = VCMPEQUH
4293 { 2221, 3, 1, 4, 487, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2221 = VCMPEQUD_rec
4294 { 2220, 3, 1, 4, 234, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2220 = VCMPEQUD
4295 { 2219, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2219 = VCMPEQUB_rec
4296 { 2218, 3, 1, 4, 169, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2218 = VCMPEQUB
4297 { 2217, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2217 = VCMPEQFP_rec
4298 { 2216, 3, 1, 4, 486, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2216 = VCMPEQFP
4299 { 2215, 3, 1, 4, 486, 0, 1, 304, PPCImpOpBase + 78, 0, 0x28ULL }, // Inst #2215 = VCMPBFP_rec
4300 { 2214, 3, 1, 4, 486, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2214 = VCMPBFP
4301 { 2213, 2, 1, 4, 232, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2213 = VCLZW
4302 { 2212, 2, 1, 4, 578, 0, 0, 1108, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2212 = VCLZLSBB
4303 { 2211, 2, 1, 4, 232, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2211 = VCLZH
4304 { 2210, 3, 1, 4, 450, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2210 = VCLZDM
4305 { 2209, 2, 1, 4, 232, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2209 = VCLZD
4306 { 2208, 2, 1, 4, 232, 0, 0, 307, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2208 = VCLZB
4307 { 2207, 3, 1, 4, 586, 0, 0, 1105, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2207 = VCLRRB
4308 { 2206, 3, 1, 4, 586, 0, 0, 1105, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2206 = VCLRLB
4309 { 2205, 3, 1, 4, 182, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2205 = VCIPHERLAST
4310 { 2204, 3, 1, 4, 182, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2204 = VCIPHER
4311 { 2203, 2, 1, 4, 429, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2203 = VCFUX_0
4312 { 2202, 3, 1, 4, 428, 0, 0, 1102, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2202 = VCFUX
4313 { 2201, 3, 1, 4, 450, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2201 = VCFUGED
4314 { 2200, 2, 1, 4, 429, 0, 0, 307, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2200 = VCFSX_0
4315 { 2199, 3, 1, 4, 428, 0, 0, 1102, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2199 = VCFSX
4316 { 2198, 3, 1, 4, 585, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2198 = VBPERMQ
4317 { 2197, 3, 1, 4, 308, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2197 = VBPERMD
4318 { 2196, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2196 = VAVGUW
4319 { 2195, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2195 = VAVGUH
4320 { 2194, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2194 = VAVGUB
4321 { 2193, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2193 = VAVGSW
4322 { 2192, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2192 = VAVGSH
4323 { 2191, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2191 = VAVGSB
4324 { 2190, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0, 0x28ULL }, // Inst #2190 = VANDC
4325 { 2189, 3, 1, 4, 261, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2189 = VAND
4326 { 2188, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2188 = VADDUWS
4327 { 2187, 3, 1, 4, 167, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2187 = VADDUWM
4328 { 2186, 3, 1, 4, 238, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2186 = VADDUQM
4329 { 2185, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2185 = VADDUHS
4330 { 2184, 3, 1, 4, 167, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2184 = VADDUHM
4331 { 2183, 3, 1, 4, 260, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2183 = VADDUDM
4332 { 2182, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2182 = VADDUBS
4333 { 2181, 3, 1, 4, 167, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2181 = VADDUBM
4334 { 2180, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2180 = VADDSWS
4335 { 2179, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2179 = VADDSHS
4336 { 2178, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2178 = VADDSBS
4337 { 2177, 3, 1, 4, 437, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2177 = VADDFP
4338 { 2176, 4, 1, 4, 237, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2176 = VADDEUQM
4339 { 2175, 4, 1, 4, 237, 0, 0, 1098, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2175 = VADDECUQ
4340 { 2174, 3, 1, 4, 485, 0, 0, 304, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x28ULL }, // Inst #2174 = VADDCUW
4341 { 2173, 3, 1, 4, 466, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2173 = VADDCUQ
4342 { 2172, 3, 1, 4, 307, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2172 = VABSDUW
4343 { 2171, 3, 1, 4, 307, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2171 = VABSDUH
4344 { 2170, 3, 1, 4, 307, 0, 0, 304, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2170 = VABSDUB
4345 { 2169, 3, 2, 4, 0, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2169 = UpdateGBR
4346 { 2168, 0, 0, 4, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2168 = UNENCODED_NOP
4347 { 2167, 3, 0, 4, 484, 0, 0, 1081, PPCImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2167 = TWI
4348 { 2166, 3, 0, 4, 195, 0, 0, 443, PPCImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2166 = TW
4349 { 2165, 1, 0, 4, 305, 0, 1, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2165 = TSR
4350 { 2164, 1, 0, 4, 305, 0, 1, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2164 = TRECLAIM
4351 { 2163, 0, 0, 4, 295, 0, 1, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2163 = TRECHKPT
4352 { 2162, 0, 0, 4, 492, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2162 = TRAP
4353 { 2161, 2, 1, 4, 0, 0, 0, 261, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2161 = TLSLDAIX8
4354 { 2160, 2, 1, 4, 0, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2160 = TLSLDAIX
4355 { 2159, 3, 1, 4, 0, 0, 0, 228, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2159 = TLSGDAIX8
4356 { 2158, 3, 1, 4, 0, 0, 0, 222, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #2158 = TLSGDAIX
4357 { 2157, 3, 0, 4, 618, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2157 = TLBWE2
4358 { 2156, 0, 0, 4, 413, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2156 = TLBWE
4359 { 2155, 0, 0, 4, 345, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2155 = TLBSYNC
4360 { 2154, 3, 0, 4, 618, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2154 = TLBSX2D
4361 { 2153, 3, 0, 4, 618, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2153 = TLBSX2
4362 { 2152, 2, 0, 4, 413, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2152 = TLBSX
4363 { 2151, 3, 1, 4, 618, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2151 = TLBRE2
4364 { 2150, 0, 0, 4, 413, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2150 = TLBRE
4365 { 2149, 1, 0, 4, 618, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2149 = TLBLI
4366 { 2148, 1, 0, 4, 618, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2148 = TLBLD
4367 { 2147, 2, 0, 4, 413, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2147 = TLBIVAX
4368 { 2146, 3, 0, 4, 15, 0, 0, 443, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2146 = TLBILX
4369 { 2145, 1, 0, 4, 354, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2145 = TLBIEL
4370 { 2144, 2, 0, 4, 372, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2144 = TLBIE
4371 { 2143, 0, 0, 4, 419, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2143 = TLBIA
4372 { 2142, 1, 0, 4, 357, 0, 1, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2142 = TEND
4373 { 2141, 3, 0, 4, 483, 0, 0, 1095, PPCImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2141 = TDI
4374 { 2140, 3, 0, 4, 194, 0, 0, 1092, PPCImpOpBase + 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2140 = TD
4375 { 2139, 2, 0, 4, 0, 1, 0, 1090, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2139 = TCRETURNri8
4376 { 2138, 2, 0, 4, 0, 1, 0, 1088, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2138 = TCRETURNri
4377 { 2137, 2, 0, 4, 0, 1, 0, 1086, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2137 = TCRETURNdi8
4378 { 2136, 2, 0, 4, 0, 1, 0, 1086, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2136 = TCRETURNdi
4379 { 2135, 2, 0, 4, 0, 1, 0, 1084, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2135 = TCRETURNai8
4380 { 2134, 2, 0, 4, 0, 1, 0, 1084, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #2134 = TCRETURNai
4381 { 2133, 1, 1, 4, 0, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2133 = TCHECK_RET
4382 { 2132, 1, 1, 4, 359, 0, 0, 675, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2132 = TCHECK
4383 { 2131, 2, 1, 4, 0, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2131 = TBEGIN_RET
4384 { 2130, 1, 0, 4, 295, 0, 1, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2130 = TBEGIN
4385 { 2129, 0, 0, 4, 402, 2, 0, 1, PPCImpOpBase + 209, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2129 = TAILBCTR8
4386 { 2128, 0, 0, 4, 402, 2, 0, 1, PPCImpOpBase + 207, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2128 = TAILBCTR
4387 { 2127, 1, 0, 4, 446, 1, 0, 0, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2127 = TAILBA8
4388 { 2126, 1, 0, 4, 446, 1, 0, 0, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2126 = TAILBA
4389 { 2125, 1, 0, 4, 446, 1, 0, 285, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2125 = TAILB8
4390 { 2124, 1, 0, 4, 446, 1, 0, 285, PPCImpOpBase + 134, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #2124 = TAILB
4391 { 2123, 3, 0, 4, 271, 0, 1, 1081, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2123 = TABORTWCI
4392 { 2122, 3, 0, 4, 271, 0, 1, 443, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2122 = TABORTWC
4393 { 2121, 3, 0, 4, 271, 0, 1, 1081, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2121 = TABORTDCI
4394 { 2120, 3, 0, 4, 271, 0, 1, 443, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2120 = TABORTDC
4395 { 2119, 1, 0, 4, 305, 0, 1, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2119 = TABORT
4396 { 2118, 2, 0, 4, 612, 0, 0, 21, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2118 = SYNCP10
4397 { 2117, 1, 0, 4, 346, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2117 = SYNC
4398 { 2116, 3, 1, 4, 287, 0, 1, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #2116 = SUBF_rec
4399 { 2115, 2, 1, 4, 532, 1, 2, 259, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #2115 = SUBFZE_rec
4400 { 2114, 2, 1, 4, 532, 1, 3, 259, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #2114 = SUBFZEO_rec
4401 { 2113, 2, 1, 4, 502, 1, 2, 259, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #2113 = SUBFZEO
4402 { 2112, 2, 1, 4, 532, 1, 2, 261, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #2112 = SUBFZE8_rec
4403 { 2111, 2, 1, 4, 532, 1, 3, 261, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #2111 = SUBFZE8O_rec
4404 { 2110, 2, 1, 4, 502, 1, 2, 261, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #2110 = SUBFZE8O
4405 { 2109, 2, 1, 4, 501, 1, 1, 261, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #2109 = SUBFZE8
4406 { 2108, 2, 1, 4, 501, 1, 1, 259, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #2108 = SUBFZE
4407 { 2107, 4, 1, 4, 144, 0, 1, 241, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2107 = SUBFUS_rec
4408 { 2106, 4, 1, 4, 144, 0, 0, 241, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2106 = SUBFUS
4409 { 2105, 3, 1, 4, 534, 0, 2, 222, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #2105 = SUBFO_rec
4410 { 2104, 3, 1, 4, 521, 0, 1, 222, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #2104 = SUBFO
4411 { 2103, 2, 1, 4, 532, 1, 2, 259, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #2103 = SUBFME_rec
4412 { 2102, 2, 1, 4, 532, 1, 3, 259, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #2102 = SUBFMEO_rec
4413 { 2101, 2, 1, 4, 502, 1, 2, 259, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #2101 = SUBFMEO
4414 { 2100, 2, 1, 4, 532, 1, 2, 261, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #2100 = SUBFME8_rec
4415 { 2099, 2, 1, 4, 532, 1, 3, 261, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #2099 = SUBFME8O_rec
4416 { 2098, 2, 1, 4, 502, 1, 2, 261, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #2098 = SUBFME8O
4417 { 2097, 2, 1, 4, 501, 1, 1, 261, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #2097 = SUBFME8
4418 { 2096, 2, 1, 4, 501, 1, 1, 259, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #2096 = SUBFME
4419 { 2095, 3, 1, 4, 501, 0, 1, 181, PPCImpOpBase + 5, 0, 0x8ULL }, // Inst #2095 = SUBFIC8
4420 { 2094, 3, 1, 4, 501, 0, 1, 184, PPCImpOpBase + 5, 0, 0x8ULL }, // Inst #2094 = SUBFIC
4421 { 2093, 3, 1, 4, 534, 1, 2, 222, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #2093 = SUBFE_rec
4422 { 2092, 3, 1, 4, 534, 1, 3, 222, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #2092 = SUBFEO_rec
4423 { 2091, 3, 1, 4, 521, 1, 2, 222, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #2091 = SUBFEO
4424 { 2090, 3, 1, 4, 534, 1, 2, 228, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #2090 = SUBFE8_rec
4425 { 2089, 3, 1, 4, 534, 1, 3, 228, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #2089 = SUBFE8O_rec
4426 { 2088, 3, 1, 4, 521, 1, 2, 228, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #2088 = SUBFE8O
4427 { 2087, 3, 1, 4, 142, 1, 1, 228, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #2087 = SUBFE8
4428 { 2086, 3, 1, 4, 142, 1, 1, 222, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #2086 = SUBFE
4429 { 2085, 3, 1, 4, 538, 0, 2, 222, PPCImpOpBase + 11, 0, 0xcULL }, // Inst #2085 = SUBFC_rec
4430 { 2084, 3, 1, 4, 390, 0, 3, 222, PPCImpOpBase + 8, 0, 0xcULL }, // Inst #2084 = SUBFCO_rec
4431 { 2083, 3, 1, 4, 286, 0, 2, 222, PPCImpOpBase + 6, 0, 0xcULL }, // Inst #2083 = SUBFCO
4432 { 2082, 3, 1, 4, 538, 0, 2, 228, PPCImpOpBase + 11, 0, 0xcULL }, // Inst #2082 = SUBFC8_rec
4433 { 2081, 3, 1, 4, 390, 0, 3, 228, PPCImpOpBase + 8, 0, 0xcULL }, // Inst #2081 = SUBFC8O_rec
4434 { 2080, 3, 1, 4, 286, 0, 2, 228, PPCImpOpBase + 6, 0, 0xcULL }, // Inst #2080 = SUBFC8O
4435 { 2079, 3, 1, 4, 286, 0, 1, 228, PPCImpOpBase + 5, 0, 0xcULL }, // Inst #2079 = SUBFC8
4436 { 2078, 3, 1, 4, 286, 0, 1, 222, PPCImpOpBase + 5, 0, 0xcULL }, // Inst #2078 = SUBFC
4437 { 2077, 3, 1, 4, 200, 0, 1, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #2077 = SUBF8_rec
4438 { 2076, 3, 1, 4, 534, 0, 2, 228, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #2076 = SUBF8O_rec
4439 { 2075, 3, 1, 4, 521, 0, 1, 228, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #2075 = SUBF8O
4440 { 2074, 3, 1, 4, 139, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #2074 = SUBF8
4441 { 2073, 3, 1, 4, 228, 0, 0, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #2073 = SUBF
4442 { 2072, 3, 0, 4, 373, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2072 = STXVX
4443 { 2071, 3, 0, 4, 116, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2071 = STXVW4X
4444 { 2070, 3, 0, 4, 609, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2070 = STXVRWX
4445 { 2069, 3, 0, 4, 15, 0, 0, 653, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2069 = STXVRLL
4446 { 2068, 3, 0, 4, 15, 0, 0, 653, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2068 = STXVRL
4447 { 2067, 3, 0, 4, 609, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2067 = STXVRHX
4448 { 2066, 3, 0, 4, 609, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2066 = STXVRDX
4449 { 2065, 3, 0, 4, 609, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2065 = STXVRBX
4450 { 2064, 3, 0, 4, 615, 0, 0, 662, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2064 = STXVPX
4451 { 2063, 3, 0, 4, 40, 0, 0, 659, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2063 = STXVPRLL
4452 { 2062, 3, 0, 4, 40, 0, 0, 659, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2062 = STXVPRL
4453 { 2061, 3, 0, 4, 614, 0, 0, 656, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x400ULL }, // Inst #2061 = STXVP
4454 { 2060, 3, 0, 4, 374, 0, 0, 653, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2060 = STXVLL
4455 { 2059, 3, 0, 4, 374, 0, 0, 653, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2059 = STXVL
4456 { 2058, 3, 0, 4, 373, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2058 = STXVH8X
4457 { 2057, 3, 0, 4, 116, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2057 = STXVD2X
4458 { 2056, 3, 0, 4, 373, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2056 = STXVB16X
4459 { 2055, 3, 0, 4, 604, 0, 0, 645, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x400ULL }, // Inst #2055 = STXV
4460 { 2054, 3, 0, 4, 366, 0, 0, 219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2054 = STXSSPX
4461 { 2053, 3, 0, 4, 603, 0, 0, 642, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x400ULL }, // Inst #2053 = STXSSP
4462 { 2052, 3, 0, 4, 366, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2052 = STXSIWX
4463 { 2051, 3, 0, 4, 367, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2051 = STXSIHXv
4464 { 2050, 3, 0, 4, 367, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2050 = STXSIHX
4465 { 2049, 3, 0, 4, 367, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2049 = STXSIBXv
4466 { 2048, 3, 0, 4, 367, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2048 = STXSIBX
4467 { 2047, 3, 0, 4, 368, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2047 = STXSDX
4468 { 2046, 3, 0, 4, 602, 0, 0, 642, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x400ULL }, // Inst #2046 = STXSD
4469 { 2045, 3, 0, 4, 370, 0, 0, 578, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #2045 = STWXTLS_32
4470 { 2044, 3, 0, 4, 370, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #2044 = STWXTLS_
4471 { 2043, 3, 0, 4, 370, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #2043 = STWXTLS
4472 { 2042, 3, 0, 4, 127, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2042 = STWX8
4473 { 2041, 3, 0, 4, 127, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2041 = STWX
4474 { 2040, 4, 1, 4, 133, 0, 0, 1061, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2040 = STWUX8
4475 { 2039, 4, 1, 4, 133, 0, 0, 1057, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2039 = STWUX
4476 { 2038, 4, 1, 4, 132, 0, 0, 1053, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #2038 = STWU8
4477 { 2037, 4, 1, 4, 132, 0, 0, 1049, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #2037 = STWU
4478 { 2036, 3, 0, 4, 217, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2036 = STWEPX
4479 { 2035, 3, 0, 4, 130, 0, 1, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2035 = STWCX
4480 { 2034, 3, 0, 4, 611, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2034 = STWCIX
4481 { 2033, 3, 0, 4, 127, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2033 = STWBRX
4482 { 2032, 3, 0, 4, 404, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2032 = STWAT
4483 { 2031, 3, 0, 4, 596, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #2031 = STW8
4484 { 2030, 3, 0, 4, 596, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #2030 = STW
4485 { 2029, 3, 0, 4, 122, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #2029 = STVXL
4486 { 2028, 3, 0, 4, 122, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #2028 = STVX
4487 { 2027, 3, 0, 4, 122, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #2027 = STVEWX
4488 { 2026, 3, 0, 4, 122, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #2026 = STVEHX
4489 { 2025, 3, 0, 4, 122, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #2025 = STVEBX
4490 { 2024, 3, 0, 4, 221, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2024 = STSWI
4491 { 2023, 3, 0, 4, 0, 0, 0, 630, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #2023 = STQX_PSEUDO
4492 { 2022, 3, 0, 4, 92, 0, 1, 630, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2022 = STQCX
4493 { 2021, 3, 0, 4, 91, 0, 0, 907, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x410ULL }, // Inst #2021 = STQ
4494 { 2020, 0, 0, 4, 425, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2020 = STOP
4495 { 2019, 3, 0, 4, 129, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x400ULL }, // Inst #2019 = STMW
4496 { 2018, 3, 0, 4, 370, 0, 0, 578, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #2018 = STHXTLS_32
4497 { 2017, 3, 0, 4, 370, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #2017 = STHXTLS_
4498 { 2016, 3, 0, 4, 370, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #2016 = STHXTLS
4499 { 2015, 3, 0, 4, 127, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2015 = STHX8
4500 { 2014, 3, 0, 4, 127, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2014 = STHX
4501 { 2013, 4, 1, 4, 133, 0, 0, 1061, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2013 = STHUX8
4502 { 2012, 4, 1, 4, 133, 0, 0, 1057, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2012 = STHUX
4503 { 2011, 4, 1, 4, 132, 0, 0, 1053, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #2011 = STHU8
4504 { 2010, 4, 1, 4, 132, 0, 0, 1049, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #2010 = STHU
4505 { 2009, 3, 0, 4, 217, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2009 = STHEPX
4506 { 2008, 3, 0, 4, 220, 0, 1, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #2008 = STHCX
4507 { 2007, 3, 0, 4, 611, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #2007 = STHCIX
4508 { 2006, 3, 0, 4, 127, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2006 = STHBRX
4509 { 2005, 3, 0, 4, 596, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #2005 = STH8
4510 { 2004, 3, 0, 4, 596, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #2004 = STH
4511 { 2003, 3, 0, 4, 366, 0, 0, 624, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #2003 = STFSXTLS_
4512 { 2002, 3, 0, 4, 366, 0, 0, 624, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #2002 = STFSXTLS
4513 { 2001, 3, 0, 4, 120, 0, 0, 621, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #2001 = STFSX
4514 { 2000, 4, 1, 4, 121, 0, 0, 1077, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #2000 = STFSUX
4515 { 1999, 4, 1, 4, 601, 0, 0, 1073, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1999 = STFSU
4516 { 1998, 3, 0, 4, 600, 0, 0, 610, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1998 = STFS
4517 { 1997, 3, 0, 4, 120, 0, 0, 596, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1997 = STFIWX
4518 { 1996, 3, 0, 4, 366, 0, 0, 607, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1996 = STFDXTLS_
4519 { 1995, 3, 0, 4, 366, 0, 0, 607, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1995 = STFDXTLS
4520 { 1994, 3, 0, 4, 120, 0, 0, 596, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x50ULL }, // Inst #1994 = STFDX
4521 { 1993, 4, 1, 4, 121, 0, 0, 1069, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1993 = STFDUX
4522 { 1992, 4, 1, 4, 601, 0, 0, 1065, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1992 = STFDU
4523 { 1991, 3, 0, 4, 216, 0, 0, 596, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1991 = STFDEPX
4524 { 1990, 3, 0, 4, 600, 0, 0, 593, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1990 = STFD
4525 { 1989, 3, 0, 4, 218, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1989 = STDXTLS_
4526 { 1988, 3, 0, 4, 218, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1988 = STDXTLS
4527 { 1987, 3, 0, 4, 128, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1987 = STDX
4528 { 1986, 4, 1, 4, 133, 0, 0, 1061, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1986 = STDUX
4529 { 1985, 4, 1, 4, 132, 0, 0, 1053, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1985 = STDU
4530 { 1984, 3, 0, 4, 131, 0, 1, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1984 = STDCX
4531 { 1983, 3, 0, 4, 219, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1983 = STDCIX
4532 { 1982, 3, 0, 4, 370, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1982 = STDBRX
4533 { 1981, 3, 0, 4, 404, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1981 = STDAT
4534 { 1980, 3, 0, 4, 598, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1980 = STD
4535 { 1979, 3, 0, 4, 370, 0, 0, 578, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1979 = STBXTLS_32
4536 { 1978, 3, 0, 4, 370, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1978 = STBXTLS_
4537 { 1977, 3, 0, 4, 370, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0xcULL }, // Inst #1977 = STBXTLS
4538 { 1976, 3, 0, 4, 127, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1976 = STBX8
4539 { 1975, 3, 0, 4, 127, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1975 = STBX
4540 { 1974, 4, 1, 4, 133, 0, 0, 1061, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1974 = STBUX8
4541 { 1973, 4, 1, 4, 133, 0, 0, 1057, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x54ULL }, // Inst #1973 = STBUX
4542 { 1972, 4, 1, 4, 132, 0, 0, 1053, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1972 = STBU8
4543 { 1971, 4, 1, 4, 132, 0, 0, 1049, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1971 = STBU
4544 { 1970, 3, 0, 4, 217, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1970 = STBEPX
4545 { 1969, 3, 0, 4, 220, 0, 1, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #1969 = STBCX
4546 { 1968, 3, 0, 4, 219, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1968 = STBCIX
4547 { 1967, 3, 0, 4, 596, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1967 = STB8
4548 { 1966, 3, 0, 4, 596, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x410ULL }, // Inst #1966 = STB
4549 { 1965, 3, 1, 4, 199, 0, 1, 222, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #1965 = SRW_rec
4550 { 1964, 3, 1, 4, 199, 0, 1, 228, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #1964 = SRW8_rec
4551 { 1963, 3, 1, 4, 300, 0, 0, 228, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #1963 = SRW8
4552 { 1962, 3, 1, 4, 300, 0, 0, 222, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #1962 = SRW
4553 { 1961, 3, 1, 4, 482, 0, 1, 1043, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1961 = SRD_rec
4554 { 1960, 3, 1, 4, 283, 0, 0, 1043, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1960 = SRD
4555 { 1959, 3, 1, 4, 147, 0, 2, 222, PPCImpOpBase + 11, 0, 0x108ULL }, // Inst #1959 = SRAW_rec
4556 { 1958, 3, 1, 4, 493, 0, 2, 184, PPCImpOpBase + 11, 0, 0x108ULL }, // Inst #1958 = SRAWI_rec
4557 { 1957, 3, 1, 4, 493, 0, 2, 181, PPCImpOpBase + 11, 0, 0x108ULL }, // Inst #1957 = SRAWI8_rec
4558 { 1956, 3, 1, 4, 514, 0, 1, 181, PPCImpOpBase + 5, 0, 0x108ULL }, // Inst #1956 = SRAWI8
4559 { 1955, 3, 1, 4, 514, 0, 1, 184, PPCImpOpBase + 5, 0, 0x108ULL }, // Inst #1955 = SRAWI
4560 { 1954, 3, 1, 4, 147, 0, 2, 228, PPCImpOpBase + 11, 0, 0x108ULL }, // Inst #1954 = SRAW8_rec
4561 { 1953, 3, 1, 4, 302, 0, 1, 228, PPCImpOpBase + 5, 0, 0x108ULL }, // Inst #1953 = SRAW8
4562 { 1952, 3, 1, 4, 302, 0, 1, 222, PPCImpOpBase + 5, 0, 0x108ULL }, // Inst #1952 = SRAW
4563 { 1951, 3, 1, 4, 146, 0, 2, 1043, PPCImpOpBase + 11, 0, 0x8ULL }, // Inst #1951 = SRAD_rec
4564 { 1950, 3, 1, 4, 145, 0, 2, 181, PPCImpOpBase + 11, 0, 0x8ULL }, // Inst #1950 = SRADI_rec
4565 { 1949, 3, 1, 4, 284, 0, 1, 184, PPCImpOpBase + 5, 0, 0x8ULL }, // Inst #1949 = SRADI_32
4566 { 1948, 3, 1, 4, 284, 0, 1, 181, PPCImpOpBase + 5, 0, 0x8ULL }, // Inst #1948 = SRADI
4567 { 1947, 3, 1, 4, 283, 0, 1, 1043, PPCImpOpBase + 5, 0, 0x8ULL }, // Inst #1947 = SRAD
4568 { 1946, 3, 2, 4, 0, 0, 0, 1046, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1946 = SPLIT_QUADWORD
4569 { 1945, 3, 0, 4, 0, 0, 0, 913, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1945 = SPILL_WACC
4570 { 1944, 3, 0, 4, 0, 0, 0, 910, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1944 = SPILL_UACC
4571 { 1943, 3, 0, 4, 0, 0, 0, 907, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1943 = SPILL_QUADWORD
4572 { 1942, 3, 0, 4, 0, 0, 0, 904, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1942 = SPILL_DMRP
4573 { 1941, 3, 0, 4, 0, 0, 0, 901, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1941 = SPILL_DMR
4574 { 1940, 3, 0, 4, 0, 0, 0, 898, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1940 = SPILL_CRBIT
4575 { 1939, 3, 0, 4, 0, 0, 0, 895, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1939 = SPILL_CR
4576 { 1938, 3, 0, 4, 0, 0, 0, 892, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1938 = SPILL_ACC
4577 { 1937, 3, 0, 4, 25, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1937 = SPESTWX
4578 { 1936, 3, 0, 4, 25, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x400ULL }, // Inst #1936 = SPESTW
4579 { 1935, 3, 1, 4, 15, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1935 = SPELWZX
4580 { 1934, 3, 1, 4, 15, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x400ULL }, // Inst #1934 = SPELWZ
4581 { 1933, 3, 1, 4, 199, 0, 1, 222, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #1933 = SLW_rec
4582 { 1932, 3, 1, 4, 199, 0, 1, 228, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #1932 = SLW8_rec
4583 { 1931, 3, 1, 4, 300, 0, 0, 228, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #1931 = SLW8
4584 { 1930, 3, 1, 4, 300, 0, 0, 222, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #1930 = SLW
4585 { 1929, 3, 1, 4, 482, 0, 1, 1043, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1929 = SLD_rec
4586 { 1928, 3, 1, 4, 283, 0, 0, 1043, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1928 = SLD
4587 { 1927, 0, 0, 4, 423, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1927 = SLBSYNC
4588 { 1926, 2, 0, 4, 353, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1926 = SLBMTE
4589 { 1925, 2, 1, 4, 352, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1925 = SLBMFEV
4590 { 1924, 2, 1, 4, 351, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1924 = SLBMFEE
4591 { 1923, 2, 0, 4, 371, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1923 = SLBIEG
4592 { 1922, 1, 0, 4, 350, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1922 = SLBIE
4593 { 1921, 0, 0, 4, 349, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1921 = SLBIA
4594 { 1920, 2, 1, 4, 424, 0, 1, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1920 = SLBFEE_rec
4595 { 1919, 2, 1, 4, 0, 1, 1, 680, PPCImpOpBase + 205, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1919 = SETRNDi
4596 { 1918, 2, 1, 4, 0, 1, 1, 1041, PPCImpOpBase + 205, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1918 = SETRND
4597 { 1917, 2, 1, 4, 513, 0, 0, 1039, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1917 = SETNBCR8
4598 { 1916, 2, 1, 4, 513, 0, 0, 1037, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1916 = SETNBCR
4599 { 1915, 2, 1, 4, 513, 0, 0, 1039, PPCImpOpBase + 0, 0, 0x100ULL }, // Inst #1915 = SETNBC8
4600 { 1914, 2, 1, 4, 513, 0, 0, 1037, PPCImpOpBase + 0, 0, 0x100ULL }, // Inst #1914 = SETNBC
4601 { 1913, 2, 1, 4, 0, 1, 1, 345, PPCImpOpBase + 205, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1913 = SETFLM
4602 { 1912, 2, 1, 4, 513, 0, 0, 1039, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL }, // Inst #1912 = SETBCR8
4603 { 1911, 2, 1, 4, 513, 0, 0, 1037, PPCImpOpBase + 0, 0, 0x300ULL }, // Inst #1911 = SETBCR
4604 { 1910, 2, 1, 4, 513, 0, 0, 1039, PPCImpOpBase + 0, 0, 0x300ULL }, // Inst #1910 = SETBC8
4605 { 1909, 2, 1, 4, 513, 0, 0, 1037, PPCImpOpBase + 0, 0, 0x300ULL }, // Inst #1909 = SETBC
4606 { 1908, 2, 1, 4, 512, 0, 0, 1035, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1908 = SETB8
4607 { 1907, 2, 1, 4, 512, 0, 0, 1033, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // Inst #1907 = SETB
4608 { 1906, 4, 1, 4, 0, 0, 0, 1005, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1906 = SELECT_VSSRC
4609 { 1905, 4, 1, 4, 0, 0, 0, 1029, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1905 = SELECT_VSRC
4610 { 1904, 4, 1, 4, 0, 0, 0, 1009, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1904 = SELECT_VSFRC
4611 { 1903, 4, 1, 4, 0, 0, 0, 1001, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1903 = SELECT_VRRC
4612 { 1902, 4, 1, 4, 0, 0, 0, 1025, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1902 = SELECT_SPE4
4613 { 1901, 4, 1, 4, 0, 0, 0, 1021, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1901 = SELECT_SPE
4614 { 1900, 4, 1, 4, 0, 0, 0, 1017, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1900 = SELECT_I8
4615 { 1899, 4, 1, 4, 0, 0, 0, 1013, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1899 = SELECT_I4
4616 { 1898, 4, 1, 4, 0, 0, 0, 1009, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1898 = SELECT_F8
4617 { 1897, 4, 1, 4, 0, 0, 0, 1005, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1897 = SELECT_F4
4618 { 1896, 4, 1, 4, 0, 0, 0, 1001, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL }, // Inst #1896 = SELECT_F16
4619 { 1895, 5, 1, 4, 0, 0, 0, 966, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1895 = SELECT_CC_VSSRC
4620 { 1894, 5, 1, 4, 0, 0, 0, 996, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1894 = SELECT_CC_VSRC
4621 { 1893, 5, 1, 4, 0, 0, 0, 971, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1893 = SELECT_CC_VSFRC
4622 { 1892, 5, 1, 4, 0, 0, 0, 961, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1892 = SELECT_CC_VRRC
4623 { 1891, 5, 1, 4, 0, 0, 0, 991, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1891 = SELECT_CC_SPE4
4624 { 1890, 5, 1, 4, 0, 0, 0, 986, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1890 = SELECT_CC_SPE
4625 { 1889, 5, 1, 4, 0, 0, 0, 981, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1889 = SELECT_CC_I8
4626 { 1888, 5, 1, 4, 0, 0, 0, 976, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1888 = SELECT_CC_I4
4627 { 1887, 5, 1, 4, 0, 0, 0, 971, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1887 = SELECT_CC_F8
4628 { 1886, 5, 1, 4, 0, 0, 0, 966, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1886 = SELECT_CC_F4
4629 { 1885, 5, 1, 4, 0, 0, 0, 961, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1885 = SELECT_CC_F16
4630 { 1884, 1, 0, 4, 4, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1884 = SCV
4631 { 1883, 1, 0, 4, 535, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #1883 = SC
4632 { 1882, 2, 2, 4, 0, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1882 = ReadTB
4633 { 1881, 5, 1, 4, 199, 0, 1, 951, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1881 = RLWNM_rec
4634 { 1880, 5, 1, 4, 199, 0, 1, 956, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1880 = RLWNM8_rec
4635 { 1879, 5, 1, 4, 300, 0, 0, 956, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1879 = RLWNM8
4636 { 1878, 5, 1, 4, 300, 0, 0, 951, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1878 = RLWNM
4637 { 1877, 5, 1, 4, 474, 0, 1, 941, PPCImpOpBase + 0, 0, 0xcULL }, // Inst #1877 = RLWINM_rec
4638 { 1876, 5, 1, 4, 474, 0, 1, 946, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1876 = RLWINM8_rec
4639 { 1875, 5, 1, 4, 511, 0, 0, 946, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1875 = RLWINM8
4640 { 1874, 5, 1, 4, 511, 0, 0, 941, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1874 = RLWINM
4641 { 1873, 6, 1, 4, 204, 0, 1, 929, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #1873 = RLWIMI_rec
4642 { 1872, 6, 1, 4, 204, 0, 1, 935, PPCImpOpBase + 0, 0, 0xcULL }, // Inst #1872 = RLWIMI8_rec
4643 { 1871, 6, 1, 4, 197, 0, 0, 935, PPCImpOpBase + 0, 0, 0xcULL }, // Inst #1871 = RLWIMI8
4644 { 1870, 6, 1, 4, 197, 0, 0, 929, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #1870 = RLWIMI
4645 { 1869, 5, 1, 4, 393, 0, 1, 924, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1869 = RLDIMI_rec
4646 { 1868, 5, 1, 4, 298, 0, 0, 924, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1868 = RLDIMI
4647 { 1867, 4, 1, 4, 472, 0, 1, 173, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1867 = RLDIC_rec
4648 { 1866, 4, 1, 4, 473, 0, 1, 173, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1866 = RLDICR_rec
4649 { 1865, 4, 1, 4, 510, 0, 0, 177, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1865 = RLDICR_32
4650 { 1864, 4, 1, 4, 510, 0, 0, 173, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1864 = RLDICR
4651 { 1863, 4, 1, 4, 473, 0, 1, 173, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1863 = RLDICL_rec
4652 { 1862, 4, 1, 4, 473, 0, 1, 177, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1862 = RLDICL_32_rec
4653 { 1861, 4, 1, 4, 510, 0, 0, 920, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1861 = RLDICL_32_64
4654 { 1860, 4, 1, 4, 510, 0, 0, 177, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1860 = RLDICL_32
4655 { 1859, 4, 1, 4, 510, 0, 0, 173, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1859 = RLDICL
4656 { 1858, 4, 1, 4, 284, 0, 0, 173, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1858 = RLDIC
4657 { 1857, 4, 1, 4, 392, 0, 1, 916, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1857 = RLDCR_rec
4658 { 1856, 4, 1, 4, 297, 0, 0, 916, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1856 = RLDCR
4659 { 1855, 4, 1, 4, 392, 0, 1, 916, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1855 = RLDCL_rec
4660 { 1854, 4, 1, 4, 297, 0, 0, 916, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1854 = RLDCL
4661 { 1853, 0, 0, 4, 410, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1853 = RFMCI
4662 { 1852, 0, 0, 4, 412, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1852 = RFID
4663 { 1851, 0, 0, 4, 411, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1851 = RFI
4664 { 1850, 1, 0, 4, 294, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1850 = RFEBB
4665 { 1849, 0, 0, 4, 410, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1849 = RFDI
4666 { 1848, 0, 0, 4, 410, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1848 = RFCI
4667 { 1847, 3, 1, 4, 0, 0, 0, 913, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1847 = RESTORE_WACC
4668 { 1846, 3, 1, 4, 0, 0, 0, 910, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1846 = RESTORE_UACC
4669 { 1845, 3, 1, 4, 0, 0, 0, 907, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1845 = RESTORE_QUADWORD
4670 { 1844, 3, 1, 4, 0, 0, 0, 904, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1844 = RESTORE_DMRP
4671 { 1843, 3, 1, 4, 0, 0, 0, 901, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1843 = RESTORE_DMR
4672 { 1842, 3, 1, 4, 0, 0, 0, 898, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1842 = RESTORE_CRBIT
4673 { 1841, 3, 1, 4, 0, 0, 0, 895, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1841 = RESTORE_CR
4674 { 1840, 3, 1, 4, 0, 0, 0, 892, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1840 = RESTORE_ACC
4675 { 1839, 0, 0, 4, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1839 = PseudoEIEIO
4676 { 1838, 3, 0, 8, 613, 0, 0, 779, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1838 = PSTXVpc
4677 { 1837, 2, 0, 8, 40, 0, 0, 651, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1837 = PSTXVonlypc
4678 { 1836, 3, 0, 8, 40, 0, 0, 768, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1836 = PSTXVnopc
4679 { 1835, 3, 0, 8, 595, 0, 0, 776, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1835 = PSTXVPpc
4680 { 1834, 2, 0, 8, 40, 0, 0, 774, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1834 = PSTXVPonlypc
4681 { 1833, 3, 0, 8, 40, 0, 0, 771, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1833 = PSTXVPnopc
4682 { 1832, 3, 0, 8, 595, 0, 0, 771, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1832 = PSTXVP
4683 { 1831, 3, 0, 8, 613, 0, 0, 768, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1831 = PSTXV
4684 { 1830, 3, 0, 8, 613, 0, 0, 765, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1830 = PSTXSSPpc
4685 { 1829, 2, 0, 8, 40, 0, 0, 763, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1829 = PSTXSSPonlypc
4686 { 1828, 3, 0, 8, 40, 0, 0, 760, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1828 = PSTXSSPnopc
4687 { 1827, 3, 0, 8, 613, 0, 0, 760, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1827 = PSTXSSP
4688 { 1826, 3, 0, 8, 613, 0, 0, 765, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1826 = PSTXSDpc
4689 { 1825, 2, 0, 8, 40, 0, 0, 763, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1825 = PSTXSDonlypc
4690 { 1824, 3, 0, 8, 40, 0, 0, 760, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1824 = PSTXSDnopc
4691 { 1823, 3, 0, 8, 613, 0, 0, 760, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1823 = PSTXSD
4692 { 1822, 3, 0, 8, 613, 0, 0, 743, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1822 = PSTWpc
4693 { 1821, 2, 0, 8, 40, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1821 = PSTWonlypc
4694 { 1820, 3, 0, 8, 40, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1820 = PSTWnopc
4695 { 1819, 3, 0, 8, 613, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1819 = PSTW8pc
4696 { 1818, 2, 0, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1818 = PSTW8onlypc
4697 { 1817, 3, 0, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1817 = PSTW8nopc
4698 { 1816, 3, 0, 8, 613, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1816 = PSTW8
4699 { 1815, 3, 0, 8, 613, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1815 = PSTW
4700 { 1814, 3, 0, 8, 613, 0, 0, 743, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1814 = PSTHpc
4701 { 1813, 2, 0, 8, 40, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1813 = PSTHonlypc
4702 { 1812, 3, 0, 8, 40, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1812 = PSTHnopc
4703 { 1811, 3, 0, 8, 613, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1811 = PSTH8pc
4704 { 1810, 2, 0, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1810 = PSTH8onlypc
4705 { 1809, 3, 0, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1809 = PSTH8nopc
4706 { 1808, 3, 0, 8, 613, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1808 = PSTH8
4707 { 1807, 3, 0, 8, 613, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1807 = PSTH
4708 { 1806, 3, 0, 8, 613, 0, 0, 757, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1806 = PSTFSpc
4709 { 1805, 2, 0, 8, 40, 0, 0, 755, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1805 = PSTFSonlypc
4710 { 1804, 3, 0, 8, 40, 0, 0, 752, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1804 = PSTFSnopc
4711 { 1803, 3, 0, 8, 613, 0, 0, 752, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1803 = PSTFS
4712 { 1802, 3, 0, 8, 613, 0, 0, 749, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1802 = PSTFDpc
4713 { 1801, 2, 0, 8, 40, 0, 0, 680, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1801 = PSTFDonlypc
4714 { 1800, 3, 0, 8, 40, 0, 0, 746, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1800 = PSTFDnopc
4715 { 1799, 3, 0, 8, 613, 0, 0, 746, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1799 = PSTFD
4716 { 1798, 3, 0, 8, 613, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1798 = PSTDpc
4717 { 1797, 2, 0, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1797 = PSTDonlypc
4718 { 1796, 3, 0, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1796 = PSTDnopc
4719 { 1795, 3, 0, 8, 613, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1795 = PSTD
4720 { 1794, 3, 0, 8, 613, 0, 0, 743, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1794 = PSTBpc
4721 { 1793, 2, 0, 8, 40, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1793 = PSTBonlypc
4722 { 1792, 3, 0, 8, 40, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1792 = PSTBnopc
4723 { 1791, 3, 0, 8, 613, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1791 = PSTB8pc
4724 { 1790, 2, 0, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1790 = PSTB8onlypc
4725 { 1789, 3, 0, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1789 = PSTB8nopc
4726 { 1788, 3, 0, 8, 613, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1788 = PSTB8
4727 { 1787, 3, 0, 8, 613, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x480ULL }, // Inst #1787 = PSTB
4728 { 1786, 3, 2, 4, 0, 1, 1, 181, PPCImpOpBase + 132, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1786 = PROBED_STACKALLOC_64
4729 { 1785, 3, 2, 4, 0, 1, 1, 184, PPCImpOpBase + 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1785 = PROBED_STACKALLOC_32
4730 { 1784, 4, 1, 4, 0, 1, 1, 468, PPCImpOpBase + 132, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1784 = PROBED_ALLOCA_64
4731 { 1783, 4, 1, 4, 0, 1, 1, 464, PPCImpOpBase + 61, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1783 = PROBED_ALLOCA_32
4732 { 1782, 5, 2, 4, 0, 1, 1, 887, PPCImpOpBase + 132, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1782 = PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64
4733 { 1781, 5, 2, 4, 0, 1, 1, 882, PPCImpOpBase + 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1781 = PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32
4734 { 1780, 5, 2, 4, 0, 1, 1, 877, PPCImpOpBase + 132, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1780 = PREPARE_PROBED_ALLOCA_64
4735 { 1779, 5, 2, 4, 0, 1, 1, 872, PPCImpOpBase + 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1779 = PREPARE_PROBED_ALLOCA_32
4736 { 1778, 2, 2, 4, 0, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1778 = PPC32PICGOT
4737 { 1777, 1, 1, 4, 0, 0, 0, 171, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1777 = PPC32GOT
4738 { 1776, 2, 1, 4, 280, 0, 0, 259, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1776 = POPCNTW
4739 { 1775, 2, 1, 4, 280, 0, 0, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #1775 = POPCNTD
4740 { 1774, 2, 1, 4, 206, 0, 0, 261, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1774 = POPCNTB8
4741 { 1773, 2, 1, 4, 206, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1773 = POPCNTB
4742 { 1772, 7, 1, 8, 19, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1772 = PMXVI8GER4WSPP
4743 { 1771, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1771 = PMXVI8GER4WPP
4744 { 1770, 6, 1, 8, 5, 0, 0, 808, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1770 = PMXVI8GER4W
4745 { 1769, 7, 1, 8, 569, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1769 = PMXVI8GER4SPP
4746 { 1768, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1768 = PMXVI8GER4PP
4747 { 1767, 6, 1, 8, 567, 0, 0, 795, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1767 = PMXVI8GER4
4748 { 1766, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1766 = PMXVI4GER8WPP
4749 { 1765, 6, 1, 8, 5, 0, 0, 808, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1765 = PMXVI4GER8W
4750 { 1764, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1764 = PMXVI4GER8PP
4751 { 1763, 6, 1, 8, 567, 0, 0, 795, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1763 = PMXVI4GER8
4752 { 1762, 7, 1, 8, 5, 0, 0, 865, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1762 = PMXVI16GER2WPP
4753 { 1761, 6, 1, 8, 5, 0, 0, 808, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1761 = PMXVI16GER2W
4754 { 1760, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1760 = PMXVI16GER2SWPP
4755 { 1759, 6, 1, 8, 5, 0, 0, 808, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1759 = PMXVI16GER2SW
4756 { 1758, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1758 = PMXVI16GER2SPP
4757 { 1757, 6, 1, 8, 567, 0, 0, 795, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1757 = PMXVI16GER2S
4758 { 1756, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1756 = PMXVI16GER2PP
4759 { 1755, 6, 1, 8, 567, 0, 0, 795, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1755 = PMXVI16GER2
4760 { 1754, 6, 1, 8, 5, 0, 0, 859, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1754 = PMXVF64GERWPP
4761 { 1753, 6, 1, 8, 5, 0, 0, 859, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1753 = PMXVF64GERWPN
4762 { 1752, 6, 1, 8, 5, 0, 0, 859, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1752 = PMXVF64GERWNP
4763 { 1751, 6, 1, 8, 5, 0, 0, 859, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1751 = PMXVF64GERWNN
4764 { 1750, 5, 1, 8, 5, 0, 0, 854, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1750 = PMXVF64GERW
4765 { 1749, 6, 1, 8, 568, 0, 0, 848, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1749 = PMXVF64GERPP
4766 { 1748, 6, 1, 8, 568, 0, 0, 848, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1748 = PMXVF64GERPN
4767 { 1747, 6, 1, 8, 568, 0, 0, 848, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1747 = PMXVF64GERNP
4768 { 1746, 6, 1, 8, 568, 0, 0, 848, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1746 = PMXVF64GERNN
4769 { 1745, 5, 1, 8, 567, 0, 0, 843, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1745 = PMXVF64GER
4770 { 1744, 6, 1, 8, 5, 0, 0, 837, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1744 = PMXVF32GERWPP
4771 { 1743, 6, 1, 8, 5, 0, 0, 837, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1743 = PMXVF32GERWPN
4772 { 1742, 6, 1, 8, 5, 0, 0, 837, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1742 = PMXVF32GERWNP
4773 { 1741, 6, 1, 8, 5, 0, 0, 837, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1741 = PMXVF32GERWNN
4774 { 1740, 5, 1, 8, 5, 0, 0, 832, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1740 = PMXVF32GERW
4775 { 1739, 6, 1, 8, 568, 0, 0, 826, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1739 = PMXVF32GERPP
4776 { 1738, 6, 1, 8, 568, 0, 0, 826, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1738 = PMXVF32GERPN
4777 { 1737, 6, 1, 8, 568, 0, 0, 826, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1737 = PMXVF32GERNP
4778 { 1736, 6, 1, 8, 568, 0, 0, 826, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1736 = PMXVF32GERNN
4779 { 1735, 5, 1, 8, 567, 0, 0, 821, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1735 = PMXVF32GER
4780 { 1734, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1734 = PMXVF16GER2WPP
4781 { 1733, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1733 = PMXVF16GER2WPN
4782 { 1732, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1732 = PMXVF16GER2WNP
4783 { 1731, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1731 = PMXVF16GER2WNN
4784 { 1730, 6, 1, 8, 5, 0, 0, 808, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1730 = PMXVF16GER2W
4785 { 1729, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1729 = PMXVF16GER2PP
4786 { 1728, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1728 = PMXVF16GER2PN
4787 { 1727, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1727 = PMXVF16GER2NP
4788 { 1726, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1726 = PMXVF16GER2NN
4789 { 1725, 6, 1, 8, 567, 0, 0, 795, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1725 = PMXVF16GER2
4790 { 1724, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1724 = PMXVBF16GER2WPP
4791 { 1723, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1723 = PMXVBF16GER2WPN
4792 { 1722, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1722 = PMXVBF16GER2WNP
4793 { 1721, 7, 1, 8, 5, 0, 0, 814, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1721 = PMXVBF16GER2WNN
4794 { 1720, 6, 1, 8, 5, 0, 0, 808, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1720 = PMXVBF16GER2W
4795 { 1719, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1719 = PMXVBF16GER2PP
4796 { 1718, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1718 = PMXVBF16GER2PN
4797 { 1717, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1717 = PMXVBF16GER2NP
4798 { 1716, 7, 1, 8, 568, 0, 0, 801, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1716 = PMXVBF16GER2NN
4799 { 1715, 6, 1, 8, 567, 0, 0, 795, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1715 = PMXVBF16GER2
4800 { 1714, 7, 1, 8, 19, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1714 = PMDMXVI8GERX4SPP
4801 { 1713, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1713 = PMDMXVI8GERX4PP
4802 { 1712, 6, 1, 8, 5, 0, 0, 782, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1712 = PMDMXVI8GERX4
4803 { 1711, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1711 = PMDMXVF16GERX2PP
4804 { 1710, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1710 = PMDMXVF16GERX2PN
4805 { 1709, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1709 = PMDMXVF16GERX2NP
4806 { 1708, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1708 = PMDMXVF16GERX2NN
4807 { 1707, 6, 1, 8, 5, 0, 0, 782, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1707 = PMDMXVF16GERX2
4808 { 1706, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1706 = PMDMXVBF16GERX2PP
4809 { 1705, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1705 = PMDMXVBF16GERX2PN
4810 { 1704, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1704 = PMDMXVBF16GERX2NP
4811 { 1703, 7, 1, 8, 5, 0, 0, 788, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1703 = PMDMXVBF16GERX2NN
4812 { 1702, 6, 1, 8, 5, 0, 0, 782, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1702 = PMDMXVBF16GERX2
4813 { 1701, 3, 1, 8, 556, 0, 0, 779, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1701 = PLXVpc
4814 { 1700, 2, 1, 8, 40, 0, 0, 651, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1700 = PLXVonlypc
4815 { 1699, 3, 1, 8, 40, 0, 0, 768, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1699 = PLXVnopc
4816 { 1698, 3, 1, 8, 556, 0, 0, 776, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1698 = PLXVPpc
4817 { 1697, 2, 1, 8, 40, 0, 0, 774, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1697 = PLXVPonlypc
4818 { 1696, 3, 1, 8, 40, 0, 0, 771, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1696 = PLXVPnopc
4819 { 1695, 3, 1, 8, 556, 0, 0, 771, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1695 = PLXVP
4820 { 1694, 3, 1, 8, 556, 0, 0, 768, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1694 = PLXV
4821 { 1693, 3, 1, 8, 556, 0, 0, 765, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1693 = PLXSSPpc
4822 { 1692, 2, 1, 8, 40, 0, 0, 763, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1692 = PLXSSPonlypc
4823 { 1691, 3, 1, 8, 40, 0, 0, 760, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1691 = PLXSSPnopc
4824 { 1690, 3, 1, 8, 556, 0, 0, 760, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1690 = PLXSSP
4825 { 1689, 3, 1, 8, 556, 0, 0, 765, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1689 = PLXSDpc
4826 { 1688, 2, 1, 8, 40, 0, 0, 763, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1688 = PLXSDonlypc
4827 { 1687, 3, 1, 8, 40, 0, 0, 760, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1687 = PLXSDnopc
4828 { 1686, 3, 1, 8, 556, 0, 0, 760, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1686 = PLXSD
4829 { 1685, 3, 1, 8, 556, 0, 0, 743, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1685 = PLWZpc
4830 { 1684, 2, 1, 8, 40, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1684 = PLWZonlypc
4831 { 1683, 3, 1, 8, 40, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1683 = PLWZnopc
4832 { 1682, 3, 1, 8, 556, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1682 = PLWZ8pc
4833 { 1681, 2, 1, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1681 = PLWZ8onlypc
4834 { 1680, 3, 1, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1680 = PLWZ8nopc
4835 { 1679, 3, 1, 8, 556, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1679 = PLWZ8
4836 { 1678, 3, 1, 8, 556, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1678 = PLWZ
4837 { 1677, 3, 1, 8, 556, 0, 0, 743, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1677 = PLWApc
4838 { 1676, 2, 1, 8, 40, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1676 = PLWAonlypc
4839 { 1675, 3, 1, 8, 40, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1675 = PLWAnopc
4840 { 1674, 3, 1, 8, 556, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1674 = PLWA8pc
4841 { 1673, 2, 1, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1673 = PLWA8onlypc
4842 { 1672, 3, 1, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1672 = PLWA8nopc
4843 { 1671, 3, 1, 8, 556, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1671 = PLWA8
4844 { 1670, 3, 1, 8, 556, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1670 = PLWA
4845 { 1669, 2, 1, 8, 621, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #1669 = PLI8
4846 { 1668, 2, 1, 8, 621, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL }, // Inst #1668 = PLI
4847 { 1667, 3, 1, 8, 556, 0, 0, 743, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1667 = PLHZpc
4848 { 1666, 2, 1, 8, 40, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1666 = PLHZonlypc
4849 { 1665, 3, 1, 8, 40, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1665 = PLHZnopc
4850 { 1664, 3, 1, 8, 556, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1664 = PLHZ8pc
4851 { 1663, 2, 1, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1663 = PLHZ8onlypc
4852 { 1662, 3, 1, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1662 = PLHZ8nopc
4853 { 1661, 3, 1, 8, 556, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1661 = PLHZ8
4854 { 1660, 3, 1, 8, 556, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1660 = PLHZ
4855 { 1659, 3, 1, 8, 556, 0, 0, 743, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1659 = PLHApc
4856 { 1658, 2, 1, 8, 40, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1658 = PLHAonlypc
4857 { 1657, 3, 1, 8, 40, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1657 = PLHAnopc
4858 { 1656, 3, 1, 8, 556, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1656 = PLHA8pc
4859 { 1655, 2, 1, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1655 = PLHA8onlypc
4860 { 1654, 3, 1, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1654 = PLHA8nopc
4861 { 1653, 3, 1, 8, 556, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1653 = PLHA8
4862 { 1652, 3, 1, 8, 556, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1652 = PLHA
4863 { 1651, 3, 1, 8, 556, 0, 0, 757, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1651 = PLFSpc
4864 { 1650, 2, 1, 8, 40, 0, 0, 755, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1650 = PLFSonlypc
4865 { 1649, 3, 1, 8, 40, 0, 0, 752, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1649 = PLFSnopc
4866 { 1648, 3, 1, 8, 556, 0, 0, 752, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1648 = PLFS
4867 { 1647, 3, 1, 8, 556, 0, 0, 749, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1647 = PLFDpc
4868 { 1646, 2, 1, 8, 40, 0, 0, 680, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1646 = PLFDonlypc
4869 { 1645, 3, 1, 8, 40, 0, 0, 746, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1645 = PLFDnopc
4870 { 1644, 3, 1, 8, 556, 0, 0, 746, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1644 = PLFD
4871 { 1643, 3, 1, 8, 556, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1643 = PLDpc
4872 { 1642, 2, 1, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1642 = PLDonlypc
4873 { 1641, 3, 1, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1641 = PLDnopc
4874 { 1640, 3, 1, 8, 556, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1640 = PLD
4875 { 1639, 3, 1, 8, 556, 0, 0, 743, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1639 = PLBZpc
4876 { 1638, 2, 1, 8, 40, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1638 = PLBZonlypc
4877 { 1637, 3, 1, 8, 40, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1637 = PLBZnopc
4878 { 1636, 3, 1, 8, 556, 0, 0, 740, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1636 = PLBZ8pc
4879 { 1635, 2, 1, 8, 40, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1635 = PLBZ8onlypc
4880 { 1634, 3, 1, 8, 40, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1634 = PLBZ8nopc
4881 { 1633, 3, 1, 8, 556, 0, 0, 737, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1633 = PLBZ8
4882 { 1632, 3, 1, 8, 556, 0, 0, 734, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x480ULL }, // Inst #1632 = PLBZ
4883 { 1631, 2, 1, 8, 2, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1631 = PLApc
4884 { 1630, 2, 1, 8, 2, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1630 = PLA8pc
4885 { 1629, 3, 1, 8, 2, 0, 0, 208, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1629 = PLA8
4886 { 1628, 3, 1, 8, 2, 0, 0, 245, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x480ULL }, // Inst #1628 = PLA
4887 { 1627, 3, 1, 4, 449, 0, 0, 228, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1627 = PEXTD
4888 { 1626, 3, 1, 4, 449, 0, 0, 228, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1626 = PDEPD
4889 { 1625, 3, 1, 8, 620, 0, 0, 676, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1625 = PADDIpc
4890 { 1624, 3, 1, 4, 0, 0, 0, 208, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1624 = PADDIdtprel
4891 { 1623, 3, 1, 8, 620, 0, 0, 731, PPCImpOpBase + 0, 0, 0x80ULL }, // Inst #1623 = PADDI8pc
4892 { 1622, 3, 1, 8, 620, 0, 0, 208, PPCImpOpBase + 0, 0, 0x80ULL }, // Inst #1622 = PADDI8
4893 { 1621, 3, 1, 8, 620, 0, 0, 245, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL }, // Inst #1621 = PADDI
4894 { 1620, 3, 1, 4, 201, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1620 = OR_rec
4895 { 1619, 3, 1, 4, 508, 0, 0, 181, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1619 = ORIS8
4896 { 1618, 3, 1, 4, 508, 0, 0, 184, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1618 = ORIS
4897 { 1617, 3, 1, 4, 508, 0, 0, 181, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1617 = ORI8
4898 { 1616, 3, 1, 4, 508, 0, 0, 184, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1616 = ORI
4899 { 1615, 3, 1, 4, 198, 0, 1, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1615 = ORC_rec
4900 { 1614, 3, 1, 4, 198, 0, 1, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1614 = ORC8_rec
4901 { 1613, 3, 1, 4, 198, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1613 = ORC8
4902 { 1612, 3, 1, 4, 198, 0, 0, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1612 = ORC
4903 { 1611, 3, 1, 4, 201, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1611 = OR8_rec
4904 { 1610, 3, 1, 4, 201, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1610 = OR8
4905 { 1609, 3, 1, 4, 201, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1609 = OR
4906 { 1608, 3, 1, 4, 198, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1608 = NOR_rec
4907 { 1607, 3, 1, 4, 198, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1607 = NOR8_rec
4908 { 1606, 3, 1, 4, 198, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1606 = NOR8
4909 { 1605, 3, 1, 4, 198, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1605 = NOR
4910 { 1604, 0, 0, 4, 418, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1604 = NOP_GT_PWR7
4911 { 1603, 0, 0, 4, 418, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1603 = NOP_GT_PWR6
4912 { 1602, 0, 0, 4, 509, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #1602 = NOP
4913 { 1601, 2, 1, 4, 508, 0, 1, 259, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1601 = NEG_rec
4914 { 1600, 2, 1, 4, 533, 0, 2, 259, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #1600 = NEGO_rec
4915 { 1599, 2, 1, 4, 498, 0, 1, 259, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #1599 = NEGO
4916 { 1598, 2, 1, 4, 508, 0, 1, 261, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1598 = NEG8_rec
4917 { 1597, 2, 1, 4, 533, 0, 2, 261, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #1597 = NEG8O_rec
4918 { 1596, 2, 1, 4, 498, 0, 1, 261, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #1596 = NEG8O
4919 { 1595, 2, 1, 4, 498, 0, 0, 261, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1595 = NEG8
4920 { 1594, 2, 1, 4, 498, 0, 0, 259, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1594 = NEG
4921 { 1593, 0, 0, 4, 616, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1593 = NAP
4922 { 1592, 3, 1, 4, 198, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1592 = NAND_rec
4923 { 1591, 3, 1, 4, 198, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1591 = NAND8_rec
4924 { 1590, 3, 1, 4, 198, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1590 = NAND8
4925 { 1589, 3, 1, 4, 198, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1589 = NAND
4926 { 1588, 0, 0, 4, 0, 0, 1, 1, PPCImpOpBase + 204, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #1588 = MovePCtoLR8
4927 { 1587, 0, 0, 4, 0, 0, 1, 1, PPCImpOpBase + 203, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #1587 = MovePCtoLR
4928 { 1586, 0, 0, 4, 0, 0, 1, 1, PPCImpOpBase + 203, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #1586 = MoveGOTtoLR
4929 { 1585, 3, 1, 4, 150, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1585 = MULLW_rec
4930 { 1584, 3, 1, 4, 150, 0, 2, 222, PPCImpOpBase + 3, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1584 = MULLWO_rec
4931 { 1583, 3, 1, 4, 312, 0, 1, 222, PPCImpOpBase + 2, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1583 = MULLWO
4932 { 1582, 3, 1, 4, 312, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1582 = MULLW
4933 { 1581, 3, 1, 4, 149, 0, 0, 181, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1581 = MULLI8
4934 { 1580, 3, 1, 4, 149, 0, 0, 184, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1580 = MULLI
4935 { 1579, 3, 1, 4, 152, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1579 = MULLD_rec
4936 { 1578, 3, 1, 4, 152, 0, 2, 228, PPCImpOpBase + 3, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1578 = MULLDO_rec
4937 { 1577, 3, 1, 4, 314, 0, 1, 228, PPCImpOpBase + 2, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1577 = MULLDO
4938 { 1576, 3, 1, 4, 314, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1576 = MULLD
4939 { 1575, 3, 1, 4, 150, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1575 = MULHW_rec
4940 { 1574, 3, 1, 4, 151, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1574 = MULHWU_rec
4941 { 1573, 3, 1, 4, 313, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1573 = MULHWU
4942 { 1572, 3, 1, 4, 312, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1572 = MULHW
4943 { 1571, 3, 1, 4, 150, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1571 = MULHD_rec
4944 { 1570, 3, 1, 4, 151, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1570 = MULHDU_rec
4945 { 1569, 3, 1, 4, 313, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1569 = MULHDU
4946 { 1568, 3, 1, 4, 312, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #1568 = MULHD
4947 { 1567, 2, 1, 4, 259, 0, 0, 729, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1567 = MTVSRWZ
4948 { 1566, 2, 1, 4, 578, 0, 0, 718, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1566 = MTVSRWS
4949 { 1565, 2, 1, 4, 471, 0, 0, 720, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1565 = MTVSRWM
4950 { 1564, 2, 1, 4, 259, 0, 0, 729, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1564 = MTVSRWA
4951 { 1563, 2, 1, 4, 471, 0, 0, 720, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1563 = MTVSRQM
4952 { 1562, 2, 1, 4, 471, 0, 0, 720, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1562 = MTVSRHM
4953 { 1561, 2, 1, 4, 471, 0, 0, 720, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1561 = MTVSRDM
4954 { 1560, 3, 1, 4, 262, 0, 0, 726, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1560 = MTVSRDD
4955 { 1559, 2, 1, 4, 259, 0, 0, 724, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1559 = MTVSRD
4956 { 1558, 2, 1, 4, 468, 0, 0, 722, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1558 = MTVSRBMI
4957 { 1557, 2, 1, 4, 471, 0, 0, 720, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1557 = MTVSRBM
4958 { 1556, 1, 0, 4, 236, 0, 0, 692, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1556 = MTVSCR
4959 { 1555, 2, 1, 4, 259, 0, 0, 718, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1555 = MTVRWZ
4960 { 1554, 2, 1, 4, 259, 0, 0, 718, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1554 = MTVRWA
4961 { 1553, 2, 1, 4, 554, 0, 0, 716, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL }, // Inst #1553 = MTVRSAVEv
4962 { 1552, 1, 0, 4, 554, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL }, // Inst #1552 = MTVRSAVE
4963 { 1551, 2, 1, 4, 259, 0, 0, 714, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1551 = MTVRD
4964 { 1550, 1, 0, 4, 382, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL }, // Inst #1550 = MTUDSCR
4965 { 1549, 2, 0, 4, 415, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1549 = MTSRIN
4966 { 1548, 2, 0, 4, 553, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1548 = MTSR
4967 { 1547, 2, 0, 4, 382, 0, 0, 699, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1547 = MTSPR8
4968 { 1546, 2, 0, 4, 382, 0, 0, 697, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1546 = MTSPR
4969 { 1545, 2, 0, 4, 377, 0, 0, 697, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1545 = MTPMR
4970 { 1544, 2, 1, 4, 299, 0, 0, 712, PPCImpOpBase + 0, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL }, // Inst #1544 = MTOCRF8
4971 { 1543, 2, 1, 4, 299, 0, 0, 710, PPCImpOpBase + 0, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL }, // Inst #1543 = MTOCRF
4972 { 1542, 2, 0, 4, 381, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1542 = MTMSRD
4973 { 1541, 2, 0, 4, 380, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1541 = MTMSR
4974 { 1540, 1, 0, 4, 104, 0, 1, 172, PPCImpOpBase + 204, 0, 0x9ULL }, // Inst #1540 = MTLR8
4975 { 1539, 1, 0, 4, 104, 0, 1, 171, PPCImpOpBase + 203, 0, 0x9ULL }, // Inst #1539 = MTLR
4976 { 1538, 2, 0, 4, 186, 0, 1, 708, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1538 = MTFSFb
4977 { 1537, 4, 0, 4, 185, 0, 1, 701, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1537 = MTFSF_rec
4978 { 1536, 2, 0, 4, 536, 0, 1, 21, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1536 = MTFSFIb
4979 { 1535, 3, 0, 4, 536, 0, 1, 705, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1535 = MTFSFI_rec
4980 { 1534, 3, 0, 4, 536, 0, 1, 705, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1534 = MTFSFI
4981 { 1533, 4, 0, 4, 185, 0, 1, 701, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1533 = MTFSF
4982 { 1532, 1, 0, 4, 272, 0, 1, 1, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1532 = MTFSB1
4983 { 1531, 1, 0, 4, 531, 0, 1, 1, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1531 = MTFSB0
4984 { 1530, 2, 0, 4, 417, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1530 = MTDCR
4985 { 1529, 1, 0, 4, 104, 0, 1, 171, PPCImpOpBase + 63, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1529 = MTCTRloop
4986 { 1528, 1, 0, 4, 104, 0, 1, 172, PPCImpOpBase + 64, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1528 = MTCTR8loop
4987 { 1527, 1, 0, 4, 104, 0, 1, 172, PPCImpOpBase + 64, 0, 0x9ULL }, // Inst #1527 = MTCTR8
4988 { 1526, 1, 0, 4, 104, 0, 1, 171, PPCImpOpBase + 63, 0, 0x9ULL }, // Inst #1526 = MTCTR
4989 { 1525, 2, 0, 4, 196, 0, 0, 699, PPCImpOpBase + 0, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL }, // Inst #1525 = MTCRF8
4990 { 1524, 2, 0, 4, 196, 0, 0, 697, PPCImpOpBase + 0, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL }, // Inst #1524 = MTCRF
4991 { 1523, 0, 0, 4, 422, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1523 = MSYNC
4992 { 1522, 0, 0, 4, 344, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1522 = MSGSYNC
4993 { 1521, 3, 1, 4, 387, 0, 0, 222, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1521 = MODUW
4994 { 1520, 3, 1, 4, 387, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1520 = MODUD
4995 { 1519, 3, 1, 4, 384, 0, 0, 222, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1519 = MODSW
4996 { 1518, 3, 1, 4, 387, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1518 = MODSD
4997 { 1517, 2, 1, 4, 259, 0, 0, 695, PPCImpOpBase + 0, 0, 0x200ULL }, // Inst #1517 = MFVSRWZ
4998 { 1516, 2, 1, 4, 578, 0, 0, 686, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1516 = MFVSRLD
4999 { 1515, 2, 1, 4, 259, 0, 0, 693, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1515 = MFVSRD
5000 { 1514, 1, 1, 4, 235, 0, 0, 692, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1514 = MFVSCR
5001 { 1513, 2, 1, 4, 259, 0, 0, 690, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1513 = MFVRWZ
5002 { 1512, 2, 1, 4, 375, 0, 0, 688, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1512 = MFVRSAVEv
5003 { 1511, 1, 1, 4, 375, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1511 = MFVRSAVE
5004 { 1510, 2, 1, 4, 259, 0, 0, 686, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1510 = MFVRD
5005 { 1509, 1, 1, 4, 378, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1509 = MFUDSCR
5006 { 1508, 1, 1, 4, 562, 0, 0, 172, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1508 = MFTB8
5007 { 1507, 2, 1, 4, 208, 0, 0, 206, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1507 = MFTB
5008 { 1506, 2, 1, 4, 112, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1506 = MFSRIN
5009 { 1505, 2, 1, 4, 561, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1505 = MFSR
5010 { 1504, 2, 1, 4, 378, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1504 = MFSPR8
5011 { 1503, 2, 1, 4, 378, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1503 = MFSPR
5012 { 1502, 2, 1, 4, 376, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1502 = MFPMR
5013 { 1501, 2, 1, 4, 181, 0, 0, 684, PPCImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL }, // Inst #1501 = MFOCRF8
5014 { 1500, 2, 1, 4, 181, 0, 0, 682, PPCImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL }, // Inst #1500 = MFOCRF
5015 { 1499, 1, 1, 4, 379, 0, 0, 171, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1499 = MFMSR
5016 { 1498, 1, 1, 4, 103, 1, 0, 172, PPCImpOpBase + 204, 0, 0x9ULL }, // Inst #1498 = MFLR8
5017 { 1497, 1, 1, 4, 103, 1, 0, 171, PPCImpOpBase + 203, 0, 0x9ULL }, // Inst #1497 = MFLR
5018 { 1496, 1, 1, 4, 529, 1, 1, 679, PPCImpOpBase + 135, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1496 = MFFS_rec
5019 { 1495, 1, 1, 4, 529, 1, 0, 679, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1495 = MFFSL
5020 { 1494, 2, 1, 4, 530, 1, 0, 680, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1494 = MFFSCRNI
5021 { 1493, 2, 1, 4, 273, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1493 = MFFSCRN
5022 { 1492, 1, 1, 4, 394, 1, 0, 679, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1492 = MFFSCE
5023 { 1491, 2, 1, 4, 530, 1, 0, 680, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1491 = MFFSCDRNI
5024 { 1490, 2, 1, 4, 273, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1490 = MFFSCDRN
5025 { 1489, 1, 1, 4, 529, 1, 0, 679, PPCImpOpBase + 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL }, // Inst #1489 = MFFS
5026 { 1488, 2, 1, 4, 416, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1488 = MFDCR
5027 { 1487, 1, 1, 4, 103, 1, 0, 172, PPCImpOpBase + 64, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1487 = MFCTR8
5028 { 1486, 1, 1, 4, 103, 1, 0, 171, PPCImpOpBase + 63, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL }, // Inst #1486 = MFCTR
5029 { 1485, 1, 1, 4, 105, 0, 0, 172, PPCImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL }, // Inst #1485 = MFCR8
5030 { 1484, 1, 1, 4, 105, 0, 0, 171, PPCImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL }, // Inst #1484 = MFCR
5031 { 1483, 3, 1, 4, 619, 0, 0, 676, PPCImpOpBase + 0, 0, 0x1ULL }, // Inst #1483 = MFBHRBE
5032 { 1482, 1, 1, 4, 291, 0, 0, 675, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1482 = MCRXRX
5033 { 1481, 2, 1, 4, 391, 0, 0, 673, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1481 = MCRFS
5034 { 1480, 2, 1, 4, 106, 0, 0, 673, PPCImpOpBase + 0, 0, 0x21ULL }, // Inst #1480 = MCRF
5035 { 1479, 1, 0, 4, 413, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1479 = MBAR
5036 { 1478, 4, 1, 4, 311, 0, 0, 665, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1478 = MADDLD8
5037 { 1477, 4, 1, 4, 311, 0, 0, 669, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1477 = MADDLD
5038 { 1476, 4, 1, 4, 311, 0, 0, 665, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1476 = MADDHDU
5039 { 1475, 4, 1, 4, 311, 0, 0, 665, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1475 = MADDHD
5040 { 1474, 3, 1, 4, 334, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1474 = LXVX
5041 { 1473, 3, 1, 4, 334, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1473 = LXVWSX
5042 { 1472, 3, 1, 4, 113, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1472 = LXVW4X
5043 { 1471, 3, 1, 4, 552, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1471 = LXVRWX
5044 { 1470, 3, 1, 4, 15, 0, 0, 653, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1470 = LXVRLL
5045 { 1469, 3, 1, 4, 15, 0, 0, 653, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1469 = LXVRL
5046 { 1468, 3, 1, 4, 552, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1468 = LXVRHX
5047 { 1467, 3, 1, 4, 552, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1467 = LXVRDX
5048 { 1466, 3, 1, 4, 552, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1466 = LXVRBX
5049 { 1465, 3, 1, 4, 560, 0, 0, 662, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1465 = LXVPX
5050 { 1464, 3, 1, 4, 40, 0, 0, 659, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1464 = LXVPRLL
5051 { 1463, 3, 1, 4, 40, 0, 0, 659, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1463 = LXVPRL
5052 { 1462, 3, 1, 4, 559, 0, 0, 656, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x400ULL }, // Inst #1462 = LXVP
5053 { 1461, 3, 1, 4, 333, 0, 0, 653, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1461 = LXVLL
5054 { 1460, 3, 1, 4, 333, 0, 0, 653, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1460 = LXVL
5055 { 1459, 2, 1, 4, 573, 0, 0, 651, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1459 = LXVKQ
5056 { 1458, 3, 1, 4, 365, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1458 = LXVH8X
5057 { 1457, 3, 1, 4, 113, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1457 = LXVDSX
5058 { 1456, 3, 1, 4, 335, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1456 = LXVD2X
5059 { 1455, 3, 1, 4, 213, 0, 0, 648, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1455 = LXVB16X
5060 { 1454, 3, 1, 4, 547, 0, 0, 645, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x400ULL }, // Inst #1454 = LXV
5061 { 1453, 3, 1, 4, 363, 0, 0, 219, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1453 = LXSSPX
5062 { 1452, 3, 1, 4, 558, 0, 0, 642, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x400ULL }, // Inst #1452 = LXSSP
5063 { 1451, 3, 1, 4, 213, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1451 = LXSIWZX
5064 { 1450, 3, 1, 4, 360, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1450 = LXSIWAX
5065 { 1449, 3, 1, 4, 334, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1449 = LXSIHZX
5066 { 1448, 3, 1, 4, 334, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1448 = LXSIBZX
5067 { 1447, 3, 1, 4, 335, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1447 = LXSDX
5068 { 1446, 3, 1, 4, 547, 0, 0, 642, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x400ULL }, // Inst #1446 = LXSD
5069 { 1445, 3, 1, 4, 542, 0, 0, 639, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1445 = LWZtocL
5070 { 1444, 3, 1, 4, 542, 0, 0, 636, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1444 = LWZtoc
5071 { 1443, 3, 1, 4, 340, 0, 0, 578, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1443 = LWZXTLS_32
5072 { 1442, 3, 1, 4, 340, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1442 = LWZXTLS_
5073 { 1441, 3, 1, 4, 340, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1441 = LWZXTLS
5074 { 1440, 3, 1, 4, 340, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1440 = LWZX8
5075 { 1439, 3, 1, 4, 340, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1439 = LWZX
5076 { 1438, 4, 2, 4, 356, 0, 0, 568, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1438 = LWZUX8
5077 { 1437, 4, 2, 4, 356, 0, 0, 564, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1437 = LWZUX
5078 { 1436, 4, 2, 4, 355, 0, 0, 560, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1436 = LWZU8
5079 { 1435, 4, 2, 4, 355, 0, 0, 556, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1435 = LWZU
5080 { 1434, 3, 1, 4, 555, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1434 = LWZCIX
5081 { 1433, 3, 1, 4, 540, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x610ULL }, // Inst #1433 = LWZ8
5082 { 1432, 3, 1, 4, 540, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x610ULL }, // Inst #1432 = LWZ
5083 { 1431, 3, 1, 4, 225, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1431 = LWEPX
5084 { 1430, 3, 1, 4, 111, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1430 = LWBRX8
5085 { 1429, 3, 1, 4, 111, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1429 = LWBRX
5086 { 1428, 3, 1, 4, 124, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x514ULL }, // Inst #1428 = LWA_32
5087 { 1427, 3, 1, 4, 123, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x154ULL }, // Inst #1427 = LWAX_32
5088 { 1426, 3, 1, 4, 222, 0, 0, 578, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1426 = LWAXTLS_32
5089 { 1425, 3, 1, 4, 222, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1425 = LWAXTLS_
5090 { 1424, 3, 1, 4, 222, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1424 = LWAXTLS
5091 { 1423, 3, 1, 4, 123, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x154ULL }, // Inst #1423 = LWAX
5092 { 1422, 4, 2, 4, 126, 0, 0, 568, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1422 = LWAUX
5093 { 1421, 3, 1, 4, 403, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x40ULL }, // Inst #1421 = LWAT
5094 { 1420, 3, 1, 4, 109, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1420 = LWARXL
5095 { 1419, 3, 1, 4, 109, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1419 = LWARX
5096 { 1418, 3, 1, 4, 124, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x514ULL }, // Inst #1418 = LWA
5097 { 1417, 3, 1, 4, 212, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1417 = LVXL
5098 { 1416, 3, 1, 4, 212, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1416 = LVX
5099 { 1415, 3, 1, 4, 322, 0, 0, 633, PPCImpOpBase + 0, 0, 0x50ULL }, // Inst #1415 = LVSR
5100 { 1414, 3, 1, 4, 322, 0, 0, 633, PPCImpOpBase + 0, 0, 0x50ULL }, // Inst #1414 = LVSL
5101 { 1413, 3, 1, 4, 212, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1413 = LVEWX
5102 { 1412, 3, 1, 4, 212, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1412 = LVEHX
5103 { 1411, 3, 1, 4, 212, 0, 0, 633, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1411 = LVEBX
5104 { 1410, 3, 1, 4, 118, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1410 = LSWI
5105 { 1409, 3, 1, 4, 0, 0, 0, 630, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #1409 = LQX_PSEUDO
5106 { 1408, 3, 1, 4, 48, 0, 0, 630, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1408 = LQARXL
5107 { 1407, 3, 1, 4, 48, 0, 0, 630, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1407 = LQARX
5108 { 1406, 3, 1, 4, 215, 0, 0, 627, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x410ULL }, // Inst #1406 = LQ
5109 { 1405, 3, 1, 4, 108, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x400ULL }, // Inst #1405 = LMW
5110 { 1404, 2, 1, 4, 498, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL }, // Inst #1404 = LIS8
5111 { 1403, 2, 1, 4, 498, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL }, // Inst #1403 = LIS
5112 { 1402, 2, 1, 4, 498, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL }, // Inst #1402 = LI8
5113 { 1401, 2, 1, 4, 498, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL }, // Inst #1401 = LI
5114 { 1400, 3, 1, 4, 340, 0, 0, 578, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1400 = LHZXTLS_32
5115 { 1399, 3, 1, 4, 340, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1399 = LHZXTLS_
5116 { 1398, 3, 1, 4, 340, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1398 = LHZXTLS
5117 { 1397, 3, 1, 4, 340, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x350ULL }, // Inst #1397 = LHZX8
5118 { 1396, 3, 1, 4, 340, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x350ULL }, // Inst #1396 = LHZX
5119 { 1395, 4, 2, 4, 356, 0, 0, 568, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1395 = LHZUX8
5120 { 1394, 4, 2, 4, 356, 0, 0, 564, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1394 = LHZUX
5121 { 1393, 4, 2, 4, 355, 0, 0, 560, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1393 = LHZU8
5122 { 1392, 4, 2, 4, 355, 0, 0, 556, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1392 = LHZU
5123 { 1391, 3, 1, 4, 555, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1391 = LHZCIX
5124 { 1390, 3, 1, 4, 540, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x710ULL }, // Inst #1390 = LHZ8
5125 { 1389, 3, 1, 4, 540, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x710ULL }, // Inst #1389 = LHZ
5126 { 1388, 3, 1, 4, 225, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1388 = LHEPX
5127 { 1387, 3, 1, 4, 111, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1387 = LHBRX8
5128 { 1386, 3, 1, 4, 111, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL }, // Inst #1386 = LHBRX
5129 { 1385, 3, 1, 4, 222, 0, 0, 578, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1385 = LHAXTLS_32
5130 { 1384, 3, 1, 4, 222, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1384 = LHAXTLS_
5131 { 1383, 3, 1, 4, 222, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1383 = LHAXTLS
5132 { 1382, 3, 1, 4, 123, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x154ULL }, // Inst #1382 = LHAX8
5133 { 1381, 3, 1, 4, 123, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x154ULL }, // Inst #1381 = LHAX
5134 { 1380, 4, 2, 4, 126, 0, 0, 568, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1380 = LHAUX8
5135 { 1379, 4, 2, 4, 126, 0, 0, 564, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1379 = LHAUX
5136 { 1378, 4, 2, 4, 125, 0, 0, 560, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1378 = LHAU8
5137 { 1377, 4, 2, 4, 125, 0, 0, 556, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1377 = LHAU
5138 { 1376, 3, 1, 4, 224, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1376 = LHARXL
5139 { 1375, 3, 1, 4, 117, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1375 = LHARX
5140 { 1374, 3, 1, 4, 546, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x514ULL }, // Inst #1374 = LHA8
5141 { 1373, 3, 1, 4, 546, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x514ULL }, // Inst #1373 = LHA
5142 { 1372, 3, 1, 4, 362, 0, 0, 624, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1372 = LFSXTLS_
5143 { 1371, 3, 1, 4, 362, 0, 0, 624, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1371 = LFSXTLS
5144 { 1370, 3, 1, 4, 362, 0, 0, 621, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1370 = LFSX
5145 { 1369, 4, 2, 4, 401, 0, 0, 617, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1369 = LFSUX
5146 { 1368, 4, 2, 4, 400, 0, 0, 613, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1368 = LFSU
5147 { 1367, 3, 1, 4, 557, 0, 0, 610, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1367 = LFS
5148 { 1366, 3, 1, 4, 347, 0, 0, 596, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1366 = LFIWZX
5149 { 1365, 3, 1, 4, 119, 0, 0, 596, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1365 = LFIWAX
5150 { 1364, 3, 1, 4, 348, 0, 0, 607, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1364 = LFDXTLS_
5151 { 1363, 3, 1, 4, 348, 0, 0, 607, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1363 = LFDXTLS
5152 { 1362, 3, 1, 4, 348, 0, 0, 596, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1362 = LFDX
5153 { 1361, 4, 2, 4, 115, 0, 0, 603, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1361 = LFDUX
5154 { 1360, 4, 2, 4, 114, 0, 0, 599, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1360 = LFDU
5155 { 1359, 3, 1, 4, 226, 0, 0, 596, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1359 = LFDEPX
5156 { 1358, 3, 1, 4, 545, 0, 0, 593, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1358 = LFD
5157 { 1357, 3, 1, 4, 542, 0, 0, 590, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1357 = LDtocL
5158 { 1356, 3, 1, 4, 542, 0, 0, 587, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1356 = LDtocJTI
5159 { 1355, 3, 1, 4, 542, 0, 0, 587, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1355 = LDtocCPT
5160 { 1354, 3, 1, 4, 542, 0, 0, 587, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1354 = LDtocBA
5161 { 1353, 3, 1, 4, 542, 0, 0, 587, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL }, // Inst #1353 = LDtoc
5162 { 1352, 3, 1, 4, 0, 0, 0, 584, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1352 = LDgotTprelL32
5163 { 1351, 3, 1, 4, 0, 0, 0, 581, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1351 = LDgotTprelL
5164 { 1350, 3, 1, 4, 223, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1350 = LDXTLS_
5165 { 1349, 3, 1, 4, 223, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1349 = LDXTLS
5166 { 1348, 3, 1, 4, 223, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1348 = LDX
5167 { 1347, 4, 2, 4, 137, 0, 0, 568, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1347 = LDUX
5168 { 1346, 4, 2, 4, 135, 0, 0, 560, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1346 = LDU
5169 { 1345, 3, 1, 4, 555, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1345 = LDCIX
5170 { 1344, 3, 1, 4, 550, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1344 = LDBRX
5171 { 1343, 3, 1, 4, 403, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x40ULL }, // Inst #1343 = LDAT
5172 { 1342, 3, 1, 4, 110, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1342 = LDARXL
5173 { 1341, 3, 1, 4, 110, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1341 = LDARX
5174 { 1340, 3, 1, 4, 541, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1340 = LD
5175 { 1339, 3, 1, 4, 340, 0, 0, 578, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1339 = LBZXTLS_32
5176 { 1338, 3, 1, 4, 340, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1338 = LBZXTLS_
5177 { 1337, 3, 1, 4, 340, 0, 0, 575, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL }, // Inst #1337 = LBZXTLS
5178 { 1336, 3, 1, 4, 340, 0, 0, 572, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x350ULL }, // Inst #1336 = LBZX8
5179 { 1335, 3, 1, 4, 340, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x350ULL }, // Inst #1335 = LBZX
5180 { 1334, 4, 2, 4, 136, 0, 0, 568, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1334 = LBZUX8
5181 { 1333, 4, 2, 4, 136, 0, 0, 564, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL }, // Inst #1333 = LBZUX
5182 { 1332, 4, 2, 4, 134, 0, 0, 560, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1332 = LBZU8
5183 { 1331, 4, 2, 4, 134, 0, 0, 556, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x410ULL }, // Inst #1331 = LBZU
5184 { 1330, 3, 1, 4, 555, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL }, // Inst #1330 = LBZCIX
5185 { 1329, 3, 1, 4, 540, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x710ULL }, // Inst #1329 = LBZ8
5186 { 1328, 3, 1, 4, 540, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x710ULL }, // Inst #1328 = LBZ
5187 { 1327, 3, 1, 4, 225, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1327 = LBEPX
5188 { 1326, 3, 1, 4, 224, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1326 = LBARXL
5189 { 1325, 3, 1, 4, 117, 0, 0, 553, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #1325 = LBARX
5190 { 1324, 3, 1, 4, 289, 0, 0, 208, PPCImpOpBase + 0, 0, 0x408ULL }, // Inst #1324 = LA8
5191 { 1323, 3, 1, 4, 289, 0, 0, 245, PPCImpOpBase + 0, 0, 0x408ULL }, // Inst #1323 = LA
5192 { 1322, 0, 0, 4, 343, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1322 = ISYNC
5193 { 1321, 4, 1, 4, 207, 0, 0, 549, PPCImpOpBase + 0, 0|(1ULL<<MCID::Select), 0x8ULL }, // Inst #1321 = ISEL8
5194 { 1320, 4, 1, 4, 207, 0, 0, 545, PPCImpOpBase + 0, 0|(1ULL<<MCID::Select), 0x8ULL }, // Inst #1320 = ISEL
5195 { 1319, 2, 0, 4, 618, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1319 = ICCCI
5196 { 1318, 3, 0, 4, 339, 0, 0, 342, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1318 = ICBTLS
5197 { 1317, 3, 0, 4, 549, 0, 0, 342, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1317 = ICBT
5198 { 1316, 3, 0, 4, 618, 0, 0, 342, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1316 = ICBLQ
5199 { 1315, 3, 0, 4, 414, 0, 0, 342, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1315 = ICBLC
5200 { 1314, 2, 0, 4, 338, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1314 = ICBIEP
5201 { 1313, 2, 0, 4, 606, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1313 = ICBI
5202 { 1312, 0, 0, 4, 535, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1312 = HRFID
5203 { 1311, 3, 0, 4, 453, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1311 = HASHSTP8
5204 { 1310, 3, 0, 4, 453, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1310 = HASHSTP
5205 { 1309, 3, 0, 4, 453, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1309 = HASHST8
5206 { 1308, 3, 0, 4, 453, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1308 = HASHST
5207 { 1307, 3, 0, 4, 421, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1307 = HASHCHKP8
5208 { 1306, 3, 0, 4, 421, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1306 = HASHCHKP
5209 { 1305, 3, 0, 4, 421, 0, 0, 542, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1305 = HASHCHK8
5210 { 1304, 3, 0, 4, 421, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1304 = HASHCHK
5211 { 1303, 3, 1, 4, 0, 0, 18, 234, PPCImpOpBase + 183, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1303 = GETtlsldADDRPCREL
5212 { 1302, 3, 1, 4, 0, 0, 17, 225, PPCImpOpBase + 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1302 = GETtlsldADDR32
5213 { 1301, 3, 1, 4, 0, 0, 17, 234, PPCImpOpBase + 137, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1301 = GETtlsldADDR
5214 { 1300, 1, 1, 4, 0, 0, 2, 171, PPCImpOpBase + 201, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1300 = GETtlsTpointer32AIX
5215 { 1299, 2, 1, 4, 0, 0, 6, 261, PPCImpOpBase + 177, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1299 = GETtlsMOD64AIX
5216 { 1298, 2, 1, 4, 0, 0, 6, 259, PPCImpOpBase + 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1298 = GETtlsMOD32AIX
5217 { 1297, 3, 1, 8, 0, 0, 18, 234, PPCImpOpBase + 183, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1297 = GETtlsADDRPCREL
5218 { 1296, 3, 1, 4, 0, 0, 6, 228, PPCImpOpBase + 177, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1296 = GETtlsADDR64AIX
5219 { 1295, 3, 1, 4, 0, 0, 6, 222, PPCImpOpBase + 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1295 = GETtlsADDR32AIX
5220 { 1294, 3, 1, 4, 0, 0, 17, 225, PPCImpOpBase + 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1294 = GETtlsADDR32
5221 { 1293, 3, 1, 8, 0, 0, 17, 234, PPCImpOpBase + 137, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1293 = GETtlsADDR
5222 { 1292, 2, 1, 4, 470, 0, 0, 540, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1292 = FTSQRT
5223 { 1291, 3, 1, 4, 276, 0, 0, 351, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x18ULL }, // Inst #1291 = FTDIV
5224 { 1290, 3, 1, 4, 157, 1, 1, 336, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1290 = FSUB_rec
5225 { 1289, 3, 1, 4, 442, 1, 1, 520, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1289 = FSUBS_rec
5226 { 1288, 3, 1, 4, 435, 1, 0, 520, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1288 = FSUBS
5227 { 1287, 3, 1, 4, 316, 1, 0, 336, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1287 = FSUB
5228 { 1286, 2, 1, 4, 176, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1286 = FSQRT_rec
5229 { 1285, 2, 1, 4, 184, 1, 1, 518, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1285 = FSQRTS_rec
5230 { 1284, 2, 1, 4, 398, 1, 0, 518, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1284 = FSQRTS
5231 { 1283, 2, 1, 4, 397, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1283 = FSQRT
5232 { 1282, 4, 1, 4, 319, 0, 1, 536, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1282 = FSELS_rec
5233 { 1281, 4, 1, 4, 315, 0, 0, 536, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1281 = FSELS
5234 { 1280, 4, 1, 4, 319, 0, 1, 528, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1280 = FSELD_rec
5235 { 1279, 4, 1, 4, 315, 0, 0, 528, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1279 = FSELD
5236 { 1278, 2, 1, 4, 444, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1278 = FRSQRTE_rec
5237 { 1277, 2, 1, 4, 444, 0, 1, 518, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1277 = FRSQRTES_rec
5238 { 1276, 2, 1, 4, 427, 0, 0, 518, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1276 = FRSQRTES
5239 { 1275, 2, 1, 4, 427, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1275 = FRSQRTE
5240 { 1274, 2, 1, 4, 444, 1, 1, 523, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1274 = FRSP_rec
5241 { 1273, 2, 1, 4, 427, 1, 0, 523, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1273 = FRSP
5242 { 1272, 2, 1, 4, 444, 0, 1, 518, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1272 = FRIZS_rec
5243 { 1271, 2, 1, 4, 427, 0, 0, 518, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1271 = FRIZS
5244 { 1270, 2, 1, 4, 444, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1270 = FRIZD_rec
5245 { 1269, 2, 1, 4, 427, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1269 = FRIZD
5246 { 1268, 2, 1, 4, 444, 0, 1, 518, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1268 = FRIPS_rec
5247 { 1267, 2, 1, 4, 427, 0, 0, 518, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1267 = FRIPS
5248 { 1266, 2, 1, 4, 444, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1266 = FRIPD_rec
5249 { 1265, 2, 1, 4, 427, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1265 = FRIPD
5250 { 1264, 2, 1, 4, 444, 0, 1, 518, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1264 = FRINS_rec
5251 { 1263, 2, 1, 4, 427, 0, 0, 518, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1263 = FRINS
5252 { 1262, 2, 1, 4, 444, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1262 = FRIND_rec
5253 { 1261, 2, 1, 4, 427, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1261 = FRIND
5254 { 1260, 2, 1, 4, 444, 0, 1, 518, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1260 = FRIMS_rec
5255 { 1259, 2, 1, 4, 427, 0, 0, 518, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1259 = FRIMS
5256 { 1258, 2, 1, 4, 444, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1258 = FRIMD_rec
5257 { 1257, 2, 1, 4, 427, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1257 = FRIMD
5258 { 1256, 2, 1, 4, 444, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1256 = FRE_rec
5259 { 1255, 2, 1, 4, 444, 0, 1, 518, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1255 = FRES_rec
5260 { 1254, 2, 1, 4, 427, 0, 0, 518, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1254 = FRES
5261 { 1253, 2, 1, 4, 427, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1253 = FRE
5262 { 1252, 4, 1, 4, 158, 1, 1, 528, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1252 = FNMSUB_rec
5263 { 1251, 4, 1, 4, 320, 1, 1, 532, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1251 = FNMSUBS_rec
5264 { 1250, 4, 1, 4, 315, 1, 0, 532, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1250 = FNMSUBS
5265 { 1249, 4, 1, 4, 317, 1, 0, 528, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1249 = FNMSUB
5266 { 1248, 4, 1, 4, 158, 1, 1, 528, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1248 = FNMADD_rec
5267 { 1247, 4, 1, 4, 320, 1, 1, 532, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1247 = FNMADDS_rec
5268 { 1246, 4, 1, 4, 315, 1, 0, 532, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1246 = FNMADDS
5269 { 1245, 4, 1, 4, 317, 1, 0, 528, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1245 = FNMADD
5270 { 1244, 2, 1, 4, 537, 0, 1, 518, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1244 = FNEGS_rec
5271 { 1243, 2, 1, 4, 507, 0, 0, 518, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1243 = FNEGS
5272 { 1242, 2, 1, 4, 537, 0, 1, 345, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1242 = FNEGD_rec
5273 { 1241, 2, 1, 4, 507, 0, 0, 345, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1241 = FNEGD
5274 { 1240, 2, 1, 4, 537, 0, 1, 518, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1240 = FNABSS_rec
5275 { 1239, 2, 1, 4, 507, 0, 0, 518, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1239 = FNABSS
5276 { 1238, 2, 1, 4, 537, 0, 1, 345, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1238 = FNABSD_rec
5277 { 1237, 2, 1, 4, 507, 0, 0, 345, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1237 = FNABSD
5278 { 1236, 3, 1, 4, 443, 1, 1, 336, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1236 = FMUL_rec
5279 { 1235, 3, 1, 4, 442, 1, 1, 520, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1235 = FMULS_rec
5280 { 1234, 3, 1, 4, 435, 1, 0, 520, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1234 = FMULS
5281 { 1233, 3, 1, 4, 436, 1, 0, 336, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1233 = FMUL
5282 { 1232, 4, 1, 4, 158, 1, 1, 528, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1232 = FMSUB_rec
5283 { 1231, 4, 1, 4, 320, 1, 1, 532, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1231 = FMSUBS_rec
5284 { 1230, 4, 1, 4, 315, 1, 0, 532, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1230 = FMSUBS
5285 { 1229, 4, 1, 4, 317, 1, 0, 528, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1229 = FMSUB
5286 { 1228, 2, 1, 4, 537, 0, 1, 518, PPCImpOpBase + 131, 0, 0x0ULL }, // Inst #1228 = FMR_rec
5287 { 1227, 2, 1, 4, 507, 0, 0, 518, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #1227 = FMR
5288 { 1226, 4, 1, 4, 158, 1, 1, 528, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1226 = FMADD_rec
5289 { 1225, 4, 1, 4, 320, 1, 1, 532, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1225 = FMADDS_rec
5290 { 1224, 4, 1, 4, 315, 1, 0, 532, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1224 = FMADDS
5291 { 1223, 4, 1, 4, 317, 1, 0, 528, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1223 = FMADD
5292 { 1222, 0, 0, 4, 0, 0, 1, 1, PPCImpOpBase + 134, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1222 = FENCE
5293 { 1221, 3, 1, 4, 174, 1, 1, 336, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1221 = FDIV_rec
5294 { 1220, 3, 1, 4, 171, 1, 1, 520, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1220 = FDIVS_rec
5295 { 1219, 3, 1, 4, 399, 1, 0, 520, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1219 = FDIVS
5296 { 1218, 3, 1, 4, 396, 1, 0, 336, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1218 = FDIV
5297 { 1217, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1217 = FCTIW_rec
5298 { 1216, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1216 = FCTIWZ_rec
5299 { 1215, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1215 = FCTIWZ
5300 { 1214, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1214 = FCTIWU_rec
5301 { 1213, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1213 = FCTIWUZ_rec
5302 { 1212, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1212 = FCTIWUZ
5303 { 1211, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1211 = FCTIWU
5304 { 1210, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1210 = FCTIW
5305 { 1209, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1209 = FCTID_rec
5306 { 1208, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1208 = FCTIDZ_rec
5307 { 1207, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1207 = FCTIDZ
5308 { 1206, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1206 = FCTIDU_rec
5309 { 1205, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1205 = FCTIDUZ_rec
5310 { 1204, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1204 = FCTIDUZ
5311 { 1203, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1203 = FCTIDU
5312 { 1202, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1202 = FCTID
5313 { 1201, 3, 1, 4, 156, 0, 1, 520, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1201 = FCPSGNS_rec
5314 { 1200, 3, 1, 4, 301, 0, 0, 520, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1200 = FCPSGNS
5315 { 1199, 3, 1, 4, 156, 0, 1, 336, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1199 = FCPSGND_rec
5316 { 1198, 3, 1, 4, 301, 0, 0, 336, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1198 = FCPSGND
5317 { 1197, 3, 1, 4, 170, 0, 0, 525, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1197 = FCMPUS
5318 { 1196, 3, 1, 4, 170, 0, 0, 351, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1196 = FCMPUD
5319 { 1195, 3, 1, 4, 170, 0, 0, 525, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1195 = FCMPOS
5320 { 1194, 3, 1, 4, 170, 0, 0, 351, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1194 = FCMPOD
5321 { 1193, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1193 = FCFID_rec
5322 { 1192, 2, 1, 4, 444, 1, 1, 345, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1192 = FCFIDU_rec
5323 { 1191, 2, 1, 4, 444, 1, 1, 523, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1191 = FCFIDUS_rec
5324 { 1190, 2, 1, 4, 427, 1, 0, 523, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1190 = FCFIDUS
5325 { 1189, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1189 = FCFIDU
5326 { 1188, 2, 1, 4, 444, 1, 1, 523, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1188 = FCFIDS_rec
5327 { 1187, 2, 1, 4, 427, 1, 0, 523, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1187 = FCFIDS
5328 { 1186, 2, 1, 4, 427, 1, 0, 345, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL }, // Inst #1186 = FCFID
5329 { 1185, 3, 1, 4, 0, 1, 0, 336, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #1185 = FADDrtz
5330 { 1184, 3, 1, 4, 157, 1, 1, 336, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1184 = FADD_rec
5331 { 1183, 3, 1, 4, 442, 1, 1, 520, PPCImpOpBase + 135, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1183 = FADDS_rec
5332 { 1182, 3, 1, 4, 435, 1, 0, 520, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1182 = FADDS
5333 { 1181, 3, 1, 4, 316, 1, 0, 336, PPCImpOpBase + 134, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL }, // Inst #1181 = FADD
5334 { 1180, 2, 1, 4, 537, 0, 1, 518, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1180 = FABSS_rec
5335 { 1179, 2, 1, 4, 507, 0, 0, 518, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1179 = FABSS
5336 { 1178, 2, 1, 4, 537, 0, 1, 345, PPCImpOpBase + 131, 0, 0x18ULL }, // Inst #1178 = FABSD_rec
5337 { 1177, 2, 1, 4, 507, 0, 0, 345, PPCImpOpBase + 0, 0, 0x18ULL }, // Inst #1177 = FABSD
5338 { 1176, 0, 0, 4, 610, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1176 = EnforceIEIO
5339 { 1175, 2, 1, 4, 506, 0, 1, 261, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1175 = EXTSW_rec
5340 { 1174, 2, 1, 4, 506, 0, 1, 513, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1174 = EXTSW_32_64_rec
5341 { 1173, 2, 1, 4, 506, 0, 0, 513, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1173 = EXTSW_32_64
5342 { 1172, 2, 1, 4, 506, 0, 0, 259, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1172 = EXTSW_32
5343 { 1171, 3, 1, 4, 395, 0, 2, 181, PPCImpOpBase + 11, 0, 0x8ULL }, // Inst #1171 = EXTSWSLI_rec
5344 { 1170, 3, 1, 4, 395, 0, 1, 515, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1170 = EXTSWSLI_32_64_rec
5345 { 1169, 3, 1, 4, 285, 0, 0, 515, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #1169 = EXTSWSLI_32_64
5346 { 1168, 3, 1, 4, 285, 0, 1, 181, PPCImpOpBase + 5, 0, 0x8ULL }, // Inst #1168 = EXTSWSLI
5347 { 1167, 2, 1, 4, 506, 0, 0, 261, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1167 = EXTSW
5348 { 1166, 2, 1, 4, 506, 0, 1, 259, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1166 = EXTSH_rec
5349 { 1165, 2, 1, 4, 506, 0, 1, 261, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1165 = EXTSH8_rec
5350 { 1164, 2, 1, 4, 506, 0, 0, 513, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1164 = EXTSH8_32_64
5351 { 1163, 2, 1, 4, 506, 0, 0, 261, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1163 = EXTSH8
5352 { 1162, 2, 1, 4, 506, 0, 0, 259, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1162 = EXTSH
5353 { 1161, 2, 1, 4, 506, 0, 1, 259, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1161 = EXTSB_rec
5354 { 1160, 2, 1, 4, 506, 0, 1, 261, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1160 = EXTSB8_rec
5355 { 1159, 2, 1, 4, 506, 0, 0, 513, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1159 = EXTSB8_32_64
5356 { 1158, 2, 1, 4, 506, 0, 0, 261, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1158 = EXTSB8
5357 { 1157, 2, 1, 4, 506, 0, 0, 259, PPCImpOpBase + 0, 0, 0x108ULL }, // Inst #1157 = EXTSB
5358 { 1156, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1156 = EVXOR
5359 { 1155, 3, 1, 4, 406, 0, 0, 510, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1155 = EVSUBIFW
5360 { 1154, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1154 = EVSUBFW
5361 { 1153, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1153 = EVSUBFUSIAAW
5362 { 1152, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1152 = EVSUBFUMIAAW
5363 { 1151, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1151 = EVSUBFSSIAAW
5364 { 1150, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1150 = EVSUBFSMIAAW
5365 { 1149, 3, 0, 4, 409, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1149 = EVSTWWOX
5366 { 1148, 3, 0, 4, 409, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1148 = EVSTWWO
5367 { 1147, 3, 0, 4, 409, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1147 = EVSTWWEX
5368 { 1146, 3, 0, 4, 409, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1146 = EVSTWWE
5369 { 1145, 3, 0, 4, 409, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1145 = EVSTWHOX
5370 { 1144, 3, 0, 4, 409, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1144 = EVSTWHO
5371 { 1143, 3, 0, 4, 409, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1143 = EVSTWHEX
5372 { 1142, 3, 0, 4, 409, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1142 = EVSTWHE
5373 { 1141, 3, 0, 4, 409, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1141 = EVSTDWX
5374 { 1140, 3, 0, 4, 409, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1140 = EVSTDW
5375 { 1139, 3, 0, 4, 409, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1139 = EVSTDHX
5376 { 1138, 3, 0, 4, 409, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1138 = EVSTDH
5377 { 1137, 3, 0, 4, 409, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1137 = EVSTDDX
5378 { 1136, 3, 0, 4, 409, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x400ULL }, // Inst #1136 = EVSTDD
5379 { 1135, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1135 = EVSRWU
5380 { 1134, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1134 = EVSRWS
5381 { 1133, 3, 1, 4, 406, 0, 0, 492, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1133 = EVSRWIU
5382 { 1132, 3, 1, 4, 406, 0, 0, 492, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1132 = EVSRWIS
5383 { 1131, 2, 1, 4, 406, 0, 0, 508, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1131 = EVSPLATI
5384 { 1130, 2, 1, 4, 406, 0, 0, 508, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1130 = EVSPLATFI
5385 { 1129, 3, 1, 4, 406, 0, 0, 492, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1129 = EVSLWI
5386 { 1128, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1128 = EVSLW
5387 { 1127, 4, 1, 4, 19, 0, 0, 504, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1127 = EVSEL
5388 { 1126, 2, 1, 4, 406, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1126 = EVRNDW
5389 { 1125, 3, 1, 4, 406, 0, 0, 492, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1125 = EVRLWI
5390 { 1124, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1124 = EVRLW
5391 { 1123, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1123 = EVORC
5392 { 1122, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1122 = EVOR
5393 { 1121, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1121 = EVNOR
5394 { 1120, 2, 1, 4, 406, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1120 = EVNEG
5395 { 1119, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1119 = EVNAND
5396 { 1118, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1118 = EVMWUMIAN
5397 { 1117, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1117 = EVMWUMIAA
5398 { 1116, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1116 = EVMWUMIA
5399 { 1115, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1115 = EVMWUMI
5400 { 1114, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1114 = EVMWSSFAN
5401 { 1113, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1113 = EVMWSSFAA
5402 { 1112, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1112 = EVMWSSFA
5403 { 1111, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1111 = EVMWSSF
5404 { 1110, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1110 = EVMWSMIAN
5405 { 1109, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1109 = EVMWSMIAA
5406 { 1108, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1108 = EVMWSMIA
5407 { 1107, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1107 = EVMWSMI
5408 { 1106, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1106 = EVMWSMFAN
5409 { 1105, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1105 = EVMWSMFAA
5410 { 1104, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1104 = EVMWSMFA
5411 { 1103, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1103 = EVMWSMF
5412 { 1102, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1102 = EVMWLUSIANW
5413 { 1101, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1101 = EVMWLUSIAAW
5414 { 1100, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1100 = EVMWLUMIANW
5415 { 1099, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1099 = EVMWLUMIAAW
5416 { 1098, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1098 = EVMWLUMIA
5417 { 1097, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1097 = EVMWLUMI
5418 { 1096, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1096 = EVMWLSSIANW
5419 { 1095, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1095 = EVMWLSSIAAW
5420 { 1094, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1094 = EVMWLSMIANW
5421 { 1093, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1093 = EVMWLSMIAAW
5422 { 1092, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1092 = EVMWHUMIA
5423 { 1091, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1091 = EVMWHUMI
5424 { 1090, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1090 = EVMWHSSFA
5425 { 1089, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1089 = EVMWHSSF
5426 { 1088, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1088 = EVMWHSMIA
5427 { 1087, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1087 = EVMWHSMI
5428 { 1086, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1086 = EVMWHSMFA
5429 { 1085, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1085 = EVMWHSMF
5430 { 1084, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1084 = EVMRA
5431 { 1083, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1083 = EVMHOUSIANW
5432 { 1082, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1082 = EVMHOUSIAAW
5433 { 1081, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1081 = EVMHOUMIANW
5434 { 1080, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1080 = EVMHOUMIAAW
5435 { 1079, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1079 = EVMHOUMIA
5436 { 1078, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1078 = EVMHOUMI
5437 { 1077, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1077 = EVMHOSSIANW
5438 { 1076, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1076 = EVMHOSSIAAW
5439 { 1075, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1075 = EVMHOSSFANW
5440 { 1074, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1074 = EVMHOSSFAAW
5441 { 1073, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1073 = EVMHOSSFA
5442 { 1072, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1072 = EVMHOSSF
5443 { 1071, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1071 = EVMHOSMIANW
5444 { 1070, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1070 = EVMHOSMIAAW
5445 { 1069, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1069 = EVMHOSMIA
5446 { 1068, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1068 = EVMHOSMI
5447 { 1067, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1067 = EVMHOSMFANW
5448 { 1066, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1066 = EVMHOSMFAAW
5449 { 1065, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1065 = EVMHOSMFA
5450 { 1064, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1064 = EVMHOSMF
5451 { 1063, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1063 = EVMHOGUMIAN
5452 { 1062, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1062 = EVMHOGUMIAA
5453 { 1061, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1061 = EVMHOGSMIAN
5454 { 1060, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1060 = EVMHOGSMIAA
5455 { 1059, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1059 = EVMHOGSMFAN
5456 { 1058, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1058 = EVMHOGSMFAA
5457 { 1057, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1057 = EVMHEUSIANW
5458 { 1056, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1056 = EVMHEUSIAAW
5459 { 1055, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1055 = EVMHEUMIANW
5460 { 1054, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1054 = EVMHEUMIAAW
5461 { 1053, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1053 = EVMHEUMIA
5462 { 1052, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1052 = EVMHEUMI
5463 { 1051, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1051 = EVMHESSIANW
5464 { 1050, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1050 = EVMHESSIAAW
5465 { 1049, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1049 = EVMHESSFANW
5466 { 1048, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1048 = EVMHESSFAAW
5467 { 1047, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1047 = EVMHESSFA
5468 { 1046, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1046 = EVMHESSF
5469 { 1045, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1045 = EVMHESMIANW
5470 { 1044, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1044 = EVMHESMIAAW
5471 { 1043, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1043 = EVMHESMIA
5472 { 1042, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1042 = EVMHESMI
5473 { 1041, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1041 = EVMHESMFANW
5474 { 1040, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1040 = EVMHESMFAAW
5475 { 1039, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1039 = EVMHESMFA
5476 { 1038, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1038 = EVMHESMF
5477 { 1037, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1037 = EVMHEGUMIAN
5478 { 1036, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1036 = EVMHEGUMIAA
5479 { 1035, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1035 = EVMHEGSMIAN
5480 { 1034, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1034 = EVMHEGSMIAA
5481 { 1033, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1033 = EVMHEGSMFAN
5482 { 1032, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1032 = EVMHEGSMFAA
5483 { 1031, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1031 = EVMERGELOHI
5484 { 1030, 3, 1, 4, 406, 0, 0, 501, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1030 = EVMERGELO
5485 { 1029, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1029 = EVMERGEHILO
5486 { 1028, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1028 = EVMERGEHI
5487 { 1027, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1027 = EVLWWSPLATX
5488 { 1026, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1026 = EVLWWSPLAT
5489 { 1025, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1025 = EVLWHSPLATX
5490 { 1024, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1024 = EVLWHSPLAT
5491 { 1023, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1023 = EVLWHOUX
5492 { 1022, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1022 = EVLWHOU
5493 { 1021, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1021 = EVLWHOSX
5494 { 1020, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1020 = EVLWHOS
5495 { 1019, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1019 = EVLWHEX
5496 { 1018, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1018 = EVLWHE
5497 { 1017, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1017 = EVLHHOUSPLATX
5498 { 1016, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1016 = EVLHHOUSPLAT
5499 { 1015, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1015 = EVLHHOSSPLATX
5500 { 1014, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1014 = EVLHHOSSPLAT
5501 { 1013, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1013 = EVLHHESPLATX
5502 { 1012, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1012 = EVLHHESPLAT
5503 { 1011, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1011 = EVLDWX
5504 { 1010, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1010 = EVLDW
5505 { 1009, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1009 = EVLDHX
5506 { 1008, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #1008 = EVLDH
5507 { 1007, 3, 1, 4, 408, 0, 0, 498, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1007 = EVLDDX
5508 { 1006, 3, 1, 4, 408, 0, 0, 495, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x400ULL }, // Inst #1006 = EVLDD
5509 { 1005, 3, 1, 4, 19, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1005 = EVFSTSTLT
5510 { 1004, 3, 1, 4, 19, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1004 = EVFSTSTGT
5511 { 1003, 3, 1, 4, 19, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1003 = EVFSTSTEQ
5512 { 1002, 3, 1, 4, 24, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1002 = EVFSSUB
5513 { 1001, 2, 1, 4, 19, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1001 = EVFSNEG
5514 { 1000, 2, 1, 4, 19, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1000 = EVFSNABS
5515 { 999, 3, 1, 4, 24, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #999 = EVFSMUL
5516 { 998, 3, 1, 4, 22, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #998 = EVFSDIV
5517 { 997, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #997 = EVFSCTUIZ
5518 { 996, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #996 = EVFSCTUI
5519 { 995, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #995 = EVFSCTUF
5520 { 994, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #994 = EVFSCTSIZ
5521 { 993, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #993 = EVFSCTSI
5522 { 992, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #992 = EVFSCTSF
5523 { 991, 3, 1, 4, 23, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #991 = EVFSCMPLT
5524 { 990, 3, 1, 4, 23, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #990 = EVFSCMPGT
5525 { 989, 3, 1, 4, 23, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #989 = EVFSCMPEQ
5526 { 988, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #988 = EVFSCFUI
5527 { 987, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #987 = EVFSCFUF
5528 { 986, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #986 = EVFSCFSI
5529 { 985, 2, 1, 4, 24, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #985 = EVFSCFSF
5530 { 984, 3, 1, 4, 24, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #984 = EVFSADD
5531 { 983, 2, 1, 4, 19, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #983 = EVFSABS
5532 { 982, 2, 1, 4, 406, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #982 = EVEXTSH
5533 { 981, 2, 1, 4, 406, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #981 = EVEXTSB
5534 { 980, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #980 = EVEQV
5535 { 979, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #979 = EVDIVWU
5536 { 978, 3, 1, 4, 407, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #978 = EVDIVWS
5537 { 977, 2, 1, 4, 406, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #977 = EVCNTLZW
5538 { 976, 2, 1, 4, 406, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #976 = EVCNTLSW
5539 { 975, 3, 1, 4, 406, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #975 = EVCMPLTU
5540 { 974, 3, 1, 4, 406, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #974 = EVCMPLTS
5541 { 973, 3, 1, 4, 406, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #973 = EVCMPGTU
5542 { 972, 3, 1, 4, 406, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #972 = EVCMPGTS
5543 { 971, 3, 1, 4, 406, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #971 = EVCMPEQ
5544 { 970, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #970 = EVANDC
5545 { 969, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #969 = EVAND
5546 { 968, 3, 1, 4, 406, 0, 0, 479, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #968 = EVADDW
5547 { 967, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #967 = EVADDUSIAAW
5548 { 966, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #966 = EVADDUMIAAW
5549 { 965, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #965 = EVADDSSIAAW
5550 { 964, 2, 1, 4, 407, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #964 = EVADDSMIAAW
5551 { 963, 3, 1, 4, 406, 0, 0, 492, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #963 = EVADDIW
5552 { 962, 2, 1, 4, 406, 0, 0, 477, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #962 = EVABS
5553 { 961, 3, 1, 4, 198, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #961 = EQV_rec
5554 { 960, 3, 1, 4, 198, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #960 = EQV8_rec
5555 { 959, 3, 1, 4, 198, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #959 = EQV8
5556 { 958, 3, 1, 4, 198, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #958 = EQV
5557 { 957, 1, 0, 0, 0, 0, 0, 285, PPCImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #957 = EH_SjLj_Setup
5558 { 956, 2, 1, 4, 0, 0, 1, 490, PPCImpOpBase + 64, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #956 = EH_SjLj_SetJmp64
5559 { 955, 2, 1, 4, 0, 0, 1, 490, PPCImpOpBase + 63, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #955 = EH_SjLj_SetJmp32
5560 { 954, 1, 0, 4, 0, 0, 0, 489, PPCImpOpBase + 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #954 = EH_SjLj_LongJmp64
5561 { 953, 1, 0, 4, 0, 0, 0, 489, PPCImpOpBase + 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #953 = EH_SjLj_LongJmp32
5562 { 952, 3, 1, 4, 16, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #952 = EFSTSTLT
5563 { 951, 3, 1, 4, 16, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #951 = EFSTSTGT
5564 { 950, 3, 1, 4, 16, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #950 = EFSTSTEQ
5565 { 949, 3, 1, 4, 23, 0, 0, 222, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #949 = EFSSUB
5566 { 948, 2, 1, 4, 12, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #948 = EFSNEG
5567 { 947, 2, 1, 4, 12, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #947 = EFSNABS
5568 { 946, 3, 1, 4, 12, 0, 0, 222, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #946 = EFSMUL
5569 { 945, 3, 1, 4, 22, 0, 0, 222, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #945 = EFSDIV
5570 { 944, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #944 = EFSCTUIZ
5571 { 943, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #943 = EFSCTUI
5572 { 942, 2, 1, 4, 23, 0, 0, 482, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #942 = EFSCTUF
5573 { 941, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #941 = EFSCTSIZ
5574 { 940, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #940 = EFSCTSI
5575 { 939, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #939 = EFSCTSF
5576 { 938, 3, 1, 4, 16, 0, 0, 317, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #938 = EFSCMPLT
5577 { 937, 3, 1, 4, 16, 0, 0, 317, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #937 = EFSCMPGT
5578 { 936, 3, 1, 4, 16, 0, 0, 317, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #936 = EFSCMPEQ
5579 { 935, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #935 = EFSCFUI
5580 { 934, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #934 = EFSCFUF
5581 { 933, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #933 = EFSCFSI
5582 { 932, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #932 = EFSCFSF
5583 { 931, 2, 1, 4, 23, 0, 0, 487, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #931 = EFSCFD
5584 { 930, 3, 1, 4, 21, 0, 0, 222, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #930 = EFSADD
5585 { 929, 2, 1, 4, 23, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #929 = EFSABS
5586 { 928, 3, 1, 4, 20, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #928 = EFDTSTLT
5587 { 927, 3, 1, 4, 20, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #927 = EFDTSTGT
5588 { 926, 3, 1, 4, 20, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #926 = EFDTSTEQ
5589 { 925, 3, 1, 4, 20, 0, 0, 479, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #925 = EFDSUB
5590 { 924, 2, 1, 4, 20, 0, 0, 477, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #924 = EFDNEG
5591 { 923, 2, 1, 4, 20, 0, 0, 477, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #923 = EFDNABS
5592 { 922, 3, 1, 4, 20, 0, 0, 479, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #922 = EFDMUL
5593 { 921, 3, 1, 4, 22, 0, 0, 479, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #921 = EFDDIV
5594 { 920, 2, 1, 4, 20, 0, 0, 487, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #920 = EFDCTUIZ
5595 { 919, 2, 1, 4, 20, 0, 0, 487, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #919 = EFDCTUIDZ
5596 { 918, 2, 1, 4, 20, 0, 0, 487, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #918 = EFDCTUI
5597 { 917, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #917 = EFDCTUF
5598 { 916, 2, 1, 4, 20, 0, 0, 487, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #916 = EFDCTSIZ
5599 { 915, 2, 1, 4, 20, 0, 0, 487, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #915 = EFDCTSIDZ
5600 { 914, 2, 1, 4, 20, 0, 0, 487, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #914 = EFDCTSI
5601 { 913, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #913 = EFDCTSF
5602 { 912, 3, 1, 4, 20, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #912 = EFDCMPLT
5603 { 911, 3, 1, 4, 20, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #911 = EFDCMPGT
5604 { 910, 3, 1, 4, 20, 0, 0, 484, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #910 = EFDCMPEQ
5605 { 909, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #909 = EFDCFUID
5606 { 908, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #908 = EFDCFUI
5607 { 907, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #907 = EFDCFUF
5608 { 906, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #906 = EFDCFSID
5609 { 905, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #905 = EFDCFSI
5610 { 904, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #904 = EFDCFSF
5611 { 903, 2, 1, 4, 20, 0, 0, 482, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #903 = EFDCFS
5612 { 902, 3, 1, 4, 21, 0, 0, 479, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #902 = EFDADD
5613 { 901, 2, 1, 4, 20, 0, 0, 477, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #901 = EFDABS
5614 { 900, 2, 1, 4, 0, 1, 1, 475, PPCImpOpBase + 105, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #900 = DecreaseCTRloop
5615 { 899, 2, 1, 4, 0, 1, 1, 475, PPCImpOpBase + 107, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #899 = DecreaseCTR8loop
5616 { 898, 3, 1, 4, 0, 0, 0, 472, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #898 = DYNAREAOFFSET8
5617 { 897, 3, 1, 4, 0, 0, 0, 472, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #897 = DYNAREAOFFSET
5618 { 896, 4, 1, 4, 0, 1, 1, 468, PPCImpOpBase + 132, 0, 0x0ULL }, // Inst #896 = DYNALLOC8
5619 { 895, 4, 1, 4, 0, 1, 1, 464, PPCImpOpBase + 61, 0, 0x0ULL }, // Inst #895 = DYNALLOC
5620 { 894, 2, 1, 4, 244, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #894 = DXEX_rec
5621 { 893, 2, 1, 4, 244, 0, 1, 357, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #893 = DXEXQ_rec
5622 { 892, 2, 1, 4, 244, 0, 0, 357, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #892 = DXEXQ
5623 { 891, 2, 1, 4, 244, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #891 = DXEX
5624 { 890, 3, 1, 4, 243, 0, 0, 461, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #890 = DTSTSFQ
5625 { 889, 3, 1, 4, 16, 0, 0, 458, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #889 = DTSTSFIQ
5626 { 888, 3, 1, 4, 16, 0, 0, 455, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #888 = DTSTSFI
5627 { 887, 3, 1, 4, 243, 0, 0, 351, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #887 = DTSTSF
5628 { 886, 3, 1, 4, 248, 0, 0, 354, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #886 = DTSTEXQ
5629 { 885, 3, 1, 4, 243, 0, 0, 351, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #885 = DTSTEX
5630 { 884, 3, 1, 4, 243, 0, 0, 452, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #884 = DTSTDGQ
5631 { 883, 3, 1, 4, 243, 0, 0, 449, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #883 = DTSTDG
5632 { 882, 3, 1, 4, 243, 0, 0, 452, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #882 = DTSTDCQ
5633 { 881, 3, 1, 4, 243, 0, 0, 449, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #881 = DTSTDC
5634 { 880, 3, 1, 4, 245, 0, 1, 336, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #880 = DSUB_rec
5635 { 879, 3, 1, 4, 250, 0, 1, 339, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #879 = DSUBQ_rec
5636 { 878, 3, 1, 4, 250, 0, 0, 339, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #878 = DSUBQ
5637 { 877, 3, 1, 4, 245, 0, 0, 336, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #877 = DSUB
5638 { 876, 3, 0, 4, 526, 0, 0, 446, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #876 = DSTT64
5639 { 875, 3, 0, 4, 526, 0, 0, 443, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #875 = DSTT
5640 { 874, 3, 0, 4, 526, 0, 0, 446, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #874 = DSTSTT64
5641 { 873, 3, 0, 4, 526, 0, 0, 443, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #873 = DSTSTT
5642 { 872, 3, 0, 4, 526, 0, 0, 446, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #872 = DSTST64
5643 { 871, 3, 0, 4, 526, 0, 0, 443, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #871 = DSTST
5644 { 870, 3, 0, 4, 526, 0, 0, 446, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #870 = DST64
5645 { 869, 3, 0, 4, 526, 0, 0, 443, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #869 = DST
5646 { 868, 0, 0, 4, 496, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #868 = DSSALL
5647 { 867, 1, 0, 4, 496, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #867 = DSS
5648 { 866, 3, 1, 4, 244, 0, 1, 437, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #866 = DSCRI_rec
5649 { 865, 3, 1, 4, 247, 0, 1, 440, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #865 = DSCRIQ_rec
5650 { 864, 3, 1, 4, 247, 0, 0, 440, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #864 = DSCRIQ
5651 { 863, 3, 1, 4, 244, 0, 0, 437, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #863 = DSCRI
5652 { 862, 3, 1, 4, 244, 0, 1, 437, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #862 = DSCLI_rec
5653 { 861, 3, 1, 4, 247, 0, 1, 440, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #861 = DSCLIQ_rec
5654 { 860, 3, 1, 4, 247, 0, 0, 440, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #860 = DSCLIQ
5655 { 859, 3, 1, 4, 244, 0, 0, 437, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #859 = DSCLI
5656 { 858, 2, 1, 4, 252, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #858 = DRSP_rec
5657 { 857, 2, 1, 4, 252, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #857 = DRSP
5658 { 856, 4, 1, 4, 244, 0, 1, 415, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #856 = DRRND_rec
5659 { 855, 4, 1, 4, 247, 0, 1, 433, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #855 = DRRNDQ_rec
5660 { 854, 4, 1, 4, 247, 0, 0, 433, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #854 = DRRNDQ
5661 { 853, 4, 1, 4, 244, 0, 0, 415, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #853 = DRRND
5662 { 852, 4, 1, 4, 244, 0, 1, 419, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #852 = DRINTX_rec
5663 { 851, 4, 1, 4, 247, 0, 1, 423, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #851 = DRINTXQ_rec
5664 { 850, 4, 1, 4, 247, 0, 0, 423, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #850 = DRINTXQ
5665 { 849, 4, 1, 4, 244, 0, 0, 419, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #849 = DRINTX
5666 { 848, 4, 1, 4, 244, 0, 1, 419, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #848 = DRINTN_rec
5667 { 847, 4, 1, 4, 247, 0, 1, 423, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #847 = DRINTNQ_rec
5668 { 846, 4, 1, 4, 247, 0, 0, 423, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #846 = DRINTNQ
5669 { 845, 4, 1, 4, 244, 0, 0, 419, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #845 = DRINTN
5670 { 844, 2, 1, 4, 12, 0, 1, 431, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #844 = DRDPQ_rec
5671 { 843, 2, 1, 4, 12, 0, 0, 431, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #843 = DRDPQ
5672 { 842, 4, 1, 4, 244, 0, 1, 415, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #842 = DQUA_rec
5673 { 841, 4, 1, 4, 251, 0, 1, 427, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #841 = DQUAQ_rec
5674 { 840, 4, 1, 4, 251, 0, 0, 427, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #840 = DQUAQ
5675 { 839, 4, 1, 4, 0, 0, 1, 419, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #839 = DQUAI_rec
5676 { 838, 4, 1, 4, 247, 0, 1, 423, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #838 = DQUAIQ_rec
5677 { 837, 4, 1, 4, 247, 0, 0, 423, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #837 = DQUAIQ
5678 { 836, 4, 1, 4, 244, 0, 0, 419, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #836 = DQUAI
5679 { 835, 4, 1, 4, 244, 0, 0, 415, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #835 = DQUA
5680 { 834, 6, 1, 4, 0, 0, 0, 409, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #834 = DMXXSHAPAD
5681 { 833, 1, 1, 4, 19, 0, 0, 408, PPCImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #833 = DMXXSETACCZ
5682 { 832, 3, 1, 4, 0, 0, 0, 405, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #832 = DMXXINSTDMR512_HI
5683 { 831, 3, 1, 4, 0, 0, 0, 402, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #831 = DMXXINSTDMR512
5684 { 830, 3, 1, 4, 0, 0, 0, 399, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #830 = DMXXINSTDMR256
5685 { 829, 3, 2, 4, 0, 0, 0, 396, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #829 = DMXXEXTFDMR512_HI
5686 { 828, 3, 2, 4, 0, 0, 0, 393, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #828 = DMXXEXTFDMR512
5687 { 827, 3, 1, 4, 0, 0, 0, 390, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #827 = DMXXEXTFDMR256
5688 { 826, 4, 1, 4, 19, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #826 = DMXVI8GERX4SPP
5689 { 825, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #825 = DMXVI8GERX4PP
5690 { 824, 3, 1, 4, 5, 0, 0, 383, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #824 = DMXVI8GERX4
5691 { 823, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #823 = DMXVF16GERX2PP
5692 { 822, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #822 = DMXVF16GERX2PN
5693 { 821, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #821 = DMXVF16GERX2NP
5694 { 820, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #820 = DMXVF16GERX2NN
5695 { 819, 3, 1, 4, 5, 0, 0, 383, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #819 = DMXVF16GERX2
5696 { 818, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #818 = DMXVBF16GERX2PP
5697 { 817, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #817 = DMXVBF16GERX2PN
5698 { 816, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #816 = DMXVBF16GERX2NP
5699 { 815, 4, 1, 4, 5, 0, 0, 386, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #815 = DMXVBF16GERX2NN
5700 { 814, 3, 1, 4, 5, 0, 0, 383, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #814 = DMXVBF16GERX2
5701 { 813, 3, 1, 4, 0, 0, 0, 380, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #813 = DMXOR
5702 { 812, 3, 1, 4, 255, 0, 1, 336, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #812 = DMUL_rec
5703 { 811, 3, 1, 4, 256, 0, 1, 339, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #811 = DMULQ_rec
5704 { 810, 3, 1, 4, 256, 0, 0, 339, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #810 = DMULQ
5705 { 809, 3, 1, 4, 255, 0, 0, 336, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #809 = DMUL
5706 { 808, 3, 1, 4, 0, 0, 0, 377, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #808 = DMSHA3HASH
5707 { 807, 4, 1, 4, 0, 0, 0, 373, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #807 = DMSHA2HASH
5708 { 806, 1, 1, 4, 0, 0, 0, 372, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #806 = DMSETDMRZ
5709 { 805, 2, 1, 4, 0, 0, 0, 370, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #805 = DMMR
5710 { 804, 3, 1, 4, 389, 0, 1, 222, PPCImpOpBase + 0, 0, 0xdULL }, // Inst #804 = DIVW_rec
5711 { 803, 3, 1, 4, 389, 0, 1, 222, PPCImpOpBase + 0, 0, 0xdULL }, // Inst #803 = DIVWU_rec
5712 { 802, 3, 1, 4, 389, 0, 2, 222, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #802 = DIVWUO_rec
5713 { 801, 3, 1, 4, 383, 0, 1, 222, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #801 = DIVWUO
5714 { 800, 3, 1, 4, 209, 0, 0, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #800 = DIVWU
5715 { 799, 3, 1, 4, 389, 0, 2, 222, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #799 = DIVWO_rec
5716 { 798, 3, 1, 4, 383, 0, 1, 222, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #798 = DIVWO
5717 { 797, 3, 1, 4, 154, 0, 1, 222, PPCImpOpBase + 0, 0, 0xdULL }, // Inst #797 = DIVWE_rec
5718 { 796, 3, 1, 4, 154, 0, 1, 222, PPCImpOpBase + 0, 0, 0xdULL }, // Inst #796 = DIVWEU_rec
5719 { 795, 3, 1, 4, 154, 0, 2, 222, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #795 = DIVWEUO_rec
5720 { 794, 3, 1, 4, 385, 0, 1, 222, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #794 = DIVWEUO
5721 { 793, 3, 1, 4, 211, 0, 0, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #793 = DIVWEU
5722 { 792, 3, 1, 4, 154, 0, 2, 222, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #792 = DIVWEO_rec
5723 { 791, 3, 1, 4, 385, 0, 1, 222, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #791 = DIVWEO
5724 { 790, 3, 1, 4, 211, 0, 0, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #790 = DIVWE
5725 { 789, 3, 1, 4, 209, 0, 0, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #789 = DIVW
5726 { 788, 3, 1, 4, 155, 0, 1, 228, PPCImpOpBase + 0, 0, 0xdULL }, // Inst #788 = DIVD_rec
5727 { 787, 3, 1, 4, 155, 0, 1, 228, PPCImpOpBase + 0, 0, 0xdULL }, // Inst #787 = DIVDU_rec
5728 { 786, 3, 1, 4, 155, 0, 2, 228, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #786 = DIVDUO_rec
5729 { 785, 3, 1, 4, 386, 0, 1, 228, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #785 = DIVDUO
5730 { 784, 3, 1, 4, 210, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #784 = DIVDU
5731 { 783, 3, 1, 4, 155, 0, 2, 228, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #783 = DIVDO_rec
5732 { 782, 3, 1, 4, 386, 0, 1, 228, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #782 = DIVDO
5733 { 781, 3, 1, 4, 153, 0, 1, 228, PPCImpOpBase + 0, 0, 0xdULL }, // Inst #781 = DIVDE_rec
5734 { 780, 3, 1, 4, 153, 0, 1, 228, PPCImpOpBase + 0, 0, 0xdULL }, // Inst #780 = DIVDEU_rec
5735 { 779, 3, 1, 4, 153, 0, 2, 228, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #779 = DIVDEUO_rec
5736 { 778, 3, 1, 4, 388, 0, 1, 228, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #778 = DIVDEUO
5737 { 777, 3, 1, 4, 388, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #777 = DIVDEU
5738 { 776, 3, 1, 4, 153, 0, 2, 228, PPCImpOpBase + 3, 0, 0x8ULL }, // Inst #776 = DIVDEO_rec
5739 { 775, 3, 1, 4, 388, 0, 1, 228, PPCImpOpBase + 2, 0, 0x8ULL }, // Inst #775 = DIVDEO
5740 { 774, 3, 1, 4, 388, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #774 = DIVDE
5741 { 773, 3, 1, 4, 210, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #773 = DIVD
5742 { 772, 3, 1, 4, 244, 0, 1, 336, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #772 = DIEX_rec
5743 { 771, 3, 1, 4, 247, 0, 1, 367, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #771 = DIEXQ_rec
5744 { 770, 3, 1, 4, 247, 0, 0, 367, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #770 = DIEXQ
5745 { 769, 3, 1, 4, 244, 0, 0, 336, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #769 = DIEX
5746 { 768, 3, 1, 4, 244, 0, 1, 361, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #768 = DENBCD_rec
5747 { 767, 3, 1, 4, 247, 0, 1, 364, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #767 = DENBCDQ_rec
5748 { 766, 3, 1, 4, 247, 0, 0, 364, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #766 = DENBCDQ
5749 { 765, 3, 1, 4, 244, 0, 0, 361, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #765 = DENBCD
5750 { 764, 3, 1, 4, 257, 0, 1, 336, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #764 = DDIV_rec
5751 { 763, 3, 1, 4, 258, 0, 1, 339, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #763 = DDIVQ_rec
5752 { 762, 3, 1, 4, 258, 0, 0, 339, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #762 = DDIVQ
5753 { 761, 3, 1, 4, 257, 0, 0, 336, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #761 = DDIV
5754 { 760, 3, 1, 4, 244, 0, 1, 361, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #760 = DDEDPD_rec
5755 { 759, 3, 1, 4, 247, 0, 1, 364, PPCImpOpBase + 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #759 = DDEDPDQ_rec
5756 { 758, 3, 1, 4, 247, 0, 0, 364, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #758 = DDEDPDQ
5757 { 757, 3, 1, 4, 244, 0, 0, 361, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #757 = DDEDPD
5758 { 756, 2, 1, 4, 249, 0, 1, 347, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #756 = DCTQPQ_rec
5759 { 755, 2, 1, 4, 249, 0, 0, 347, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #755 = DCTQPQ
5760 { 754, 2, 1, 4, 252, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #754 = DCTFIX_rec
5761 { 753, 2, 1, 4, 12, 0, 1, 357, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #753 = DCTFIXQ_rec
5762 { 752, 2, 1, 4, 12, 0, 0, 359, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #752 = DCTFIXQQ
5763 { 751, 2, 1, 4, 12, 0, 0, 357, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #751 = DCTFIXQ
5764 { 750, 2, 1, 4, 252, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #750 = DCTFIX
5765 { 749, 2, 1, 4, 245, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #749 = DCTDP_rec
5766 { 748, 2, 1, 4, 245, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #748 = DCTDP
5767 { 747, 3, 1, 4, 248, 0, 0, 354, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #747 = DCMPUQ
5768 { 746, 3, 1, 4, 243, 0, 0, 351, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #746 = DCMPU
5769 { 745, 3, 1, 4, 248, 0, 0, 354, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #745 = DCMPOQ
5770 { 744, 3, 1, 4, 243, 0, 0, 351, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #744 = DCMPO
5771 { 743, 2, 1, 4, 253, 0, 1, 345, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #743 = DCFFIX_rec
5772 { 742, 2, 1, 4, 254, 0, 1, 347, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #742 = DCFFIXQ_rec
5773 { 741, 2, 1, 4, 12, 0, 0, 349, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #741 = DCFFIXQQ
5774 { 740, 2, 1, 4, 254, 0, 0, 347, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #740 = DCFFIXQ
5775 { 739, 2, 1, 4, 253, 0, 0, 345, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL }, // Inst #739 = DCFFIX
5776 { 738, 2, 0, 4, 618, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #738 = DCCCI
5777 { 737, 2, 0, 4, 336, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #737 = DCBZLEP
5778 { 736, 2, 0, 4, 617, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #736 = DCBZL
5779 { 735, 2, 0, 4, 336, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #735 = DCBZEP
5780 { 734, 2, 0, 4, 605, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #734 = DCBZ
5781 { 733, 3, 0, 4, 336, 0, 0, 189, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #733 = DCBTSTEP
5782 { 732, 3, 0, 4, 548, 0, 0, 342, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #732 = DCBTST
5783 { 731, 3, 0, 4, 336, 0, 0, 189, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #731 = DCBTEP
5784 { 730, 3, 0, 4, 548, 0, 0, 342, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #730 = DCBT
5785 { 729, 2, 0, 4, 336, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #729 = DCBSTEP
5786 { 728, 2, 0, 4, 605, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #728 = DCBST
5787 { 727, 2, 0, 4, 426, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #727 = DCBI
5788 { 726, 2, 0, 4, 336, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #726 = DCBFEP
5789 { 725, 3, 0, 4, 605, 0, 0, 342, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #725 = DCBF
5790 { 724, 2, 0, 4, 426, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #724 = DCBA
5791 { 723, 2, 1, 4, 342, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #723 = DARN
5792 { 722, 3, 1, 4, 245, 0, 1, 336, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #722 = DADD_rec
5793 { 721, 3, 1, 4, 250, 0, 1, 339, PPCImpOpBase + 131, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #721 = DADDQ_rec
5794 { 720, 3, 1, 4, 250, 0, 0, 339, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #720 = DADDQ
5795 { 719, 3, 1, 4, 245, 0, 0, 336, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #719 = DADD
5796 { 718, 3, 0, 4, 446, 0, 0, 288, PPCImpOpBase + 0, 0|(1ULL<<MCID::Branch), 0x38ULL }, // Inst #718 = CTRL_DEP
5797 { 717, 3, 1, 4, 304, 0, 0, 331, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #717 = CRXOR
5798 { 716, 1, 1, 4, 525, 0, 0, 296, PPCImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #716 = CRUNSET
5799 { 715, 1, 1, 4, 525, 0, 0, 296, PPCImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #715 = CRSET
5800 { 714, 3, 1, 4, 525, 0, 0, 331, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #714 = CRORC
5801 { 713, 3, 1, 4, 525, 0, 0, 331, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #713 = CROR
5802 { 712, 2, 1, 4, 107, 0, 0, 334, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #712 = CRNOT
5803 { 711, 3, 1, 4, 525, 0, 0, 331, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #711 = CRNOR
5804 { 710, 3, 1, 4, 525, 0, 0, 331, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #710 = CRNAND
5805 { 709, 3, 1, 4, 525, 0, 0, 331, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #709 = CREQV
5806 { 708, 3, 1, 4, 525, 0, 0, 331, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #708 = CRANDC
5807 { 707, 3, 1, 4, 525, 0, 0, 331, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #707 = CRAND
5808 { 706, 0, 0, 4, 525, 0, 1, 1, PPCImpOpBase + 130, 0, 0x0ULL }, // Inst #706 = CR6UNSET
5809 { 705, 0, 0, 4, 525, 0, 1, 1, PPCImpOpBase + 130, 0, 0x0ULL }, // Inst #705 = CR6SET
5810 { 704, 3, 0, 4, 358, 0, 1, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #704 = CP_PASTE_rec
5811 { 703, 3, 0, 4, 358, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #703 = CP_PASTE8_rec
5812 { 702, 3, 0, 4, 337, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #702 = CP_COPY8
5813 { 701, 3, 0, 4, 337, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #701 = CP_COPY
5814 { 700, 0, 0, 4, 341, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #700 = CP_ABORT
5815 { 699, 2, 1, 4, 279, 0, 1, 259, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #699 = CNTTZW_rec
5816 { 698, 2, 1, 4, 279, 0, 1, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #698 = CNTTZW8_rec
5817 { 697, 2, 1, 4, 279, 0, 0, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #697 = CNTTZW8
5818 { 696, 2, 1, 4, 279, 0, 0, 259, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #696 = CNTTZW
5819 { 695, 2, 1, 4, 279, 0, 1, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #695 = CNTTZD_rec
5820 { 694, 3, 1, 4, 148, 0, 0, 228, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #694 = CNTTZDM
5821 { 693, 2, 1, 4, 279, 0, 0, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #693 = CNTTZD
5822 { 692, 2, 1, 4, 205, 0, 1, 259, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #692 = CNTLZW_rec
5823 { 691, 2, 1, 4, 205, 0, 1, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #691 = CNTLZW8_rec
5824 { 690, 2, 1, 4, 205, 0, 0, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #690 = CNTLZW8
5825 { 689, 2, 1, 4, 205, 0, 0, 259, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #689 = CNTLZW
5826 { 688, 2, 1, 4, 205, 0, 1, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #688 = CNTLZD_rec
5827 { 687, 3, 1, 4, 148, 0, 0, 228, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #687 = CNTLZDM
5828 { 686, 2, 1, 4, 205, 0, 0, 261, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #686 = CNTLZD
5829 { 685, 3, 1, 4, 505, 0, 0, 320, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #685 = CMPWI
5830 { 684, 3, 1, 4, 140, 0, 0, 317, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #684 = CMPW
5831 { 683, 4, 1, 4, 274, 0, 0, 327, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #683 = CMPRB8
5832 { 682, 4, 1, 4, 274, 0, 0, 323, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #682 = CMPRB
5833 { 681, 3, 1, 4, 505, 0, 0, 320, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #681 = CMPLWI
5834 { 680, 3, 1, 4, 140, 0, 0, 317, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #680 = CMPLW
5835 { 679, 3, 1, 4, 505, 0, 0, 314, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #679 = CMPLDI
5836 { 678, 3, 1, 4, 140, 0, 0, 311, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #678 = CMPLD
5837 { 677, 3, 1, 4, 274, 0, 0, 311, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #677 = CMPEQB
5838 { 676, 3, 1, 4, 505, 0, 0, 314, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #676 = CMPDI
5839 { 675, 3, 1, 4, 140, 0, 0, 311, PPCImpOpBase + 0, 0|(1ULL<<MCID::Compare), 0x8ULL }, // Inst #675 = CMPD
5840 { 674, 3, 1, 4, 524, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #674 = CMPB8
5841 { 673, 3, 1, 4, 524, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #673 = CMPB
5842 { 672, 0, 0, 4, 619, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #672 = CLRBHRB
5843 { 671, 3, 1, 4, 449, 0, 0, 228, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #671 = CFUGED
5844 { 670, 2, 1, 4, 469, 0, 0, 261, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #670 = CDTBCD8
5845 { 669, 2, 1, 4, 469, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #669 = CDTBCD
5846 { 668, 2, 1, 4, 469, 0, 0, 261, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #668 = CBCDTD8
5847 { 667, 2, 1, 4, 469, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #667 = CBCDTD
5848 { 666, 2, 1, 4, 577, 0, 0, 261, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #666 = BRW8
5849 { 665, 2, 1, 4, 577, 0, 0, 259, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #665 = BRW
5850 { 664, 3, 1, 4, 405, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #664 = BRINC
5851 { 663, 2, 1, 4, 577, 0, 0, 261, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #663 = BRH8
5852 { 662, 2, 1, 4, 577, 0, 0, 259, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #662 = BRH
5853 { 661, 2, 1, 4, 577, 0, 0, 261, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #661 = BRD
5854 { 660, 3, 1, 4, 281, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #660 = BPERMD
5855 { 659, 2, 0, 4, 242, 1, 1, 13, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #659 = BL_TLS
5856 { 658, 1, 0, 4, 242, 1, 2, 285, PPCImpOpBase + 125, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #658 = BL_RM
5857 { 657, 1, 0, 8, 242, 1, 2, 285, PPCImpOpBase + 125, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #657 = BL_NOP_RM
5858 { 656, 1, 0, 8, 242, 1, 1, 285, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #656 = BL_NOP
5859 { 655, 0, 0, 4, 445, 2, 1, 1, PPCImpOpBase + 75, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #655 = BLRL
5860 { 654, 0, 0, 4, 445, 2, 0, 1, PPCImpOpBase + 128, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #654 = BLR8
5861 { 653, 0, 0, 4, 445, 2, 0, 1, PPCImpOpBase + 73, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #653 = BLR
5862 { 652, 1, 0, 4, 242, 1, 2, 0, PPCImpOpBase + 125, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #652 = BLA_RM
5863 { 651, 1, 0, 4, 242, 1, 2, 0, PPCImpOpBase + 122, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #651 = BLA8_RM
5864 { 650, 1, 0, 8, 242, 1, 2, 0, PPCImpOpBase + 122, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #650 = BLA8_NOP_RM
5865 { 649, 1, 0, 8, 242, 1, 1, 0, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #649 = BLA8_NOP
5866 { 648, 1, 0, 4, 242, 1, 1, 0, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #648 = BLA8
5867 { 647, 1, 0, 4, 242, 1, 1, 0, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #647 = BLA
5868 { 646, 2, 0, 4, 242, 1, 1, 13, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #646 = BL8_TLS_
5869 { 645, 2, 0, 4, 242, 1, 1, 13, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #645 = BL8_TLS
5870 { 644, 1, 0, 4, 242, 1, 2, 285, PPCImpOpBase + 122, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #644 = BL8_RM
5871 { 643, 2, 0, 4, 101, 1, 1, 13, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #643 = BL8_NOTOC_TLS
5872 { 642, 1, 0, 4, 101, 1, 2, 285, PPCImpOpBase + 122, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #642 = BL8_NOTOC_RM
5873 { 641, 1, 0, 4, 101, 1, 1, 285, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #641 = BL8_NOTOC
5874 { 640, 2, 0, 8, 242, 1, 1, 13, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #640 = BL8_NOP_TLS
5875 { 639, 1, 0, 8, 242, 1, 2, 285, PPCImpOpBase + 122, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #639 = BL8_NOP_RM
5876 { 638, 1, 0, 8, 242, 1, 1, 285, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #638 = BL8_NOP
5877 { 637, 1, 0, 4, 242, 1, 1, 285, PPCImpOpBase + 120, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #637 = BL8
5878 { 636, 1, 0, 4, 242, 1, 1, 285, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #636 = BL
5879 { 635, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #635 = BDZp
5880 { 634, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #634 = BDZm
5881 { 633, 1, 0, 4, 102, 2, 1, 285, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #633 = BDZLp
5882 { 632, 1, 0, 4, 102, 2, 1, 285, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #632 = BDZLm
5883 { 631, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #631 = BDZLRp
5884 { 630, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #630 = BDZLRm
5885 { 629, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #629 = BDZLRLp
5886 { 628, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #628 = BDZLRLm
5887 { 627, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #627 = BDZLRL
5888 { 626, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 116, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #626 = BDZLR8
5889 { 625, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #625 = BDZLR
5890 { 624, 1, 0, 4, 102, 2, 1, 0, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #624 = BDZLAp
5891 { 623, 1, 0, 4, 102, 2, 1, 0, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #623 = BDZLAm
5892 { 622, 1, 0, 4, 102, 2, 1, 0, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #622 = BDZLA
5893 { 621, 1, 0, 4, 102, 2, 1, 285, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #621 = BDZL
5894 { 620, 1, 0, 4, 102, 1, 1, 0, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #620 = BDZAp
5895 { 619, 1, 0, 4, 102, 1, 1, 0, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #619 = BDZAm
5896 { 618, 1, 0, 4, 102, 1, 1, 0, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #618 = BDZA
5897 { 617, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 107, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #617 = BDZ8
5898 { 616, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #616 = BDZ
5899 { 615, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #615 = BDNZp
5900 { 614, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #614 = BDNZm
5901 { 613, 1, 0, 4, 102, 2, 1, 285, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #613 = BDNZLp
5902 { 612, 1, 0, 4, 102, 2, 1, 285, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #612 = BDNZLm
5903 { 611, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #611 = BDNZLRp
5904 { 610, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #610 = BDNZLRm
5905 { 609, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #609 = BDNZLRLp
5906 { 608, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #608 = BDNZLRLm
5907 { 607, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #607 = BDNZLRL
5908 { 606, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 116, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #606 = BDNZLR8
5909 { 605, 0, 0, 4, 445, 3, 1, 1, PPCImpOpBase + 112, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #605 = BDNZLR
5910 { 604, 1, 0, 4, 102, 2, 1, 0, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #604 = BDNZLAp
5911 { 603, 1, 0, 4, 102, 2, 1, 0, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #603 = BDNZLAm
5912 { 602, 1, 0, 4, 102, 2, 1, 0, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #602 = BDNZLA
5913 { 601, 1, 0, 4, 102, 2, 1, 285, PPCImpOpBase + 109, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #601 = BDNZL
5914 { 600, 1, 0, 4, 102, 1, 1, 0, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #600 = BDNZAp
5915 { 599, 1, 0, 4, 102, 1, 1, 0, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #599 = BDNZAm
5916 { 598, 1, 0, 4, 102, 1, 1, 0, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #598 = BDNZA
5917 { 597, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 107, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #597 = BDNZ8
5918 { 596, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #596 = BDNZ
5919 { 595, 2, 0, 4, 102, 0, 0, 286, PPCImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #595 = BCn
5920 { 594, 0, 0, 4, 102, 2, 2, 1, PPCImpOpBase + 101, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL }, // Inst #594 = BCTRL_RM
5921 { 593, 2, 0, 8, 102, 2, 3, 309, PPCImpOpBase + 96, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #593 = BCTRL_LWZinto_toc_RM
5922 { 592, 2, 0, 8, 102, 2, 2, 309, PPCImpOpBase + 92, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #592 = BCTRL_LWZinto_toc
5923 { 591, 0, 0, 4, 102, 2, 2, 1, PPCImpOpBase + 88, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL }, // Inst #591 = BCTRL8_RM
5924 { 590, 2, 0, 8, 102, 2, 3, 309, PPCImpOpBase + 83, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #590 = BCTRL8_LDinto_toc_RM
5925 { 589, 2, 0, 8, 102, 2, 2, 309, PPCImpOpBase + 79, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #589 = BCTRL8_LDinto_toc
5926 { 588, 0, 0, 4, 102, 2, 1, 1, PPCImpOpBase + 68, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL }, // Inst #588 = BCTRL8
5927 { 587, 0, 0, 4, 102, 2, 1, 1, PPCImpOpBase + 65, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL }, // Inst #587 = BCTRL
5928 { 586, 0, 0, 4, 102, 1, 0, 1, PPCImpOpBase + 64, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #586 = BCTR8
5929 { 585, 0, 0, 4, 102, 1, 0, 1, PPCImpOpBase + 63, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #585 = BCTR
5930 { 584, 2, 0, 4, 102, 1, 1, 286, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #584 = BCLn
5931 { 583, 1, 0, 4, 102, 1, 1, 285, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #583 = BCLalways
5932 { 582, 1, 0, 4, 445, 2, 0, 296, PPCImpOpBase + 73, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #582 = BCLRn
5933 { 581, 1, 0, 4, 445, 2, 1, 296, PPCImpOpBase + 75, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #581 = BCLRLn
5934 { 580, 1, 0, 4, 445, 2, 1, 296, PPCImpOpBase + 75, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #580 = BCLRL
5935 { 579, 1, 0, 4, 445, 2, 0, 296, PPCImpOpBase + 73, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #579 = BCLR
5936 { 578, 2, 0, 4, 102, 1, 1, 286, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #578 = BCL
5937 { 577, 3, 1, 4, 465, 0, 1, 304, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #577 = BCDUTRUNC_rec
5938 { 576, 3, 1, 4, 465, 0, 1, 304, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #576 = BCDUS_rec
5939 { 575, 4, 1, 4, 465, 0, 1, 297, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #575 = BCDTRUNC_rec
5940 { 574, 4, 1, 4, 465, 0, 1, 297, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #574 = BCDS_rec
5941 { 573, 4, 1, 4, 246, 0, 1, 297, PPCImpOpBase + 78, 0, 0x0ULL }, // Inst #573 = BCDSUB_rec
5942 { 572, 4, 1, 4, 327, 0, 1, 297, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #572 = BCDSR_rec
5943 { 571, 3, 1, 4, 463, 0, 1, 301, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #571 = BCDSETSGN_rec
5944 { 570, 3, 1, 4, 463, 0, 1, 301, PPCImpOpBase + 78, 0, 0x0ULL }, // Inst #570 = BCDCTZ_rec
5945 { 569, 2, 1, 4, 328, 0, 1, 307, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = BCDCTSQ_rec
5946 { 568, 2, 1, 4, 463, 0, 1, 307, PPCImpOpBase + 78, 0, 0x0ULL }, // Inst #568 = BCDCTN_rec
5947 { 567, 3, 1, 4, 465, 0, 1, 304, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #567 = BCDCPSGN_rec
5948 { 566, 3, 1, 4, 463, 0, 1, 301, PPCImpOpBase + 78, 0, 0x0ULL }, // Inst #566 = BCDCFZ_rec
5949 { 565, 3, 1, 4, 330, 0, 1, 301, PPCImpOpBase + 78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #565 = BCDCFSQ_rec
5950 { 564, 3, 1, 4, 463, 0, 1, 301, PPCImpOpBase + 78, 0, 0x0ULL }, // Inst #564 = BCDCFN_rec
5951 { 563, 4, 1, 4, 246, 0, 1, 297, PPCImpOpBase + 78, 0, 0x0ULL }, // Inst #563 = BCDADD_rec
5952 { 562, 1, 0, 4, 445, 1, 0, 296, PPCImpOpBase + 63, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #562 = BCCTRn
5953 { 561, 1, 0, 4, 445, 2, 1, 296, PPCImpOpBase + 65, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #561 = BCCTRLn
5954 { 560, 1, 0, 4, 445, 2, 1, 296, PPCImpOpBase + 68, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #560 = BCCTRL8n
5955 { 559, 1, 0, 4, 445, 2, 1, 296, PPCImpOpBase + 68, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #559 = BCCTRL8
5956 { 558, 1, 0, 4, 445, 2, 1, 296, PPCImpOpBase + 65, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #558 = BCCTRL
5957 { 557, 1, 0, 4, 445, 1, 0, 296, PPCImpOpBase + 64, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #557 = BCCTR8n
5958 { 556, 1, 0, 4, 445, 1, 0, 296, PPCImpOpBase + 64, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #556 = BCCTR8
5959 { 555, 1, 0, 4, 445, 1, 0, 296, PPCImpOpBase + 63, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #555 = BCCTR
5960 { 554, 2, 0, 4, 445, 2, 1, 294, PPCImpOpBase + 75, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #554 = BCCLRL
5961 { 553, 2, 0, 4, 445, 2, 0, 294, PPCImpOpBase + 73, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #553 = BCCLR
5962 { 552, 3, 0, 4, 445, 1, 1, 291, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #552 = BCCLA
5963 { 551, 3, 0, 4, 445, 1, 1, 288, PPCImpOpBase + 71, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #551 = BCCL
5964 { 550, 2, 0, 4, 445, 2, 1, 294, PPCImpOpBase + 68, 0|(1ULL<<MCID::Call), 0x38ULL }, // Inst #550 = BCCCTRL8
5965 { 549, 2, 0, 4, 445, 2, 1, 294, PPCImpOpBase + 65, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL }, // Inst #549 = BCCCTRL
5966 { 548, 2, 0, 4, 445, 1, 0, 294, PPCImpOpBase + 64, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #548 = BCCCTR8
5967 { 547, 2, 0, 4, 445, 1, 0, 294, PPCImpOpBase + 63, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #547 = BCCCTR
5968 { 546, 3, 0, 4, 445, 0, 0, 291, PPCImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #546 = BCCA
5969 { 545, 3, 0, 4, 445, 0, 0, 288, PPCImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #545 = BCC
5970 { 544, 2, 0, 4, 102, 0, 0, 286, PPCImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #544 = BC
5971 { 543, 1, 0, 4, 242, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #543 = BA
5972 { 542, 1, 0, 4, 242, 0, 0, 285, PPCImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL }, // Inst #542 = B
5973 { 541, 0, 0, 4, 616, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #541 = ATTN
5974 { 540, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #540 = ATOMIC_SWAP_I8
5975 { 539, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #539 = ATOMIC_SWAP_I64
5976 { 538, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #538 = ATOMIC_SWAP_I32
5977 { 537, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #537 = ATOMIC_SWAP_I16
5978 { 536, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #536 = ATOMIC_LOAD_XOR_I8
5979 { 535, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #535 = ATOMIC_LOAD_XOR_I64
5980 { 534, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #534 = ATOMIC_LOAD_XOR_I32
5981 { 533, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #533 = ATOMIC_LOAD_XOR_I16
5982 { 532, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #532 = ATOMIC_LOAD_UMIN_I8
5983 { 531, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #531 = ATOMIC_LOAD_UMIN_I64
5984 { 530, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #530 = ATOMIC_LOAD_UMIN_I32
5985 { 529, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #529 = ATOMIC_LOAD_UMIN_I16
5986 { 528, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #528 = ATOMIC_LOAD_UMAX_I8
5987 { 527, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #527 = ATOMIC_LOAD_UMAX_I64
5988 { 526, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #526 = ATOMIC_LOAD_UMAX_I32
5989 { 525, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #525 = ATOMIC_LOAD_UMAX_I16
5990 { 524, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #524 = ATOMIC_LOAD_SUB_I8
5991 { 523, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #523 = ATOMIC_LOAD_SUB_I64
5992 { 522, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #522 = ATOMIC_LOAD_SUB_I32
5993 { 521, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #521 = ATOMIC_LOAD_SUB_I16
5994 { 520, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #520 = ATOMIC_LOAD_OR_I8
5995 { 519, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #519 = ATOMIC_LOAD_OR_I64
5996 { 518, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #518 = ATOMIC_LOAD_OR_I32
5997 { 517, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #517 = ATOMIC_LOAD_OR_I16
5998 { 516, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #516 = ATOMIC_LOAD_NAND_I8
5999 { 515, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #515 = ATOMIC_LOAD_NAND_I64
6000 { 514, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #514 = ATOMIC_LOAD_NAND_I32
6001 { 513, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #513 = ATOMIC_LOAD_NAND_I16
6002 { 512, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #512 = ATOMIC_LOAD_MIN_I8
6003 { 511, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #511 = ATOMIC_LOAD_MIN_I64
6004 { 510, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #510 = ATOMIC_LOAD_MIN_I32
6005 { 509, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #509 = ATOMIC_LOAD_MIN_I16
6006 { 508, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #508 = ATOMIC_LOAD_MAX_I8
6007 { 507, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #507 = ATOMIC_LOAD_MAX_I64
6008 { 506, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #506 = ATOMIC_LOAD_MAX_I32
6009 { 505, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #505 = ATOMIC_LOAD_MAX_I16
6010 { 504, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #504 = ATOMIC_LOAD_AND_I8
6011 { 503, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #503 = ATOMIC_LOAD_AND_I64
6012 { 502, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #502 = ATOMIC_LOAD_AND_I32
6013 { 501, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #501 = ATOMIC_LOAD_AND_I16
6014 { 500, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #500 = ATOMIC_LOAD_ADD_I8
6015 { 499, 4, 1, 4, 0, 0, 1, 281, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #499 = ATOMIC_LOAD_ADD_I64
6016 { 498, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #498 = ATOMIC_LOAD_ADD_I32
6017 { 497, 4, 1, 4, 0, 0, 1, 277, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #497 = ATOMIC_LOAD_ADD_I16
6018 { 496, 5, 1, 4, 0, 0, 1, 267, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #496 = ATOMIC_CMP_SWAP_I8
6019 { 495, 5, 1, 4, 0, 0, 1, 272, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #495 = ATOMIC_CMP_SWAP_I64
6020 { 494, 5, 1, 4, 0, 0, 1, 267, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #494 = ATOMIC_CMP_SWAP_I32
6021 { 493, 5, 1, 4, 0, 0, 1, 267, PPCImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #493 = ATOMIC_CMP_SWAP_I16
6022 { 492, 3, 1, 4, 198, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #492 = AND_rec
6023 { 491, 2, 1, 4, 0, 0, 1, 265, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #491 = ANDI_rec_1_GT_BIT8
6024 { 490, 2, 1, 4, 0, 0, 1, 263, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #490 = ANDI_rec_1_GT_BIT
6025 { 489, 2, 1, 4, 0, 0, 1, 265, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #489 = ANDI_rec_1_EQ_BIT8
6026 { 488, 2, 1, 4, 0, 0, 1, 263, PPCImpOpBase + 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #488 = ANDI_rec_1_EQ_BIT
6027 { 487, 3, 1, 4, 504, 0, 1, 184, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #487 = ANDI_rec
6028 { 486, 3, 1, 4, 504, 0, 1, 184, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #486 = ANDIS_rec
6029 { 485, 3, 1, 4, 502, 0, 1, 181, PPCImpOpBase + 0, 0, 0x208ULL }, // Inst #485 = ANDIS8_rec
6030 { 484, 3, 1, 4, 502, 0, 1, 181, PPCImpOpBase + 0, 0, 0x308ULL }, // Inst #484 = ANDI8_rec
6031 { 483, 3, 1, 4, 198, 0, 1, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #483 = ANDC_rec
6032 { 482, 3, 1, 4, 198, 0, 1, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #482 = ANDC8_rec
6033 { 481, 3, 1, 4, 198, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #481 = ANDC8
6034 { 480, 3, 1, 4, 198, 0, 0, 222, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #480 = ANDC
6035 { 479, 3, 1, 4, 198, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #479 = AND8_rec
6036 { 478, 3, 1, 4, 198, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #478 = AND8
6037 { 477, 3, 1, 4, 198, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #477 = AND
6038 { 476, 2, 0, 4, 0, 1, 1, 21, PPCImpOpBase + 61, 0, 0x0ULL }, // Inst #476 = ADJCALLSTACKUP
6039 { 475, 2, 0, 4, 0, 1, 1, 21, PPCImpOpBase + 61, 0, 0x0ULL }, // Inst #475 = ADJCALLSTACKDOWN
6040 { 474, 2, 1, 4, 532, 1, 2, 259, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #474 = ADDZE_rec
6041 { 473, 2, 1, 4, 532, 1, 3, 259, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #473 = ADDZEO_rec
6042 { 472, 2, 1, 4, 502, 1, 2, 259, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #472 = ADDZEO
6043 { 471, 2, 1, 4, 532, 1, 2, 261, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #471 = ADDZE8_rec
6044 { 470, 2, 1, 4, 532, 1, 3, 261, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #470 = ADDZE8O_rec
6045 { 469, 2, 1, 4, 502, 1, 2, 261, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #469 = ADDZE8O
6046 { 468, 2, 1, 4, 503, 1, 1, 261, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #468 = ADDZE8
6047 { 467, 2, 1, 4, 503, 1, 1, 259, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #467 = ADDZE
6048 { 466, 2, 1, 4, 143, 0, 0, 217, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #466 = ADDPCIS
6049 { 465, 2, 1, 4, 532, 1, 2, 259, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #465 = ADDME_rec
6050 { 464, 2, 1, 4, 532, 1, 3, 259, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #464 = ADDMEO_rec
6051 { 463, 2, 1, 4, 502, 1, 2, 259, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #463 = ADDMEO
6052 { 462, 2, 1, 4, 532, 1, 2, 261, PPCImpOpBase + 22, 0, 0x8ULL }, // Inst #462 = ADDME8_rec
6053 { 461, 2, 1, 4, 532, 1, 3, 261, PPCImpOpBase + 18, 0, 0x8ULL }, // Inst #461 = ADDME8O_rec
6054 { 460, 2, 1, 4, 502, 1, 2, 261, PPCImpOpBase + 15, 0, 0x8ULL }, // Inst #460 = ADDME8O
6055 { 459, 2, 1, 4, 501, 1, 1, 261, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #459 = ADDME8
6056 { 458, 2, 1, 4, 501, 1, 1, 259, PPCImpOpBase + 13, 0, 0x8ULL }, // Inst #458 = ADDME
6057 { 457, 3, 1, 4, 288, 0, 0, 231, PPCImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #457 = ADDItocL8
6058 { 456, 3, 1, 4, 288, 0, 0, 248, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = ADDItocL
6059 { 455, 3, 1, 4, 227, 0, 0, 231, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #455 = ADDItoc8
6060 { 454, 3, 1, 4, 227, 0, 0, 225, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #454 = ADDItoc
6061 { 453, 4, 1, 4, 500, 0, 18, 255, PPCImpOpBase + 43, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = ADDItlsldLADDR32
6062 { 452, 4, 1, 4, 0, 0, 18, 251, PPCImpOpBase + 25, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = ADDItlsldLADDR
6063 { 451, 3, 1, 4, 0, 0, 0, 245, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #451 = ADDItlsldL32
6064 { 450, 3, 1, 4, 0, 0, 0, 208, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #450 = ADDItlsldL
6065 { 449, 4, 1, 4, 227, 0, 18, 255, PPCImpOpBase + 43, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = ADDItlsgdLADDR32
6066 { 448, 4, 1, 4, 227, 0, 18, 251, PPCImpOpBase + 25, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = ADDItlsgdLADDR
6067 { 447, 3, 1, 4, 227, 0, 0, 245, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #447 = ADDItlsgdL32
6068 { 446, 3, 1, 4, 227, 0, 0, 208, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #446 = ADDItlsgdL
6069 { 445, 3, 1, 4, 499, 0, 0, 245, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #445 = ADDIdtprelL32
6070 { 444, 3, 1, 4, 227, 0, 0, 208, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #444 = ADDIdtprelL
6071 { 443, 3, 1, 4, 288, 0, 0, 231, PPCImpOpBase + 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #443 = ADDIStocHA8
6072 { 442, 3, 1, 4, 288, 0, 0, 248, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #442 = ADDIStocHA
6073 { 441, 3, 1, 4, 0, 0, 0, 208, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #441 = ADDIStlsldHA
6074 { 440, 3, 1, 4, 227, 0, 0, 208, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #440 = ADDIStlsgdHA
6075 { 439, 3, 1, 4, 227, 0, 0, 208, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #439 = ADDISgotTprelHA
6076 { 438, 3, 1, 4, 499, 0, 0, 245, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #438 = ADDISdtprelHA32
6077 { 437, 3, 1, 4, 227, 0, 0, 208, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #437 = ADDISdtprelHA
6078 { 436, 3, 1, 4, 498, 0, 0, 208, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #436 = ADDIS8
6079 { 435, 3, 1, 4, 498, 0, 0, 245, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #435 = ADDIS
6080 { 434, 3, 1, 4, 532, 0, 2, 184, PPCImpOpBase + 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL }, // Inst #434 = ADDIC_rec
6081 { 433, 3, 1, 4, 501, 0, 1, 181, PPCImpOpBase + 5, 0, 0x8ULL }, // Inst #433 = ADDIC8
6082 { 432, 3, 1, 4, 501, 0, 1, 184, PPCImpOpBase + 5, 0, 0xcULL }, // Inst #432 = ADDIC
6083 { 431, 3, 1, 4, 498, 0, 0, 208, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #431 = ADDI8
6084 { 430, 3, 1, 4, 498, 0, 0, 245, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #430 = ADDI
6085 { 429, 3, 1, 4, 203, 0, 0, 228, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #429 = ADDG6S8
6086 { 428, 3, 1, 4, 203, 0, 0, 222, PPCImpOpBase + 0, 0, 0x0ULL }, // Inst #428 = ADDG6S
6087 { 427, 3, 1, 4, 534, 1, 2, 222, PPCImpOpBase + 22, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #427 = ADDE_rec
6088 { 426, 4, 1, 4, 522, 0, 0, 241, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #426 = ADDEX8
6089 { 425, 4, 1, 4, 522, 0, 0, 237, PPCImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #425 = ADDEX
6090 { 424, 3, 1, 4, 534, 1, 3, 222, PPCImpOpBase + 18, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #424 = ADDEO_rec
6091 { 423, 3, 1, 4, 521, 1, 2, 222, PPCImpOpBase + 15, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #423 = ADDEO
6092 { 422, 3, 1, 4, 534, 1, 2, 228, PPCImpOpBase + 22, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #422 = ADDE8_rec
6093 { 421, 3, 1, 4, 534, 1, 3, 228, PPCImpOpBase + 18, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #421 = ADDE8O_rec
6094 { 420, 3, 1, 4, 521, 1, 2, 228, PPCImpOpBase + 15, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #420 = ADDE8O
6095 { 419, 3, 1, 4, 139, 1, 1, 228, PPCImpOpBase + 13, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #419 = ADDE8
6096 { 418, 3, 1, 4, 139, 1, 1, 222, PPCImpOpBase + 13, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #418 = ADDE
6097 { 417, 3, 1, 4, 538, 0, 2, 222, PPCImpOpBase + 11, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #417 = ADDC_rec
6098 { 416, 3, 1, 4, 390, 0, 3, 222, PPCImpOpBase + 8, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #416 = ADDCO_rec
6099 { 415, 3, 1, 4, 286, 0, 2, 222, PPCImpOpBase + 6, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #415 = ADDCO
6100 { 414, 3, 1, 4, 538, 0, 2, 228, PPCImpOpBase + 11, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #414 = ADDC8_rec
6101 { 413, 3, 1, 4, 390, 0, 3, 228, PPCImpOpBase + 8, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #413 = ADDC8O_rec
6102 { 412, 3, 1, 4, 286, 0, 2, 228, PPCImpOpBase + 6, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #412 = ADDC8O
6103 { 411, 3, 1, 4, 286, 0, 1, 228, PPCImpOpBase + 5, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #411 = ADDC8
6104 { 410, 3, 1, 4, 286, 0, 1, 222, PPCImpOpBase + 5, 0|(1ULL<<MCID::Commutable), 0xcULL }, // Inst #410 = ADDC
6105 { 409, 3, 1, 4, 198, 0, 1, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #409 = ADD8_rec
6106 { 408, 3, 1, 4, 138, 0, 0, 234, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #408 = ADD8TLS_
6107 { 407, 3, 1, 4, 138, 0, 0, 231, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #407 = ADD8TLS
6108 { 406, 3, 1, 4, 141, 0, 2, 228, PPCImpOpBase + 3, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #406 = ADD8O_rec
6109 { 405, 3, 1, 4, 523, 0, 1, 228, PPCImpOpBase + 2, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #405 = ADD8O
6110 { 404, 3, 1, 4, 138, 0, 0, 228, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #404 = ADD8
6111 { 403, 3, 1, 4, 198, 0, 1, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #403 = ADD4_rec
6112 { 402, 3, 1, 4, 138, 0, 0, 225, PPCImpOpBase + 0, 0, 0x8ULL }, // Inst #402 = ADD4TLS
6113 { 401, 3, 1, 4, 141, 0, 2, 222, PPCImpOpBase + 3, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #401 = ADD4O_rec
6114 { 400, 3, 1, 4, 523, 0, 1, 222, PPCImpOpBase + 2, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #400 = ADD4O
6115 { 399, 3, 1, 4, 138, 0, 0, 222, PPCImpOpBase + 0, 0|(1ULL<<MCID::Commutable), 0x8ULL }, // Inst #399 = ADD4
6116 { 398, 3, 0, 4, 369, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #398 = XFSTOREf64
6117 { 397, 3, 0, 4, 369, 0, 0, 219, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #397 = XFSTOREf32
6118 { 396, 3, 1, 4, 214, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #396 = XFLOADf64
6119 { 395, 3, 1, 4, 364, 0, 0, 219, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #395 = XFLOADf32
6120 { 394, 2, 0, 0, 0, 0, 0, 217, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #394 = SUBPCIS
6121 { 393, 3, 0, 0, 0, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #393 = SUBIS
6122 { 392, 3, 0, 0, 0, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #392 = SUBIC_rec
6123 { 391, 3, 0, 0, 0, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #391 = SUBIC
6124 { 390, 3, 0, 0, 0, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #390 = SUBI
6125 { 389, 3, 0, 4, 608, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #389 = STIWX
6126 { 388, 3, 0, 0, 202, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #388 = SRWI_rec
6127 { 387, 3, 0, 0, 202, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #387 = SRWI
6128 { 386, 3, 0, 0, 202, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #386 = SRDI_rec
6129 { 385, 3, 0, 0, 202, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #385 = SRDI
6130 { 384, 3, 0, 4, 607, 0, 0, 214, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x40ULL }, // Inst #384 = SPILLTOVSR_STX
6131 { 383, 3, 0, 4, 597, 0, 0, 211, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #383 = SPILLTOVSR_ST
6132 { 382, 3, 1, 4, 551, 0, 0, 214, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #382 = SPILLTOVSR_LDX
6133 { 381, 3, 1, 4, 542, 0, 0, 211, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #381 = SPILLTOVSR_LD
6134 { 380, 3, 0, 0, 202, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #380 = SLWI_rec
6135 { 379, 3, 0, 0, 202, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #379 = SLWI
6136 { 378, 3, 0, 0, 202, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #378 = SLDI_rec
6137 { 377, 3, 0, 0, 202, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #377 = SLDI
6138 { 376, 3, 0, 0, 0, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #376 = ROTRWI_rec
6139 { 375, 3, 0, 0, 0, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #375 = ROTRWI
6140 { 374, 3, 0, 0, 0, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #374 = ROTRDI_rec
6141 { 373, 3, 0, 0, 0, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #373 = ROTRDI
6142 { 372, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #372 = RLWNMbm_rec
6143 { 371, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #371 = RLWNMbm
6144 { 370, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #370 = RLWINMbm_rec
6145 { 369, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #369 = RLWINMbm
6146 { 368, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #368 = RLWIMIbm_rec
6147 { 367, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #367 = RLWIMIbm
6148 { 366, 3, 0, 0, 0, 0, 0, 208, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #366 = PSUBI
6149 { 365, 2, 1, 4, 0, 0, 0, 206, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #365 = PPCLdFixedAddr
6150 { 364, 3, 1, 4, 214, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #364 = LIWZX
6151 { 363, 3, 1, 4, 361, 0, 0, 203, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL }, // Inst #363 = LIWAX
6152 { 362, 3, 0, 0, 0, 0, 0, 200, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x400ULL }, // Inst #362 = LAx
6153 { 361, 2, 1, 4, 0, 0, 0, 198, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #361 = KILL_PAIR
6154 { 360, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #360 = INSRWI_rec
6155 { 359, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #359 = INSRWI
6156 { 358, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #358 = INSRDI_rec
6157 { 357, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #357 = INSRDI
6158 { 356, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #356 = INSLWI_rec
6159 { 355, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #355 = INSLWI
6160 { 354, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #354 = EXTRWI_rec
6161 { 353, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #353 = EXTRWI
6162 { 352, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #352 = EXTRDI_rec
6163 { 351, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #351 = EXTRDI
6164 { 350, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #350 = EXTLWI_rec
6165 { 349, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #349 = EXTLWI
6166 { 348, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #348 = EXTLDI_rec
6167 { 347, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #347 = EXTLDI
6168 { 346, 3, 0, 4, 599, 0, 0, 195, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #346 = DFSTOREf64
6169 { 345, 3, 0, 4, 599, 0, 0, 192, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #345 = DFSTOREf32
6170 { 344, 3, 1, 4, 544, 0, 0, 195, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #344 = DFLOADf64
6171 { 343, 3, 1, 4, 543, 0, 0, 192, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #343 = DFLOADf32
6172 { 342, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #342 = DCBTx
6173 { 341, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #341 = DCBTT
6174 { 340, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #340 = DCBTSTx
6175 { 339, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #339 = DCBTSTT
6176 { 338, 3, 0, 0, 0, 0, 0, 189, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #338 = DCBTSTDS
6177 { 337, 3, 0, 0, 0, 0, 0, 189, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #337 = DCBTSTCT
6178 { 336, 3, 0, 0, 0, 0, 0, 189, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #336 = DCBTDS
6179 { 335, 3, 0, 0, 0, 0, 0, 189, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #335 = DCBTCT
6180 { 334, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #334 = DCBSTPS
6181 { 333, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #333 = DCBFx
6182 { 332, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #332 = DCBFPS
6183 { 331, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #331 = DCBFLP
6184 { 330, 2, 0, 0, 0, 0, 0, 187, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #330 = DCBFL
6185 { 329, 3, 0, 0, 0, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #329 = CLRRWI_rec
6186 { 328, 3, 0, 0, 0, 0, 0, 184, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #328 = CLRRWI
6187 { 327, 3, 0, 0, 0, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #327 = CLRRDI_rec
6188 { 326, 3, 0, 0, 0, 0, 0, 181, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #326 = CLRRDI
6189 { 325, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #325 = CLRLSLWI_rec
6190 { 324, 4, 0, 0, 0, 0, 0, 177, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #324 = CLRLSLWI
6191 { 323, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #323 = CLRLSLDI_rec
6192 { 322, 4, 0, 0, 0, 0, 0, 173, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #322 = CLRLSLDI
6193 { 321, 1, 0, 4, 1, 0, 1, 172, PPCImpOpBase + 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #321 = CFENCE8
6194 { 320, 1, 0, 4, 1, 0, 1, 171, PPCImpOpBase + 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #320 = CFENCE
6195 { 319, 2, 1, 4, 0, 0, 0, 169, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #319 = BUILD_UACC
6196 { 318, 3, 1, 4, 0, 0, 0, 166, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #318 = BUILD_QUADWORD
6197 { 317, 6, 2, 4, 0, 0, 1, 160, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #317 = ATOMIC_SWAP_I128
6198 { 316, 6, 2, 4, 0, 0, 1, 160, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #316 = ATOMIC_LOAD_XOR_I128
6199 { 315, 6, 2, 4, 0, 0, 1, 160, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #315 = ATOMIC_LOAD_SUB_I128
6200 { 314, 6, 2, 4, 0, 0, 1, 160, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #314 = ATOMIC_LOAD_OR_I128
6201 { 313, 6, 2, 4, 0, 0, 1, 160, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #313 = ATOMIC_LOAD_NAND_I128
6202 { 312, 6, 2, 4, 0, 0, 1, 160, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #312 = ATOMIC_LOAD_AND_I128
6203 { 311, 6, 2, 4, 0, 0, 1, 160, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #311 = ATOMIC_LOAD_ADD_I128
6204 { 310, 8, 2, 4, 0, 0, 1, 152, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #310 = ATOMIC_CMP_SWAP_I128
6205 { 309, 4, 1, 0, 0, 0, 0, 148, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #309 = G_UBFX
6206 { 308, 4, 1, 0, 0, 0, 0, 148, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #308 = G_SBFX
6207 { 307, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
6208 { 306, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
6209 { 305, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
6210 { 304, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
6211 { 303, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
6212 { 302, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
6213 { 301, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
6214 { 300, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
6215 { 299, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
6216 { 298, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
6217 { 297, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
6218 { 296, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
6219 { 295, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
6220 { 294, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
6221 { 293, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
6222 { 292, 3, 1, 0, 0, 0, 0, 131, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
6223 { 291, 3, 1, 0, 0, 0, 0, 131, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
6224 { 290, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #290 = G_UBSANTRAP
6225 { 289, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
6226 { 288, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #288 = G_TRAP
6227 { 287, 3, 0, 0, 0, 0, 0, 58, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #287 = G_BZERO
6228 { 286, 4, 0, 0, 0, 0, 0, 144, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #286 = G_MEMSET
6229 { 285, 4, 0, 0, 0, 0, 0, 144, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #285 = G_MEMMOVE
6230 { 284, 3, 0, 0, 0, 0, 0, 131, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
6231 { 283, 4, 0, 0, 0, 0, 0, 144, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #283 = G_MEMCPY
6232 { 282, 2, 0, 0, 0, 0, 0, 142, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
6233 { 281, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
6234 { 280, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
6235 { 279, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
6236 { 278, 4, 1, 0, 0, 0, 0, 46, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #278 = G_STRICT_FMA
6237 { 277, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #277 = G_STRICT_FREM
6238 { 276, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
6239 { 275, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
6240 { 274, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
6241 { 273, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_STRICT_FADD
6242 { 272, 1, 0, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #272 = G_STACKRESTORE
6243 { 271, 1, 1, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = G_STACKSAVE
6244 { 270, 3, 1, 0, 0, 0, 0, 69, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
6245 { 269, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
6246 { 268, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
6247 { 267, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
6248 { 266, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #266 = G_FNEARBYINT
6249 { 265, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #265 = G_FRINT
6250 { 264, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #264 = G_FFLOOR
6251 { 263, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #263 = G_FSQRT
6252 { 262, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #262 = G_FTANH
6253 { 261, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #261 = G_FSINH
6254 { 260, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_FCOSH
6255 { 259, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_FATAN2
6256 { 258, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_FATAN
6257 { 257, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_FASIN
6258 { 256, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_FACOS
6259 { 255, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_FTAN
6260 { 254, 3, 2, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_FSINCOS
6261 { 253, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_FSIN
6262 { 252, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FCOS
6263 { 251, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FCEIL
6264 { 250, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_BITREVERSE
6265 { 249, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_BSWAP
6266 { 248, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_CTPOP
6267 { 247, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
6268 { 246, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_CTLZ
6269 { 245, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
6270 { 244, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_CTTZ
6271 { 243, 4, 1, 0, 0, 0, 0, 138, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
6272 { 242, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
6273 { 241, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
6274 { 240, 4, 1, 0, 0, 0, 0, 134, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
6275 { 239, 3, 1, 0, 0, 0, 0, 131, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
6276 { 238, 4, 1, 0, 0, 0, 0, 127, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
6277 { 237, 3, 1, 0, 0, 0, 0, 58, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
6278 { 236, 4, 1, 0, 0, 0, 0, 63, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
6279 { 235, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_VSCALE
6280 { 234, 3, 0, 0, 0, 0, 0, 124, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #234 = G_BRJT
6281 { 233, 1, 0, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #233 = G_BR
6282 { 232, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_LLROUND
6283 { 231, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_LROUND
6284 { 230, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_ABS
6285 { 229, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #229 = G_UMAX
6286 { 228, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #228 = G_UMIN
6287 { 227, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #227 = G_SMAX
6288 { 226, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #226 = G_SMIN
6289 { 225, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_PTRMASK
6290 { 224, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_PTR_ADD
6291 { 223, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
6292 { 222, 1, 0, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #222 = G_SET_FPMODE
6293 { 221, 1, 1, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #221 = G_GET_FPMODE
6294 { 220, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #220 = G_RESET_FPENV
6295 { 219, 1, 0, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #219 = G_SET_FPENV
6296 { 218, 1, 1, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #218 = G_GET_FPENV
6297 { 217, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
6298 { 216, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
6299 { 215, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_FMAXIMUM
6300 { 214, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_FMINIMUM
6301 { 213, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
6302 { 212, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
6303 { 211, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #211 = G_FMAXNUM
6304 { 210, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #210 = G_FMINNUM
6305 { 209, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
6306 { 208, 3, 1, 0, 0, 0, 0, 98, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
6307 { 207, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
6308 { 206, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #206 = G_FABS
6309 { 205, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
6310 { 204, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
6311 { 203, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_UITOFP
6312 { 202, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #202 = G_SITOFP
6313 { 201, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #201 = G_FPTOUI
6314 { 200, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FPTOSI
6315 { 199, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FPTRUNC
6316 { 198, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FPEXT
6317 { 197, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FNEG
6318 { 196, 3, 2, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FFREXP
6319 { 195, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_FLDEXP
6320 { 194, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FLOG10
6321 { 193, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FLOG2
6322 { 192, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FLOG
6323 { 191, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FEXP10
6324 { 190, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FEXP2
6325 { 189, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FEXP
6326 { 188, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FPOWI
6327 { 187, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FPOW
6328 { 186, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FREM
6329 { 185, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FDIV
6330 { 184, 4, 1, 0, 0, 0, 0, 46, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FMAD
6331 { 183, 4, 1, 0, 0, 0, 0, 46, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FMA
6332 { 182, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #182 = G_FMUL
6333 { 181, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FSUB
6334 { 180, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #180 = G_FADD
6335 { 179, 4, 1, 0, 0, 0, 0, 120, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
6336 { 178, 4, 1, 0, 0, 0, 0, 120, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
6337 { 177, 4, 1, 0, 0, 0, 0, 120, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_UDIVFIX
6338 { 176, 4, 1, 0, 0, 0, 0, 120, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_SDIVFIX
6339 { 175, 4, 1, 0, 0, 0, 0, 120, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
6340 { 174, 4, 1, 0, 0, 0, 0, 120, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
6341 { 173, 4, 1, 0, 0, 0, 0, 120, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_UMULFIX
6342 { 172, 4, 1, 0, 0, 0, 0, 120, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_SMULFIX
6343 { 171, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SSHLSAT
6344 { 170, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_USHLSAT
6345 { 169, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SSUBSAT
6346 { 168, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_USUBSAT
6347 { 167, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SADDSAT
6348 { 166, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UADDSAT
6349 { 165, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULH
6350 { 164, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_UMULH
6351 { 163, 4, 2, 0, 0, 0, 0, 87, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_SMULO
6352 { 162, 4, 2, 0, 0, 0, 0, 87, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #162 = G_UMULO
6353 { 161, 5, 2, 0, 0, 0, 0, 115, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBE
6354 { 160, 4, 2, 0, 0, 0, 0, 87, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_SSUBO
6355 { 159, 5, 2, 0, 0, 0, 0, 115, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #159 = G_SADDE
6356 { 158, 4, 2, 0, 0, 0, 0, 87, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SADDO
6357 { 157, 5, 2, 0, 0, 0, 0, 115, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #157 = G_USUBE
6358 { 156, 4, 2, 0, 0, 0, 0, 87, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #156 = G_USUBO
6359 { 155, 5, 2, 0, 0, 0, 0, 115, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #155 = G_UADDE
6360 { 154, 4, 2, 0, 0, 0, 0, 87, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UADDO
6361 { 153, 4, 1, 0, 0, 0, 0, 87, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SELECT
6362 { 152, 3, 1, 0, 0, 0, 0, 112, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_UCMP
6363 { 151, 3, 1, 0, 0, 0, 0, 112, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SCMP
6364 { 150, 4, 1, 0, 0, 0, 0, 108, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_FCMP
6365 { 149, 4, 1, 0, 0, 0, 0, 108, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_ICMP
6366 { 148, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_ROTL
6367 { 147, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_ROTR
6368 { 146, 4, 1, 0, 0, 0, 0, 104, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_FSHR
6369 { 145, 4, 1, 0, 0, 0, 0, 104, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_FSHL
6370 { 144, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_ASHR
6371 { 143, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_LSHR
6372 { 142, 3, 1, 0, 0, 0, 0, 101, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_SHL
6373 { 141, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ZEXT
6374 { 140, 3, 1, 0, 0, 0, 0, 40, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_SEXT_INREG
6375 { 139, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_SEXT
6376 { 138, 3, 1, 0, 0, 0, 0, 98, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #138 = G_VAARG
6377 { 137, 1, 0, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #137 = G_VASTART
6378 { 136, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_FCONSTANT
6379 { 135, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_CONSTANT
6380 { 134, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_TRUNC
6381 { 133, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ANYEXT
6382 { 132, 1, 0, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
6383 { 131, 1, 0, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
6384 { 130, 1, 0, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
6385 { 129, 1, 0, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #129 = G_INTRINSIC
6386 { 128, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
6387 { 127, 1, 0, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #127 = G_BRINDIRECT
6388 { 126, 2, 0, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #126 = G_BRCOND
6389 { 125, 4, 0, 0, 0, 0, 0, 94, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #125 = G_PREFETCH
6390 { 124, 2, 0, 0, 0, 0, 0, 21, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #124 = G_FENCE
6391 { 123, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
6392 { 122, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
6393 { 121, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
6394 { 120, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
6395 { 119, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
6396 { 118, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
6397 { 117, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
6398 { 116, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
6399 { 115, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
6400 { 114, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
6401 { 113, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
6402 { 112, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
6403 { 111, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
6404 { 110, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
6405 { 109, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
6406 { 108, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
6407 { 107, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
6408 { 106, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
6409 { 105, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
6410 { 104, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
6411 { 103, 3, 1, 0, 0, 0, 0, 91, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
6412 { 102, 4, 1, 0, 0, 0, 0, 87, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
6413 { 101, 5, 2, 0, 0, 0, 0, 82, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
6414 { 100, 5, 1, 0, 0, 0, 0, 77, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
6415 { 99, 2, 0, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_STORE
6416 { 98, 5, 2, 0, 0, 0, 0, 72, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
6417 { 97, 5, 2, 0, 0, 0, 0, 72, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
6418 { 96, 5, 2, 0, 0, 0, 0, 72, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
6419 { 95, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
6420 { 94, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_SEXTLOAD
6421 { 93, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_LOAD
6422 { 92, 1, 1, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
6423 { 91, 1, 1, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
6424 { 90, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
6425 { 89, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
6426 { 88, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
6427 { 87, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
6428 { 86, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
6429 { 85, 3, 1, 0, 0, 0, 0, 69, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
6430 { 84, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
6431 { 83, 2, 1, 0, 0, 0, 0, 67, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_FREEZE
6432 { 82, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_BITCAST
6433 { 81, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTTOPTR
6434 { 80, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_PTRTOINT
6435 { 79, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
6436 { 78, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
6437 { 77, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
6438 { 76, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
6439 { 75, 4, 1, 0, 0, 0, 0, 63, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #75 = G_INSERT
6440 { 74, 2, 1, 0, 0, 0, 0, 61, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
6441 { 73, 3, 1, 0, 0, 0, 0, 58, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_EXTRACT
6442 { 72, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
6443 { 71, 5, 1, 0, 0, 0, 0, 53, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
6444 { 70, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
6445 { 69, 2, 1, 0, 0, 0, 0, 51, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
6446 { 68, 1, 1, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #68 = G_PHI
6447 { 67, 1, 1, 0, 0, 0, 0, 50, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
6448 { 66, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #66 = G_ABDU
6449 { 65, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #65 = G_ABDS
6450 { 64, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #64 = G_XOR
6451 { 63, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_OR
6452 { 62, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_AND
6453 { 61, 4, 2, 0, 0, 0, 0, 46, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_UDIVREM
6454 { 60, 4, 2, 0, 0, 0, 0, 46, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_SDIVREM
6455 { 59, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UREM
6456 { 58, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SREM
6457 { 57, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UDIV
6458 { 56, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SDIV
6459 { 55, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #55 = G_MUL
6460 { 54, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SUB
6461 { 53, 3, 1, 0, 0, 0, 0, 43, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_ADD
6462 { 52, 3, 1, 0, 0, 0, 0, 40, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
6463 { 51, 3, 1, 0, 0, 0, 0, 40, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
6464 { 50, 3, 1, 0, 0, 0, 0, 40, PPCImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
6465 { 49, 1, 0, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
6466 { 48, 2, 1, 0, 0, 0, 0, 13, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
6467 { 47, 1, 1, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
6468 { 46, 1, 1, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
6469 { 45, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
6470 { 44, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #44 = MEMBARRIER
6471 { 43, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #43 = FAKE_USE
6472 { 42, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
6473 { 41, 3, 0, 0, 0, 0, 0, 37, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
6474 { 40, 2, 0, 0, 0, 0, 0, 35, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
6475 { 39, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
6476 { 38, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
6477 { 37, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_RET
6478 { 36, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
6479 { 35, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_OP
6480 { 34, 1, 1, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = FAULTING_OP
6481 { 33, 2, 0, 0, 0, 0, 0, 33, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
6482 { 32, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #32 = STATEPOINT
6483 { 31, 3, 1, 0, 0, 0, 0, 30, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
6484 { 30, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
6485 { 29, 1, 1, 0, 0, 0, 0, 29, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
6486 { 28, 6, 1, 0, 0, 0, 0, 23, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #28 = PATCHPOINT
6487 { 27, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = FENTRY_CALL
6488 { 26, 2, 0, 0, 0, 0, 0, 21, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = STACKMAP
6489 { 25, 2, 1, 0, 0, 0, 0, 19, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #25 = ARITH_FENCE
6490 { 24, 4, 0, 0, 0, 0, 0, 15, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
6491 { 23, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #23 = LIFETIME_END
6492 { 22, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_START
6493 { 21, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #21 = BUNDLE
6494 { 20, 2, 1, 0, 290, 0, 0, 13, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #20 = COPY
6495 { 19, 2, 1, 0, 0, 0, 0, 13, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = REG_SEQUENCE
6496 { 18, 1, 0, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #18 = DBG_LABEL
6497 { 17, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #17 = DBG_PHI
6498 { 16, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
6499 { 15, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
6500 { 14, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE
6501 { 13, 3, 1, 0, 0, 0, 0, 2, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
6502 { 12, 4, 1, 0, 0, 0, 0, 9, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
6503 { 11, 1, 1, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = INIT_UNDEF
6504 { 10, 1, 1, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
6505 { 9, 4, 1, 0, 0, 0, 0, 5, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
6506 { 8, 3, 1, 0, 0, 0, 0, 2, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
6507 { 7, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
6508 { 6, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
6509 { 5, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
6510 { 4, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
6511 { 3, 1, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
6512 { 2, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
6513 { 1, 0, 0, 0, 0, 0, 0, 1, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
6514 { 0, 1, 1, 0, 0, 0, 0, 0, PPCImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
6515 }, {
6516 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6517 /* 1 */
6518 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6519 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6520 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6521 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6522 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6523 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6524 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
6525 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6526 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6527 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
6528 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6529 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6530 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6531 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6532 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
6533 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6534 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6535 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6536 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6537 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6538 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
6539 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
6540 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
6541 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6542 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6543 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6544 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6545 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6546 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6547 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6548 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6549 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6550 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
6551 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
6552 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
6553 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
6554 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
6555 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
6556 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
6557 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
6558 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
6559 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6560 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6561 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
6562 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
6563 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
6564 /* 152 */ { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6565 /* 160 */ { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6566 /* 166 */ { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6567 /* 169 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::UACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6568 /* 171 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6569 /* 172 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6570 /* 173 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6571 /* 177 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6572 /* 181 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6573 /* 184 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6574 /* 187 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6575 /* 189 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6576 /* 192 */ { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6577 /* 195 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6578 /* 198 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
6579 /* 200 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6580 /* 203 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6581 /* 206 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6582 /* 208 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6583 /* 211 */ { PPC::SPILLTOVSRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6584 /* 214 */ { PPC::SPILLTOVSRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6585 /* 217 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6586 /* 219 */ { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6587 /* 222 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6588 /* 225 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6589 /* 228 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6590 /* 231 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6591 /* 234 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6592 /* 237 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6593 /* 241 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6594 /* 245 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6595 /* 248 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6596 /* 251 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6597 /* 255 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6598 /* 259 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6599 /* 261 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6600 /* 263 */ { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6601 /* 265 */ { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6602 /* 267 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6603 /* 272 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6604 /* 277 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6605 /* 281 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6606 /* 285 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },
6607 /* 286 */ { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
6608 /* 288 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
6609 /* 291 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6610 /* 294 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
6611 /* 296 */ { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6612 /* 297 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6613 /* 301 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6614 /* 304 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6615 /* 307 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6616 /* 309 */ { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6617 /* 311 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6618 /* 314 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6619 /* 317 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6620 /* 320 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6621 /* 323 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6622 /* 327 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6623 /* 331 */ { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6624 /* 334 */ { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6625 /* 336 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6626 /* 339 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6627 /* 342 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6628 /* 345 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6629 /* 347 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6630 /* 349 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6631 /* 351 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6632 /* 354 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6633 /* 357 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6634 /* 359 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6635 /* 361 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6636 /* 364 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6637 /* 367 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6638 /* 370 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6639 /* 372 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6640 /* 373 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6641 /* 377 */ { PPC::DMRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6642 /* 380 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6643 /* 383 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6644 /* 386 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6645 /* 390 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRROWpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6646 /* 393 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6647 /* 396 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACC_HIRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6648 /* 399 */ { PPC::DMRROWpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6649 /* 402 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6650 /* 405 */ { PPC::WACC_HIRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6651 /* 408 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6652 /* 409 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6653 /* 415 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6654 /* 419 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6655 /* 423 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6656 /* 427 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6657 /* 431 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6658 /* 433 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6659 /* 437 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6660 /* 440 */ { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6661 /* 443 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6662 /* 446 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6663 /* 449 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6664 /* 452 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6665 /* 455 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6666 /* 458 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6667 /* 461 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::FpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6668 /* 464 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6669 /* 468 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6670 /* 472 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6671 /* 475 */ { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6672 /* 477 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6673 /* 479 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6674 /* 482 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6675 /* 484 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6676 /* 487 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6677 /* 489 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6678 /* 490 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6679 /* 492 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6680 /* 495 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6681 /* 498 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6682 /* 501 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6683 /* 504 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6684 /* 508 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6685 /* 510 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6686 /* 513 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6687 /* 515 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6688 /* 518 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6689 /* 520 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6690 /* 523 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6691 /* 525 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6692 /* 528 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6693 /* 532 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6694 /* 536 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6695 /* 540 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6696 /* 542 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6697 /* 545 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6698 /* 549 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6699 /* 553 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6700 /* 556 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) },
6701 /* 560 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) },
6702 /* 564 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6703 /* 568 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6704 /* 572 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6705 /* 575 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6706 /* 578 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6707 /* 581 */ { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6708 /* 584 */ { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6709 /* 587 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6710 /* 590 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6711 /* 593 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6712 /* 596 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6713 /* 599 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) },
6714 /* 603 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6715 /* 607 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6716 /* 610 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6717 /* 613 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) },
6718 /* 617 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6719 /* 621 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6720 /* 624 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6721 /* 627 */ { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6722 /* 630 */ { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6723 /* 633 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6724 /* 636 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6725 /* 639 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6726 /* 642 */ { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6727 /* 645 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6728 /* 648 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6729 /* 651 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6730 /* 653 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6731 /* 656 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6732 /* 659 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6733 /* 662 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6734 /* 665 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6735 /* 669 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6736 /* 673 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6737 /* 675 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6738 /* 676 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6739 /* 679 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6740 /* 680 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6741 /* 682 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6742 /* 684 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6743 /* 686 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6744 /* 688 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6745 /* 690 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6746 /* 692 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6747 /* 693 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6748 /* 695 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6749 /* 697 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6750 /* 699 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6751 /* 701 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6752 /* 705 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6753 /* 708 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6754 /* 710 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6755 /* 712 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6756 /* 714 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6757 /* 716 */ { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6758 /* 718 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6759 /* 720 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6760 /* 722 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6761 /* 724 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6762 /* 726 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6763 /* 729 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6764 /* 731 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6765 /* 734 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
6766 /* 737 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
6767 /* 740 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6768 /* 743 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6769 /* 746 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
6770 /* 749 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6771 /* 752 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
6772 /* 755 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6773 /* 757 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6774 /* 760 */ { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
6775 /* 763 */ { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6776 /* 765 */ { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6777 /* 768 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
6778 /* 771 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
6779 /* 774 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6780 /* 776 */ { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6781 /* 779 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6782 /* 782 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6783 /* 788 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6784 /* 795 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6785 /* 801 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6786 /* 808 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6787 /* 814 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6788 /* 821 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6789 /* 826 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6790 /* 832 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6791 /* 837 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6792 /* 843 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6793 /* 848 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6794 /* 854 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6795 /* 859 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6796 /* 865 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6797 /* 872 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6798 /* 877 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6799 /* 882 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6800 /* 887 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6801 /* 892 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6802 /* 895 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6803 /* 898 */ { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6804 /* 901 */ { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6805 /* 904 */ { PPC::DMRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6806 /* 907 */ { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6807 /* 910 */ { PPC::UACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6808 /* 913 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6809 /* 916 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6810 /* 920 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6811 /* 924 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6812 /* 929 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6813 /* 935 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6814 /* 941 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6815 /* 946 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6816 /* 951 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6817 /* 956 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6818 /* 961 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6819 /* 966 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6820 /* 971 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6821 /* 976 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6822 /* 981 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6823 /* 986 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6824 /* 991 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6825 /* 996 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6826 /* 1001 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6827 /* 1005 */ { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6828 /* 1009 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6829 /* 1013 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6830 /* 1017 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6831 /* 1021 */ { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6832 /* 1025 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6833 /* 1029 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6834 /* 1033 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6835 /* 1035 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6836 /* 1037 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6837 /* 1039 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6838 /* 1041 */ { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6839 /* 1043 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6840 /* 1046 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6841 /* 1049 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) },
6842 /* 1053 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) },
6843 /* 1057 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6844 /* 1061 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6845 /* 1065 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) },
6846 /* 1069 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6847 /* 1073 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) },
6848 /* 1077 */ { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 },
6849 /* 1081 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6850 /* 1084 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6851 /* 1086 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6852 /* 1088 */ { PPC::CTRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6853 /* 1090 */ { PPC::CTRRC8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6854 /* 1092 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6855 /* 1095 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6856 /* 1098 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6857 /* 1102 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6858 /* 1105 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6859 /* 1108 */ { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6860 /* 1110 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6861 /* 1113 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6862 /* 1116 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6863 /* 1120 */ { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6864 /* 1122 */ { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6865 /* 1125 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6866 /* 1129 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6867 /* 1133 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6868 /* 1137 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6869 /* 1141 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6870 /* 1145 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6871 /* 1149 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
6872 /* 1153 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6873 /* 1157 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6874 /* 1160 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6875 /* 1162 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6876 /* 1165 */ { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6877 /* 1168 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6878 /* 1171 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6879 /* 1174 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6880 /* 1176 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6881 /* 1178 */ { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6882 /* 1180 */ { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6883 /* 1182 */ { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6884 /* 1184 */ { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6885 /* 1186 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6886 /* 1189 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6887 /* 1192 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6888 /* 1196 */ { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6889 /* 1200 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6890 /* 1204 */ { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6891 /* 1208 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6892 /* 1210 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6893 /* 1213 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6894 /* 1216 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6895 /* 1219 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6896 /* 1221 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6897 /* 1224 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6898 /* 1227 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6899 /* 1231 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6900 /* 1234 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6901 /* 1238 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6902 /* 1241 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6903 /* 1245 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6904 /* 1248 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6905 /* 1252 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6906 /* 1256 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6907 /* 1259 */ { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6908 /* 1261 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6909 /* 1264 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6910 /* 1268 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6911 /* 1273 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6912 /* 1276 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6913 /* 1279 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6914 /* 1283 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6915 /* 1284 */ { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6916 /* 1285 */ { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6917 /* 1286 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
6918 /* 1288 */ { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
6919 /* 1290 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6920 /* 1294 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6921 /* 1298 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6922 /* 1301 */ { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
6923 /* 1302 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6924 /* 1306 */ { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6925 /* 1309 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
6926 /* 1312 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6927 /* 1315 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
6928 /* 1319 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
6929 /* 1322 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 },
6930 }, {
6931 /* 0 */
6932 /* 0 */ PPC::CR0,
6933 /* 1 */ PPC::CR7,
6934 /* 2 */ PPC::XER,
6935 /* 3 */ PPC::XER, PPC::CR0,
6936 /* 5 */ PPC::CARRY,
6937 /* 6 */ PPC::CARRY, PPC::XER,
6938 /* 8 */ PPC::CARRY, PPC::XER, PPC::CR0,
6939 /* 11 */ PPC::CARRY, PPC::CR0,
6940 /* 13 */ PPC::CARRY, PPC::CARRY,
6941 /* 15 */ PPC::CARRY, PPC::CARRY, PPC::XER,
6942 /* 18 */ PPC::CARRY, PPC::CARRY, PPC::XER, PPC::CR0,
6943 /* 22 */ PPC::CARRY, PPC::CARRY, PPC::CR0,
6944 /* 25 */ PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7,
6945 /* 43 */ PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7,
6946 /* 61 */ PPC::R1, PPC::R1,
6947 /* 63 */ PPC::CTR,
6948 /* 64 */ PPC::CTR8,
6949 /* 65 */ PPC::CTR, PPC::RM, PPC::LR,
6950 /* 68 */ PPC::CTR8, PPC::RM, PPC::LR8,
6951 /* 71 */ PPC::RM, PPC::LR,
6952 /* 73 */ PPC::LR, PPC::RM,
6953 /* 75 */ PPC::LR, PPC::RM, PPC::LR,
6954 /* 78 */ PPC::CR6,
6955 /* 79 */ PPC::CTR8, PPC::RM, PPC::LR8, PPC::X2,
6956 /* 83 */ PPC::CTR8, PPC::RM, PPC::LR8, PPC::X2, PPC::RM,
6957 /* 88 */ PPC::CTR8, PPC::RM, PPC::LR8, PPC::RM,
6958 /* 92 */ PPC::CTR, PPC::RM, PPC::LR, PPC::R2,
6959 /* 96 */ PPC::CTR, PPC::RM, PPC::LR, PPC::R2, PPC::RM,
6960 /* 101 */ PPC::CTR, PPC::RM, PPC::LR, PPC::RM,
6961 /* 105 */ PPC::CTR, PPC::CTR,
6962 /* 107 */ PPC::CTR8, PPC::CTR8,
6963 /* 109 */ PPC::CTR, PPC::RM, PPC::CTR,
6964 /* 112 */ PPC::CTR, PPC::LR, PPC::RM, PPC::CTR,
6965 /* 116 */ PPC::CTR8, PPC::LR8, PPC::RM, PPC::CTR8,
6966 /* 120 */ PPC::RM, PPC::LR8,
6967 /* 122 */ PPC::RM, PPC::LR8, PPC::RM,
6968 /* 125 */ PPC::RM, PPC::LR, PPC::RM,
6969 /* 128 */ PPC::LR8, PPC::RM,
6970 /* 130 */ PPC::CR1EQ,
6971 /* 131 */ PPC::CR1,
6972 /* 132 */ PPC::X1, PPC::X1,
6973 /* 134 */ PPC::RM,
6974 /* 135 */ PPC::RM, PPC::CR1,
6975 /* 137 */ PPC::X0, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7,
6976 /* 154 */ PPC::R0, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7,
6977 /* 171 */ PPC::R0, PPC::R4, PPC::R5, PPC::R11, PPC::LR, PPC::CR0,
6978 /* 177 */ PPC::X0, PPC::X4, PPC::X5, PPC::X11, PPC::LR8, PPC::CR0,
6979 /* 183 */ PPC::X0, PPC::X2, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7,
6980 /* 201 */ PPC::R3, PPC::LR,
6981 /* 203 */ PPC::LR,
6982 /* 204 */ PPC::LR8,
6983 /* 205 */ PPC::RM, PPC::RM,
6984 /* 207 */ PPC::CTR, PPC::RM,
6985 /* 209 */ PPC::CTR8, PPC::RM,
6986 /* 211 */ PPC::RM, PPC::CR6,
6987 /* 213 */ PPC::CTR, PPC::LR, PPC::RM, PPC::LR, PPC::CTR,
6988 /* 218 */ PPC::CTR, PPC::RM, PPC::LR, PPC::CTR,
6989 }
6990};
6991
6992
6993#ifdef __GNUC__
6994#pragma GCC diagnostic push
6995#pragma GCC diagnostic ignored "-Woverlength-strings"
6996#endif
6997extern const char PPCInstrNameData[] = {
6998 /* 0 */ "G_FLOG10\000"
6999 /* 9 */ "SYNCP10\000"
7000 /* 17 */ "WAITP10\000"
7001 /* 25 */ "G_FEXP10\000"
7002 /* 34 */ "MTFSB0\000"
7003 /* 41 */ "V_SET0\000"
7004 /* 48 */ "VCTSXS_0\000"
7005 /* 57 */ "VCTUXS_0\000"
7006 /* 66 */ "VCFSX_0\000"
7007 /* 74 */ "VCFUX_0\000"
7008 /* 82 */ "MTFSB1\000"
7009 /* 89 */ "DMXXEXTFDMR512\000"
7010 /* 104 */ "DMXXINSTDMR512\000"
7011 /* 119 */ "ADDISdtprelHA32\000"
7012 /* 135 */ "ATOMIC_LOAD_SUB_I32\000"
7013 /* 155 */ "ATOMIC_LOAD_ADD_I32\000"
7014 /* 175 */ "ATOMIC_LOAD_NAND_I32\000"
7015 /* 196 */ "ATOMIC_LOAD_AND_I32\000"
7016 /* 216 */ "ATOMIC_LOAD_UMIN_I32\000"
7017 /* 237 */ "ATOMIC_LOAD_MIN_I32\000"
7018 /* 257 */ "ATOMIC_SWAP_I32\000"
7019 /* 273 */ "ATOMIC_CMP_SWAP_I32\000"
7020 /* 293 */ "ATOMIC_LOAD_XOR_I32\000"
7021 /* 313 */ "ATOMIC_LOAD_OR_I32\000"
7022 /* 332 */ "ATOMIC_LOAD_UMAX_I32\000"
7023 /* 353 */ "ATOMIC_LOAD_MAX_I32\000"
7024 /* 373 */ "ADDItlsgdL32\000"
7025 /* 386 */ "ADDItlsldL32\000"
7026 /* 399 */ "LDgotTprelL32\000"
7027 /* 413 */ "ADDIdtprelL32\000"
7028 /* 427 */ "ADDItlsgdLADDR32\000"
7029 /* 444 */ "ADDItlsldLADDR32\000"
7030 /* 461 */ "GETtlsldADDR32\000"
7031 /* 476 */ "GETtlsADDR32\000"
7032 /* 489 */ "PREPARE_PROBED_ALLOCA_32\000"
7033 /* 514 */ "LWA_32\000"
7034 /* 521 */ "PROBED_STACKALLOC_32\000"
7035 /* 542 */ "PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32\000"
7036 /* 584 */ "SRADI_32\000"
7037 /* 593 */ "RLDICL_32\000"
7038 /* 603 */ "RLDICR_32\000"
7039 /* 613 */ "LHAXTLS_32\000"
7040 /* 624 */ "LWAXTLS_32\000"
7041 /* 635 */ "STBXTLS_32\000"
7042 /* 646 */ "STHXTLS_32\000"
7043 /* 657 */ "STWXTLS_32\000"
7044 /* 668 */ "LBZXTLS_32\000"
7045 /* 679 */ "LHZXTLS_32\000"
7046 /* 690 */ "LWZXTLS_32\000"
7047 /* 701 */ "EXTSW_32\000"
7048 /* 710 */ "LWAX_32\000"
7049 /* 718 */ "DFLOADf32\000"
7050 /* 728 */ "XFLOADf32\000"
7051 /* 738 */ "DFSTOREf32\000"
7052 /* 749 */ "XFSTOREf32\000"
7053 /* 760 */ "EH_SjLj_LongJmp32\000"
7054 /* 778 */ "EH_SjLj_SetJmp32\000"
7055 /* 795 */ "TLBRE2\000"
7056 /* 802 */ "TLBWE2\000"
7057 /* 809 */ "G_FLOG2\000"
7058 /* 817 */ "G_FATAN2\000"
7059 /* 826 */ "G_FEXP2\000"
7060 /* 834 */ "PMXVBF16GER2\000"
7061 /* 847 */ "PMXVF16GER2\000"
7062 /* 859 */ "PMXVI16GER2\000"
7063 /* 871 */ "PMDMXVBF16GERX2\000"
7064 /* 887 */ "PMDMXVF16GERX2\000"
7065 /* 902 */ "TLBSX2\000"
7066 /* 909 */ "ATOMIC_LOAD_SUB_I64\000"
7067 /* 929 */ "ATOMIC_LOAD_ADD_I64\000"
7068 /* 949 */ "ATOMIC_LOAD_NAND_I64\000"
7069 /* 970 */ "ATOMIC_LOAD_AND_I64\000"
7070 /* 990 */ "ATOMIC_LOAD_UMIN_I64\000"
7071 /* 1011 */ "ATOMIC_LOAD_MIN_I64\000"
7072 /* 1031 */ "ATOMIC_SWAP_I64\000"
7073 /* 1047 */ "ATOMIC_CMP_SWAP_I64\000"
7074 /* 1067 */ "ATOMIC_LOAD_XOR_I64\000"
7075 /* 1087 */ "ATOMIC_LOAD_OR_I64\000"
7076 /* 1106 */ "ATOMIC_LOAD_UMAX_I64\000"
7077 /* 1127 */ "ATOMIC_LOAD_MAX_I64\000"
7078 /* 1147 */ "DST64\000"
7079 /* 1153 */ "DSTST64\000"
7080 /* 1161 */ "DSTT64\000"
7081 /* 1168 */ "DSTSTT64\000"
7082 /* 1177 */ "EXTSB8_32_64\000"
7083 /* 1190 */ "EXTSH8_32_64\000"
7084 /* 1203 */ "EXTSWSLI_32_64\000"
7085 /* 1218 */ "RLDICL_32_64\000"
7086 /* 1231 */ "EXTSW_32_64\000"
7087 /* 1243 */ "PREPARE_PROBED_ALLOCA_64\000"
7088 /* 1268 */ "PROBED_STACKALLOC_64\000"
7089 /* 1289 */ "PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64\000"
7090 /* 1331 */ "DFLOADf64\000"
7091 /* 1341 */ "XFLOADf64\000"
7092 /* 1351 */ "DFSTOREf64\000"
7093 /* 1362 */ "XFSTOREf64\000"
7094 /* 1373 */ "EH_SjLj_LongJmp64\000"
7095 /* 1391 */ "EH_SjLj_SetJmp64\000"
7096 /* 1408 */ "ADD4\000"
7097 /* 1413 */ "SELECT_CC_SPE4\000"
7098 /* 1428 */ "SELECT_SPE4\000"
7099 /* 1440 */ "SELECT_CC_F4\000"
7100 /* 1453 */ "SELECT_F4\000"
7101 /* 1463 */ "SELECT_CC_I4\000"
7102 /* 1476 */ "SELECT_I4\000"
7103 /* 1486 */ "PMXVI8GER4\000"
7104 /* 1497 */ "PMDMXVI8GERX4\000"
7105 /* 1511 */ "XVCVSPBF16\000"
7106 /* 1522 */ "SELECT_CC_F16\000"
7107 /* 1536 */ "SELECT_F16\000"
7108 /* 1547 */ "ATOMIC_LOAD_SUB_I16\000"
7109 /* 1567 */ "ATOMIC_LOAD_ADD_I16\000"
7110 /* 1587 */ "ATOMIC_LOAD_NAND_I16\000"
7111 /* 1608 */ "ATOMIC_LOAD_AND_I16\000"
7112 /* 1628 */ "ATOMIC_LOAD_UMIN_I16\000"
7113 /* 1649 */ "ATOMIC_LOAD_MIN_I16\000"
7114 /* 1669 */ "ATOMIC_SWAP_I16\000"
7115 /* 1685 */ "ATOMIC_CMP_SWAP_I16\000"
7116 /* 1705 */ "ATOMIC_LOAD_XOR_I16\000"
7117 /* 1725 */ "ATOMIC_LOAD_OR_I16\000"
7118 /* 1744 */ "ATOMIC_LOAD_UMAX_I16\000"
7119 /* 1765 */ "ATOMIC_LOAD_MAX_I16\000"
7120 /* 1785 */ "DMXXEXTFDMR256\000"
7121 /* 1800 */ "DMXXINSTDMR256\000"
7122 /* 1815 */ "NOP_GT_PWR6\000"
7123 /* 1827 */ "NOP_GT_PWR7\000"
7124 /* 1839 */ "ATOMIC_LOAD_SUB_I128\000"
7125 /* 1860 */ "ATOMIC_LOAD_ADD_I128\000"
7126 /* 1881 */ "ATOMIC_LOAD_NAND_I128\000"
7127 /* 1903 */ "ATOMIC_LOAD_AND_I128\000"
7128 /* 1924 */ "ATOMIC_SWAP_I128\000"
7129 /* 1941 */ "ATOMIC_CMP_SWAP_I128\000"
7130 /* 1962 */ "ATOMIC_LOAD_XOR_I128\000"
7131 /* 1983 */ "ATOMIC_LOAD_OR_I128\000"
7132 /* 2003 */ "TAILBA8\000"
7133 /* 2011 */ "PLHA8\000"
7134 /* 2017 */ "ADDIStocHA8\000"
7135 /* 2029 */ "BLA8\000"
7136 /* 2034 */ "PLA8\000"
7137 /* 2039 */ "PLWA8\000"
7138 /* 2045 */ "TAILB8\000"
7139 /* 2052 */ "CMPB8\000"
7140 /* 2058 */ "CMPRB8\000"
7141 /* 2065 */ "EXTSB8\000"
7142 /* 2072 */ "SETB8\000"
7143 /* 2078 */ "MFTB8\000"
7144 /* 2084 */ "POPCNTB8\000"
7145 /* 2093 */ "PSTB8\000"
7146 /* 2099 */ "SETNBC8\000"
7147 /* 2107 */ "SETBC8\000"
7148 /* 2114 */ "ADDC8\000"
7149 /* 2120 */ "ANDC8\000"
7150 /* 2126 */ "SUBFC8\000"
7151 /* 2133 */ "ADDIC8\000"
7152 /* 2140 */ "SUBFIC8\000"
7153 /* 2148 */ "DYNALLOC8\000"
7154 /* 2158 */ "ORC8\000"
7155 /* 2163 */ "CDTBCD8\000"
7156 /* 2171 */ "ADD8\000"
7157 /* 2176 */ "MADDLD8\000"
7158 /* 2184 */ "NAND8\000"
7159 /* 2190 */ "CBCDTD8\000"
7160 /* 2198 */ "CFENCE8\000"
7161 /* 2206 */ "ADDE8\000"
7162 /* 2212 */ "SUBFE8\000"
7163 /* 2219 */ "ADDME8\000"
7164 /* 2226 */ "SUBFME8\000"
7165 /* 2234 */ "ADDZE8\000"
7166 /* 2241 */ "SUBFZE8\000"
7167 /* 2249 */ "SUBF8\000"
7168 /* 2255 */ "MFOCRF8\000"
7169 /* 2263 */ "MTOCRF8\000"
7170 /* 2271 */ "MTCRF8\000"
7171 /* 2278 */ "SELECT_CC_F8\000"
7172 /* 2291 */ "SELECT_F8\000"
7173 /* 2301 */ "NEG8\000"
7174 /* 2306 */ "BRH8\000"
7175 /* 2311 */ "EXTSH8\000"
7176 /* 2318 */ "PSTH8\000"
7177 /* 2324 */ "PADDI8\000"
7178 /* 2331 */ "MULLI8\000"
7179 /* 2338 */ "PLI8\000"
7180 /* 2343 */ "RLWIMI8\000"
7181 /* 2351 */ "XORI8\000"
7182 /* 2357 */ "SRAWI8\000"
7183 /* 2364 */ "ATOMIC_LOAD_SUB_I8\000"
7184 /* 2383 */ "SELECT_CC_I8\000"
7185 /* 2396 */ "ATOMIC_LOAD_ADD_I8\000"
7186 /* 2415 */ "ATOMIC_LOAD_NAND_I8\000"
7187 /* 2435 */ "ATOMIC_LOAD_AND_I8\000"
7188 /* 2454 */ "ATOMIC_LOAD_UMIN_I8\000"
7189 /* 2474 */ "ATOMIC_LOAD_MIN_I8\000"
7190 /* 2493 */ "ATOMIC_SWAP_I8\000"
7191 /* 2508 */ "ATOMIC_CMP_SWAP_I8\000"
7192 /* 2527 */ "ATOMIC_LOAD_XOR_I8\000"
7193 /* 2546 */ "ATOMIC_LOAD_OR_I8\000"
7194 /* 2564 */ "SELECT_I8\000"
7195 /* 2574 */ "ATOMIC_LOAD_UMAX_I8\000"
7196 /* 2594 */ "ATOMIC_LOAD_MAX_I8\000"
7197 /* 2613 */ "HASHCHK8\000"
7198 /* 2622 */ "BL8\000"
7199 /* 2626 */ "ISEL8\000"
7200 /* 2632 */ "BCTRL8\000"
7201 /* 2639 */ "BCCTRL8\000"
7202 /* 2647 */ "BCCCTRL8\000"
7203 /* 2656 */ "ADDItocL8\000"
7204 /* 2666 */ "RLWINM8\000"
7205 /* 2674 */ "RLWNM8\000"
7206 /* 2681 */ "HASHCHKP8\000"
7207 /* 2691 */ "HASHSTP8\000"
7208 /* 2700 */ "SETNBCR8\000"
7209 /* 2709 */ "SETBCR8\000"
7210 /* 2717 */ "MFCR8\000"
7211 /* 2723 */ "PMXVI4GER8\000"
7212 /* 2734 */ "BLR8\000"
7213 /* 2739 */ "MFLR8\000"
7214 /* 2745 */ "MTLR8\000"
7215 /* 2751 */ "BDZLR8\000"
7216 /* 2758 */ "BDNZLR8\000"
7217 /* 2766 */ "MovePCtoLR8\000"
7218 /* 2778 */ "NOR8\000"
7219 /* 2783 */ "XOR8\000"
7220 /* 2788 */ "MFSPR8\000"
7221 /* 2795 */ "MTSPR8\000"
7222 /* 2802 */ "TAILBCTR8\000"
7223 /* 2812 */ "BCCTR8\000"
7224 /* 2819 */ "BCCCTR8\000"
7225 /* 2827 */ "MFCTR8\000"
7226 /* 2834 */ "MTCTR8\000"
7227 /* 2841 */ "ADDG6S8\000"
7228 /* 2849 */ "ADDIS8\000"
7229 /* 2856 */ "LIS8\000"
7230 /* 2861 */ "XORIS8\000"
7231 /* 2868 */ "DYNAREAOFFSET8\000"
7232 /* 2883 */ "ANDI_rec_1_EQ_BIT8\000"
7233 /* 2902 */ "ANDI_rec_1_GT_BIT8\000"
7234 /* 2921 */ "HASHST8\000"
7235 /* 2929 */ "LHAU8\000"
7236 /* 2935 */ "STBU8\000"
7237 /* 2941 */ "STHU8\000"
7238 /* 2947 */ "STWU8\000"
7239 /* 2953 */ "LBZU8\000"
7240 /* 2959 */ "LHZU8\000"
7241 /* 2965 */ "LWZU8\000"
7242 /* 2971 */ "EQV8\000"
7243 /* 2976 */ "SRAW8\000"
7244 /* 2982 */ "SLW8\000"
7245 /* 2987 */ "BRW8\000"
7246 /* 2992 */ "SRW8\000"
7247 /* 2997 */ "PSTW8\000"
7248 /* 3003 */ "CNTLZW8\000"
7249 /* 3011 */ "CNTTZW8\000"
7250 /* 3019 */ "LHAX8\000"
7251 /* 3025 */ "STBX8\000"
7252 /* 3031 */ "ADDEX8\000"
7253 /* 3038 */ "STHX8\000"
7254 /* 3044 */ "TLSGDAIX8\000"
7255 /* 3054 */ "TLSLDAIX8\000"
7256 /* 3064 */ "LHBRX8\000"
7257 /* 3071 */ "LWBRX8\000"
7258 /* 3078 */ "LHAUX8\000"
7259 /* 3085 */ "STBUX8\000"
7260 /* 3092 */ "STHUX8\000"
7261 /* 3099 */ "STWUX8\000"
7262 /* 3106 */ "LBZUX8\000"
7263 /* 3113 */ "LHZUX8\000"
7264 /* 3120 */ "LWZUX8\000"
7265 /* 3127 */ "STWX8\000"
7266 /* 3133 */ "LBZX8\000"
7267 /* 3139 */ "LHZX8\000"
7268 /* 3145 */ "LWZX8\000"
7269 /* 3151 */ "CP_COPY8\000"
7270 /* 3160 */ "PLBZ8\000"
7271 /* 3166 */ "BDZ8\000"
7272 /* 3171 */ "PLHZ8\000"
7273 /* 3177 */ "BDNZ8\000"
7274 /* 3183 */ "PLWZ8\000"
7275 /* 3189 */ "ADDItoc8\000"
7276 /* 3198 */ "TCRETURNai8\000"
7277 /* 3210 */ "TCRETURNdi8\000"
7278 /* 3222 */ "TCRETURNri8\000"
7279 /* 3234 */ "EVMHEGSMFAA\000"
7280 /* 3246 */ "EVMHOGSMFAA\000"
7281 /* 3258 */ "EVMWSMFAA\000"
7282 /* 3268 */ "EVMWSSFAA\000"
7283 /* 3278 */ "EVMHEGSMIAA\000"
7284 /* 3290 */ "EVMHOGSMIAA\000"
7285 /* 3302 */ "EVMWSMIAA\000"
7286 /* 3312 */ "EVMHEGUMIAA\000"
7287 /* 3324 */ "EVMHOGUMIAA\000"
7288 /* 3336 */ "EVMWUMIAA\000"
7289 /* 3346 */ "DCBA\000"
7290 /* 3351 */ "TAILBA\000"
7291 /* 3358 */ "LDtocBA\000"
7292 /* 3366 */ "gBCA\000"
7293 /* 3371 */ "BCCA\000"
7294 /* 3376 */ "EVMHESMFA\000"
7295 /* 3386 */ "EVMWHSMFA\000"
7296 /* 3396 */ "EVMHOSMFA\000"
7297 /* 3406 */ "EVMWSMFA\000"
7298 /* 3415 */ "EVMHESSFA\000"
7299 /* 3425 */ "EVMWHSSFA\000"
7300 /* 3435 */ "EVMHOSSFA\000"
7301 /* 3445 */ "EVMWSSFA\000"
7302 /* 3454 */ "PLHA\000"
7303 /* 3459 */ "ADDIStocHA\000"
7304 /* 3470 */ "ADDIStlsgdHA\000"
7305 /* 3483 */ "ADDIStlsldHA\000"
7306 /* 3496 */ "ADDISgotTprelHA\000"
7307 /* 3512 */ "ADDISdtprelHA\000"
7308 /* 3526 */ "SLBIA\000"
7309 /* 3532 */ "TLBIA\000"
7310 /* 3538 */ "EVMHESMIA\000"
7311 /* 3548 */ "EVMWHSMIA\000"
7312 /* 3558 */ "EVMHOSMIA\000"
7313 /* 3568 */ "EVMWSMIA\000"
7314 /* 3577 */ "EVMHEUMIA\000"
7315 /* 3587 */ "EVMWHUMIA\000"
7316 /* 3597 */ "EVMWLUMIA\000"
7317 /* 3607 */ "EVMHOUMIA\000"
7318 /* 3617 */ "EVMWUMIA\000"
7319 /* 3626 */ "BLA\000"
7320 /* 3630 */ "gBCLA\000"
7321 /* 3636 */ "BCCLA\000"
7322 /* 3642 */ "PLA\000"
7323 /* 3646 */ "BDZLA\000"
7324 /* 3652 */ "BDNZLA\000"
7325 /* 3659 */ "G_FMA\000"
7326 /* 3665 */ "G_STRICT_FMA\000"
7327 /* 3678 */ "EVMRA\000"
7328 /* 3684 */ "DQUA\000"
7329 /* 3689 */ "PLWA\000"
7330 /* 3694 */ "MTVSRWA\000"
7331 /* 3702 */ "MTVRWA\000"
7332 /* 3709 */ "BDZA\000"
7333 /* 3714 */ "BDNZA\000"
7334 /* 3720 */ "V_SET0B\000"
7335 /* 3728 */ "VSRAB\000"
7336 /* 3734 */ "RFEBB\000"
7337 /* 3740 */ "VCNTMBB\000"
7338 /* 3748 */ "XVTLSBB\000"
7339 /* 3756 */ "VCLZLSBB\000"
7340 /* 3765 */ "VCTZLSBB\000"
7341 /* 3774 */ "VCMPNEB\000"
7342 /* 3782 */ "VMRGHB\000"
7343 /* 3789 */ "XXSPLTIB\000"
7344 /* 3798 */ "VMRGLB\000"
7345 /* 3805 */ "TAILB\000"
7346 /* 3811 */ "VCLRLB\000"
7347 /* 3818 */ "VRLB\000"
7348 /* 3823 */ "VSLB\000"
7349 /* 3828 */ "VPMSUMB\000"
7350 /* 3836 */ "VGNB\000"
7351 /* 3841 */ "CMPB\000"
7352 /* 3846 */ "CMPEQB\000"
7353 /* 3853 */ "CLRBHRB\000"
7354 /* 3861 */ "CMPRB\000"
7355 /* 3867 */ "VCLRRB\000"
7356 /* 3874 */ "VSRB\000"
7357 /* 3879 */ "VMULESB\000"
7358 /* 3887 */ "V_SETALLONESB\000"
7359 /* 3901 */ "VAVGSB\000"
7360 /* 3908 */ "VUPKHSB\000"
7361 /* 3916 */ "VSPLTISB\000"
7362 /* 3925 */ "VUPKLSB\000"
7363 /* 3933 */ "VMINSB\000"
7364 /* 3940 */ "VMULOSB\000"
7365 /* 3948 */ "VCMPGTSB\000"
7366 /* 3957 */ "EVEXTSB\000"
7367 /* 3965 */ "VMAXSB\000"
7368 /* 3972 */ "SETB\000"
7369 /* 3977 */ "MFTB\000"
7370 /* 3982 */ "VSPLTB\000"
7371 /* 3989 */ "VPOPCNTB\000"
7372 /* 3998 */ "VINSERTB\000"
7373 /* 4007 */ "PSTB\000"
7374 /* 4012 */ "ReadTB\000"
7375 /* 4019 */ "VABSDUB\000"
7376 /* 4027 */ "VMULEUB\000"
7377 /* 4035 */ "VAVGUB\000"
7378 /* 4042 */ "VMINUB\000"
7379 /* 4049 */ "VMULOUB\000"
7380 /* 4057 */ "VCMPEQUB\000"
7381 /* 4066 */ "EFDSUB\000"
7382 /* 4073 */ "G_FSUB\000"
7383 /* 4080 */ "G_STRICT_FSUB\000"
7384 /* 4094 */ "G_ATOMICRMW_FSUB\000"
7385 /* 4111 */ "FMSUB\000"
7386 /* 4117 */ "FNMSUB\000"
7387 /* 4124 */ "EFSSUB\000"
7388 /* 4131 */ "EVFSSUB\000"
7389 /* 4139 */ "G_SUB\000"
7390 /* 4145 */ "G_ATOMICRMW_SUB\000"
7391 /* 4161 */ "VEXTRACTUB\000"
7392 /* 4172 */ "VCMPGTUB\000"
7393 /* 4181 */ "VMAXUB\000"
7394 /* 4188 */ "XXBLENDVB\000"
7395 /* 4198 */ "VCMPNEZB\000"
7396 /* 4207 */ "VCLZB\000"
7397 /* 4213 */ "VCTZB\000"
7398 /* 4219 */ "SETNBC\000"
7399 /* 4226 */ "SETBC\000"
7400 /* 4232 */ "gBC\000"
7401 /* 4236 */ "XXMFACC\000"
7402 /* 4244 */ "XXMTACC\000"
7403 /* 4252 */ "BUILD_UACC\000"
7404 /* 4263 */ "RESTORE_UACC\000"
7405 /* 4276 */ "SPILL_UACC\000"
7406 /* 4287 */ "RESTORE_WACC\000"
7407 /* 4300 */ "SPILL_WACC\000"
7408 /* 4311 */ "RESTORE_ACC\000"
7409 /* 4323 */ "SPILL_ACC\000"
7410 /* 4333 */ "BCC\000"
7411 /* 4337 */ "ADDC\000"
7412 /* 4342 */ "XXLANDC\000"
7413 /* 4350 */ "CRANDC\000"
7414 /* 4357 */ "EVANDC\000"
7415 /* 4364 */ "TABORTDC\000"
7416 /* 4373 */ "DTSTDC\000"
7417 /* 4380 */ "SUBFC\000"
7418 /* 4386 */ "SUBIC\000"
7419 /* 4392 */ "ADDIC\000"
7420 /* 4398 */ "RLDIC\000"
7421 /* 4404 */ "SUBFIC\000"
7422 /* 4411 */ "XSRDPIC\000"
7423 /* 4419 */ "XVRDPIC\000"
7424 /* 4427 */ "XVRSPIC\000"
7425 /* 4435 */ "G_INTRINSIC\000"
7426 /* 4447 */ "ICBLC\000"
7427 /* 4453 */ "BRINC\000"
7428 /* 4459 */ "G_FPTRUNC\000"
7429 /* 4469 */ "G_INTRINSIC_TRUNC\000"
7430 /* 4487 */ "G_TRUNC\000"
7431 /* 4495 */ "G_BUILD_VECTOR_TRUNC\000"
7432 /* 4516 */ "SLBSYNC\000"
7433 /* 4524 */ "TLBSYNC\000"
7434 /* 4532 */ "MSGSYNC\000"
7435 /* 4540 */ "ISYNC\000"
7436 /* 4546 */ "MSYNC\000"
7437 /* 4552 */ "G_DYN_STACKALLOC\000"
7438 /* 4569 */ "DYNALLOC\000"
7439 /* 4578 */ "BL8_NOTOC\000"
7440 /* 4588 */ "SELECT_CC_VSFRC\000"
7441 /* 4604 */ "SELECT_VSFRC\000"
7442 /* 4617 */ "XXLORC\000"
7443 /* 4624 */ "CRORC\000"
7444 /* 4630 */ "EVORC\000"
7445 /* 4636 */ "SELECT_CC_VRRC\000"
7446 /* 4651 */ "SELECT_VRRC\000"
7447 /* 4663 */ "SELECT_CC_VSSRC\000"
7448 /* 4679 */ "SELECT_VSSRC\000"
7449 /* 4692 */ "SELECT_CC_VSRC\000"
7450 /* 4707 */ "SELECT_VSRC\000"
7451 /* 4719 */ "SC\000"
7452 /* 4722 */ "TABORTWC\000"
7453 /* 4731 */ "VEXTSB2D\000"
7454 /* 4740 */ "VEXTSH2D\000"
7455 /* 4749 */ "VEXTSW2D\000"
7456 /* 4758 */ "TLBSX2D\000"
7457 /* 4766 */ "G_FMAD\000"
7458 /* 4773 */ "VSHASIGMAD\000"
7459 /* 4784 */ "G_INDEXED_SEXTLOAD\000"
7460 /* 4803 */ "G_SEXTLOAD\000"
7461 /* 4814 */ "G_INDEXED_ZEXTLOAD\000"
7462 /* 4833 */ "G_ZEXTLOAD\000"
7463 /* 4844 */ "G_INDEXED_LOAD\000"
7464 /* 4859 */ "G_LOAD\000"
7465 /* 4866 */ "DMXXSHAPAD\000"
7466 /* 4877 */ "VSRAD\000"
7467 /* 4883 */ "VGBBD\000"
7468 /* 4889 */ "VCNTMBD\000"
7469 /* 4897 */ "VPRTYBD\000"
7470 /* 4905 */ "DENBCD\000"
7471 /* 4912 */ "CDTBCD\000"
7472 /* 4919 */ "EFDADD\000"
7473 /* 4926 */ "G_VECREDUCE_FADD\000"
7474 /* 4943 */ "G_FADD\000"
7475 /* 4950 */ "G_VECREDUCE_SEQ_FADD\000"
7476 /* 4971 */ "G_STRICT_FADD\000"
7477 /* 4985 */ "G_ATOMICRMW_FADD\000"
7478 /* 5002 */ "FMADD\000"
7479 /* 5008 */ "FNMADD\000"
7480 /* 5015 */ "EFSADD\000"
7481 /* 5022 */ "EVFSADD\000"
7482 /* 5030 */ "G_VECREDUCE_ADD\000"
7483 /* 5046 */ "G_ADD\000"
7484 /* 5052 */ "G_PTR_ADD\000"
7485 /* 5062 */ "G_ATOMICRMW_ADD\000"
7486 /* 5078 */ "EVLDD\000"
7487 /* 5084 */ "MTVSRDD\000"
7488 /* 5092 */ "EVSTDD\000"
7489 /* 5099 */ "VCFUGED\000"
7490 /* 5107 */ "EFSCFD\000"
7491 /* 5114 */ "PLFD\000"
7492 /* 5119 */ "PSTFD\000"
7493 /* 5125 */ "FNEGD\000"
7494 /* 5131 */ "VNEGD\000"
7495 /* 5137 */ "MADDHD\000"
7496 /* 5144 */ "MULHD\000"
7497 /* 5150 */ "FCFID\000"
7498 /* 5156 */ "HRFID\000"
7499 /* 5162 */ "EFDCFSID\000"
7500 /* 5171 */ "FCTID\000"
7501 /* 5177 */ "EFDCFUID\000"
7502 /* 5186 */ "TLBLD\000"
7503 /* 5192 */ "MADDLD\000"
7504 /* 5199 */ "FSELD\000"
7505 /* 5205 */ "VMULLD\000"
7506 /* 5212 */ "CMPLD\000"
7507 /* 5218 */ "MFVSRLD\000"
7508 /* 5226 */ "VRLD\000"
7509 /* 5231 */ "VSLD\000"
7510 /* 5236 */ "SPILLTOVSR_LD\000"
7511 /* 5250 */ "FRIMD\000"
7512 /* 5256 */ "VBPERMD\000"
7513 /* 5264 */ "VPMSUMD\000"
7514 /* 5272 */ "XXLAND\000"
7515 /* 5279 */ "XXLNAND\000"
7516 /* 5287 */ "CRNAND\000"
7517 /* 5294 */ "EVNAND\000"
7518 /* 5301 */ "G_ATOMICRMW_NAND\000"
7519 /* 5318 */ "CRAND\000"
7520 /* 5324 */ "EVAND\000"
7521 /* 5330 */ "G_VECREDUCE_AND\000"
7522 /* 5346 */ "G_AND\000"
7523 /* 5352 */ "G_ATOMICRMW_AND\000"
7524 /* 5368 */ "TEND\000"
7525 /* 5373 */ "LIFETIME_END\000"
7526 /* 5386 */ "FCPSGND\000"
7527 /* 5394 */ "FRIND\000"
7528 /* 5400 */ "G_BRCOND\000"
7529 /* 5409 */ "G_ATOMICRMW_USUB_COND\000"
7530 /* 5431 */ "DRRND\000"
7531 /* 5437 */ "SETRND\000"
7532 /* 5444 */ "G_LLROUND\000"
7533 /* 5454 */ "G_LROUND\000"
7534 /* 5463 */ "G_INTRINSIC_ROUND\000"
7535 /* 5481 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
7536 /* 5507 */ "FCMPOD\000"
7537 /* 5514 */ "DDEDPD\000"
7538 /* 5521 */ "VPDEPD\000"
7539 /* 5528 */ "FRIPD\000"
7540 /* 5534 */ "CMPD\000"
7541 /* 5539 */ "LOAD_STACK_GUARD\000"
7542 /* 5556 */ "XXBRD\000"
7543 /* 5562 */ "BUILD_QUADWORD\000"
7544 /* 5577 */ "RESTORE_QUADWORD\000"
7545 /* 5594 */ "SPILL_QUADWORD\000"
7546 /* 5609 */ "SPLIT_QUADWORD\000"
7547 /* 5624 */ "MTMSRD\000"
7548 /* 5631 */ "MFVSRD\000"
7549 /* 5638 */ "MTVSRD\000"
7550 /* 5645 */ "MFVRD\000"
7551 /* 5651 */ "MTVRD\000"
7552 /* 5657 */ "FABSD\000"
7553 /* 5663 */ "FNABSD\000"
7554 /* 5670 */ "VMODSD\000"
7555 /* 5677 */ "VMULESD\000"
7556 /* 5685 */ "VDIVESD\000"
7557 /* 5693 */ "VMULHSD\000"
7558 /* 5701 */ "VMINSD\000"
7559 /* 5708 */ "VINSD\000"
7560 /* 5714 */ "VMULOSD\000"
7561 /* 5722 */ "VCMPGTSD\000"
7562 /* 5731 */ "VDIVSD\000"
7563 /* 5738 */ "VMAXSD\000"
7564 /* 5745 */ "PLXSD\000"
7565 /* 5751 */ "PSTXSD\000"
7566 /* 5758 */ "VEXTRACTD\000"
7567 /* 5768 */ "CBCDTD\000"
7568 /* 5775 */ "VPOPCNTD\000"
7569 /* 5784 */ "VINSERTD\000"
7570 /* 5793 */ "PSTD\000"
7571 /* 5798 */ "VPEXTD\000"
7572 /* 5805 */ "VMSUMCUD\000"
7573 /* 5814 */ "VMODUD\000"
7574 /* 5821 */ "VMULEUD\000"
7575 /* 5829 */ "VDIVEUD\000"
7576 /* 5837 */ "VMULHUD\000"
7577 /* 5845 */ "VMINUD\000"
7578 /* 5852 */ "VMULOUD\000"
7579 /* 5860 */ "FCMPUD\000"
7580 /* 5867 */ "VCMPEQUD\000"
7581 /* 5876 */ "VCMPGTUD\000"
7582 /* 5885 */ "VDIVUD\000"
7583 /* 5892 */ "VMAXUD\000"
7584 /* 5899 */ "XXBLENDVD\000"
7585 /* 5909 */ "DIVD\000"
7586 /* 5914 */ "FRIZD\000"
7587 /* 5920 */ "VCLZD\000"
7588 /* 5926 */ "CNTLZD\000"
7589 /* 5933 */ "VCTZD\000"
7590 /* 5939 */ "CNTTZD\000"
7591 /* 5946 */ "PSEUDO_PROBE\000"
7592 /* 5959 */ "MFBHRBE\000"
7593 /* 5967 */ "G_SSUBE\000"
7594 /* 5975 */ "G_USUBE\000"
7595 /* 5983 */ "CFENCE\000"
7596 /* 5990 */ "G_FENCE\000"
7597 /* 5998 */ "ARITH_FENCE\000"
7598 /* 6010 */ "REG_SEQUENCE\000"
7599 /* 6023 */ "MFFSCE\000"
7600 /* 6030 */ "G_SADDE\000"
7601 /* 6038 */ "G_UADDE\000"
7602 /* 6046 */ "G_GET_FPMODE\000"
7603 /* 6059 */ "G_RESET_FPMODE\000"
7604 /* 6074 */ "G_SET_FPMODE\000"
7605 /* 6087 */ "DIVDE\000"
7606 /* 6093 */ "G_FMINNUM_IEEE\000"
7607 /* 6108 */ "G_FMAXNUM_IEEE\000"
7608 /* 6123 */ "SLBMFEE\000"
7609 /* 6131 */ "WRTEE\000"
7610 /* 6137 */ "SUBFE\000"
7611 /* 6143 */ "EVLWHE\000"
7612 /* 6150 */ "EVSTWHE\000"
7613 /* 6158 */ "SLBIE\000"
7614 /* 6164 */ "TLBIE\000"
7615 /* 6170 */ "G_VSCALE\000"
7616 /* 6179 */ "G_JUMP_TABLE\000"
7617 /* 6192 */ "BUNDLE\000"
7618 /* 6199 */ "ADDME\000"
7619 /* 6205 */ "SUBFME\000"
7620 /* 6212 */ "G_MEMCPY_INLINE\000"
7621 /* 6228 */ "LOCAL_ESCAPE\000"
7622 /* 6241 */ "SELECT_CC_SPE\000"
7623 /* 6255 */ "SELECT_SPE\000"
7624 /* 6266 */ "TLBRE\000"
7625 /* 6272 */ "FRE\000"
7626 /* 6276 */ "G_STACKRESTORE\000"
7627 /* 6291 */ "G_INDEXED_STORE\000"
7628 /* 6307 */ "G_STORE\000"
7629 /* 6315 */ "G_BITREVERSE\000"
7630 /* 6328 */ "FAKE_USE\000"
7631 /* 6337 */ "SLBMTE\000"
7632 /* 6344 */ "FRSQRTE\000"
7633 /* 6352 */ "DBG_VALUE\000"
7634 /* 6362 */ "G_GLOBAL_VALUE\000"
7635 /* 6377 */ "G_PTRAUTH_GLOBAL_VALUE\000"
7636 /* 6400 */ "CONVERGENCECTRL_GLUE\000"
7637 /* 6421 */ "G_STACKSAVE\000"
7638 /* 6433 */ "MFVRSAVE\000"
7639 /* 6442 */ "MTVRSAVE\000"
7640 /* 6451 */ "G_MEMMOVE\000"
7641 /* 6461 */ "TLBWE\000"
7642 /* 6467 */ "DIVWE\000"
7643 /* 6473 */ "EVSTWWE\000"
7644 /* 6481 */ "ADDZE\000"
7645 /* 6487 */ "G_FREEZE\000"
7646 /* 6496 */ "SUBFZE\000"
7647 /* 6503 */ "G_FCANONICALIZE\000"
7648 /* 6519 */ "DCBF\000"
7649 /* 6524 */ "SUBF\000"
7650 /* 6529 */ "G_CTLZ_ZERO_UNDEF\000"
7651 /* 6547 */ "G_CTTZ_ZERO_UNDEF\000"
7652 /* 6565 */ "INIT_UNDEF\000"
7653 /* 6576 */ "G_IMPLICIT_DEF\000"
7654 /* 6591 */ "DBG_INSTR_REF\000"
7655 /* 6605 */ "EVMHESMF\000"
7656 /* 6614 */ "EVMWHSMF\000"
7657 /* 6623 */ "EVMHOSMF\000"
7658 /* 6632 */ "EVMWSMF\000"
7659 /* 6640 */ "MCRF\000"
7660 /* 6645 */ "MFOCRF\000"
7661 /* 6652 */ "MTOCRF\000"
7662 /* 6659 */ "MTCRF\000"
7663 /* 6665 */ "EFDCFSF\000"
7664 /* 6673 */ "EFSCFSF\000"
7665 /* 6681 */ "EVFSCFSF\000"
7666 /* 6690 */ "MTFSF\000"
7667 /* 6696 */ "EVMHESSF\000"
7668 /* 6705 */ "EVMWHSSF\000"
7669 /* 6714 */ "EVMHOSSF\000"
7670 /* 6723 */ "EVMWSSF\000"
7671 /* 6731 */ "EFDCTSF\000"
7672 /* 6739 */ "EFSCTSF\000"
7673 /* 6747 */ "EVFSCTSF\000"
7674 /* 6756 */ "DTSTSF\000"
7675 /* 6763 */ "EFDCFUF\000"
7676 /* 6771 */ "EFSCFUF\000"
7677 /* 6779 */ "EVFSCFUF\000"
7678 /* 6788 */ "EFDCTUF\000"
7679 /* 6796 */ "EFSCTUF\000"
7680 /* 6804 */ "EVFSCTUF\000"
7681 /* 6813 */ "DTSTDG\000"
7682 /* 6820 */ "SLBIEG\000"
7683 /* 6827 */ "EFDNEG\000"
7684 /* 6834 */ "G_FNEG\000"
7685 /* 6841 */ "EFSNEG\000"
7686 /* 6848 */ "EVFSNEG\000"
7687 /* 6856 */ "EVNEG\000"
7688 /* 6862 */ "EXTRACT_SUBREG\000"
7689 /* 6877 */ "INSERT_SUBREG\000"
7690 /* 6891 */ "G_SEXT_INREG\000"
7691 /* 6904 */ "SUBREG_TO_REG\000"
7692 /* 6918 */ "G_ATOMIC_CMPXCHG\000"
7693 /* 6935 */ "G_ATOMICRMW_XCHG\000"
7694 /* 6952 */ "G_FLOG\000"
7695 /* 6959 */ "G_VAARG\000"
7696 /* 6967 */ "PREALLOCATED_ARG\000"
7697 /* 6984 */ "V_SET0H\000"
7698 /* 6992 */ "VSRAH\000"
7699 /* 6998 */ "VCNTMBH\000"
7700 /* 7006 */ "G_PREFETCH\000"
7701 /* 7017 */ "EVLDH\000"
7702 /* 7023 */ "EVSTDH\000"
7703 /* 7030 */ "VCMPNEH\000"
7704 /* 7038 */ "VMRGHH\000"
7705 /* 7045 */ "VMRGLH\000"
7706 /* 7052 */ "VRLH\000"
7707 /* 7057 */ "VSLH\000"
7708 /* 7062 */ "G_SMULH\000"
7709 /* 7070 */ "G_UMULH\000"
7710 /* 7078 */ "VPMSUMH\000"
7711 /* 7086 */ "G_FTANH\000"
7712 /* 7094 */ "G_FSINH\000"
7713 /* 7102 */ "XXBRH\000"
7714 /* 7108 */ "VSRH\000"
7715 /* 7113 */ "DMSHA2HASH\000"
7716 /* 7124 */ "DMSHA3HASH\000"
7717 /* 7135 */ "VMULESH\000"
7718 /* 7143 */ "V_SETALLONESH\000"
7719 /* 7157 */ "VAVGSH\000"
7720 /* 7164 */ "VUPKHSH\000"
7721 /* 7172 */ "VSPLTISH\000"
7722 /* 7181 */ "VUPKLSH\000"
7723 /* 7189 */ "VMINSH\000"
7724 /* 7196 */ "G_FCOSH\000"
7725 /* 7204 */ "VMULOSH\000"
7726 /* 7212 */ "VCMPGTSH\000"
7727 /* 7221 */ "EVEXTSH\000"
7728 /* 7229 */ "VMAXSH\000"
7729 /* 7236 */ "VSPLTH\000"
7730 /* 7243 */ "VPOPCNTH\000"
7731 /* 7252 */ "VINSERTH\000"
7732 /* 7261 */ "PSTH\000"
7733 /* 7266 */ "VABSDUH\000"
7734 /* 7274 */ "VMULEUH\000"
7735 /* 7282 */ "VAVGUH\000"
7736 /* 7289 */ "VMINUH\000"
7737 /* 7296 */ "VMULOUH\000"
7738 /* 7304 */ "VCMPEQUH\000"
7739 /* 7313 */ "VEXTRACTUH\000"
7740 /* 7324 */ "VCMPGTUH\000"
7741 /* 7333 */ "VMAXUH\000"
7742 /* 7340 */ "XXBLENDVH\000"
7743 /* 7350 */ "VCMPNEZH\000"
7744 /* 7359 */ "VCLZH\000"
7745 /* 7365 */ "VCTZH\000"
7746 /* 7371 */ "DQUAI\000"
7747 /* 7377 */ "DCBI\000"
7748 /* 7382 */ "ICBI\000"
7749 /* 7387 */ "VSLDBI\000"
7750 /* 7394 */ "VSRDBI\000"
7751 /* 7401 */ "PSUBI\000"
7752 /* 7407 */ "DCCCI\000"
7753 /* 7413 */ "ICCCI\000"
7754 /* 7419 */ "TABORTDCI\000"
7755 /* 7429 */ "RFCI\000"
7756 /* 7434 */ "RFMCI\000"
7757 /* 7440 */ "TABORTWCI\000"
7758 /* 7450 */ "SRADI\000"
7759 /* 7456 */ "PADDI\000"
7760 /* 7462 */ "RFDI\000"
7761 /* 7467 */ "CMPLDI\000"
7762 /* 7474 */ "CLRLSLDI\000"
7763 /* 7483 */ "EXTLDI\000"
7764 /* 7490 */ "XXPERMDI\000"
7765 /* 7499 */ "CMPDI\000"
7766 /* 7505 */ "CLRRDI\000"
7767 /* 7512 */ "INSRDI\000"
7768 /* 7519 */ "ROTRDI\000"
7769 /* 7526 */ "EXTRDI\000"
7770 /* 7533 */ "TDI\000"
7771 /* 7537 */ "WRTEEI\000"
7772 /* 7544 */ "RFI\000"
7773 /* 7548 */ "MTFSFI\000"
7774 /* 7555 */ "DTSTSFI\000"
7775 /* 7563 */ "EVSPLATFI\000"
7776 /* 7573 */ "EVMERGEHI\000"
7777 /* 7583 */ "EVMERGELOHI\000"
7778 /* 7595 */ "DBG_PHI\000"
7779 /* 7603 */ "DMXXEXTFDMR512_HI\000"
7780 /* 7621 */ "DMXXINSTDMR512_HI\000"
7781 /* 7639 */ "TLBLI\000"
7782 /* 7645 */ "DSCLI\000"
7783 /* 7651 */ "MULLI\000"
7784 /* 7657 */ "PLI\000"
7785 /* 7661 */ "EXTSWSLI\000"
7786 /* 7670 */ "MTVSRBMI\000"
7787 /* 7679 */ "VRLDMI\000"
7788 /* 7686 */ "RLDIMI\000"
7789 /* 7693 */ "RLWIMI\000"
7790 /* 7700 */ "VRLQMI\000"
7791 /* 7707 */ "EVMHESMI\000"
7792 /* 7716 */ "EVMWHSMI\000"
7793 /* 7725 */ "EVMHOSMI\000"
7794 /* 7734 */ "EVMWSMI\000"
7795 /* 7742 */ "EVMHEUMI\000"
7796 /* 7751 */ "EVMWHUMI\000"
7797 /* 7760 */ "EVMWLUMI\000"
7798 /* 7769 */ "EVMHOUMI\000"
7799 /* 7778 */ "EVMWUMI\000"
7800 /* 7786 */ "VRLWMI\000"
7801 /* 7793 */ "MFFSCRNI\000"
7802 /* 7802 */ "MFFSCDRNI\000"
7803 /* 7812 */ "VSLDOI\000"
7804 /* 7819 */ "XSRDPI\000"
7805 /* 7826 */ "XVRDPI\000"
7806 /* 7833 */ "XSRQPI\000"
7807 /* 7840 */ "XVRSPI\000"
7808 /* 7847 */ "DSCRI\000"
7809 /* 7853 */ "XORI\000"
7810 /* 7858 */ "EFDCFSI\000"
7811 /* 7866 */ "EFSCFSI\000"
7812 /* 7874 */ "EVFSCFSI\000"
7813 /* 7883 */ "G_FPTOSI\000"
7814 /* 7892 */ "EFDCTSI\000"
7815 /* 7900 */ "EFSCTSI\000"
7816 /* 7908 */ "EVFSCTSI\000"
7817 /* 7917 */ "EVSPLATI\000"
7818 /* 7926 */ "LDtocJTI\000"
7819 /* 7935 */ "EFDCFUI\000"
7820 /* 7943 */ "EFSCFUI\000"
7821 /* 7951 */ "EVFSCFUI\000"
7822 /* 7960 */ "G_FPTOUI\000"
7823 /* 7969 */ "EFDCTUI\000"
7824 /* 7977 */ "EFSCTUI\000"
7825 /* 7985 */ "EVFSCTUI\000"
7826 /* 7994 */ "SRAWI\000"
7827 /* 8000 */ "XXSLDWI\000"
7828 /* 8008 */ "CMPLWI\000"
7829 /* 8015 */ "EVRLWI\000"
7830 /* 8022 */ "CLRLSLWI\000"
7831 /* 8031 */ "INSLWI\000"
7832 /* 8038 */ "EVSLWI\000"
7833 /* 8045 */ "EXTLWI\000"
7834 /* 8052 */ "G_FPOWI\000"
7835 /* 8060 */ "CMPWI\000"
7836 /* 8066 */ "CLRRWI\000"
7837 /* 8073 */ "INSRWI\000"
7838 /* 8080 */ "ROTRWI\000"
7839 /* 8087 */ "EXTRWI\000"
7840 /* 8094 */ "LSWI\000"
7841 /* 8099 */ "STSWI\000"
7842 /* 8105 */ "TWI\000"
7843 /* 8109 */ "TCHECK\000"
7844 /* 8116 */ "HASHCHK\000"
7845 /* 8124 */ "G_PTRMASK\000"
7846 /* 8134 */ "XXEVAL\000"
7847 /* 8141 */ "VSTRIBL\000"
7848 /* 8149 */ "gBCL\000"
7849 /* 8154 */ "BCCL\000"
7850 /* 8159 */ "RLDCL\000"
7851 /* 8165 */ "RLDICL\000"
7852 /* 8172 */ "GC_LABEL\000"
7853 /* 8181 */ "DBG_LABEL\000"
7854 /* 8191 */ "EH_LABEL\000"
7855 /* 8200 */ "ANNOTATION_LABEL\000"
7856 /* 8217 */ "TLBIEL\000"
7857 /* 8224 */ "ICALL_BRANCH_FUNNEL\000"
7858 /* 8244 */ "GETtlsldADDRPCREL\000"
7859 /* 8262 */ "GETtlsADDRPCREL\000"
7860 /* 8278 */ "ISEL\000"
7861 /* 8283 */ "EVSEL\000"
7862 /* 8289 */ "XXSEL\000"
7863 /* 8295 */ "DCBFL\000"
7864 /* 8301 */ "VSTRIHL\000"
7865 /* 8309 */ "G_FSHL\000"
7866 /* 8316 */ "G_SHL\000"
7867 /* 8322 */ "G_FCEIL\000"
7868 /* 8330 */ "PATCHABLE_TAIL_CALL\000"
7869 /* 8350 */ "PATCHABLE_TYPED_EVENT_CALL\000"
7870 /* 8377 */ "PATCHABLE_EVENT_CALL\000"
7871 /* 8398 */ "FENTRY_CALL\000"
7872 /* 8410 */ "DSSALL\000"
7873 /* 8417 */ "KILL\000"
7874 /* 8422 */ "LXVPRLL\000"
7875 /* 8430 */ "STXVPRLL\000"
7876 /* 8439 */ "LXVRLL\000"
7877 /* 8446 */ "STXVRLL\000"
7878 /* 8454 */ "LXVLL\000"
7879 /* 8460 */ "STXVLL\000"
7880 /* 8467 */ "G_CONSTANT_POOL\000"
7881 /* 8483 */ "BLRL\000"
7882 /* 8488 */ "gBCLRL\000"
7883 /* 8495 */ "BCCLRL\000"
7884 /* 8502 */ "BDZLRL\000"
7885 /* 8509 */ "BDNZLRL\000"
7886 /* 8517 */ "LXVPRL\000"
7887 /* 8524 */ "STXVPRL\000"
7888 /* 8532 */ "BCTRL\000"
7889 /* 8538 */ "gBCCTRL\000"
7890 /* 8546 */ "BCCCTRL\000"
7891 /* 8554 */ "LXVRL\000"
7892 /* 8560 */ "STXVRL\000"
7893 /* 8567 */ "MFFSL\000"
7894 /* 8573 */ "LVSL\000"
7895 /* 8578 */ "G_ROTL\000"
7896 /* 8585 */ "EFDMUL\000"
7897 /* 8592 */ "G_VECREDUCE_FMUL\000"
7898 /* 8609 */ "G_FMUL\000"
7899 /* 8616 */ "G_VECREDUCE_SEQ_FMUL\000"
7900 /* 8637 */ "G_STRICT_FMUL\000"
7901 /* 8651 */ "EFSMUL\000"
7902 /* 8658 */ "EVFSMUL\000"
7903 /* 8666 */ "G_VECREDUCE_MUL\000"
7904 /* 8682 */ "G_MUL\000"
7905 /* 8688 */ "LXVL\000"
7906 /* 8693 */ "STXVL\000"
7907 /* 8699 */ "LBARXL\000"
7908 /* 8706 */ "LDARXL\000"
7909 /* 8713 */ "LHARXL\000"
7910 /* 8720 */ "LQARXL\000"
7911 /* 8727 */ "LWARXL\000"
7912 /* 8734 */ "LVXL\000"
7913 /* 8739 */ "STVXL\000"
7914 /* 8745 */ "DCBZL\000"
7915 /* 8751 */ "BDZL\000"
7916 /* 8756 */ "BDNZL\000"
7917 /* 8762 */ "LDtocL\000"
7918 /* 8769 */ "ADDItocL\000"
7919 /* 8778 */ "LWZtocL\000"
7920 /* 8786 */ "ADDItlsgdL\000"
7921 /* 8797 */ "ADDItlsldL\000"
7922 /* 8808 */ "LDgotTprelL\000"
7923 /* 8820 */ "ADDIdtprelL\000"
7924 /* 8832 */ "VEXPANDBM\000"
7925 /* 8842 */ "VMSUMMBM\000"
7926 /* 8851 */ "MTVSRBM\000"
7927 /* 8859 */ "VEXTRACTBM\000"
7928 /* 8870 */ "VSUBUBM\000"
7929 /* 8878 */ "VADDUBM\000"
7930 /* 8886 */ "VMSUMUBM\000"
7931 /* 8895 */ "XXGENPCVBM\000"
7932 /* 8906 */ "VEXPANDDM\000"
7933 /* 8916 */ "MTVSRDM\000"
7934 /* 8924 */ "VEXTRACTDM\000"
7935 /* 8935 */ "VSUBUDM\000"
7936 /* 8943 */ "VADDUDM\000"
7937 /* 8951 */ "VMSUMUDM\000"
7938 /* 8960 */ "XXGENPCVDM\000"
7939 /* 8971 */ "VCLZDM\000"
7940 /* 8978 */ "CNTLZDM\000"
7941 /* 8986 */ "VCTZDM\000"
7942 /* 8993 */ "CNTTZDM\000"
7943 /* 9001 */ "G_FREM\000"
7944 /* 9008 */ "G_STRICT_FREM\000"
7945 /* 9022 */ "G_SREM\000"
7946 /* 9029 */ "G_UREM\000"
7947 /* 9036 */ "G_SDIVREM\000"
7948 /* 9046 */ "G_UDIVREM\000"
7949 /* 9056 */ "VEXPANDHM\000"
7950 /* 9066 */ "MTVSRHM\000"
7951 /* 9074 */ "VMSUMSHM\000"
7952 /* 9083 */ "VEXTRACTHM\000"
7953 /* 9094 */ "VSUBUHM\000"
7954 /* 9102 */ "VMLADDUHM\000"
7955 /* 9112 */ "VADDUHM\000"
7956 /* 9120 */ "VMSUMUHM\000"
7957 /* 9129 */ "XXGENPCVHM\000"
7958 /* 9140 */ "TRECLAIM\000"
7959 /* 9149 */ "VRFIM\000"
7960 /* 9155 */ "XSRDPIM\000"
7961 /* 9163 */ "XVRDPIM\000"
7962 /* 9171 */ "XVRSPIM\000"
7963 /* 9179 */ "SETFLM\000"
7964 /* 9186 */ "VRLDNM\000"
7965 /* 9193 */ "RLWINM\000"
7966 /* 9200 */ "VRLQNM\000"
7967 /* 9207 */ "VRLWNM\000"
7968 /* 9214 */ "VEXPANDQM\000"
7969 /* 9224 */ "MTVSRQM\000"
7970 /* 9232 */ "VEXTRACTQM\000"
7971 /* 9243 */ "VSUBUQM\000"
7972 /* 9251 */ "VADDUQM\000"
7973 /* 9259 */ "VSUBEUQM\000"
7974 /* 9268 */ "VADDEUQM\000"
7975 /* 9277 */ "VPERM\000"
7976 /* 9283 */ "XXPERM\000"
7977 /* 9290 */ "BLA8_RM\000"
7978 /* 9298 */ "BL8_RM\000"
7979 /* 9305 */ "BCTRL8_RM\000"
7980 /* 9315 */ "BLA_RM\000"
7981 /* 9322 */ "BL8_NOTOC_RM\000"
7982 /* 9335 */ "BL_RM\000"
7983 /* 9341 */ "BCTRL_RM\000"
7984 /* 9350 */ "BLA8_NOP_RM\000"
7985 /* 9362 */ "BL8_NOP_RM\000"
7986 /* 9373 */ "BL_NOP_RM\000"
7987 /* 9383 */ "BCTRL8_LDinto_toc_RM\000"
7988 /* 9404 */ "BCTRL_LWZinto_toc_RM\000"
7989 /* 9425 */ "INLINEASM\000"
7990 /* 9435 */ "VPKUDUM\000"
7991 /* 9443 */ "VPKUHUM\000"
7992 /* 9451 */ "G_VECREDUCE_FMINIMUM\000"
7993 /* 9472 */ "G_FMINIMUM\000"
7994 /* 9483 */ "G_ATOMICRMW_FMINIMUM\000"
7995 /* 9504 */ "G_VECREDUCE_FMAXIMUM\000"
7996 /* 9525 */ "G_FMAXIMUM\000"
7997 /* 9536 */ "G_ATOMICRMW_FMAXIMUM\000"
7998 /* 9557 */ "G_FMINIMUMNUM\000"
7999 /* 9571 */ "G_FMAXIMUMNUM\000"
8000 /* 9585 */ "G_FMINNUM\000"
8001 /* 9595 */ "G_FMAXNUM\000"
8002 /* 9605 */ "VPKUWUM\000"
8003 /* 9613 */ "VEXPANDWM\000"
8004 /* 9623 */ "MTVSRWM\000"
8005 /* 9631 */ "VEXTRACTWM\000"
8006 /* 9642 */ "VSUBUWM\000"
8007 /* 9650 */ "VADDUWM\000"
8008 /* 9658 */ "VMULUWM\000"
8009 /* 9666 */ "XXGENPCVWM\000"
8010 /* 9677 */ "EVMHEGSMFAN\000"
8011 /* 9689 */ "EVMHOGSMFAN\000"
8012 /* 9701 */ "EVMWSMFAN\000"
8013 /* 9711 */ "EVMWSSFAN\000"
8014 /* 9721 */ "EVMHEGSMIAN\000"
8015 /* 9733 */ "EVMHOGSMIAN\000"
8016 /* 9745 */ "EVMWSMIAN\000"
8017 /* 9755 */ "EVMHEGUMIAN\000"
8018 /* 9767 */ "EVMHOGUMIAN\000"
8019 /* 9779 */ "EVMWUMIAN\000"
8020 /* 9789 */ "G_FATAN\000"
8021 /* 9797 */ "G_FTAN\000"
8022 /* 9804 */ "G_INTRINSIC_ROUNDEVEN\000"
8023 /* 9826 */ "G_ASSERT_ALIGN\000"
8024 /* 9841 */ "G_FCOPYSIGN\000"
8025 /* 9853 */ "VRFIN\000"
8026 /* 9859 */ "TBEGIN\000"
8027 /* 9866 */ "G_VECREDUCE_FMIN\000"
8028 /* 9883 */ "G_ATOMICRMW_FMIN\000"
8029 /* 9900 */ "G_VECREDUCE_SMIN\000"
8030 /* 9917 */ "G_SMIN\000"
8031 /* 9924 */ "G_VECREDUCE_UMIN\000"
8032 /* 9941 */ "G_UMIN\000"
8033 /* 9948 */ "G_ATOMICRMW_UMIN\000"
8034 /* 9965 */ "G_ATOMICRMW_MIN\000"
8035 /* 9981 */ "MFSRIN\000"
8036 /* 9988 */ "MTSRIN\000"
8037 /* 9995 */ "G_FASIN\000"
8038 /* 10003 */ "G_FSIN\000"
8039 /* 10010 */ "PMXVBF16GER2NN\000"
8040 /* 10025 */ "PMXVF16GER2NN\000"
8041 /* 10039 */ "PMDMXVBF16GERX2NN\000"
8042 /* 10057 */ "PMDMXVF16GERX2NN\000"
8043 /* 10074 */ "PMXVF32GERNN\000"
8044 /* 10087 */ "PMXVF64GERNN\000"
8045 /* 10100 */ "PMXVBF16GER2WNN\000"
8046 /* 10116 */ "PMXVF16GER2WNN\000"
8047 /* 10131 */ "PMXVF32GERWNN\000"
8048 /* 10145 */ "PMXVF64GERWNN\000"
8049 /* 10159 */ "CFI_INSTRUCTION\000"
8050 /* 10175 */ "PMXVBF16GER2PN\000"
8051 /* 10190 */ "PMXVF16GER2PN\000"
8052 /* 10204 */ "PMDMXVBF16GERX2PN\000"
8053 /* 10222 */ "PMDMXVF16GERX2PN\000"
8054 /* 10239 */ "XSCVSPDPN\000"
8055 /* 10249 */ "PMXVF32GERPN\000"
8056 /* 10262 */ "PMXVF64GERPN\000"
8057 /* 10275 */ "XVCVBF16SPN\000"
8058 /* 10287 */ "XSCVDPSPN\000"
8059 /* 10297 */ "PMXVBF16GER2WPN\000"
8060 /* 10313 */ "PMXVF16GER2WPN\000"
8061 /* 10328 */ "PMXVF32GERWPN\000"
8062 /* 10342 */ "PMXVF64GERWPN\000"
8063 /* 10356 */ "DARN\000"
8064 /* 10361 */ "MFFSCRN\000"
8065 /* 10369 */ "MFFSCDRN\000"
8066 /* 10378 */ "DRINTN\000"
8067 /* 10385 */ "ATTN\000"
8068 /* 10390 */ "ADJCALLSTACKDOWN\000"
8069 /* 10407 */ "ADD4O\000"
8070 /* 10413 */ "ADDC8O\000"
8071 /* 10420 */ "SUBFC8O\000"
8072 /* 10428 */ "ADD8O\000"
8073 /* 10434 */ "ADDE8O\000"
8074 /* 10441 */ "SUBFE8O\000"
8075 /* 10449 */ "ADDME8O\000"
8076 /* 10457 */ "SUBFME8O\000"
8077 /* 10466 */ "ADDZE8O\000"
8078 /* 10474 */ "SUBFZE8O\000"
8079 /* 10483 */ "SUBF8O\000"
8080 /* 10490 */ "NEG8O\000"
8081 /* 10496 */ "G_SSUBO\000"
8082 /* 10504 */ "G_USUBO\000"
8083 /* 10512 */ "ADDCO\000"
8084 /* 10518 */ "SUBFCO\000"
8085 /* 10525 */ "G_SADDO\000"
8086 /* 10533 */ "G_UADDO\000"
8087 /* 10541 */ "MULLDO\000"
8088 /* 10548 */ "LQX_PSEUDO\000"
8089 /* 10559 */ "STQX_PSEUDO\000"
8090 /* 10571 */ "DIVDO\000"
8091 /* 10577 */ "ADDEO\000"
8092 /* 10583 */ "DIVDEO\000"
8093 /* 10590 */ "SUBFEO\000"
8094 /* 10597 */ "ADDMEO\000"
8095 /* 10604 */ "SUBFMEO\000"
8096 /* 10612 */ "DIVWEO\000"
8097 /* 10619 */ "ADDZEO\000"
8098 /* 10626 */ "SUBFZEO\000"
8099 /* 10634 */ "SUBFO\000"
8100 /* 10640 */ "JUMP_TABLE_DEBUG_INFO\000"
8101 /* 10662 */ "NEGO\000"
8102 /* 10667 */ "EVSTWHO\000"
8103 /* 10675 */ "PseudoEIEIO\000"
8104 /* 10687 */ "EnforceIEIO\000"
8105 /* 10699 */ "EVMERGELO\000"
8106 /* 10709 */ "EVMERGEHILO\000"
8107 /* 10721 */ "VSLO\000"
8108 /* 10726 */ "G_SMULO\000"
8109 /* 10734 */ "G_UMULO\000"
8110 /* 10742 */ "XSCVQPDPO\000"
8111 /* 10752 */ "DCMPO\000"
8112 /* 10758 */ "XSNMSUBQPO\000"
8113 /* 10769 */ "XSMSUBQPO\000"
8114 /* 10779 */ "XSSUBQPO\000"
8115 /* 10788 */ "XSNMADDQPO\000"
8116 /* 10799 */ "XSMADDQPO\000"
8117 /* 10809 */ "XSADDQPO\000"
8118 /* 10818 */ "XSMULQPO\000"
8119 /* 10827 */ "XSSQRTQPO\000"
8120 /* 10837 */ "XSDIVQPO\000"
8121 /* 10846 */ "G_BZERO\000"
8122 /* 10854 */ "VSRO\000"
8123 /* 10859 */ "DIVDUO\000"
8124 /* 10866 */ "DIVDEUO\000"
8125 /* 10874 */ "DIVWEUO\000"
8126 /* 10882 */ "DIVWUO\000"
8127 /* 10889 */ "MULLWO\000"
8128 /* 10896 */ "DIVWO\000"
8129 /* 10902 */ "EVSTWWO\000"
8130 /* 10910 */ "STACKMAP\000"
8131 /* 10919 */ "NAP\000"
8132 /* 10923 */ "G_DEBUGTRAP\000"
8133 /* 10935 */ "G_UBSANTRAP\000"
8134 /* 10947 */ "G_TRAP\000"
8135 /* 10954 */ "G_ATOMICRMW_UDEC_WRAP\000"
8136 /* 10976 */ "G_ATOMICRMW_UINC_WRAP\000"
8137 /* 10998 */ "G_BSWAP\000"
8138 /* 11006 */ "XSNMSUBADP\000"
8139 /* 11017 */ "XVNMSUBADP\000"
8140 /* 11028 */ "XSMSUBADP\000"
8141 /* 11038 */ "XVMSUBADP\000"
8142 /* 11048 */ "XSNMADDADP\000"
8143 /* 11059 */ "XVNMADDADP\000"
8144 /* 11070 */ "XSMADDADP\000"
8145 /* 11080 */ "XVMADDADP\000"
8146 /* 11090 */ "XSSUBDP\000"
8147 /* 11098 */ "XVSUBDP\000"
8148 /* 11106 */ "XSTSTDCDP\000"
8149 /* 11116 */ "XVTSTDCDP\000"
8150 /* 11126 */ "XSMINCDP\000"
8151 /* 11135 */ "XSMAXCDP\000"
8152 /* 11144 */ "XSADDDP\000"
8153 /* 11152 */ "XVADDDP\000"
8154 /* 11160 */ "XSCVSXDDP\000"
8155 /* 11170 */ "XVCVSXDDP\000"
8156 /* 11180 */ "XSCVUXDDP\000"
8157 /* 11190 */ "XVCVUXDDP\000"
8158 /* 11200 */ "XSCMPGEDP\000"
8159 /* 11210 */ "XVCMPGEDP\000"
8160 /* 11220 */ "XSREDP\000"
8161 /* 11227 */ "XVREDP\000"
8162 /* 11234 */ "XSRSQRTEDP\000"
8163 /* 11245 */ "XVRSQRTEDP\000"
8164 /* 11256 */ "XSNEGDP\000"
8165 /* 11264 */ "XVNEGDP\000"
8166 /* 11272 */ "XSXSIGDP\000"
8167 /* 11281 */ "XVXSIGDP\000"
8168 /* 11290 */ "XXSPLTIDP\000"
8169 /* 11300 */ "XSMINJDP\000"
8170 /* 11309 */ "XSMAXJDP\000"
8171 /* 11318 */ "XSMULDP\000"
8172 /* 11326 */ "XVMULDP\000"
8173 /* 11334 */ "XSNMSUBMDP\000"
8174 /* 11345 */ "XVNMSUBMDP\000"
8175 /* 11356 */ "XSMSUBMDP\000"
8176 /* 11366 */ "XVMSUBMDP\000"
8177 /* 11376 */ "XSNMADDMDP\000"
8178 /* 11387 */ "XVNMADDMDP\000"
8179 /* 11398 */ "XSMADDMDP\000"
8180 /* 11408 */ "XVMADDMDP\000"
8181 /* 11418 */ "XSCPSGNDP\000"
8182 /* 11428 */ "XVCPSGNDP\000"
8183 /* 11438 */ "XSMINDP\000"
8184 /* 11446 */ "XVMINDP\000"
8185 /* 11454 */ "XSCMPODP\000"
8186 /* 11463 */ "XSCVHPDP\000"
8187 /* 11472 */ "XSCVQPDP\000"
8188 /* 11481 */ "XSCVSPDP\000"
8189 /* 11490 */ "XVCVSPDP\000"
8190 /* 11499 */ "XSIEXPDP\000"
8191 /* 11508 */ "XVIEXPDP\000"
8192 /* 11517 */ "XSCMPEXPDP\000"
8193 /* 11528 */ "XSXEXPDP\000"
8194 /* 11537 */ "XVXEXPDP\000"
8195 /* 11546 */ "XSCMPEQDP\000"
8196 /* 11556 */ "XVCMPEQDP\000"
8197 /* 11566 */ "XSNABSDP\000"
8198 /* 11575 */ "XVNABSDP\000"
8199 /* 11584 */ "XSABSDP\000"
8200 /* 11592 */ "XVABSDP\000"
8201 /* 11600 */ "DCTDP\000"
8202 /* 11606 */ "XSCMPGTDP\000"
8203 /* 11616 */ "XVCMPGTDP\000"
8204 /* 11626 */ "XSSQRTDP\000"
8205 /* 11635 */ "XSTSQRTDP\000"
8206 /* 11645 */ "XVTSQRTDP\000"
8207 /* 11655 */ "XVSQRTDP\000"
8208 /* 11664 */ "XSCMPUDP\000"
8209 /* 11673 */ "XSDIVDP\000"
8210 /* 11681 */ "XSTDIVDP\000"
8211 /* 11690 */ "XVTDIVDP\000"
8212 /* 11699 */ "XVDIVDP\000"
8213 /* 11707 */ "XVCVSXWDP\000"
8214 /* 11717 */ "XVCVUXWDP\000"
8215 /* 11727 */ "XSMAXDP\000"
8216 /* 11735 */ "XVMAXDP\000"
8217 /* 11743 */ "CTRL_DEP\000"
8218 /* 11752 */ "DCBFEP\000"
8219 /* 11759 */ "ICBIEP\000"
8220 /* 11766 */ "DCBZLEP\000"
8221 /* 11774 */ "DCBTEP\000"
8222 /* 11781 */ "DCBSTEP\000"
8223 /* 11789 */ "DCBTSTEP\000"
8224 /* 11798 */ "DCBZEP\000"
8225 /* 11805 */ "VCMPBFP\000"
8226 /* 11813 */ "VNMSUBFP\000"
8227 /* 11822 */ "VSUBFP\000"
8228 /* 11829 */ "VMADDFP\000"
8229 /* 11837 */ "VADDFP\000"
8230 /* 11844 */ "VLOGEFP\000"
8231 /* 11852 */ "VCMPGEFP\000"
8232 /* 11861 */ "VREFP\000"
8233 /* 11867 */ "VEXPTEFP\000"
8234 /* 11876 */ "VRSQRTEFP\000"
8235 /* 11886 */ "VMINFP\000"
8236 /* 11893 */ "G_SITOFP\000"
8237 /* 11902 */ "G_UITOFP\000"
8238 /* 11911 */ "VCMPEQFP\000"
8239 /* 11920 */ "VCMPGTFP\000"
8240 /* 11929 */ "VMAXFP\000"
8241 /* 11936 */ "XSCVDPHP\000"
8242 /* 11945 */ "XVCVSPHP\000"
8243 /* 11954 */ "VRFIP\000"
8244 /* 11960 */ "XSRDPIP\000"
8245 /* 11968 */ "XVRDPIP\000"
8246 /* 11976 */ "XVRSPIP\000"
8247 /* 11984 */ "HASHCHKP\000"
8248 /* 11993 */ "DCBFLP\000"
8249 /* 12000 */ "G_FCMP\000"
8250 /* 12007 */ "G_ICMP\000"
8251 /* 12014 */ "G_SCMP\000"
8252 /* 12021 */ "G_UCMP\000"
8253 /* 12028 */ "PMXVBF16GER2NP\000"
8254 /* 12043 */ "PMXVF16GER2NP\000"
8255 /* 12057 */ "PMDMXVBF16GERX2NP\000"
8256 /* 12075 */ "PMDMXVF16GERX2NP\000"
8257 /* 12092 */ "PMXVF32GERNP\000"
8258 /* 12105 */ "PMXVF64GERNP\000"
8259 /* 12118 */ "PMXVBF16GER2WNP\000"
8260 /* 12134 */ "PMXVF16GER2WNP\000"
8261 /* 12149 */ "PMXVF32GERWNP\000"
8262 /* 12163 */ "PMXVF64GERWNP\000"
8263 /* 12177 */ "BLA8_NOP\000"
8264 /* 12186 */ "BL8_NOP\000"
8265 /* 12194 */ "UNENCODED_NOP\000"
8266 /* 12208 */ "BL_NOP\000"
8267 /* 12215 */ "CONVERGENCECTRL_LOOP\000"
8268 /* 12236 */ "G_CTPOP\000"
8269 /* 12244 */ "STOP\000"
8270 /* 12249 */ "PATCHABLE_OP\000"
8271 /* 12262 */ "FAULTING_OP\000"
8272 /* 12274 */ "PMXVBF16GER2PP\000"
8273 /* 12289 */ "PMXVF16GER2PP\000"
8274 /* 12303 */ "PMXVI16GER2PP\000"
8275 /* 12317 */ "PMDMXVBF16GERX2PP\000"
8276 /* 12335 */ "PMDMXVF16GERX2PP\000"
8277 /* 12352 */ "PMXVI8GER4PP\000"
8278 /* 12365 */ "PMDMXVI8GERX4PP\000"
8279 /* 12381 */ "PMXVI4GER8PP\000"
8280 /* 12394 */ "PMXVF32GERPP\000"
8281 /* 12407 */ "PMXVF64GERPP\000"
8282 /* 12420 */ "PMXVI16GER2SPP\000"
8283 /* 12435 */ "PMXVI8GER4SPP\000"
8284 /* 12449 */ "PMDMXVI8GERX4SPP\000"
8285 /* 12466 */ "PMXVI8GER4WSPP\000"
8286 /* 12481 */ "PMXVBF16GER2WPP\000"
8287 /* 12497 */ "PMXVF16GER2WPP\000"
8288 /* 12512 */ "PMXVI16GER2WPP\000"
8289 /* 12527 */ "PMXVI8GER4WPP\000"
8290 /* 12541 */ "PMXVI4GER8WPP\000"
8291 /* 12555 */ "PMXVF32GERWPP\000"
8292 /* 12569 */ "PMXVF64GERWPP\000"
8293 /* 12583 */ "PMXVI16GER2SWPP\000"
8294 /* 12599 */ "XSNMSUBQP\000"
8295 /* 12609 */ "XSMSUBQP\000"
8296 /* 12618 */ "XSSUBQP\000"
8297 /* 12626 */ "XSTSTDCQP\000"
8298 /* 12636 */ "XSMINCQP\000"
8299 /* 12645 */ "XSMAXCQP\000"
8300 /* 12654 */ "XSNMADDQP\000"
8301 /* 12664 */ "XSMADDQP\000"
8302 /* 12673 */ "XSADDQP\000"
8303 /* 12681 */ "XSCVSDQP\000"
8304 /* 12690 */ "XSCVUDQP\000"
8305 /* 12699 */ "XSCMPGEQP\000"
8306 /* 12709 */ "XSNEGQP\000"
8307 /* 12717 */ "XSXSIGQP\000"
8308 /* 12726 */ "XSMULQP\000"
8309 /* 12734 */ "XSCPSGNQP\000"
8310 /* 12744 */ "XSCMPOQP\000"
8311 /* 12753 */ "XSCVDPQP\000"
8312 /* 12762 */ "XSIEXPQP\000"
8313 /* 12771 */ "XSCMPEXPQP\000"
8314 /* 12782 */ "XSXEXPQP\000"
8315 /* 12791 */ "XSCMPEQQP\000"
8316 /* 12801 */ "XSCVSQQP\000"
8317 /* 12810 */ "XSCVUQQP\000"
8318 /* 12819 */ "XSNABSQP\000"
8319 /* 12828 */ "XSABSQP\000"
8320 /* 12836 */ "XSCMPGTQP\000"
8321 /* 12846 */ "XSSQRTQP\000"
8322 /* 12855 */ "XSCMPUQP\000"
8323 /* 12864 */ "XSDIVQP\000"
8324 /* 12872 */ "RESTORE_DMRP\000"
8325 /* 12885 */ "SPILL_DMRP\000"
8326 /* 12896 */ "XSNMSUBASP\000"
8327 /* 12907 */ "XVNMSUBASP\000"
8328 /* 12918 */ "XSMSUBASP\000"
8329 /* 12928 */ "XVMSUBASP\000"
8330 /* 12938 */ "XSNMADDASP\000"
8331 /* 12949 */ "XVNMADDASP\000"
8332 /* 12960 */ "XSMADDASP\000"
8333 /* 12970 */ "XVMADDASP\000"
8334 /* 12980 */ "XSSUBSP\000"
8335 /* 12988 */ "XVSUBSP\000"
8336 /* 12996 */ "XSTSTDCSP\000"
8337 /* 13006 */ "XVTSTDCSP\000"
8338 /* 13016 */ "XSADDSP\000"
8339 /* 13024 */ "XVADDSP\000"
8340 /* 13032 */ "XSCVSXDSP\000"
8341 /* 13042 */ "XVCVSXDSP\000"
8342 /* 13052 */ "XSCVUXDSP\000"
8343 /* 13062 */ "XVCVUXDSP\000"
8344 /* 13072 */ "XVCMPGESP\000"
8345 /* 13082 */ "XSRESP\000"
8346 /* 13089 */ "XVRESP\000"
8347 /* 13096 */ "XSRSQRTESP\000"
8348 /* 13107 */ "XVRSQRTESP\000"
8349 /* 13118 */ "XVNEGSP\000"
8350 /* 13126 */ "XVXSIGSP\000"
8351 /* 13135 */ "XSMULSP\000"
8352 /* 13143 */ "XVMULSP\000"
8353 /* 13151 */ "XSNMSUBMSP\000"
8354 /* 13162 */ "XVNMSUBMSP\000"
8355 /* 13173 */ "XSMSUBMSP\000"
8356 /* 13183 */ "XVMSUBMSP\000"
8357 /* 13193 */ "XSNMADDMSP\000"
8358 /* 13204 */ "XVNMADDMSP\000"
8359 /* 13215 */ "XSMADDMSP\000"
8360 /* 13225 */ "XVMADDMSP\000"
8361 /* 13235 */ "XVCPSGNSP\000"
8362 /* 13245 */ "XVMINSP\000"
8363 /* 13253 */ "XSCVDPSP\000"
8364 /* 13262 */ "XVCVDPSP\000"
8365 /* 13271 */ "XVCVHPSP\000"
8366 /* 13280 */ "XVIEXPSP\000"
8367 /* 13289 */ "XVXEXPSP\000"
8368 /* 13298 */ "XVCMPEQSP\000"
8369 /* 13308 */ "DRSP\000"
8370 /* 13313 */ "FRSP\000"
8371 /* 13318 */ "XSRSP\000"
8372 /* 13324 */ "XVNABSSP\000"
8373 /* 13333 */ "XVABSSP\000"
8374 /* 13341 */ "PLXSSP\000"
8375 /* 13348 */ "PSTXSSP\000"
8376 /* 13356 */ "XVCMPGTSP\000"
8377 /* 13366 */ "XSSQRTSP\000"
8378 /* 13375 */ "XVTSQRTSP\000"
8379 /* 13385 */ "XVSQRTSP\000"
8380 /* 13394 */ "XSDIVSP\000"
8381 /* 13402 */ "XVTDIVSP\000"
8382 /* 13411 */ "XVDIVSP\000"
8383 /* 13419 */ "XVCVSXWSP\000"
8384 /* 13429 */ "XVCVUXWSP\000"
8385 /* 13439 */ "XVMAXSP\000"
8386 /* 13447 */ "HASHSTP\000"
8387 /* 13455 */ "ADJCALLSTACKUP\000"
8388 /* 13470 */ "PREALLOCATED_SETUP\000"
8389 /* 13489 */ "PLXVP\000"
8390 /* 13495 */ "PSTXVP\000"
8391 /* 13502 */ "G_FLDEXP\000"
8392 /* 13511 */ "G_STRICT_FLDEXP\000"
8393 /* 13527 */ "G_FEXP\000"
8394 /* 13534 */ "G_FFREXP\000"
8395 /* 13543 */ "XSRQPXP\000"
8396 /* 13551 */ "VEXTSD2Q\000"
8397 /* 13560 */ "VSRAQ\000"
8398 /* 13566 */ "DQUAQ\000"
8399 /* 13572 */ "DSUBQ\000"
8400 /* 13578 */ "VPRTYBQ\000"
8401 /* 13586 */ "DTSTDCQ\000"
8402 /* 13594 */ "DENBCDQ\000"
8403 /* 13602 */ "DADDQ\000"
8404 /* 13608 */ "DRRNDQ\000"
8405 /* 13615 */ "DDEDPDQ\000"
8406 /* 13623 */ "EFDCMPEQ\000"
8407 /* 13632 */ "EFSCMPEQ\000"
8408 /* 13641 */ "EVFSCMPEQ\000"
8409 /* 13651 */ "EVCMPEQ\000"
8410 /* 13659 */ "EFDTSTEQ\000"
8411 /* 13668 */ "EFSTSTEQ\000"
8412 /* 13677 */ "EVFSTSTEQ\000"
8413 /* 13687 */ "DTSTSFQ\000"
8414 /* 13695 */ "DTSTDGQ\000"
8415 /* 13703 */ "DQUAIQ\000"
8416 /* 13710 */ "DTSTSFIQ\000"
8417 /* 13719 */ "DSCLIQ\000"
8418 /* 13726 */ "DSCRIQ\000"
8419 /* 13733 */ "LXVKQ\000"
8420 /* 13739 */ "ICBLQ\000"
8421 /* 13745 */ "VRLQ\000"
8422 /* 13750 */ "VSLQ\000"
8423 /* 13755 */ "DMULQ\000"
8424 /* 13761 */ "VBPERMQ\000"
8425 /* 13769 */ "DRINTNQ\000"
8426 /* 13777 */ "DCMPOQ\000"
8427 /* 13784 */ "DRDPQ\000"
8428 /* 13790 */ "DCTQPQ\000"
8429 /* 13797 */ "DCFFIXQQ\000"
8430 /* 13806 */ "DCTFIXQQ\000"
8431 /* 13815 */ "XXBRQ\000"
8432 /* 13821 */ "VSRQ\000"
8433 /* 13826 */ "VMODSQ\000"
8434 /* 13833 */ "VDIVESQ\000"
8435 /* 13841 */ "VCMPSQ\000"
8436 /* 13848 */ "VCMPGTSQ\000"
8437 /* 13857 */ "VDIVSQ\000"
8438 /* 13864 */ "STQ\000"
8439 /* 13868 */ "VMUL10UQ\000"
8440 /* 13877 */ "VMUL10CUQ\000"
8441 /* 13887 */ "VSUBCUQ\000"
8442 /* 13895 */ "VADDCUQ\000"
8443 /* 13903 */ "VMUL10ECUQ\000"
8444 /* 13914 */ "VSUBECUQ\000"
8445 /* 13923 */ "VADDECUQ\000"
8446 /* 13932 */ "VMODUQ\000"
8447 /* 13939 */ "VMUL10EUQ\000"
8448 /* 13949 */ "VDIVEUQ\000"
8449 /* 13957 */ "DCMPUQ\000"
8450 /* 13964 */ "VCMPUQ\000"
8451 /* 13971 */ "VCMPEQUQ\000"
8452 /* 13980 */ "VCMPGTUQ\000"
8453 /* 13989 */ "VDIVUQ\000"
8454 /* 13996 */ "DDIVQ\000"
8455 /* 14002 */ "DIEXQ\000"
8456 /* 14008 */ "DTSTEXQ\000"
8457 /* 14016 */ "DXEXQ\000"
8458 /* 14022 */ "DCFFIXQ\000"
8459 /* 14030 */ "DCTFIXQ\000"
8460 /* 14038 */ "DRINTXQ\000"
8461 /* 14046 */ "MBAR\000"
8462 /* 14051 */ "UpdateGBR\000"
8463 /* 14061 */ "VSTRIBR\000"
8464 /* 14069 */ "G_BR\000"
8465 /* 14074 */ "INLINEASM_BR\000"
8466 /* 14087 */ "SETNBCR\000"
8467 /* 14095 */ "SETBCR\000"
8468 /* 14102 */ "MFDCR\000"
8469 /* 14108 */ "RLDCR\000"
8470 /* 14114 */ "MTDCR\000"
8471 /* 14120 */ "MFCR\000"
8472 /* 14125 */ "RLDICR\000"
8473 /* 14132 */ "MFUDSCR\000"
8474 /* 14140 */ "MTUDSCR\000"
8475 /* 14148 */ "MFVSCR\000"
8476 /* 14155 */ "MTVSCR\000"
8477 /* 14162 */ "RESTORE_CR\000"
8478 /* 14173 */ "SPILL_CR\000"
8479 /* 14182 */ "ADDItlsgdLADDR\000"
8480 /* 14197 */ "ADDItlsldLADDR\000"
8481 /* 14212 */ "G_BLOCK_ADDR\000"
8482 /* 14225 */ "GETtlsldADDR\000"
8483 /* 14238 */ "GETtlsADDR\000"
8484 /* 14249 */ "PMXVF32GER\000"
8485 /* 14260 */ "PMXVF64GER\000"
8486 /* 14271 */ "VNCIPHER\000"
8487 /* 14280 */ "VCIPHER\000"
8488 /* 14288 */ "MEMBARRIER\000"
8489 /* 14299 */ "G_CONSTANT_FOLD_BARRIER\000"
8490 /* 14323 */ "PATCHABLE_FUNCTION_ENTER\000"
8491 /* 14348 */ "G_READCYCLECOUNTER\000"
8492 /* 14367 */ "G_READSTEADYCOUNTER\000"
8493 /* 14387 */ "G_READ_REGISTER\000"
8494 /* 14403 */ "G_WRITE_REGISTER\000"
8495 /* 14420 */ "VSTRIHR\000"
8496 /* 14428 */ "G_ASHR\000"
8497 /* 14435 */ "G_FSHR\000"
8498 /* 14442 */ "G_LSHR\000"
8499 /* 14449 */ "KILL_PAIR\000"
8500 /* 14459 */ "BLR\000"
8501 /* 14463 */ "gBCLR\000"
8502 /* 14469 */ "BCCLR\000"
8503 /* 14475 */ "MFLR\000"
8504 /* 14480 */ "MTLR\000"
8505 /* 14485 */ "BDZLR\000"
8506 /* 14491 */ "BDNZLR\000"
8507 /* 14498 */ "MovePCtoLR\000"
8508 /* 14509 */ "MoveGOTtoLR\000"
8509 /* 14521 */ "RESTORE_DMR\000"
8510 /* 14533 */ "SPILL_DMR\000"
8511 /* 14543 */ "FMR\000"
8512 /* 14547 */ "DMMR\000"
8513 /* 14552 */ "MFPMR\000"
8514 /* 14558 */ "MTPMR\000"
8515 /* 14564 */ "VPERMR\000"
8516 /* 14571 */ "XXPERMR\000"
8517 /* 14579 */ "CONVERGENCECTRL_ANCHOR\000"
8518 /* 14602 */ "XXLOR\000"
8519 /* 14608 */ "XXLNOR\000"
8520 /* 14615 */ "CRNOR\000"
8521 /* 14621 */ "EVNOR\000"
8522 /* 14627 */ "G_FFLOOR\000"
8523 /* 14636 */ "CROR\000"
8524 /* 14641 */ "G_EXTRACT_SUBVECTOR\000"
8525 /* 14661 */ "G_INSERT_SUBVECTOR\000"
8526 /* 14680 */ "G_BUILD_VECTOR\000"
8527 /* 14695 */ "G_SHUFFLE_VECTOR\000"
8528 /* 14712 */ "G_STEP_VECTOR\000"
8529 /* 14726 */ "G_SPLAT_VECTOR\000"
8530 /* 14741 */ "EVOR\000"
8531 /* 14746 */ "XXLXOR\000"
8532 /* 14753 */ "DMXOR\000"
8533 /* 14759 */ "VPERMXOR\000"
8534 /* 14768 */ "CRXOR\000"
8535 /* 14774 */ "EVXOR\000"
8536 /* 14780 */ "G_VECREDUCE_XOR\000"
8537 /* 14796 */ "G_XOR\000"
8538 /* 14802 */ "G_ATOMICRMW_XOR\000"
8539 /* 14818 */ "G_VECREDUCE_OR\000"
8540 /* 14833 */ "G_OR\000"
8541 /* 14838 */ "G_ATOMICRMW_OR\000"
8542 /* 14853 */ "MFSPR\000"
8543 /* 14859 */ "MTSPR\000"
8544 /* 14865 */ "MFSR\000"
8545 /* 14870 */ "MFMSR\000"
8546 /* 14876 */ "MTMSR\000"
8547 /* 14882 */ "MTSR\000"
8548 /* 14887 */ "LVSR\000"
8549 /* 14892 */ "TAILBCTR\000"
8550 /* 14901 */ "gBCCTR\000"
8551 /* 14908 */ "BCCCTR\000"
8552 /* 14915 */ "MFCTR\000"
8553 /* 14921 */ "MTCTR\000"
8554 /* 14927 */ "G_ROTR\000"
8555 /* 14934 */ "G_INTTOPTR\000"
8556 /* 14945 */ "PMXVI16GER2S\000"
8557 /* 14958 */ "ADDG6S\000"
8558 /* 14965 */ "EFDABS\000"
8559 /* 14972 */ "G_FABS\000"
8560 /* 14979 */ "EFDNABS\000"
8561 /* 14987 */ "EFSNABS\000"
8562 /* 14995 */ "EVFSNABS\000"
8563 /* 15004 */ "EFSABS\000"
8564 /* 15011 */ "EVFSABS\000"
8565 /* 15019 */ "EVABS\000"
8566 /* 15025 */ "G_ABS\000"
8567 /* 15031 */ "VSUM4SBS\000"
8568 /* 15040 */ "VSUBSBS\000"
8569 /* 15048 */ "VADDSBS\000"
8570 /* 15056 */ "VSUM4UBS\000"
8571 /* 15065 */ "VSUBUBS\000"
8572 /* 15073 */ "VADDUBS\000"
8573 /* 15081 */ "FSUBS\000"
8574 /* 15087 */ "FMSUBS\000"
8575 /* 15094 */ "FNMSUBS\000"
8576 /* 15102 */ "G_ABDS\000"
8577 /* 15109 */ "FADDS\000"
8578 /* 15115 */ "FMADDS\000"
8579 /* 15122 */ "FNMADDS\000"
8580 /* 15130 */ "FCFIDS\000"
8581 /* 15137 */ "DCBTDS\000"
8582 /* 15144 */ "DCBTSTDS\000"
8583 /* 15153 */ "XSCVDPSXDS\000"
8584 /* 15164 */ "XVCVDPSXDS\000"
8585 /* 15175 */ "XVCVSPSXDS\000"
8586 /* 15186 */ "XSCVDPUXDS\000"
8587 /* 15197 */ "XVCVDPUXDS\000"
8588 /* 15208 */ "XVCVSPUXDS\000"
8589 /* 15219 */ "V_SETALLONES\000"
8590 /* 15232 */ "FRES\000"
8591 /* 15237 */ "FRSQRTES\000"
8592 /* 15246 */ "G_UNMERGE_VALUES\000"
8593 /* 15263 */ "G_MERGE_VALUES\000"
8594 /* 15278 */ "EFDCFS\000"
8595 /* 15285 */ "MFFS\000"
8596 /* 15290 */ "PLFS\000"
8597 /* 15295 */ "MCRFS\000"
8598 /* 15301 */ "PSTFS\000"
8599 /* 15307 */ "FNEGS\000"
8600 /* 15313 */ "VSUM4SHS\000"
8601 /* 15322 */ "VSUBSHS\000"
8602 /* 15330 */ "VMHADDSHS\000"
8603 /* 15340 */ "VMHRADDSHS\000"
8604 /* 15351 */ "VADDSHS\000"
8605 /* 15359 */ "VMSUMSHS\000"
8606 /* 15368 */ "VSUBUHS\000"
8607 /* 15376 */ "VADDUHS\000"
8608 /* 15384 */ "VMSUMUHS\000"
8609 /* 15393 */ "SUBIS\000"
8610 /* 15399 */ "SUBPCIS\000"
8611 /* 15407 */ "ADDPCIS\000"
8612 /* 15415 */ "ADDIS\000"
8613 /* 15421 */ "LIS\000"
8614 /* 15425 */ "XORIS\000"
8615 /* 15431 */ "EVSRWIS\000"
8616 /* 15439 */ "FSELS\000"
8617 /* 15445 */ "ADD4TLS\000"
8618 /* 15453 */ "ADD8TLS\000"
8619 /* 15461 */ "ICBTLS\000"
8620 /* 15468 */ "LHAXTLS\000"
8621 /* 15476 */ "LWAXTLS\000"
8622 /* 15484 */ "STBXTLS\000"
8623 /* 15492 */ "LFDXTLS\000"
8624 /* 15500 */ "STFDXTLS\000"
8625 /* 15509 */ "LDXTLS\000"
8626 /* 15516 */ "STDXTLS\000"
8627 /* 15524 */ "STHXTLS\000"
8628 /* 15532 */ "LFSXTLS\000"
8629 /* 15540 */ "STFSXTLS\000"
8630 /* 15549 */ "STWXTLS\000"
8631 /* 15557 */ "LBZXTLS\000"
8632 /* 15565 */ "LHZXTLS\000"
8633 /* 15573 */ "LWZXTLS\000"
8634 /* 15581 */ "BL8_TLS\000"
8635 /* 15589 */ "BL8_NOTOC_TLS\000"
8636 /* 15603 */ "BL_TLS\000"
8637 /* 15610 */ "BL8_NOP_TLS\000"
8638 /* 15622 */ "FMULS\000"
8639 /* 15628 */ "FRIMS\000"
8640 /* 15634 */ "FCPSGNS\000"
8641 /* 15642 */ "FRINS\000"
8642 /* 15648 */ "G_FACOS\000"
8643 /* 15656 */ "G_FCOS\000"
8644 /* 15663 */ "G_FSINCOS\000"
8645 /* 15673 */ "EVLWHOS\000"
8646 /* 15681 */ "FCMPOS\000"
8647 /* 15688 */ "DCBFPS\000"
8648 /* 15695 */ "FRIPS\000"
8649 /* 15701 */ "DCBSTPS\000"
8650 /* 15709 */ "G_CONCAT_VECTORS\000"
8651 /* 15726 */ "COPY_TO_REGCLASS\000"
8652 /* 15743 */ "G_IS_FPCLASS\000"
8653 /* 15756 */ "FABSS\000"
8654 /* 15762 */ "FNABSS\000"
8655 /* 15769 */ "VPKSDSS\000"
8656 /* 15777 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
8657 /* 15807 */ "G_VECTOR_COMPRESS\000"
8658 /* 15825 */ "VPKSHSS\000"
8659 /* 15833 */ "VPKSWSS\000"
8660 /* 15841 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
8661 /* 15868 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
8662 /* 15906 */ "EVCMPGTS\000"
8663 /* 15915 */ "EVCMPLTS\000"
8664 /* 15924 */ "FSQRTS\000"
8665 /* 15931 */ "FCFIDUS\000"
8666 /* 15939 */ "VPKSDUS\000"
8667 /* 15947 */ "VPKUDUS\000"
8668 /* 15955 */ "SUBFUS\000"
8669 /* 15962 */ "VPKSHUS\000"
8670 /* 15970 */ "VPKUHUS\000"
8671 /* 15978 */ "FCMPUS\000"
8672 /* 15985 */ "VPKSWUS\000"
8673 /* 15993 */ "VPKUWUS\000"
8674 /* 16001 */ "FDIVS\000"
8675 /* 16007 */ "EVSRWS\000"
8676 /* 16014 */ "MTVSRWS\000"
8677 /* 16022 */ "VSUM2SWS\000"
8678 /* 16031 */ "VSUBSWS\000"
8679 /* 16039 */ "VADDSWS\000"
8680 /* 16047 */ "VSUMSWS\000"
8681 /* 16055 */ "VSUBUWS\000"
8682 /* 16063 */ "VADDUWS\000"
8683 /* 16071 */ "EVDIVWS\000"
8684 /* 16079 */ "XSCVDPSXWS\000"
8685 /* 16090 */ "XVCVDPSXWS\000"
8686 /* 16101 */ "XVCVSPSXWS\000"
8687 /* 16112 */ "XSCVDPUXWS\000"
8688 /* 16123 */ "XVCVDPUXWS\000"
8689 /* 16134 */ "XVCVSPUXWS\000"
8690 /* 16145 */ "VCTSXS\000"
8691 /* 16152 */ "VCTUXS\000"
8692 /* 16159 */ "FRIZS\000"
8693 /* 16165 */ "LDAT\000"
8694 /* 16170 */ "STDAT\000"
8695 /* 16176 */ "EVLHHESPLAT\000"
8696 /* 16188 */ "EVLWHSPLAT\000"
8697 /* 16199 */ "EVLHHOSSPLAT\000"
8698 /* 16212 */ "EVLHHOUSPLAT\000"
8699 /* 16225 */ "EVLWWSPLAT\000"
8700 /* 16236 */ "G_SSUBSAT\000"
8701 /* 16246 */ "G_USUBSAT\000"
8702 /* 16256 */ "G_SADDSAT\000"
8703 /* 16266 */ "G_UADDSAT\000"
8704 /* 16276 */ "G_SSHLSAT\000"
8705 /* 16286 */ "G_USHLSAT\000"
8706 /* 16296 */ "G_SMULFIXSAT\000"
8707 /* 16309 */ "G_UMULFIXSAT\000"
8708 /* 16322 */ "G_SDIVFIXSAT\000"
8709 /* 16335 */ "G_UDIVFIXSAT\000"
8710 /* 16348 */ "G_ATOMICRMW_USUB_SAT\000"
8711 /* 16369 */ "G_FPTOSI_SAT\000"
8712 /* 16382 */ "G_FPTOUI_SAT\000"
8713 /* 16395 */ "LWAT\000"
8714 /* 16400 */ "STWAT\000"
8715 /* 16406 */ "DCBT\000"
8716 /* 16411 */ "ICBT\000"
8717 /* 16416 */ "G_EXTRACT\000"
8718 /* 16426 */ "G_SELECT\000"
8719 /* 16435 */ "G_BRINDIRECT\000"
8720 /* 16448 */ "DCBTCT\000"
8721 /* 16455 */ "DCBTSTCT\000"
8722 /* 16464 */ "PATCHABLE_RET\000"
8723 /* 16478 */ "TCHECK_RET\000"
8724 /* 16489 */ "TBEGIN_RET\000"
8725 /* 16500 */ "CR6SET\000"
8726 /* 16507 */ "DYNAREAOFFSET\000"
8727 /* 16521 */ "G_MEMSET\000"
8728 /* 16530 */ "CR6UNSET\000"
8729 /* 16539 */ "CRUNSET\000"
8730 /* 16547 */ "CRSET\000"
8731 /* 16553 */ "EFDCMPGT\000"
8732 /* 16562 */ "EFSCMPGT\000"
8733 /* 16571 */ "EVFSCMPGT\000"
8734 /* 16581 */ "EFDTSTGT\000"
8735 /* 16590 */ "EFSTSTGT\000"
8736 /* 16599 */ "EVFSTSTGT\000"
8737 /* 16609 */ "WAIT\000"
8738 /* 16614 */ "RESTORE_CRBIT\000"
8739 /* 16628 */ "SPILL_CRBIT\000"
8740 /* 16640 */ "ANDI_rec_1_EQ_BIT\000"
8741 /* 16658 */ "ANDI_rec_1_GT_BIT\000"
8742 /* 16676 */ "PATCHABLE_FUNCTION_EXIT\000"
8743 /* 16700 */ "G_BRJT\000"
8744 /* 16707 */ "G_EXTRACT_VECTOR_ELT\000"
8745 /* 16728 */ "G_INSERT_VECTOR_ELT\000"
8746 /* 16748 */ "EFDCMPLT\000"
8747 /* 16757 */ "EFSCMPLT\000"
8748 /* 16766 */ "EVFSCMPLT\000"
8749 /* 16776 */ "EFDTSTLT\000"
8750 /* 16785 */ "EFSTSTLT\000"
8751 /* 16794 */ "EVFSTSTLT\000"
8752 /* 16804 */ "G_FCONSTANT\000"
8753 /* 16816 */ "G_CONSTANT\000"
8754 /* 16827 */ "G_INTRINSIC_CONVERGENT\000"
8755 /* 16850 */ "STATEPOINT\000"
8756 /* 16861 */ "PATCHPOINT\000"
8757 /* 16872 */ "G_PTRTOINT\000"
8758 /* 16883 */ "G_FRINT\000"
8759 /* 16891 */ "G_INTRINSIC_LLRINT\000"
8760 /* 16910 */ "G_INTRINSIC_LRINT\000"
8761 /* 16928 */ "G_FNEARBYINT\000"
8762 /* 16941 */ "PPC32GOT\000"
8763 /* 16950 */ "PPC32PICGOT\000"
8764 /* 16962 */ "CRNOT\000"
8765 /* 16968 */ "LDtocCPT\000"
8766 /* 16977 */ "TRECHKPT\000"
8767 /* 16986 */ "G_VASTART\000"
8768 /* 16996 */ "LIFETIME_START\000"
8769 /* 17011 */ "G_INVOKE_REGION_START\000"
8770 /* 17033 */ "G_INSERT\000"
8771 /* 17042 */ "TABORT\000"
8772 /* 17049 */ "CP_ABORT\000"
8773 /* 17058 */ "G_FSQRT\000"
8774 /* 17066 */ "G_STRICT_FSQRT\000"
8775 /* 17081 */ "FTSQRT\000"
8776 /* 17088 */ "G_BITCAST\000"
8777 /* 17098 */ "G_ADDRSPACE_CAST\000"
8778 /* 17115 */ "VNCIPHERLAST\000"
8779 /* 17128 */ "VCIPHERLAST\000"
8780 /* 17140 */ "DCBST\000"
8781 /* 17146 */ "DST\000"
8782 /* 17150 */ "HASHST\000"
8783 /* 17157 */ "DBG_VALUE_LIST\000"
8784 /* 17172 */ "DCBTST\000"
8785 /* 17179 */ "DSTST\000"
8786 /* 17185 */ "SPILLTOVSR_ST\000"
8787 /* 17199 */ "DCBTT\000"
8788 /* 17205 */ "DSTT\000"
8789 /* 17210 */ "DCBTSTT\000"
8790 /* 17218 */ "DSTSTT\000"
8791 /* 17225 */ "G_FPEXT\000"
8792 /* 17233 */ "G_SEXT\000"
8793 /* 17240 */ "G_ASSERT_SEXT\000"
8794 /* 17254 */ "G_ANYEXT\000"
8795 /* 17263 */ "G_ZEXT\000"
8796 /* 17270 */ "G_ASSERT_ZEXT\000"
8797 /* 17284 */ "LHAU\000"
8798 /* 17289 */ "STBU\000"
8799 /* 17294 */ "G_ABDU\000"
8800 /* 17301 */ "LFDU\000"
8801 /* 17306 */ "STFDU\000"
8802 /* 17312 */ "MADDHDU\000"
8803 /* 17320 */ "MULHDU\000"
8804 /* 17327 */ "FCFIDU\000"
8805 /* 17334 */ "FCTIDU\000"
8806 /* 17341 */ "LDU\000"
8807 /* 17345 */ "STDU\000"
8808 /* 17350 */ "DIVDU\000"
8809 /* 17356 */ "DIVDEU\000"
8810 /* 17363 */ "DIVWEU\000"
8811 /* 17370 */ "STHU\000"
8812 /* 17375 */ "EVSRWIU\000"
8813 /* 17383 */ "EVLWHOU\000"
8814 /* 17391 */ "DCMPU\000"
8815 /* 17397 */ "LFSU\000"
8816 /* 17402 */ "STFSU\000"
8817 /* 17408 */ "EVCMPGTU\000"
8818 /* 17417 */ "EVCMPLTU\000"
8819 /* 17426 */ "MULHWU\000"
8820 /* 17433 */ "FCTIWU\000"
8821 /* 17440 */ "EVSRWU\000"
8822 /* 17447 */ "STWU\000"
8823 /* 17452 */ "EVDIVWU\000"
8824 /* 17460 */ "LBZU\000"
8825 /* 17465 */ "LHZU\000"
8826 /* 17470 */ "LWZU\000"
8827 /* 17475 */ "SCV\000"
8828 /* 17479 */ "SLBMFEV\000"
8829 /* 17487 */ "EFDDIV\000"
8830 /* 17494 */ "G_FDIV\000"
8831 /* 17501 */ "G_STRICT_FDIV\000"
8832 /* 17515 */ "EFSDIV\000"
8833 /* 17522 */ "EVFSDIV\000"
8834 /* 17530 */ "G_SDIV\000"
8835 /* 17537 */ "FTDIV\000"
8836 /* 17543 */ "G_UDIV\000"
8837 /* 17550 */ "VSLV\000"
8838 /* 17555 */ "G_GET_FPENV\000"
8839 /* 17567 */ "G_RESET_FPENV\000"
8840 /* 17581 */ "G_SET_FPENV\000"
8841 /* 17593 */ "XXLEQV\000"
8842 /* 17600 */ "CREQV\000"
8843 /* 17606 */ "EVEQV\000"
8844 /* 17612 */ "VSRV\000"
8845 /* 17617 */ "PLXV\000"
8846 /* 17622 */ "PSTXV\000"
8847 /* 17628 */ "VEXTSB2W\000"
8848 /* 17637 */ "VEXTSH2W\000"
8849 /* 17646 */ "PMXVBF16GER2W\000"
8850 /* 17660 */ "PMXVF16GER2W\000"
8851 /* 17673 */ "PMXVI16GER2W\000"
8852 /* 17686 */ "PMXVI8GER4W\000"
8853 /* 17698 */ "PMXVI4GER8W\000"
8854 /* 17710 */ "EVMHESMFAAW\000"
8855 /* 17722 */ "EVMHOSMFAAW\000"
8856 /* 17734 */ "EVMHESSFAAW\000"
8857 /* 17746 */ "EVMHOSSFAAW\000"
8858 /* 17758 */ "EVADDSMIAAW\000"
8859 /* 17770 */ "EVMHESMIAAW\000"
8860 /* 17782 */ "EVSUBFSMIAAW\000"
8861 /* 17795 */ "EVMWLSMIAAW\000"
8862 /* 17807 */ "EVMHOSMIAAW\000"
8863 /* 17819 */ "EVADDUMIAAW\000"
8864 /* 17831 */ "EVMHEUMIAAW\000"
8865 /* 17843 */ "EVSUBFUMIAAW\000"
8866 /* 17856 */ "EVMWLUMIAAW\000"
8867 /* 17868 */ "EVMHOUMIAAW\000"
8868 /* 17880 */ "EVADDSSIAAW\000"
8869 /* 17892 */ "EVMHESSIAAW\000"
8870 /* 17904 */ "EVSUBFSSIAAW\000"
8871 /* 17917 */ "EVMWLSSIAAW\000"
8872 /* 17929 */ "EVMHOSSIAAW\000"
8873 /* 17941 */ "EVADDUSIAAW\000"
8874 /* 17953 */ "EVMHEUSIAAW\000"
8875 /* 17965 */ "EVSUBFUSIAAW\000"
8876 /* 17978 */ "EVMWLUSIAAW\000"
8877 /* 17990 */ "EVMHOUSIAAW\000"
8878 /* 18002 */ "VSHASIGMAW\000"
8879 /* 18013 */ "VSRAW\000"
8880 /* 18019 */ "VCNTMBW\000"
8881 /* 18027 */ "VPRTYBW\000"
8882 /* 18035 */ "XXMFACCW\000"
8883 /* 18044 */ "XXMTACCW\000"
8884 /* 18053 */ "EVADDW\000"
8885 /* 18060 */ "EVLDW\000"
8886 /* 18066 */ "EVRNDW\000"
8887 /* 18073 */ "EVSTDW\000"
8888 /* 18080 */ "VMRGEW\000"
8889 /* 18087 */ "VCMPNEW\000"
8890 /* 18095 */ "EVSUBFW\000"
8891 /* 18103 */ "EVSUBIFW\000"
8892 /* 18112 */ "VNEGW\000"
8893 /* 18118 */ "VMRGHW\000"
8894 /* 18125 */ "XXMRGHW\000"
8895 /* 18133 */ "MULHW\000"
8896 /* 18139 */ "EVADDIW\000"
8897 /* 18147 */ "FCTIW\000"
8898 /* 18153 */ "XXSPLTIW\000"
8899 /* 18162 */ "VMRGLW\000"
8900 /* 18169 */ "XXMRGLW\000"
8901 /* 18177 */ "MULLW\000"
8902 /* 18183 */ "CMPLW\000"
8903 /* 18189 */ "EVRLW\000"
8904 /* 18195 */ "EVSLW\000"
8905 /* 18201 */ "LMW\000"
8906 /* 18205 */ "STMW\000"
8907 /* 18210 */ "VPMSUMW\000"
8908 /* 18218 */ "EVMHESMFANW\000"
8909 /* 18230 */ "EVMHOSMFANW\000"
8910 /* 18242 */ "EVMHESSFANW\000"
8911 /* 18254 */ "EVMHOSSFANW\000"
8912 /* 18266 */ "EVMHESMIANW\000"
8913 /* 18278 */ "EVMWLSMIANW\000"
8914 /* 18290 */ "EVMHOSMIANW\000"
8915 /* 18302 */ "EVMHEUMIANW\000"
8916 /* 18314 */ "EVMWLUMIANW\000"
8917 /* 18326 */ "EVMHOUMIANW\000"
8918 /* 18338 */ "EVMHESSIANW\000"
8919 /* 18350 */ "EVMWLSSIANW\000"
8920 /* 18362 */ "EVMHOSSIANW\000"
8921 /* 18374 */ "EVMHEUSIANW\000"
8922 /* 18386 */ "EVMWLUSIANW\000"
8923 /* 18398 */ "EVMHOUSIANW\000"
8924 /* 18410 */ "VMRGOW\000"
8925 /* 18417 */ "G_FPOW\000"
8926 /* 18424 */ "CMPW\000"
8927 /* 18429 */ "XXBRW\000"
8928 /* 18435 */ "PMXVF32GERW\000"
8929 /* 18447 */ "PMXVF64GERW\000"
8930 /* 18459 */ "VSRW\000"
8931 /* 18464 */ "PMXVI16GER2SW\000"
8932 /* 18478 */ "VMODSW\000"
8933 /* 18485 */ "VMULESW\000"
8934 /* 18493 */ "VDIVESW\000"
8935 /* 18501 */ "VAVGSW\000"
8936 /* 18508 */ "VUPKHSW\000"
8937 /* 18516 */ "VMULHSW\000"
8938 /* 18524 */ "VSPLTISW\000"
8939 /* 18533 */ "VUPKLSW\000"
8940 /* 18541 */ "EVCNTLSW\000"
8941 /* 18550 */ "VMINSW\000"
8942 /* 18557 */ "VINSW\000"
8943 /* 18563 */ "VMULOSW\000"
8944 /* 18571 */ "VCMPGTSW\000"
8945 /* 18580 */ "EXTSW\000"
8946 /* 18586 */ "VDIVSW\000"
8947 /* 18593 */ "VMAXSW\000"
8948 /* 18600 */ "VSPLTW\000"
8949 /* 18607 */ "XXSPLTW\000"
8950 /* 18615 */ "VPOPCNTW\000"
8951 /* 18624 */ "VINSERTW\000"
8952 /* 18633 */ "XXINSERTW\000"
8953 /* 18643 */ "SPESTW\000"
8954 /* 18650 */ "PSTW\000"
8955 /* 18655 */ "VSUBCUW\000"
8956 /* 18663 */ "VADDCUW\000"
8957 /* 18671 */ "VMODUW\000"
8958 /* 18678 */ "VABSDUW\000"
8959 /* 18686 */ "VMULEUW\000"
8960 /* 18694 */ "VDIVEUW\000"
8961 /* 18702 */ "VAVGUW\000"
8962 /* 18709 */ "VMULHUW\000"
8963 /* 18717 */ "VMINUW\000"
8964 /* 18724 */ "VMULOUW\000"
8965 /* 18732 */ "VCMPEQUW\000"
8966 /* 18741 */ "VEXTRACTUW\000"
8967 /* 18752 */ "XXEXTRACTUW\000"
8968 /* 18764 */ "VCMPGTUW\000"
8969 /* 18773 */ "VDIVUW\000"
8970 /* 18780 */ "VMAXUW\000"
8971 /* 18787 */ "XXBLENDVW\000"
8972 /* 18797 */ "DIVW\000"
8973 /* 18802 */ "VCMPNEZW\000"
8974 /* 18811 */ "VCLZW\000"
8975 /* 18817 */ "EVCNTLZW\000"
8976 /* 18826 */ "VCTZW\000"
8977 /* 18832 */ "CNTTZW\000"
8978 /* 18839 */ "LXVD2X\000"
8979 /* 18846 */ "STXVD2X\000"
8980 /* 18854 */ "LXVW4X\000"
8981 /* 18861 */ "STXVW4X\000"
8982 /* 18869 */ "LXVB16X\000"
8983 /* 18877 */ "STXVB16X\000"
8984 /* 18886 */ "LXVH8X\000"
8985 /* 18893 */ "STXVH8X\000"
8986 /* 18901 */ "LHAX\000"
8987 /* 18906 */ "G_VECREDUCE_FMAX\000"
8988 /* 18923 */ "G_ATOMICRMW_FMAX\000"
8989 /* 18940 */ "G_VECREDUCE_SMAX\000"
8990 /* 18957 */ "G_SMAX\000"
8991 /* 18964 */ "G_VECREDUCE_UMAX\000"
8992 /* 18981 */ "G_UMAX\000"
8993 /* 18988 */ "G_ATOMICRMW_UMAX\000"
8994 /* 19005 */ "G_ATOMICRMW_MAX\000"
8995 /* 19021 */ "TLBIVAX\000"
8996 /* 19029 */ "LFIWAX\000"
8997 /* 19036 */ "LIWAX\000"
8998 /* 19042 */ "LXSIWAX\000"
8999 /* 19050 */ "LWAX\000"
9000 /* 19055 */ "LVEBX\000"
9001 /* 19061 */ "STVEBX\000"
9002 /* 19068 */ "STXSIBX\000"
9003 /* 19076 */ "LXVRBX\000"
9004 /* 19083 */ "STXVRBX\000"
9005 /* 19091 */ "STBX\000"
9006 /* 19096 */ "STBCX\000"
9007 /* 19102 */ "STDCX\000"
9008 /* 19108 */ "STHCX\000"
9009 /* 19114 */ "STQCX\000"
9010 /* 19120 */ "STWCX\000"
9011 /* 19126 */ "XXSPLTI32DX\000"
9012 /* 19138 */ "EVLDDX\000"
9013 /* 19145 */ "EVSTDDX\000"
9014 /* 19153 */ "LFDX\000"
9015 /* 19158 */ "STFDX\000"
9016 /* 19164 */ "SPILLTOVSR_LDX\000"
9017 /* 19179 */ "LXVRDX\000"
9018 /* 19186 */ "STXVRDX\000"
9019 /* 19194 */ "LXSDX\000"
9020 /* 19200 */ "STXSDX\000"
9021 /* 19207 */ "STDX\000"
9022 /* 19212 */ "ADDEX\000"
9023 /* 19218 */ "G_FRAME_INDEX\000"
9024 /* 19232 */ "EVLWHEX\000"
9025 /* 19240 */ "EVSTWHEX\000"
9026 /* 19249 */ "DIEX\000"
9027 /* 19254 */ "DTSTEX\000"
9028 /* 19261 */ "EVSTWWEX\000"
9029 /* 19270 */ "DXEX\000"
9030 /* 19275 */ "G_SBFX\000"
9031 /* 19282 */ "G_UBFX\000"
9032 /* 19289 */ "EVLDHX\000"
9033 /* 19296 */ "EVSTDHX\000"
9034 /* 19304 */ "LVEHX\000"
9035 /* 19310 */ "STVEHX\000"
9036 /* 19317 */ "STXSIHX\000"
9037 /* 19325 */ "LXVRHX\000"
9038 /* 19332 */ "STXVRHX\000"
9039 /* 19340 */ "STHX\000"
9040 /* 19345 */ "GETtlsMOD32AIX\000"
9041 /* 19360 */ "GETtlsADDR32AIX\000"
9042 /* 19376 */ "GETtlsTpointer32AIX\000"
9043 /* 19396 */ "GETtlsMOD64AIX\000"
9044 /* 19411 */ "GETtlsADDR64AIX\000"
9045 /* 19427 */ "TLSGDAIX\000"
9046 /* 19436 */ "TLSLDAIX\000"
9047 /* 19445 */ "STBCIX\000"
9048 /* 19452 */ "LDCIX\000"
9049 /* 19458 */ "STDCIX\000"
9050 /* 19465 */ "STHCIX\000"
9051 /* 19472 */ "STWCIX\000"
9052 /* 19479 */ "LBZCIX\000"
9053 /* 19486 */ "LHZCIX\000"
9054 /* 19493 */ "LWZCIX\000"
9055 /* 19500 */ "DCFFIX\000"
9056 /* 19507 */ "G_SMULFIX\000"
9057 /* 19517 */ "G_UMULFIX\000"
9058 /* 19527 */ "DCTFIX\000"
9059 /* 19534 */ "G_SDIVFIX\000"
9060 /* 19544 */ "G_UDIVFIX\000"
9061 /* 19554 */ "XSRQPIX\000"
9062 /* 19562 */ "VINSBLX\000"
9063 /* 19570 */ "VEXTUBLX\000"
9064 /* 19579 */ "VINSDLX\000"
9065 /* 19587 */ "VINSHLX\000"
9066 /* 19595 */ "VEXTUHLX\000"
9067 /* 19604 */ "TLBILX\000"
9068 /* 19611 */ "VINSBVLX\000"
9069 /* 19620 */ "VEXTDUBVLX\000"
9070 /* 19631 */ "VEXTDDVLX\000"
9071 /* 19641 */ "VINSHVLX\000"
9072 /* 19650 */ "VEXTDUHVLX\000"
9073 /* 19661 */ "VINSWVLX\000"
9074 /* 19670 */ "VEXTDUWVLX\000"
9075 /* 19681 */ "VINSWLX\000"
9076 /* 19689 */ "VEXTUWLX\000"
9077 /* 19698 */ "XXPERMX\000"
9078 /* 19706 */ "VSBOX\000"
9079 /* 19712 */ "EVSTWHOX\000"
9080 /* 19721 */ "EVSTWWOX\000"
9081 /* 19730 */ "LBEPX\000"
9082 /* 19736 */ "STBEPX\000"
9083 /* 19743 */ "LFDEPX\000"
9084 /* 19750 */ "STFDEPX\000"
9085 /* 19758 */ "LHEPX\000"
9086 /* 19764 */ "STHEPX\000"
9087 /* 19771 */ "LWEPX\000"
9088 /* 19777 */ "STWEPX\000"
9089 /* 19784 */ "VUPKHPX\000"
9090 /* 19792 */ "VPKPX\000"
9091 /* 19798 */ "VUPKLPX\000"
9092 /* 19806 */ "LXSSPX\000"
9093 /* 19813 */ "STXSSPX\000"
9094 /* 19821 */ "LXVPX\000"
9095 /* 19827 */ "STXVPX\000"
9096 /* 19834 */ "LBARX\000"
9097 /* 19840 */ "LDARX\000"
9098 /* 19846 */ "LHARX\000"
9099 /* 19852 */ "LQARX\000"
9100 /* 19858 */ "LWARX\000"
9101 /* 19864 */ "LDBRX\000"
9102 /* 19870 */ "STDBRX\000"
9103 /* 19877 */ "LHBRX\000"
9104 /* 19883 */ "STHBRX\000"
9105 /* 19890 */ "VINSBRX\000"
9106 /* 19898 */ "VEXTUBRX\000"
9107 /* 19907 */ "LWBRX\000"
9108 /* 19913 */ "STWBRX\000"
9109 /* 19920 */ "VINSDRX\000"
9110 /* 19928 */ "VINSHRX\000"
9111 /* 19936 */ "VEXTUHRX\000"
9112 /* 19945 */ "VINSBVRX\000"
9113 /* 19954 */ "VEXTDUBVRX\000"
9114 /* 19965 */ "VEXTDDVRX\000"
9115 /* 19975 */ "VINSHVRX\000"
9116 /* 19984 */ "VEXTDUHVRX\000"
9117 /* 19995 */ "VINSWVRX\000"
9118 /* 20004 */ "VEXTDUWVRX\000"
9119 /* 20015 */ "VINSWRX\000"
9120 /* 20023 */ "VEXTUWRX\000"
9121 /* 20032 */ "MCRXRX\000"
9122 /* 20039 */ "TLBSX\000"
9123 /* 20045 */ "LXVDSX\000"
9124 /* 20052 */ "VCFSX\000"
9125 /* 20058 */ "LFSX\000"
9126 /* 20063 */ "STFSX\000"
9127 /* 20069 */ "EVLWHOSX\000"
9128 /* 20078 */ "LXVWSX\000"
9129 /* 20085 */ "EVLHHESPLATX\000"
9130 /* 20098 */ "EVLWHSPLATX\000"
9131 /* 20110 */ "EVLHHOSSPLATX\000"
9132 /* 20124 */ "EVLHHOUSPLATX\000"
9133 /* 20138 */ "EVLWWSPLATX\000"
9134 /* 20150 */ "DRINTX\000"
9135 /* 20157 */ "SPILLTOVSR_STX\000"
9136 /* 20172 */ "LHAUX\000"
9137 /* 20178 */ "LWAUX\000"
9138 /* 20184 */ "STBUX\000"
9139 /* 20190 */ "LFDUX\000"
9140 /* 20196 */ "STFDUX\000"
9141 /* 20203 */ "LDUX\000"
9142 /* 20208 */ "STDUX\000"
9143 /* 20214 */ "VCFUX\000"
9144 /* 20220 */ "STHUX\000"
9145 /* 20226 */ "EVLWHOUX\000"
9146 /* 20235 */ "LFSUX\000"
9147 /* 20241 */ "STFSUX\000"
9148 /* 20248 */ "STWUX\000"
9149 /* 20254 */ "LBZUX\000"
9150 /* 20260 */ "LHZUX\000"
9151 /* 20266 */ "LWZUX\000"
9152 /* 20272 */ "LVX\000"
9153 /* 20276 */ "STVX\000"
9154 /* 20281 */ "LXVX\000"
9155 /* 20286 */ "STXVX\000"
9156 /* 20292 */ "EVLDWX\000"
9157 /* 20299 */ "EVSTDWX\000"
9158 /* 20307 */ "LVEWX\000"
9159 /* 20313 */ "STVEWX\000"
9160 /* 20320 */ "STFIWX\000"
9161 /* 20327 */ "STXSIWX\000"
9162 /* 20335 */ "STIWX\000"
9163 /* 20341 */ "LXVRWX\000"
9164 /* 20348 */ "STXVRWX\000"
9165 /* 20356 */ "SPESTWX\000"
9166 /* 20364 */ "LXSIBZX\000"
9167 /* 20372 */ "LBZX\000"
9168 /* 20377 */ "LXSIHZX\000"
9169 /* 20385 */ "LHZX\000"
9170 /* 20390 */ "LFIWZX\000"
9171 /* 20397 */ "LIWZX\000"
9172 /* 20403 */ "LXSIWZX\000"
9173 /* 20411 */ "SPELWZX\000"
9174 /* 20419 */ "G_MEMCPY\000"
9175 /* 20428 */ "CP_COPY\000"
9176 /* 20436 */ "CONVERGENCECTRL_ENTRY\000"
9177 /* 20458 */ "DCBZ\000"
9178 /* 20463 */ "PLBZ\000"
9179 /* 20468 */ "DMXXSETACCZ\000"
9180 /* 20480 */ "BDZ\000"
9181 /* 20484 */ "EFDCTSIDZ\000"
9182 /* 20494 */ "FCTIDZ\000"
9183 /* 20501 */ "EFDCTUIDZ\000"
9184 /* 20511 */ "XSCVQPSDZ\000"
9185 /* 20521 */ "XSCVQPUDZ\000"
9186 /* 20531 */ "PLHZ\000"
9187 /* 20536 */ "VRFIZ\000"
9188 /* 20542 */ "XSRDPIZ\000"
9189 /* 20550 */ "XVRDPIZ\000"
9190 /* 20558 */ "XVRSPIZ\000"
9191 /* 20566 */ "EFDCTSIZ\000"
9192 /* 20575 */ "EFSCTSIZ\000"
9193 /* 20584 */ "EVFSCTSIZ\000"
9194 /* 20594 */ "EFDCTUIZ\000"
9195 /* 20603 */ "EFSCTUIZ\000"
9196 /* 20612 */ "EVFSCTUIZ\000"
9197 /* 20622 */ "G_CTLZ\000"
9198 /* 20629 */ "BDNZ\000"
9199 /* 20634 */ "XSCVQPSQZ\000"
9200 /* 20644 */ "XSCVQPUQZ\000"
9201 /* 20654 */ "DMSETDMRZ\000"
9202 /* 20664 */ "G_CTTZ\000"
9203 /* 20671 */ "FCTIDUZ\000"
9204 /* 20679 */ "FCTIWUZ\000"
9205 /* 20687 */ "FCTIWZ\000"
9206 /* 20694 */ "SPELWZ\000"
9207 /* 20701 */ "PLWZ\000"
9208 /* 20706 */ "MFVSRWZ\000"
9209 /* 20714 */ "MTVSRWZ\000"
9210 /* 20722 */ "MFVRWZ\000"
9211 /* 20729 */ "MTVRWZ\000"
9212 /* 20736 */ "XSCVQPSWZ\000"
9213 /* 20746 */ "XSCVQPUWZ\000"
9214 /* 20756 */ "ADD8TLS_\000"
9215 /* 20765 */ "LHAXTLS_\000"
9216 /* 20774 */ "LWAXTLS_\000"
9217 /* 20783 */ "STBXTLS_\000"
9218 /* 20792 */ "LFDXTLS_\000"
9219 /* 20801 */ "STFDXTLS_\000"
9220 /* 20811 */ "LDXTLS_\000"
9221 /* 20819 */ "STDXTLS_\000"
9222 /* 20828 */ "STHXTLS_\000"
9223 /* 20837 */ "LFSXTLS_\000"
9224 /* 20846 */ "STFSXTLS_\000"
9225 /* 20856 */ "STWXTLS_\000"
9226 /* 20865 */ "LBZXTLS_\000"
9227 /* 20874 */ "LHZXTLS_\000"
9228 /* 20883 */ "LWZXTLS_\000"
9229 /* 20892 */ "BL8_TLS_\000"
9230 /* 20901 */ "MTFSFb\000"
9231 /* 20908 */ "MTFSFIb\000"
9232 /* 20916 */ "RLDICL_32_rec\000"
9233 /* 20930 */ "EXTSWSLI_32_64_rec\000"
9234 /* 20949 */ "EXTSW_32_64_rec\000"
9235 /* 20965 */ "ADD4_rec\000"
9236 /* 20974 */ "EXTSB8_rec\000"
9237 /* 20985 */ "ADDC8_rec\000"
9238 /* 20995 */ "ANDC8_rec\000"
9239 /* 21005 */ "SUBFC8_rec\000"
9240 /* 21016 */ "ORC8_rec\000"
9241 /* 21025 */ "ADD8_rec\000"
9242 /* 21034 */ "NAND8_rec\000"
9243 /* 21044 */ "ADDE8_rec\000"
9244 /* 21054 */ "SUBFE8_rec\000"
9245 /* 21065 */ "ADDME8_rec\000"
9246 /* 21076 */ "SUBFME8_rec\000"
9247 /* 21088 */ "CP_PASTE8_rec\000"
9248 /* 21102 */ "ADDZE8_rec\000"
9249 /* 21113 */ "SUBFZE8_rec\000"
9250 /* 21125 */ "SUBF8_rec\000"
9251 /* 21135 */ "NEG8_rec\000"
9252 /* 21144 */ "EXTSH8_rec\000"
9253 /* 21155 */ "ANDI8_rec\000"
9254 /* 21165 */ "RLWIMI8_rec\000"
9255 /* 21177 */ "SRAWI8_rec\000"
9256 /* 21188 */ "RLWINM8_rec\000"
9257 /* 21200 */ "RLWNM8_rec\000"
9258 /* 21211 */ "NOR8_rec\000"
9259 /* 21220 */ "XOR8_rec\000"
9260 /* 21229 */ "ANDIS8_rec\000"
9261 /* 21240 */ "EQV8_rec\000"
9262 /* 21249 */ "SRAW8_rec\000"
9263 /* 21259 */ "SLW8_rec\000"
9264 /* 21268 */ "SRW8_rec\000"
9265 /* 21277 */ "CNTLZW8_rec\000"
9266 /* 21289 */ "CNTTZW8_rec\000"
9267 /* 21301 */ "DQUA_rec\000"
9268 /* 21310 */ "VCMPNEB_rec\000"
9269 /* 21322 */ "VCMPGTSB_rec\000"
9270 /* 21335 */ "EXTSB_rec\000"
9271 /* 21345 */ "VCMPEQUB_rec\000"
9272 /* 21358 */ "BCDSUB_rec\000"
9273 /* 21369 */ "FSUB_rec\000"
9274 /* 21378 */ "FMSUB_rec\000"
9275 /* 21388 */ "FNMSUB_rec\000"
9276 /* 21399 */ "VCMPGTUB_rec\000"
9277 /* 21412 */ "VCMPNEZB_rec\000"
9278 /* 21425 */ "ADDC_rec\000"
9279 /* 21434 */ "ANDC_rec\000"
9280 /* 21443 */ "SUBFC_rec\000"
9281 /* 21453 */ "SUBIC_rec\000"
9282 /* 21463 */ "ADDIC_rec\000"
9283 /* 21473 */ "RLDIC_rec\000"
9284 /* 21483 */ "BCDTRUNC_rec\000"
9285 /* 21496 */ "BCDUTRUNC_rec\000"
9286 /* 21510 */ "ORC_rec\000"
9287 /* 21518 */ "SRAD_rec\000"
9288 /* 21527 */ "DENBCD_rec\000"
9289 /* 21538 */ "BCDADD_rec\000"
9290 /* 21549 */ "FADD_rec\000"
9291 /* 21558 */ "FMADD_rec\000"
9292 /* 21568 */ "FNMADD_rec\000"
9293 /* 21579 */ "FNEGD_rec\000"
9294 /* 21589 */ "MULHD_rec\000"
9295 /* 21599 */ "FCFID_rec\000"
9296 /* 21609 */ "FCTID_rec\000"
9297 /* 21619 */ "FSELD_rec\000"
9298 /* 21629 */ "MULLD_rec\000"
9299 /* 21639 */ "SLD_rec\000"
9300 /* 21647 */ "FRIMD_rec\000"
9301 /* 21657 */ "NAND_rec\000"
9302 /* 21666 */ "FCPSGND_rec\000"
9303 /* 21678 */ "FRIND_rec\000"
9304 /* 21688 */ "DRRND_rec\000"
9305 /* 21698 */ "DDEDPD_rec\000"
9306 /* 21709 */ "FRIPD_rec\000"
9307 /* 21719 */ "SRD_rec\000"
9308 /* 21727 */ "FABSD_rec\000"
9309 /* 21737 */ "FNABSD_rec\000"
9310 /* 21748 */ "VCMPGTSD_rec\000"
9311 /* 21761 */ "VCMPEQUD_rec\000"
9312 /* 21774 */ "VCMPGTUD_rec\000"
9313 /* 21787 */ "DIVD_rec\000"
9314 /* 21796 */ "FRIZD_rec\000"
9315 /* 21806 */ "CNTLZD_rec\000"
9316 /* 21817 */ "CNTTZD_rec\000"
9317 /* 21828 */ "ADDE_rec\000"
9318 /* 21837 */ "DIVDE_rec\000"
9319 /* 21847 */ "SLBFEE_rec\000"
9320 /* 21858 */ "SUBFE_rec\000"
9321 /* 21868 */ "ADDME_rec\000"
9322 /* 21878 */ "SUBFME_rec\000"
9323 /* 21889 */ "FRE_rec\000"
9324 /* 21897 */ "FRSQRTE_rec\000"
9325 /* 21909 */ "CP_PASTE_rec\000"
9326 /* 21922 */ "DIVWE_rec\000"
9327 /* 21932 */ "ADDZE_rec\000"
9328 /* 21942 */ "SUBFZE_rec\000"
9329 /* 21953 */ "SUBF_rec\000"
9330 /* 21962 */ "MTFSF_rec\000"
9331 /* 21972 */ "NEG_rec\000"
9332 /* 21980 */ "VCMPNEH_rec\000"
9333 /* 21992 */ "VCMPGTSH_rec\000"
9334 /* 22005 */ "EXTSH_rec\000"
9335 /* 22015 */ "VCMPEQUH_rec\000"
9336 /* 22028 */ "VCMPGTUH_rec\000"
9337 /* 22041 */ "VCMPNEZH_rec\000"
9338 /* 22054 */ "DQUAI_rec\000"
9339 /* 22064 */ "SRADI_rec\000"
9340 /* 22074 */ "CLRLSLDI_rec\000"
9341 /* 22087 */ "EXTLDI_rec\000"
9342 /* 22098 */ "ANDI_rec\000"
9343 /* 22107 */ "CLRRDI_rec\000"
9344 /* 22118 */ "INSRDI_rec\000"
9345 /* 22129 */ "ROTRDI_rec\000"
9346 /* 22140 */ "EXTRDI_rec\000"
9347 /* 22151 */ "MTFSFI_rec\000"
9348 /* 22162 */ "DSCLI_rec\000"
9349 /* 22172 */ "EXTSWSLI_rec\000"
9350 /* 22185 */ "RLDIMI_rec\000"
9351 /* 22196 */ "RLWIMI_rec\000"
9352 /* 22207 */ "DSCRI_rec\000"
9353 /* 22217 */ "SRAWI_rec\000"
9354 /* 22227 */ "CLRLSLWI_rec\000"
9355 /* 22240 */ "INSLWI_rec\000"
9356 /* 22251 */ "EXTLWI_rec\000"
9357 /* 22262 */ "CLRRWI_rec\000"
9358 /* 22273 */ "INSRWI_rec\000"
9359 /* 22284 */ "ROTRWI_rec\000"
9360 /* 22295 */ "EXTRWI_rec\000"
9361 /* 22306 */ "VSTRIBL_rec\000"
9362 /* 22318 */ "RLDCL_rec\000"
9363 /* 22328 */ "RLDICL_rec\000"
9364 /* 22339 */ "VSTRIHL_rec\000"
9365 /* 22351 */ "DMUL_rec\000"
9366 /* 22360 */ "FMUL_rec\000"
9367 /* 22369 */ "RLWINM_rec\000"
9368 /* 22380 */ "RLWNM_rec\000"
9369 /* 22390 */ "BCDCFN_rec\000"
9370 /* 22401 */ "BCDCPSGN_rec\000"
9371 /* 22414 */ "BCDSETSGN_rec\000"
9372 /* 22428 */ "BCDCTN_rec\000"
9373 /* 22439 */ "DRINTN_rec\000"
9374 /* 22450 */ "ADD4O_rec\000"
9375 /* 22460 */ "ADDC8O_rec\000"
9376 /* 22471 */ "SUBFC8O_rec\000"
9377 /* 22483 */ "ADD8O_rec\000"
9378 /* 22493 */ "ADDE8O_rec\000"
9379 /* 22504 */ "SUBFE8O_rec\000"
9380 /* 22516 */ "ADDME8O_rec\000"
9381 /* 22528 */ "SUBFME8O_rec\000"
9382 /* 22541 */ "ADDZE8O_rec\000"
9383 /* 22553 */ "SUBFZE8O_rec\000"
9384 /* 22566 */ "SUBF8O_rec\000"
9385 /* 22577 */ "NEG8O_rec\000"
9386 /* 22587 */ "ADDCO_rec\000"
9387 /* 22597 */ "SUBFCO_rec\000"
9388 /* 22608 */ "MULLDO_rec\000"
9389 /* 22619 */ "DIVDO_rec\000"
9390 /* 22629 */ "ADDEO_rec\000"
9391 /* 22639 */ "DIVDEO_rec\000"
9392 /* 22650 */ "SUBFEO_rec\000"
9393 /* 22661 */ "ADDMEO_rec\000"
9394 /* 22672 */ "SUBFMEO_rec\000"
9395 /* 22684 */ "DIVWEO_rec\000"
9396 /* 22695 */ "ADDZEO_rec\000"
9397 /* 22706 */ "SUBFZEO_rec\000"
9398 /* 22718 */ "SUBFO_rec\000"
9399 /* 22728 */ "NEGO_rec\000"
9400 /* 22737 */ "DIVDUO_rec\000"
9401 /* 22748 */ "DIVDEUO_rec\000"
9402 /* 22760 */ "DIVWEUO_rec\000"
9403 /* 22772 */ "DIVWUO_rec\000"
9404 /* 22783 */ "MULLWO_rec\000"
9405 /* 22794 */ "DIVWO_rec\000"
9406 /* 22804 */ "XVCMPGEDP_rec\000"
9407 /* 22818 */ "XVCMPEQDP_rec\000"
9408 /* 22832 */ "DCTDP_rec\000"
9409 /* 22842 */ "XVCMPGTDP_rec\000"
9410 /* 22856 */ "VCMPBFP_rec\000"
9411 /* 22868 */ "VCMPGEFP_rec\000"
9412 /* 22881 */ "VCMPEQFP_rec\000"
9413 /* 22894 */ "VCMPGTFP_rec\000"
9414 /* 22907 */ "XVCMPGESP_rec\000"
9415 /* 22921 */ "XVCMPEQSP_rec\000"
9416 /* 22935 */ "DRSP_rec\000"
9417 /* 22944 */ "FRSP_rec\000"
9418 /* 22953 */ "XVCMPGTSP_rec\000"
9419 /* 22967 */ "DQUAQ_rec\000"
9420 /* 22977 */ "DSUBQ_rec\000"
9421 /* 22987 */ "DENBCDQ_rec\000"
9422 /* 22999 */ "DADDQ_rec\000"
9423 /* 23009 */ "DRRNDQ_rec\000"
9424 /* 23020 */ "DDEDPDQ_rec\000"
9425 /* 23032 */ "DQUAIQ_rec\000"
9426 /* 23043 */ "DSCLIQ_rec\000"
9427 /* 23054 */ "DSCRIQ_rec\000"
9428 /* 23065 */ "DMULQ_rec\000"
9429 /* 23075 */ "DRINTNQ_rec\000"
9430 /* 23087 */ "DRDPQ_rec\000"
9431 /* 23097 */ "DCTQPQ_rec\000"
9432 /* 23108 */ "BCDCFSQ_rec\000"
9433 /* 23120 */ "BCDCTSQ_rec\000"
9434 /* 23132 */ "VCMPGTSQ_rec\000"
9435 /* 23145 */ "VCMPEQUQ_rec\000"
9436 /* 23158 */ "VCMPGTUQ_rec\000"
9437 /* 23171 */ "DDIVQ_rec\000"
9438 /* 23181 */ "DIEXQ_rec\000"
9439 /* 23191 */ "DXEXQ_rec\000"
9440 /* 23201 */ "DCFFIXQ_rec\000"
9441 /* 23213 */ "DCTFIXQ_rec\000"
9442 /* 23225 */ "DRINTXQ_rec\000"
9443 /* 23237 */ "VSTRIBR_rec\000"
9444 /* 23249 */ "RLDCR_rec\000"
9445 /* 23259 */ "RLDICR_rec\000"
9446 /* 23270 */ "VSTRIHR_rec\000"
9447 /* 23282 */ "FMR_rec\000"
9448 /* 23290 */ "NOR_rec\000"
9449 /* 23298 */ "XOR_rec\000"
9450 /* 23306 */ "BCDSR_rec\000"
9451 /* 23316 */ "FSUBS_rec\000"
9452 /* 23326 */ "FMSUBS_rec\000"
9453 /* 23337 */ "FNMSUBS_rec\000"
9454 /* 23349 */ "BCDS_rec\000"
9455 /* 23358 */ "FADDS_rec\000"
9456 /* 23368 */ "FMADDS_rec\000"
9457 /* 23379 */ "FNMADDS_rec\000"
9458 /* 23391 */ "FCFIDS_rec\000"
9459 /* 23402 */ "FRES_rec\000"
9460 /* 23411 */ "FRSQRTES_rec\000"
9461 /* 23424 */ "MFFS_rec\000"
9462 /* 23433 */ "FNEGS_rec\000"
9463 /* 23443 */ "ANDIS_rec\000"
9464 /* 23453 */ "FSELS_rec\000"
9465 /* 23463 */ "FMULS_rec\000"
9466 /* 23473 */ "FRIMS_rec\000"
9467 /* 23483 */ "FCPSGNS_rec\000"
9468 /* 23495 */ "FRINS_rec\000"
9469 /* 23505 */ "FRIPS_rec\000"
9470 /* 23515 */ "FABSS_rec\000"
9471 /* 23525 */ "FNABSS_rec\000"
9472 /* 23536 */ "FSQRTS_rec\000"
9473 /* 23547 */ "BCDUS_rec\000"
9474 /* 23557 */ "FCFIDUS_rec\000"
9475 /* 23569 */ "SUBFUS_rec\000"
9476 /* 23580 */ "FDIVS_rec\000"
9477 /* 23590 */ "FRIZS_rec\000"
9478 /* 23600 */ "FSQRT_rec\000"
9479 /* 23610 */ "MULHDU_rec\000"
9480 /* 23621 */ "FCFIDU_rec\000"
9481 /* 23632 */ "FCTIDU_rec\000"
9482 /* 23643 */ "DIVDU_rec\000"
9483 /* 23653 */ "DIVDEU_rec\000"
9484 /* 23664 */ "DIVWEU_rec\000"
9485 /* 23675 */ "MULHWU_rec\000"
9486 /* 23686 */ "FCTIWU_rec\000"
9487 /* 23697 */ "DIVWU_rec\000"
9488 /* 23707 */ "DDIV_rec\000"
9489 /* 23716 */ "FDIV_rec\000"
9490 /* 23725 */ "EQV_rec\000"
9491 /* 23733 */ "SRAW_rec\000"
9492 /* 23742 */ "VCMPNEW_rec\000"
9493 /* 23754 */ "MULHW_rec\000"
9494 /* 23764 */ "FCTIW_rec\000"
9495 /* 23774 */ "MULLW_rec\000"
9496 /* 23784 */ "SLW_rec\000"
9497 /* 23792 */ "SRW_rec\000"
9498 /* 23800 */ "VCMPGTSW_rec\000"
9499 /* 23813 */ "EXTSW_rec\000"
9500 /* 23823 */ "VCMPEQUW_rec\000"
9501 /* 23836 */ "VCMPGTUW_rec\000"
9502 /* 23849 */ "DIVW_rec\000"
9503 /* 23858 */ "VCMPNEZW_rec\000"
9504 /* 23871 */ "CNTLZW_rec\000"
9505 /* 23882 */ "CNTTZW_rec\000"
9506 /* 23893 */ "DIEX_rec\000"
9507 /* 23902 */ "DXEX_rec\000"
9508 /* 23911 */ "DCFFIX_rec\000"
9509 /* 23922 */ "DCTFIX_rec\000"
9510 /* 23933 */ "DRINTX_rec\000"
9511 /* 23944 */ "FCTIDZ_rec\000"
9512 /* 23955 */ "BCDCFZ_rec\000"
9513 /* 23966 */ "BCDCTZ_rec\000"
9514 /* 23977 */ "FCTIDUZ_rec\000"
9515 /* 23989 */ "FCTIWUZ_rec\000"
9516 /* 24001 */ "FCTIWZ_rec\000"
9517 /* 24012 */ "RLWIMIbm_rec\000"
9518 /* 24025 */ "RLWINMbm_rec\000"
9519 /* 24038 */ "RLWNMbm_rec\000"
9520 /* 24050 */ "LDtoc\000"
9521 /* 24056 */ "ADDItoc\000"
9522 /* 24064 */ "LWZtoc\000"
9523 /* 24071 */ "BCTRL8_LDinto_toc\000"
9524 /* 24089 */ "BCTRL_LWZinto_toc\000"
9525 /* 24107 */ "PLHA8pc\000"
9526 /* 24115 */ "PLA8pc\000"
9527 /* 24122 */ "PLWA8pc\000"
9528 /* 24130 */ "PSTB8pc\000"
9529 /* 24138 */ "PSTH8pc\000"
9530 /* 24146 */ "PADDI8pc\000"
9531 /* 24155 */ "PSTW8pc\000"
9532 /* 24163 */ "PLBZ8pc\000"
9533 /* 24171 */ "PLHZ8pc\000"
9534 /* 24179 */ "PLWZ8pc\000"
9535 /* 24187 */ "PLHApc\000"
9536 /* 24194 */ "PLApc\000"
9537 /* 24200 */ "PLWApc\000"
9538 /* 24207 */ "PSTBpc\000"
9539 /* 24214 */ "PLFDpc\000"
9540 /* 24221 */ "PSTFDpc\000"
9541 /* 24229 */ "PLDpc\000"
9542 /* 24235 */ "PLXSDpc\000"
9543 /* 24243 */ "PSTXSDpc\000"
9544 /* 24252 */ "PSTDpc\000"
9545 /* 24259 */ "PSTHpc\000"
9546 /* 24266 */ "PADDIpc\000"
9547 /* 24274 */ "PLXSSPpc\000"
9548 /* 24283 */ "PSTXSSPpc\000"
9549 /* 24293 */ "PLXVPpc\000"
9550 /* 24301 */ "PSTXVPpc\000"
9551 /* 24310 */ "PLFSpc\000"
9552 /* 24317 */ "PSTFSpc\000"
9553 /* 24325 */ "PLXVpc\000"
9554 /* 24332 */ "PSTXVpc\000"
9555 /* 24340 */ "PSTWpc\000"
9556 /* 24347 */ "PLBZpc\000"
9557 /* 24354 */ "PLHZpc\000"
9558 /* 24361 */ "PLWZpc\000"
9559 /* 24368 */ "PLHA8nopc\000"
9560 /* 24378 */ "PLWA8nopc\000"
9561 /* 24388 */ "PSTB8nopc\000"
9562 /* 24398 */ "PSTH8nopc\000"
9563 /* 24408 */ "PSTW8nopc\000"
9564 /* 24418 */ "PLBZ8nopc\000"
9565 /* 24428 */ "PLHZ8nopc\000"
9566 /* 24438 */ "PLWZ8nopc\000"
9567 /* 24448 */ "PLHAnopc\000"
9568 /* 24457 */ "PLWAnopc\000"
9569 /* 24466 */ "PSTBnopc\000"
9570 /* 24475 */ "PLFDnopc\000"
9571 /* 24484 */ "PSTFDnopc\000"
9572 /* 24494 */ "PLDnopc\000"
9573 /* 24502 */ "PLXSDnopc\000"
9574 /* 24512 */ "PSTXSDnopc\000"
9575 /* 24523 */ "PSTDnopc\000"
9576 /* 24532 */ "PSTHnopc\000"
9577 /* 24541 */ "PLXSSPnopc\000"
9578 /* 24552 */ "PSTXSSPnopc\000"
9579 /* 24564 */ "PLXVPnopc\000"
9580 /* 24574 */ "PSTXVPnopc\000"
9581 /* 24585 */ "PLFSnopc\000"
9582 /* 24594 */ "PSTFSnopc\000"
9583 /* 24604 */ "PLXVnopc\000"
9584 /* 24613 */ "PSTXVnopc\000"
9585 /* 24623 */ "PSTWnopc\000"
9586 /* 24632 */ "PLBZnopc\000"
9587 /* 24641 */ "PLHZnopc\000"
9588 /* 24650 */ "PLWZnopc\000"
9589 /* 24659 */ "PLHA8onlypc\000"
9590 /* 24671 */ "PLWA8onlypc\000"
9591 /* 24683 */ "PSTB8onlypc\000"
9592 /* 24695 */ "PSTH8onlypc\000"
9593 /* 24707 */ "PSTW8onlypc\000"
9594 /* 24719 */ "PLBZ8onlypc\000"
9595 /* 24731 */ "PLHZ8onlypc\000"
9596 /* 24743 */ "PLWZ8onlypc\000"
9597 /* 24755 */ "PLHAonlypc\000"
9598 /* 24766 */ "PLWAonlypc\000"
9599 /* 24777 */ "PSTBonlypc\000"
9600 /* 24788 */ "PLFDonlypc\000"
9601 /* 24799 */ "PSTFDonlypc\000"
9602 /* 24811 */ "PLDonlypc\000"
9603 /* 24821 */ "PLXSDonlypc\000"
9604 /* 24833 */ "PSTXSDonlypc\000"
9605 /* 24846 */ "PSTDonlypc\000"
9606 /* 24857 */ "PSTHonlypc\000"
9607 /* 24868 */ "PLXSSPonlypc\000"
9608 /* 24881 */ "PSTXSSPonlypc\000"
9609 /* 24895 */ "PLXVPonlypc\000"
9610 /* 24907 */ "PSTXVPonlypc\000"
9611 /* 24920 */ "PLFSonlypc\000"
9612 /* 24931 */ "PSTFSonlypc\000"
9613 /* 24943 */ "PLXVonlypc\000"
9614 /* 24954 */ "PSTXVonlypc\000"
9615 /* 24966 */ "PSTWonlypc\000"
9616 /* 24977 */ "PLBZonlypc\000"
9617 /* 24988 */ "PLHZonlypc\000"
9618 /* 24999 */ "PLWZonlypc\000"
9619 /* 25010 */ "XXLORf\000"
9620 /* 25017 */ "SETRNDi\000"
9621 /* 25025 */ "TCRETURNai\000"
9622 /* 25036 */ "TCRETURNdi\000"
9623 /* 25047 */ "TCRETURNri\000"
9624 /* 25058 */ "PADDIdtprel\000"
9625 /* 25070 */ "BDZLAm\000"
9626 /* 25077 */ "BDNZLAm\000"
9627 /* 25085 */ "BDZAm\000"
9628 /* 25091 */ "BDNZAm\000"
9629 /* 25098 */ "BDZLRLm\000"
9630 /* 25106 */ "BDNZLRLm\000"
9631 /* 25115 */ "BDZLm\000"
9632 /* 25121 */ "BDNZLm\000"
9633 /* 25128 */ "BDZLRm\000"
9634 /* 25135 */ "BDNZLRm\000"
9635 /* 25143 */ "BDZm\000"
9636 /* 25148 */ "BDNZm\000"
9637 /* 25154 */ "RLWIMIbm\000"
9638 /* 25163 */ "RLWINMbm\000"
9639 /* 25172 */ "RLWNMbm\000"
9640 /* 25180 */ "BCCTRL8n\000"
9641 /* 25189 */ "BCCTR8n\000"
9642 /* 25197 */ "BCn\000"
9643 /* 25201 */ "BCLn\000"
9644 /* 25206 */ "BCLRLn\000"
9645 /* 25213 */ "BCCTRLn\000"
9646 /* 25221 */ "BCLRn\000"
9647 /* 25227 */ "BCCTRn\000"
9648 /* 25234 */ "BDZLAp\000"
9649 /* 25241 */ "BDNZLAp\000"
9650 /* 25249 */ "BDZAp\000"
9651 /* 25255 */ "BDNZAp\000"
9652 /* 25262 */ "BDZLRLp\000"
9653 /* 25270 */ "BDNZLRLp\000"
9654 /* 25279 */ "BDZLp\000"
9655 /* 25285 */ "BDNZLp\000"
9656 /* 25292 */ "BDZLRp\000"
9657 /* 25299 */ "BDNZLRp\000"
9658 /* 25307 */ "BDZp\000"
9659 /* 25312 */ "BDNZp\000"
9660 /* 25318 */ "MTCTR8loop\000"
9661 /* 25329 */ "DecreaseCTR8loop\000"
9662 /* 25346 */ "MTCTRloop\000"
9663 /* 25356 */ "DecreaseCTRloop\000"
9664 /* 25372 */ "EH_SjLj_Setup\000"
9665 /* 25386 */ "PPCLdFixedAddr\000"
9666 /* 25401 */ "VSPLTBs\000"
9667 /* 25409 */ "VEXTSB2Ds\000"
9668 /* 25419 */ "VEXTSH2Ds\000"
9669 /* 25429 */ "VEXTSW2Ds\000"
9670 /* 25439 */ "VSPLTHs\000"
9671 /* 25447 */ "XXPERMDIs\000"
9672 /* 25457 */ "XXSLDWIs\000"
9673 /* 25466 */ "XSNABSDPs\000"
9674 /* 25476 */ "XSCVDPSXDSs\000"
9675 /* 25488 */ "XSCVDPUXDSs\000"
9676 /* 25500 */ "XSCVDPSXWSs\000"
9677 /* 25512 */ "XSCVDPUXWSs\000"
9678 /* 25524 */ "VEXTSB2Ws\000"
9679 /* 25534 */ "VEXTSH2Ws\000"
9680 /* 25544 */ "XXSPLTWs\000"
9681 /* 25553 */ "XXLEQVOnes\000"
9682 /* 25564 */ "BCLalways\000"
9683 /* 25574 */ "gBCAat\000"
9684 /* 25581 */ "gBCLAat\000"
9685 /* 25589 */ "gBCat\000"
9686 /* 25595 */ "gBCLat\000"
9687 /* 25602 */ "MFVRSAVEv\000"
9688 /* 25612 */ "MTVRSAVEv\000"
9689 /* 25622 */ "STXSIBXv\000"
9690 /* 25631 */ "STXSIHXv\000"
9691 /* 25640 */ "LAx\000"
9692 /* 25644 */ "DCBFx\000"
9693 /* 25650 */ "DCBTx\000"
9694 /* 25656 */ "DCBTSTx\000"
9695 /* 25664 */ "XXLXORz\000"
9696 /* 25672 */ "XXLXORdpz\000"
9697 /* 25682 */ "XXLXORspz\000"
9698 /* 25692 */ "FADDrtz\000"
9699};
9700#ifdef __GNUC__
9701#pragma GCC diagnostic pop
9702#endif
9703
9704extern const unsigned PPCInstrNameIndices[] = {
9705 7599U, 9425U, 14074U, 10159U, 8191U, 8172U, 8200U, 8417U,
9706 6862U, 6877U, 6578U, 6565U, 6904U, 15726U, 6352U, 17157U,
9707 6591U, 7595U, 8181U, 6010U, 20431U, 6192U, 16996U, 5373U,
9708 5946U, 5998U, 10910U, 8398U, 16861U, 5539U, 13470U, 6967U,
9709 16850U, 6228U, 12262U, 12249U, 14323U, 16464U, 16676U, 8330U,
9710 8377U, 8350U, 8224U, 6328U, 14288U, 10640U, 20436U, 14579U,
9711 12215U, 6400U, 17240U, 17270U, 9826U, 5046U, 4139U, 8682U,
9712 17530U, 17543U, 9022U, 9029U, 9036U, 9046U, 5346U, 14833U,
9713 14796U, 15102U, 17294U, 6576U, 7597U, 19218U, 6362U, 6377U,
9714 8467U, 16416U, 15246U, 17033U, 15263U, 14680U, 4495U, 15709U,
9715 16872U, 14934U, 17088U, 6487U, 14299U, 5481U, 4469U, 5463U,
9716 16910U, 16891U, 9804U, 14348U, 14367U, 4859U, 4803U, 4833U,
9717 4844U, 4784U, 4814U, 6307U, 6291U, 15777U, 6918U, 6935U,
9718 5062U, 4145U, 5352U, 5301U, 14838U, 14802U, 19005U, 9965U,
9719 18988U, 9948U, 4985U, 4094U, 18923U, 9883U, 9536U, 9483U,
9720 10976U, 10954U, 5409U, 16348U, 5990U, 7006U, 5400U, 16435U,
9721 17011U, 4435U, 15841U, 16827U, 15868U, 17254U, 4487U, 16816U,
9722 16804U, 16986U, 6959U, 17233U, 6891U, 17263U, 8316U, 14442U,
9723 14428U, 8309U, 14435U, 14927U, 8578U, 12007U, 12000U, 12014U,
9724 12021U, 16426U, 10533U, 6038U, 10504U, 5975U, 10525U, 6030U,
9725 10496U, 5967U, 10734U, 10726U, 7070U, 7062U, 16266U, 16256U,
9726 16246U, 16236U, 16286U, 16276U, 19507U, 19517U, 16296U, 16309U,
9727 19534U, 19544U, 16322U, 16335U, 4943U, 4073U, 8609U, 3659U,
9728 4766U, 17494U, 9001U, 18417U, 8052U, 13527U, 826U, 25U,
9729 6952U, 809U, 0U, 13502U, 13534U, 6834U, 17225U, 4459U,
9730 7883U, 7960U, 11893U, 11902U, 16369U, 16382U, 14972U, 9841U,
9731 15743U, 6503U, 9585U, 9595U, 6093U, 6108U, 9472U, 9525U,
9732 9557U, 9571U, 17555U, 17581U, 17567U, 6046U, 6074U, 6059U,
9733 5052U, 8124U, 9917U, 18957U, 9941U, 18981U, 15025U, 5454U,
9734 5444U, 14069U, 16700U, 6170U, 14661U, 14641U, 16728U, 16707U,
9735 14695U, 14726U, 14712U, 15807U, 20664U, 6547U, 20622U, 6529U,
9736 12236U, 10998U, 6315U, 8322U, 15656U, 10003U, 15663U, 9797U,
9737 15648U, 9995U, 9789U, 817U, 7196U, 7094U, 7086U, 17058U,
9738 14627U, 16883U, 16928U, 17098U, 14212U, 6179U, 4552U, 6421U,
9739 6276U, 4971U, 4080U, 8637U, 17501U, 9008U, 3665U, 17066U,
9740 13511U, 14387U, 14403U, 20419U, 6212U, 6451U, 16521U, 10846U,
9741 10947U, 10923U, 10935U, 4950U, 8616U, 4926U, 8592U, 18906U,
9742 9866U, 9504U, 9451U, 5030U, 8666U, 5330U, 14818U, 14780U,
9743 18940U, 9900U, 18964U, 9924U, 19275U, 19282U, 1941U, 1860U,
9744 1903U, 1881U, 1983U, 1839U, 1962U, 1924U, 5562U, 4252U,
9745 5983U, 2198U, 7474U, 22074U, 8022U, 22227U, 7505U, 22107U,
9746 8066U, 22262U, 8295U, 11993U, 15688U, 25644U, 15701U, 16448U,
9747 15137U, 16455U, 15144U, 17210U, 25656U, 17199U, 25650U, 718U,
9748 1331U, 738U, 1351U, 7483U, 22087U, 8045U, 22251U, 7526U,
9749 22140U, 8087U, 22295U, 8031U, 22240U, 7512U, 22118U, 8073U,
9750 22273U, 14449U, 25640U, 19036U, 20397U, 25386U, 7401U, 25154U,
9751 24012U, 25163U, 24025U, 25172U, 24038U, 7519U, 22129U, 8080U,
9752 22284U, 7478U, 22078U, 8026U, 22231U, 5236U, 19164U, 17185U,
9753 20157U, 7514U, 22120U, 8075U, 22275U, 20335U, 7402U, 4386U,
9754 21453U, 15393U, 15399U, 728U, 1341U, 749U, 1362U, 1408U,
9755 10407U, 22450U, 15445U, 20965U, 2171U, 10428U, 22483U, 15453U,
9756 20756U, 21025U, 4337U, 2114U, 10413U, 22460U, 20985U, 10512U,
9757 22587U, 21425U, 6033U, 2206U, 10434U, 22493U, 21044U, 10577U,
9758 22629U, 19212U, 3031U, 21828U, 14958U, 2841U, 7457U, 2325U,
9759 4392U, 2133U, 21463U, 15415U, 2849U, 3512U, 119U, 3496U,
9760 3470U, 3483U, 3459U, 2017U, 8820U, 413U, 8786U, 373U,
9761 14182U, 427U, 8797U, 386U, 14197U, 444U, 24056U, 3189U,
9762 8769U, 2656U, 6199U, 2219U, 10449U, 22516U, 21065U, 10597U,
9763 22661U, 21868U, 15407U, 6481U, 2234U, 10466U, 22541U, 21102U,
9764 10619U, 22695U, 21932U, 10390U, 13455U, 5275U, 2185U, 21035U,
9765 4345U, 2120U, 20995U, 21434U, 21155U, 21229U, 23443U, 22098U,
9766 16640U, 2883U, 16658U, 2902U, 21658U, 1685U, 273U, 1047U,
9767 2508U, 1567U, 155U, 929U, 2396U, 1608U, 196U, 970U,
9768 2435U, 1765U, 353U, 1127U, 2594U, 1649U, 237U, 1011U,
9769 2474U, 1587U, 175U, 949U, 2415U, 1725U, 313U, 1087U,
9770 2546U, 1547U, 135U, 909U, 2364U, 1744U, 332U, 1106U,
9771 2574U, 1628U, 216U, 990U, 2454U, 1705U, 293U, 1067U,
9772 2527U, 1669U, 257U, 1031U, 2493U, 10385U, 3726U, 3348U,
9773 4223U, 4333U, 3371U, 14908U, 2819U, 8546U, 2647U, 8154U,
9774 3636U, 14469U, 8495U, 14902U, 2812U, 25189U, 8539U, 2639U,
9775 25180U, 25213U, 25227U, 21538U, 22390U, 23108U, 23955U, 22401U,
9776 22428U, 23120U, 23966U, 22414U, 23306U, 21358U, 23349U, 21483U,
9777 23547U, 21496U, 8150U, 14464U, 8489U, 25206U, 25221U, 25564U,
9778 25201U, 14896U, 2806U, 8532U, 2632U, 24071U, 9383U, 9305U,
9779 24089U, 9404U, 9341U, 25197U, 20629U, 3177U, 3714U, 25091U,
9780 25255U, 8756U, 3652U, 25077U, 25241U, 14491U, 2758U, 8509U,
9781 25106U, 25270U, 25135U, 25299U, 25121U, 25285U, 25148U, 25312U,
9782 20480U, 3166U, 3709U, 25085U, 25249U, 8751U, 3646U, 25070U,
9783 25234U, 14485U, 2751U, 8502U, 25098U, 25262U, 25128U, 25292U,
9784 25115U, 25279U, 25143U, 25307U, 8146U, 2622U, 12186U, 9362U,
9785 15610U, 4578U, 9322U, 15589U, 9298U, 15581U, 20892U, 3626U,
9786 2029U, 12177U, 9350U, 9290U, 9315U, 14459U, 2734U, 8483U,
9787 12208U, 9373U, 9335U, 15603U, 5257U, 5558U, 7104U, 2306U,
9788 4453U, 18431U, 2987U, 5768U, 2190U, 4912U, 2163U, 5100U,
9789 3853U, 3841U, 2052U, 5534U, 7499U, 3846U, 5212U, 7467U,
9790 18183U, 8008U, 3861U, 2058U, 18424U, 8060U, 5926U, 8978U,
9791 21806U, 18819U, 3003U, 21277U, 23871U, 5939U, 8993U, 21817U,
9792 18832U, 3011U, 21289U, 23882U, 17049U, 20428U, 3151U, 21088U,
9793 21909U, 16500U, 16530U, 5318U, 4350U, 17600U, 5287U, 14615U,
9794 16962U, 14636U, 4624U, 16547U, 16539U, 14768U, 11743U, 4921U,
9795 13602U, 22999U, 21540U, 10356U, 3346U, 6519U, 11752U, 7377U,
9796 17140U, 11781U, 16406U, 11774U, 17172U, 11789U, 20458U, 11798U,
9797 8745U, 11766U, 7407U, 19500U, 14022U, 13797U, 23201U, 23911U,
9798 10752U, 13777U, 17391U, 13957U, 11600U, 22832U, 19527U, 14030U,
9799 13806U, 23213U, 23922U, 13790U, 23097U, 5514U, 13615U, 23020U,
9800 21698U, 17489U, 13996U, 23171U, 23707U, 4905U, 13594U, 22987U,
9801 21527U, 19249U, 14002U, 23181U, 23893U, 5909U, 6087U, 10583U,
9802 22639U, 17356U, 10866U, 22748U, 23653U, 21837U, 10571U, 22619U,
9803 17350U, 10859U, 22737U, 23643U, 21787U, 18797U, 6467U, 10612U,
9804 22684U, 17363U, 10874U, 22760U, 23664U, 21922U, 10896U, 22794U,
9805 17454U, 10882U, 22772U, 23697U, 23849U, 14547U, 20654U, 7113U,
9806 7124U, 8587U, 13755U, 23065U, 22351U, 14753U, 873U, 10041U,
9807 12059U, 10206U, 12319U, 889U, 10059U, 12077U, 10224U, 12337U,
9808 1499U, 12367U, 12451U, 1785U, 89U, 7603U, 1800U, 104U,
9809 7621U, 20468U, 4866U, 3684U, 7371U, 13703U, 23032U, 22054U,
9810 13566U, 22967U, 21301U, 13784U, 23087U, 10378U, 13769U, 23075U,
9811 22439U, 20150U, 14038U, 23225U, 23933U, 5431U, 13608U, 23009U,
9812 21688U, 13308U, 22935U, 7645U, 13719U, 23043U, 22162U, 7847U,
9813 13726U, 23054U, 22207U, 15773U, 8410U, 17146U, 1147U, 17179U,
9814 1153U, 17218U, 1168U, 17205U, 1161U, 4068U, 13572U, 22977U,
9815 21360U, 4373U, 13586U, 6813U, 13695U, 19254U, 14008U, 6756U,
9816 7555U, 13710U, 13687U, 19270U, 14016U, 23191U, 23902U, 4569U,
9817 2148U, 16507U, 2868U, 25329U, 25356U, 14965U, 4919U, 15278U,
9818 6665U, 7858U, 5162U, 6763U, 7935U, 5177U, 13623U, 16553U,
9819 16748U, 6731U, 7892U, 20484U, 20566U, 6788U, 7969U, 20501U,
9820 20594U, 17487U, 8585U, 14979U, 6827U, 4066U, 13659U, 16581U,
9821 16776U, 15004U, 5015U, 5107U, 6673U, 7866U, 6771U, 7943U,
9822 13632U, 16562U, 16757U, 6739U, 7900U, 20575U, 6796U, 7977U,
9823 20603U, 17515U, 8651U, 14987U, 6841U, 4124U, 13668U, 16590U,
9824 16785U, 760U, 1373U, 778U, 1391U, 25372U, 17596U, 2971U,
9825 21240U, 23725U, 15019U, 18139U, 17758U, 17880U, 17819U, 17941U,
9826 18053U, 5324U, 4357U, 13651U, 15906U, 17408U, 15915U, 17417U,
9827 18541U, 18817U, 16071U, 17452U, 17606U, 3957U, 7221U, 15011U,
9828 5022U, 6681U, 7874U, 6779U, 7951U, 13641U, 16571U, 16766U,
9829 6747U, 7908U, 20584U, 6804U, 7985U, 20612U, 17522U, 8658U,
9830 14995U, 6848U, 4131U, 13677U, 16599U, 16794U, 5078U, 19138U,
9831 7017U, 19289U, 18060U, 20292U, 16176U, 20085U, 16199U, 20110U,
9832 16212U, 20124U, 6143U, 19232U, 15673U, 20069U, 17383U, 20226U,
9833 16188U, 20098U, 16225U, 20138U, 7573U, 10709U, 10699U, 7583U,
9834 3234U, 9677U, 3278U, 9721U, 3312U, 9755U, 6605U, 3376U,
9835 17710U, 18218U, 7707U, 3538U, 17770U, 18266U, 6696U, 3415U,
9836 17734U, 18242U, 17892U, 18338U, 7742U, 3577U, 17831U, 18302U,
9837 17953U, 18374U, 3246U, 9689U, 3290U, 9733U, 3324U, 9767U,
9838 6623U, 3396U, 17722U, 18230U, 7725U, 3558U, 17807U, 18290U,
9839 6714U, 3435U, 17746U, 18254U, 17929U, 18362U, 7769U, 3607U,
9840 17868U, 18326U, 17990U, 18398U, 3678U, 6614U, 3386U, 7716U,
9841 3548U, 6705U, 3425U, 7751U, 3587U, 17795U, 18278U, 17917U,
9842 18350U, 7760U, 3597U, 17856U, 18314U, 17978U, 18386U, 6632U,
9843 3406U, 3258U, 9701U, 7734U, 3568U, 3302U, 9745U, 6723U,
9844 3445U, 3268U, 9711U, 7778U, 3617U, 3336U, 9779U, 5294U,
9845 6856U, 14621U, 14741U, 4630U, 18189U, 8015U, 18066U, 8283U,
9846 18195U, 8038U, 7563U, 7917U, 15431U, 17375U, 16007U, 17440U,
9847 5092U, 19145U, 7023U, 19296U, 18073U, 20299U, 6150U, 19240U,
9848 10667U, 19712U, 6473U, 19261U, 10902U, 19721U, 17782U, 17904U,
9849 17843U, 17965U, 18095U, 18103U, 14774U, 3959U, 2065U, 1177U,
9850 20974U, 21335U, 7223U, 2311U, 1190U, 21144U, 22005U, 18580U,
9851 7661U, 1203U, 20930U, 22172U, 701U, 1231U, 20949U, 23813U,
9852 10687U, 5657U, 21727U, 15756U, 23515U, 4938U, 15109U, 23358U,
9853 21549U, 25692U, 5150U, 15130U, 23391U, 17327U, 15931U, 23557U,
9854 23621U, 21599U, 5507U, 15681U, 5860U, 15978U, 5386U, 21666U,
9855 15634U, 23483U, 5171U, 17334U, 20671U, 23977U, 23632U, 20494U,
9856 23944U, 21609U, 18147U, 17433U, 20679U, 23989U, 23686U, 20687U,
9857 24001U, 23764U, 17496U, 16001U, 23580U, 23716U, 5984U, 5002U,
9858 15115U, 23368U, 21558U, 14543U, 23282U, 4111U, 15087U, 23326U,
9859 21378U, 8604U, 15622U, 23463U, 22360U, 5663U, 21737U, 15762U,
9860 23525U, 5125U, 21579U, 15307U, 23433U, 5008U, 15122U, 23379U,
9861 21568U, 4117U, 15094U, 23337U, 21388U, 6272U, 15232U, 23402U,
9862 21889U, 5250U, 21647U, 15628U, 23473U, 5394U, 21678U, 15642U,
9863 23495U, 5528U, 21709U, 15695U, 23505U, 5914U, 21796U, 16159U,
9864 23590U, 13313U, 22944U, 6344U, 15237U, 23411U, 21897U, 5199U,
9865 21619U, 15439U, 23453U, 17060U, 15924U, 23536U, 23600U, 4075U,
9866 15081U, 23316U, 21369U, 17537U, 17081U, 14238U, 476U, 19360U,
9867 19411U, 8262U, 19345U, 19396U, 19376U, 14225U, 461U, 8244U,
9868 8116U, 2613U, 11984U, 2681U, 17150U, 2921U, 13447U, 2691U,
9869 5156U, 7382U, 11759U, 4447U, 13739U, 16411U, 15461U, 7413U,
9870 8278U, 2626U, 4540U, 3627U, 2030U, 19834U, 8699U, 19730U,
9871 20464U, 3161U, 19479U, 17460U, 2953U, 20254U, 3106U, 20372U,
9872 3133U, 15557U, 20865U, 668U, 5189U, 19840U, 8706U, 16165U,
9873 19864U, 19452U, 17341U, 20203U, 19175U, 15509U, 20811U, 8808U,
9874 399U, 24050U, 3358U, 16968U, 7926U, 8762U, 5115U, 19743U,
9875 17301U, 20190U, 19153U, 15492U, 20792U, 19029U, 20390U, 15291U,
9876 17397U, 20235U, 20058U, 15532U, 20837U, 3455U, 2012U, 19846U,
9877 8713U, 17284U, 2929U, 20172U, 3078U, 18901U, 3019U, 15468U,
9878 20765U, 613U, 19877U, 3064U, 19758U, 20532U, 3172U, 19486U,
9879 17465U, 2959U, 20260U, 3113U, 20385U, 3139U, 15565U, 20874U,
9880 679U, 7642U, 2334U, 15421U, 2856U, 18201U, 13742U, 19852U,
9881 8720U, 10548U, 8094U, 19055U, 19304U, 20307U, 8573U, 14887U,
9882 20272U, 8734U, 3690U, 19858U, 8727U, 16395U, 20178U, 19050U,
9883 15476U, 20774U, 624U, 710U, 514U, 19907U, 3071U, 19771U,
9884 20697U, 3184U, 19493U, 17470U, 2965U, 20266U, 3120U, 20414U,
9885 3145U, 15573U, 20883U, 690U, 24064U, 8778U, 5746U, 19194U,
9886 20364U, 20377U, 19042U, 20403U, 13342U, 19806U, 17618U, 18869U,
9887 18839U, 20045U, 18886U, 13733U, 8688U, 8454U, 13490U, 8517U,
9888 8422U, 19821U, 19076U, 19179U, 19325U, 8554U, 8439U, 20341U,
9889 18854U, 20078U, 20281U, 5137U, 17312U, 5192U, 2176U, 14046U,
9890 6640U, 15295U, 20032U, 5959U, 14120U, 2717U, 14915U, 2827U,
9891 14102U, 15285U, 10369U, 7802U, 6023U, 10361U, 7793U, 8567U,
9892 23424U, 14475U, 2739U, 14870U, 6645U, 2255U, 14552U, 14853U,
9893 2788U, 14865U, 9981U, 3977U, 2078U, 14132U, 5645U, 6433U,
9894 25602U, 20722U, 14148U, 5631U, 5218U, 20706U, 5671U, 18479U,
9895 5815U, 18672U, 4532U, 4546U, 6659U, 2271U, 14921U, 2834U,
9896 25318U, 25346U, 14114U, 34U, 82U, 6690U, 7548U, 22151U,
9897 20908U, 21962U, 20901U, 14480U, 2745U, 14876U, 5624U, 6652U,
9898 2263U, 14558U, 14859U, 2795U, 14882U, 9988U, 14140U, 5651U,
9899 6442U, 25612U, 3702U, 20729U, 14155U, 8851U, 7670U, 5638U,
9900 5084U, 8916U, 9066U, 9224U, 3694U, 9623U, 16014U, 20714U,
9901 5144U, 17320U, 23610U, 21589U, 18133U, 17426U, 23675U, 23754U,
9902 5206U, 10541U, 22608U, 21629U, 7651U, 2331U, 18177U, 10889U,
9903 22783U, 23774U, 14509U, 14498U, 2766U, 5282U, 2184U, 21034U,
9904 21657U, 10919U, 6830U, 2301U, 10490U, 22577U, 21135U, 10662U,
9905 22728U, 21972U, 12182U, 1815U, 1827U, 14611U, 2778U, 21211U,
9906 23290U, 14599U, 2779U, 21212U, 4620U, 2158U, 21016U, 21510U,
9907 7854U, 2352U, 15426U, 2862U, 23291U, 7456U, 2324U, 24146U,
9908 25058U, 24266U, 5522U, 5799U, 3642U, 2034U, 24115U, 24194U,
9909 20463U, 3160U, 24418U, 24719U, 24163U, 24632U, 24977U, 24347U,
9910 5214U, 24494U, 24811U, 24229U, 5114U, 24475U, 24788U, 24214U,
9911 15290U, 24585U, 24920U, 24310U, 3454U, 2011U, 24368U, 24659U,
9912 24107U, 24448U, 24755U, 24187U, 20531U, 3171U, 24428U, 24731U,
9913 24171U, 24641U, 24988U, 24354U, 7657U, 2338U, 3689U, 2039U,
9914 24378U, 24671U, 24122U, 24457U, 24766U, 24200U, 20701U, 3183U,
9915 24438U, 24743U, 24179U, 24650U, 24999U, 24361U, 5745U, 24502U,
9916 24821U, 24235U, 13341U, 24541U, 24868U, 24274U, 17617U, 13489U,
9917 24564U, 24895U, 24293U, 24604U, 24943U, 24325U, 871U, 10039U,
9918 12057U, 10204U, 12317U, 887U, 10057U, 12075U, 10222U, 12335U,
9919 1497U, 12365U, 12449U, 834U, 10010U, 12028U, 10175U, 12274U,
9920 17646U, 10100U, 12118U, 10297U, 12481U, 847U, 10025U, 12043U,
9921 10190U, 12289U, 17660U, 10116U, 12134U, 10313U, 12497U, 14249U,
9922 10074U, 12092U, 10249U, 12394U, 18435U, 10131U, 12149U, 10328U,
9923 12555U, 14260U, 10087U, 12105U, 10262U, 12407U, 18447U, 10145U,
9924 12163U, 10342U, 12569U, 859U, 12303U, 14945U, 12420U, 18464U,
9925 12583U, 17673U, 12512U, 2723U, 12381U, 17698U, 12541U, 1486U,
9926 12352U, 12435U, 17686U, 12527U, 12466U, 3990U, 2084U, 5776U,
9927 18616U, 16941U, 16950U, 489U, 1243U, 542U, 1289U, 497U,
9928 1251U, 521U, 1268U, 4007U, 2093U, 24388U, 24683U, 24130U,
9929 24466U, 24777U, 24207U, 5793U, 24523U, 24846U, 24252U, 5119U,
9930 24484U, 24799U, 24221U, 15301U, 24594U, 24931U, 24317U, 7261U,
9931 2318U, 24398U, 24695U, 24138U, 24532U, 24857U, 24259U, 18650U,
9932 2997U, 24408U, 24707U, 24155U, 24623U, 24966U, 24340U, 5751U,
9933 24512U, 24833U, 24243U, 13348U, 24552U, 24881U, 24283U, 17622U,
9934 13495U, 24574U, 24907U, 24301U, 24613U, 24954U, 24332U, 10675U,
9935 4311U, 14162U, 16614U, 14521U, 12872U, 5577U, 4263U, 4287U,
9936 7429U, 7462U, 3734U, 7544U, 5157U, 7434U, 8159U, 22318U,
9937 14108U, 23249U, 4398U, 8165U, 593U, 1218U, 20916U, 22328U,
9938 14125U, 603U, 23259U, 21473U, 7686U, 22185U, 7693U, 2343U,
9939 21165U, 22196U, 9193U, 2666U, 21188U, 22369U, 9208U, 2674U,
9940 21200U, 22380U, 4012U, 4719U, 17475U, 1522U, 1440U, 2278U,
9941 1463U, 2383U, 6241U, 1413U, 4636U, 4588U, 4692U, 4663U,
9942 1536U, 1453U, 2291U, 1476U, 2564U, 6255U, 1428U, 4651U,
9943 4604U, 4707U, 4679U, 3972U, 2072U, 4226U, 2107U, 14095U,
9944 2709U, 9179U, 4219U, 2099U, 14087U, 2700U, 5437U, 25017U,
9945 21847U, 3526U, 6158U, 6820U, 6123U, 17479U, 6337U, 4516U,
9946 5232U, 21639U, 18197U, 2982U, 21259U, 23784U, 20694U, 20411U,
9947 18643U, 20356U, 4323U, 14173U, 16628U, 14533U, 12885U, 5594U,
9948 4276U, 4300U, 5609U, 4878U, 7450U, 584U, 22064U, 21518U,
9949 18014U, 2976U, 21249U, 7994U, 2357U, 21177U, 22217U, 23733U,
9950 5627U, 21719U, 18460U, 2992U, 21268U, 23792U, 4008U, 2094U,
9951 19445U, 19096U, 19736U, 17289U, 2935U, 20184U, 3085U, 19091U,
9952 3025U, 15484U, 20783U, 635U, 5794U, 16170U, 19870U, 19458U,
9953 19102U, 17345U, 20208U, 19207U, 15516U, 20819U, 5120U, 19750U,
9954 17306U, 20196U, 19158U, 15500U, 20801U, 20320U, 15302U, 17402U,
9955 20241U, 20063U, 15540U, 20846U, 7262U, 2319U, 19883U, 19465U,
9956 19108U, 19764U, 17370U, 2941U, 20220U, 3092U, 19340U, 3038U,
9957 15524U, 20828U, 646U, 18205U, 12244U, 13864U, 19114U, 10559U,
9958 8099U, 19061U, 19310U, 20313U, 20276U, 8739U, 18646U, 2998U,
9959 16400U, 19913U, 19472U, 19120U, 19777U, 17447U, 2947U, 20248U,
9960 3099U, 20359U, 3127U, 15549U, 20856U, 657U, 5752U, 19200U,
9961 19068U, 25622U, 19317U, 25631U, 20327U, 13349U, 19813U, 17623U,
9962 18877U, 18846U, 18893U, 8693U, 8460U, 13496U, 8524U, 8430U,
9963 19827U, 19083U, 19186U, 19332U, 8560U, 8446U, 20348U, 18861U,
9964 20286U, 6524U, 2249U, 10483U, 22566U, 21125U, 4380U, 2126U,
9965 10420U, 22471U, 21005U, 10518U, 22597U, 21443U, 6137U, 2212U,
9966 10441U, 22504U, 21054U, 10590U, 22650U, 21858U, 4404U, 2140U,
9967 6205U, 2226U, 10457U, 22528U, 21076U, 10604U, 22672U, 21878U,
9968 10634U, 22718U, 15955U, 23569U, 6496U, 2241U, 10474U, 22553U,
9969 21113U, 10626U, 22706U, 21942U, 21953U, 4519U, 9U, 17042U,
9970 4364U, 7419U, 4722U, 7440U, 3805U, 2045U, 3351U, 2003U,
9971 14892U, 2802U, 9859U, 16489U, 8109U, 16478U, 25025U, 3198U,
9972 25036U, 3210U, 25047U, 3222U, 5765U, 7533U, 5368U, 3532U,
9973 6164U, 8217U, 19604U, 19021U, 5186U, 7639U, 6266U, 795U,
9974 20039U, 902U, 4758U, 4524U, 6461U, 802U, 19427U, 3044U,
9975 19436U, 3054U, 10930U, 16977U, 9140U, 14883U, 18604U, 8105U,
9976 12194U, 14051U, 4019U, 7266U, 18678U, 13895U, 18663U, 13923U,
9977 9268U, 11837U, 15048U, 15351U, 16039U, 8878U, 15073U, 8943U,
9978 9112U, 15376U, 9251U, 9650U, 16063U, 5325U, 4358U, 3901U,
9979 7157U, 18501U, 4035U, 7282U, 18702U, 5256U, 13761U, 20052U,
9980 66U, 5099U, 20214U, 74U, 14280U, 17128U, 3811U, 3867U,
9981 4207U, 5920U, 8971U, 7359U, 3756U, 18811U, 11805U, 22856U,
9982 11911U, 22881U, 4057U, 21345U, 5867U, 21761U, 7304U, 22015U,
9983 13971U, 23145U, 18732U, 23823U, 11852U, 22868U, 11920U, 22894U,
9984 3948U, 21322U, 5722U, 21748U, 7212U, 21992U, 13848U, 23132U,
9985 18571U, 23800U, 4172U, 21399U, 5876U, 21774U, 7324U, 22028U,
9986 13980U, 23158U, 18764U, 23836U, 3774U, 21310U, 7030U, 21980U,
9987 18087U, 23742U, 4198U, 21412U, 7350U, 22041U, 18802U, 23858U,
9988 13841U, 13964U, 3740U, 4889U, 6998U, 18019U, 16145U, 48U,
9989 16152U, 57U, 4213U, 5933U, 8986U, 7365U, 3765U, 18826U,
9990 5685U, 13833U, 18493U, 5829U, 13949U, 18694U, 5731U, 13857U,
9991 18586U, 5885U, 13989U, 18773U, 17607U, 8832U, 8906U, 9056U,
9992 9214U, 9613U, 11867U, 19631U, 19965U, 19620U, 19954U, 19650U,
9993 19984U, 19670U, 20004U, 8859U, 5758U, 8924U, 9083U, 9232U,
9994 4161U, 7313U, 18741U, 9631U, 4731U, 25409U, 17628U, 25524U,
9995 13551U, 4740U, 25419U, 17637U, 25534U, 4749U, 25429U, 19570U,
9996 19898U, 19595U, 19936U, 19689U, 20023U, 4883U, 3836U, 19562U,
9997 19890U, 19611U, 19945U, 5708U, 19579U, 19920U, 3998U, 5784U,
9998 7252U, 18624U, 19587U, 19928U, 19641U, 19975U, 18557U, 19681U,
9999 20015U, 19661U, 19995U, 11844U, 11829U, 11929U, 3965U, 5738U,
10000 7229U, 18593U, 4181U, 5892U, 7333U, 18780U, 15330U, 15340U,
10001 11886U, 3933U, 5701U, 7189U, 18550U, 4042U, 5845U, 7289U,
10002 18717U, 9102U, 5670U, 13826U, 18478U, 5814U, 13932U, 18671U,
10003 18080U, 3782U, 7038U, 18118U, 3798U, 7045U, 18162U, 18410U,
10004 5805U, 8842U, 9074U, 15359U, 8886U, 8951U, 9120U, 15384U,
10005 13877U, 13903U, 13939U, 13868U, 3879U, 5677U, 7135U, 18485U,
10006 4027U, 5821U, 7274U, 18686U, 5693U, 18516U, 5837U, 18709U,
10007 5205U, 3940U, 5714U, 7204U, 18563U, 4049U, 5852U, 7296U,
10008 18724U, 9658U, 5295U, 14271U, 17115U, 5131U, 18112U, 11813U,
10009 14622U, 14742U, 4631U, 5521U, 9277U, 14564U, 14759U, 5798U,
10010 19792U, 15769U, 15939U, 15825U, 15962U, 15833U, 15985U, 9435U,
10011 15947U, 9443U, 15970U, 9605U, 15993U, 3828U, 5264U, 7078U,
10012 18210U, 3989U, 5775U, 7243U, 18615U, 4897U, 13578U, 18027U,
10013 11861U, 9149U, 9853U, 11954U, 20536U, 3818U, 5226U, 7679U,
10014 9186U, 7052U, 13745U, 7700U, 9200U, 18190U, 7786U, 9207U,
10015 11876U, 19706U, 8284U, 4773U, 18002U, 8574U, 3823U, 5231U,
10016 7387U, 7812U, 7057U, 10721U, 13750U, 17550U, 18196U, 3982U,
10017 25401U, 7236U, 25439U, 3916U, 7172U, 18524U, 18600U, 14888U,
10018 3728U, 4877U, 6992U, 13560U, 18013U, 3874U, 5633U, 7394U,
10019 7108U, 10854U, 13821U, 17612U, 18459U, 8141U, 22306U, 14061U,
10020 23237U, 8301U, 22339U, 14420U, 23270U, 13887U, 18655U, 13914U,
10021 9259U, 11822U, 15040U, 15322U, 16031U, 8870U, 15065U, 8935U,
10022 9094U, 15368U, 9243U, 9642U, 16055U, 16022U, 15031U, 15313U,
10023 15056U, 16047U, 19784U, 3908U, 7164U, 18508U, 19798U, 3925U,
10024 7181U, 18533U, 14775U, 41U, 3720U, 6984U, 15219U, 3887U,
10025 7143U, 16609U, 17U, 6131U, 7537U, 14749U, 2783U, 21220U,
10026 7853U, 2351U, 15425U, 2861U, 23298U, 11584U, 12828U, 11144U,
10027 12673U, 10809U, 13016U, 11546U, 12791U, 11517U, 12771U, 11200U,
10028 12699U, 11606U, 12836U, 11454U, 12744U, 11664U, 12855U, 11418U,
10029 12734U, 11936U, 12753U, 13253U, 10287U, 15153U, 25476U, 16079U,
10030 25500U, 15186U, 25488U, 16112U, 25512U, 11463U, 11472U, 10742U,
10031 20511U, 20634U, 20736U, 20521U, 20644U, 20746U, 12681U, 11481U,
10032 10239U, 12801U, 11160U, 13032U, 12690U, 12810U, 11180U, 13052U,
10033 11673U, 12864U, 10837U, 13394U, 11499U, 12762U, 11070U, 12960U,
10034 11398U, 13215U, 12664U, 10799U, 11135U, 12645U, 11727U, 11309U,
10035 11126U, 12636U, 11438U, 11300U, 11028U, 12918U, 11356U, 13173U,
10036 12609U, 10769U, 11318U, 12726U, 10818U, 13135U, 11566U, 25466U,
10037 12819U, 11256U, 12709U, 11048U, 12938U, 11376U, 13193U, 12654U,
10038 10788U, 11006U, 12896U, 11334U, 13151U, 12599U, 10758U, 7819U,
10039 4411U, 9155U, 11960U, 20542U, 11220U, 13082U, 7833U, 19554U,
10040 13543U, 13318U, 11234U, 13096U, 11626U, 12846U, 10827U, 13366U,
10041 11090U, 12618U, 10779U, 12980U, 11681U, 11635U, 11106U, 12626U,
10042 12996U, 11528U, 12782U, 11272U, 12717U, 11592U, 13333U, 11152U,
10043 13024U, 836U, 10012U, 12030U, 10177U, 12276U, 17648U, 10102U,
10044 12120U, 10299U, 12483U, 11556U, 22818U, 13298U, 22921U, 11210U,
10045 22804U, 13072U, 22907U, 11616U, 22842U, 13356U, 22953U, 11428U,
10046 13235U, 10275U, 13262U, 15164U, 16090U, 15197U, 16123U, 13271U,
10047 1511U, 11490U, 11945U, 15175U, 16101U, 15208U, 16134U, 11170U,
10048 13042U, 11707U, 13419U, 11190U, 13062U, 11717U, 13429U, 11699U,
10049 13411U, 849U, 10027U, 12045U, 10192U, 12291U, 17662U, 10118U,
10050 12136U, 10315U, 12499U, 14251U, 10076U, 12094U, 10251U, 12396U,
10051 18437U, 10133U, 12151U, 10330U, 12557U, 14262U, 10089U, 12107U,
10052 10264U, 12409U, 18449U, 10147U, 12165U, 10344U, 12571U, 861U,
10053 12305U, 14947U, 12422U, 18466U, 12585U, 17675U, 12514U, 2725U,
10054 12383U, 17700U, 12543U, 1488U, 12354U, 12437U, 17688U, 12529U,
10055 12468U, 11508U, 13280U, 11080U, 12970U, 11408U, 13225U, 11735U,
10056 13439U, 11446U, 13245U, 11038U, 12928U, 11366U, 13183U, 11326U,
10057 13143U, 11575U, 13324U, 11264U, 13118U, 11059U, 12949U, 11387U,
10058 13204U, 11017U, 12907U, 11345U, 13162U, 7826U, 4419U, 9163U,
10059 11968U, 20550U, 11227U, 13089U, 7840U, 4427U, 9171U, 11976U,
10060 20558U, 11245U, 13107U, 11655U, 13385U, 11098U, 12988U, 11690U,
10061 13402U, 3748U, 11645U, 13375U, 11116U, 13006U, 11537U, 13289U,
10062 11281U, 13126U, 4188U, 5899U, 7340U, 18787U, 5556U, 7102U,
10063 13815U, 18429U, 8134U, 18752U, 8895U, 8960U, 9129U, 9666U,
10064 18633U, 5272U, 4342U, 17593U, 25553U, 5279U, 14608U, 14602U,
10065 4617U, 25010U, 14746U, 25672U, 25682U, 25664U, 4236U, 18035U,
10066 18125U, 18169U, 4244U, 18044U, 9283U, 7490U, 25447U, 14571U,
10067 19698U, 8289U, 20470U, 8000U, 25457U, 19126U, 3789U, 11290U,
10068 18153U, 18607U, 25544U, 4232U, 3366U, 25574U, 14901U, 8538U,
10069 8149U, 3630U, 25581U, 14463U, 8488U, 25595U, 25589U,
10070};
10071
10072extern const uint8_t PPCInstrDeprecationFeatures[] = {
10073 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10074 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10075 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10076 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10077 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10078 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10079 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10080 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10081 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10082 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10083 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10084 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10085 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10086 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10087 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10088 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10089 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10090 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10091 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10092 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10093 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10094 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10095 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10096 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10097 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10098 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10099 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10100 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10101 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10102 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10103 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10104 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10105 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10106 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10107 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10108 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10109 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10110 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10111 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10112 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10113 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10114 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10115 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10116 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10117 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10118 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10119 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10120 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10121 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10122 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10123 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10124 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10125 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10126 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10127 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10128 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10129 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10130 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10131 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10132 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10133 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10134 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10135 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10136 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10137 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10138 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10139 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10140 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10141 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10142 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10143 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10144 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10145 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10146 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10147 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10148 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10149 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10150 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10151 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10152 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10153 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10154 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10155 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10156 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10157 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10158 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10159 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10160 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10161 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10162 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10163 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10164 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10165 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10166 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10167 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10168 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10169 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10170 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10171 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10172 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10173 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10174 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10175 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10176 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10177 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10178 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10179 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10180 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10181 uint8_t(-1), uint8_t(-1), uint8_t(-1), PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST,
10182 PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, uint8_t(-1), uint8_t(-1), uint8_t(-1),
10183 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10184 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10185 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10186 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10187 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10188 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10189 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10190 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10191 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10192 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10193 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10194 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10195 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10196 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10197 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10198 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10199 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10200 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10201 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10202 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10203 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10204 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10205 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10206 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10207 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10208 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10209 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10210 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10211 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10212 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10213 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10214 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10215 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10216 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10217 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10218 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10219 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10220 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10221 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10222 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10223 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10224 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10225 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10226 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10227 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10228 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10229 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10230 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10231 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10232 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10233 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10234 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10235 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10236 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10237 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10238 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10239 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10240 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10241 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10242 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10243 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10244 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10245 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10246 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10247 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10248 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10249 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10250 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10251 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10252 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10253 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10254 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10255 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10256 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10257 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10258 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10259 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10260 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10261 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10262 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10263 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10264 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10265 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10266 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10267 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10268 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10269 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10270 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10271 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10272 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10273 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10274 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10275 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10276 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10277 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10278 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10279 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10280 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10281 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10282 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10283 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10284 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10285 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10286 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10287 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10288 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10289 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10290 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10291 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10292 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10293 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10294 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10295 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10296 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10297 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10298 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10299 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10300 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10301 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10302 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10303 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10304 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10305 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10306 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10307 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10308 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10309 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10310 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10311 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10312 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10313 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10314 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10315 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10316 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10317 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10318 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10319 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10320 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10321 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10322 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10323 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10324 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10325 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10326 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10327 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10328 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10329 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10330 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10331 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10332 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10333 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10334 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10335 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10336 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10337 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10338 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10339 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10340 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10341 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10342 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10343 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10344 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10345 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10346 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10347 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10348 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10349 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10350 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10351 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10352 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10353 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10354 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10355 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10356 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10357 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10358 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10359 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10360 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10361 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10362 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10363 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10364 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10365 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10366 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10367 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10368 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10369 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10370 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10371 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10372 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10373 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10374 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10375 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10376 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10377 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10378 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10379 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10380 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10381 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10382 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10383 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10384 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10385 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10386 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10387 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10388 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10389 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10390 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10391 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10392 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10393 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10394 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10395 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10396 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10397 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10398 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10399 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10400 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10401 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10402 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10403 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10404 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10405 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10406 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10407 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10408 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10409 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10410 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10411 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10412 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10413 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10414 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10415 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10416 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10417 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10418 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10419 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10420 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10421 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10422 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10423 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10424 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10425 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10426 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10427 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10428 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10429 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10430 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10431 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10432 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10433 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10434 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10435 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10436 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10437 uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1),
10438};
10439
10440static inline void InitPPCMCInstrInfo(MCInstrInfo *II) {
10441 II->InitMCInstrInfo(PPCDescs.Insts, PPCInstrNameIndices, PPCInstrNameData, PPCInstrDeprecationFeatures, nullptr, 2919);
10442}
10443
10444} // end namespace llvm
10445#endif // GET_INSTRINFO_MC_DESC
10446
10447#ifdef GET_INSTRINFO_HEADER
10448#undef GET_INSTRINFO_HEADER
10449namespace llvm {
10450struct PPCGenInstrInfo : public TargetInstrInfo {
10451 explicit PPCGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
10452 ~PPCGenInstrInfo() override = default;
10453
10454};
10455} // end namespace llvm
10456#endif // GET_INSTRINFO_HEADER
10457
10458#ifdef GET_INSTRINFO_HELPER_DECLS
10459#undef GET_INSTRINFO_HELPER_DECLS
10460
10461
10462#endif // GET_INSTRINFO_HELPER_DECLS
10463
10464#ifdef GET_INSTRINFO_HELPERS
10465#undef GET_INSTRINFO_HELPERS
10466
10467#endif // GET_INSTRINFO_HELPERS
10468
10469#ifdef GET_INSTRINFO_CTOR_DTOR
10470#undef GET_INSTRINFO_CTOR_DTOR
10471namespace llvm {
10472extern const PPCInstrTable PPCDescs;
10473extern const unsigned PPCInstrNameIndices[];
10474extern const char PPCInstrNameData[];
10475extern const uint8_t PPCInstrDeprecationFeatures[];
10476PPCGenInstrInfo::PPCGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
10477 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
10478 InitMCInstrInfo(PPCDescs.Insts, PPCInstrNameIndices, PPCInstrNameData, PPCInstrDeprecationFeatures, nullptr, 2919);
10479}
10480} // end namespace llvm
10481#endif // GET_INSTRINFO_CTOR_DTOR
10482
10483#ifdef GET_INSTRINFO_MC_HELPER_DECLS
10484#undef GET_INSTRINFO_MC_HELPER_DECLS
10485
10486namespace llvm {
10487class MCInst;
10488class FeatureBitset;
10489
10490namespace PPC_MC {
10491
10492void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
10493
10494} // end namespace PPC_MC
10495} // end namespace llvm
10496
10497#endif // GET_INSTRINFO_MC_HELPER_DECLS
10498
10499#ifdef GET_INSTRINFO_MC_HELPERS
10500#undef GET_INSTRINFO_MC_HELPERS
10501
10502namespace llvm::PPC_MC {
10503} // end namespace llvm::PPC_MC
10504#endif // GET_GENISTRINFO_MC_HELPERS
10505
10506#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
10507 defined(GET_AVAILABLE_OPCODE_CHECKER)
10508#define GET_COMPUTE_FEATURES
10509#endif
10510#ifdef GET_COMPUTE_FEATURES
10511#undef GET_COMPUTE_FEATURES
10512namespace llvm::PPC_MC {
10513// Bits for subtarget features that participate in instruction matching.
10514enum SubtargetFeatureBits : uint8_t {
10515 Feature_ModernAsBit = 0,
10516};
10517
10518inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
10519 FeatureBitset Features;
10520 if (!FB[PPC::AIXOS] || FB[PPC::FeatureModernAIXAs])
10521 Features.set(Feature_ModernAsBit);
10522 return Features;
10523}
10524
10525inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
10526 enum : uint8_t {
10527 CEFBS_None,
10528 };
10529
10530 static constexpr FeatureBitset FeatureBitsets[] = {
10531 {}, // CEFBS_None
10532 };
10533 static constexpr uint8_t RequiredFeaturesRefs[] = {
10534 CEFBS_None, // PHI = 0
10535 CEFBS_None, // INLINEASM = 1
10536 CEFBS_None, // INLINEASM_BR = 2
10537 CEFBS_None, // CFI_INSTRUCTION = 3
10538 CEFBS_None, // EH_LABEL = 4
10539 CEFBS_None, // GC_LABEL = 5
10540 CEFBS_None, // ANNOTATION_LABEL = 6
10541 CEFBS_None, // KILL = 7
10542 CEFBS_None, // EXTRACT_SUBREG = 8
10543 CEFBS_None, // INSERT_SUBREG = 9
10544 CEFBS_None, // IMPLICIT_DEF = 10
10545 CEFBS_None, // INIT_UNDEF = 11
10546 CEFBS_None, // SUBREG_TO_REG = 12
10547 CEFBS_None, // COPY_TO_REGCLASS = 13
10548 CEFBS_None, // DBG_VALUE = 14
10549 CEFBS_None, // DBG_VALUE_LIST = 15
10550 CEFBS_None, // DBG_INSTR_REF = 16
10551 CEFBS_None, // DBG_PHI = 17
10552 CEFBS_None, // DBG_LABEL = 18
10553 CEFBS_None, // REG_SEQUENCE = 19
10554 CEFBS_None, // COPY = 20
10555 CEFBS_None, // BUNDLE = 21
10556 CEFBS_None, // LIFETIME_START = 22
10557 CEFBS_None, // LIFETIME_END = 23
10558 CEFBS_None, // PSEUDO_PROBE = 24
10559 CEFBS_None, // ARITH_FENCE = 25
10560 CEFBS_None, // STACKMAP = 26
10561 CEFBS_None, // FENTRY_CALL = 27
10562 CEFBS_None, // PATCHPOINT = 28
10563 CEFBS_None, // LOAD_STACK_GUARD = 29
10564 CEFBS_None, // PREALLOCATED_SETUP = 30
10565 CEFBS_None, // PREALLOCATED_ARG = 31
10566 CEFBS_None, // STATEPOINT = 32
10567 CEFBS_None, // LOCAL_ESCAPE = 33
10568 CEFBS_None, // FAULTING_OP = 34
10569 CEFBS_None, // PATCHABLE_OP = 35
10570 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
10571 CEFBS_None, // PATCHABLE_RET = 37
10572 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
10573 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
10574 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
10575 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
10576 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
10577 CEFBS_None, // FAKE_USE = 43
10578 CEFBS_None, // MEMBARRIER = 44
10579 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
10580 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
10581 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
10582 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
10583 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
10584 CEFBS_None, // G_ASSERT_SEXT = 50
10585 CEFBS_None, // G_ASSERT_ZEXT = 51
10586 CEFBS_None, // G_ASSERT_ALIGN = 52
10587 CEFBS_None, // G_ADD = 53
10588 CEFBS_None, // G_SUB = 54
10589 CEFBS_None, // G_MUL = 55
10590 CEFBS_None, // G_SDIV = 56
10591 CEFBS_None, // G_UDIV = 57
10592 CEFBS_None, // G_SREM = 58
10593 CEFBS_None, // G_UREM = 59
10594 CEFBS_None, // G_SDIVREM = 60
10595 CEFBS_None, // G_UDIVREM = 61
10596 CEFBS_None, // G_AND = 62
10597 CEFBS_None, // G_OR = 63
10598 CEFBS_None, // G_XOR = 64
10599 CEFBS_None, // G_ABDS = 65
10600 CEFBS_None, // G_ABDU = 66
10601 CEFBS_None, // G_IMPLICIT_DEF = 67
10602 CEFBS_None, // G_PHI = 68
10603 CEFBS_None, // G_FRAME_INDEX = 69
10604 CEFBS_None, // G_GLOBAL_VALUE = 70
10605 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
10606 CEFBS_None, // G_CONSTANT_POOL = 72
10607 CEFBS_None, // G_EXTRACT = 73
10608 CEFBS_None, // G_UNMERGE_VALUES = 74
10609 CEFBS_None, // G_INSERT = 75
10610 CEFBS_None, // G_MERGE_VALUES = 76
10611 CEFBS_None, // G_BUILD_VECTOR = 77
10612 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
10613 CEFBS_None, // G_CONCAT_VECTORS = 79
10614 CEFBS_None, // G_PTRTOINT = 80
10615 CEFBS_None, // G_INTTOPTR = 81
10616 CEFBS_None, // G_BITCAST = 82
10617 CEFBS_None, // G_FREEZE = 83
10618 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
10619 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
10620 CEFBS_None, // G_INTRINSIC_TRUNC = 86
10621 CEFBS_None, // G_INTRINSIC_ROUND = 87
10622 CEFBS_None, // G_INTRINSIC_LRINT = 88
10623 CEFBS_None, // G_INTRINSIC_LLRINT = 89
10624 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
10625 CEFBS_None, // G_READCYCLECOUNTER = 91
10626 CEFBS_None, // G_READSTEADYCOUNTER = 92
10627 CEFBS_None, // G_LOAD = 93
10628 CEFBS_None, // G_SEXTLOAD = 94
10629 CEFBS_None, // G_ZEXTLOAD = 95
10630 CEFBS_None, // G_INDEXED_LOAD = 96
10631 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
10632 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
10633 CEFBS_None, // G_STORE = 99
10634 CEFBS_None, // G_INDEXED_STORE = 100
10635 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
10636 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
10637 CEFBS_None, // G_ATOMICRMW_XCHG = 103
10638 CEFBS_None, // G_ATOMICRMW_ADD = 104
10639 CEFBS_None, // G_ATOMICRMW_SUB = 105
10640 CEFBS_None, // G_ATOMICRMW_AND = 106
10641 CEFBS_None, // G_ATOMICRMW_NAND = 107
10642 CEFBS_None, // G_ATOMICRMW_OR = 108
10643 CEFBS_None, // G_ATOMICRMW_XOR = 109
10644 CEFBS_None, // G_ATOMICRMW_MAX = 110
10645 CEFBS_None, // G_ATOMICRMW_MIN = 111
10646 CEFBS_None, // G_ATOMICRMW_UMAX = 112
10647 CEFBS_None, // G_ATOMICRMW_UMIN = 113
10648 CEFBS_None, // G_ATOMICRMW_FADD = 114
10649 CEFBS_None, // G_ATOMICRMW_FSUB = 115
10650 CEFBS_None, // G_ATOMICRMW_FMAX = 116
10651 CEFBS_None, // G_ATOMICRMW_FMIN = 117
10652 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
10653 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
10654 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
10655 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
10656 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
10657 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
10658 CEFBS_None, // G_FENCE = 124
10659 CEFBS_None, // G_PREFETCH = 125
10660 CEFBS_None, // G_BRCOND = 126
10661 CEFBS_None, // G_BRINDIRECT = 127
10662 CEFBS_None, // G_INVOKE_REGION_START = 128
10663 CEFBS_None, // G_INTRINSIC = 129
10664 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
10665 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
10666 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
10667 CEFBS_None, // G_ANYEXT = 133
10668 CEFBS_None, // G_TRUNC = 134
10669 CEFBS_None, // G_CONSTANT = 135
10670 CEFBS_None, // G_FCONSTANT = 136
10671 CEFBS_None, // G_VASTART = 137
10672 CEFBS_None, // G_VAARG = 138
10673 CEFBS_None, // G_SEXT = 139
10674 CEFBS_None, // G_SEXT_INREG = 140
10675 CEFBS_None, // G_ZEXT = 141
10676 CEFBS_None, // G_SHL = 142
10677 CEFBS_None, // G_LSHR = 143
10678 CEFBS_None, // G_ASHR = 144
10679 CEFBS_None, // G_FSHL = 145
10680 CEFBS_None, // G_FSHR = 146
10681 CEFBS_None, // G_ROTR = 147
10682 CEFBS_None, // G_ROTL = 148
10683 CEFBS_None, // G_ICMP = 149
10684 CEFBS_None, // G_FCMP = 150
10685 CEFBS_None, // G_SCMP = 151
10686 CEFBS_None, // G_UCMP = 152
10687 CEFBS_None, // G_SELECT = 153
10688 CEFBS_None, // G_UADDO = 154
10689 CEFBS_None, // G_UADDE = 155
10690 CEFBS_None, // G_USUBO = 156
10691 CEFBS_None, // G_USUBE = 157
10692 CEFBS_None, // G_SADDO = 158
10693 CEFBS_None, // G_SADDE = 159
10694 CEFBS_None, // G_SSUBO = 160
10695 CEFBS_None, // G_SSUBE = 161
10696 CEFBS_None, // G_UMULO = 162
10697 CEFBS_None, // G_SMULO = 163
10698 CEFBS_None, // G_UMULH = 164
10699 CEFBS_None, // G_SMULH = 165
10700 CEFBS_None, // G_UADDSAT = 166
10701 CEFBS_None, // G_SADDSAT = 167
10702 CEFBS_None, // G_USUBSAT = 168
10703 CEFBS_None, // G_SSUBSAT = 169
10704 CEFBS_None, // G_USHLSAT = 170
10705 CEFBS_None, // G_SSHLSAT = 171
10706 CEFBS_None, // G_SMULFIX = 172
10707 CEFBS_None, // G_UMULFIX = 173
10708 CEFBS_None, // G_SMULFIXSAT = 174
10709 CEFBS_None, // G_UMULFIXSAT = 175
10710 CEFBS_None, // G_SDIVFIX = 176
10711 CEFBS_None, // G_UDIVFIX = 177
10712 CEFBS_None, // G_SDIVFIXSAT = 178
10713 CEFBS_None, // G_UDIVFIXSAT = 179
10714 CEFBS_None, // G_FADD = 180
10715 CEFBS_None, // G_FSUB = 181
10716 CEFBS_None, // G_FMUL = 182
10717 CEFBS_None, // G_FMA = 183
10718 CEFBS_None, // G_FMAD = 184
10719 CEFBS_None, // G_FDIV = 185
10720 CEFBS_None, // G_FREM = 186
10721 CEFBS_None, // G_FPOW = 187
10722 CEFBS_None, // G_FPOWI = 188
10723 CEFBS_None, // G_FEXP = 189
10724 CEFBS_None, // G_FEXP2 = 190
10725 CEFBS_None, // G_FEXP10 = 191
10726 CEFBS_None, // G_FLOG = 192
10727 CEFBS_None, // G_FLOG2 = 193
10728 CEFBS_None, // G_FLOG10 = 194
10729 CEFBS_None, // G_FLDEXP = 195
10730 CEFBS_None, // G_FFREXP = 196
10731 CEFBS_None, // G_FNEG = 197
10732 CEFBS_None, // G_FPEXT = 198
10733 CEFBS_None, // G_FPTRUNC = 199
10734 CEFBS_None, // G_FPTOSI = 200
10735 CEFBS_None, // G_FPTOUI = 201
10736 CEFBS_None, // G_SITOFP = 202
10737 CEFBS_None, // G_UITOFP = 203
10738 CEFBS_None, // G_FPTOSI_SAT = 204
10739 CEFBS_None, // G_FPTOUI_SAT = 205
10740 CEFBS_None, // G_FABS = 206
10741 CEFBS_None, // G_FCOPYSIGN = 207
10742 CEFBS_None, // G_IS_FPCLASS = 208
10743 CEFBS_None, // G_FCANONICALIZE = 209
10744 CEFBS_None, // G_FMINNUM = 210
10745 CEFBS_None, // G_FMAXNUM = 211
10746 CEFBS_None, // G_FMINNUM_IEEE = 212
10747 CEFBS_None, // G_FMAXNUM_IEEE = 213
10748 CEFBS_None, // G_FMINIMUM = 214
10749 CEFBS_None, // G_FMAXIMUM = 215
10750 CEFBS_None, // G_FMINIMUMNUM = 216
10751 CEFBS_None, // G_FMAXIMUMNUM = 217
10752 CEFBS_None, // G_GET_FPENV = 218
10753 CEFBS_None, // G_SET_FPENV = 219
10754 CEFBS_None, // G_RESET_FPENV = 220
10755 CEFBS_None, // G_GET_FPMODE = 221
10756 CEFBS_None, // G_SET_FPMODE = 222
10757 CEFBS_None, // G_RESET_FPMODE = 223
10758 CEFBS_None, // G_PTR_ADD = 224
10759 CEFBS_None, // G_PTRMASK = 225
10760 CEFBS_None, // G_SMIN = 226
10761 CEFBS_None, // G_SMAX = 227
10762 CEFBS_None, // G_UMIN = 228
10763 CEFBS_None, // G_UMAX = 229
10764 CEFBS_None, // G_ABS = 230
10765 CEFBS_None, // G_LROUND = 231
10766 CEFBS_None, // G_LLROUND = 232
10767 CEFBS_None, // G_BR = 233
10768 CEFBS_None, // G_BRJT = 234
10769 CEFBS_None, // G_VSCALE = 235
10770 CEFBS_None, // G_INSERT_SUBVECTOR = 236
10771 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
10772 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
10773 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
10774 CEFBS_None, // G_SHUFFLE_VECTOR = 240
10775 CEFBS_None, // G_SPLAT_VECTOR = 241
10776 CEFBS_None, // G_STEP_VECTOR = 242
10777 CEFBS_None, // G_VECTOR_COMPRESS = 243
10778 CEFBS_None, // G_CTTZ = 244
10779 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
10780 CEFBS_None, // G_CTLZ = 246
10781 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
10782 CEFBS_None, // G_CTPOP = 248
10783 CEFBS_None, // G_BSWAP = 249
10784 CEFBS_None, // G_BITREVERSE = 250
10785 CEFBS_None, // G_FCEIL = 251
10786 CEFBS_None, // G_FCOS = 252
10787 CEFBS_None, // G_FSIN = 253
10788 CEFBS_None, // G_FSINCOS = 254
10789 CEFBS_None, // G_FTAN = 255
10790 CEFBS_None, // G_FACOS = 256
10791 CEFBS_None, // G_FASIN = 257
10792 CEFBS_None, // G_FATAN = 258
10793 CEFBS_None, // G_FATAN2 = 259
10794 CEFBS_None, // G_FCOSH = 260
10795 CEFBS_None, // G_FSINH = 261
10796 CEFBS_None, // G_FTANH = 262
10797 CEFBS_None, // G_FSQRT = 263
10798 CEFBS_None, // G_FFLOOR = 264
10799 CEFBS_None, // G_FRINT = 265
10800 CEFBS_None, // G_FNEARBYINT = 266
10801 CEFBS_None, // G_ADDRSPACE_CAST = 267
10802 CEFBS_None, // G_BLOCK_ADDR = 268
10803 CEFBS_None, // G_JUMP_TABLE = 269
10804 CEFBS_None, // G_DYN_STACKALLOC = 270
10805 CEFBS_None, // G_STACKSAVE = 271
10806 CEFBS_None, // G_STACKRESTORE = 272
10807 CEFBS_None, // G_STRICT_FADD = 273
10808 CEFBS_None, // G_STRICT_FSUB = 274
10809 CEFBS_None, // G_STRICT_FMUL = 275
10810 CEFBS_None, // G_STRICT_FDIV = 276
10811 CEFBS_None, // G_STRICT_FREM = 277
10812 CEFBS_None, // G_STRICT_FMA = 278
10813 CEFBS_None, // G_STRICT_FSQRT = 279
10814 CEFBS_None, // G_STRICT_FLDEXP = 280
10815 CEFBS_None, // G_READ_REGISTER = 281
10816 CEFBS_None, // G_WRITE_REGISTER = 282
10817 CEFBS_None, // G_MEMCPY = 283
10818 CEFBS_None, // G_MEMCPY_INLINE = 284
10819 CEFBS_None, // G_MEMMOVE = 285
10820 CEFBS_None, // G_MEMSET = 286
10821 CEFBS_None, // G_BZERO = 287
10822 CEFBS_None, // G_TRAP = 288
10823 CEFBS_None, // G_DEBUGTRAP = 289
10824 CEFBS_None, // G_UBSANTRAP = 290
10825 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
10826 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
10827 CEFBS_None, // G_VECREDUCE_FADD = 293
10828 CEFBS_None, // G_VECREDUCE_FMUL = 294
10829 CEFBS_None, // G_VECREDUCE_FMAX = 295
10830 CEFBS_None, // G_VECREDUCE_FMIN = 296
10831 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
10832 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
10833 CEFBS_None, // G_VECREDUCE_ADD = 299
10834 CEFBS_None, // G_VECREDUCE_MUL = 300
10835 CEFBS_None, // G_VECREDUCE_AND = 301
10836 CEFBS_None, // G_VECREDUCE_OR = 302
10837 CEFBS_None, // G_VECREDUCE_XOR = 303
10838 CEFBS_None, // G_VECREDUCE_SMAX = 304
10839 CEFBS_None, // G_VECREDUCE_SMIN = 305
10840 CEFBS_None, // G_VECREDUCE_UMAX = 306
10841 CEFBS_None, // G_VECREDUCE_UMIN = 307
10842 CEFBS_None, // G_SBFX = 308
10843 CEFBS_None, // G_UBFX = 309
10844 CEFBS_None, // ATOMIC_CMP_SWAP_I128 = 310
10845 CEFBS_None, // ATOMIC_LOAD_ADD_I128 = 311
10846 CEFBS_None, // ATOMIC_LOAD_AND_I128 = 312
10847 CEFBS_None, // ATOMIC_LOAD_NAND_I128 = 313
10848 CEFBS_None, // ATOMIC_LOAD_OR_I128 = 314
10849 CEFBS_None, // ATOMIC_LOAD_SUB_I128 = 315
10850 CEFBS_None, // ATOMIC_LOAD_XOR_I128 = 316
10851 CEFBS_None, // ATOMIC_SWAP_I128 = 317
10852 CEFBS_None, // BUILD_QUADWORD = 318
10853 CEFBS_None, // BUILD_UACC = 319
10854 CEFBS_None, // CFENCE = 320
10855 CEFBS_None, // CFENCE8 = 321
10856 CEFBS_None, // CLRLSLDI = 322
10857 CEFBS_None, // CLRLSLDI_rec = 323
10858 CEFBS_None, // CLRLSLWI = 324
10859 CEFBS_None, // CLRLSLWI_rec = 325
10860 CEFBS_None, // CLRRDI = 326
10861 CEFBS_None, // CLRRDI_rec = 327
10862 CEFBS_None, // CLRRWI = 328
10863 CEFBS_None, // CLRRWI_rec = 329
10864 CEFBS_None, // DCBFL = 330
10865 CEFBS_None, // DCBFLP = 331
10866 CEFBS_None, // DCBFPS = 332
10867 CEFBS_None, // DCBFx = 333
10868 CEFBS_None, // DCBSTPS = 334
10869 CEFBS_None, // DCBTCT = 335
10870 CEFBS_None, // DCBTDS = 336
10871 CEFBS_None, // DCBTSTCT = 337
10872 CEFBS_None, // DCBTSTDS = 338
10873 CEFBS_None, // DCBTSTT = 339
10874 CEFBS_None, // DCBTSTx = 340
10875 CEFBS_None, // DCBTT = 341
10876 CEFBS_None, // DCBTx = 342
10877 CEFBS_None, // DFLOADf32 = 343
10878 CEFBS_None, // DFLOADf64 = 344
10879 CEFBS_None, // DFSTOREf32 = 345
10880 CEFBS_None, // DFSTOREf64 = 346
10881 CEFBS_None, // EXTLDI = 347
10882 CEFBS_None, // EXTLDI_rec = 348
10883 CEFBS_None, // EXTLWI = 349
10884 CEFBS_None, // EXTLWI_rec = 350
10885 CEFBS_None, // EXTRDI = 351
10886 CEFBS_None, // EXTRDI_rec = 352
10887 CEFBS_None, // EXTRWI = 353
10888 CEFBS_None, // EXTRWI_rec = 354
10889 CEFBS_None, // INSLWI = 355
10890 CEFBS_None, // INSLWI_rec = 356
10891 CEFBS_None, // INSRDI = 357
10892 CEFBS_None, // INSRDI_rec = 358
10893 CEFBS_None, // INSRWI = 359
10894 CEFBS_None, // INSRWI_rec = 360
10895 CEFBS_None, // KILL_PAIR = 361
10896 CEFBS_None, // LAx = 362
10897 CEFBS_None, // LIWAX = 363
10898 CEFBS_None, // LIWZX = 364
10899 CEFBS_None, // PPCLdFixedAddr = 365
10900 CEFBS_None, // PSUBI = 366
10901 CEFBS_None, // RLWIMIbm = 367
10902 CEFBS_None, // RLWIMIbm_rec = 368
10903 CEFBS_None, // RLWINMbm = 369
10904 CEFBS_None, // RLWINMbm_rec = 370
10905 CEFBS_None, // RLWNMbm = 371
10906 CEFBS_None, // RLWNMbm_rec = 372
10907 CEFBS_None, // ROTRDI = 373
10908 CEFBS_None, // ROTRDI_rec = 374
10909 CEFBS_None, // ROTRWI = 375
10910 CEFBS_None, // ROTRWI_rec = 376
10911 CEFBS_None, // SLDI = 377
10912 CEFBS_None, // SLDI_rec = 378
10913 CEFBS_None, // SLWI = 379
10914 CEFBS_None, // SLWI_rec = 380
10915 CEFBS_None, // SPILLTOVSR_LD = 381
10916 CEFBS_None, // SPILLTOVSR_LDX = 382
10917 CEFBS_None, // SPILLTOVSR_ST = 383
10918 CEFBS_None, // SPILLTOVSR_STX = 384
10919 CEFBS_None, // SRDI = 385
10920 CEFBS_None, // SRDI_rec = 386
10921 CEFBS_None, // SRWI = 387
10922 CEFBS_None, // SRWI_rec = 388
10923 CEFBS_None, // STIWX = 389
10924 CEFBS_None, // SUBI = 390
10925 CEFBS_None, // SUBIC = 391
10926 CEFBS_None, // SUBIC_rec = 392
10927 CEFBS_None, // SUBIS = 393
10928 CEFBS_None, // SUBPCIS = 394
10929 CEFBS_None, // XFLOADf32 = 395
10930 CEFBS_None, // XFLOADf64 = 396
10931 CEFBS_None, // XFSTOREf32 = 397
10932 CEFBS_None, // XFSTOREf64 = 398
10933 CEFBS_None, // ADD4 = 399
10934 CEFBS_None, // ADD4O = 400
10935 CEFBS_None, // ADD4O_rec = 401
10936 CEFBS_None, // ADD4TLS = 402
10937 CEFBS_None, // ADD4_rec = 403
10938 CEFBS_None, // ADD8 = 404
10939 CEFBS_None, // ADD8O = 405
10940 CEFBS_None, // ADD8O_rec = 406
10941 CEFBS_None, // ADD8TLS = 407
10942 CEFBS_None, // ADD8TLS_ = 408
10943 CEFBS_None, // ADD8_rec = 409
10944 CEFBS_None, // ADDC = 410
10945 CEFBS_None, // ADDC8 = 411
10946 CEFBS_None, // ADDC8O = 412
10947 CEFBS_None, // ADDC8O_rec = 413
10948 CEFBS_None, // ADDC8_rec = 414
10949 CEFBS_None, // ADDCO = 415
10950 CEFBS_None, // ADDCO_rec = 416
10951 CEFBS_None, // ADDC_rec = 417
10952 CEFBS_None, // ADDE = 418
10953 CEFBS_None, // ADDE8 = 419
10954 CEFBS_None, // ADDE8O = 420
10955 CEFBS_None, // ADDE8O_rec = 421
10956 CEFBS_None, // ADDE8_rec = 422
10957 CEFBS_None, // ADDEO = 423
10958 CEFBS_None, // ADDEO_rec = 424
10959 CEFBS_None, // ADDEX = 425
10960 CEFBS_None, // ADDEX8 = 426
10961 CEFBS_None, // ADDE_rec = 427
10962 CEFBS_None, // ADDG6S = 428
10963 CEFBS_None, // ADDG6S8 = 429
10964 CEFBS_None, // ADDI = 430
10965 CEFBS_None, // ADDI8 = 431
10966 CEFBS_None, // ADDIC = 432
10967 CEFBS_None, // ADDIC8 = 433
10968 CEFBS_None, // ADDIC_rec = 434
10969 CEFBS_None, // ADDIS = 435
10970 CEFBS_None, // ADDIS8 = 436
10971 CEFBS_None, // ADDISdtprelHA = 437
10972 CEFBS_None, // ADDISdtprelHA32 = 438
10973 CEFBS_None, // ADDISgotTprelHA = 439
10974 CEFBS_None, // ADDIStlsgdHA = 440
10975 CEFBS_None, // ADDIStlsldHA = 441
10976 CEFBS_None, // ADDIStocHA = 442
10977 CEFBS_None, // ADDIStocHA8 = 443
10978 CEFBS_None, // ADDIdtprelL = 444
10979 CEFBS_None, // ADDIdtprelL32 = 445
10980 CEFBS_None, // ADDItlsgdL = 446
10981 CEFBS_None, // ADDItlsgdL32 = 447
10982 CEFBS_None, // ADDItlsgdLADDR = 448
10983 CEFBS_None, // ADDItlsgdLADDR32 = 449
10984 CEFBS_None, // ADDItlsldL = 450
10985 CEFBS_None, // ADDItlsldL32 = 451
10986 CEFBS_None, // ADDItlsldLADDR = 452
10987 CEFBS_None, // ADDItlsldLADDR32 = 453
10988 CEFBS_None, // ADDItoc = 454
10989 CEFBS_None, // ADDItoc8 = 455
10990 CEFBS_None, // ADDItocL = 456
10991 CEFBS_None, // ADDItocL8 = 457
10992 CEFBS_None, // ADDME = 458
10993 CEFBS_None, // ADDME8 = 459
10994 CEFBS_None, // ADDME8O = 460
10995 CEFBS_None, // ADDME8O_rec = 461
10996 CEFBS_None, // ADDME8_rec = 462
10997 CEFBS_None, // ADDMEO = 463
10998 CEFBS_None, // ADDMEO_rec = 464
10999 CEFBS_None, // ADDME_rec = 465
11000 CEFBS_None, // ADDPCIS = 466
11001 CEFBS_None, // ADDZE = 467
11002 CEFBS_None, // ADDZE8 = 468
11003 CEFBS_None, // ADDZE8O = 469
11004 CEFBS_None, // ADDZE8O_rec = 470
11005 CEFBS_None, // ADDZE8_rec = 471
11006 CEFBS_None, // ADDZEO = 472
11007 CEFBS_None, // ADDZEO_rec = 473
11008 CEFBS_None, // ADDZE_rec = 474
11009 CEFBS_None, // ADJCALLSTACKDOWN = 475
11010 CEFBS_None, // ADJCALLSTACKUP = 476
11011 CEFBS_None, // AND = 477
11012 CEFBS_None, // AND8 = 478
11013 CEFBS_None, // AND8_rec = 479
11014 CEFBS_None, // ANDC = 480
11015 CEFBS_None, // ANDC8 = 481
11016 CEFBS_None, // ANDC8_rec = 482
11017 CEFBS_None, // ANDC_rec = 483
11018 CEFBS_None, // ANDI8_rec = 484
11019 CEFBS_None, // ANDIS8_rec = 485
11020 CEFBS_None, // ANDIS_rec = 486
11021 CEFBS_None, // ANDI_rec = 487
11022 CEFBS_None, // ANDI_rec_1_EQ_BIT = 488
11023 CEFBS_None, // ANDI_rec_1_EQ_BIT8 = 489
11024 CEFBS_None, // ANDI_rec_1_GT_BIT = 490
11025 CEFBS_None, // ANDI_rec_1_GT_BIT8 = 491
11026 CEFBS_None, // AND_rec = 492
11027 CEFBS_None, // ATOMIC_CMP_SWAP_I16 = 493
11028 CEFBS_None, // ATOMIC_CMP_SWAP_I32 = 494
11029 CEFBS_None, // ATOMIC_CMP_SWAP_I64 = 495
11030 CEFBS_None, // ATOMIC_CMP_SWAP_I8 = 496
11031 CEFBS_None, // ATOMIC_LOAD_ADD_I16 = 497
11032 CEFBS_None, // ATOMIC_LOAD_ADD_I32 = 498
11033 CEFBS_None, // ATOMIC_LOAD_ADD_I64 = 499
11034 CEFBS_None, // ATOMIC_LOAD_ADD_I8 = 500
11035 CEFBS_None, // ATOMIC_LOAD_AND_I16 = 501
11036 CEFBS_None, // ATOMIC_LOAD_AND_I32 = 502
11037 CEFBS_None, // ATOMIC_LOAD_AND_I64 = 503
11038 CEFBS_None, // ATOMIC_LOAD_AND_I8 = 504
11039 CEFBS_None, // ATOMIC_LOAD_MAX_I16 = 505
11040 CEFBS_None, // ATOMIC_LOAD_MAX_I32 = 506
11041 CEFBS_None, // ATOMIC_LOAD_MAX_I64 = 507
11042 CEFBS_None, // ATOMIC_LOAD_MAX_I8 = 508
11043 CEFBS_None, // ATOMIC_LOAD_MIN_I16 = 509
11044 CEFBS_None, // ATOMIC_LOAD_MIN_I32 = 510
11045 CEFBS_None, // ATOMIC_LOAD_MIN_I64 = 511
11046 CEFBS_None, // ATOMIC_LOAD_MIN_I8 = 512
11047 CEFBS_None, // ATOMIC_LOAD_NAND_I16 = 513
11048 CEFBS_None, // ATOMIC_LOAD_NAND_I32 = 514
11049 CEFBS_None, // ATOMIC_LOAD_NAND_I64 = 515
11050 CEFBS_None, // ATOMIC_LOAD_NAND_I8 = 516
11051 CEFBS_None, // ATOMIC_LOAD_OR_I16 = 517
11052 CEFBS_None, // ATOMIC_LOAD_OR_I32 = 518
11053 CEFBS_None, // ATOMIC_LOAD_OR_I64 = 519
11054 CEFBS_None, // ATOMIC_LOAD_OR_I8 = 520
11055 CEFBS_None, // ATOMIC_LOAD_SUB_I16 = 521
11056 CEFBS_None, // ATOMIC_LOAD_SUB_I32 = 522
11057 CEFBS_None, // ATOMIC_LOAD_SUB_I64 = 523
11058 CEFBS_None, // ATOMIC_LOAD_SUB_I8 = 524
11059 CEFBS_None, // ATOMIC_LOAD_UMAX_I16 = 525
11060 CEFBS_None, // ATOMIC_LOAD_UMAX_I32 = 526
11061 CEFBS_None, // ATOMIC_LOAD_UMAX_I64 = 527
11062 CEFBS_None, // ATOMIC_LOAD_UMAX_I8 = 528
11063 CEFBS_None, // ATOMIC_LOAD_UMIN_I16 = 529
11064 CEFBS_None, // ATOMIC_LOAD_UMIN_I32 = 530
11065 CEFBS_None, // ATOMIC_LOAD_UMIN_I64 = 531
11066 CEFBS_None, // ATOMIC_LOAD_UMIN_I8 = 532
11067 CEFBS_None, // ATOMIC_LOAD_XOR_I16 = 533
11068 CEFBS_None, // ATOMIC_LOAD_XOR_I32 = 534
11069 CEFBS_None, // ATOMIC_LOAD_XOR_I64 = 535
11070 CEFBS_None, // ATOMIC_LOAD_XOR_I8 = 536
11071 CEFBS_None, // ATOMIC_SWAP_I16 = 537
11072 CEFBS_None, // ATOMIC_SWAP_I32 = 538
11073 CEFBS_None, // ATOMIC_SWAP_I64 = 539
11074 CEFBS_None, // ATOMIC_SWAP_I8 = 540
11075 CEFBS_None, // ATTN = 541
11076 CEFBS_None, // B = 542
11077 CEFBS_None, // BA = 543
11078 CEFBS_None, // BC = 544
11079 CEFBS_None, // BCC = 545
11080 CEFBS_None, // BCCA = 546
11081 CEFBS_None, // BCCCTR = 547
11082 CEFBS_None, // BCCCTR8 = 548
11083 CEFBS_None, // BCCCTRL = 549
11084 CEFBS_None, // BCCCTRL8 = 550
11085 CEFBS_None, // BCCL = 551
11086 CEFBS_None, // BCCLA = 552
11087 CEFBS_None, // BCCLR = 553
11088 CEFBS_None, // BCCLRL = 554
11089 CEFBS_None, // BCCTR = 555
11090 CEFBS_None, // BCCTR8 = 556
11091 CEFBS_None, // BCCTR8n = 557
11092 CEFBS_None, // BCCTRL = 558
11093 CEFBS_None, // BCCTRL8 = 559
11094 CEFBS_None, // BCCTRL8n = 560
11095 CEFBS_None, // BCCTRLn = 561
11096 CEFBS_None, // BCCTRn = 562
11097 CEFBS_None, // BCDADD_rec = 563
11098 CEFBS_None, // BCDCFN_rec = 564
11099 CEFBS_None, // BCDCFSQ_rec = 565
11100 CEFBS_None, // BCDCFZ_rec = 566
11101 CEFBS_None, // BCDCPSGN_rec = 567
11102 CEFBS_None, // BCDCTN_rec = 568
11103 CEFBS_None, // BCDCTSQ_rec = 569
11104 CEFBS_None, // BCDCTZ_rec = 570
11105 CEFBS_None, // BCDSETSGN_rec = 571
11106 CEFBS_None, // BCDSR_rec = 572
11107 CEFBS_None, // BCDSUB_rec = 573
11108 CEFBS_None, // BCDS_rec = 574
11109 CEFBS_None, // BCDTRUNC_rec = 575
11110 CEFBS_None, // BCDUS_rec = 576
11111 CEFBS_None, // BCDUTRUNC_rec = 577
11112 CEFBS_None, // BCL = 578
11113 CEFBS_None, // BCLR = 579
11114 CEFBS_None, // BCLRL = 580
11115 CEFBS_None, // BCLRLn = 581
11116 CEFBS_None, // BCLRn = 582
11117 CEFBS_None, // BCLalways = 583
11118 CEFBS_None, // BCLn = 584
11119 CEFBS_None, // BCTR = 585
11120 CEFBS_None, // BCTR8 = 586
11121 CEFBS_None, // BCTRL = 587
11122 CEFBS_None, // BCTRL8 = 588
11123 CEFBS_None, // BCTRL8_LDinto_toc = 589
11124 CEFBS_None, // BCTRL8_LDinto_toc_RM = 590
11125 CEFBS_None, // BCTRL8_RM = 591
11126 CEFBS_None, // BCTRL_LWZinto_toc = 592
11127 CEFBS_None, // BCTRL_LWZinto_toc_RM = 593
11128 CEFBS_None, // BCTRL_RM = 594
11129 CEFBS_None, // BCn = 595
11130 CEFBS_None, // BDNZ = 596
11131 CEFBS_None, // BDNZ8 = 597
11132 CEFBS_None, // BDNZA = 598
11133 CEFBS_None, // BDNZAm = 599
11134 CEFBS_None, // BDNZAp = 600
11135 CEFBS_None, // BDNZL = 601
11136 CEFBS_None, // BDNZLA = 602
11137 CEFBS_None, // BDNZLAm = 603
11138 CEFBS_None, // BDNZLAp = 604
11139 CEFBS_None, // BDNZLR = 605
11140 CEFBS_None, // BDNZLR8 = 606
11141 CEFBS_None, // BDNZLRL = 607
11142 CEFBS_None, // BDNZLRLm = 608
11143 CEFBS_None, // BDNZLRLp = 609
11144 CEFBS_None, // BDNZLRm = 610
11145 CEFBS_None, // BDNZLRp = 611
11146 CEFBS_None, // BDNZLm = 612
11147 CEFBS_None, // BDNZLp = 613
11148 CEFBS_None, // BDNZm = 614
11149 CEFBS_None, // BDNZp = 615
11150 CEFBS_None, // BDZ = 616
11151 CEFBS_None, // BDZ8 = 617
11152 CEFBS_None, // BDZA = 618
11153 CEFBS_None, // BDZAm = 619
11154 CEFBS_None, // BDZAp = 620
11155 CEFBS_None, // BDZL = 621
11156 CEFBS_None, // BDZLA = 622
11157 CEFBS_None, // BDZLAm = 623
11158 CEFBS_None, // BDZLAp = 624
11159 CEFBS_None, // BDZLR = 625
11160 CEFBS_None, // BDZLR8 = 626
11161 CEFBS_None, // BDZLRL = 627
11162 CEFBS_None, // BDZLRLm = 628
11163 CEFBS_None, // BDZLRLp = 629
11164 CEFBS_None, // BDZLRm = 630
11165 CEFBS_None, // BDZLRp = 631
11166 CEFBS_None, // BDZLm = 632
11167 CEFBS_None, // BDZLp = 633
11168 CEFBS_None, // BDZm = 634
11169 CEFBS_None, // BDZp = 635
11170 CEFBS_None, // BL = 636
11171 CEFBS_None, // BL8 = 637
11172 CEFBS_None, // BL8_NOP = 638
11173 CEFBS_None, // BL8_NOP_RM = 639
11174 CEFBS_None, // BL8_NOP_TLS = 640
11175 CEFBS_None, // BL8_NOTOC = 641
11176 CEFBS_None, // BL8_NOTOC_RM = 642
11177 CEFBS_None, // BL8_NOTOC_TLS = 643
11178 CEFBS_None, // BL8_RM = 644
11179 CEFBS_None, // BL8_TLS = 645
11180 CEFBS_None, // BL8_TLS_ = 646
11181 CEFBS_None, // BLA = 647
11182 CEFBS_None, // BLA8 = 648
11183 CEFBS_None, // BLA8_NOP = 649
11184 CEFBS_None, // BLA8_NOP_RM = 650
11185 CEFBS_None, // BLA8_RM = 651
11186 CEFBS_None, // BLA_RM = 652
11187 CEFBS_None, // BLR = 653
11188 CEFBS_None, // BLR8 = 654
11189 CEFBS_None, // BLRL = 655
11190 CEFBS_None, // BL_NOP = 656
11191 CEFBS_None, // BL_NOP_RM = 657
11192 CEFBS_None, // BL_RM = 658
11193 CEFBS_None, // BL_TLS = 659
11194 CEFBS_None, // BPERMD = 660
11195 CEFBS_None, // BRD = 661
11196 CEFBS_None, // BRH = 662
11197 CEFBS_None, // BRH8 = 663
11198 CEFBS_None, // BRINC = 664
11199 CEFBS_None, // BRW = 665
11200 CEFBS_None, // BRW8 = 666
11201 CEFBS_None, // CBCDTD = 667
11202 CEFBS_None, // CBCDTD8 = 668
11203 CEFBS_None, // CDTBCD = 669
11204 CEFBS_None, // CDTBCD8 = 670
11205 CEFBS_None, // CFUGED = 671
11206 CEFBS_None, // CLRBHRB = 672
11207 CEFBS_None, // CMPB = 673
11208 CEFBS_None, // CMPB8 = 674
11209 CEFBS_None, // CMPD = 675
11210 CEFBS_None, // CMPDI = 676
11211 CEFBS_None, // CMPEQB = 677
11212 CEFBS_None, // CMPLD = 678
11213 CEFBS_None, // CMPLDI = 679
11214 CEFBS_None, // CMPLW = 680
11215 CEFBS_None, // CMPLWI = 681
11216 CEFBS_None, // CMPRB = 682
11217 CEFBS_None, // CMPRB8 = 683
11218 CEFBS_None, // CMPW = 684
11219 CEFBS_None, // CMPWI = 685
11220 CEFBS_None, // CNTLZD = 686
11221 CEFBS_None, // CNTLZDM = 687
11222 CEFBS_None, // CNTLZD_rec = 688
11223 CEFBS_None, // CNTLZW = 689
11224 CEFBS_None, // CNTLZW8 = 690
11225 CEFBS_None, // CNTLZW8_rec = 691
11226 CEFBS_None, // CNTLZW_rec = 692
11227 CEFBS_None, // CNTTZD = 693
11228 CEFBS_None, // CNTTZDM = 694
11229 CEFBS_None, // CNTTZD_rec = 695
11230 CEFBS_None, // CNTTZW = 696
11231 CEFBS_None, // CNTTZW8 = 697
11232 CEFBS_None, // CNTTZW8_rec = 698
11233 CEFBS_None, // CNTTZW_rec = 699
11234 CEFBS_None, // CP_ABORT = 700
11235 CEFBS_None, // CP_COPY = 701
11236 CEFBS_None, // CP_COPY8 = 702
11237 CEFBS_None, // CP_PASTE8_rec = 703
11238 CEFBS_None, // CP_PASTE_rec = 704
11239 CEFBS_None, // CR6SET = 705
11240 CEFBS_None, // CR6UNSET = 706
11241 CEFBS_None, // CRAND = 707
11242 CEFBS_None, // CRANDC = 708
11243 CEFBS_None, // CREQV = 709
11244 CEFBS_None, // CRNAND = 710
11245 CEFBS_None, // CRNOR = 711
11246 CEFBS_None, // CRNOT = 712
11247 CEFBS_None, // CROR = 713
11248 CEFBS_None, // CRORC = 714
11249 CEFBS_None, // CRSET = 715
11250 CEFBS_None, // CRUNSET = 716
11251 CEFBS_None, // CRXOR = 717
11252 CEFBS_None, // CTRL_DEP = 718
11253 CEFBS_None, // DADD = 719
11254 CEFBS_None, // DADDQ = 720
11255 CEFBS_None, // DADDQ_rec = 721
11256 CEFBS_None, // DADD_rec = 722
11257 CEFBS_None, // DARN = 723
11258 CEFBS_None, // DCBA = 724
11259 CEFBS_None, // DCBF = 725
11260 CEFBS_None, // DCBFEP = 726
11261 CEFBS_None, // DCBI = 727
11262 CEFBS_None, // DCBST = 728
11263 CEFBS_None, // DCBSTEP = 729
11264 CEFBS_None, // DCBT = 730
11265 CEFBS_None, // DCBTEP = 731
11266 CEFBS_None, // DCBTST = 732
11267 CEFBS_None, // DCBTSTEP = 733
11268 CEFBS_None, // DCBZ = 734
11269 CEFBS_None, // DCBZEP = 735
11270 CEFBS_None, // DCBZL = 736
11271 CEFBS_None, // DCBZLEP = 737
11272 CEFBS_None, // DCCCI = 738
11273 CEFBS_None, // DCFFIX = 739
11274 CEFBS_None, // DCFFIXQ = 740
11275 CEFBS_None, // DCFFIXQQ = 741
11276 CEFBS_None, // DCFFIXQ_rec = 742
11277 CEFBS_None, // DCFFIX_rec = 743
11278 CEFBS_None, // DCMPO = 744
11279 CEFBS_None, // DCMPOQ = 745
11280 CEFBS_None, // DCMPU = 746
11281 CEFBS_None, // DCMPUQ = 747
11282 CEFBS_None, // DCTDP = 748
11283 CEFBS_None, // DCTDP_rec = 749
11284 CEFBS_None, // DCTFIX = 750
11285 CEFBS_None, // DCTFIXQ = 751
11286 CEFBS_None, // DCTFIXQQ = 752
11287 CEFBS_None, // DCTFIXQ_rec = 753
11288 CEFBS_None, // DCTFIX_rec = 754
11289 CEFBS_None, // DCTQPQ = 755
11290 CEFBS_None, // DCTQPQ_rec = 756
11291 CEFBS_None, // DDEDPD = 757
11292 CEFBS_None, // DDEDPDQ = 758
11293 CEFBS_None, // DDEDPDQ_rec = 759
11294 CEFBS_None, // DDEDPD_rec = 760
11295 CEFBS_None, // DDIV = 761
11296 CEFBS_None, // DDIVQ = 762
11297 CEFBS_None, // DDIVQ_rec = 763
11298 CEFBS_None, // DDIV_rec = 764
11299 CEFBS_None, // DENBCD = 765
11300 CEFBS_None, // DENBCDQ = 766
11301 CEFBS_None, // DENBCDQ_rec = 767
11302 CEFBS_None, // DENBCD_rec = 768
11303 CEFBS_None, // DIEX = 769
11304 CEFBS_None, // DIEXQ = 770
11305 CEFBS_None, // DIEXQ_rec = 771
11306 CEFBS_None, // DIEX_rec = 772
11307 CEFBS_None, // DIVD = 773
11308 CEFBS_None, // DIVDE = 774
11309 CEFBS_None, // DIVDEO = 775
11310 CEFBS_None, // DIVDEO_rec = 776
11311 CEFBS_None, // DIVDEU = 777
11312 CEFBS_None, // DIVDEUO = 778
11313 CEFBS_None, // DIVDEUO_rec = 779
11314 CEFBS_None, // DIVDEU_rec = 780
11315 CEFBS_None, // DIVDE_rec = 781
11316 CEFBS_None, // DIVDO = 782
11317 CEFBS_None, // DIVDO_rec = 783
11318 CEFBS_None, // DIVDU = 784
11319 CEFBS_None, // DIVDUO = 785
11320 CEFBS_None, // DIVDUO_rec = 786
11321 CEFBS_None, // DIVDU_rec = 787
11322 CEFBS_None, // DIVD_rec = 788
11323 CEFBS_None, // DIVW = 789
11324 CEFBS_None, // DIVWE = 790
11325 CEFBS_None, // DIVWEO = 791
11326 CEFBS_None, // DIVWEO_rec = 792
11327 CEFBS_None, // DIVWEU = 793
11328 CEFBS_None, // DIVWEUO = 794
11329 CEFBS_None, // DIVWEUO_rec = 795
11330 CEFBS_None, // DIVWEU_rec = 796
11331 CEFBS_None, // DIVWE_rec = 797
11332 CEFBS_None, // DIVWO = 798
11333 CEFBS_None, // DIVWO_rec = 799
11334 CEFBS_None, // DIVWU = 800
11335 CEFBS_None, // DIVWUO = 801
11336 CEFBS_None, // DIVWUO_rec = 802
11337 CEFBS_None, // DIVWU_rec = 803
11338 CEFBS_None, // DIVW_rec = 804
11339 CEFBS_None, // DMMR = 805
11340 CEFBS_None, // DMSETDMRZ = 806
11341 CEFBS_None, // DMSHA2HASH = 807
11342 CEFBS_None, // DMSHA3HASH = 808
11343 CEFBS_None, // DMUL = 809
11344 CEFBS_None, // DMULQ = 810
11345 CEFBS_None, // DMULQ_rec = 811
11346 CEFBS_None, // DMUL_rec = 812
11347 CEFBS_None, // DMXOR = 813
11348 CEFBS_None, // DMXVBF16GERX2 = 814
11349 CEFBS_None, // DMXVBF16GERX2NN = 815
11350 CEFBS_None, // DMXVBF16GERX2NP = 816
11351 CEFBS_None, // DMXVBF16GERX2PN = 817
11352 CEFBS_None, // DMXVBF16GERX2PP = 818
11353 CEFBS_None, // DMXVF16GERX2 = 819
11354 CEFBS_None, // DMXVF16GERX2NN = 820
11355 CEFBS_None, // DMXVF16GERX2NP = 821
11356 CEFBS_None, // DMXVF16GERX2PN = 822
11357 CEFBS_None, // DMXVF16GERX2PP = 823
11358 CEFBS_None, // DMXVI8GERX4 = 824
11359 CEFBS_None, // DMXVI8GERX4PP = 825
11360 CEFBS_None, // DMXVI8GERX4SPP = 826
11361 CEFBS_None, // DMXXEXTFDMR256 = 827
11362 CEFBS_None, // DMXXEXTFDMR512 = 828
11363 CEFBS_None, // DMXXEXTFDMR512_HI = 829
11364 CEFBS_None, // DMXXINSTDMR256 = 830
11365 CEFBS_None, // DMXXINSTDMR512 = 831
11366 CEFBS_None, // DMXXINSTDMR512_HI = 832
11367 CEFBS_None, // DMXXSETACCZ = 833
11368 CEFBS_None, // DMXXSHAPAD = 834
11369 CEFBS_None, // DQUA = 835
11370 CEFBS_None, // DQUAI = 836
11371 CEFBS_None, // DQUAIQ = 837
11372 CEFBS_None, // DQUAIQ_rec = 838
11373 CEFBS_None, // DQUAI_rec = 839
11374 CEFBS_None, // DQUAQ = 840
11375 CEFBS_None, // DQUAQ_rec = 841
11376 CEFBS_None, // DQUA_rec = 842
11377 CEFBS_None, // DRDPQ = 843
11378 CEFBS_None, // DRDPQ_rec = 844
11379 CEFBS_None, // DRINTN = 845
11380 CEFBS_None, // DRINTNQ = 846
11381 CEFBS_None, // DRINTNQ_rec = 847
11382 CEFBS_None, // DRINTN_rec = 848
11383 CEFBS_None, // DRINTX = 849
11384 CEFBS_None, // DRINTXQ = 850
11385 CEFBS_None, // DRINTXQ_rec = 851
11386 CEFBS_None, // DRINTX_rec = 852
11387 CEFBS_None, // DRRND = 853
11388 CEFBS_None, // DRRNDQ = 854
11389 CEFBS_None, // DRRNDQ_rec = 855
11390 CEFBS_None, // DRRND_rec = 856
11391 CEFBS_None, // DRSP = 857
11392 CEFBS_None, // DRSP_rec = 858
11393 CEFBS_None, // DSCLI = 859
11394 CEFBS_None, // DSCLIQ = 860
11395 CEFBS_None, // DSCLIQ_rec = 861
11396 CEFBS_None, // DSCLI_rec = 862
11397 CEFBS_None, // DSCRI = 863
11398 CEFBS_None, // DSCRIQ = 864
11399 CEFBS_None, // DSCRIQ_rec = 865
11400 CEFBS_None, // DSCRI_rec = 866
11401 CEFBS_None, // DSS = 867
11402 CEFBS_None, // DSSALL = 868
11403 CEFBS_None, // DST = 869
11404 CEFBS_None, // DST64 = 870
11405 CEFBS_None, // DSTST = 871
11406 CEFBS_None, // DSTST64 = 872
11407 CEFBS_None, // DSTSTT = 873
11408 CEFBS_None, // DSTSTT64 = 874
11409 CEFBS_None, // DSTT = 875
11410 CEFBS_None, // DSTT64 = 876
11411 CEFBS_None, // DSUB = 877
11412 CEFBS_None, // DSUBQ = 878
11413 CEFBS_None, // DSUBQ_rec = 879
11414 CEFBS_None, // DSUB_rec = 880
11415 CEFBS_None, // DTSTDC = 881
11416 CEFBS_None, // DTSTDCQ = 882
11417 CEFBS_None, // DTSTDG = 883
11418 CEFBS_None, // DTSTDGQ = 884
11419 CEFBS_None, // DTSTEX = 885
11420 CEFBS_None, // DTSTEXQ = 886
11421 CEFBS_None, // DTSTSF = 887
11422 CEFBS_None, // DTSTSFI = 888
11423 CEFBS_None, // DTSTSFIQ = 889
11424 CEFBS_None, // DTSTSFQ = 890
11425 CEFBS_None, // DXEX = 891
11426 CEFBS_None, // DXEXQ = 892
11427 CEFBS_None, // DXEXQ_rec = 893
11428 CEFBS_None, // DXEX_rec = 894
11429 CEFBS_None, // DYNALLOC = 895
11430 CEFBS_None, // DYNALLOC8 = 896
11431 CEFBS_None, // DYNAREAOFFSET = 897
11432 CEFBS_None, // DYNAREAOFFSET8 = 898
11433 CEFBS_None, // DecreaseCTR8loop = 899
11434 CEFBS_None, // DecreaseCTRloop = 900
11435 CEFBS_None, // EFDABS = 901
11436 CEFBS_None, // EFDADD = 902
11437 CEFBS_None, // EFDCFS = 903
11438 CEFBS_None, // EFDCFSF = 904
11439 CEFBS_None, // EFDCFSI = 905
11440 CEFBS_None, // EFDCFSID = 906
11441 CEFBS_None, // EFDCFUF = 907
11442 CEFBS_None, // EFDCFUI = 908
11443 CEFBS_None, // EFDCFUID = 909
11444 CEFBS_None, // EFDCMPEQ = 910
11445 CEFBS_None, // EFDCMPGT = 911
11446 CEFBS_None, // EFDCMPLT = 912
11447 CEFBS_None, // EFDCTSF = 913
11448 CEFBS_None, // EFDCTSI = 914
11449 CEFBS_None, // EFDCTSIDZ = 915
11450 CEFBS_None, // EFDCTSIZ = 916
11451 CEFBS_None, // EFDCTUF = 917
11452 CEFBS_None, // EFDCTUI = 918
11453 CEFBS_None, // EFDCTUIDZ = 919
11454 CEFBS_None, // EFDCTUIZ = 920
11455 CEFBS_None, // EFDDIV = 921
11456 CEFBS_None, // EFDMUL = 922
11457 CEFBS_None, // EFDNABS = 923
11458 CEFBS_None, // EFDNEG = 924
11459 CEFBS_None, // EFDSUB = 925
11460 CEFBS_None, // EFDTSTEQ = 926
11461 CEFBS_None, // EFDTSTGT = 927
11462 CEFBS_None, // EFDTSTLT = 928
11463 CEFBS_None, // EFSABS = 929
11464 CEFBS_None, // EFSADD = 930
11465 CEFBS_None, // EFSCFD = 931
11466 CEFBS_None, // EFSCFSF = 932
11467 CEFBS_None, // EFSCFSI = 933
11468 CEFBS_None, // EFSCFUF = 934
11469 CEFBS_None, // EFSCFUI = 935
11470 CEFBS_None, // EFSCMPEQ = 936
11471 CEFBS_None, // EFSCMPGT = 937
11472 CEFBS_None, // EFSCMPLT = 938
11473 CEFBS_None, // EFSCTSF = 939
11474 CEFBS_None, // EFSCTSI = 940
11475 CEFBS_None, // EFSCTSIZ = 941
11476 CEFBS_None, // EFSCTUF = 942
11477 CEFBS_None, // EFSCTUI = 943
11478 CEFBS_None, // EFSCTUIZ = 944
11479 CEFBS_None, // EFSDIV = 945
11480 CEFBS_None, // EFSMUL = 946
11481 CEFBS_None, // EFSNABS = 947
11482 CEFBS_None, // EFSNEG = 948
11483 CEFBS_None, // EFSSUB = 949
11484 CEFBS_None, // EFSTSTEQ = 950
11485 CEFBS_None, // EFSTSTGT = 951
11486 CEFBS_None, // EFSTSTLT = 952
11487 CEFBS_None, // EH_SjLj_LongJmp32 = 953
11488 CEFBS_None, // EH_SjLj_LongJmp64 = 954
11489 CEFBS_None, // EH_SjLj_SetJmp32 = 955
11490 CEFBS_None, // EH_SjLj_SetJmp64 = 956
11491 CEFBS_None, // EH_SjLj_Setup = 957
11492 CEFBS_None, // EQV = 958
11493 CEFBS_None, // EQV8 = 959
11494 CEFBS_None, // EQV8_rec = 960
11495 CEFBS_None, // EQV_rec = 961
11496 CEFBS_None, // EVABS = 962
11497 CEFBS_None, // EVADDIW = 963
11498 CEFBS_None, // EVADDSMIAAW = 964
11499 CEFBS_None, // EVADDSSIAAW = 965
11500 CEFBS_None, // EVADDUMIAAW = 966
11501 CEFBS_None, // EVADDUSIAAW = 967
11502 CEFBS_None, // EVADDW = 968
11503 CEFBS_None, // EVAND = 969
11504 CEFBS_None, // EVANDC = 970
11505 CEFBS_None, // EVCMPEQ = 971
11506 CEFBS_None, // EVCMPGTS = 972
11507 CEFBS_None, // EVCMPGTU = 973
11508 CEFBS_None, // EVCMPLTS = 974
11509 CEFBS_None, // EVCMPLTU = 975
11510 CEFBS_None, // EVCNTLSW = 976
11511 CEFBS_None, // EVCNTLZW = 977
11512 CEFBS_None, // EVDIVWS = 978
11513 CEFBS_None, // EVDIVWU = 979
11514 CEFBS_None, // EVEQV = 980
11515 CEFBS_None, // EVEXTSB = 981
11516 CEFBS_None, // EVEXTSH = 982
11517 CEFBS_None, // EVFSABS = 983
11518 CEFBS_None, // EVFSADD = 984
11519 CEFBS_None, // EVFSCFSF = 985
11520 CEFBS_None, // EVFSCFSI = 986
11521 CEFBS_None, // EVFSCFUF = 987
11522 CEFBS_None, // EVFSCFUI = 988
11523 CEFBS_None, // EVFSCMPEQ = 989
11524 CEFBS_None, // EVFSCMPGT = 990
11525 CEFBS_None, // EVFSCMPLT = 991
11526 CEFBS_None, // EVFSCTSF = 992
11527 CEFBS_None, // EVFSCTSI = 993
11528 CEFBS_None, // EVFSCTSIZ = 994
11529 CEFBS_None, // EVFSCTUF = 995
11530 CEFBS_None, // EVFSCTUI = 996
11531 CEFBS_None, // EVFSCTUIZ = 997
11532 CEFBS_None, // EVFSDIV = 998
11533 CEFBS_None, // EVFSMUL = 999
11534 CEFBS_None, // EVFSNABS = 1000
11535 CEFBS_None, // EVFSNEG = 1001
11536 CEFBS_None, // EVFSSUB = 1002
11537 CEFBS_None, // EVFSTSTEQ = 1003
11538 CEFBS_None, // EVFSTSTGT = 1004
11539 CEFBS_None, // EVFSTSTLT = 1005
11540 CEFBS_None, // EVLDD = 1006
11541 CEFBS_None, // EVLDDX = 1007
11542 CEFBS_None, // EVLDH = 1008
11543 CEFBS_None, // EVLDHX = 1009
11544 CEFBS_None, // EVLDW = 1010
11545 CEFBS_None, // EVLDWX = 1011
11546 CEFBS_None, // EVLHHESPLAT = 1012
11547 CEFBS_None, // EVLHHESPLATX = 1013
11548 CEFBS_None, // EVLHHOSSPLAT = 1014
11549 CEFBS_None, // EVLHHOSSPLATX = 1015
11550 CEFBS_None, // EVLHHOUSPLAT = 1016
11551 CEFBS_None, // EVLHHOUSPLATX = 1017
11552 CEFBS_None, // EVLWHE = 1018
11553 CEFBS_None, // EVLWHEX = 1019
11554 CEFBS_None, // EVLWHOS = 1020
11555 CEFBS_None, // EVLWHOSX = 1021
11556 CEFBS_None, // EVLWHOU = 1022
11557 CEFBS_None, // EVLWHOUX = 1023
11558 CEFBS_None, // EVLWHSPLAT = 1024
11559 CEFBS_None, // EVLWHSPLATX = 1025
11560 CEFBS_None, // EVLWWSPLAT = 1026
11561 CEFBS_None, // EVLWWSPLATX = 1027
11562 CEFBS_None, // EVMERGEHI = 1028
11563 CEFBS_None, // EVMERGEHILO = 1029
11564 CEFBS_None, // EVMERGELO = 1030
11565 CEFBS_None, // EVMERGELOHI = 1031
11566 CEFBS_None, // EVMHEGSMFAA = 1032
11567 CEFBS_None, // EVMHEGSMFAN = 1033
11568 CEFBS_None, // EVMHEGSMIAA = 1034
11569 CEFBS_None, // EVMHEGSMIAN = 1035
11570 CEFBS_None, // EVMHEGUMIAA = 1036
11571 CEFBS_None, // EVMHEGUMIAN = 1037
11572 CEFBS_None, // EVMHESMF = 1038
11573 CEFBS_None, // EVMHESMFA = 1039
11574 CEFBS_None, // EVMHESMFAAW = 1040
11575 CEFBS_None, // EVMHESMFANW = 1041
11576 CEFBS_None, // EVMHESMI = 1042
11577 CEFBS_None, // EVMHESMIA = 1043
11578 CEFBS_None, // EVMHESMIAAW = 1044
11579 CEFBS_None, // EVMHESMIANW = 1045
11580 CEFBS_None, // EVMHESSF = 1046
11581 CEFBS_None, // EVMHESSFA = 1047
11582 CEFBS_None, // EVMHESSFAAW = 1048
11583 CEFBS_None, // EVMHESSFANW = 1049
11584 CEFBS_None, // EVMHESSIAAW = 1050
11585 CEFBS_None, // EVMHESSIANW = 1051
11586 CEFBS_None, // EVMHEUMI = 1052
11587 CEFBS_None, // EVMHEUMIA = 1053
11588 CEFBS_None, // EVMHEUMIAAW = 1054
11589 CEFBS_None, // EVMHEUMIANW = 1055
11590 CEFBS_None, // EVMHEUSIAAW = 1056
11591 CEFBS_None, // EVMHEUSIANW = 1057
11592 CEFBS_None, // EVMHOGSMFAA = 1058
11593 CEFBS_None, // EVMHOGSMFAN = 1059
11594 CEFBS_None, // EVMHOGSMIAA = 1060
11595 CEFBS_None, // EVMHOGSMIAN = 1061
11596 CEFBS_None, // EVMHOGUMIAA = 1062
11597 CEFBS_None, // EVMHOGUMIAN = 1063
11598 CEFBS_None, // EVMHOSMF = 1064
11599 CEFBS_None, // EVMHOSMFA = 1065
11600 CEFBS_None, // EVMHOSMFAAW = 1066
11601 CEFBS_None, // EVMHOSMFANW = 1067
11602 CEFBS_None, // EVMHOSMI = 1068
11603 CEFBS_None, // EVMHOSMIA = 1069
11604 CEFBS_None, // EVMHOSMIAAW = 1070
11605 CEFBS_None, // EVMHOSMIANW = 1071
11606 CEFBS_None, // EVMHOSSF = 1072
11607 CEFBS_None, // EVMHOSSFA = 1073
11608 CEFBS_None, // EVMHOSSFAAW = 1074
11609 CEFBS_None, // EVMHOSSFANW = 1075
11610 CEFBS_None, // EVMHOSSIAAW = 1076
11611 CEFBS_None, // EVMHOSSIANW = 1077
11612 CEFBS_None, // EVMHOUMI = 1078
11613 CEFBS_None, // EVMHOUMIA = 1079
11614 CEFBS_None, // EVMHOUMIAAW = 1080
11615 CEFBS_None, // EVMHOUMIANW = 1081
11616 CEFBS_None, // EVMHOUSIAAW = 1082
11617 CEFBS_None, // EVMHOUSIANW = 1083
11618 CEFBS_None, // EVMRA = 1084
11619 CEFBS_None, // EVMWHSMF = 1085
11620 CEFBS_None, // EVMWHSMFA = 1086
11621 CEFBS_None, // EVMWHSMI = 1087
11622 CEFBS_None, // EVMWHSMIA = 1088
11623 CEFBS_None, // EVMWHSSF = 1089
11624 CEFBS_None, // EVMWHSSFA = 1090
11625 CEFBS_None, // EVMWHUMI = 1091
11626 CEFBS_None, // EVMWHUMIA = 1092
11627 CEFBS_None, // EVMWLSMIAAW = 1093
11628 CEFBS_None, // EVMWLSMIANW = 1094
11629 CEFBS_None, // EVMWLSSIAAW = 1095
11630 CEFBS_None, // EVMWLSSIANW = 1096
11631 CEFBS_None, // EVMWLUMI = 1097
11632 CEFBS_None, // EVMWLUMIA = 1098
11633 CEFBS_None, // EVMWLUMIAAW = 1099
11634 CEFBS_None, // EVMWLUMIANW = 1100
11635 CEFBS_None, // EVMWLUSIAAW = 1101
11636 CEFBS_None, // EVMWLUSIANW = 1102
11637 CEFBS_None, // EVMWSMF = 1103
11638 CEFBS_None, // EVMWSMFA = 1104
11639 CEFBS_None, // EVMWSMFAA = 1105
11640 CEFBS_None, // EVMWSMFAN = 1106
11641 CEFBS_None, // EVMWSMI = 1107
11642 CEFBS_None, // EVMWSMIA = 1108
11643 CEFBS_None, // EVMWSMIAA = 1109
11644 CEFBS_None, // EVMWSMIAN = 1110
11645 CEFBS_None, // EVMWSSF = 1111
11646 CEFBS_None, // EVMWSSFA = 1112
11647 CEFBS_None, // EVMWSSFAA = 1113
11648 CEFBS_None, // EVMWSSFAN = 1114
11649 CEFBS_None, // EVMWUMI = 1115
11650 CEFBS_None, // EVMWUMIA = 1116
11651 CEFBS_None, // EVMWUMIAA = 1117
11652 CEFBS_None, // EVMWUMIAN = 1118
11653 CEFBS_None, // EVNAND = 1119
11654 CEFBS_None, // EVNEG = 1120
11655 CEFBS_None, // EVNOR = 1121
11656 CEFBS_None, // EVOR = 1122
11657 CEFBS_None, // EVORC = 1123
11658 CEFBS_None, // EVRLW = 1124
11659 CEFBS_None, // EVRLWI = 1125
11660 CEFBS_None, // EVRNDW = 1126
11661 CEFBS_None, // EVSEL = 1127
11662 CEFBS_None, // EVSLW = 1128
11663 CEFBS_None, // EVSLWI = 1129
11664 CEFBS_None, // EVSPLATFI = 1130
11665 CEFBS_None, // EVSPLATI = 1131
11666 CEFBS_None, // EVSRWIS = 1132
11667 CEFBS_None, // EVSRWIU = 1133
11668 CEFBS_None, // EVSRWS = 1134
11669 CEFBS_None, // EVSRWU = 1135
11670 CEFBS_None, // EVSTDD = 1136
11671 CEFBS_None, // EVSTDDX = 1137
11672 CEFBS_None, // EVSTDH = 1138
11673 CEFBS_None, // EVSTDHX = 1139
11674 CEFBS_None, // EVSTDW = 1140
11675 CEFBS_None, // EVSTDWX = 1141
11676 CEFBS_None, // EVSTWHE = 1142
11677 CEFBS_None, // EVSTWHEX = 1143
11678 CEFBS_None, // EVSTWHO = 1144
11679 CEFBS_None, // EVSTWHOX = 1145
11680 CEFBS_None, // EVSTWWE = 1146
11681 CEFBS_None, // EVSTWWEX = 1147
11682 CEFBS_None, // EVSTWWO = 1148
11683 CEFBS_None, // EVSTWWOX = 1149
11684 CEFBS_None, // EVSUBFSMIAAW = 1150
11685 CEFBS_None, // EVSUBFSSIAAW = 1151
11686 CEFBS_None, // EVSUBFUMIAAW = 1152
11687 CEFBS_None, // EVSUBFUSIAAW = 1153
11688 CEFBS_None, // EVSUBFW = 1154
11689 CEFBS_None, // EVSUBIFW = 1155
11690 CEFBS_None, // EVXOR = 1156
11691 CEFBS_None, // EXTSB = 1157
11692 CEFBS_None, // EXTSB8 = 1158
11693 CEFBS_None, // EXTSB8_32_64 = 1159
11694 CEFBS_None, // EXTSB8_rec = 1160
11695 CEFBS_None, // EXTSB_rec = 1161
11696 CEFBS_None, // EXTSH = 1162
11697 CEFBS_None, // EXTSH8 = 1163
11698 CEFBS_None, // EXTSH8_32_64 = 1164
11699 CEFBS_None, // EXTSH8_rec = 1165
11700 CEFBS_None, // EXTSH_rec = 1166
11701 CEFBS_None, // EXTSW = 1167
11702 CEFBS_None, // EXTSWSLI = 1168
11703 CEFBS_None, // EXTSWSLI_32_64 = 1169
11704 CEFBS_None, // EXTSWSLI_32_64_rec = 1170
11705 CEFBS_None, // EXTSWSLI_rec = 1171
11706 CEFBS_None, // EXTSW_32 = 1172
11707 CEFBS_None, // EXTSW_32_64 = 1173
11708 CEFBS_None, // EXTSW_32_64_rec = 1174
11709 CEFBS_None, // EXTSW_rec = 1175
11710 CEFBS_None, // EnforceIEIO = 1176
11711 CEFBS_None, // FABSD = 1177
11712 CEFBS_None, // FABSD_rec = 1178
11713 CEFBS_None, // FABSS = 1179
11714 CEFBS_None, // FABSS_rec = 1180
11715 CEFBS_None, // FADD = 1181
11716 CEFBS_None, // FADDS = 1182
11717 CEFBS_None, // FADDS_rec = 1183
11718 CEFBS_None, // FADD_rec = 1184
11719 CEFBS_None, // FADDrtz = 1185
11720 CEFBS_None, // FCFID = 1186
11721 CEFBS_None, // FCFIDS = 1187
11722 CEFBS_None, // FCFIDS_rec = 1188
11723 CEFBS_None, // FCFIDU = 1189
11724 CEFBS_None, // FCFIDUS = 1190
11725 CEFBS_None, // FCFIDUS_rec = 1191
11726 CEFBS_None, // FCFIDU_rec = 1192
11727 CEFBS_None, // FCFID_rec = 1193
11728 CEFBS_None, // FCMPOD = 1194
11729 CEFBS_None, // FCMPOS = 1195
11730 CEFBS_None, // FCMPUD = 1196
11731 CEFBS_None, // FCMPUS = 1197
11732 CEFBS_None, // FCPSGND = 1198
11733 CEFBS_None, // FCPSGND_rec = 1199
11734 CEFBS_None, // FCPSGNS = 1200
11735 CEFBS_None, // FCPSGNS_rec = 1201
11736 CEFBS_None, // FCTID = 1202
11737 CEFBS_None, // FCTIDU = 1203
11738 CEFBS_None, // FCTIDUZ = 1204
11739 CEFBS_None, // FCTIDUZ_rec = 1205
11740 CEFBS_None, // FCTIDU_rec = 1206
11741 CEFBS_None, // FCTIDZ = 1207
11742 CEFBS_None, // FCTIDZ_rec = 1208
11743 CEFBS_None, // FCTID_rec = 1209
11744 CEFBS_None, // FCTIW = 1210
11745 CEFBS_None, // FCTIWU = 1211
11746 CEFBS_None, // FCTIWUZ = 1212
11747 CEFBS_None, // FCTIWUZ_rec = 1213
11748 CEFBS_None, // FCTIWU_rec = 1214
11749 CEFBS_None, // FCTIWZ = 1215
11750 CEFBS_None, // FCTIWZ_rec = 1216
11751 CEFBS_None, // FCTIW_rec = 1217
11752 CEFBS_None, // FDIV = 1218
11753 CEFBS_None, // FDIVS = 1219
11754 CEFBS_None, // FDIVS_rec = 1220
11755 CEFBS_None, // FDIV_rec = 1221
11756 CEFBS_None, // FENCE = 1222
11757 CEFBS_None, // FMADD = 1223
11758 CEFBS_None, // FMADDS = 1224
11759 CEFBS_None, // FMADDS_rec = 1225
11760 CEFBS_None, // FMADD_rec = 1226
11761 CEFBS_None, // FMR = 1227
11762 CEFBS_None, // FMR_rec = 1228
11763 CEFBS_None, // FMSUB = 1229
11764 CEFBS_None, // FMSUBS = 1230
11765 CEFBS_None, // FMSUBS_rec = 1231
11766 CEFBS_None, // FMSUB_rec = 1232
11767 CEFBS_None, // FMUL = 1233
11768 CEFBS_None, // FMULS = 1234
11769 CEFBS_None, // FMULS_rec = 1235
11770 CEFBS_None, // FMUL_rec = 1236
11771 CEFBS_None, // FNABSD = 1237
11772 CEFBS_None, // FNABSD_rec = 1238
11773 CEFBS_None, // FNABSS = 1239
11774 CEFBS_None, // FNABSS_rec = 1240
11775 CEFBS_None, // FNEGD = 1241
11776 CEFBS_None, // FNEGD_rec = 1242
11777 CEFBS_None, // FNEGS = 1243
11778 CEFBS_None, // FNEGS_rec = 1244
11779 CEFBS_None, // FNMADD = 1245
11780 CEFBS_None, // FNMADDS = 1246
11781 CEFBS_None, // FNMADDS_rec = 1247
11782 CEFBS_None, // FNMADD_rec = 1248
11783 CEFBS_None, // FNMSUB = 1249
11784 CEFBS_None, // FNMSUBS = 1250
11785 CEFBS_None, // FNMSUBS_rec = 1251
11786 CEFBS_None, // FNMSUB_rec = 1252
11787 CEFBS_None, // FRE = 1253
11788 CEFBS_None, // FRES = 1254
11789 CEFBS_None, // FRES_rec = 1255
11790 CEFBS_None, // FRE_rec = 1256
11791 CEFBS_None, // FRIMD = 1257
11792 CEFBS_None, // FRIMD_rec = 1258
11793 CEFBS_None, // FRIMS = 1259
11794 CEFBS_None, // FRIMS_rec = 1260
11795 CEFBS_None, // FRIND = 1261
11796 CEFBS_None, // FRIND_rec = 1262
11797 CEFBS_None, // FRINS = 1263
11798 CEFBS_None, // FRINS_rec = 1264
11799 CEFBS_None, // FRIPD = 1265
11800 CEFBS_None, // FRIPD_rec = 1266
11801 CEFBS_None, // FRIPS = 1267
11802 CEFBS_None, // FRIPS_rec = 1268
11803 CEFBS_None, // FRIZD = 1269
11804 CEFBS_None, // FRIZD_rec = 1270
11805 CEFBS_None, // FRIZS = 1271
11806 CEFBS_None, // FRIZS_rec = 1272
11807 CEFBS_None, // FRSP = 1273
11808 CEFBS_None, // FRSP_rec = 1274
11809 CEFBS_None, // FRSQRTE = 1275
11810 CEFBS_None, // FRSQRTES = 1276
11811 CEFBS_None, // FRSQRTES_rec = 1277
11812 CEFBS_None, // FRSQRTE_rec = 1278
11813 CEFBS_None, // FSELD = 1279
11814 CEFBS_None, // FSELD_rec = 1280
11815 CEFBS_None, // FSELS = 1281
11816 CEFBS_None, // FSELS_rec = 1282
11817 CEFBS_None, // FSQRT = 1283
11818 CEFBS_None, // FSQRTS = 1284
11819 CEFBS_None, // FSQRTS_rec = 1285
11820 CEFBS_None, // FSQRT_rec = 1286
11821 CEFBS_None, // FSUB = 1287
11822 CEFBS_None, // FSUBS = 1288
11823 CEFBS_None, // FSUBS_rec = 1289
11824 CEFBS_None, // FSUB_rec = 1290
11825 CEFBS_None, // FTDIV = 1291
11826 CEFBS_None, // FTSQRT = 1292
11827 CEFBS_None, // GETtlsADDR = 1293
11828 CEFBS_None, // GETtlsADDR32 = 1294
11829 CEFBS_None, // GETtlsADDR32AIX = 1295
11830 CEFBS_None, // GETtlsADDR64AIX = 1296
11831 CEFBS_None, // GETtlsADDRPCREL = 1297
11832 CEFBS_None, // GETtlsMOD32AIX = 1298
11833 CEFBS_None, // GETtlsMOD64AIX = 1299
11834 CEFBS_None, // GETtlsTpointer32AIX = 1300
11835 CEFBS_None, // GETtlsldADDR = 1301
11836 CEFBS_None, // GETtlsldADDR32 = 1302
11837 CEFBS_None, // GETtlsldADDRPCREL = 1303
11838 CEFBS_None, // HASHCHK = 1304
11839 CEFBS_None, // HASHCHK8 = 1305
11840 CEFBS_None, // HASHCHKP = 1306
11841 CEFBS_None, // HASHCHKP8 = 1307
11842 CEFBS_None, // HASHST = 1308
11843 CEFBS_None, // HASHST8 = 1309
11844 CEFBS_None, // HASHSTP = 1310
11845 CEFBS_None, // HASHSTP8 = 1311
11846 CEFBS_None, // HRFID = 1312
11847 CEFBS_None, // ICBI = 1313
11848 CEFBS_None, // ICBIEP = 1314
11849 CEFBS_None, // ICBLC = 1315
11850 CEFBS_None, // ICBLQ = 1316
11851 CEFBS_None, // ICBT = 1317
11852 CEFBS_None, // ICBTLS = 1318
11853 CEFBS_None, // ICCCI = 1319
11854 CEFBS_None, // ISEL = 1320
11855 CEFBS_None, // ISEL8 = 1321
11856 CEFBS_None, // ISYNC = 1322
11857 CEFBS_None, // LA = 1323
11858 CEFBS_None, // LA8 = 1324
11859 CEFBS_None, // LBARX = 1325
11860 CEFBS_None, // LBARXL = 1326
11861 CEFBS_None, // LBEPX = 1327
11862 CEFBS_None, // LBZ = 1328
11863 CEFBS_None, // LBZ8 = 1329
11864 CEFBS_None, // LBZCIX = 1330
11865 CEFBS_None, // LBZU = 1331
11866 CEFBS_None, // LBZU8 = 1332
11867 CEFBS_None, // LBZUX = 1333
11868 CEFBS_None, // LBZUX8 = 1334
11869 CEFBS_None, // LBZX = 1335
11870 CEFBS_None, // LBZX8 = 1336
11871 CEFBS_None, // LBZXTLS = 1337
11872 CEFBS_None, // LBZXTLS_ = 1338
11873 CEFBS_None, // LBZXTLS_32 = 1339
11874 CEFBS_None, // LD = 1340
11875 CEFBS_None, // LDARX = 1341
11876 CEFBS_None, // LDARXL = 1342
11877 CEFBS_None, // LDAT = 1343
11878 CEFBS_None, // LDBRX = 1344
11879 CEFBS_None, // LDCIX = 1345
11880 CEFBS_None, // LDU = 1346
11881 CEFBS_None, // LDUX = 1347
11882 CEFBS_None, // LDX = 1348
11883 CEFBS_None, // LDXTLS = 1349
11884 CEFBS_None, // LDXTLS_ = 1350
11885 CEFBS_None, // LDgotTprelL = 1351
11886 CEFBS_None, // LDgotTprelL32 = 1352
11887 CEFBS_None, // LDtoc = 1353
11888 CEFBS_None, // LDtocBA = 1354
11889 CEFBS_None, // LDtocCPT = 1355
11890 CEFBS_None, // LDtocJTI = 1356
11891 CEFBS_None, // LDtocL = 1357
11892 CEFBS_None, // LFD = 1358
11893 CEFBS_None, // LFDEPX = 1359
11894 CEFBS_None, // LFDU = 1360
11895 CEFBS_None, // LFDUX = 1361
11896 CEFBS_None, // LFDX = 1362
11897 CEFBS_None, // LFDXTLS = 1363
11898 CEFBS_None, // LFDXTLS_ = 1364
11899 CEFBS_None, // LFIWAX = 1365
11900 CEFBS_None, // LFIWZX = 1366
11901 CEFBS_None, // LFS = 1367
11902 CEFBS_None, // LFSU = 1368
11903 CEFBS_None, // LFSUX = 1369
11904 CEFBS_None, // LFSX = 1370
11905 CEFBS_None, // LFSXTLS = 1371
11906 CEFBS_None, // LFSXTLS_ = 1372
11907 CEFBS_None, // LHA = 1373
11908 CEFBS_None, // LHA8 = 1374
11909 CEFBS_None, // LHARX = 1375
11910 CEFBS_None, // LHARXL = 1376
11911 CEFBS_None, // LHAU = 1377
11912 CEFBS_None, // LHAU8 = 1378
11913 CEFBS_None, // LHAUX = 1379
11914 CEFBS_None, // LHAUX8 = 1380
11915 CEFBS_None, // LHAX = 1381
11916 CEFBS_None, // LHAX8 = 1382
11917 CEFBS_None, // LHAXTLS = 1383
11918 CEFBS_None, // LHAXTLS_ = 1384
11919 CEFBS_None, // LHAXTLS_32 = 1385
11920 CEFBS_None, // LHBRX = 1386
11921 CEFBS_None, // LHBRX8 = 1387
11922 CEFBS_None, // LHEPX = 1388
11923 CEFBS_None, // LHZ = 1389
11924 CEFBS_None, // LHZ8 = 1390
11925 CEFBS_None, // LHZCIX = 1391
11926 CEFBS_None, // LHZU = 1392
11927 CEFBS_None, // LHZU8 = 1393
11928 CEFBS_None, // LHZUX = 1394
11929 CEFBS_None, // LHZUX8 = 1395
11930 CEFBS_None, // LHZX = 1396
11931 CEFBS_None, // LHZX8 = 1397
11932 CEFBS_None, // LHZXTLS = 1398
11933 CEFBS_None, // LHZXTLS_ = 1399
11934 CEFBS_None, // LHZXTLS_32 = 1400
11935 CEFBS_None, // LI = 1401
11936 CEFBS_None, // LI8 = 1402
11937 CEFBS_None, // LIS = 1403
11938 CEFBS_None, // LIS8 = 1404
11939 CEFBS_None, // LMW = 1405
11940 CEFBS_None, // LQ = 1406
11941 CEFBS_None, // LQARX = 1407
11942 CEFBS_None, // LQARXL = 1408
11943 CEFBS_None, // LQX_PSEUDO = 1409
11944 CEFBS_None, // LSWI = 1410
11945 CEFBS_None, // LVEBX = 1411
11946 CEFBS_None, // LVEHX = 1412
11947 CEFBS_None, // LVEWX = 1413
11948 CEFBS_None, // LVSL = 1414
11949 CEFBS_None, // LVSR = 1415
11950 CEFBS_None, // LVX = 1416
11951 CEFBS_None, // LVXL = 1417
11952 CEFBS_None, // LWA = 1418
11953 CEFBS_None, // LWARX = 1419
11954 CEFBS_None, // LWARXL = 1420
11955 CEFBS_None, // LWAT = 1421
11956 CEFBS_None, // LWAUX = 1422
11957 CEFBS_None, // LWAX = 1423
11958 CEFBS_None, // LWAXTLS = 1424
11959 CEFBS_None, // LWAXTLS_ = 1425
11960 CEFBS_None, // LWAXTLS_32 = 1426
11961 CEFBS_None, // LWAX_32 = 1427
11962 CEFBS_None, // LWA_32 = 1428
11963 CEFBS_None, // LWBRX = 1429
11964 CEFBS_None, // LWBRX8 = 1430
11965 CEFBS_None, // LWEPX = 1431
11966 CEFBS_None, // LWZ = 1432
11967 CEFBS_None, // LWZ8 = 1433
11968 CEFBS_None, // LWZCIX = 1434
11969 CEFBS_None, // LWZU = 1435
11970 CEFBS_None, // LWZU8 = 1436
11971 CEFBS_None, // LWZUX = 1437
11972 CEFBS_None, // LWZUX8 = 1438
11973 CEFBS_None, // LWZX = 1439
11974 CEFBS_None, // LWZX8 = 1440
11975 CEFBS_None, // LWZXTLS = 1441
11976 CEFBS_None, // LWZXTLS_ = 1442
11977 CEFBS_None, // LWZXTLS_32 = 1443
11978 CEFBS_None, // LWZtoc = 1444
11979 CEFBS_None, // LWZtocL = 1445
11980 CEFBS_None, // LXSD = 1446
11981 CEFBS_None, // LXSDX = 1447
11982 CEFBS_None, // LXSIBZX = 1448
11983 CEFBS_None, // LXSIHZX = 1449
11984 CEFBS_None, // LXSIWAX = 1450
11985 CEFBS_None, // LXSIWZX = 1451
11986 CEFBS_None, // LXSSP = 1452
11987 CEFBS_None, // LXSSPX = 1453
11988 CEFBS_None, // LXV = 1454
11989 CEFBS_None, // LXVB16X = 1455
11990 CEFBS_None, // LXVD2X = 1456
11991 CEFBS_None, // LXVDSX = 1457
11992 CEFBS_None, // LXVH8X = 1458
11993 CEFBS_None, // LXVKQ = 1459
11994 CEFBS_None, // LXVL = 1460
11995 CEFBS_None, // LXVLL = 1461
11996 CEFBS_None, // LXVP = 1462
11997 CEFBS_None, // LXVPRL = 1463
11998 CEFBS_None, // LXVPRLL = 1464
11999 CEFBS_None, // LXVPX = 1465
12000 CEFBS_None, // LXVRBX = 1466
12001 CEFBS_None, // LXVRDX = 1467
12002 CEFBS_None, // LXVRHX = 1468
12003 CEFBS_None, // LXVRL = 1469
12004 CEFBS_None, // LXVRLL = 1470
12005 CEFBS_None, // LXVRWX = 1471
12006 CEFBS_None, // LXVW4X = 1472
12007 CEFBS_None, // LXVWSX = 1473
12008 CEFBS_None, // LXVX = 1474
12009 CEFBS_None, // MADDHD = 1475
12010 CEFBS_None, // MADDHDU = 1476
12011 CEFBS_None, // MADDLD = 1477
12012 CEFBS_None, // MADDLD8 = 1478
12013 CEFBS_None, // MBAR = 1479
12014 CEFBS_None, // MCRF = 1480
12015 CEFBS_None, // MCRFS = 1481
12016 CEFBS_None, // MCRXRX = 1482
12017 CEFBS_None, // MFBHRBE = 1483
12018 CEFBS_None, // MFCR = 1484
12019 CEFBS_None, // MFCR8 = 1485
12020 CEFBS_None, // MFCTR = 1486
12021 CEFBS_None, // MFCTR8 = 1487
12022 CEFBS_None, // MFDCR = 1488
12023 CEFBS_None, // MFFS = 1489
12024 CEFBS_None, // MFFSCDRN = 1490
12025 CEFBS_None, // MFFSCDRNI = 1491
12026 CEFBS_None, // MFFSCE = 1492
12027 CEFBS_None, // MFFSCRN = 1493
12028 CEFBS_None, // MFFSCRNI = 1494
12029 CEFBS_None, // MFFSL = 1495
12030 CEFBS_None, // MFFS_rec = 1496
12031 CEFBS_None, // MFLR = 1497
12032 CEFBS_None, // MFLR8 = 1498
12033 CEFBS_None, // MFMSR = 1499
12034 CEFBS_None, // MFOCRF = 1500
12035 CEFBS_None, // MFOCRF8 = 1501
12036 CEFBS_None, // MFPMR = 1502
12037 CEFBS_None, // MFSPR = 1503
12038 CEFBS_None, // MFSPR8 = 1504
12039 CEFBS_None, // MFSR = 1505
12040 CEFBS_None, // MFSRIN = 1506
12041 CEFBS_None, // MFTB = 1507
12042 CEFBS_None, // MFTB8 = 1508
12043 CEFBS_None, // MFUDSCR = 1509
12044 CEFBS_None, // MFVRD = 1510
12045 CEFBS_None, // MFVRSAVE = 1511
12046 CEFBS_None, // MFVRSAVEv = 1512
12047 CEFBS_None, // MFVRWZ = 1513
12048 CEFBS_None, // MFVSCR = 1514
12049 CEFBS_None, // MFVSRD = 1515
12050 CEFBS_None, // MFVSRLD = 1516
12051 CEFBS_None, // MFVSRWZ = 1517
12052 CEFBS_None, // MODSD = 1518
12053 CEFBS_None, // MODSW = 1519
12054 CEFBS_None, // MODUD = 1520
12055 CEFBS_None, // MODUW = 1521
12056 CEFBS_None, // MSGSYNC = 1522
12057 CEFBS_None, // MSYNC = 1523
12058 CEFBS_None, // MTCRF = 1524
12059 CEFBS_None, // MTCRF8 = 1525
12060 CEFBS_None, // MTCTR = 1526
12061 CEFBS_None, // MTCTR8 = 1527
12062 CEFBS_None, // MTCTR8loop = 1528
12063 CEFBS_None, // MTCTRloop = 1529
12064 CEFBS_None, // MTDCR = 1530
12065 CEFBS_None, // MTFSB0 = 1531
12066 CEFBS_None, // MTFSB1 = 1532
12067 CEFBS_None, // MTFSF = 1533
12068 CEFBS_None, // MTFSFI = 1534
12069 CEFBS_None, // MTFSFI_rec = 1535
12070 CEFBS_None, // MTFSFIb = 1536
12071 CEFBS_None, // MTFSF_rec = 1537
12072 CEFBS_None, // MTFSFb = 1538
12073 CEFBS_None, // MTLR = 1539
12074 CEFBS_None, // MTLR8 = 1540
12075 CEFBS_None, // MTMSR = 1541
12076 CEFBS_None, // MTMSRD = 1542
12077 CEFBS_None, // MTOCRF = 1543
12078 CEFBS_None, // MTOCRF8 = 1544
12079 CEFBS_None, // MTPMR = 1545
12080 CEFBS_None, // MTSPR = 1546
12081 CEFBS_None, // MTSPR8 = 1547
12082 CEFBS_None, // MTSR = 1548
12083 CEFBS_None, // MTSRIN = 1549
12084 CEFBS_None, // MTUDSCR = 1550
12085 CEFBS_None, // MTVRD = 1551
12086 CEFBS_None, // MTVRSAVE = 1552
12087 CEFBS_None, // MTVRSAVEv = 1553
12088 CEFBS_None, // MTVRWA = 1554
12089 CEFBS_None, // MTVRWZ = 1555
12090 CEFBS_None, // MTVSCR = 1556
12091 CEFBS_None, // MTVSRBM = 1557
12092 CEFBS_None, // MTVSRBMI = 1558
12093 CEFBS_None, // MTVSRD = 1559
12094 CEFBS_None, // MTVSRDD = 1560
12095 CEFBS_None, // MTVSRDM = 1561
12096 CEFBS_None, // MTVSRHM = 1562
12097 CEFBS_None, // MTVSRQM = 1563
12098 CEFBS_None, // MTVSRWA = 1564
12099 CEFBS_None, // MTVSRWM = 1565
12100 CEFBS_None, // MTVSRWS = 1566
12101 CEFBS_None, // MTVSRWZ = 1567
12102 CEFBS_None, // MULHD = 1568
12103 CEFBS_None, // MULHDU = 1569
12104 CEFBS_None, // MULHDU_rec = 1570
12105 CEFBS_None, // MULHD_rec = 1571
12106 CEFBS_None, // MULHW = 1572
12107 CEFBS_None, // MULHWU = 1573
12108 CEFBS_None, // MULHWU_rec = 1574
12109 CEFBS_None, // MULHW_rec = 1575
12110 CEFBS_None, // MULLD = 1576
12111 CEFBS_None, // MULLDO = 1577
12112 CEFBS_None, // MULLDO_rec = 1578
12113 CEFBS_None, // MULLD_rec = 1579
12114 CEFBS_None, // MULLI = 1580
12115 CEFBS_None, // MULLI8 = 1581
12116 CEFBS_None, // MULLW = 1582
12117 CEFBS_None, // MULLWO = 1583
12118 CEFBS_None, // MULLWO_rec = 1584
12119 CEFBS_None, // MULLW_rec = 1585
12120 CEFBS_None, // MoveGOTtoLR = 1586
12121 CEFBS_None, // MovePCtoLR = 1587
12122 CEFBS_None, // MovePCtoLR8 = 1588
12123 CEFBS_None, // NAND = 1589
12124 CEFBS_None, // NAND8 = 1590
12125 CEFBS_None, // NAND8_rec = 1591
12126 CEFBS_None, // NAND_rec = 1592
12127 CEFBS_None, // NAP = 1593
12128 CEFBS_None, // NEG = 1594
12129 CEFBS_None, // NEG8 = 1595
12130 CEFBS_None, // NEG8O = 1596
12131 CEFBS_None, // NEG8O_rec = 1597
12132 CEFBS_None, // NEG8_rec = 1598
12133 CEFBS_None, // NEGO = 1599
12134 CEFBS_None, // NEGO_rec = 1600
12135 CEFBS_None, // NEG_rec = 1601
12136 CEFBS_None, // NOP = 1602
12137 CEFBS_None, // NOP_GT_PWR6 = 1603
12138 CEFBS_None, // NOP_GT_PWR7 = 1604
12139 CEFBS_None, // NOR = 1605
12140 CEFBS_None, // NOR8 = 1606
12141 CEFBS_None, // NOR8_rec = 1607
12142 CEFBS_None, // NOR_rec = 1608
12143 CEFBS_None, // OR = 1609
12144 CEFBS_None, // OR8 = 1610
12145 CEFBS_None, // OR8_rec = 1611
12146 CEFBS_None, // ORC = 1612
12147 CEFBS_None, // ORC8 = 1613
12148 CEFBS_None, // ORC8_rec = 1614
12149 CEFBS_None, // ORC_rec = 1615
12150 CEFBS_None, // ORI = 1616
12151 CEFBS_None, // ORI8 = 1617
12152 CEFBS_None, // ORIS = 1618
12153 CEFBS_None, // ORIS8 = 1619
12154 CEFBS_None, // OR_rec = 1620
12155 CEFBS_None, // PADDI = 1621
12156 CEFBS_None, // PADDI8 = 1622
12157 CEFBS_None, // PADDI8pc = 1623
12158 CEFBS_None, // PADDIdtprel = 1624
12159 CEFBS_None, // PADDIpc = 1625
12160 CEFBS_None, // PDEPD = 1626
12161 CEFBS_None, // PEXTD = 1627
12162 CEFBS_None, // PLA = 1628
12163 CEFBS_None, // PLA8 = 1629
12164 CEFBS_None, // PLA8pc = 1630
12165 CEFBS_None, // PLApc = 1631
12166 CEFBS_None, // PLBZ = 1632
12167 CEFBS_None, // PLBZ8 = 1633
12168 CEFBS_None, // PLBZ8nopc = 1634
12169 CEFBS_None, // PLBZ8onlypc = 1635
12170 CEFBS_None, // PLBZ8pc = 1636
12171 CEFBS_None, // PLBZnopc = 1637
12172 CEFBS_None, // PLBZonlypc = 1638
12173 CEFBS_None, // PLBZpc = 1639
12174 CEFBS_None, // PLD = 1640
12175 CEFBS_None, // PLDnopc = 1641
12176 CEFBS_None, // PLDonlypc = 1642
12177 CEFBS_None, // PLDpc = 1643
12178 CEFBS_None, // PLFD = 1644
12179 CEFBS_None, // PLFDnopc = 1645
12180 CEFBS_None, // PLFDonlypc = 1646
12181 CEFBS_None, // PLFDpc = 1647
12182 CEFBS_None, // PLFS = 1648
12183 CEFBS_None, // PLFSnopc = 1649
12184 CEFBS_None, // PLFSonlypc = 1650
12185 CEFBS_None, // PLFSpc = 1651
12186 CEFBS_None, // PLHA = 1652
12187 CEFBS_None, // PLHA8 = 1653
12188 CEFBS_None, // PLHA8nopc = 1654
12189 CEFBS_None, // PLHA8onlypc = 1655
12190 CEFBS_None, // PLHA8pc = 1656
12191 CEFBS_None, // PLHAnopc = 1657
12192 CEFBS_None, // PLHAonlypc = 1658
12193 CEFBS_None, // PLHApc = 1659
12194 CEFBS_None, // PLHZ = 1660
12195 CEFBS_None, // PLHZ8 = 1661
12196 CEFBS_None, // PLHZ8nopc = 1662
12197 CEFBS_None, // PLHZ8onlypc = 1663
12198 CEFBS_None, // PLHZ8pc = 1664
12199 CEFBS_None, // PLHZnopc = 1665
12200 CEFBS_None, // PLHZonlypc = 1666
12201 CEFBS_None, // PLHZpc = 1667
12202 CEFBS_None, // PLI = 1668
12203 CEFBS_None, // PLI8 = 1669
12204 CEFBS_None, // PLWA = 1670
12205 CEFBS_None, // PLWA8 = 1671
12206 CEFBS_None, // PLWA8nopc = 1672
12207 CEFBS_None, // PLWA8onlypc = 1673
12208 CEFBS_None, // PLWA8pc = 1674
12209 CEFBS_None, // PLWAnopc = 1675
12210 CEFBS_None, // PLWAonlypc = 1676
12211 CEFBS_None, // PLWApc = 1677
12212 CEFBS_None, // PLWZ = 1678
12213 CEFBS_None, // PLWZ8 = 1679
12214 CEFBS_None, // PLWZ8nopc = 1680
12215 CEFBS_None, // PLWZ8onlypc = 1681
12216 CEFBS_None, // PLWZ8pc = 1682
12217 CEFBS_None, // PLWZnopc = 1683
12218 CEFBS_None, // PLWZonlypc = 1684
12219 CEFBS_None, // PLWZpc = 1685
12220 CEFBS_None, // PLXSD = 1686
12221 CEFBS_None, // PLXSDnopc = 1687
12222 CEFBS_None, // PLXSDonlypc = 1688
12223 CEFBS_None, // PLXSDpc = 1689
12224 CEFBS_None, // PLXSSP = 1690
12225 CEFBS_None, // PLXSSPnopc = 1691
12226 CEFBS_None, // PLXSSPonlypc = 1692
12227 CEFBS_None, // PLXSSPpc = 1693
12228 CEFBS_None, // PLXV = 1694
12229 CEFBS_None, // PLXVP = 1695
12230 CEFBS_None, // PLXVPnopc = 1696
12231 CEFBS_None, // PLXVPonlypc = 1697
12232 CEFBS_None, // PLXVPpc = 1698
12233 CEFBS_None, // PLXVnopc = 1699
12234 CEFBS_None, // PLXVonlypc = 1700
12235 CEFBS_None, // PLXVpc = 1701
12236 CEFBS_None, // PMDMXVBF16GERX2 = 1702
12237 CEFBS_None, // PMDMXVBF16GERX2NN = 1703
12238 CEFBS_None, // PMDMXVBF16GERX2NP = 1704
12239 CEFBS_None, // PMDMXVBF16GERX2PN = 1705
12240 CEFBS_None, // PMDMXVBF16GERX2PP = 1706
12241 CEFBS_None, // PMDMXVF16GERX2 = 1707
12242 CEFBS_None, // PMDMXVF16GERX2NN = 1708
12243 CEFBS_None, // PMDMXVF16GERX2NP = 1709
12244 CEFBS_None, // PMDMXVF16GERX2PN = 1710
12245 CEFBS_None, // PMDMXVF16GERX2PP = 1711
12246 CEFBS_None, // PMDMXVI8GERX4 = 1712
12247 CEFBS_None, // PMDMXVI8GERX4PP = 1713
12248 CEFBS_None, // PMDMXVI8GERX4SPP = 1714
12249 CEFBS_None, // PMXVBF16GER2 = 1715
12250 CEFBS_None, // PMXVBF16GER2NN = 1716
12251 CEFBS_None, // PMXVBF16GER2NP = 1717
12252 CEFBS_None, // PMXVBF16GER2PN = 1718
12253 CEFBS_None, // PMXVBF16GER2PP = 1719
12254 CEFBS_None, // PMXVBF16GER2W = 1720
12255 CEFBS_None, // PMXVBF16GER2WNN = 1721
12256 CEFBS_None, // PMXVBF16GER2WNP = 1722
12257 CEFBS_None, // PMXVBF16GER2WPN = 1723
12258 CEFBS_None, // PMXVBF16GER2WPP = 1724
12259 CEFBS_None, // PMXVF16GER2 = 1725
12260 CEFBS_None, // PMXVF16GER2NN = 1726
12261 CEFBS_None, // PMXVF16GER2NP = 1727
12262 CEFBS_None, // PMXVF16GER2PN = 1728
12263 CEFBS_None, // PMXVF16GER2PP = 1729
12264 CEFBS_None, // PMXVF16GER2W = 1730
12265 CEFBS_None, // PMXVF16GER2WNN = 1731
12266 CEFBS_None, // PMXVF16GER2WNP = 1732
12267 CEFBS_None, // PMXVF16GER2WPN = 1733
12268 CEFBS_None, // PMXVF16GER2WPP = 1734
12269 CEFBS_None, // PMXVF32GER = 1735
12270 CEFBS_None, // PMXVF32GERNN = 1736
12271 CEFBS_None, // PMXVF32GERNP = 1737
12272 CEFBS_None, // PMXVF32GERPN = 1738
12273 CEFBS_None, // PMXVF32GERPP = 1739
12274 CEFBS_None, // PMXVF32GERW = 1740
12275 CEFBS_None, // PMXVF32GERWNN = 1741
12276 CEFBS_None, // PMXVF32GERWNP = 1742
12277 CEFBS_None, // PMXVF32GERWPN = 1743
12278 CEFBS_None, // PMXVF32GERWPP = 1744
12279 CEFBS_None, // PMXVF64GER = 1745
12280 CEFBS_None, // PMXVF64GERNN = 1746
12281 CEFBS_None, // PMXVF64GERNP = 1747
12282 CEFBS_None, // PMXVF64GERPN = 1748
12283 CEFBS_None, // PMXVF64GERPP = 1749
12284 CEFBS_None, // PMXVF64GERW = 1750
12285 CEFBS_None, // PMXVF64GERWNN = 1751
12286 CEFBS_None, // PMXVF64GERWNP = 1752
12287 CEFBS_None, // PMXVF64GERWPN = 1753
12288 CEFBS_None, // PMXVF64GERWPP = 1754
12289 CEFBS_None, // PMXVI16GER2 = 1755
12290 CEFBS_None, // PMXVI16GER2PP = 1756
12291 CEFBS_None, // PMXVI16GER2S = 1757
12292 CEFBS_None, // PMXVI16GER2SPP = 1758
12293 CEFBS_None, // PMXVI16GER2SW = 1759
12294 CEFBS_None, // PMXVI16GER2SWPP = 1760
12295 CEFBS_None, // PMXVI16GER2W = 1761
12296 CEFBS_None, // PMXVI16GER2WPP = 1762
12297 CEFBS_None, // PMXVI4GER8 = 1763
12298 CEFBS_None, // PMXVI4GER8PP = 1764
12299 CEFBS_None, // PMXVI4GER8W = 1765
12300 CEFBS_None, // PMXVI4GER8WPP = 1766
12301 CEFBS_None, // PMXVI8GER4 = 1767
12302 CEFBS_None, // PMXVI8GER4PP = 1768
12303 CEFBS_None, // PMXVI8GER4SPP = 1769
12304 CEFBS_None, // PMXVI8GER4W = 1770
12305 CEFBS_None, // PMXVI8GER4WPP = 1771
12306 CEFBS_None, // PMXVI8GER4WSPP = 1772
12307 CEFBS_None, // POPCNTB = 1773
12308 CEFBS_None, // POPCNTB8 = 1774
12309 CEFBS_None, // POPCNTD = 1775
12310 CEFBS_None, // POPCNTW = 1776
12311 CEFBS_None, // PPC32GOT = 1777
12312 CEFBS_None, // PPC32PICGOT = 1778
12313 CEFBS_None, // PREPARE_PROBED_ALLOCA_32 = 1779
12314 CEFBS_None, // PREPARE_PROBED_ALLOCA_64 = 1780
12315 CEFBS_None, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 = 1781
12316 CEFBS_None, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 = 1782
12317 CEFBS_None, // PROBED_ALLOCA_32 = 1783
12318 CEFBS_None, // PROBED_ALLOCA_64 = 1784
12319 CEFBS_None, // PROBED_STACKALLOC_32 = 1785
12320 CEFBS_None, // PROBED_STACKALLOC_64 = 1786
12321 CEFBS_None, // PSTB = 1787
12322 CEFBS_None, // PSTB8 = 1788
12323 CEFBS_None, // PSTB8nopc = 1789
12324 CEFBS_None, // PSTB8onlypc = 1790
12325 CEFBS_None, // PSTB8pc = 1791
12326 CEFBS_None, // PSTBnopc = 1792
12327 CEFBS_None, // PSTBonlypc = 1793
12328 CEFBS_None, // PSTBpc = 1794
12329 CEFBS_None, // PSTD = 1795
12330 CEFBS_None, // PSTDnopc = 1796
12331 CEFBS_None, // PSTDonlypc = 1797
12332 CEFBS_None, // PSTDpc = 1798
12333 CEFBS_None, // PSTFD = 1799
12334 CEFBS_None, // PSTFDnopc = 1800
12335 CEFBS_None, // PSTFDonlypc = 1801
12336 CEFBS_None, // PSTFDpc = 1802
12337 CEFBS_None, // PSTFS = 1803
12338 CEFBS_None, // PSTFSnopc = 1804
12339 CEFBS_None, // PSTFSonlypc = 1805
12340 CEFBS_None, // PSTFSpc = 1806
12341 CEFBS_None, // PSTH = 1807
12342 CEFBS_None, // PSTH8 = 1808
12343 CEFBS_None, // PSTH8nopc = 1809
12344 CEFBS_None, // PSTH8onlypc = 1810
12345 CEFBS_None, // PSTH8pc = 1811
12346 CEFBS_None, // PSTHnopc = 1812
12347 CEFBS_None, // PSTHonlypc = 1813
12348 CEFBS_None, // PSTHpc = 1814
12349 CEFBS_None, // PSTW = 1815
12350 CEFBS_None, // PSTW8 = 1816
12351 CEFBS_None, // PSTW8nopc = 1817
12352 CEFBS_None, // PSTW8onlypc = 1818
12353 CEFBS_None, // PSTW8pc = 1819
12354 CEFBS_None, // PSTWnopc = 1820
12355 CEFBS_None, // PSTWonlypc = 1821
12356 CEFBS_None, // PSTWpc = 1822
12357 CEFBS_None, // PSTXSD = 1823
12358 CEFBS_None, // PSTXSDnopc = 1824
12359 CEFBS_None, // PSTXSDonlypc = 1825
12360 CEFBS_None, // PSTXSDpc = 1826
12361 CEFBS_None, // PSTXSSP = 1827
12362 CEFBS_None, // PSTXSSPnopc = 1828
12363 CEFBS_None, // PSTXSSPonlypc = 1829
12364 CEFBS_None, // PSTXSSPpc = 1830
12365 CEFBS_None, // PSTXV = 1831
12366 CEFBS_None, // PSTXVP = 1832
12367 CEFBS_None, // PSTXVPnopc = 1833
12368 CEFBS_None, // PSTXVPonlypc = 1834
12369 CEFBS_None, // PSTXVPpc = 1835
12370 CEFBS_None, // PSTXVnopc = 1836
12371 CEFBS_None, // PSTXVonlypc = 1837
12372 CEFBS_None, // PSTXVpc = 1838
12373 CEFBS_None, // PseudoEIEIO = 1839
12374 CEFBS_None, // RESTORE_ACC = 1840
12375 CEFBS_None, // RESTORE_CR = 1841
12376 CEFBS_None, // RESTORE_CRBIT = 1842
12377 CEFBS_None, // RESTORE_DMR = 1843
12378 CEFBS_None, // RESTORE_DMRP = 1844
12379 CEFBS_None, // RESTORE_QUADWORD = 1845
12380 CEFBS_None, // RESTORE_UACC = 1846
12381 CEFBS_None, // RESTORE_WACC = 1847
12382 CEFBS_None, // RFCI = 1848
12383 CEFBS_None, // RFDI = 1849
12384 CEFBS_None, // RFEBB = 1850
12385 CEFBS_None, // RFI = 1851
12386 CEFBS_None, // RFID = 1852
12387 CEFBS_None, // RFMCI = 1853
12388 CEFBS_None, // RLDCL = 1854
12389 CEFBS_None, // RLDCL_rec = 1855
12390 CEFBS_None, // RLDCR = 1856
12391 CEFBS_None, // RLDCR_rec = 1857
12392 CEFBS_None, // RLDIC = 1858
12393 CEFBS_None, // RLDICL = 1859
12394 CEFBS_None, // RLDICL_32 = 1860
12395 CEFBS_None, // RLDICL_32_64 = 1861
12396 CEFBS_None, // RLDICL_32_rec = 1862
12397 CEFBS_None, // RLDICL_rec = 1863
12398 CEFBS_None, // RLDICR = 1864
12399 CEFBS_None, // RLDICR_32 = 1865
12400 CEFBS_None, // RLDICR_rec = 1866
12401 CEFBS_None, // RLDIC_rec = 1867
12402 CEFBS_None, // RLDIMI = 1868
12403 CEFBS_None, // RLDIMI_rec = 1869
12404 CEFBS_None, // RLWIMI = 1870
12405 CEFBS_None, // RLWIMI8 = 1871
12406 CEFBS_None, // RLWIMI8_rec = 1872
12407 CEFBS_None, // RLWIMI_rec = 1873
12408 CEFBS_None, // RLWINM = 1874
12409 CEFBS_None, // RLWINM8 = 1875
12410 CEFBS_None, // RLWINM8_rec = 1876
12411 CEFBS_None, // RLWINM_rec = 1877
12412 CEFBS_None, // RLWNM = 1878
12413 CEFBS_None, // RLWNM8 = 1879
12414 CEFBS_None, // RLWNM8_rec = 1880
12415 CEFBS_None, // RLWNM_rec = 1881
12416 CEFBS_None, // ReadTB = 1882
12417 CEFBS_None, // SC = 1883
12418 CEFBS_None, // SCV = 1884
12419 CEFBS_None, // SELECT_CC_F16 = 1885
12420 CEFBS_None, // SELECT_CC_F4 = 1886
12421 CEFBS_None, // SELECT_CC_F8 = 1887
12422 CEFBS_None, // SELECT_CC_I4 = 1888
12423 CEFBS_None, // SELECT_CC_I8 = 1889
12424 CEFBS_None, // SELECT_CC_SPE = 1890
12425 CEFBS_None, // SELECT_CC_SPE4 = 1891
12426 CEFBS_None, // SELECT_CC_VRRC = 1892
12427 CEFBS_None, // SELECT_CC_VSFRC = 1893
12428 CEFBS_None, // SELECT_CC_VSRC = 1894
12429 CEFBS_None, // SELECT_CC_VSSRC = 1895
12430 CEFBS_None, // SELECT_F16 = 1896
12431 CEFBS_None, // SELECT_F4 = 1897
12432 CEFBS_None, // SELECT_F8 = 1898
12433 CEFBS_None, // SELECT_I4 = 1899
12434 CEFBS_None, // SELECT_I8 = 1900
12435 CEFBS_None, // SELECT_SPE = 1901
12436 CEFBS_None, // SELECT_SPE4 = 1902
12437 CEFBS_None, // SELECT_VRRC = 1903
12438 CEFBS_None, // SELECT_VSFRC = 1904
12439 CEFBS_None, // SELECT_VSRC = 1905
12440 CEFBS_None, // SELECT_VSSRC = 1906
12441 CEFBS_None, // SETB = 1907
12442 CEFBS_None, // SETB8 = 1908
12443 CEFBS_None, // SETBC = 1909
12444 CEFBS_None, // SETBC8 = 1910
12445 CEFBS_None, // SETBCR = 1911
12446 CEFBS_None, // SETBCR8 = 1912
12447 CEFBS_None, // SETFLM = 1913
12448 CEFBS_None, // SETNBC = 1914
12449 CEFBS_None, // SETNBC8 = 1915
12450 CEFBS_None, // SETNBCR = 1916
12451 CEFBS_None, // SETNBCR8 = 1917
12452 CEFBS_None, // SETRND = 1918
12453 CEFBS_None, // SETRNDi = 1919
12454 CEFBS_None, // SLBFEE_rec = 1920
12455 CEFBS_None, // SLBIA = 1921
12456 CEFBS_None, // SLBIE = 1922
12457 CEFBS_None, // SLBIEG = 1923
12458 CEFBS_None, // SLBMFEE = 1924
12459 CEFBS_None, // SLBMFEV = 1925
12460 CEFBS_None, // SLBMTE = 1926
12461 CEFBS_None, // SLBSYNC = 1927
12462 CEFBS_None, // SLD = 1928
12463 CEFBS_None, // SLD_rec = 1929
12464 CEFBS_None, // SLW = 1930
12465 CEFBS_None, // SLW8 = 1931
12466 CEFBS_None, // SLW8_rec = 1932
12467 CEFBS_None, // SLW_rec = 1933
12468 CEFBS_None, // SPELWZ = 1934
12469 CEFBS_None, // SPELWZX = 1935
12470 CEFBS_None, // SPESTW = 1936
12471 CEFBS_None, // SPESTWX = 1937
12472 CEFBS_None, // SPILL_ACC = 1938
12473 CEFBS_None, // SPILL_CR = 1939
12474 CEFBS_None, // SPILL_CRBIT = 1940
12475 CEFBS_None, // SPILL_DMR = 1941
12476 CEFBS_None, // SPILL_DMRP = 1942
12477 CEFBS_None, // SPILL_QUADWORD = 1943
12478 CEFBS_None, // SPILL_UACC = 1944
12479 CEFBS_None, // SPILL_WACC = 1945
12480 CEFBS_None, // SPLIT_QUADWORD = 1946
12481 CEFBS_None, // SRAD = 1947
12482 CEFBS_None, // SRADI = 1948
12483 CEFBS_None, // SRADI_32 = 1949
12484 CEFBS_None, // SRADI_rec = 1950
12485 CEFBS_None, // SRAD_rec = 1951
12486 CEFBS_None, // SRAW = 1952
12487 CEFBS_None, // SRAW8 = 1953
12488 CEFBS_None, // SRAW8_rec = 1954
12489 CEFBS_None, // SRAWI = 1955
12490 CEFBS_None, // SRAWI8 = 1956
12491 CEFBS_None, // SRAWI8_rec = 1957
12492 CEFBS_None, // SRAWI_rec = 1958
12493 CEFBS_None, // SRAW_rec = 1959
12494 CEFBS_None, // SRD = 1960
12495 CEFBS_None, // SRD_rec = 1961
12496 CEFBS_None, // SRW = 1962
12497 CEFBS_None, // SRW8 = 1963
12498 CEFBS_None, // SRW8_rec = 1964
12499 CEFBS_None, // SRW_rec = 1965
12500 CEFBS_None, // STB = 1966
12501 CEFBS_None, // STB8 = 1967
12502 CEFBS_None, // STBCIX = 1968
12503 CEFBS_None, // STBCX = 1969
12504 CEFBS_None, // STBEPX = 1970
12505 CEFBS_None, // STBU = 1971
12506 CEFBS_None, // STBU8 = 1972
12507 CEFBS_None, // STBUX = 1973
12508 CEFBS_None, // STBUX8 = 1974
12509 CEFBS_None, // STBX = 1975
12510 CEFBS_None, // STBX8 = 1976
12511 CEFBS_None, // STBXTLS = 1977
12512 CEFBS_None, // STBXTLS_ = 1978
12513 CEFBS_None, // STBXTLS_32 = 1979
12514 CEFBS_None, // STD = 1980
12515 CEFBS_None, // STDAT = 1981
12516 CEFBS_None, // STDBRX = 1982
12517 CEFBS_None, // STDCIX = 1983
12518 CEFBS_None, // STDCX = 1984
12519 CEFBS_None, // STDU = 1985
12520 CEFBS_None, // STDUX = 1986
12521 CEFBS_None, // STDX = 1987
12522 CEFBS_None, // STDXTLS = 1988
12523 CEFBS_None, // STDXTLS_ = 1989
12524 CEFBS_None, // STFD = 1990
12525 CEFBS_None, // STFDEPX = 1991
12526 CEFBS_None, // STFDU = 1992
12527 CEFBS_None, // STFDUX = 1993
12528 CEFBS_None, // STFDX = 1994
12529 CEFBS_None, // STFDXTLS = 1995
12530 CEFBS_None, // STFDXTLS_ = 1996
12531 CEFBS_None, // STFIWX = 1997
12532 CEFBS_None, // STFS = 1998
12533 CEFBS_None, // STFSU = 1999
12534 CEFBS_None, // STFSUX = 2000
12535 CEFBS_None, // STFSX = 2001
12536 CEFBS_None, // STFSXTLS = 2002
12537 CEFBS_None, // STFSXTLS_ = 2003
12538 CEFBS_None, // STH = 2004
12539 CEFBS_None, // STH8 = 2005
12540 CEFBS_None, // STHBRX = 2006
12541 CEFBS_None, // STHCIX = 2007
12542 CEFBS_None, // STHCX = 2008
12543 CEFBS_None, // STHEPX = 2009
12544 CEFBS_None, // STHU = 2010
12545 CEFBS_None, // STHU8 = 2011
12546 CEFBS_None, // STHUX = 2012
12547 CEFBS_None, // STHUX8 = 2013
12548 CEFBS_None, // STHX = 2014
12549 CEFBS_None, // STHX8 = 2015
12550 CEFBS_None, // STHXTLS = 2016
12551 CEFBS_None, // STHXTLS_ = 2017
12552 CEFBS_None, // STHXTLS_32 = 2018
12553 CEFBS_None, // STMW = 2019
12554 CEFBS_None, // STOP = 2020
12555 CEFBS_None, // STQ = 2021
12556 CEFBS_None, // STQCX = 2022
12557 CEFBS_None, // STQX_PSEUDO = 2023
12558 CEFBS_None, // STSWI = 2024
12559 CEFBS_None, // STVEBX = 2025
12560 CEFBS_None, // STVEHX = 2026
12561 CEFBS_None, // STVEWX = 2027
12562 CEFBS_None, // STVX = 2028
12563 CEFBS_None, // STVXL = 2029
12564 CEFBS_None, // STW = 2030
12565 CEFBS_None, // STW8 = 2031
12566 CEFBS_None, // STWAT = 2032
12567 CEFBS_None, // STWBRX = 2033
12568 CEFBS_None, // STWCIX = 2034
12569 CEFBS_None, // STWCX = 2035
12570 CEFBS_None, // STWEPX = 2036
12571 CEFBS_None, // STWU = 2037
12572 CEFBS_None, // STWU8 = 2038
12573 CEFBS_None, // STWUX = 2039
12574 CEFBS_None, // STWUX8 = 2040
12575 CEFBS_None, // STWX = 2041
12576 CEFBS_None, // STWX8 = 2042
12577 CEFBS_None, // STWXTLS = 2043
12578 CEFBS_None, // STWXTLS_ = 2044
12579 CEFBS_None, // STWXTLS_32 = 2045
12580 CEFBS_None, // STXSD = 2046
12581 CEFBS_None, // STXSDX = 2047
12582 CEFBS_None, // STXSIBX = 2048
12583 CEFBS_None, // STXSIBXv = 2049
12584 CEFBS_None, // STXSIHX = 2050
12585 CEFBS_None, // STXSIHXv = 2051
12586 CEFBS_None, // STXSIWX = 2052
12587 CEFBS_None, // STXSSP = 2053
12588 CEFBS_None, // STXSSPX = 2054
12589 CEFBS_None, // STXV = 2055
12590 CEFBS_None, // STXVB16X = 2056
12591 CEFBS_None, // STXVD2X = 2057
12592 CEFBS_None, // STXVH8X = 2058
12593 CEFBS_None, // STXVL = 2059
12594 CEFBS_None, // STXVLL = 2060
12595 CEFBS_None, // STXVP = 2061
12596 CEFBS_None, // STXVPRL = 2062
12597 CEFBS_None, // STXVPRLL = 2063
12598 CEFBS_None, // STXVPX = 2064
12599 CEFBS_None, // STXVRBX = 2065
12600 CEFBS_None, // STXVRDX = 2066
12601 CEFBS_None, // STXVRHX = 2067
12602 CEFBS_None, // STXVRL = 2068
12603 CEFBS_None, // STXVRLL = 2069
12604 CEFBS_None, // STXVRWX = 2070
12605 CEFBS_None, // STXVW4X = 2071
12606 CEFBS_None, // STXVX = 2072
12607 CEFBS_None, // SUBF = 2073
12608 CEFBS_None, // SUBF8 = 2074
12609 CEFBS_None, // SUBF8O = 2075
12610 CEFBS_None, // SUBF8O_rec = 2076
12611 CEFBS_None, // SUBF8_rec = 2077
12612 CEFBS_None, // SUBFC = 2078
12613 CEFBS_None, // SUBFC8 = 2079
12614 CEFBS_None, // SUBFC8O = 2080
12615 CEFBS_None, // SUBFC8O_rec = 2081
12616 CEFBS_None, // SUBFC8_rec = 2082
12617 CEFBS_None, // SUBFCO = 2083
12618 CEFBS_None, // SUBFCO_rec = 2084
12619 CEFBS_None, // SUBFC_rec = 2085
12620 CEFBS_None, // SUBFE = 2086
12621 CEFBS_None, // SUBFE8 = 2087
12622 CEFBS_None, // SUBFE8O = 2088
12623 CEFBS_None, // SUBFE8O_rec = 2089
12624 CEFBS_None, // SUBFE8_rec = 2090
12625 CEFBS_None, // SUBFEO = 2091
12626 CEFBS_None, // SUBFEO_rec = 2092
12627 CEFBS_None, // SUBFE_rec = 2093
12628 CEFBS_None, // SUBFIC = 2094
12629 CEFBS_None, // SUBFIC8 = 2095
12630 CEFBS_None, // SUBFME = 2096
12631 CEFBS_None, // SUBFME8 = 2097
12632 CEFBS_None, // SUBFME8O = 2098
12633 CEFBS_None, // SUBFME8O_rec = 2099
12634 CEFBS_None, // SUBFME8_rec = 2100
12635 CEFBS_None, // SUBFMEO = 2101
12636 CEFBS_None, // SUBFMEO_rec = 2102
12637 CEFBS_None, // SUBFME_rec = 2103
12638 CEFBS_None, // SUBFO = 2104
12639 CEFBS_None, // SUBFO_rec = 2105
12640 CEFBS_None, // SUBFUS = 2106
12641 CEFBS_None, // SUBFUS_rec = 2107
12642 CEFBS_None, // SUBFZE = 2108
12643 CEFBS_None, // SUBFZE8 = 2109
12644 CEFBS_None, // SUBFZE8O = 2110
12645 CEFBS_None, // SUBFZE8O_rec = 2111
12646 CEFBS_None, // SUBFZE8_rec = 2112
12647 CEFBS_None, // SUBFZEO = 2113
12648 CEFBS_None, // SUBFZEO_rec = 2114
12649 CEFBS_None, // SUBFZE_rec = 2115
12650 CEFBS_None, // SUBF_rec = 2116
12651 CEFBS_None, // SYNC = 2117
12652 CEFBS_None, // SYNCP10 = 2118
12653 CEFBS_None, // TABORT = 2119
12654 CEFBS_None, // TABORTDC = 2120
12655 CEFBS_None, // TABORTDCI = 2121
12656 CEFBS_None, // TABORTWC = 2122
12657 CEFBS_None, // TABORTWCI = 2123
12658 CEFBS_None, // TAILB = 2124
12659 CEFBS_None, // TAILB8 = 2125
12660 CEFBS_None, // TAILBA = 2126
12661 CEFBS_None, // TAILBA8 = 2127
12662 CEFBS_None, // TAILBCTR = 2128
12663 CEFBS_None, // TAILBCTR8 = 2129
12664 CEFBS_None, // TBEGIN = 2130
12665 CEFBS_None, // TBEGIN_RET = 2131
12666 CEFBS_None, // TCHECK = 2132
12667 CEFBS_None, // TCHECK_RET = 2133
12668 CEFBS_None, // TCRETURNai = 2134
12669 CEFBS_None, // TCRETURNai8 = 2135
12670 CEFBS_None, // TCRETURNdi = 2136
12671 CEFBS_None, // TCRETURNdi8 = 2137
12672 CEFBS_None, // TCRETURNri = 2138
12673 CEFBS_None, // TCRETURNri8 = 2139
12674 CEFBS_None, // TD = 2140
12675 CEFBS_None, // TDI = 2141
12676 CEFBS_None, // TEND = 2142
12677 CEFBS_None, // TLBIA = 2143
12678 CEFBS_None, // TLBIE = 2144
12679 CEFBS_None, // TLBIEL = 2145
12680 CEFBS_None, // TLBILX = 2146
12681 CEFBS_None, // TLBIVAX = 2147
12682 CEFBS_None, // TLBLD = 2148
12683 CEFBS_None, // TLBLI = 2149
12684 CEFBS_None, // TLBRE = 2150
12685 CEFBS_None, // TLBRE2 = 2151
12686 CEFBS_None, // TLBSX = 2152
12687 CEFBS_None, // TLBSX2 = 2153
12688 CEFBS_None, // TLBSX2D = 2154
12689 CEFBS_None, // TLBSYNC = 2155
12690 CEFBS_None, // TLBWE = 2156
12691 CEFBS_None, // TLBWE2 = 2157
12692 CEFBS_None, // TLSGDAIX = 2158
12693 CEFBS_None, // TLSGDAIX8 = 2159
12694 CEFBS_None, // TLSLDAIX = 2160
12695 CEFBS_None, // TLSLDAIX8 = 2161
12696 CEFBS_None, // TRAP = 2162
12697 CEFBS_None, // TRECHKPT = 2163
12698 CEFBS_None, // TRECLAIM = 2164
12699 CEFBS_None, // TSR = 2165
12700 CEFBS_None, // TW = 2166
12701 CEFBS_None, // TWI = 2167
12702 CEFBS_None, // UNENCODED_NOP = 2168
12703 CEFBS_None, // UpdateGBR = 2169
12704 CEFBS_None, // VABSDUB = 2170
12705 CEFBS_None, // VABSDUH = 2171
12706 CEFBS_None, // VABSDUW = 2172
12707 CEFBS_None, // VADDCUQ = 2173
12708 CEFBS_None, // VADDCUW = 2174
12709 CEFBS_None, // VADDECUQ = 2175
12710 CEFBS_None, // VADDEUQM = 2176
12711 CEFBS_None, // VADDFP = 2177
12712 CEFBS_None, // VADDSBS = 2178
12713 CEFBS_None, // VADDSHS = 2179
12714 CEFBS_None, // VADDSWS = 2180
12715 CEFBS_None, // VADDUBM = 2181
12716 CEFBS_None, // VADDUBS = 2182
12717 CEFBS_None, // VADDUDM = 2183
12718 CEFBS_None, // VADDUHM = 2184
12719 CEFBS_None, // VADDUHS = 2185
12720 CEFBS_None, // VADDUQM = 2186
12721 CEFBS_None, // VADDUWM = 2187
12722 CEFBS_None, // VADDUWS = 2188
12723 CEFBS_None, // VAND = 2189
12724 CEFBS_None, // VANDC = 2190
12725 CEFBS_None, // VAVGSB = 2191
12726 CEFBS_None, // VAVGSH = 2192
12727 CEFBS_None, // VAVGSW = 2193
12728 CEFBS_None, // VAVGUB = 2194
12729 CEFBS_None, // VAVGUH = 2195
12730 CEFBS_None, // VAVGUW = 2196
12731 CEFBS_None, // VBPERMD = 2197
12732 CEFBS_None, // VBPERMQ = 2198
12733 CEFBS_None, // VCFSX = 2199
12734 CEFBS_None, // VCFSX_0 = 2200
12735 CEFBS_None, // VCFUGED = 2201
12736 CEFBS_None, // VCFUX = 2202
12737 CEFBS_None, // VCFUX_0 = 2203
12738 CEFBS_None, // VCIPHER = 2204
12739 CEFBS_None, // VCIPHERLAST = 2205
12740 CEFBS_None, // VCLRLB = 2206
12741 CEFBS_None, // VCLRRB = 2207
12742 CEFBS_None, // VCLZB = 2208
12743 CEFBS_None, // VCLZD = 2209
12744 CEFBS_None, // VCLZDM = 2210
12745 CEFBS_None, // VCLZH = 2211
12746 CEFBS_None, // VCLZLSBB = 2212
12747 CEFBS_None, // VCLZW = 2213
12748 CEFBS_None, // VCMPBFP = 2214
12749 CEFBS_None, // VCMPBFP_rec = 2215
12750 CEFBS_None, // VCMPEQFP = 2216
12751 CEFBS_None, // VCMPEQFP_rec = 2217
12752 CEFBS_None, // VCMPEQUB = 2218
12753 CEFBS_None, // VCMPEQUB_rec = 2219
12754 CEFBS_None, // VCMPEQUD = 2220
12755 CEFBS_None, // VCMPEQUD_rec = 2221
12756 CEFBS_None, // VCMPEQUH = 2222
12757 CEFBS_None, // VCMPEQUH_rec = 2223
12758 CEFBS_None, // VCMPEQUQ = 2224
12759 CEFBS_None, // VCMPEQUQ_rec = 2225
12760 CEFBS_None, // VCMPEQUW = 2226
12761 CEFBS_None, // VCMPEQUW_rec = 2227
12762 CEFBS_None, // VCMPGEFP = 2228
12763 CEFBS_None, // VCMPGEFP_rec = 2229
12764 CEFBS_None, // VCMPGTFP = 2230
12765 CEFBS_None, // VCMPGTFP_rec = 2231
12766 CEFBS_None, // VCMPGTSB = 2232
12767 CEFBS_None, // VCMPGTSB_rec = 2233
12768 CEFBS_None, // VCMPGTSD = 2234
12769 CEFBS_None, // VCMPGTSD_rec = 2235
12770 CEFBS_None, // VCMPGTSH = 2236
12771 CEFBS_None, // VCMPGTSH_rec = 2237
12772 CEFBS_None, // VCMPGTSQ = 2238
12773 CEFBS_None, // VCMPGTSQ_rec = 2239
12774 CEFBS_None, // VCMPGTSW = 2240
12775 CEFBS_None, // VCMPGTSW_rec = 2241
12776 CEFBS_None, // VCMPGTUB = 2242
12777 CEFBS_None, // VCMPGTUB_rec = 2243
12778 CEFBS_None, // VCMPGTUD = 2244
12779 CEFBS_None, // VCMPGTUD_rec = 2245
12780 CEFBS_None, // VCMPGTUH = 2246
12781 CEFBS_None, // VCMPGTUH_rec = 2247
12782 CEFBS_None, // VCMPGTUQ = 2248
12783 CEFBS_None, // VCMPGTUQ_rec = 2249
12784 CEFBS_None, // VCMPGTUW = 2250
12785 CEFBS_None, // VCMPGTUW_rec = 2251
12786 CEFBS_None, // VCMPNEB = 2252
12787 CEFBS_None, // VCMPNEB_rec = 2253
12788 CEFBS_None, // VCMPNEH = 2254
12789 CEFBS_None, // VCMPNEH_rec = 2255
12790 CEFBS_None, // VCMPNEW = 2256
12791 CEFBS_None, // VCMPNEW_rec = 2257
12792 CEFBS_None, // VCMPNEZB = 2258
12793 CEFBS_None, // VCMPNEZB_rec = 2259
12794 CEFBS_None, // VCMPNEZH = 2260
12795 CEFBS_None, // VCMPNEZH_rec = 2261
12796 CEFBS_None, // VCMPNEZW = 2262
12797 CEFBS_None, // VCMPNEZW_rec = 2263
12798 CEFBS_None, // VCMPSQ = 2264
12799 CEFBS_None, // VCMPUQ = 2265
12800 CEFBS_None, // VCNTMBB = 2266
12801 CEFBS_None, // VCNTMBD = 2267
12802 CEFBS_None, // VCNTMBH = 2268
12803 CEFBS_None, // VCNTMBW = 2269
12804 CEFBS_None, // VCTSXS = 2270
12805 CEFBS_None, // VCTSXS_0 = 2271
12806 CEFBS_None, // VCTUXS = 2272
12807 CEFBS_None, // VCTUXS_0 = 2273
12808 CEFBS_None, // VCTZB = 2274
12809 CEFBS_None, // VCTZD = 2275
12810 CEFBS_None, // VCTZDM = 2276
12811 CEFBS_None, // VCTZH = 2277
12812 CEFBS_None, // VCTZLSBB = 2278
12813 CEFBS_None, // VCTZW = 2279
12814 CEFBS_None, // VDIVESD = 2280
12815 CEFBS_None, // VDIVESQ = 2281
12816 CEFBS_None, // VDIVESW = 2282
12817 CEFBS_None, // VDIVEUD = 2283
12818 CEFBS_None, // VDIVEUQ = 2284
12819 CEFBS_None, // VDIVEUW = 2285
12820 CEFBS_None, // VDIVSD = 2286
12821 CEFBS_None, // VDIVSQ = 2287
12822 CEFBS_None, // VDIVSW = 2288
12823 CEFBS_None, // VDIVUD = 2289
12824 CEFBS_None, // VDIVUQ = 2290
12825 CEFBS_None, // VDIVUW = 2291
12826 CEFBS_None, // VEQV = 2292
12827 CEFBS_None, // VEXPANDBM = 2293
12828 CEFBS_None, // VEXPANDDM = 2294
12829 CEFBS_None, // VEXPANDHM = 2295
12830 CEFBS_None, // VEXPANDQM = 2296
12831 CEFBS_None, // VEXPANDWM = 2297
12832 CEFBS_None, // VEXPTEFP = 2298
12833 CEFBS_None, // VEXTDDVLX = 2299
12834 CEFBS_None, // VEXTDDVRX = 2300
12835 CEFBS_None, // VEXTDUBVLX = 2301
12836 CEFBS_None, // VEXTDUBVRX = 2302
12837 CEFBS_None, // VEXTDUHVLX = 2303
12838 CEFBS_None, // VEXTDUHVRX = 2304
12839 CEFBS_None, // VEXTDUWVLX = 2305
12840 CEFBS_None, // VEXTDUWVRX = 2306
12841 CEFBS_None, // VEXTRACTBM = 2307
12842 CEFBS_None, // VEXTRACTD = 2308
12843 CEFBS_None, // VEXTRACTDM = 2309
12844 CEFBS_None, // VEXTRACTHM = 2310
12845 CEFBS_None, // VEXTRACTQM = 2311
12846 CEFBS_None, // VEXTRACTUB = 2312
12847 CEFBS_None, // VEXTRACTUH = 2313
12848 CEFBS_None, // VEXTRACTUW = 2314
12849 CEFBS_None, // VEXTRACTWM = 2315
12850 CEFBS_None, // VEXTSB2D = 2316
12851 CEFBS_None, // VEXTSB2Ds = 2317
12852 CEFBS_None, // VEXTSB2W = 2318
12853 CEFBS_None, // VEXTSB2Ws = 2319
12854 CEFBS_None, // VEXTSD2Q = 2320
12855 CEFBS_None, // VEXTSH2D = 2321
12856 CEFBS_None, // VEXTSH2Ds = 2322
12857 CEFBS_None, // VEXTSH2W = 2323
12858 CEFBS_None, // VEXTSH2Ws = 2324
12859 CEFBS_None, // VEXTSW2D = 2325
12860 CEFBS_None, // VEXTSW2Ds = 2326
12861 CEFBS_None, // VEXTUBLX = 2327
12862 CEFBS_None, // VEXTUBRX = 2328
12863 CEFBS_None, // VEXTUHLX = 2329
12864 CEFBS_None, // VEXTUHRX = 2330
12865 CEFBS_None, // VEXTUWLX = 2331
12866 CEFBS_None, // VEXTUWRX = 2332
12867 CEFBS_None, // VGBBD = 2333
12868 CEFBS_None, // VGNB = 2334
12869 CEFBS_None, // VINSBLX = 2335
12870 CEFBS_None, // VINSBRX = 2336
12871 CEFBS_None, // VINSBVLX = 2337
12872 CEFBS_None, // VINSBVRX = 2338
12873 CEFBS_None, // VINSD = 2339
12874 CEFBS_None, // VINSDLX = 2340
12875 CEFBS_None, // VINSDRX = 2341
12876 CEFBS_None, // VINSERTB = 2342
12877 CEFBS_None, // VINSERTD = 2343
12878 CEFBS_None, // VINSERTH = 2344
12879 CEFBS_None, // VINSERTW = 2345
12880 CEFBS_None, // VINSHLX = 2346
12881 CEFBS_None, // VINSHRX = 2347
12882 CEFBS_None, // VINSHVLX = 2348
12883 CEFBS_None, // VINSHVRX = 2349
12884 CEFBS_None, // VINSW = 2350
12885 CEFBS_None, // VINSWLX = 2351
12886 CEFBS_None, // VINSWRX = 2352
12887 CEFBS_None, // VINSWVLX = 2353
12888 CEFBS_None, // VINSWVRX = 2354
12889 CEFBS_None, // VLOGEFP = 2355
12890 CEFBS_None, // VMADDFP = 2356
12891 CEFBS_None, // VMAXFP = 2357
12892 CEFBS_None, // VMAXSB = 2358
12893 CEFBS_None, // VMAXSD = 2359
12894 CEFBS_None, // VMAXSH = 2360
12895 CEFBS_None, // VMAXSW = 2361
12896 CEFBS_None, // VMAXUB = 2362
12897 CEFBS_None, // VMAXUD = 2363
12898 CEFBS_None, // VMAXUH = 2364
12899 CEFBS_None, // VMAXUW = 2365
12900 CEFBS_None, // VMHADDSHS = 2366
12901 CEFBS_None, // VMHRADDSHS = 2367
12902 CEFBS_None, // VMINFP = 2368
12903 CEFBS_None, // VMINSB = 2369
12904 CEFBS_None, // VMINSD = 2370
12905 CEFBS_None, // VMINSH = 2371
12906 CEFBS_None, // VMINSW = 2372
12907 CEFBS_None, // VMINUB = 2373
12908 CEFBS_None, // VMINUD = 2374
12909 CEFBS_None, // VMINUH = 2375
12910 CEFBS_None, // VMINUW = 2376
12911 CEFBS_None, // VMLADDUHM = 2377
12912 CEFBS_None, // VMODSD = 2378
12913 CEFBS_None, // VMODSQ = 2379
12914 CEFBS_None, // VMODSW = 2380
12915 CEFBS_None, // VMODUD = 2381
12916 CEFBS_None, // VMODUQ = 2382
12917 CEFBS_None, // VMODUW = 2383
12918 CEFBS_None, // VMRGEW = 2384
12919 CEFBS_None, // VMRGHB = 2385
12920 CEFBS_None, // VMRGHH = 2386
12921 CEFBS_None, // VMRGHW = 2387
12922 CEFBS_None, // VMRGLB = 2388
12923 CEFBS_None, // VMRGLH = 2389
12924 CEFBS_None, // VMRGLW = 2390
12925 CEFBS_None, // VMRGOW = 2391
12926 CEFBS_None, // VMSUMCUD = 2392
12927 CEFBS_None, // VMSUMMBM = 2393
12928 CEFBS_None, // VMSUMSHM = 2394
12929 CEFBS_None, // VMSUMSHS = 2395
12930 CEFBS_None, // VMSUMUBM = 2396
12931 CEFBS_None, // VMSUMUDM = 2397
12932 CEFBS_None, // VMSUMUHM = 2398
12933 CEFBS_None, // VMSUMUHS = 2399
12934 CEFBS_None, // VMUL10CUQ = 2400
12935 CEFBS_None, // VMUL10ECUQ = 2401
12936 CEFBS_None, // VMUL10EUQ = 2402
12937 CEFBS_None, // VMUL10UQ = 2403
12938 CEFBS_None, // VMULESB = 2404
12939 CEFBS_None, // VMULESD = 2405
12940 CEFBS_None, // VMULESH = 2406
12941 CEFBS_None, // VMULESW = 2407
12942 CEFBS_None, // VMULEUB = 2408
12943 CEFBS_None, // VMULEUD = 2409
12944 CEFBS_None, // VMULEUH = 2410
12945 CEFBS_None, // VMULEUW = 2411
12946 CEFBS_None, // VMULHSD = 2412
12947 CEFBS_None, // VMULHSW = 2413
12948 CEFBS_None, // VMULHUD = 2414
12949 CEFBS_None, // VMULHUW = 2415
12950 CEFBS_None, // VMULLD = 2416
12951 CEFBS_None, // VMULOSB = 2417
12952 CEFBS_None, // VMULOSD = 2418
12953 CEFBS_None, // VMULOSH = 2419
12954 CEFBS_None, // VMULOSW = 2420
12955 CEFBS_None, // VMULOUB = 2421
12956 CEFBS_None, // VMULOUD = 2422
12957 CEFBS_None, // VMULOUH = 2423
12958 CEFBS_None, // VMULOUW = 2424
12959 CEFBS_None, // VMULUWM = 2425
12960 CEFBS_None, // VNAND = 2426
12961 CEFBS_None, // VNCIPHER = 2427
12962 CEFBS_None, // VNCIPHERLAST = 2428
12963 CEFBS_None, // VNEGD = 2429
12964 CEFBS_None, // VNEGW = 2430
12965 CEFBS_None, // VNMSUBFP = 2431
12966 CEFBS_None, // VNOR = 2432
12967 CEFBS_None, // VOR = 2433
12968 CEFBS_None, // VORC = 2434
12969 CEFBS_None, // VPDEPD = 2435
12970 CEFBS_None, // VPERM = 2436
12971 CEFBS_None, // VPERMR = 2437
12972 CEFBS_None, // VPERMXOR = 2438
12973 CEFBS_None, // VPEXTD = 2439
12974 CEFBS_None, // VPKPX = 2440
12975 CEFBS_None, // VPKSDSS = 2441
12976 CEFBS_None, // VPKSDUS = 2442
12977 CEFBS_None, // VPKSHSS = 2443
12978 CEFBS_None, // VPKSHUS = 2444
12979 CEFBS_None, // VPKSWSS = 2445
12980 CEFBS_None, // VPKSWUS = 2446
12981 CEFBS_None, // VPKUDUM = 2447
12982 CEFBS_None, // VPKUDUS = 2448
12983 CEFBS_None, // VPKUHUM = 2449
12984 CEFBS_None, // VPKUHUS = 2450
12985 CEFBS_None, // VPKUWUM = 2451
12986 CEFBS_None, // VPKUWUS = 2452
12987 CEFBS_None, // VPMSUMB = 2453
12988 CEFBS_None, // VPMSUMD = 2454
12989 CEFBS_None, // VPMSUMH = 2455
12990 CEFBS_None, // VPMSUMW = 2456
12991 CEFBS_None, // VPOPCNTB = 2457
12992 CEFBS_None, // VPOPCNTD = 2458
12993 CEFBS_None, // VPOPCNTH = 2459
12994 CEFBS_None, // VPOPCNTW = 2460
12995 CEFBS_None, // VPRTYBD = 2461
12996 CEFBS_None, // VPRTYBQ = 2462
12997 CEFBS_None, // VPRTYBW = 2463
12998 CEFBS_None, // VREFP = 2464
12999 CEFBS_None, // VRFIM = 2465
13000 CEFBS_None, // VRFIN = 2466
13001 CEFBS_None, // VRFIP = 2467
13002 CEFBS_None, // VRFIZ = 2468
13003 CEFBS_None, // VRLB = 2469
13004 CEFBS_None, // VRLD = 2470
13005 CEFBS_None, // VRLDMI = 2471
13006 CEFBS_None, // VRLDNM = 2472
13007 CEFBS_None, // VRLH = 2473
13008 CEFBS_None, // VRLQ = 2474
13009 CEFBS_None, // VRLQMI = 2475
13010 CEFBS_None, // VRLQNM = 2476
13011 CEFBS_None, // VRLW = 2477
13012 CEFBS_None, // VRLWMI = 2478
13013 CEFBS_None, // VRLWNM = 2479
13014 CEFBS_None, // VRSQRTEFP = 2480
13015 CEFBS_None, // VSBOX = 2481
13016 CEFBS_None, // VSEL = 2482
13017 CEFBS_None, // VSHASIGMAD = 2483
13018 CEFBS_None, // VSHASIGMAW = 2484
13019 CEFBS_None, // VSL = 2485
13020 CEFBS_None, // VSLB = 2486
13021 CEFBS_None, // VSLD = 2487
13022 CEFBS_None, // VSLDBI = 2488
13023 CEFBS_None, // VSLDOI = 2489
13024 CEFBS_None, // VSLH = 2490
13025 CEFBS_None, // VSLO = 2491
13026 CEFBS_None, // VSLQ = 2492
13027 CEFBS_None, // VSLV = 2493
13028 CEFBS_None, // VSLW = 2494
13029 CEFBS_None, // VSPLTB = 2495
13030 CEFBS_None, // VSPLTBs = 2496
13031 CEFBS_None, // VSPLTH = 2497
13032 CEFBS_None, // VSPLTHs = 2498
13033 CEFBS_None, // VSPLTISB = 2499
13034 CEFBS_None, // VSPLTISH = 2500
13035 CEFBS_None, // VSPLTISW = 2501
13036 CEFBS_None, // VSPLTW = 2502
13037 CEFBS_None, // VSR = 2503
13038 CEFBS_None, // VSRAB = 2504
13039 CEFBS_None, // VSRAD = 2505
13040 CEFBS_None, // VSRAH = 2506
13041 CEFBS_None, // VSRAQ = 2507
13042 CEFBS_None, // VSRAW = 2508
13043 CEFBS_None, // VSRB = 2509
13044 CEFBS_None, // VSRD = 2510
13045 CEFBS_None, // VSRDBI = 2511
13046 CEFBS_None, // VSRH = 2512
13047 CEFBS_None, // VSRO = 2513
13048 CEFBS_None, // VSRQ = 2514
13049 CEFBS_None, // VSRV = 2515
13050 CEFBS_None, // VSRW = 2516
13051 CEFBS_None, // VSTRIBL = 2517
13052 CEFBS_None, // VSTRIBL_rec = 2518
13053 CEFBS_None, // VSTRIBR = 2519
13054 CEFBS_None, // VSTRIBR_rec = 2520
13055 CEFBS_None, // VSTRIHL = 2521
13056 CEFBS_None, // VSTRIHL_rec = 2522
13057 CEFBS_None, // VSTRIHR = 2523
13058 CEFBS_None, // VSTRIHR_rec = 2524
13059 CEFBS_None, // VSUBCUQ = 2525
13060 CEFBS_None, // VSUBCUW = 2526
13061 CEFBS_None, // VSUBECUQ = 2527
13062 CEFBS_None, // VSUBEUQM = 2528
13063 CEFBS_None, // VSUBFP = 2529
13064 CEFBS_None, // VSUBSBS = 2530
13065 CEFBS_None, // VSUBSHS = 2531
13066 CEFBS_None, // VSUBSWS = 2532
13067 CEFBS_None, // VSUBUBM = 2533
13068 CEFBS_None, // VSUBUBS = 2534
13069 CEFBS_None, // VSUBUDM = 2535
13070 CEFBS_None, // VSUBUHM = 2536
13071 CEFBS_None, // VSUBUHS = 2537
13072 CEFBS_None, // VSUBUQM = 2538
13073 CEFBS_None, // VSUBUWM = 2539
13074 CEFBS_None, // VSUBUWS = 2540
13075 CEFBS_None, // VSUM2SWS = 2541
13076 CEFBS_None, // VSUM4SBS = 2542
13077 CEFBS_None, // VSUM4SHS = 2543
13078 CEFBS_None, // VSUM4UBS = 2544
13079 CEFBS_None, // VSUMSWS = 2545
13080 CEFBS_None, // VUPKHPX = 2546
13081 CEFBS_None, // VUPKHSB = 2547
13082 CEFBS_None, // VUPKHSH = 2548
13083 CEFBS_None, // VUPKHSW = 2549
13084 CEFBS_None, // VUPKLPX = 2550
13085 CEFBS_None, // VUPKLSB = 2551
13086 CEFBS_None, // VUPKLSH = 2552
13087 CEFBS_None, // VUPKLSW = 2553
13088 CEFBS_None, // VXOR = 2554
13089 CEFBS_None, // V_SET0 = 2555
13090 CEFBS_None, // V_SET0B = 2556
13091 CEFBS_None, // V_SET0H = 2557
13092 CEFBS_None, // V_SETALLONES = 2558
13093 CEFBS_None, // V_SETALLONESB = 2559
13094 CEFBS_None, // V_SETALLONESH = 2560
13095 CEFBS_None, // WAIT = 2561
13096 CEFBS_None, // WAITP10 = 2562
13097 CEFBS_None, // WRTEE = 2563
13098 CEFBS_None, // WRTEEI = 2564
13099 CEFBS_None, // XOR = 2565
13100 CEFBS_None, // XOR8 = 2566
13101 CEFBS_None, // XOR8_rec = 2567
13102 CEFBS_None, // XORI = 2568
13103 CEFBS_None, // XORI8 = 2569
13104 CEFBS_None, // XORIS = 2570
13105 CEFBS_None, // XORIS8 = 2571
13106 CEFBS_None, // XOR_rec = 2572
13107 CEFBS_None, // XSABSDP = 2573
13108 CEFBS_None, // XSABSQP = 2574
13109 CEFBS_None, // XSADDDP = 2575
13110 CEFBS_None, // XSADDQP = 2576
13111 CEFBS_None, // XSADDQPO = 2577
13112 CEFBS_None, // XSADDSP = 2578
13113 CEFBS_None, // XSCMPEQDP = 2579
13114 CEFBS_None, // XSCMPEQQP = 2580
13115 CEFBS_None, // XSCMPEXPDP = 2581
13116 CEFBS_None, // XSCMPEXPQP = 2582
13117 CEFBS_None, // XSCMPGEDP = 2583
13118 CEFBS_None, // XSCMPGEQP = 2584
13119 CEFBS_None, // XSCMPGTDP = 2585
13120 CEFBS_None, // XSCMPGTQP = 2586
13121 CEFBS_None, // XSCMPODP = 2587
13122 CEFBS_None, // XSCMPOQP = 2588
13123 CEFBS_None, // XSCMPUDP = 2589
13124 CEFBS_None, // XSCMPUQP = 2590
13125 CEFBS_None, // XSCPSGNDP = 2591
13126 CEFBS_None, // XSCPSGNQP = 2592
13127 CEFBS_None, // XSCVDPHP = 2593
13128 CEFBS_None, // XSCVDPQP = 2594
13129 CEFBS_None, // XSCVDPSP = 2595
13130 CEFBS_None, // XSCVDPSPN = 2596
13131 CEFBS_None, // XSCVDPSXDS = 2597
13132 CEFBS_None, // XSCVDPSXDSs = 2598
13133 CEFBS_None, // XSCVDPSXWS = 2599
13134 CEFBS_None, // XSCVDPSXWSs = 2600
13135 CEFBS_None, // XSCVDPUXDS = 2601
13136 CEFBS_None, // XSCVDPUXDSs = 2602
13137 CEFBS_None, // XSCVDPUXWS = 2603
13138 CEFBS_None, // XSCVDPUXWSs = 2604
13139 CEFBS_None, // XSCVHPDP = 2605
13140 CEFBS_None, // XSCVQPDP = 2606
13141 CEFBS_None, // XSCVQPDPO = 2607
13142 CEFBS_None, // XSCVQPSDZ = 2608
13143 CEFBS_None, // XSCVQPSQZ = 2609
13144 CEFBS_None, // XSCVQPSWZ = 2610
13145 CEFBS_None, // XSCVQPUDZ = 2611
13146 CEFBS_None, // XSCVQPUQZ = 2612
13147 CEFBS_None, // XSCVQPUWZ = 2613
13148 CEFBS_None, // XSCVSDQP = 2614
13149 CEFBS_None, // XSCVSPDP = 2615
13150 CEFBS_None, // XSCVSPDPN = 2616
13151 CEFBS_None, // XSCVSQQP = 2617
13152 CEFBS_None, // XSCVSXDDP = 2618
13153 CEFBS_None, // XSCVSXDSP = 2619
13154 CEFBS_None, // XSCVUDQP = 2620
13155 CEFBS_None, // XSCVUQQP = 2621
13156 CEFBS_None, // XSCVUXDDP = 2622
13157 CEFBS_None, // XSCVUXDSP = 2623
13158 CEFBS_None, // XSDIVDP = 2624
13159 CEFBS_None, // XSDIVQP = 2625
13160 CEFBS_None, // XSDIVQPO = 2626
13161 CEFBS_None, // XSDIVSP = 2627
13162 CEFBS_None, // XSIEXPDP = 2628
13163 CEFBS_None, // XSIEXPQP = 2629
13164 CEFBS_None, // XSMADDADP = 2630
13165 CEFBS_None, // XSMADDASP = 2631
13166 CEFBS_None, // XSMADDMDP = 2632
13167 CEFBS_None, // XSMADDMSP = 2633
13168 CEFBS_None, // XSMADDQP = 2634
13169 CEFBS_None, // XSMADDQPO = 2635
13170 CEFBS_None, // XSMAXCDP = 2636
13171 CEFBS_None, // XSMAXCQP = 2637
13172 CEFBS_None, // XSMAXDP = 2638
13173 CEFBS_None, // XSMAXJDP = 2639
13174 CEFBS_None, // XSMINCDP = 2640
13175 CEFBS_None, // XSMINCQP = 2641
13176 CEFBS_None, // XSMINDP = 2642
13177 CEFBS_None, // XSMINJDP = 2643
13178 CEFBS_None, // XSMSUBADP = 2644
13179 CEFBS_None, // XSMSUBASP = 2645
13180 CEFBS_None, // XSMSUBMDP = 2646
13181 CEFBS_None, // XSMSUBMSP = 2647
13182 CEFBS_None, // XSMSUBQP = 2648
13183 CEFBS_None, // XSMSUBQPO = 2649
13184 CEFBS_None, // XSMULDP = 2650
13185 CEFBS_None, // XSMULQP = 2651
13186 CEFBS_None, // XSMULQPO = 2652
13187 CEFBS_None, // XSMULSP = 2653
13188 CEFBS_None, // XSNABSDP = 2654
13189 CEFBS_None, // XSNABSDPs = 2655
13190 CEFBS_None, // XSNABSQP = 2656
13191 CEFBS_None, // XSNEGDP = 2657
13192 CEFBS_None, // XSNEGQP = 2658
13193 CEFBS_None, // XSNMADDADP = 2659
13194 CEFBS_None, // XSNMADDASP = 2660
13195 CEFBS_None, // XSNMADDMDP = 2661
13196 CEFBS_None, // XSNMADDMSP = 2662
13197 CEFBS_None, // XSNMADDQP = 2663
13198 CEFBS_None, // XSNMADDQPO = 2664
13199 CEFBS_None, // XSNMSUBADP = 2665
13200 CEFBS_None, // XSNMSUBASP = 2666
13201 CEFBS_None, // XSNMSUBMDP = 2667
13202 CEFBS_None, // XSNMSUBMSP = 2668
13203 CEFBS_None, // XSNMSUBQP = 2669
13204 CEFBS_None, // XSNMSUBQPO = 2670
13205 CEFBS_None, // XSRDPI = 2671
13206 CEFBS_None, // XSRDPIC = 2672
13207 CEFBS_None, // XSRDPIM = 2673
13208 CEFBS_None, // XSRDPIP = 2674
13209 CEFBS_None, // XSRDPIZ = 2675
13210 CEFBS_None, // XSREDP = 2676
13211 CEFBS_None, // XSRESP = 2677
13212 CEFBS_None, // XSRQPI = 2678
13213 CEFBS_None, // XSRQPIX = 2679
13214 CEFBS_None, // XSRQPXP = 2680
13215 CEFBS_None, // XSRSP = 2681
13216 CEFBS_None, // XSRSQRTEDP = 2682
13217 CEFBS_None, // XSRSQRTESP = 2683
13218 CEFBS_None, // XSSQRTDP = 2684
13219 CEFBS_None, // XSSQRTQP = 2685
13220 CEFBS_None, // XSSQRTQPO = 2686
13221 CEFBS_None, // XSSQRTSP = 2687
13222 CEFBS_None, // XSSUBDP = 2688
13223 CEFBS_None, // XSSUBQP = 2689
13224 CEFBS_None, // XSSUBQPO = 2690
13225 CEFBS_None, // XSSUBSP = 2691
13226 CEFBS_None, // XSTDIVDP = 2692
13227 CEFBS_None, // XSTSQRTDP = 2693
13228 CEFBS_None, // XSTSTDCDP = 2694
13229 CEFBS_None, // XSTSTDCQP = 2695
13230 CEFBS_None, // XSTSTDCSP = 2696
13231 CEFBS_None, // XSXEXPDP = 2697
13232 CEFBS_None, // XSXEXPQP = 2698
13233 CEFBS_None, // XSXSIGDP = 2699
13234 CEFBS_None, // XSXSIGQP = 2700
13235 CEFBS_None, // XVABSDP = 2701
13236 CEFBS_None, // XVABSSP = 2702
13237 CEFBS_None, // XVADDDP = 2703
13238 CEFBS_None, // XVADDSP = 2704
13239 CEFBS_None, // XVBF16GER2 = 2705
13240 CEFBS_None, // XVBF16GER2NN = 2706
13241 CEFBS_None, // XVBF16GER2NP = 2707
13242 CEFBS_None, // XVBF16GER2PN = 2708
13243 CEFBS_None, // XVBF16GER2PP = 2709
13244 CEFBS_None, // XVBF16GER2W = 2710
13245 CEFBS_None, // XVBF16GER2WNN = 2711
13246 CEFBS_None, // XVBF16GER2WNP = 2712
13247 CEFBS_None, // XVBF16GER2WPN = 2713
13248 CEFBS_None, // XVBF16GER2WPP = 2714
13249 CEFBS_None, // XVCMPEQDP = 2715
13250 CEFBS_None, // XVCMPEQDP_rec = 2716
13251 CEFBS_None, // XVCMPEQSP = 2717
13252 CEFBS_None, // XVCMPEQSP_rec = 2718
13253 CEFBS_None, // XVCMPGEDP = 2719
13254 CEFBS_None, // XVCMPGEDP_rec = 2720
13255 CEFBS_None, // XVCMPGESP = 2721
13256 CEFBS_None, // XVCMPGESP_rec = 2722
13257 CEFBS_None, // XVCMPGTDP = 2723
13258 CEFBS_None, // XVCMPGTDP_rec = 2724
13259 CEFBS_None, // XVCMPGTSP = 2725
13260 CEFBS_None, // XVCMPGTSP_rec = 2726
13261 CEFBS_None, // XVCPSGNDP = 2727
13262 CEFBS_None, // XVCPSGNSP = 2728
13263 CEFBS_None, // XVCVBF16SPN = 2729
13264 CEFBS_None, // XVCVDPSP = 2730
13265 CEFBS_None, // XVCVDPSXDS = 2731
13266 CEFBS_None, // XVCVDPSXWS = 2732
13267 CEFBS_None, // XVCVDPUXDS = 2733
13268 CEFBS_None, // XVCVDPUXWS = 2734
13269 CEFBS_None, // XVCVHPSP = 2735
13270 CEFBS_None, // XVCVSPBF16 = 2736
13271 CEFBS_None, // XVCVSPDP = 2737
13272 CEFBS_None, // XVCVSPHP = 2738
13273 CEFBS_None, // XVCVSPSXDS = 2739
13274 CEFBS_None, // XVCVSPSXWS = 2740
13275 CEFBS_None, // XVCVSPUXDS = 2741
13276 CEFBS_None, // XVCVSPUXWS = 2742
13277 CEFBS_None, // XVCVSXDDP = 2743
13278 CEFBS_None, // XVCVSXDSP = 2744
13279 CEFBS_None, // XVCVSXWDP = 2745
13280 CEFBS_None, // XVCVSXWSP = 2746
13281 CEFBS_None, // XVCVUXDDP = 2747
13282 CEFBS_None, // XVCVUXDSP = 2748
13283 CEFBS_None, // XVCVUXWDP = 2749
13284 CEFBS_None, // XVCVUXWSP = 2750
13285 CEFBS_None, // XVDIVDP = 2751
13286 CEFBS_None, // XVDIVSP = 2752
13287 CEFBS_None, // XVF16GER2 = 2753
13288 CEFBS_None, // XVF16GER2NN = 2754
13289 CEFBS_None, // XVF16GER2NP = 2755
13290 CEFBS_None, // XVF16GER2PN = 2756
13291 CEFBS_None, // XVF16GER2PP = 2757
13292 CEFBS_None, // XVF16GER2W = 2758
13293 CEFBS_None, // XVF16GER2WNN = 2759
13294 CEFBS_None, // XVF16GER2WNP = 2760
13295 CEFBS_None, // XVF16GER2WPN = 2761
13296 CEFBS_None, // XVF16GER2WPP = 2762
13297 CEFBS_None, // XVF32GER = 2763
13298 CEFBS_None, // XVF32GERNN = 2764
13299 CEFBS_None, // XVF32GERNP = 2765
13300 CEFBS_None, // XVF32GERPN = 2766
13301 CEFBS_None, // XVF32GERPP = 2767
13302 CEFBS_None, // XVF32GERW = 2768
13303 CEFBS_None, // XVF32GERWNN = 2769
13304 CEFBS_None, // XVF32GERWNP = 2770
13305 CEFBS_None, // XVF32GERWPN = 2771
13306 CEFBS_None, // XVF32GERWPP = 2772
13307 CEFBS_None, // XVF64GER = 2773
13308 CEFBS_None, // XVF64GERNN = 2774
13309 CEFBS_None, // XVF64GERNP = 2775
13310 CEFBS_None, // XVF64GERPN = 2776
13311 CEFBS_None, // XVF64GERPP = 2777
13312 CEFBS_None, // XVF64GERW = 2778
13313 CEFBS_None, // XVF64GERWNN = 2779
13314 CEFBS_None, // XVF64GERWNP = 2780
13315 CEFBS_None, // XVF64GERWPN = 2781
13316 CEFBS_None, // XVF64GERWPP = 2782
13317 CEFBS_None, // XVI16GER2 = 2783
13318 CEFBS_None, // XVI16GER2PP = 2784
13319 CEFBS_None, // XVI16GER2S = 2785
13320 CEFBS_None, // XVI16GER2SPP = 2786
13321 CEFBS_None, // XVI16GER2SW = 2787
13322 CEFBS_None, // XVI16GER2SWPP = 2788
13323 CEFBS_None, // XVI16GER2W = 2789
13324 CEFBS_None, // XVI16GER2WPP = 2790
13325 CEFBS_None, // XVI4GER8 = 2791
13326 CEFBS_None, // XVI4GER8PP = 2792
13327 CEFBS_None, // XVI4GER8W = 2793
13328 CEFBS_None, // XVI4GER8WPP = 2794
13329 CEFBS_None, // XVI8GER4 = 2795
13330 CEFBS_None, // XVI8GER4PP = 2796
13331 CEFBS_None, // XVI8GER4SPP = 2797
13332 CEFBS_None, // XVI8GER4W = 2798
13333 CEFBS_None, // XVI8GER4WPP = 2799
13334 CEFBS_None, // XVI8GER4WSPP = 2800
13335 CEFBS_None, // XVIEXPDP = 2801
13336 CEFBS_None, // XVIEXPSP = 2802
13337 CEFBS_None, // XVMADDADP = 2803
13338 CEFBS_None, // XVMADDASP = 2804
13339 CEFBS_None, // XVMADDMDP = 2805
13340 CEFBS_None, // XVMADDMSP = 2806
13341 CEFBS_None, // XVMAXDP = 2807
13342 CEFBS_None, // XVMAXSP = 2808
13343 CEFBS_None, // XVMINDP = 2809
13344 CEFBS_None, // XVMINSP = 2810
13345 CEFBS_None, // XVMSUBADP = 2811
13346 CEFBS_None, // XVMSUBASP = 2812
13347 CEFBS_None, // XVMSUBMDP = 2813
13348 CEFBS_None, // XVMSUBMSP = 2814
13349 CEFBS_None, // XVMULDP = 2815
13350 CEFBS_None, // XVMULSP = 2816
13351 CEFBS_None, // XVNABSDP = 2817
13352 CEFBS_None, // XVNABSSP = 2818
13353 CEFBS_None, // XVNEGDP = 2819
13354 CEFBS_None, // XVNEGSP = 2820
13355 CEFBS_None, // XVNMADDADP = 2821
13356 CEFBS_None, // XVNMADDASP = 2822
13357 CEFBS_None, // XVNMADDMDP = 2823
13358 CEFBS_None, // XVNMADDMSP = 2824
13359 CEFBS_None, // XVNMSUBADP = 2825
13360 CEFBS_None, // XVNMSUBASP = 2826
13361 CEFBS_None, // XVNMSUBMDP = 2827
13362 CEFBS_None, // XVNMSUBMSP = 2828
13363 CEFBS_None, // XVRDPI = 2829
13364 CEFBS_None, // XVRDPIC = 2830
13365 CEFBS_None, // XVRDPIM = 2831
13366 CEFBS_None, // XVRDPIP = 2832
13367 CEFBS_None, // XVRDPIZ = 2833
13368 CEFBS_None, // XVREDP = 2834
13369 CEFBS_None, // XVRESP = 2835
13370 CEFBS_None, // XVRSPI = 2836
13371 CEFBS_None, // XVRSPIC = 2837
13372 CEFBS_None, // XVRSPIM = 2838
13373 CEFBS_None, // XVRSPIP = 2839
13374 CEFBS_None, // XVRSPIZ = 2840
13375 CEFBS_None, // XVRSQRTEDP = 2841
13376 CEFBS_None, // XVRSQRTESP = 2842
13377 CEFBS_None, // XVSQRTDP = 2843
13378 CEFBS_None, // XVSQRTSP = 2844
13379 CEFBS_None, // XVSUBDP = 2845
13380 CEFBS_None, // XVSUBSP = 2846
13381 CEFBS_None, // XVTDIVDP = 2847
13382 CEFBS_None, // XVTDIVSP = 2848
13383 CEFBS_None, // XVTLSBB = 2849
13384 CEFBS_None, // XVTSQRTDP = 2850
13385 CEFBS_None, // XVTSQRTSP = 2851
13386 CEFBS_None, // XVTSTDCDP = 2852
13387 CEFBS_None, // XVTSTDCSP = 2853
13388 CEFBS_None, // XVXEXPDP = 2854
13389 CEFBS_None, // XVXEXPSP = 2855
13390 CEFBS_None, // XVXSIGDP = 2856
13391 CEFBS_None, // XVXSIGSP = 2857
13392 CEFBS_None, // XXBLENDVB = 2858
13393 CEFBS_None, // XXBLENDVD = 2859
13394 CEFBS_None, // XXBLENDVH = 2860
13395 CEFBS_None, // XXBLENDVW = 2861
13396 CEFBS_None, // XXBRD = 2862
13397 CEFBS_None, // XXBRH = 2863
13398 CEFBS_None, // XXBRQ = 2864
13399 CEFBS_None, // XXBRW = 2865
13400 CEFBS_None, // XXEVAL = 2866
13401 CEFBS_None, // XXEXTRACTUW = 2867
13402 CEFBS_None, // XXGENPCVBM = 2868
13403 CEFBS_None, // XXGENPCVDM = 2869
13404 CEFBS_None, // XXGENPCVHM = 2870
13405 CEFBS_None, // XXGENPCVWM = 2871
13406 CEFBS_None, // XXINSERTW = 2872
13407 CEFBS_None, // XXLAND = 2873
13408 CEFBS_None, // XXLANDC = 2874
13409 CEFBS_None, // XXLEQV = 2875
13410 CEFBS_None, // XXLEQVOnes = 2876
13411 CEFBS_None, // XXLNAND = 2877
13412 CEFBS_None, // XXLNOR = 2878
13413 CEFBS_None, // XXLOR = 2879
13414 CEFBS_None, // XXLORC = 2880
13415 CEFBS_None, // XXLORf = 2881
13416 CEFBS_None, // XXLXOR = 2882
13417 CEFBS_None, // XXLXORdpz = 2883
13418 CEFBS_None, // XXLXORspz = 2884
13419 CEFBS_None, // XXLXORz = 2885
13420 CEFBS_None, // XXMFACC = 2886
13421 CEFBS_None, // XXMFACCW = 2887
13422 CEFBS_None, // XXMRGHW = 2888
13423 CEFBS_None, // XXMRGLW = 2889
13424 CEFBS_None, // XXMTACC = 2890
13425 CEFBS_None, // XXMTACCW = 2891
13426 CEFBS_None, // XXPERM = 2892
13427 CEFBS_None, // XXPERMDI = 2893
13428 CEFBS_None, // XXPERMDIs = 2894
13429 CEFBS_None, // XXPERMR = 2895
13430 CEFBS_None, // XXPERMX = 2896
13431 CEFBS_None, // XXSEL = 2897
13432 CEFBS_None, // XXSETACCZ = 2898
13433 CEFBS_None, // XXSLDWI = 2899
13434 CEFBS_None, // XXSLDWIs = 2900
13435 CEFBS_None, // XXSPLTI32DX = 2901
13436 CEFBS_None, // XXSPLTIB = 2902
13437 CEFBS_None, // XXSPLTIDP = 2903
13438 CEFBS_None, // XXSPLTIW = 2904
13439 CEFBS_None, // XXSPLTW = 2905
13440 CEFBS_None, // XXSPLTWs = 2906
13441 CEFBS_None, // gBC = 2907
13442 CEFBS_None, // gBCA = 2908
13443 CEFBS_None, // gBCAat = 2909
13444 CEFBS_None, // gBCCTR = 2910
13445 CEFBS_None, // gBCCTRL = 2911
13446 CEFBS_None, // gBCL = 2912
13447 CEFBS_None, // gBCLA = 2913
13448 CEFBS_None, // gBCLAat = 2914
13449 CEFBS_None, // gBCLR = 2915
13450 CEFBS_None, // gBCLRL = 2916
13451 CEFBS_None, // gBCLat = 2917
13452 CEFBS_None, // gBCat = 2918
13453 };
13454
13455 assert(Opcode < 2919);
13456 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
13457}
13458
13459} // end namespace llvm::PPC_MC
13460#endif // GET_COMPUTE_FEATURES
13461
13462#ifdef GET_AVAILABLE_OPCODE_CHECKER
13463#undef GET_AVAILABLE_OPCODE_CHECKER
13464namespace llvm::PPC_MC {
13465bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
13466 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
13467 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
13468 FeatureBitset MissingFeatures =
13469 (AvailableFeatures & RequiredFeatures) ^
13470 RequiredFeatures;
13471 return !MissingFeatures.any();
13472}
13473} // end namespace llvm::PPC_MC
13474#endif // GET_AVAILABLE_OPCODE_CHECKER
13475
13476#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
13477#undef ENABLE_INSTR_PREDICATE_VERIFIER
13478#include <sstream>
13479
13480namespace llvm::PPC_MC {
13481#ifndef NDEBUG
13482static const char *SubtargetFeatureNames[] = {
13483 "Feature_ModernAs",
13484 nullptr
13485};
13486
13487#endif // NDEBUG
13488
13489void verifyInstructionPredicates(
13490 unsigned Opcode, const FeatureBitset &Features) {
13491#ifndef NDEBUG
13492 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
13493 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
13494 FeatureBitset MissingFeatures =
13495 (AvailableFeatures & RequiredFeatures) ^
13496 RequiredFeatures;
13497 if (MissingFeatures.any()) {
13498 std::ostringstream Msg;
13499 Msg << "Attempting to emit " << &PPCInstrNameData[PPCInstrNameIndices[Opcode]]
13500 << " instruction but the ";
13501 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
13502 if (MissingFeatures.test(i))
13503 Msg << SubtargetFeatureNames[i] << " ";
13504 Msg << "predicate(s) are not met";
13505 report_fatal_error(Msg.str().c_str());
13506 }
13507#endif // NDEBUG
13508}
13509} // end namespace llvm::PPC_MC
13510#endif // ENABLE_INSTR_PREDICATE_VERIFIER
13511
13512#ifdef GET_INSTRMAP_INFO
13513#undef GET_INSTRMAP_INFO
13514namespace llvm::PPC {
13515
13516enum Interpretation64Bit {
13517 Interpretation64Bit_1
13518};
13519
13520enum IsVSXFMAAlt {
13521 IsVSXFMAAlt_1
13522};
13523
13524enum RC {
13525 RC_0,
13526 RC_1
13527};
13528
13529// get64BitInstrFromSignedExt32BitInstr
13530LLVM_READONLY
13531int get64BitInstrFromSignedExt32BitInstr(uint16_t Opcode) {
13532 using namespace PPC;
13533 static constexpr uint16_t Table[][2] = {
13534 { ANDI_rec, ANDI8_rec },
13535 { EXTSB, EXTSB8 },
13536 { EXTSB8_32_64, EXTSB8 },
13537 { EXTSB_rec, EXTSB8_rec },
13538 { EXTSH, EXTSH8 },
13539 { EXTSH8_32_64, EXTSH8 },
13540 { EXTSH_rec, EXTSH8_rec },
13541 { EXTSW, EXTSW_32_64 },
13542 { EXTSW_rec, EXTSW_32_64_rec },
13543 { LBZ, LBZ8 },
13544 { LBZX, LBZX8 },
13545 { LHA, LHA8 },
13546 { LHAX, LHAX8 },
13547 { LHZ, LHZ8 },
13548 { LHZX, LHZX8 },
13549 { LI, LI8 },
13550 { LIS, LIS8 },
13551 { SETB, SETB8 },
13552 { SETBC, SETBC8 },
13553 { SETBCR, SETBCR8 },
13554 { SETNBC, SETNBC8 },
13555 { SETNBCR, SETNBCR8 },
13556 { SRAW, SRAW8 },
13557 { SRAWI, SRAWI8 },
13558 { SRAWI_rec, SRAWI8_rec },
13559 { SRAW_rec, SRAW8_rec },
13560 }; // End of Table
13561
13562 unsigned mid;
13563 unsigned start = 0;
13564 unsigned end = 26;
13565 while (start < end) {
13566 mid = start + (end - start) / 2;
13567 if (Opcode == Table[mid][0])
13568 break;
13569 if (Opcode < Table[mid][0])
13570 end = mid;
13571 else
13572 start = mid + 1;
13573 }
13574 if (start == end)
13575 return -1; // Instruction doesn't exist in this table.
13576
13577 return Table[mid][1];
13578}
13579
13580// getAltVSXFMAOpcode
13581LLVM_READONLY
13582int getAltVSXFMAOpcode(uint16_t Opcode) {
13583 using namespace PPC;
13584 static constexpr uint16_t Table[][2] = {
13585 { XSMADDADP, XSMADDMDP },
13586 { XSMADDASP, XSMADDMSP },
13587 { XSMSUBADP, XSMSUBMDP },
13588 { XSMSUBASP, XSMSUBMSP },
13589 { XSNMADDADP, XSNMADDMDP },
13590 { XSNMADDASP, XSNMADDMSP },
13591 { XSNMSUBADP, XSNMSUBMDP },
13592 { XSNMSUBASP, XSNMSUBMSP },
13593 { XVMADDADP, XVMADDMDP },
13594 { XVMADDASP, XVMADDMSP },
13595 { XVMSUBADP, XVMSUBMDP },
13596 { XVMSUBASP, XVMSUBMSP },
13597 { XVNMADDADP, XVNMADDMDP },
13598 { XVNMADDASP, XVNMADDMSP },
13599 { XVNMSUBADP, XVNMSUBMDP },
13600 { XVNMSUBASP, XVNMSUBMSP },
13601 }; // End of Table
13602
13603 unsigned mid;
13604 unsigned start = 0;
13605 unsigned end = 16;
13606 while (start < end) {
13607 mid = start + (end - start) / 2;
13608 if (Opcode == Table[mid][0])
13609 break;
13610 if (Opcode < Table[mid][0])
13611 end = mid;
13612 else
13613 start = mid + 1;
13614 }
13615 if (start == end)
13616 return -1; // Instruction doesn't exist in this table.
13617
13618 return Table[mid][1];
13619}
13620
13621// getNonRecordFormOpcode
13622LLVM_READONLY
13623int getNonRecordFormOpcode(uint16_t Opcode) {
13624 using namespace PPC;
13625 static constexpr uint16_t Table[][2] = {
13626 { ADD4O_rec, ADD4O },
13627 { ADD4_rec, ADD4 },
13628 { ADD8O_rec, ADD8O },
13629 { ADD8_rec, ADD8 },
13630 { ADDC8O_rec, ADDC8O },
13631 { ADDC8_rec, ADDC8 },
13632 { ADDCO_rec, ADDCO },
13633 { ADDC_rec, ADDC },
13634 { ADDE8O_rec, ADDE8O },
13635 { ADDE8_rec, ADDE8 },
13636 { ADDEO_rec, ADDEO },
13637 { ADDE_rec, ADDE },
13638 { ADDIC_rec, ADDIC },
13639 { ADDME8O_rec, ADDME8O },
13640 { ADDME8_rec, ADDME8 },
13641 { ADDMEO_rec, ADDMEO },
13642 { ADDME_rec, ADDME },
13643 { ADDZE8O_rec, ADDZE8O },
13644 { ADDZE8_rec, ADDZE8 },
13645 { ADDZEO_rec, ADDZEO },
13646 { ADDZE_rec, ADDZE },
13647 { AND8_rec, AND8 },
13648 { ANDC8_rec, ANDC8 },
13649 { ANDC_rec, ANDC },
13650 { AND_rec, AND },
13651 { CNTLZD_rec, CNTLZD },
13652 { CNTLZW8_rec, CNTLZW8 },
13653 { CNTLZW_rec, CNTLZW },
13654 { CNTTZD_rec, CNTTZD },
13655 { CNTTZW8_rec, CNTTZW8 },
13656 { CNTTZW_rec, CNTTZW },
13657 { DADDQ_rec, DADDQ },
13658 { DADD_rec, DADD },
13659 { DCFFIXQ_rec, DCFFIXQ },
13660 { DCFFIX_rec, DCFFIX },
13661 { DCTDP_rec, DCTDP },
13662 { DCTFIXQ_rec, DCTFIXQ },
13663 { DCTFIX_rec, DCTFIX },
13664 { DCTQPQ_rec, DCTQPQ },
13665 { DDEDPDQ_rec, DDEDPDQ },
13666 { DDEDPD_rec, DDEDPD },
13667 { DDIVQ_rec, DDIVQ },
13668 { DDIV_rec, DDIV },
13669 { DENBCDQ_rec, DENBCDQ },
13670 { DENBCD_rec, DENBCD },
13671 { DIEXQ_rec, DIEXQ },
13672 { DIEX_rec, DIEX },
13673 { DIVDEO_rec, DIVDEO },
13674 { DIVDEUO_rec, DIVDEUO },
13675 { DIVDEU_rec, DIVDEU },
13676 { DIVDE_rec, DIVDE },
13677 { DIVDO_rec, DIVDO },
13678 { DIVDUO_rec, DIVDUO },
13679 { DIVDU_rec, DIVDU },
13680 { DIVD_rec, DIVD },
13681 { DIVWEO_rec, DIVWEO },
13682 { DIVWEUO_rec, DIVWEUO },
13683 { DIVWEU_rec, DIVWEU },
13684 { DIVWE_rec, DIVWE },
13685 { DIVWO_rec, DIVWO },
13686 { DIVWUO_rec, DIVWUO },
13687 { DIVWU_rec, DIVWU },
13688 { DIVW_rec, DIVW },
13689 { DMULQ_rec, DMULQ },
13690 { DMUL_rec, DMUL },
13691 { DQUAIQ_rec, DQUAIQ },
13692 { DQUAI_rec, DQUAI },
13693 { DQUAQ_rec, DQUAQ },
13694 { DQUA_rec, DQUA },
13695 { DRDPQ_rec, DRDPQ },
13696 { DRINTNQ_rec, DRINTNQ },
13697 { DRINTN_rec, DRINTN },
13698 { DRINTXQ_rec, DRINTXQ },
13699 { DRINTX_rec, DRINTX },
13700 { DRRNDQ_rec, DRRNDQ },
13701 { DRRND_rec, DRRND },
13702 { DRSP_rec, DRSP },
13703 { DSCLIQ_rec, DSCLIQ },
13704 { DSCLI_rec, DSCLI },
13705 { DSCRIQ_rec, DSCRIQ },
13706 { DSCRI_rec, DSCRI },
13707 { DSUBQ_rec, DSUBQ },
13708 { DSUB_rec, DSUB },
13709 { DXEXQ_rec, DXEXQ },
13710 { DXEX_rec, DXEX },
13711 { EQV8_rec, EQV8 },
13712 { EQV_rec, EQV },
13713 { EXTSB8_rec, EXTSB8 },
13714 { EXTSB_rec, EXTSB },
13715 { EXTSH8_rec, EXTSH8 },
13716 { EXTSH_rec, EXTSH },
13717 { EXTSWSLI_32_64_rec, EXTSWSLI_32_64 },
13718 { EXTSWSLI_rec, EXTSWSLI },
13719 { EXTSW_32_64_rec, EXTSW_32_64 },
13720 { EXTSW_rec, EXTSW },
13721 { FABSD_rec, FABSD },
13722 { FABSS_rec, FABSS },
13723 { FADDS_rec, FADDS },
13724 { FADD_rec, FADD },
13725 { FCFIDS_rec, FCFIDS },
13726 { FCFIDUS_rec, FCFIDUS },
13727 { FCFIDU_rec, FCFIDU },
13728 { FCFID_rec, FCFID },
13729 { FCPSGND_rec, FCPSGND },
13730 { FCPSGNS_rec, FCPSGNS },
13731 { FCTIDUZ_rec, FCTIDUZ },
13732 { FCTIDU_rec, FCTIDU },
13733 { FCTIDZ_rec, FCTIDZ },
13734 { FCTID_rec, FCTID },
13735 { FCTIWUZ_rec, FCTIWUZ },
13736 { FCTIWU_rec, FCTIWU },
13737 { FCTIWZ_rec, FCTIWZ },
13738 { FCTIW_rec, FCTIW },
13739 { FDIVS_rec, FDIVS },
13740 { FDIV_rec, FDIV },
13741 { FMADDS_rec, FMADDS },
13742 { FMADD_rec, FMADD },
13743 { FMR_rec, FMR },
13744 { FMSUBS_rec, FMSUBS },
13745 { FMSUB_rec, FMSUB },
13746 { FMULS_rec, FMULS },
13747 { FMUL_rec, FMUL },
13748 { FNABSD_rec, FNABSD },
13749 { FNABSS_rec, FNABSS },
13750 { FNEGD_rec, FNEGD },
13751 { FNEGS_rec, FNEGS },
13752 { FNMADDS_rec, FNMADDS },
13753 { FNMADD_rec, FNMADD },
13754 { FNMSUBS_rec, FNMSUBS },
13755 { FNMSUB_rec, FNMSUB },
13756 { FRES_rec, FRES },
13757 { FRE_rec, FRE },
13758 { FRIMD_rec, FRIMD },
13759 { FRIMS_rec, FRIMS },
13760 { FRIND_rec, FRIND },
13761 { FRINS_rec, FRINS },
13762 { FRIPD_rec, FRIPD },
13763 { FRIPS_rec, FRIPS },
13764 { FRIZD_rec, FRIZD },
13765 { FRIZS_rec, FRIZS },
13766 { FRSP_rec, FRSP },
13767 { FRSQRTES_rec, FRSQRTES },
13768 { FRSQRTE_rec, FRSQRTE },
13769 { FSELD_rec, FSELD },
13770 { FSELS_rec, FSELS },
13771 { FSQRTS_rec, FSQRTS },
13772 { FSQRT_rec, FSQRT },
13773 { FSUBS_rec, FSUBS },
13774 { FSUB_rec, FSUB },
13775 { MULHDU_rec, MULHDU },
13776 { MULHD_rec, MULHD },
13777 { MULHWU_rec, MULHWU },
13778 { MULHW_rec, MULHW },
13779 { MULLDO_rec, MULLDO },
13780 { MULLD_rec, MULLD },
13781 { MULLWO_rec, MULLWO },
13782 { MULLW_rec, MULLW },
13783 { NAND8_rec, NAND8 },
13784 { NAND_rec, NAND },
13785 { NEG8O_rec, NEG8O },
13786 { NEG8_rec, NEG8 },
13787 { NEGO_rec, NEGO },
13788 { NEG_rec, NEG },
13789 { NOR8_rec, NOR8 },
13790 { NOR_rec, NOR },
13791 { OR8_rec, OR8 },
13792 { ORC8_rec, ORC8 },
13793 { ORC_rec, ORC },
13794 { OR_rec, OR },
13795 { RLDCL_rec, RLDCL },
13796 { RLDCR_rec, RLDCR },
13797 { RLDICL_32_rec, RLDICL_32 },
13798 { RLDICL_rec, RLDICL },
13799 { RLDICR_rec, RLDICR },
13800 { RLDIC_rec, RLDIC },
13801 { RLDIMI_rec, RLDIMI },
13802 { RLWIMI8_rec, RLWIMI8 },
13803 { RLWIMI_rec, RLWIMI },
13804 { RLWINM8_rec, RLWINM8 },
13805 { RLWINM_rec, RLWINM },
13806 { RLWNM8_rec, RLWNM8 },
13807 { RLWNM_rec, RLWNM },
13808 { SLD_rec, SLD },
13809 { SLW8_rec, SLW8 },
13810 { SLW_rec, SLW },
13811 { SRADI_rec, SRADI },
13812 { SRAD_rec, SRAD },
13813 { SRAW8_rec, SRAW8 },
13814 { SRAWI8_rec, SRAWI8 },
13815 { SRAWI_rec, SRAWI },
13816 { SRAW_rec, SRAW },
13817 { SRD_rec, SRD },
13818 { SRW8_rec, SRW8 },
13819 { SRW_rec, SRW },
13820 { SUBF8O_rec, SUBF8O },
13821 { SUBF8_rec, SUBF8 },
13822 { SUBFC8O_rec, SUBFC8O },
13823 { SUBFC8_rec, SUBFC8 },
13824 { SUBFCO_rec, SUBFCO },
13825 { SUBFC_rec, SUBFC },
13826 { SUBFE8O_rec, SUBFE8O },
13827 { SUBFE8_rec, SUBFE8 },
13828 { SUBFEO_rec, SUBFEO },
13829 { SUBFE_rec, SUBFE },
13830 { SUBFME8O_rec, SUBFME8O },
13831 { SUBFME8_rec, SUBFME8 },
13832 { SUBFMEO_rec, SUBFMEO },
13833 { SUBFME_rec, SUBFME },
13834 { SUBFO_rec, SUBFO },
13835 { SUBFUS_rec, SUBFUS },
13836 { SUBFZE8O_rec, SUBFZE8O },
13837 { SUBFZE8_rec, SUBFZE8 },
13838 { SUBFZEO_rec, SUBFZEO },
13839 { SUBFZE_rec, SUBFZE },
13840 { SUBF_rec, SUBF },
13841 { VSTRIBL_rec, VSTRIBL },
13842 { VSTRIBR_rec, VSTRIBR },
13843 { VSTRIHL_rec, VSTRIHL },
13844 { VSTRIHR_rec, VSTRIHR },
13845 { XOR8_rec, XOR8 },
13846 { XOR_rec, XOR },
13847 }; // End of Table
13848
13849 unsigned mid;
13850 unsigned start = 0;
13851 unsigned end = 221;
13852 while (start < end) {
13853 mid = start + (end - start) / 2;
13854 if (Opcode == Table[mid][0])
13855 break;
13856 if (Opcode < Table[mid][0])
13857 end = mid;
13858 else
13859 start = mid + 1;
13860 }
13861 if (start == end)
13862 return -1; // Instruction doesn't exist in this table.
13863
13864 return Table[mid][1];
13865}
13866
13867// getRecordFormOpcode
13868LLVM_READONLY
13869int getRecordFormOpcode(uint16_t Opcode) {
13870 using namespace PPC;
13871 static constexpr uint16_t Table[][2] = {
13872 { ADD4, ADD4_rec },
13873 { ADD4O, ADD4O_rec },
13874 { ADD8, ADD8_rec },
13875 { ADD8O, ADD8O_rec },
13876 { ADDC, ADDC_rec },
13877 { ADDC8, ADDC8_rec },
13878 { ADDC8O, ADDC8O_rec },
13879 { ADDCO, ADDCO_rec },
13880 { ADDE, ADDE_rec },
13881 { ADDE8, ADDE8_rec },
13882 { ADDE8O, ADDE8O_rec },
13883 { ADDEO, ADDEO_rec },
13884 { ADDIC, ADDIC_rec },
13885 { ADDME, ADDME_rec },
13886 { ADDME8, ADDME8_rec },
13887 { ADDME8O, ADDME8O_rec },
13888 { ADDMEO, ADDMEO_rec },
13889 { ADDZE, ADDZE_rec },
13890 { ADDZE8, ADDZE8_rec },
13891 { ADDZE8O, ADDZE8O_rec },
13892 { ADDZEO, ADDZEO_rec },
13893 { AND, AND_rec },
13894 { AND8, AND8_rec },
13895 { ANDC, ANDC_rec },
13896 { ANDC8, ANDC8_rec },
13897 { CNTLZD, CNTLZD_rec },
13898 { CNTLZW, CNTLZW_rec },
13899 { CNTLZW8, CNTLZW8_rec },
13900 { CNTTZD, CNTTZD_rec },
13901 { CNTTZW, CNTTZW_rec },
13902 { CNTTZW8, CNTTZW8_rec },
13903 { DADD, DADD_rec },
13904 { DADDQ, DADDQ_rec },
13905 { DCFFIX, DCFFIX_rec },
13906 { DCFFIXQ, DCFFIXQ_rec },
13907 { DCTDP, DCTDP_rec },
13908 { DCTFIX, DCTFIX_rec },
13909 { DCTFIXQ, DCTFIXQ_rec },
13910 { DCTQPQ, DCTQPQ_rec },
13911 { DDEDPD, DDEDPD_rec },
13912 { DDEDPDQ, DDEDPDQ_rec },
13913 { DDIV, DDIV_rec },
13914 { DDIVQ, DDIVQ_rec },
13915 { DENBCD, DENBCD_rec },
13916 { DENBCDQ, DENBCDQ_rec },
13917 { DIEX, DIEX_rec },
13918 { DIEXQ, DIEXQ_rec },
13919 { DIVD, DIVD_rec },
13920 { DIVDE, DIVDE_rec },
13921 { DIVDEO, DIVDEO_rec },
13922 { DIVDEU, DIVDEU_rec },
13923 { DIVDEUO, DIVDEUO_rec },
13924 { DIVDO, DIVDO_rec },
13925 { DIVDU, DIVDU_rec },
13926 { DIVDUO, DIVDUO_rec },
13927 { DIVW, DIVW_rec },
13928 { DIVWE, DIVWE_rec },
13929 { DIVWEO, DIVWEO_rec },
13930 { DIVWEU, DIVWEU_rec },
13931 { DIVWEUO, DIVWEUO_rec },
13932 { DIVWO, DIVWO_rec },
13933 { DIVWU, DIVWU_rec },
13934 { DIVWUO, DIVWUO_rec },
13935 { DMUL, DMUL_rec },
13936 { DMULQ, DMULQ_rec },
13937 { DQUA, DQUA_rec },
13938 { DQUAI, DQUAI_rec },
13939 { DQUAIQ, DQUAIQ_rec },
13940 { DQUAQ, DQUAQ_rec },
13941 { DRDPQ, DRDPQ_rec },
13942 { DRINTN, DRINTN_rec },
13943 { DRINTNQ, DRINTNQ_rec },
13944 { DRINTX, DRINTX_rec },
13945 { DRINTXQ, DRINTXQ_rec },
13946 { DRRND, DRRND_rec },
13947 { DRRNDQ, DRRNDQ_rec },
13948 { DRSP, DRSP_rec },
13949 { DSCLI, DSCLI_rec },
13950 { DSCLIQ, DSCLIQ_rec },
13951 { DSCRI, DSCRI_rec },
13952 { DSCRIQ, DSCRIQ_rec },
13953 { DSUB, DSUB_rec },
13954 { DSUBQ, DSUBQ_rec },
13955 { DXEX, DXEX_rec },
13956 { DXEXQ, DXEXQ_rec },
13957 { EQV, EQV_rec },
13958 { EQV8, EQV8_rec },
13959 { EXTSB, EXTSB_rec },
13960 { EXTSB8, EXTSB8_rec },
13961 { EXTSH, EXTSH_rec },
13962 { EXTSH8, EXTSH8_rec },
13963 { EXTSW, EXTSW_rec },
13964 { EXTSWSLI, EXTSWSLI_rec },
13965 { EXTSWSLI_32_64, EXTSWSLI_32_64_rec },
13966 { EXTSW_32_64, EXTSW_32_64_rec },
13967 { FABSD, FABSD_rec },
13968 { FABSS, FABSS_rec },
13969 { FADD, FADD_rec },
13970 { FADDS, FADDS_rec },
13971 { FCFID, FCFID_rec },
13972 { FCFIDS, FCFIDS_rec },
13973 { FCFIDU, FCFIDU_rec },
13974 { FCFIDUS, FCFIDUS_rec },
13975 { FCPSGND, FCPSGND_rec },
13976 { FCPSGNS, FCPSGNS_rec },
13977 { FCTID, FCTID_rec },
13978 { FCTIDU, FCTIDU_rec },
13979 { FCTIDUZ, FCTIDUZ_rec },
13980 { FCTIDZ, FCTIDZ_rec },
13981 { FCTIW, FCTIW_rec },
13982 { FCTIWU, FCTIWU_rec },
13983 { FCTIWUZ, FCTIWUZ_rec },
13984 { FCTIWZ, FCTIWZ_rec },
13985 { FDIV, FDIV_rec },
13986 { FDIVS, FDIVS_rec },
13987 { FMADD, FMADD_rec },
13988 { FMADDS, FMADDS_rec },
13989 { FMR, FMR_rec },
13990 { FMSUB, FMSUB_rec },
13991 { FMSUBS, FMSUBS_rec },
13992 { FMUL, FMUL_rec },
13993 { FMULS, FMULS_rec },
13994 { FNABSD, FNABSD_rec },
13995 { FNABSS, FNABSS_rec },
13996 { FNEGD, FNEGD_rec },
13997 { FNEGS, FNEGS_rec },
13998 { FNMADD, FNMADD_rec },
13999 { FNMADDS, FNMADDS_rec },
14000 { FNMSUB, FNMSUB_rec },
14001 { FNMSUBS, FNMSUBS_rec },
14002 { FRE, FRE_rec },
14003 { FRES, FRES_rec },
14004 { FRIMD, FRIMD_rec },
14005 { FRIMS, FRIMS_rec },
14006 { FRIND, FRIND_rec },
14007 { FRINS, FRINS_rec },
14008 { FRIPD, FRIPD_rec },
14009 { FRIPS, FRIPS_rec },
14010 { FRIZD, FRIZD_rec },
14011 { FRIZS, FRIZS_rec },
14012 { FRSP, FRSP_rec },
14013 { FRSQRTE, FRSQRTE_rec },
14014 { FRSQRTES, FRSQRTES_rec },
14015 { FSELD, FSELD_rec },
14016 { FSELS, FSELS_rec },
14017 { FSQRT, FSQRT_rec },
14018 { FSQRTS, FSQRTS_rec },
14019 { FSUB, FSUB_rec },
14020 { FSUBS, FSUBS_rec },
14021 { MULHD, MULHD_rec },
14022 { MULHDU, MULHDU_rec },
14023 { MULHW, MULHW_rec },
14024 { MULHWU, MULHWU_rec },
14025 { MULLD, MULLD_rec },
14026 { MULLDO, MULLDO_rec },
14027 { MULLW, MULLW_rec },
14028 { MULLWO, MULLWO_rec },
14029 { NAND, NAND_rec },
14030 { NAND8, NAND8_rec },
14031 { NEG, NEG_rec },
14032 { NEG8, NEG8_rec },
14033 { NEG8O, NEG8O_rec },
14034 { NEGO, NEGO_rec },
14035 { NOR, NOR_rec },
14036 { NOR8, NOR8_rec },
14037 { OR, OR_rec },
14038 { OR8, OR8_rec },
14039 { ORC, ORC_rec },
14040 { ORC8, ORC8_rec },
14041 { RLDCL, RLDCL_rec },
14042 { RLDCR, RLDCR_rec },
14043 { RLDIC, RLDIC_rec },
14044 { RLDICL, RLDICL_rec },
14045 { RLDICL_32, RLDICL_32_rec },
14046 { RLDICR, RLDICR_rec },
14047 { RLDIMI, RLDIMI_rec },
14048 { RLWIMI, RLWIMI_rec },
14049 { RLWIMI8, RLWIMI8_rec },
14050 { RLWINM, RLWINM_rec },
14051 { RLWINM8, RLWINM8_rec },
14052 { RLWNM, RLWNM_rec },
14053 { RLWNM8, RLWNM8_rec },
14054 { SLD, SLD_rec },
14055 { SLW, SLW_rec },
14056 { SLW8, SLW8_rec },
14057 { SRAD, SRAD_rec },
14058 { SRADI, SRADI_rec },
14059 { SRAW, SRAW_rec },
14060 { SRAW8, SRAW8_rec },
14061 { SRAWI, SRAWI_rec },
14062 { SRAWI8, SRAWI8_rec },
14063 { SRD, SRD_rec },
14064 { SRW, SRW_rec },
14065 { SRW8, SRW8_rec },
14066 { SUBF, SUBF_rec },
14067 { SUBF8, SUBF8_rec },
14068 { SUBF8O, SUBF8O_rec },
14069 { SUBFC, SUBFC_rec },
14070 { SUBFC8, SUBFC8_rec },
14071 { SUBFC8O, SUBFC8O_rec },
14072 { SUBFCO, SUBFCO_rec },
14073 { SUBFE, SUBFE_rec },
14074 { SUBFE8, SUBFE8_rec },
14075 { SUBFE8O, SUBFE8O_rec },
14076 { SUBFEO, SUBFEO_rec },
14077 { SUBFME, SUBFME_rec },
14078 { SUBFME8, SUBFME8_rec },
14079 { SUBFME8O, SUBFME8O_rec },
14080 { SUBFMEO, SUBFMEO_rec },
14081 { SUBFO, SUBFO_rec },
14082 { SUBFUS, SUBFUS_rec },
14083 { SUBFZE, SUBFZE_rec },
14084 { SUBFZE8, SUBFZE8_rec },
14085 { SUBFZE8O, SUBFZE8O_rec },
14086 { SUBFZEO, SUBFZEO_rec },
14087 { VSTRIBL, VSTRIBL_rec },
14088 { VSTRIBR, VSTRIBR_rec },
14089 { VSTRIHL, VSTRIHL_rec },
14090 { VSTRIHR, VSTRIHR_rec },
14091 { XOR, XOR_rec },
14092 { XOR8, XOR8_rec },
14093 }; // End of Table
14094
14095 unsigned mid;
14096 unsigned start = 0;
14097 unsigned end = 221;
14098 while (start < end) {
14099 mid = start + (end - start) / 2;
14100 if (Opcode == Table[mid][0])
14101 break;
14102 if (Opcode < Table[mid][0])
14103 end = mid;
14104 else
14105 start = mid + 1;
14106 }
14107 if (start == end)
14108 return -1; // Instruction doesn't exist in this table.
14109
14110 return Table[mid][1];
14111}
14112
14113} // end namespace llvm::PPC
14114#endif // GET_INSTRMAP_INFO
14115
14116