1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass PPCMCRegisterClasses[];
17
18namespace PPC {
19enum : unsigned {
20 NoRegister,
21 BP = 1,
22 CARRY = 2,
23 CTR = 3,
24 FP = 4,
25 LR = 5,
26 RM = 6,
27 SPEFSCR = 7,
28 VRSAVE = 8,
29 XER = 9,
30 ZERO = 10,
31 ACC0 = 11,
32 ACC1 = 12,
33 ACC2 = 13,
34 ACC3 = 14,
35 ACC4 = 15,
36 ACC5 = 16,
37 ACC6 = 17,
38 ACC7 = 18,
39 BP8 = 19,
40 CR0 = 20,
41 CR1 = 21,
42 CR2 = 22,
43 CR3 = 23,
44 CR4 = 24,
45 CR5 = 25,
46 CR6 = 26,
47 CR7 = 27,
48 CTR8 = 28,
49 DMR0 = 29,
50 DMR1 = 30,
51 DMR2 = 31,
52 DMR3 = 32,
53 DMR4 = 33,
54 DMR5 = 34,
55 DMR6 = 35,
56 DMR7 = 36,
57 DMRROW0 = 37,
58 DMRROW1 = 38,
59 DMRROW2 = 39,
60 DMRROW3 = 40,
61 DMRROW4 = 41,
62 DMRROW5 = 42,
63 DMRROW6 = 43,
64 DMRROW7 = 44,
65 DMRROW8 = 45,
66 DMRROW9 = 46,
67 DMRROW10 = 47,
68 DMRROW11 = 48,
69 DMRROW12 = 49,
70 DMRROW13 = 50,
71 DMRROW14 = 51,
72 DMRROW15 = 52,
73 DMRROW16 = 53,
74 DMRROW17 = 54,
75 DMRROW18 = 55,
76 DMRROW19 = 56,
77 DMRROW20 = 57,
78 DMRROW21 = 58,
79 DMRROW22 = 59,
80 DMRROW23 = 60,
81 DMRROW24 = 61,
82 DMRROW25 = 62,
83 DMRROW26 = 63,
84 DMRROW27 = 64,
85 DMRROW28 = 65,
86 DMRROW29 = 66,
87 DMRROW30 = 67,
88 DMRROW31 = 68,
89 DMRROW32 = 69,
90 DMRROW33 = 70,
91 DMRROW34 = 71,
92 DMRROW35 = 72,
93 DMRROW36 = 73,
94 DMRROW37 = 74,
95 DMRROW38 = 75,
96 DMRROW39 = 76,
97 DMRROW40 = 77,
98 DMRROW41 = 78,
99 DMRROW42 = 79,
100 DMRROW43 = 80,
101 DMRROW44 = 81,
102 DMRROW45 = 82,
103 DMRROW46 = 83,
104 DMRROW47 = 84,
105 DMRROW48 = 85,
106 DMRROW49 = 86,
107 DMRROW50 = 87,
108 DMRROW51 = 88,
109 DMRROW52 = 89,
110 DMRROW53 = 90,
111 DMRROW54 = 91,
112 DMRROW55 = 92,
113 DMRROW56 = 93,
114 DMRROW57 = 94,
115 DMRROW58 = 95,
116 DMRROW59 = 96,
117 DMRROW60 = 97,
118 DMRROW61 = 98,
119 DMRROW62 = 99,
120 DMRROW63 = 100,
121 DMRROWp0 = 101,
122 DMRROWp1 = 102,
123 DMRROWp2 = 103,
124 DMRROWp3 = 104,
125 DMRROWp4 = 105,
126 DMRROWp5 = 106,
127 DMRROWp6 = 107,
128 DMRROWp7 = 108,
129 DMRROWp8 = 109,
130 DMRROWp9 = 110,
131 DMRROWp10 = 111,
132 DMRROWp11 = 112,
133 DMRROWp12 = 113,
134 DMRROWp13 = 114,
135 DMRROWp14 = 115,
136 DMRROWp15 = 116,
137 DMRROWp16 = 117,
138 DMRROWp17 = 118,
139 DMRROWp18 = 119,
140 DMRROWp19 = 120,
141 DMRROWp20 = 121,
142 DMRROWp21 = 122,
143 DMRROWp22 = 123,
144 DMRROWp23 = 124,
145 DMRROWp24 = 125,
146 DMRROWp25 = 126,
147 DMRROWp26 = 127,
148 DMRROWp27 = 128,
149 DMRROWp28 = 129,
150 DMRROWp29 = 130,
151 DMRROWp30 = 131,
152 DMRROWp31 = 132,
153 DMRp0 = 133,
154 DMRp1 = 134,
155 DMRp2 = 135,
156 DMRp3 = 136,
157 F0 = 137,
158 F1 = 138,
159 F2 = 139,
160 F3 = 140,
161 F4 = 141,
162 F5 = 142,
163 F6 = 143,
164 F7 = 144,
165 F8 = 145,
166 F9 = 146,
167 F10 = 147,
168 F11 = 148,
169 F12 = 149,
170 F13 = 150,
171 F14 = 151,
172 F15 = 152,
173 F16 = 153,
174 F17 = 154,
175 F18 = 155,
176 F19 = 156,
177 F20 = 157,
178 F21 = 158,
179 F22 = 159,
180 F23 = 160,
181 F24 = 161,
182 F25 = 162,
183 F26 = 163,
184 F27 = 164,
185 F28 = 165,
186 F29 = 166,
187 F30 = 167,
188 F31 = 168,
189 FH0 = 169,
190 FH1 = 170,
191 FH2 = 171,
192 FH3 = 172,
193 FH4 = 173,
194 FH5 = 174,
195 FH6 = 175,
196 FH7 = 176,
197 FH8 = 177,
198 FH9 = 178,
199 FH10 = 179,
200 FH11 = 180,
201 FH12 = 181,
202 FH13 = 182,
203 FH14 = 183,
204 FH15 = 184,
205 FH16 = 185,
206 FH17 = 186,
207 FH18 = 187,
208 FH19 = 188,
209 FH20 = 189,
210 FH21 = 190,
211 FH22 = 191,
212 FH23 = 192,
213 FH24 = 193,
214 FH25 = 194,
215 FH26 = 195,
216 FH27 = 196,
217 FH28 = 197,
218 FH29 = 198,
219 FH30 = 199,
220 FH31 = 200,
221 FP8 = 201,
222 Fpair0 = 202,
223 Fpair2 = 203,
224 Fpair4 = 204,
225 Fpair6 = 205,
226 Fpair8 = 206,
227 Fpair10 = 207,
228 Fpair12 = 208,
229 Fpair14 = 209,
230 Fpair16 = 210,
231 Fpair18 = 211,
232 Fpair20 = 212,
233 Fpair22 = 213,
234 Fpair24 = 214,
235 Fpair26 = 215,
236 Fpair28 = 216,
237 Fpair30 = 217,
238 H0 = 218,
239 H1 = 219,
240 H2 = 220,
241 H3 = 221,
242 H4 = 222,
243 H5 = 223,
244 H6 = 224,
245 H7 = 225,
246 H8 = 226,
247 H9 = 227,
248 H10 = 228,
249 H11 = 229,
250 H12 = 230,
251 H13 = 231,
252 H14 = 232,
253 H15 = 233,
254 H16 = 234,
255 H17 = 235,
256 H18 = 236,
257 H19 = 237,
258 H20 = 238,
259 H21 = 239,
260 H22 = 240,
261 H23 = 241,
262 H24 = 242,
263 H25 = 243,
264 H26 = 244,
265 H27 = 245,
266 H28 = 246,
267 H29 = 247,
268 H30 = 248,
269 H31 = 249,
270 LR8 = 250,
271 R0 = 251,
272 R1 = 252,
273 R2 = 253,
274 R3 = 254,
275 R4 = 255,
276 R5 = 256,
277 R6 = 257,
278 R7 = 258,
279 R8 = 259,
280 R9 = 260,
281 R10 = 261,
282 R11 = 262,
283 R12 = 263,
284 R13 = 264,
285 R14 = 265,
286 R15 = 266,
287 R16 = 267,
288 R17 = 268,
289 R18 = 269,
290 R19 = 270,
291 R20 = 271,
292 R21 = 272,
293 R22 = 273,
294 R23 = 274,
295 R24 = 275,
296 R25 = 276,
297 R26 = 277,
298 R27 = 278,
299 R28 = 279,
300 R29 = 280,
301 R30 = 281,
302 R31 = 282,
303 S0 = 283,
304 S1 = 284,
305 S2 = 285,
306 S3 = 286,
307 S4 = 287,
308 S5 = 288,
309 S6 = 289,
310 S7 = 290,
311 S8 = 291,
312 S9 = 292,
313 S10 = 293,
314 S11 = 294,
315 S12 = 295,
316 S13 = 296,
317 S14 = 297,
318 S15 = 298,
319 S16 = 299,
320 S17 = 300,
321 S18 = 301,
322 S19 = 302,
323 S20 = 303,
324 S21 = 304,
325 S22 = 305,
326 S23 = 306,
327 S24 = 307,
328 S25 = 308,
329 S26 = 309,
330 S27 = 310,
331 S28 = 311,
332 S29 = 312,
333 S30 = 313,
334 S31 = 314,
335 UACC0 = 315,
336 UACC1 = 316,
337 UACC2 = 317,
338 UACC3 = 318,
339 UACC4 = 319,
340 UACC5 = 320,
341 UACC6 = 321,
342 UACC7 = 322,
343 V0 = 323,
344 V1 = 324,
345 V2 = 325,
346 V3 = 326,
347 V4 = 327,
348 V5 = 328,
349 V6 = 329,
350 V7 = 330,
351 V8 = 331,
352 V9 = 332,
353 V10 = 333,
354 V11 = 334,
355 V12 = 335,
356 V13 = 336,
357 V14 = 337,
358 V15 = 338,
359 V16 = 339,
360 V17 = 340,
361 V18 = 341,
362 V19 = 342,
363 V20 = 343,
364 V21 = 344,
365 V22 = 345,
366 V23 = 346,
367 V24 = 347,
368 V25 = 348,
369 V26 = 349,
370 V27 = 350,
371 V28 = 351,
372 V29 = 352,
373 V30 = 353,
374 V31 = 354,
375 VF0 = 355,
376 VF1 = 356,
377 VF2 = 357,
378 VF3 = 358,
379 VF4 = 359,
380 VF5 = 360,
381 VF6 = 361,
382 VF7 = 362,
383 VF8 = 363,
384 VF9 = 364,
385 VF10 = 365,
386 VF11 = 366,
387 VF12 = 367,
388 VF13 = 368,
389 VF14 = 369,
390 VF15 = 370,
391 VF16 = 371,
392 VF17 = 372,
393 VF18 = 373,
394 VF19 = 374,
395 VF20 = 375,
396 VF21 = 376,
397 VF22 = 377,
398 VF23 = 378,
399 VF24 = 379,
400 VF25 = 380,
401 VF26 = 381,
402 VF27 = 382,
403 VF28 = 383,
404 VF29 = 384,
405 VF30 = 385,
406 VF31 = 386,
407 VFH0 = 387,
408 VFH1 = 388,
409 VFH2 = 389,
410 VFH3 = 390,
411 VFH4 = 391,
412 VFH5 = 392,
413 VFH6 = 393,
414 VFH7 = 394,
415 VFH8 = 395,
416 VFH9 = 396,
417 VFH10 = 397,
418 VFH11 = 398,
419 VFH12 = 399,
420 VFH13 = 400,
421 VFH14 = 401,
422 VFH15 = 402,
423 VFH16 = 403,
424 VFH17 = 404,
425 VFH18 = 405,
426 VFH19 = 406,
427 VFH20 = 407,
428 VFH21 = 408,
429 VFH22 = 409,
430 VFH23 = 410,
431 VFH24 = 411,
432 VFH25 = 412,
433 VFH26 = 413,
434 VFH27 = 414,
435 VFH28 = 415,
436 VFH29 = 416,
437 VFH30 = 417,
438 VFH31 = 418,
439 VSL0 = 419,
440 VSL1 = 420,
441 VSL2 = 421,
442 VSL3 = 422,
443 VSL4 = 423,
444 VSL5 = 424,
445 VSL6 = 425,
446 VSL7 = 426,
447 VSL8 = 427,
448 VSL9 = 428,
449 VSL10 = 429,
450 VSL11 = 430,
451 VSL12 = 431,
452 VSL13 = 432,
453 VSL14 = 433,
454 VSL15 = 434,
455 VSL16 = 435,
456 VSL17 = 436,
457 VSL18 = 437,
458 VSL19 = 438,
459 VSL20 = 439,
460 VSL21 = 440,
461 VSL22 = 441,
462 VSL23 = 442,
463 VSL24 = 443,
464 VSL25 = 444,
465 VSL26 = 445,
466 VSL27 = 446,
467 VSL28 = 447,
468 VSL29 = 448,
469 VSL30 = 449,
470 VSL31 = 450,
471 VSRp0 = 451,
472 VSRp1 = 452,
473 VSRp2 = 453,
474 VSRp3 = 454,
475 VSRp4 = 455,
476 VSRp5 = 456,
477 VSRp6 = 457,
478 VSRp7 = 458,
479 VSRp8 = 459,
480 VSRp9 = 460,
481 VSRp10 = 461,
482 VSRp11 = 462,
483 VSRp12 = 463,
484 VSRp13 = 464,
485 VSRp14 = 465,
486 VSRp15 = 466,
487 VSRp16 = 467,
488 VSRp17 = 468,
489 VSRp18 = 469,
490 VSRp19 = 470,
491 VSRp20 = 471,
492 VSRp21 = 472,
493 VSRp22 = 473,
494 VSRp23 = 474,
495 VSRp24 = 475,
496 VSRp25 = 476,
497 VSRp26 = 477,
498 VSRp27 = 478,
499 VSRp28 = 479,
500 VSRp29 = 480,
501 VSRp30 = 481,
502 VSRp31 = 482,
503 VSX32 = 483,
504 VSX33 = 484,
505 VSX34 = 485,
506 VSX35 = 486,
507 VSX36 = 487,
508 VSX37 = 488,
509 VSX38 = 489,
510 VSX39 = 490,
511 VSX40 = 491,
512 VSX41 = 492,
513 VSX42 = 493,
514 VSX43 = 494,
515 VSX44 = 495,
516 VSX45 = 496,
517 VSX46 = 497,
518 VSX47 = 498,
519 VSX48 = 499,
520 VSX49 = 500,
521 VSX50 = 501,
522 VSX51 = 502,
523 VSX52 = 503,
524 VSX53 = 504,
525 VSX54 = 505,
526 VSX55 = 506,
527 VSX56 = 507,
528 VSX57 = 508,
529 VSX58 = 509,
530 VSX59 = 510,
531 VSX60 = 511,
532 VSX61 = 512,
533 VSX62 = 513,
534 VSX63 = 514,
535 WACC0 = 515,
536 WACC1 = 516,
537 WACC2 = 517,
538 WACC3 = 518,
539 WACC4 = 519,
540 WACC5 = 520,
541 WACC6 = 521,
542 WACC7 = 522,
543 WACC_HI0 = 523,
544 WACC_HI1 = 524,
545 WACC_HI2 = 525,
546 WACC_HI3 = 526,
547 WACC_HI4 = 527,
548 WACC_HI5 = 528,
549 WACC_HI6 = 529,
550 WACC_HI7 = 530,
551 X0 = 531,
552 X1 = 532,
553 X2 = 533,
554 X3 = 534,
555 X4 = 535,
556 X5 = 536,
557 X6 = 537,
558 X7 = 538,
559 X8 = 539,
560 X9 = 540,
561 X10 = 541,
562 X11 = 542,
563 X12 = 543,
564 X13 = 544,
565 X14 = 545,
566 X15 = 546,
567 X16 = 547,
568 X17 = 548,
569 X18 = 549,
570 X19 = 550,
571 X20 = 551,
572 X21 = 552,
573 X22 = 553,
574 X23 = 554,
575 X24 = 555,
576 X25 = 556,
577 X26 = 557,
578 X27 = 558,
579 X28 = 559,
580 X29 = 560,
581 X30 = 561,
582 X31 = 562,
583 ZERO8 = 563,
584 CR0EQ = 564,
585 CR1EQ = 565,
586 CR2EQ = 566,
587 CR3EQ = 567,
588 CR4EQ = 568,
589 CR5EQ = 569,
590 CR6EQ = 570,
591 CR7EQ = 571,
592 CR0GT = 572,
593 CR1GT = 573,
594 CR2GT = 574,
595 CR3GT = 575,
596 CR4GT = 576,
597 CR5GT = 577,
598 CR6GT = 578,
599 CR7GT = 579,
600 CR0LT = 580,
601 CR1LT = 581,
602 CR2LT = 582,
603 CR3LT = 583,
604 CR4LT = 584,
605 CR5LT = 585,
606 CR6LT = 586,
607 CR7LT = 587,
608 CR0UN = 588,
609 CR1UN = 589,
610 CR2UN = 590,
611 CR3UN = 591,
612 CR4UN = 592,
613 CR5UN = 593,
614 CR6UN = 594,
615 CR7UN = 595,
616 G8p0 = 596,
617 G8p1 = 597,
618 G8p2 = 598,
619 G8p3 = 599,
620 G8p4 = 600,
621 G8p5 = 601,
622 G8p6 = 602,
623 G8p7 = 603,
624 G8p8 = 604,
625 G8p9 = 605,
626 G8p10 = 606,
627 G8p11 = 607,
628 G8p12 = 608,
629 G8p13 = 609,
630 G8p14 = 610,
631 G8p15 = 611,
632 NUM_TARGET_REGS // 612
633};
634} // end namespace PPC
635
636// Register classes
637
638namespace PPC {
639enum {
640 VSSRCRegClassID = 0,
641 GPRCRegClassID = 1,
642 GPRC_NOR0RegClassID = 2,
643 GPRC_and_GPRC_NOR0RegClassID = 3,
644 CRBITRCRegClassID = 4,
645 F4RCRegClassID = 5,
646 GPRC32RegClassID = 6,
647 CRRCRegClassID = 7,
648 CARRYRCRegClassID = 8,
649 CTRRCRegClassID = 9,
650 LRRCRegClassID = 10,
651 VRSAVERCRegClassID = 11,
652 SPILLTOVSRRCRegClassID = 12,
653 VSFRCRegClassID = 13,
654 G8RCRegClassID = 14,
655 G8RC_NOX0RegClassID = 15,
656 SPILLTOVSRRC_and_VSFRCRegClassID = 16,
657 G8RC_and_G8RC_NOX0RegClassID = 17,
658 F8RCRegClassID = 18,
659 FHRCRegClassID = 19,
660 SPERCRegClassID = 20,
661 VFHRCRegClassID = 21,
662 VFRCRegClassID = 22,
663 SPERC_with_sub_32_in_GPRC_NOR0RegClassID = 23,
664 SPILLTOVSRRC_and_VFRCRegClassID = 24,
665 SPILLTOVSRRC_and_F4RCRegClassID = 25,
666 CTRRC8RegClassID = 26,
667 LR8RCRegClassID = 27,
668 DMRROWRCRegClassID = 28,
669 VSRCRegClassID = 29,
670 VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 30,
671 VRRCRegClassID = 31,
672 VSLRCRegClassID = 32,
673 VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 33,
674 FpRCRegClassID = 34,
675 G8pRCRegClassID = 35,
676 G8pRC_with_sub_32_in_GPRC_NOR0RegClassID = 36,
677 VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 37,
678 FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID = 38,
679 DMRROWpRCRegClassID = 39,
680 VSRpRCRegClassID = 40,
681 VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 41,
682 VSRpRC_with_sub_64_in_F4RCRegClassID = 42,
683 VSRpRC_with_sub_64_in_VFRCRegClassID = 43,
684 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID = 44,
685 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID = 45,
686 ACCRCRegClassID = 46,
687 UACCRCRegClassID = 47,
688 WACCRCRegClassID = 48,
689 WACC_HIRCRegClassID = 49,
690 ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 50,
691 UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 51,
692 ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 52,
693 UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 53,
694 DMRRCRegClassID = 54,
695 DMRpRCRegClassID = 55,
696
697};
698} // end namespace PPC
699
700
701// Subregister indices
702
703namespace PPC {
704enum : uint16_t {
705 NoSubRegister,
706 sub_32, // 1
707 sub_32_hi_phony, // 2
708 sub_64, // 3
709 sub_64_hi_phony, // 4
710 sub_dmr0, // 5
711 sub_dmr1, // 6
712 sub_dmrrow0, // 7
713 sub_dmrrow1, // 8
714 sub_dmrrowp0, // 9
715 sub_dmrrowp1, // 10
716 sub_eq, // 11
717 sub_fp0, // 12
718 sub_fp1, // 13
719 sub_gp8_x0, // 14
720 sub_gp8_x1, // 15
721 sub_gt, // 16
722 sub_lt, // 17
723 sub_pair0, // 18
724 sub_pair1, // 19
725 sub_un, // 20
726 sub_vsx0, // 21
727 sub_vsx1, // 22
728 sub_wacc_hi, // 23
729 sub_wacc_lo, // 24
730 sub_vsx1_then_sub_64, // 25
731 sub_vsx1_then_sub_64_hi_phony, // 26
732 sub_pair1_then_sub_64, // 27
733 sub_pair1_then_sub_64_hi_phony, // 28
734 sub_pair1_then_sub_vsx0, // 29
735 sub_pair1_then_sub_vsx1, // 30
736 sub_pair1_then_sub_vsx1_then_sub_64, // 31
737 sub_pair1_then_sub_vsx1_then_sub_64_hi_phony, // 32
738 sub_dmrrowp1_then_sub_dmrrow0, // 33
739 sub_dmrrowp1_then_sub_dmrrow1, // 34
740 sub_wacc_hi_then_sub_dmrrow0, // 35
741 sub_wacc_hi_then_sub_dmrrow1, // 36
742 sub_wacc_hi_then_sub_dmrrowp0, // 37
743 sub_wacc_hi_then_sub_dmrrowp1, // 38
744 sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 39
745 sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 40
746 sub_dmr1_then_sub_dmrrow0, // 41
747 sub_dmr1_then_sub_dmrrow1, // 42
748 sub_dmr1_then_sub_dmrrowp0, // 43
749 sub_dmr1_then_sub_dmrrowp1, // 44
750 sub_dmr1_then_sub_wacc_hi, // 45
751 sub_dmr1_then_sub_wacc_lo, // 46
752 sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, // 47
753 sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, // 48
754 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, // 49
755 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, // 50
756 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, // 51
757 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, // 52
758 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 53
759 sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 54
760 sub_gp8_x1_then_sub_32, // 55
761 NUM_TARGET_SUBREGS
762};
763} // end namespace PPC
764
765// Register pressure sets enum.
766namespace PPC {
767enum RegisterPressureSets {
768 VRSAVERC = 0,
769 SPILLTOVSRRC_and_F4RC = 1,
770 SPILLTOVSRRC_and_VFRC = 2,
771 CRBITRC = 3,
772 F4RC = 4,
773 VFRC = 5,
774 WACCRC = 6,
775 WACC_HIRC = 7,
776 GPRC = 8,
777 SPILLTOVSRRC_and_VSFRC = 9,
778 SPILLTOVSRRC_and_VSFRC_with_VFRC = 10,
779 F4RC_with_SPILLTOVSRRC_and_VSFRC = 11,
780 VSSRC = 12,
781 DMRROWRC = 13,
782 SPILLTOVSRRC = 14,
783 SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC = 15,
784 SPILLTOVSRRC_with_VFRC = 16,
785 F4RC_with_SPILLTOVSRRC = 17,
786 VSSRC_with_SPILLTOVSRRC = 18,
787};
788} // end namespace PPC
789
790} // end namespace llvm
791
792#endif // GET_REGINFO_ENUM
793
794/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
795|* *|
796|* MC Register Information *|
797|* *|
798|* Automatically generated file, do not edit! *|
799|* *|
800\*===----------------------------------------------------------------------===*/
801
802
803#ifdef GET_REGINFO_MC_DESC
804#undef GET_REGINFO_MC_DESC
805
806namespace llvm {
807
808extern const int16_t PPCRegDiffLists[] = {
809 /* 0 */ -568, 0,
810 /* 2 */ -560, 0,
811 /* 4 */ -553, 0,
812 /* 6 */ -552, 0,
813 /* 8 */ -544, 0,
814 /* 10 */ -65, -280, 281, -280, 0,
815 /* 15 */ -64, -280, 281, -280, 0,
816 /* 20 */ -63, -280, 281, -280, 0,
817 /* 25 */ -62, -280, 281, -280, 0,
818 /* 30 */ -61, -280, 281, -280, 0,
819 /* 35 */ -60, -280, 281, -280, 0,
820 /* 40 */ -59, -280, 281, -280, 0,
821 /* 45 */ -58, -280, 281, -280, 0,
822 /* 50 */ -57, -280, 281, -280, 0,
823 /* 55 */ -56, -280, 281, -280, 0,
824 /* 60 */ -55, -280, 281, -280, 0,
825 /* 65 */ -54, -280, 281, -280, 0,
826 /* 70 */ -53, -280, 281, -280, 0,
827 /* 75 */ -52, -280, 281, -280, 0,
828 /* 80 */ -51, -280, 281, -280, 0,
829 /* 85 */ -50, -280, 281, -280, 0,
830 /* 90 */ -197, 0,
831 /* 92 */ -32, -33, 0,
832 /* 95 */ -18, 0,
833 /* 97 */ -65, 1, 0,
834 /* 100 */ -64, 1, 0,
835 /* 103 */ -414, -64, 1, 64, -63, 1, 0,
836 /* 110 */ -62, 1, 0,
837 /* 113 */ 486, -414, -64, 1, 64, -63, 1, 483, -420, -62, 1, 62, -61, 1, 0,
838 /* 128 */ -60, 1, 0,
839 /* 131 */ -411, -60, 1, 60, -59, 1, 0,
840 /* 138 */ -58, 1, 0,
841 /* 141 */ -104, 486, -414, -64, 1, 64, -63, 1, 483, -420, -62, 1, 62, -61, 1, -14, 486, -411, -60, 1, 60, -59, 1, 476, -417, -58, 1, 58, -57, 1, 0,
842 /* 172 */ -56, 1, 0,
843 /* 175 */ -408, -56, 1, 56, -55, 1, 0,
844 /* 182 */ -54, 1, 0,
845 /* 185 */ 486, -408, -56, 1, 56, -55, 1, 469, -414, -54, 1, 54, -53, 1, 0,
846 /* 200 */ -52, 1, 0,
847 /* 203 */ -405, -52, 1, 52, -51, 1, 0,
848 /* 210 */ -50, 1, 0,
849 /* 213 */ -103, 486, -408, -56, 1, 56, -55, 1, 469, -414, -54, 1, 54, -53, 1, -28, 486, -405, -52, 1, 52, -51, 1, 462, -411, -50, 1, 50, -49, 1, 0,
850 /* 244 */ -48, 1, 0,
851 /* 247 */ -402, -48, 1, 48, -47, 1, 0,
852 /* 254 */ -46, 1, 0,
853 /* 257 */ 486, -402, -48, 1, 48, -47, 1, 455, -408, -46, 1, 46, -45, 1, 0,
854 /* 272 */ -44, 1, 0,
855 /* 275 */ -399, -44, 1, 44, -43, 1, 0,
856 /* 282 */ -42, 1, 0,
857 /* 285 */ -102, 486, -402, -48, 1, 48, -47, 1, 455, -408, -46, 1, 46, -45, 1, -42, 486, -399, -44, 1, 44, -43, 1, 448, -405, -42, 1, 42, -41, 1, 0,
858 /* 316 */ -40, 1, 0,
859 /* 319 */ -396, -40, 1, 40, -39, 1, 0,
860 /* 326 */ -38, 1, 0,
861 /* 329 */ 486, -396, -40, 1, 40, -39, 1, 441, -402, -38, 1, 38, -37, 1, 0,
862 /* 344 */ -36, 1, 0,
863 /* 347 */ -393, -36, 1, 36, -35, 1, 0,
864 /* 354 */ -34, 1, 0,
865 /* 357 */ -101, 486, -396, -40, 1, 40, -39, 1, 441, -402, -38, 1, 38, -37, 1, -56, 486, -393, -36, 1, 36, -35, 1, 434, -399, -34, 1, 34, -33, 1, 0,
866 /* 388 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
867 /* 404 */ 2, 0,
868 /* 406 */ 9, 0,
869 /* 408 */ 18, 0,
870 /* 410 */ 560, -8, -8, 24, 0,
871 /* 415 */ -32, -282, 32, 251, -282, 32, 0,
872 /* 422 */ 136, -32, -282, 32, 251, -282, 32, 282, -31, -282, 32, 251, -282, 32, 0,
873 /* 437 */ 440, -32, -282, 32, 251, -282, 32, 282, -31, -282, 32, 251, -282, 32, 0,
874 /* 452 */ -30, -282, 32, 251, -282, 32, 0,
875 /* 459 */ 137, -30, -282, 32, 251, -282, 32, 280, -29, -282, 32, 251, -282, 32, 0,
876 /* 474 */ 441, -30, -282, 32, 251, -282, 32, 280, -29, -282, 32, 251, -282, 32, 0,
877 /* 489 */ -28, -282, 32, 251, -282, 32, 0,
878 /* 496 */ 138, -28, -282, 32, 251, -282, 32, 278, -27, -282, 32, 251, -282, 32, 0,
879 /* 511 */ 442, -28, -282, 32, 251, -282, 32, 278, -27, -282, 32, 251, -282, 32, 0,
880 /* 526 */ -26, -282, 32, 251, -282, 32, 0,
881 /* 533 */ 139, -26, -282, 32, 251, -282, 32, 276, -25, -282, 32, 251, -282, 32, 0,
882 /* 548 */ 443, -26, -282, 32, 251, -282, 32, 276, -25, -282, 32, 251, -282, 32, 0,
883 /* 563 */ -24, -282, 32, 251, -282, 32, 0,
884 /* 570 */ 140, -24, -282, 32, 251, -282, 32, 274, -23, -282, 32, 251, -282, 32, 0,
885 /* 585 */ 444, -24, -282, 32, 251, -282, 32, 274, -23, -282, 32, 251, -282, 32, 0,
886 /* 600 */ -22, -282, 32, 251, -282, 32, 0,
887 /* 607 */ 141, -22, -282, 32, 251, -282, 32, 272, -21, -282, 32, 251, -282, 32, 0,
888 /* 622 */ 445, -22, -282, 32, 251, -282, 32, 272, -21, -282, 32, 251, -282, 32, 0,
889 /* 637 */ -20, -282, 32, 251, -282, 32, 0,
890 /* 644 */ 142, -20, -282, 32, 251, -282, 32, 270, -19, -282, 32, 251, -282, 32, 0,
891 /* 659 */ 446, -20, -282, 32, 251, -282, 32, 270, -19, -282, 32, 251, -282, 32, 0,
892 /* 674 */ -18, -282, 32, 251, -282, 32, 0,
893 /* 681 */ 143, -18, -282, 32, 251, -282, 32, 268, -17, -282, 32, 251, -282, 32, 0,
894 /* 696 */ 447, -18, -282, 32, 251, -282, 32, 268, -17, -282, 32, 251, -282, 32, 0,
895 /* 711 */ -144, 32, 32, -63, 32, 32, 0,
896 /* 718 */ -143, 32, 32, -63, 32, 32, 0,
897 /* 725 */ -142, 32, 32, -63, 32, 32, 0,
898 /* 732 */ -141, 32, 32, -63, 32, 32, 0,
899 /* 739 */ -140, 32, 32, -63, 32, 32, 0,
900 /* 746 */ -139, 32, 32, -63, 32, 32, 0,
901 /* 753 */ -138, 32, 32, -63, 32, 32, 0,
902 /* 760 */ -137, 32, 32, -63, 32, 32, 0,
903 /* 767 */ -136, 32, 32, -63, 32, 32, 0,
904 /* 774 */ -135, 32, 32, -63, 32, 32, 0,
905 /* 781 */ -134, 32, 32, -63, 32, 32, 0,
906 /* 788 */ -133, 32, 32, -63, 32, 32, 0,
907 /* 795 */ -132, 32, 32, -63, 32, 32, 0,
908 /* 802 */ -131, 32, 32, -63, 32, 32, 0,
909 /* 809 */ -130, 32, 32, -63, 32, 32, 0,
910 /* 816 */ -129, 32, 32, -63, 32, 32, 0,
911 /* 823 */ 33, 0,
912 /* 825 */ 32, 248, 49, 0,
913 /* 829 */ 32, 248, 50, 0,
914 /* 833 */ 32, 248, 51, 0,
915 /* 837 */ 32, 248, 52, 0,
916 /* 841 */ 32, 248, 53, 0,
917 /* 845 */ 32, 248, 54, 0,
918 /* 849 */ 32, 248, 55, 0,
919 /* 853 */ 32, 248, 56, 0,
920 /* 857 */ 32, 248, 57, 0,
921 /* 861 */ 32, 248, 58, 0,
922 /* 865 */ 32, 248, 59, 0,
923 /* 869 */ 32, 248, 60, 0,
924 /* 873 */ 32, 248, 61, 0,
925 /* 877 */ 32, 248, 62, 0,
926 /* 881 */ 32, 248, 63, 0,
927 /* 885 */ 32, 248, 64, 0,
928 /* 889 */ 32, 248, 65, 0,
929 /* 893 */ 32, 398, -494, 100, 0,
930 /* 898 */ 33, 398, -494, 100, 0,
931 /* 903 */ 33, 399, -494, 100, 0,
932 /* 908 */ 34, 399, -494, 100, 0,
933 /* 913 */ 34, 392, -486, 100, 0,
934 /* 918 */ 35, 392, -486, 100, 0,
935 /* 923 */ 35, 393, -486, 100, 0,
936 /* 928 */ 36, 393, -486, 100, 0,
937 /* 933 */ 36, 401, -494, 101, 0,
938 /* 938 */ 37, 401, -494, 101, 0,
939 /* 943 */ 37, 402, -494, 101, 0,
940 /* 948 */ 38, 402, -494, 101, 0,
941 /* 953 */ 40, 404, -494, 101, 0,
942 /* 958 */ 41, 404, -494, 101, 0,
943 /* 963 */ 41, 405, -494, 101, 0,
944 /* 968 */ 42, 405, -494, 101, 0,
945 /* 973 */ 38, 395, -486, 101, 0,
946 /* 978 */ 39, 395, -486, 101, 0,
947 /* 983 */ 39, 396, -486, 101, 0,
948 /* 988 */ 40, 396, -486, 101, 0,
949 /* 993 */ 42, 398, -486, 101, 0,
950 /* 998 */ 43, 398, -486, 101, 0,
951 /* 1003 */ 43, 399, -486, 101, 0,
952 /* 1008 */ 44, 399, -486, 101, 0,
953 /* 1013 */ 44, 407, -494, 102, 0,
954 /* 1018 */ 45, 407, -494, 102, 0,
955 /* 1023 */ 45, 408, -494, 102, 0,
956 /* 1028 */ 46, 408, -494, 102, 0,
957 /* 1033 */ 48, 410, -494, 102, 0,
958 /* 1038 */ 49, 410, -494, 102, 0,
959 /* 1043 */ 49, 411, -494, 102, 0,
960 /* 1048 */ 50, 411, -494, 102, 0,
961 /* 1053 */ 46, 401, -486, 102, 0,
962 /* 1058 */ 47, 401, -486, 102, 0,
963 /* 1063 */ 47, 402, -486, 102, 0,
964 /* 1068 */ 48, 402, -486, 102, 0,
965 /* 1073 */ 50, 404, -486, 102, 0,
966 /* 1078 */ 51, 404, -486, 102, 0,
967 /* 1083 */ 51, 405, -486, 102, 0,
968 /* 1088 */ 52, 405, -486, 102, 0,
969 /* 1093 */ 52, 413, -494, 103, 0,
970 /* 1098 */ 53, 413, -494, 103, 0,
971 /* 1103 */ 53, 414, -494, 103, 0,
972 /* 1108 */ 54, 414, -494, 103, 0,
973 /* 1113 */ 56, 416, -494, 103, 0,
974 /* 1118 */ 57, 416, -494, 103, 0,
975 /* 1123 */ 57, 417, -494, 103, 0,
976 /* 1128 */ 58, 417, -494, 103, 0,
977 /* 1133 */ 54, 407, -486, 103, 0,
978 /* 1138 */ 55, 407, -486, 103, 0,
979 /* 1143 */ 55, 408, -486, 103, 0,
980 /* 1148 */ 56, 408, -486, 103, 0,
981 /* 1153 */ 58, 410, -486, 103, 0,
982 /* 1158 */ 59, 410, -486, 103, 0,
983 /* 1163 */ 59, 411, -486, 103, 0,
984 /* 1168 */ 60, 411, -486, 103, 0,
985 /* 1173 */ 60, 419, -494, 104, 0,
986 /* 1178 */ 61, 419, -494, 104, 0,
987 /* 1183 */ 61, 420, -494, 104, 0,
988 /* 1188 */ 62, 420, -494, 104, 0,
989 /* 1193 */ 62, 413, -486, 104, 0,
990 /* 1198 */ 63, 413, -486, 104, 0,
991 /* 1203 */ 63, 414, -486, 104, 0,
992 /* 1208 */ 64, 414, -486, 104, 0,
993 /* 1213 */ 282, 16, -448, 199, 105, 0,
994 /* 1219 */ 282, 17, -448, 199, 105, 0,
995 /* 1225 */ 282, 17, -447, 198, 106, 0,
996 /* 1231 */ 282, 18, -447, 198, 106, 0,
997 /* 1237 */ 282, 19, -447, 198, 106, 0,
998 /* 1243 */ 282, 19, -446, 197, 107, 0,
999 /* 1249 */ 282, 20, -446, 197, 107, 0,
1000 /* 1255 */ 282, 21, -446, 197, 107, 0,
1001 /* 1261 */ 282, 21, -445, 196, 108, 0,
1002 /* 1267 */ 282, 22, -445, 196, 108, 0,
1003 /* 1273 */ 282, 23, -445, 196, 108, 0,
1004 /* 1279 */ 282, 23, -444, 195, 109, 0,
1005 /* 1285 */ 282, 24, -444, 195, 109, 0,
1006 /* 1291 */ 282, 25, -444, 195, 109, 0,
1007 /* 1297 */ 282, 25, -443, 194, 110, 0,
1008 /* 1303 */ 282, 26, -443, 194, 110, 0,
1009 /* 1309 */ 282, 27, -443, 194, 110, 0,
1010 /* 1315 */ 282, 27, -442, 193, 111, 0,
1011 /* 1321 */ 282, 28, -442, 193, 111, 0,
1012 /* 1327 */ 282, 29, -442, 193, 111, 0,
1013 /* 1333 */ 282, 29, -441, 192, 112, 0,
1014 /* 1339 */ 282, 30, -441, 192, 112, 0,
1015 /* 1345 */ 282, 31, -441, 192, 112, 0,
1016 /* 1351 */ 282, 31, -440, 191, 113, 0,
1017 /* 1357 */ 282, 32, -440, 191, 113, 0,
1018 /* 1363 */ -64, 128, 0,
1019 /* 1366 */ -32, 128, 0,
1020 /* 1369 */ -64, 129, 0,
1021 /* 1372 */ -32, 129, 0,
1022 /* 1375 */ -64, 130, 0,
1023 /* 1378 */ -32, 130, 0,
1024 /* 1381 */ -64, 131, 0,
1025 /* 1384 */ -32, 131, 0,
1026 /* 1387 */ -64, 132, 0,
1027 /* 1390 */ -32, 132, 0,
1028 /* 1393 */ -64, 133, 0,
1029 /* 1396 */ -32, 133, 0,
1030 /* 1399 */ -64, 134, 0,
1031 /* 1402 */ -32, 134, 0,
1032 /* 1405 */ -64, 135, 0,
1033 /* 1408 */ -32, 135, 0,
1034 /* 1411 */ -64, 136, 0,
1035 /* 1414 */ -32, 136, 0,
1036 /* 1417 */ -64, 137, 0,
1037 /* 1420 */ -32, 137, 0,
1038 /* 1423 */ -64, 138, 0,
1039 /* 1426 */ -32, 138, 0,
1040 /* 1429 */ -64, 139, 0,
1041 /* 1432 */ -32, 139, 0,
1042 /* 1435 */ -64, 140, 0,
1043 /* 1438 */ -32, 140, 0,
1044 /* 1441 */ -64, 141, 0,
1045 /* 1444 */ -32, 141, 0,
1046 /* 1447 */ -64, 142, 0,
1047 /* 1450 */ -32, 142, 0,
1048 /* 1453 */ -64, 143, 0,
1049 /* 1456 */ -32, 143, 0,
1050 /* 1459 */ -64, 144, 0,
1051 /* 1462 */ -32, 144, 0,
1052 /* 1465 */ 197, 0,
1053 /* 1467 */ 199, 0,
1054 /* 1469 */ 250, 16, -448, 304, 0,
1055 /* 1474 */ 250, 17, -448, 304, 0,
1056 /* 1479 */ 250, 17, -447, 304, 0,
1057 /* 1484 */ 250, 18, -447, 304, 0,
1058 /* 1489 */ 250, 19, -447, 304, 0,
1059 /* 1494 */ 250, 19, -446, 304, 0,
1060 /* 1499 */ 250, 20, -446, 304, 0,
1061 /* 1504 */ 250, 21, -446, 304, 0,
1062 /* 1509 */ 250, 21, -445, 304, 0,
1063 /* 1514 */ 250, 22, -445, 304, 0,
1064 /* 1519 */ 250, 23, -445, 304, 0,
1065 /* 1524 */ 250, 23, -444, 304, 0,
1066 /* 1529 */ 250, 24, -444, 304, 0,
1067 /* 1534 */ 250, 25, -444, 304, 0,
1068 /* 1539 */ 250, 25, -443, 304, 0,
1069 /* 1544 */ 250, 26, -443, 304, 0,
1070 /* 1549 */ 250, 27, -443, 304, 0,
1071 /* 1554 */ 250, 27, -442, 304, 0,
1072 /* 1559 */ 250, 28, -442, 304, 0,
1073 /* 1564 */ 250, 29, -442, 304, 0,
1074 /* 1569 */ 250, 29, -441, 304, 0,
1075 /* 1574 */ 250, 30, -441, 304, 0,
1076 /* 1579 */ 250, 31, -441, 304, 0,
1077 /* 1584 */ 250, 31, -440, 304, 0,
1078 /* 1589 */ 250, 32, -440, 304, 0,
1079 /* 1594 */ 553, 0,
1080};
1081
1082extern const LaneBitmask PPCLaneMaskLists[] = {
1083 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001),
1084 /* 2 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
1085 /* 4 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020),
1086 /* 6 */ LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100),
1087 /* 8 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000800),
1088 /* 12 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000),
1089 /* 16 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000),
1090 /* 24 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000),
1091 /* 28 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000800000),
1092 /* 36 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000001000000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000004000000), LaneBitmask(0x0000000008000000), LaneBitmask(0x0000000010000000), LaneBitmask(0x0000000020000000), LaneBitmask(0x0000000040000000), LaneBitmask(0x0000000080000000),
1093 /* 52 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000100000000),
1094 /* 54 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask(0xFFFFFFFFFFFFFFFF),
1095};
1096
1097extern const uint16_t PPCSubRegIdxLists[] = {
1098 /* 0 */ 1,
1099 /* 1 */ 1, 2,
1100 /* 3 */ 3, 4,
1101 /* 5 */ 7, 8,
1102 /* 7 */ 12, 13,
1103 /* 9 */ 17, 16, 11, 20,
1104 /* 13 */ 21, 3, 4, 22, 25, 26,
1105 /* 19 */ 18, 21, 3, 4, 22, 25, 26, 19, 29, 27, 28, 30, 31, 32,
1106 /* 33 */ 9, 7, 8, 10, 33, 34,
1107 /* 39 */ 24, 9, 7, 8, 10, 33, 34, 23, 37, 35, 36, 38, 39, 40,
1108 /* 53 */ 5, 24, 9, 7, 8, 10, 33, 34, 23, 37, 35, 36, 38, 39, 40, 6, 46, 43, 41, 42, 44, 47, 48, 45, 51, 49, 50, 52, 53, 54,
1109 /* 83 */ 14, 1, 15, 55,
1110};
1111
1112
1113#ifdef __GNUC__
1114#pragma GCC diagnostic push
1115#pragma GCC diagnostic ignored "-Woverlength-strings"
1116#endif
1117extern const char PPCRegStrings[] = {
1118 /* 0 */ "VF10\000"
1119 /* 5 */ "VFH10\000"
1120 /* 11 */ "VSL10\000"
1121 /* 17 */ "R10\000"
1122 /* 21 */ "S10\000"
1123 /* 25 */ "V10\000"
1124 /* 29 */ "DMRROW10\000"
1125 /* 38 */ "X10\000"
1126 /* 42 */ "G8p10\000"
1127 /* 48 */ "VSRp10\000"
1128 /* 55 */ "DMRROWp10\000"
1129 /* 65 */ "Fpair10\000"
1130 /* 73 */ "VF20\000"
1131 /* 78 */ "VFH20\000"
1132 /* 84 */ "VSL20\000"
1133 /* 90 */ "R20\000"
1134 /* 94 */ "S20\000"
1135 /* 98 */ "V20\000"
1136 /* 102 */ "DMRROW20\000"
1137 /* 111 */ "X20\000"
1138 /* 115 */ "VSRp20\000"
1139 /* 122 */ "DMRROWp20\000"
1140 /* 132 */ "Fpair20\000"
1141 /* 140 */ "VF30\000"
1142 /* 145 */ "VFH30\000"
1143 /* 151 */ "VSL30\000"
1144 /* 157 */ "R30\000"
1145 /* 161 */ "S30\000"
1146 /* 165 */ "V30\000"
1147 /* 169 */ "DMRROW30\000"
1148 /* 178 */ "X30\000"
1149 /* 182 */ "VSRp30\000"
1150 /* 189 */ "DMRROWp30\000"
1151 /* 199 */ "Fpair30\000"
1152 /* 207 */ "DMRROW40\000"
1153 /* 216 */ "VSX40\000"
1154 /* 222 */ "DMRROW50\000"
1155 /* 231 */ "VSX50\000"
1156 /* 237 */ "DMRROW60\000"
1157 /* 246 */ "VSX60\000"
1158 /* 252 */ "UACC0\000"
1159 /* 258 */ "WACC0\000"
1160 /* 264 */ "VF0\000"
1161 /* 268 */ "VFH0\000"
1162 /* 273 */ "WACC_HI0\000"
1163 /* 282 */ "VSL0\000"
1164 /* 287 */ "CR0\000"
1165 /* 291 */ "DMR0\000"
1166 /* 296 */ "S0\000"
1167 /* 299 */ "V0\000"
1168 /* 302 */ "DMRROW0\000"
1169 /* 310 */ "X0\000"
1170 /* 313 */ "G8p0\000"
1171 /* 318 */ "DMRp0\000"
1172 /* 324 */ "VSRp0\000"
1173 /* 330 */ "DMRROWp0\000"
1174 /* 339 */ "Fpair0\000"
1175 /* 346 */ "VF11\000"
1176 /* 351 */ "VFH11\000"
1177 /* 357 */ "VSL11\000"
1178 /* 363 */ "R11\000"
1179 /* 367 */ "S11\000"
1180 /* 371 */ "V11\000"
1181 /* 375 */ "DMRROW11\000"
1182 /* 384 */ "X11\000"
1183 /* 388 */ "G8p11\000"
1184 /* 394 */ "VSRp11\000"
1185 /* 401 */ "DMRROWp11\000"
1186 /* 411 */ "VF21\000"
1187 /* 416 */ "VFH21\000"
1188 /* 422 */ "VSL21\000"
1189 /* 428 */ "R21\000"
1190 /* 432 */ "S21\000"
1191 /* 436 */ "V21\000"
1192 /* 440 */ "DMRROW21\000"
1193 /* 449 */ "X21\000"
1194 /* 453 */ "VSRp21\000"
1195 /* 460 */ "DMRROWp21\000"
1196 /* 470 */ "VF31\000"
1197 /* 475 */ "VFH31\000"
1198 /* 481 */ "VSL31\000"
1199 /* 487 */ "R31\000"
1200 /* 491 */ "S31\000"
1201 /* 495 */ "V31\000"
1202 /* 499 */ "DMRROW31\000"
1203 /* 508 */ "X31\000"
1204 /* 512 */ "VSRp31\000"
1205 /* 519 */ "DMRROWp31\000"
1206 /* 529 */ "DMRROW41\000"
1207 /* 538 */ "VSX41\000"
1208 /* 544 */ "DMRROW51\000"
1209 /* 553 */ "VSX51\000"
1210 /* 559 */ "DMRROW61\000"
1211 /* 568 */ "VSX61\000"
1212 /* 574 */ "UACC1\000"
1213 /* 580 */ "WACC1\000"
1214 /* 586 */ "VF1\000"
1215 /* 590 */ "VFH1\000"
1216 /* 595 */ "WACC_HI1\000"
1217 /* 604 */ "VSL1\000"
1218 /* 609 */ "CR1\000"
1219 /* 613 */ "DMR1\000"
1220 /* 618 */ "S1\000"
1221 /* 621 */ "V1\000"
1222 /* 624 */ "DMRROW1\000"
1223 /* 632 */ "X1\000"
1224 /* 635 */ "G8p1\000"
1225 /* 640 */ "DMRp1\000"
1226 /* 646 */ "VSRp1\000"
1227 /* 652 */ "DMRROWp1\000"
1228 /* 661 */ "VF12\000"
1229 /* 666 */ "VFH12\000"
1230 /* 672 */ "VSL12\000"
1231 /* 678 */ "R12\000"
1232 /* 682 */ "S12\000"
1233 /* 686 */ "V12\000"
1234 /* 690 */ "DMRROW12\000"
1235 /* 699 */ "X12\000"
1236 /* 703 */ "G8p12\000"
1237 /* 709 */ "VSRp12\000"
1238 /* 716 */ "DMRROWp12\000"
1239 /* 726 */ "Fpair12\000"
1240 /* 734 */ "VF22\000"
1241 /* 739 */ "VFH22\000"
1242 /* 745 */ "VSL22\000"
1243 /* 751 */ "R22\000"
1244 /* 755 */ "S22\000"
1245 /* 759 */ "V22\000"
1246 /* 763 */ "DMRROW22\000"
1247 /* 772 */ "X22\000"
1248 /* 776 */ "VSRp22\000"
1249 /* 783 */ "DMRROWp22\000"
1250 /* 793 */ "Fpair22\000"
1251 /* 801 */ "DMRROW32\000"
1252 /* 810 */ "VSX32\000"
1253 /* 816 */ "DMRROW42\000"
1254 /* 825 */ "VSX42\000"
1255 /* 831 */ "DMRROW52\000"
1256 /* 840 */ "VSX52\000"
1257 /* 846 */ "DMRROW62\000"
1258 /* 855 */ "VSX62\000"
1259 /* 861 */ "UACC2\000"
1260 /* 867 */ "WACC2\000"
1261 /* 873 */ "VF2\000"
1262 /* 877 */ "VFH2\000"
1263 /* 882 */ "WACC_HI2\000"
1264 /* 891 */ "VSL2\000"
1265 /* 896 */ "CR2\000"
1266 /* 900 */ "DMR2\000"
1267 /* 905 */ "S2\000"
1268 /* 908 */ "V2\000"
1269 /* 911 */ "DMRROW2\000"
1270 /* 919 */ "X2\000"
1271 /* 922 */ "G8p2\000"
1272 /* 927 */ "DMRp2\000"
1273 /* 933 */ "VSRp2\000"
1274 /* 939 */ "DMRROWp2\000"
1275 /* 948 */ "Fpair2\000"
1276 /* 955 */ "VF13\000"
1277 /* 960 */ "VFH13\000"
1278 /* 966 */ "VSL13\000"
1279 /* 972 */ "R13\000"
1280 /* 976 */ "S13\000"
1281 /* 980 */ "V13\000"
1282 /* 984 */ "DMRROW13\000"
1283 /* 993 */ "X13\000"
1284 /* 997 */ "G8p13\000"
1285 /* 1003 */ "VSRp13\000"
1286 /* 1010 */ "DMRROWp13\000"
1287 /* 1020 */ "VF23\000"
1288 /* 1025 */ "VFH23\000"
1289 /* 1031 */ "VSL23\000"
1290 /* 1037 */ "R23\000"
1291 /* 1041 */ "S23\000"
1292 /* 1045 */ "V23\000"
1293 /* 1049 */ "DMRROW23\000"
1294 /* 1058 */ "X23\000"
1295 /* 1062 */ "VSRp23\000"
1296 /* 1069 */ "DMRROWp23\000"
1297 /* 1079 */ "DMRROW33\000"
1298 /* 1088 */ "VSX33\000"
1299 /* 1094 */ "DMRROW43\000"
1300 /* 1103 */ "VSX43\000"
1301 /* 1109 */ "DMRROW53\000"
1302 /* 1118 */ "VSX53\000"
1303 /* 1124 */ "DMRROW63\000"
1304 /* 1133 */ "VSX63\000"
1305 /* 1139 */ "UACC3\000"
1306 /* 1145 */ "WACC3\000"
1307 /* 1151 */ "VF3\000"
1308 /* 1155 */ "VFH3\000"
1309 /* 1160 */ "WACC_HI3\000"
1310 /* 1169 */ "VSL3\000"
1311 /* 1174 */ "CR3\000"
1312 /* 1178 */ "DMR3\000"
1313 /* 1183 */ "S3\000"
1314 /* 1186 */ "V3\000"
1315 /* 1189 */ "DMRROW3\000"
1316 /* 1197 */ "X3\000"
1317 /* 1200 */ "G8p3\000"
1318 /* 1205 */ "DMRp3\000"
1319 /* 1211 */ "VSRp3\000"
1320 /* 1217 */ "DMRROWp3\000"
1321 /* 1226 */ "VF14\000"
1322 /* 1231 */ "VFH14\000"
1323 /* 1237 */ "VSL14\000"
1324 /* 1243 */ "R14\000"
1325 /* 1247 */ "S14\000"
1326 /* 1251 */ "V14\000"
1327 /* 1255 */ "DMRROW14\000"
1328 /* 1264 */ "X14\000"
1329 /* 1268 */ "G8p14\000"
1330 /* 1274 */ "VSRp14\000"
1331 /* 1281 */ "DMRROWp14\000"
1332 /* 1291 */ "Fpair14\000"
1333 /* 1299 */ "VF24\000"
1334 /* 1304 */ "VFH24\000"
1335 /* 1310 */ "VSL24\000"
1336 /* 1316 */ "R24\000"
1337 /* 1320 */ "S24\000"
1338 /* 1324 */ "V24\000"
1339 /* 1328 */ "DMRROW24\000"
1340 /* 1337 */ "X24\000"
1341 /* 1341 */ "VSRp24\000"
1342 /* 1348 */ "DMRROWp24\000"
1343 /* 1358 */ "Fpair24\000"
1344 /* 1366 */ "DMRROW34\000"
1345 /* 1375 */ "VSX34\000"
1346 /* 1381 */ "DMRROW44\000"
1347 /* 1390 */ "VSX44\000"
1348 /* 1396 */ "DMRROW54\000"
1349 /* 1405 */ "VSX54\000"
1350 /* 1411 */ "UACC4\000"
1351 /* 1417 */ "WACC4\000"
1352 /* 1423 */ "VF4\000"
1353 /* 1427 */ "VFH4\000"
1354 /* 1432 */ "WACC_HI4\000"
1355 /* 1441 */ "VSL4\000"
1356 /* 1446 */ "CR4\000"
1357 /* 1450 */ "DMR4\000"
1358 /* 1455 */ "S4\000"
1359 /* 1458 */ "V4\000"
1360 /* 1461 */ "DMRROW4\000"
1361 /* 1469 */ "X4\000"
1362 /* 1472 */ "G8p4\000"
1363 /* 1477 */ "VSRp4\000"
1364 /* 1483 */ "DMRROWp4\000"
1365 /* 1492 */ "Fpair4\000"
1366 /* 1499 */ "VF15\000"
1367 /* 1504 */ "VFH15\000"
1368 /* 1510 */ "VSL15\000"
1369 /* 1516 */ "R15\000"
1370 /* 1520 */ "S15\000"
1371 /* 1524 */ "V15\000"
1372 /* 1528 */ "DMRROW15\000"
1373 /* 1537 */ "X15\000"
1374 /* 1541 */ "G8p15\000"
1375 /* 1547 */ "VSRp15\000"
1376 /* 1554 */ "DMRROWp15\000"
1377 /* 1564 */ "VF25\000"
1378 /* 1569 */ "VFH25\000"
1379 /* 1575 */ "VSL25\000"
1380 /* 1581 */ "R25\000"
1381 /* 1585 */ "S25\000"
1382 /* 1589 */ "V25\000"
1383 /* 1593 */ "DMRROW25\000"
1384 /* 1602 */ "X25\000"
1385 /* 1606 */ "VSRp25\000"
1386 /* 1613 */ "DMRROWp25\000"
1387 /* 1623 */ "DMRROW35\000"
1388 /* 1632 */ "VSX35\000"
1389 /* 1638 */ "DMRROW45\000"
1390 /* 1647 */ "VSX45\000"
1391 /* 1653 */ "DMRROW55\000"
1392 /* 1662 */ "VSX55\000"
1393 /* 1668 */ "UACC5\000"
1394 /* 1674 */ "WACC5\000"
1395 /* 1680 */ "VF5\000"
1396 /* 1684 */ "VFH5\000"
1397 /* 1689 */ "WACC_HI5\000"
1398 /* 1698 */ "VSL5\000"
1399 /* 1703 */ "CR5\000"
1400 /* 1707 */ "DMR5\000"
1401 /* 1712 */ "S5\000"
1402 /* 1715 */ "V5\000"
1403 /* 1718 */ "DMRROW5\000"
1404 /* 1726 */ "X5\000"
1405 /* 1729 */ "G8p5\000"
1406 /* 1734 */ "VSRp5\000"
1407 /* 1740 */ "DMRROWp5\000"
1408 /* 1749 */ "VF16\000"
1409 /* 1754 */ "VFH16\000"
1410 /* 1760 */ "VSL16\000"
1411 /* 1766 */ "R16\000"
1412 /* 1770 */ "S16\000"
1413 /* 1774 */ "V16\000"
1414 /* 1778 */ "DMRROW16\000"
1415 /* 1787 */ "X16\000"
1416 /* 1791 */ "VSRp16\000"
1417 /* 1798 */ "DMRROWp16\000"
1418 /* 1808 */ "Fpair16\000"
1419 /* 1816 */ "VF26\000"
1420 /* 1821 */ "VFH26\000"
1421 /* 1827 */ "VSL26\000"
1422 /* 1833 */ "R26\000"
1423 /* 1837 */ "S26\000"
1424 /* 1841 */ "V26\000"
1425 /* 1845 */ "DMRROW26\000"
1426 /* 1854 */ "X26\000"
1427 /* 1858 */ "VSRp26\000"
1428 /* 1865 */ "DMRROWp26\000"
1429 /* 1875 */ "Fpair26\000"
1430 /* 1883 */ "DMRROW36\000"
1431 /* 1892 */ "VSX36\000"
1432 /* 1898 */ "DMRROW46\000"
1433 /* 1907 */ "VSX46\000"
1434 /* 1913 */ "DMRROW56\000"
1435 /* 1922 */ "VSX56\000"
1436 /* 1928 */ "UACC6\000"
1437 /* 1934 */ "WACC6\000"
1438 /* 1940 */ "VF6\000"
1439 /* 1944 */ "VFH6\000"
1440 /* 1949 */ "WACC_HI6\000"
1441 /* 1958 */ "VSL6\000"
1442 /* 1963 */ "CR6\000"
1443 /* 1967 */ "DMR6\000"
1444 /* 1972 */ "S6\000"
1445 /* 1975 */ "V6\000"
1446 /* 1978 */ "DMRROW6\000"
1447 /* 1986 */ "X6\000"
1448 /* 1989 */ "G8p6\000"
1449 /* 1994 */ "VSRp6\000"
1450 /* 2000 */ "DMRROWp6\000"
1451 /* 2009 */ "Fpair6\000"
1452 /* 2016 */ "VF17\000"
1453 /* 2021 */ "VFH17\000"
1454 /* 2027 */ "VSL17\000"
1455 /* 2033 */ "R17\000"
1456 /* 2037 */ "S17\000"
1457 /* 2041 */ "V17\000"
1458 /* 2045 */ "DMRROW17\000"
1459 /* 2054 */ "X17\000"
1460 /* 2058 */ "VSRp17\000"
1461 /* 2065 */ "DMRROWp17\000"
1462 /* 2075 */ "VF27\000"
1463 /* 2080 */ "VFH27\000"
1464 /* 2086 */ "VSL27\000"
1465 /* 2092 */ "R27\000"
1466 /* 2096 */ "S27\000"
1467 /* 2100 */ "V27\000"
1468 /* 2104 */ "DMRROW27\000"
1469 /* 2113 */ "X27\000"
1470 /* 2117 */ "VSRp27\000"
1471 /* 2124 */ "DMRROWp27\000"
1472 /* 2134 */ "DMRROW37\000"
1473 /* 2143 */ "VSX37\000"
1474 /* 2149 */ "DMRROW47\000"
1475 /* 2158 */ "VSX47\000"
1476 /* 2164 */ "DMRROW57\000"
1477 /* 2173 */ "VSX57\000"
1478 /* 2179 */ "UACC7\000"
1479 /* 2185 */ "WACC7\000"
1480 /* 2191 */ "VF7\000"
1481 /* 2195 */ "VFH7\000"
1482 /* 2200 */ "WACC_HI7\000"
1483 /* 2209 */ "VSL7\000"
1484 /* 2214 */ "CR7\000"
1485 /* 2218 */ "DMR7\000"
1486 /* 2223 */ "S7\000"
1487 /* 2226 */ "V7\000"
1488 /* 2229 */ "DMRROW7\000"
1489 /* 2237 */ "X7\000"
1490 /* 2240 */ "G8p7\000"
1491 /* 2245 */ "VSRp7\000"
1492 /* 2251 */ "DMRROWp7\000"
1493 /* 2260 */ "VF18\000"
1494 /* 2265 */ "VFH18\000"
1495 /* 2271 */ "VSL18\000"
1496 /* 2277 */ "R18\000"
1497 /* 2281 */ "S18\000"
1498 /* 2285 */ "V18\000"
1499 /* 2289 */ "DMRROW18\000"
1500 /* 2298 */ "X18\000"
1501 /* 2302 */ "VSRp18\000"
1502 /* 2309 */ "DMRROWp18\000"
1503 /* 2319 */ "Fpair18\000"
1504 /* 2327 */ "VF28\000"
1505 /* 2332 */ "VFH28\000"
1506 /* 2338 */ "VSL28\000"
1507 /* 2344 */ "R28\000"
1508 /* 2348 */ "S28\000"
1509 /* 2352 */ "V28\000"
1510 /* 2356 */ "DMRROW28\000"
1511 /* 2365 */ "X28\000"
1512 /* 2369 */ "VSRp28\000"
1513 /* 2376 */ "DMRROWp28\000"
1514 /* 2386 */ "Fpair28\000"
1515 /* 2394 */ "DMRROW38\000"
1516 /* 2403 */ "VSX38\000"
1517 /* 2409 */ "DMRROW48\000"
1518 /* 2418 */ "VSX48\000"
1519 /* 2424 */ "DMRROW58\000"
1520 /* 2433 */ "VSX58\000"
1521 /* 2439 */ "VF8\000"
1522 /* 2443 */ "VFH8\000"
1523 /* 2448 */ "VSL8\000"
1524 /* 2453 */ "ZERO8\000"
1525 /* 2459 */ "BP8\000"
1526 /* 2463 */ "FP8\000"
1527 /* 2467 */ "LR8\000"
1528 /* 2471 */ "CTR8\000"
1529 /* 2476 */ "S8\000"
1530 /* 2479 */ "V8\000"
1531 /* 2482 */ "DMRROW8\000"
1532 /* 2490 */ "X8\000"
1533 /* 2493 */ "G8p8\000"
1534 /* 2498 */ "VSRp8\000"
1535 /* 2504 */ "DMRROWp8\000"
1536 /* 2513 */ "Fpair8\000"
1537 /* 2520 */ "VF19\000"
1538 /* 2525 */ "VFH19\000"
1539 /* 2531 */ "VSL19\000"
1540 /* 2537 */ "R19\000"
1541 /* 2541 */ "S19\000"
1542 /* 2545 */ "V19\000"
1543 /* 2549 */ "DMRROW19\000"
1544 /* 2558 */ "X19\000"
1545 /* 2562 */ "VSRp19\000"
1546 /* 2569 */ "DMRROWp19\000"
1547 /* 2579 */ "VF29\000"
1548 /* 2584 */ "VFH29\000"
1549 /* 2590 */ "VSL29\000"
1550 /* 2596 */ "R29\000"
1551 /* 2600 */ "S29\000"
1552 /* 2604 */ "V29\000"
1553 /* 2608 */ "DMRROW29\000"
1554 /* 2617 */ "X29\000"
1555 /* 2621 */ "VSRp29\000"
1556 /* 2628 */ "DMRROWp29\000"
1557 /* 2638 */ "DMRROW39\000"
1558 /* 2647 */ "VSX39\000"
1559 /* 2653 */ "DMRROW49\000"
1560 /* 2662 */ "VSX49\000"
1561 /* 2668 */ "DMRROW59\000"
1562 /* 2677 */ "VSX59\000"
1563 /* 2683 */ "VF9\000"
1564 /* 2687 */ "VFH9\000"
1565 /* 2692 */ "VSL9\000"
1566 /* 2697 */ "R9\000"
1567 /* 2700 */ "S9\000"
1568 /* 2703 */ "V9\000"
1569 /* 2706 */ "DMRROW9\000"
1570 /* 2714 */ "X9\000"
1571 /* 2717 */ "G8p9\000"
1572 /* 2722 */ "VSRp9\000"
1573 /* 2728 */ "DMRROWp9\000"
1574 /* 2737 */ "VRSAVE\000"
1575 /* 2744 */ "RM\000"
1576 /* 2747 */ "CR0UN\000"
1577 /* 2753 */ "CR1UN\000"
1578 /* 2759 */ "CR2UN\000"
1579 /* 2765 */ "CR3UN\000"
1580 /* 2771 */ "CR4UN\000"
1581 /* 2777 */ "CR5UN\000"
1582 /* 2783 */ "CR6UN\000"
1583 /* 2789 */ "CR7UN\000"
1584 /* 2795 */ "ZERO\000"
1585 /* 2800 */ "BP\000"
1586 /* 2803 */ "FP\000"
1587 /* 2806 */ "CR0EQ\000"
1588 /* 2812 */ "CR1EQ\000"
1589 /* 2818 */ "CR2EQ\000"
1590 /* 2824 */ "CR3EQ\000"
1591 /* 2830 */ "CR4EQ\000"
1592 /* 2836 */ "CR5EQ\000"
1593 /* 2842 */ "CR6EQ\000"
1594 /* 2848 */ "CR7EQ\000"
1595 /* 2854 */ "SPEFSCR\000"
1596 /* 2862 */ "XER\000"
1597 /* 2866 */ "LR\000"
1598 /* 2869 */ "CTR\000"
1599 /* 2873 */ "CR0GT\000"
1600 /* 2879 */ "CR1GT\000"
1601 /* 2885 */ "CR2GT\000"
1602 /* 2891 */ "CR3GT\000"
1603 /* 2897 */ "CR4GT\000"
1604 /* 2903 */ "CR5GT\000"
1605 /* 2909 */ "CR6GT\000"
1606 /* 2915 */ "CR7GT\000"
1607 /* 2921 */ "CR0LT\000"
1608 /* 2927 */ "CR1LT\000"
1609 /* 2933 */ "CR2LT\000"
1610 /* 2939 */ "CR3LT\000"
1611 /* 2945 */ "CR4LT\000"
1612 /* 2951 */ "CR5LT\000"
1613 /* 2957 */ "CR6LT\000"
1614 /* 2963 */ "CR7LT\000"
1615 /* 2969 */ "CARRY\000"
1616};
1617#ifdef __GNUC__
1618#pragma GCC diagnostic pop
1619#endif
1620
1621extern const MCRegisterDesc PPCRegDesc[] = { // Descriptors
1622 { 4, 0, 0, 0, 0, 0, 0, 0 },
1623 { 2800, 1, 408, 1, 4096, 55, 0, 0 },
1624 { 2969, 1, 1, 1, 401409, 54, 0, 0 },
1625 { 2869, 1, 1, 1, 401411, 54, 0, 0 },
1626 { 2803, 1, 1465, 1, 4101, 55, 0, 0 },
1627 { 2866, 1, 1, 1, 401414, 54, 0, 0 },
1628 { 2744, 1, 1, 1, 4104, 55, 0, 0 },
1629 { 2854, 1, 1, 1, 4105, 55, 0, 0 },
1630 { 2737, 1, 1, 1, 4106, 55, 0, 0 },
1631 { 2862, 1, 1, 1, 1662978, 54, 0, 0 },
1632 { 2795, 1, 1594, 1, 4108, 55, 1, 0 },
1633 { 253, 437, 1, 19, 1622029, 16, 0, 0 },
1634 { 575, 474, 1, 19, 1622037, 16, 0, 0 },
1635 { 862, 511, 1, 19, 1622045, 16, 0, 0 },
1636 { 1140, 548, 1, 19, 1622053, 16, 0, 0 },
1637 { 1412, 585, 1, 19, 1622061, 16, 0, 0 },
1638 { 1669, 622, 1, 19, 1622069, 16, 0, 0 },
1639 { 1929, 659, 1, 19, 1622077, 16, 0, 0 },
1640 { 2180, 696, 1, 19, 1622085, 16, 0, 0 },
1641 { 2459, 95, 1, 0, 4096, 1, 0, 0 },
1642 { 287, 410, 1, 9, 1638477, 8, 0, 0 },
1643 { 609, 410, 1, 9, 1638481, 8, 0, 0 },
1644 { 896, 410, 1, 9, 1638485, 8, 0, 0 },
1645 { 1174, 410, 1, 9, 1638489, 8, 0, 0 },
1646 { 1446, 410, 1, 9, 1638493, 8, 0, 0 },
1647 { 1703, 410, 1, 9, 1638497, 8, 0, 0 },
1648 { 1963, 410, 1, 9, 1638501, 8, 0, 0 },
1649 { 2214, 410, 1, 9, 1638505, 8, 0, 0 },
1650 { 2471, 1, 1, 1, 4984836, 54, 0, 0 },
1651 { 291, 113, 1176, 39, 1622126, 28, 0, 0 },
1652 { 613, 157, 1096, 39, 1622134, 28, 0, 0 },
1653 { 900, 185, 1096, 39, 1622142, 28, 0, 0 },
1654 { 1178, 229, 1016, 39, 1622150, 28, 0, 0 },
1655 { 1450, 257, 1016, 39, 1622158, 28, 0, 0 },
1656 { 1707, 301, 936, 39, 1622166, 28, 0, 0 },
1657 { 1967, 329, 936, 39, 1622174, 28, 0, 0 },
1658 { 2218, 373, 896, 39, 1622182, 28, 0, 0 },
1659 { 302, 1, 1208, 1, 4206, 55, 0, 0 },
1660 { 624, 1, 1203, 1, 4207, 55, 0, 0 },
1661 { 911, 1, 1198, 1, 4208, 55, 0, 0 },
1662 { 1189, 1, 1193, 1, 4209, 55, 0, 0 },
1663 { 1461, 1, 1188, 1, 4210, 55, 0, 0 },
1664 { 1718, 1, 1183, 1, 4211, 55, 0, 0 },
1665 { 1978, 1, 1178, 1, 4212, 55, 0, 0 },
1666 { 2229, 1, 1173, 1, 4213, 55, 0, 0 },
1667 { 2482, 1, 1168, 1, 4214, 55, 0, 0 },
1668 { 2706, 1, 1163, 1, 4215, 55, 0, 0 },
1669 { 29, 1, 1158, 1, 4216, 55, 0, 0 },
1670 { 375, 1, 1153, 1, 4217, 55, 0, 0 },
1671 { 690, 1, 1128, 1, 4218, 55, 0, 0 },
1672 { 984, 1, 1123, 1, 4219, 55, 0, 0 },
1673 { 1255, 1, 1118, 1, 4220, 55, 0, 0 },
1674 { 1528, 1, 1113, 1, 4221, 55, 0, 0 },
1675 { 1778, 1, 1148, 1, 4222, 55, 0, 0 },
1676 { 2045, 1, 1143, 1, 4223, 55, 0, 0 },
1677 { 2289, 1, 1138, 1, 4224, 55, 0, 0 },
1678 { 2549, 1, 1133, 1, 4225, 55, 0, 0 },
1679 { 102, 1, 1108, 1, 4226, 55, 0, 0 },
1680 { 440, 1, 1103, 1, 4227, 55, 0, 0 },
1681 { 763, 1, 1098, 1, 4228, 55, 0, 0 },
1682 { 1049, 1, 1093, 1, 4229, 55, 0, 0 },
1683 { 1328, 1, 1088, 1, 4230, 55, 0, 0 },
1684 { 1593, 1, 1083, 1, 4231, 55, 0, 0 },
1685 { 1845, 1, 1078, 1, 4232, 55, 0, 0 },
1686 { 2104, 1, 1073, 1, 4233, 55, 0, 0 },
1687 { 2356, 1, 1048, 1, 4234, 55, 0, 0 },
1688 { 2608, 1, 1043, 1, 4235, 55, 0, 0 },
1689 { 169, 1, 1038, 1, 4236, 55, 0, 0 },
1690 { 499, 1, 1033, 1, 4237, 55, 0, 0 },
1691 { 801, 1, 1068, 1, 4238, 55, 0, 0 },
1692 { 1079, 1, 1063, 1, 4239, 55, 0, 0 },
1693 { 1366, 1, 1058, 1, 4240, 55, 0, 0 },
1694 { 1623, 1, 1053, 1, 4241, 55, 0, 0 },
1695 { 1883, 1, 1028, 1, 4242, 55, 0, 0 },
1696 { 2134, 1, 1023, 1, 4243, 55, 0, 0 },
1697 { 2394, 1, 1018, 1, 4244, 55, 0, 0 },
1698 { 2638, 1, 1013, 1, 4245, 55, 0, 0 },
1699 { 207, 1, 1008, 1, 4246, 55, 0, 0 },
1700 { 529, 1, 1003, 1, 4247, 55, 0, 0 },
1701 { 816, 1, 998, 1, 4248, 55, 0, 0 },
1702 { 1094, 1, 993, 1, 4249, 55, 0, 0 },
1703 { 1381, 1, 968, 1, 4250, 55, 0, 0 },
1704 { 1638, 1, 963, 1, 4251, 55, 0, 0 },
1705 { 1898, 1, 958, 1, 4252, 55, 0, 0 },
1706 { 2149, 1, 953, 1, 4253, 55, 0, 0 },
1707 { 2409, 1, 988, 1, 4254, 55, 0, 0 },
1708 { 2653, 1, 983, 1, 4255, 55, 0, 0 },
1709 { 222, 1, 978, 1, 4256, 55, 0, 0 },
1710 { 544, 1, 973, 1, 4257, 55, 0, 0 },
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1725 { 939, 110, 1184, 5, 401522, 4, 0, 0 },
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1745 { 783, 282, 964, 5, 401562, 4, 0, 0 },
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1747 { 1348, 316, 984, 5, 401566, 4, 0, 0 },
1748 { 1613, 323, 974, 5, 401568, 4, 0, 0 },
1749 { 1865, 326, 944, 5, 401570, 4, 0, 0 },
1750 { 2124, 341, 934, 5, 401572, 4, 0, 0 },
1751 { 2376, 344, 924, 5, 401574, 4, 0, 0 },
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1753 { 189, 354, 904, 5, 401578, 4, 0, 0 },
1754 { 519, 385, 894, 5, 401580, 4, 0, 0 },
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1756 { 640, 213, 1, 53, 1589374, 36, 0, 0 },
1757 { 927, 285, 1, 53, 1589390, 36, 0, 0 },
1758 { 1205, 357, 1, 53, 1589406, 36, 0, 0 },
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1760 { 587, 1, 1351, 1, 4111, 55, 0, 0 },
1761 { 874, 1, 1345, 1, 4113, 55, 0, 0 },
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1764 { 1681, 1, 1333, 1, 4119, 55, 0, 0 },
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1767 { 2440, 1, 1321, 1, 4125, 55, 0, 0 },
1768 { 2684, 1, 1315, 1, 4127, 55, 0, 0 },
1769 { 1, 1, 1309, 1, 4129, 55, 0, 0 },
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1771 { 662, 1, 1303, 1, 4133, 55, 0, 0 },
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1785 { 1817, 1, 1237, 1, 4161, 55, 0, 0 },
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1790 { 471, 1, 1213, 1, 4171, 55, 0, 0 },
1791 { 269, 1, 1589, 1, 4110, 55, 0, 1 },
1792 { 591, 1, 1584, 1, 4112, 55, 0, 1 },
1793 { 878, 1, 1579, 1, 4114, 55, 0, 1 },
1794 { 1156, 1, 1574, 1, 4116, 55, 0, 1 },
1795 { 1428, 1, 1574, 1, 4118, 55, 0, 1 },
1796 { 1685, 1, 1569, 1, 4120, 55, 0, 1 },
1797 { 1945, 1, 1564, 1, 4122, 55, 0, 1 },
1798 { 2196, 1, 1559, 1, 4124, 55, 0, 1 },
1799 { 2444, 1, 1559, 1, 4126, 55, 0, 1 },
1800 { 2688, 1, 1554, 1, 4128, 55, 0, 1 },
1801 { 6, 1, 1549, 1, 4130, 55, 0, 1 },
1802 { 352, 1, 1544, 1, 4132, 55, 0, 1 },
1803 { 667, 1, 1544, 1, 4134, 55, 0, 1 },
1804 { 961, 1, 1539, 1, 4136, 55, 0, 1 },
1805 { 1232, 1, 1534, 1, 4138, 55, 0, 1 },
1806 { 1505, 1, 1529, 1, 4140, 55, 0, 1 },
1807 { 1755, 1, 1529, 1, 4142, 55, 0, 1 },
1808 { 2022, 1, 1524, 1, 4144, 55, 0, 1 },
1809 { 2266, 1, 1519, 1, 4146, 55, 0, 1 },
1810 { 2526, 1, 1514, 1, 4148, 55, 0, 1 },
1811 { 79, 1, 1514, 1, 4150, 55, 0, 1 },
1812 { 417, 1, 1509, 1, 4152, 55, 0, 1 },
1813 { 740, 1, 1504, 1, 4154, 55, 0, 1 },
1814 { 1026, 1, 1499, 1, 4156, 55, 0, 1 },
1815 { 1305, 1, 1499, 1, 4158, 55, 0, 1 },
1816 { 1570, 1, 1494, 1, 4160, 55, 0, 1 },
1817 { 1822, 1, 1489, 1, 4162, 55, 0, 1 },
1818 { 2081, 1, 1484, 1, 4164, 55, 0, 1 },
1819 { 2333, 1, 1484, 1, 4166, 55, 0, 1 },
1820 { 2585, 1, 1479, 1, 4168, 55, 0, 1 },
1821 { 146, 1, 1474, 1, 4170, 55, 0, 1 },
1822 { 476, 1, 1469, 1, 4172, 55, 0, 1 },
1823 { 2463, 90, 1, 0, 4101, 1, 0, 0 },
1824 { 339, 97, 1, 7, 1654797, 6, 0, 0 },
1825 { 948, 100, 1, 7, 1654801, 6, 0, 0 },
1826 { 1492, 107, 1, 7, 1654805, 6, 0, 0 },
1827 { 2009, 110, 1, 7, 1654809, 6, 0, 0 },
1828 { 2513, 125, 1, 7, 1654813, 6, 0, 0 },
1829 { 65, 128, 1, 7, 1654817, 6, 0, 0 },
1830 { 726, 135, 1, 7, 1654821, 6, 0, 0 },
1831 { 1291, 138, 1, 7, 1654825, 6, 0, 0 },
1832 { 1808, 169, 1, 7, 1654829, 6, 0, 0 },
1833 { 2319, 172, 1, 7, 1654833, 6, 0, 0 },
1834 { 132, 179, 1, 7, 1654837, 6, 0, 0 },
1835 { 793, 182, 1, 7, 1654841, 6, 0, 0 },
1836 { 1358, 197, 1, 7, 1654845, 6, 0, 0 },
1837 { 1875, 200, 1, 7, 1654849, 6, 0, 0 },
1838 { 2386, 207, 1, 7, 1654853, 6, 0, 0 },
1839 { 199, 210, 1, 7, 1654857, 6, 0, 0 },
1840 { 270, 1, 891, 1, 4270, 55, 0, 1 },
1841 { 592, 1, 891, 1, 4271, 55, 0, 1 },
1842 { 879, 1, 891, 1, 4272, 55, 0, 1 },
1843 { 1157, 1, 891, 1, 4273, 55, 0, 1 },
1844 { 1429, 1, 891, 1, 4274, 55, 0, 1 },
1845 { 1686, 1, 891, 1, 4275, 55, 0, 1 },
1846 { 1946, 1, 891, 1, 4276, 55, 0, 1 },
1847 { 2197, 1, 891, 1, 4277, 55, 0, 1 },
1848 { 2445, 1, 891, 1, 4278, 55, 0, 1 },
1849 { 2689, 1, 891, 1, 4279, 55, 0, 1 },
1850 { 7, 1, 891, 1, 4280, 55, 0, 1 },
1851 { 353, 1, 891, 1, 4281, 55, 0, 1 },
1852 { 668, 1, 891, 1, 4282, 55, 0, 1 },
1853 { 962, 1, 891, 1, 4283, 55, 0, 1 },
1854 { 1233, 1, 891, 1, 4284, 55, 0, 1 },
1855 { 1506, 1, 891, 1, 4285, 55, 0, 1 },
1856 { 1756, 1, 891, 1, 4286, 55, 0, 1 },
1857 { 2023, 1, 891, 1, 4287, 55, 0, 1 },
1858 { 2267, 1, 891, 1, 4288, 55, 0, 1 },
1859 { 2527, 1, 891, 1, 4289, 55, 0, 1 },
1860 { 80, 1, 891, 1, 4290, 55, 0, 1 },
1861 { 418, 1, 891, 1, 4291, 55, 0, 1 },
1862 { 741, 1, 891, 1, 4292, 55, 0, 1 },
1863 { 1027, 1, 891, 1, 4293, 55, 0, 1 },
1864 { 1306, 1, 891, 1, 4294, 55, 0, 1 },
1865 { 1571, 1, 891, 1, 4295, 55, 0, 1 },
1866 { 1823, 1, 891, 1, 4296, 55, 0, 1 },
1867 { 2082, 1, 891, 1, 4297, 55, 0, 1 },
1868 { 2334, 1, 891, 1, 4298, 55, 0, 1 },
1869 { 2586, 1, 891, 1, 4299, 55, 0, 1 },
1870 { 147, 1, 891, 1, 4300, 55, 0, 1 },
1871 { 477, 1, 891, 1, 4301, 55, 0, 1 },
1872 { 2467, 1, 1, 1, 6008839, 54, 0, 0 },
1873 { 288, 1, 889, 1, 4303, 55, 0, 0 },
1874 { 610, 1, 885, 1, 4304, 55, 0, 0 },
1875 { 897, 1, 885, 1, 4305, 55, 0, 0 },
1876 { 1175, 1, 881, 1, 4306, 55, 0, 0 },
1877 { 1447, 1, 881, 1, 4307, 55, 0, 0 },
1878 { 1704, 1, 877, 1, 4308, 55, 0, 0 },
1879 { 1964, 1, 877, 1, 4309, 55, 0, 0 },
1880 { 2215, 1, 873, 1, 4310, 55, 0, 0 },
1881 { 2468, 1, 873, 1, 4311, 55, 0, 0 },
1882 { 2697, 1, 869, 1, 4312, 55, 0, 0 },
1883 { 17, 1, 869, 1, 4313, 55, 0, 0 },
1884 { 363, 1, 865, 1, 4314, 55, 0, 0 },
1885 { 678, 1, 865, 1, 4315, 55, 0, 0 },
1886 { 972, 1, 861, 1, 4316, 55, 0, 0 },
1887 { 1243, 1, 861, 1, 4317, 55, 0, 0 },
1888 { 1516, 1, 857, 1, 4318, 55, 0, 0 },
1889 { 1766, 1, 857, 1, 4319, 55, 0, 0 },
1890 { 2033, 1, 853, 1, 4320, 55, 0, 0 },
1891 { 2277, 1, 853, 1, 4321, 55, 0, 0 },
1892 { 2537, 1, 849, 1, 4322, 55, 0, 0 },
1893 { 90, 1, 849, 1, 4323, 55, 0, 0 },
1894 { 428, 1, 845, 1, 4324, 55, 0, 0 },
1895 { 751, 1, 845, 1, 4325, 55, 0, 0 },
1896 { 1037, 1, 841, 1, 4326, 55, 0, 0 },
1897 { 1316, 1, 841, 1, 4327, 55, 0, 0 },
1898 { 1581, 1, 837, 1, 4328, 55, 0, 0 },
1899 { 1833, 1, 837, 1, 4329, 55, 0, 0 },
1900 { 2092, 1, 833, 1, 4330, 55, 0, 0 },
1901 { 2344, 1, 833, 1, 4331, 55, 0, 0 },
1902 { 2596, 1, 829, 1, 4332, 55, 0, 0 },
1903 { 157, 1, 829, 1, 4333, 55, 0, 0 },
1904 { 487, 1, 825, 1, 4334, 55, 0, 0 },
1905 { 296, 92, 1, 1, 3371182, 0, 0, 0 },
1906 { 618, 92, 1, 1, 3371183, 0, 0, 0 },
1907 { 905, 92, 1, 1, 3371184, 0, 0, 0 },
1908 { 1183, 92, 1, 1, 3371185, 0, 0, 0 },
1909 { 1455, 92, 1, 1, 3371186, 0, 0, 0 },
1910 { 1712, 92, 1, 1, 3371187, 0, 0, 0 },
1911 { 1972, 92, 1, 1, 3371188, 0, 0, 0 },
1912 { 2223, 92, 1, 1, 3371189, 0, 0, 0 },
1913 { 2476, 92, 1, 1, 3371190, 0, 0, 0 },
1914 { 2700, 92, 1, 1, 3371191, 0, 0, 0 },
1915 { 21, 92, 1, 1, 3371192, 0, 0, 0 },
1916 { 367, 92, 1, 1, 3371193, 0, 0, 0 },
1917 { 682, 92, 1, 1, 3371194, 0, 0, 0 },
1918 { 976, 92, 1, 1, 3371195, 0, 0, 0 },
1919 { 1247, 92, 1, 1, 3371196, 0, 0, 0 },
1920 { 1520, 92, 1, 1, 3371197, 0, 0, 0 },
1921 { 1770, 92, 1, 1, 3371198, 0, 0, 0 },
1922 { 2037, 92, 1, 1, 3371199, 0, 0, 0 },
1923 { 2281, 92, 1, 1, 3371200, 0, 0, 0 },
1924 { 2541, 92, 1, 1, 3371201, 0, 0, 0 },
1925 { 94, 92, 1, 1, 3371202, 0, 0, 0 },
1926 { 432, 92, 1, 1, 3371203, 0, 0, 0 },
1927 { 755, 92, 1, 1, 3371204, 0, 0, 0 },
1928 { 1041, 92, 1, 1, 3371205, 0, 0, 0 },
1929 { 1320, 92, 1, 1, 3371206, 0, 0, 0 },
1930 { 1585, 92, 1, 1, 3371207, 0, 0, 0 },
1931 { 1837, 92, 1, 1, 3371208, 0, 0, 0 },
1932 { 2096, 92, 1, 1, 3371209, 0, 0, 0 },
1933 { 2348, 92, 1, 1, 3371210, 0, 0, 0 },
1934 { 2600, 92, 1, 1, 3371211, 0, 0, 0 },
1935 { 161, 92, 1, 1, 3371212, 0, 0, 0 },
1936 { 491, 92, 1, 1, 3371213, 0, 0, 0 },
1937 { 252, 422, 1, 19, 1622029, 16, 0, 0 },
1938 { 574, 459, 1, 19, 1622037, 16, 0, 0 },
1939 { 861, 496, 1, 19, 1622045, 16, 0, 0 },
1940 { 1139, 533, 1, 19, 1622053, 16, 0, 0 },
1941 { 1411, 570, 1, 19, 1622061, 16, 0, 0 },
1942 { 1668, 607, 1, 19, 1622069, 16, 0, 0 },
1943 { 1928, 644, 1, 19, 1622077, 16, 0, 0 },
1944 { 2179, 681, 1, 19, 1622085, 16, 0, 0 },
1945 { 299, 715, 1460, 3, 401647, 2, 0, 0 },
1946 { 621, 715, 1454, 3, 401649, 2, 0, 0 },
1947 { 908, 715, 1454, 3, 401651, 2, 0, 0 },
1948 { 1186, 715, 1448, 3, 401653, 2, 0, 0 },
1949 { 1458, 715, 1448, 3, 401655, 2, 0, 0 },
1950 { 1715, 715, 1442, 3, 401657, 2, 0, 0 },
1951 { 1975, 715, 1442, 3, 401659, 2, 0, 0 },
1952 { 2226, 715, 1436, 3, 401661, 2, 0, 0 },
1953 { 2479, 715, 1436, 3, 401663, 2, 0, 0 },
1954 { 2703, 715, 1430, 3, 401665, 2, 0, 0 },
1955 { 25, 715, 1430, 3, 401667, 2, 0, 0 },
1956 { 371, 715, 1424, 3, 401669, 2, 0, 0 },
1957 { 686, 715, 1424, 3, 401671, 2, 0, 0 },
1958 { 980, 715, 1418, 3, 401673, 2, 0, 0 },
1959 { 1251, 715, 1418, 3, 401675, 2, 0, 0 },
1960 { 1524, 715, 1412, 3, 401677, 2, 0, 0 },
1961 { 1774, 715, 1412, 3, 401679, 2, 0, 0 },
1962 { 2041, 715, 1406, 3, 401681, 2, 0, 0 },
1963 { 2285, 715, 1406, 3, 401683, 2, 0, 0 },
1964 { 2545, 715, 1400, 3, 401685, 2, 0, 0 },
1965 { 98, 715, 1400, 3, 401687, 2, 0, 0 },
1966 { 436, 715, 1394, 3, 401689, 2, 0, 0 },
1967 { 759, 715, 1394, 3, 401691, 2, 0, 0 },
1968 { 1045, 715, 1388, 3, 401693, 2, 0, 0 },
1969 { 1324, 715, 1388, 3, 401695, 2, 0, 0 },
1970 { 1589, 715, 1382, 3, 401697, 2, 0, 0 },
1971 { 1841, 715, 1382, 3, 401699, 2, 0, 0 },
1972 { 2100, 715, 1376, 3, 401701, 2, 0, 0 },
1973 { 2352, 715, 1376, 3, 401703, 2, 0, 0 },
1974 { 2604, 715, 1370, 3, 401705, 2, 0, 0 },
1975 { 165, 715, 1370, 3, 401707, 2, 0, 0 },
1976 { 495, 715, 1364, 3, 401709, 2, 0, 0 },
1977 { 264, 1, 1462, 1, 4335, 55, 0, 0 },
1978 { 586, 1, 1456, 1, 4337, 55, 0, 0 },
1979 { 873, 1, 1456, 1, 4339, 55, 0, 0 },
1980 { 1151, 1, 1450, 1, 4341, 55, 0, 0 },
1981 { 1423, 1, 1450, 1, 4343, 55, 0, 0 },
1982 { 1680, 1, 1444, 1, 4345, 55, 0, 0 },
1983 { 1940, 1, 1444, 1, 4347, 55, 0, 0 },
1984 { 2191, 1, 1438, 1, 4349, 55, 0, 0 },
1985 { 2439, 1, 1438, 1, 4351, 55, 0, 0 },
1986 { 2683, 1, 1432, 1, 4353, 55, 0, 0 },
1987 { 0, 1, 1432, 1, 4355, 55, 0, 0 },
1988 { 346, 1, 1426, 1, 4357, 55, 0, 0 },
1989 { 661, 1, 1426, 1, 4359, 55, 0, 0 },
1990 { 955, 1, 1420, 1, 4361, 55, 0, 0 },
1991 { 1226, 1, 1420, 1, 4363, 55, 0, 0 },
1992 { 1499, 1, 1414, 1, 4365, 55, 0, 0 },
1993 { 1749, 1, 1414, 1, 4367, 55, 0, 0 },
1994 { 2016, 1, 1408, 1, 4369, 55, 0, 0 },
1995 { 2260, 1, 1408, 1, 4371, 55, 0, 0 },
1996 { 2520, 1, 1402, 1, 4373, 55, 0, 0 },
1997 { 73, 1, 1402, 1, 4375, 55, 0, 0 },
1998 { 411, 1, 1396, 1, 4377, 55, 0, 0 },
1999 { 734, 1, 1396, 1, 4379, 55, 0, 0 },
2000 { 1020, 1, 1390, 1, 4381, 55, 0, 0 },
2001 { 1299, 1, 1390, 1, 4383, 55, 0, 0 },
2002 { 1564, 1, 1384, 1, 4385, 55, 0, 0 },
2003 { 1816, 1, 1384, 1, 4387, 55, 0, 0 },
2004 { 2075, 1, 1378, 1, 4389, 55, 0, 0 },
2005 { 2327, 1, 1378, 1, 4391, 55, 0, 0 },
2006 { 2579, 1, 1372, 1, 4393, 55, 0, 0 },
2007 { 140, 1, 1372, 1, 4395, 55, 0, 0 },
2008 { 470, 1, 1366, 1, 4397, 55, 0, 0 },
2009 { 268, 1, 1459, 1, 4336, 55, 0, 1 },
2010 { 590, 1, 1453, 1, 4338, 55, 0, 1 },
2011 { 877, 1, 1453, 1, 4340, 55, 0, 1 },
2012 { 1155, 1, 1447, 1, 4342, 55, 0, 1 },
2013 { 1427, 1, 1447, 1, 4344, 55, 0, 1 },
2014 { 1684, 1, 1441, 1, 4346, 55, 0, 1 },
2015 { 1944, 1, 1441, 1, 4348, 55, 0, 1 },
2016 { 2195, 1, 1435, 1, 4350, 55, 0, 1 },
2017 { 2443, 1, 1435, 1, 4352, 55, 0, 1 },
2018 { 2687, 1, 1429, 1, 4354, 55, 0, 1 },
2019 { 5, 1, 1429, 1, 4356, 55, 0, 1 },
2020 { 351, 1, 1423, 1, 4358, 55, 0, 1 },
2021 { 666, 1, 1423, 1, 4360, 55, 0, 1 },
2022 { 960, 1, 1417, 1, 4362, 55, 0, 1 },
2023 { 1231, 1, 1417, 1, 4364, 55, 0, 1 },
2024 { 1504, 1, 1411, 1, 4366, 55, 0, 1 },
2025 { 1754, 1, 1411, 1, 4368, 55, 0, 1 },
2026 { 2021, 1, 1405, 1, 4370, 55, 0, 1 },
2027 { 2265, 1, 1405, 1, 4372, 55, 0, 1 },
2028 { 2525, 1, 1399, 1, 4374, 55, 0, 1 },
2029 { 78, 1, 1399, 1, 4376, 55, 0, 1 },
2030 { 416, 1, 1393, 1, 4378, 55, 0, 1 },
2031 { 739, 1, 1393, 1, 4380, 55, 0, 1 },
2032 { 1025, 1, 1387, 1, 4382, 55, 0, 1 },
2033 { 1304, 1, 1387, 1, 4384, 55, 0, 1 },
2034 { 1569, 1, 1381, 1, 4386, 55, 0, 1 },
2035 { 1821, 1, 1381, 1, 4388, 55, 0, 1 },
2036 { 2080, 1, 1375, 1, 4390, 55, 0, 1 },
2037 { 2332, 1, 1375, 1, 4392, 55, 0, 1 },
2038 { 2584, 1, 1369, 1, 4394, 55, 0, 1 },
2039 { 145, 1, 1369, 1, 4396, 55, 0, 1 },
2040 { 475, 1, 1363, 1, 4398, 55, 0, 1 },
2041 { 282, 419, 1590, 3, 401421, 2, 0, 0 },
2042 { 604, 419, 1585, 3, 401423, 2, 0, 0 },
2043 { 891, 419, 1580, 3, 401425, 2, 0, 0 },
2044 { 1169, 419, 1575, 3, 401427, 2, 0, 0 },
2045 { 1441, 419, 1575, 3, 401429, 2, 0, 0 },
2046 { 1698, 419, 1570, 3, 401431, 2, 0, 0 },
2047 { 1958, 419, 1565, 3, 401433, 2, 0, 0 },
2048 { 2209, 419, 1560, 3, 401435, 2, 0, 0 },
2049 { 2448, 419, 1560, 3, 401437, 2, 0, 0 },
2050 { 2692, 419, 1555, 3, 401439, 2, 0, 0 },
2051 { 11, 419, 1550, 3, 401441, 2, 0, 0 },
2052 { 357, 419, 1545, 3, 401443, 2, 0, 0 },
2053 { 672, 419, 1545, 3, 401445, 2, 0, 0 },
2054 { 966, 419, 1540, 3, 401447, 2, 0, 0 },
2055 { 1237, 419, 1535, 3, 401449, 2, 0, 0 },
2056 { 1510, 419, 1530, 3, 401451, 2, 0, 0 },
2057 { 1760, 419, 1530, 3, 401453, 2, 0, 0 },
2058 { 2027, 419, 1525, 3, 401455, 2, 0, 0 },
2059 { 2271, 419, 1520, 3, 401457, 2, 0, 0 },
2060 { 2531, 419, 1515, 3, 401459, 2, 0, 0 },
2061 { 84, 419, 1515, 3, 401461, 2, 0, 0 },
2062 { 422, 419, 1510, 3, 401463, 2, 0, 0 },
2063 { 745, 419, 1505, 3, 401465, 2, 0, 0 },
2064 { 1031, 419, 1500, 3, 401467, 2, 0, 0 },
2065 { 1310, 419, 1500, 3, 401469, 2, 0, 0 },
2066 { 1575, 419, 1495, 3, 401471, 2, 0, 0 },
2067 { 1827, 419, 1490, 3, 401473, 2, 0, 0 },
2068 { 2086, 419, 1485, 3, 401475, 2, 0, 0 },
2069 { 2338, 419, 1485, 3, 401477, 2, 0, 0 },
2070 { 2590, 419, 1480, 3, 401479, 2, 0, 0 },
2071 { 151, 419, 1475, 3, 401481, 2, 0, 0 },
2072 { 481, 419, 1470, 3, 401483, 2, 0, 0 },
2073 { 324, 415, 1586, 13, 1638413, 12, 0, 0 },
2074 { 646, 430, 1571, 13, 1638417, 12, 0, 0 },
2075 { 933, 452, 1571, 13, 1638421, 12, 0, 0 },
2076 { 1211, 467, 1556, 13, 1638425, 12, 0, 0 },
2077 { 1477, 489, 1556, 13, 1638429, 12, 0, 0 },
2078 { 1734, 504, 1541, 13, 1638433, 12, 0, 0 },
2079 { 1994, 526, 1541, 13, 1638437, 12, 0, 0 },
2080 { 2245, 541, 1526, 13, 1638441, 12, 0, 0 },
2081 { 2498, 563, 1526, 13, 1638445, 12, 0, 0 },
2082 { 2722, 578, 1511, 13, 1638449, 12, 0, 0 },
2083 { 48, 600, 1511, 13, 1638453, 12, 0, 0 },
2084 { 394, 615, 1496, 13, 1638457, 12, 0, 0 },
2085 { 709, 637, 1496, 13, 1638461, 12, 0, 0 },
2086 { 1003, 652, 1481, 13, 1638465, 12, 0, 0 },
2087 { 1274, 674, 1481, 13, 1638469, 12, 0, 0 },
2088 { 1547, 689, 1471, 13, 1638473, 12, 0, 0 },
2089 { 1791, 711, 1, 13, 1638639, 12, 0, 0 },
2090 { 2058, 718, 1, 13, 1638643, 12, 0, 0 },
2091 { 2302, 725, 1, 13, 1638647, 12, 0, 0 },
2092 { 2562, 732, 1, 13, 1638651, 12, 0, 0 },
2093 { 115, 739, 1, 13, 1638655, 12, 0, 0 },
2094 { 453, 746, 1, 13, 1638659, 12, 0, 0 },
2095 { 776, 753, 1, 13, 1638663, 12, 0, 0 },
2096 { 1062, 760, 1, 13, 1638667, 12, 0, 0 },
2097 { 1341, 767, 1, 13, 1638671, 12, 0, 0 },
2098 { 1606, 774, 1, 13, 1638675, 12, 0, 0 },
2099 { 1858, 781, 1, 13, 1638679, 12, 0, 0 },
2100 { 2117, 788, 1, 13, 1638683, 12, 0, 0 },
2101 { 2369, 795, 1, 13, 1638687, 12, 0, 0 },
2102 { 2621, 802, 1, 13, 1638691, 12, 0, 0 },
2103 { 182, 809, 1, 13, 1638695, 12, 0, 0 },
2104 { 512, 816, 1, 13, 1638699, 12, 0, 0 },
2105 { 810, 1, 1, 1, 4399, 55, 0, 0 },
2106 { 1088, 1, 1, 1, 4400, 55, 0, 0 },
2107 { 1375, 1, 1, 1, 4401, 55, 0, 0 },
2108 { 1632, 1, 1, 1, 4402, 55, 0, 0 },
2109 { 1892, 1, 1, 1, 4403, 55, 0, 0 },
2110 { 2143, 1, 1, 1, 4404, 55, 0, 0 },
2111 { 2403, 1, 1, 1, 4405, 55, 0, 0 },
2112 { 2647, 1, 1, 1, 4406, 55, 0, 0 },
2113 { 216, 1, 1, 1, 4407, 55, 0, 0 },
2114 { 538, 1, 1, 1, 4408, 55, 0, 0 },
2115 { 825, 1, 1, 1, 4409, 55, 0, 0 },
2116 { 1103, 1, 1, 1, 4410, 55, 0, 0 },
2117 { 1390, 1, 1, 1, 4411, 55, 0, 0 },
2118 { 1647, 1, 1, 1, 4412, 55, 0, 0 },
2119 { 1907, 1, 1, 1, 4413, 55, 0, 0 },
2120 { 2158, 1, 1, 1, 4414, 55, 0, 0 },
2121 { 2418, 1, 1, 1, 4415, 55, 0, 0 },
2122 { 2662, 1, 1, 1, 4416, 55, 0, 0 },
2123 { 231, 1, 1, 1, 4417, 55, 0, 0 },
2124 { 553, 1, 1, 1, 4418, 55, 0, 0 },
2125 { 840, 1, 1, 1, 4419, 55, 0, 0 },
2126 { 1118, 1, 1, 1, 4420, 55, 0, 0 },
2127 { 1405, 1, 1, 1, 4421, 55, 0, 0 },
2128 { 1662, 1, 1, 1, 4422, 55, 0, 0 },
2129 { 1922, 1, 1, 1, 4423, 55, 0, 0 },
2130 { 2173, 1, 1, 1, 4424, 55, 0, 0 },
2131 { 2433, 1, 1, 1, 4425, 55, 0, 0 },
2132 { 2677, 1, 1, 1, 4426, 55, 0, 0 },
2133 { 246, 1, 1, 1, 4427, 55, 0, 0 },
2134 { 568, 1, 1, 1, 4428, 55, 0, 0 },
2135 { 855, 1, 1, 1, 4429, 55, 0, 0 },
2136 { 1133, 1, 1, 1, 4430, 55, 0, 0 },
2137 { 258, 103, 1195, 33, 1638510, 24, 0, 0 },
2138 { 580, 131, 1135, 33, 1638518, 24, 0, 0 },
2139 { 867, 175, 1135, 33, 1638526, 24, 0, 0 },
2140 { 1145, 203, 1055, 33, 1638534, 24, 0, 0 },
2141 { 1417, 247, 1055, 33, 1638542, 24, 0, 0 },
2142 { 1674, 275, 975, 33, 1638550, 24, 0, 0 },
2143 { 1934, 319, 975, 33, 1638558, 24, 0, 0 },
2144 { 2185, 347, 915, 33, 1638566, 24, 0, 0 },
2145 { 273, 121, 1175, 33, 1638514, 24, 0, 0 },
2146 { 595, 165, 1095, 33, 1638522, 24, 0, 0 },
2147 { 882, 193, 1095, 33, 1638530, 24, 0, 0 },
2148 { 1160, 237, 1015, 33, 1638538, 24, 0, 0 },
2149 { 1432, 265, 1015, 33, 1638546, 24, 0, 0 },
2150 { 1689, 309, 935, 33, 1638554, 24, 0, 0 },
2151 { 1949, 337, 935, 33, 1638562, 24, 0, 0 },
2152 { 2200, 381, 895, 33, 1638570, 24, 0, 0 },
2153 { 310, 13, 891, 0, 4303, 1, 0, 0 },
2154 { 632, 13, 887, 0, 4304, 1, 0, 0 },
2155 { 919, 13, 887, 0, 4305, 1, 0, 0 },
2156 { 1197, 13, 883, 0, 4306, 1, 0, 0 },
2157 { 1469, 13, 883, 0, 4307, 1, 0, 0 },
2158 { 1726, 13, 879, 0, 4308, 1, 0, 0 },
2159 { 1986, 13, 879, 0, 4309, 1, 0, 0 },
2160 { 2237, 13, 875, 0, 4310, 1, 0, 0 },
2161 { 2490, 13, 875, 0, 4311, 1, 0, 0 },
2162 { 2714, 13, 871, 0, 4312, 1, 0, 0 },
2163 { 38, 13, 871, 0, 4313, 1, 0, 0 },
2164 { 384, 13, 867, 0, 4314, 1, 0, 0 },
2165 { 699, 13, 867, 0, 4315, 1, 0, 0 },
2166 { 993, 13, 863, 0, 4316, 1, 0, 0 },
2167 { 1264, 13, 863, 0, 4317, 1, 0, 0 },
2168 { 1537, 13, 859, 0, 4318, 1, 0, 0 },
2169 { 1787, 13, 859, 0, 4319, 1, 0, 0 },
2170 { 2054, 13, 855, 0, 4320, 1, 0, 0 },
2171 { 2298, 13, 855, 0, 4321, 1, 0, 0 },
2172 { 2558, 13, 851, 0, 4322, 1, 0, 0 },
2173 { 111, 13, 851, 0, 4323, 1, 0, 0 },
2174 { 449, 13, 847, 0, 4324, 1, 0, 0 },
2175 { 772, 13, 847, 0, 4325, 1, 0, 0 },
2176 { 1058, 13, 843, 0, 4326, 1, 0, 0 },
2177 { 1337, 13, 843, 0, 4327, 1, 0, 0 },
2178 { 1602, 13, 839, 0, 4328, 1, 0, 0 },
2179 { 1854, 13, 839, 0, 4329, 1, 0, 0 },
2180 { 2113, 13, 835, 0, 4330, 1, 0, 0 },
2181 { 2365, 13, 835, 0, 4331, 1, 0, 0 },
2182 { 2617, 13, 831, 0, 4332, 1, 0, 0 },
2183 { 178, 13, 831, 0, 4333, 1, 0, 0 },
2184 { 508, 13, 827, 0, 4334, 1, 0, 0 },
2185 { 2453, 4, 1, 0, 4108, 1, 1, 0 },
2186 { 2806, 1, 8, 1, 4175, 55, 0, 0 },
2187 { 2812, 1, 8, 1, 4179, 55, 0, 0 },
2188 { 2818, 1, 8, 1, 4183, 55, 0, 0 },
2189 { 2824, 1, 8, 1, 4187, 55, 0, 0 },
2190 { 2830, 1, 8, 1, 4191, 55, 0, 0 },
2191 { 2836, 1, 8, 1, 4195, 55, 0, 0 },
2192 { 2842, 1, 8, 1, 4199, 55, 0, 0 },
2193 { 2848, 1, 8, 1, 4203, 55, 0, 0 },
2194 { 2873, 1, 6, 1, 4174, 55, 0, 0 },
2195 { 2879, 1, 6, 1, 4178, 55, 0, 0 },
2196 { 2885, 1, 6, 1, 4182, 55, 0, 0 },
2197 { 2891, 1, 6, 1, 4186, 55, 0, 0 },
2198 { 2897, 1, 6, 1, 4190, 55, 0, 0 },
2199 { 2903, 1, 6, 1, 4194, 55, 0, 0 },
2200 { 2909, 1, 6, 1, 4198, 55, 0, 0 },
2201 { 2915, 1, 6, 1, 4202, 55, 0, 0 },
2202 { 2921, 1, 2, 1, 4173, 55, 0, 0 },
2203 { 2927, 1, 2, 1, 4177, 55, 0, 0 },
2204 { 2933, 1, 2, 1, 4181, 55, 0, 0 },
2205 { 2939, 1, 2, 1, 4185, 55, 0, 0 },
2206 { 2945, 1, 2, 1, 4189, 55, 0, 0 },
2207 { 2951, 1, 2, 1, 4193, 55, 0, 0 },
2208 { 2957, 1, 2, 1, 4197, 55, 0, 0 },
2209 { 2963, 1, 2, 1, 4201, 55, 0, 0 },
2210 { 2747, 1, 0, 1, 4176, 55, 0, 0 },
2211 { 2753, 1, 0, 1, 4180, 55, 0, 0 },
2212 { 2759, 1, 0, 1, 4184, 55, 0, 0 },
2213 { 2765, 1, 0, 1, 4188, 55, 0, 0 },
2214 { 2771, 1, 0, 1, 4192, 55, 0, 0 },
2215 { 2777, 1, 0, 1, 4196, 55, 0, 0 },
2216 { 2783, 1, 0, 1, 4200, 55, 0, 0 },
2217 { 2789, 1, 0, 1, 4204, 55, 0, 0 },
2218 { 313, 10, 1, 83, 401615, 52, 0, 0 },
2219 { 635, 15, 1, 83, 401617, 52, 0, 0 },
2220 { 922, 20, 1, 83, 401619, 52, 0, 0 },
2221 { 1200, 25, 1, 83, 401621, 52, 0, 0 },
2222 { 1472, 30, 1, 83, 401623, 52, 0, 0 },
2223 { 1729, 35, 1, 83, 401625, 52, 0, 0 },
2224 { 1989, 40, 1, 83, 401627, 52, 0, 0 },
2225 { 2240, 45, 1, 83, 401629, 52, 0, 0 },
2226 { 2493, 50, 1, 83, 401631, 52, 0, 0 },
2227 { 2717, 55, 1, 83, 401633, 52, 0, 0 },
2228 { 42, 60, 1, 83, 401635, 52, 0, 0 },
2229 { 388, 65, 1, 83, 401637, 52, 0, 0 },
2230 { 703, 70, 1, 83, 401639, 52, 0, 0 },
2231 { 997, 75, 1, 83, 401641, 52, 0, 0 },
2232 { 1268, 80, 1, 83, 401643, 52, 0, 0 },
2233 { 1541, 85, 1, 83, 401645, 52, 0, 0 },
2234};
2235
2236extern const MCPhysReg PPCRegUnitRoots[][2] = {
2237 { PPC::BP },
2238 { PPC::CARRY },
2239 { PPC::CARRY, PPC::XER },
2240 { PPC::CTR },
2241 { PPC::CTR, PPC::CTR8 },
2242 { PPC::FP },
2243 { PPC::LR },
2244 { PPC::LR, PPC::LR8 },
2245 { PPC::RM },
2246 { PPC::SPEFSCR },
2247 { PPC::VRSAVE },
2248 { PPC::XER },
2249 { PPC::ZERO },
2250 { PPC::F0 },
2251 { PPC::FH0 },
2252 { PPC::F1 },
2253 { PPC::FH1 },
2254 { PPC::F2 },
2255 { PPC::FH2 },
2256 { PPC::F3 },
2257 { PPC::FH3 },
2258 { PPC::F4 },
2259 { PPC::FH4 },
2260 { PPC::F5 },
2261 { PPC::FH5 },
2262 { PPC::F6 },
2263 { PPC::FH6 },
2264 { PPC::F7 },
2265 { PPC::FH7 },
2266 { PPC::F8 },
2267 { PPC::FH8 },
2268 { PPC::F9 },
2269 { PPC::FH9 },
2270 { PPC::F10 },
2271 { PPC::FH10 },
2272 { PPC::F11 },
2273 { PPC::FH11 },
2274 { PPC::F12 },
2275 { PPC::FH12 },
2276 { PPC::F13 },
2277 { PPC::FH13 },
2278 { PPC::F14 },
2279 { PPC::FH14 },
2280 { PPC::F15 },
2281 { PPC::FH15 },
2282 { PPC::F16 },
2283 { PPC::FH16 },
2284 { PPC::F17 },
2285 { PPC::FH17 },
2286 { PPC::F18 },
2287 { PPC::FH18 },
2288 { PPC::F19 },
2289 { PPC::FH19 },
2290 { PPC::F20 },
2291 { PPC::FH20 },
2292 { PPC::F21 },
2293 { PPC::FH21 },
2294 { PPC::F22 },
2295 { PPC::FH22 },
2296 { PPC::F23 },
2297 { PPC::FH23 },
2298 { PPC::F24 },
2299 { PPC::FH24 },
2300 { PPC::F25 },
2301 { PPC::FH25 },
2302 { PPC::F26 },
2303 { PPC::FH26 },
2304 { PPC::F27 },
2305 { PPC::FH27 },
2306 { PPC::F28 },
2307 { PPC::FH28 },
2308 { PPC::F29 },
2309 { PPC::FH29 },
2310 { PPC::F30 },
2311 { PPC::FH30 },
2312 { PPC::F31 },
2313 { PPC::FH31 },
2314 { PPC::CR0LT },
2315 { PPC::CR0GT },
2316 { PPC::CR0EQ },
2317 { PPC::CR0UN },
2318 { PPC::CR1LT },
2319 { PPC::CR1GT },
2320 { PPC::CR1EQ },
2321 { PPC::CR1UN },
2322 { PPC::CR2LT },
2323 { PPC::CR2GT },
2324 { PPC::CR2EQ },
2325 { PPC::CR2UN },
2326 { PPC::CR3LT },
2327 { PPC::CR3GT },
2328 { PPC::CR3EQ },
2329 { PPC::CR3UN },
2330 { PPC::CR4LT },
2331 { PPC::CR4GT },
2332 { PPC::CR4EQ },
2333 { PPC::CR4UN },
2334 { PPC::CR5LT },
2335 { PPC::CR5GT },
2336 { PPC::CR5EQ },
2337 { PPC::CR5UN },
2338 { PPC::CR6LT },
2339 { PPC::CR6GT },
2340 { PPC::CR6EQ },
2341 { PPC::CR6UN },
2342 { PPC::CR7LT },
2343 { PPC::CR7GT },
2344 { PPC::CR7EQ },
2345 { PPC::CR7UN },
2346 { PPC::CTR8 },
2347 { PPC::DMRROW0 },
2348 { PPC::DMRROW1 },
2349 { PPC::DMRROW2 },
2350 { PPC::DMRROW3 },
2351 { PPC::DMRROW4 },
2352 { PPC::DMRROW5 },
2353 { PPC::DMRROW6 },
2354 { PPC::DMRROW7 },
2355 { PPC::DMRROW8 },
2356 { PPC::DMRROW9 },
2357 { PPC::DMRROW10 },
2358 { PPC::DMRROW11 },
2359 { PPC::DMRROW12 },
2360 { PPC::DMRROW13 },
2361 { PPC::DMRROW14 },
2362 { PPC::DMRROW15 },
2363 { PPC::DMRROW16 },
2364 { PPC::DMRROW17 },
2365 { PPC::DMRROW18 },
2366 { PPC::DMRROW19 },
2367 { PPC::DMRROW20 },
2368 { PPC::DMRROW21 },
2369 { PPC::DMRROW22 },
2370 { PPC::DMRROW23 },
2371 { PPC::DMRROW24 },
2372 { PPC::DMRROW25 },
2373 { PPC::DMRROW26 },
2374 { PPC::DMRROW27 },
2375 { PPC::DMRROW28 },
2376 { PPC::DMRROW29 },
2377 { PPC::DMRROW30 },
2378 { PPC::DMRROW31 },
2379 { PPC::DMRROW32 },
2380 { PPC::DMRROW33 },
2381 { PPC::DMRROW34 },
2382 { PPC::DMRROW35 },
2383 { PPC::DMRROW36 },
2384 { PPC::DMRROW37 },
2385 { PPC::DMRROW38 },
2386 { PPC::DMRROW39 },
2387 { PPC::DMRROW40 },
2388 { PPC::DMRROW41 },
2389 { PPC::DMRROW42 },
2390 { PPC::DMRROW43 },
2391 { PPC::DMRROW44 },
2392 { PPC::DMRROW45 },
2393 { PPC::DMRROW46 },
2394 { PPC::DMRROW47 },
2395 { PPC::DMRROW48 },
2396 { PPC::DMRROW49 },
2397 { PPC::DMRROW50 },
2398 { PPC::DMRROW51 },
2399 { PPC::DMRROW52 },
2400 { PPC::DMRROW53 },
2401 { PPC::DMRROW54 },
2402 { PPC::DMRROW55 },
2403 { PPC::DMRROW56 },
2404 { PPC::DMRROW57 },
2405 { PPC::DMRROW58 },
2406 { PPC::DMRROW59 },
2407 { PPC::DMRROW60 },
2408 { PPC::DMRROW61 },
2409 { PPC::DMRROW62 },
2410 { PPC::DMRROW63 },
2411 { PPC::H0 },
2412 { PPC::H1 },
2413 { PPC::H2 },
2414 { PPC::H3 },
2415 { PPC::H4 },
2416 { PPC::H5 },
2417 { PPC::H6 },
2418 { PPC::H7 },
2419 { PPC::H8 },
2420 { PPC::H9 },
2421 { PPC::H10 },
2422 { PPC::H11 },
2423 { PPC::H12 },
2424 { PPC::H13 },
2425 { PPC::H14 },
2426 { PPC::H15 },
2427 { PPC::H16 },
2428 { PPC::H17 },
2429 { PPC::H18 },
2430 { PPC::H19 },
2431 { PPC::H20 },
2432 { PPC::H21 },
2433 { PPC::H22 },
2434 { PPC::H23 },
2435 { PPC::H24 },
2436 { PPC::H25 },
2437 { PPC::H26 },
2438 { PPC::H27 },
2439 { PPC::H28 },
2440 { PPC::H29 },
2441 { PPC::H30 },
2442 { PPC::H31 },
2443 { PPC::LR8 },
2444 { PPC::R0 },
2445 { PPC::R1 },
2446 { PPC::R2 },
2447 { PPC::R3 },
2448 { PPC::R4 },
2449 { PPC::R5 },
2450 { PPC::R6 },
2451 { PPC::R7 },
2452 { PPC::R8 },
2453 { PPC::R9 },
2454 { PPC::R10 },
2455 { PPC::R11 },
2456 { PPC::R12 },
2457 { PPC::R13 },
2458 { PPC::R14 },
2459 { PPC::R15 },
2460 { PPC::R16 },
2461 { PPC::R17 },
2462 { PPC::R18 },
2463 { PPC::R19 },
2464 { PPC::R20 },
2465 { PPC::R21 },
2466 { PPC::R22 },
2467 { PPC::R23 },
2468 { PPC::R24 },
2469 { PPC::R25 },
2470 { PPC::R26 },
2471 { PPC::R27 },
2472 { PPC::R28 },
2473 { PPC::R29 },
2474 { PPC::R30 },
2475 { PPC::R31 },
2476 { PPC::VF0 },
2477 { PPC::VFH0 },
2478 { PPC::VF1 },
2479 { PPC::VFH1 },
2480 { PPC::VF2 },
2481 { PPC::VFH2 },
2482 { PPC::VF3 },
2483 { PPC::VFH3 },
2484 { PPC::VF4 },
2485 { PPC::VFH4 },
2486 { PPC::VF5 },
2487 { PPC::VFH5 },
2488 { PPC::VF6 },
2489 { PPC::VFH6 },
2490 { PPC::VF7 },
2491 { PPC::VFH7 },
2492 { PPC::VF8 },
2493 { PPC::VFH8 },
2494 { PPC::VF9 },
2495 { PPC::VFH9 },
2496 { PPC::VF10 },
2497 { PPC::VFH10 },
2498 { PPC::VF11 },
2499 { PPC::VFH11 },
2500 { PPC::VF12 },
2501 { PPC::VFH12 },
2502 { PPC::VF13 },
2503 { PPC::VFH13 },
2504 { PPC::VF14 },
2505 { PPC::VFH14 },
2506 { PPC::VF15 },
2507 { PPC::VFH15 },
2508 { PPC::VF16 },
2509 { PPC::VFH16 },
2510 { PPC::VF17 },
2511 { PPC::VFH17 },
2512 { PPC::VF18 },
2513 { PPC::VFH18 },
2514 { PPC::VF19 },
2515 { PPC::VFH19 },
2516 { PPC::VF20 },
2517 { PPC::VFH20 },
2518 { PPC::VF21 },
2519 { PPC::VFH21 },
2520 { PPC::VF22 },
2521 { PPC::VFH22 },
2522 { PPC::VF23 },
2523 { PPC::VFH23 },
2524 { PPC::VF24 },
2525 { PPC::VFH24 },
2526 { PPC::VF25 },
2527 { PPC::VFH25 },
2528 { PPC::VF26 },
2529 { PPC::VFH26 },
2530 { PPC::VF27 },
2531 { PPC::VFH27 },
2532 { PPC::VF28 },
2533 { PPC::VFH28 },
2534 { PPC::VF29 },
2535 { PPC::VFH29 },
2536 { PPC::VF30 },
2537 { PPC::VFH30 },
2538 { PPC::VF31 },
2539 { PPC::VFH31 },
2540 { PPC::VSX32 },
2541 { PPC::VSX33 },
2542 { PPC::VSX34 },
2543 { PPC::VSX35 },
2544 { PPC::VSX36 },
2545 { PPC::VSX37 },
2546 { PPC::VSX38 },
2547 { PPC::VSX39 },
2548 { PPC::VSX40 },
2549 { PPC::VSX41 },
2550 { PPC::VSX42 },
2551 { PPC::VSX43 },
2552 { PPC::VSX44 },
2553 { PPC::VSX45 },
2554 { PPC::VSX46 },
2555 { PPC::VSX47 },
2556 { PPC::VSX48 },
2557 { PPC::VSX49 },
2558 { PPC::VSX50 },
2559 { PPC::VSX51 },
2560 { PPC::VSX52 },
2561 { PPC::VSX53 },
2562 { PPC::VSX54 },
2563 { PPC::VSX55 },
2564 { PPC::VSX56 },
2565 { PPC::VSX57 },
2566 { PPC::VSX58 },
2567 { PPC::VSX59 },
2568 { PPC::VSX60 },
2569 { PPC::VSX61 },
2570 { PPC::VSX62 },
2571 { PPC::VSX63 },
2572};
2573
2574namespace { // Register classes...
2575 // VSSRC Register Class...
2576 const MCPhysReg VSSRC[] = {
2577 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2578 };
2579
2580 // VSSRC Bit set.
2581 const uint8_t VSSRCBits[] = {
2582 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2583 };
2584
2585 // GPRC Register Class...
2586 const MCPhysReg GPRC[] = {
2587 PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP,
2588 };
2589
2590 // GPRC Bit set.
2591 const uint8_t GPRCBits[] = {
2592 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2593 };
2594
2595 // GPRC_NOR0 Register Class...
2596 const MCPhysReg GPRC_NOR0[] = {
2597 PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO,
2598 };
2599
2600 // GPRC_NOR0 Bit set.
2601 const uint8_t GPRC_NOR0Bits[] = {
2602 0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2603 };
2604
2605 // GPRC_and_GPRC_NOR0 Register Class...
2606 const MCPhysReg GPRC_and_GPRC_NOR0[] = {
2607 PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP,
2608 };
2609
2610 // GPRC_and_GPRC_NOR0 Bit set.
2611 const uint8_t GPRC_and_GPRC_NOR0Bits[] = {
2612 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2613 };
2614
2615 // CRBITRC Register Class...
2616 const MCPhysReg CRBITRC[] = {
2617 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
2618 };
2619
2620 // CRBITRC Bit set.
2621 const uint8_t CRBITRCBits[] = {
2622 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2623 };
2624
2625 // F4RC Register Class...
2626 const MCPhysReg F4RC[] = {
2627 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
2628 };
2629
2630 // F4RC Bit set.
2631 const uint8_t F4RCBits[] = {
2632 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2633 };
2634
2635 // GPRC32 Register Class...
2636 const MCPhysReg GPRC32[] = {
2637 PPC::H2, PPC::H3, PPC::H4, PPC::H5, PPC::H6, PPC::H7, PPC::H8, PPC::H9, PPC::H10, PPC::H11, PPC::H12, PPC::H30, PPC::H29, PPC::H28, PPC::H27, PPC::H26, PPC::H25, PPC::H24, PPC::H23, PPC::H22, PPC::H21, PPC::H20, PPC::H19, PPC::H18, PPC::H17, PPC::H16, PPC::H15, PPC::H14, PPC::H13, PPC::H31, PPC::H0, PPC::H1,
2638 };
2639
2640 // GPRC32 Bit set.
2641 const uint8_t GPRC32Bits[] = {
2642 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
2643 };
2644
2645 // CRRC Register Class...
2646 const MCPhysReg CRRC[] = {
2647 PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4,
2648 };
2649
2650 // CRRC Bit set.
2651 const uint8_t CRRCBits[] = {
2652 0x00, 0x00, 0xf0, 0x0f,
2653 };
2654
2655 // CARRYRC Register Class...
2656 const MCPhysReg CARRYRC[] = {
2657 PPC::CARRY, PPC::XER,
2658 };
2659
2660 // CARRYRC Bit set.
2661 const uint8_t CARRYRCBits[] = {
2662 0x04, 0x02,
2663 };
2664
2665 // CTRRC Register Class...
2666 const MCPhysReg CTRRC[] = {
2667 PPC::CTR,
2668 };
2669
2670 // CTRRC Bit set.
2671 const uint8_t CTRRCBits[] = {
2672 0x08,
2673 };
2674
2675 // LRRC Register Class...
2676 const MCPhysReg LRRC[] = {
2677 PPC::LR,
2678 };
2679
2680 // LRRC Bit set.
2681 const uint8_t LRRCBits[] = {
2682 0x20,
2683 };
2684
2685 // VRSAVERC Register Class...
2686 const MCPhysReg VRSAVERC[] = {
2687 PPC::VRSAVE,
2688 };
2689
2690 // VRSAVERC Bit set.
2691 const uint8_t VRSAVERCBits[] = {
2692 0x00, 0x01,
2693 };
2694
2695 // SPILLTOVSRRC Register Class...
2696 const MCPhysReg SPILLTOVSRRC[] = {
2697 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2698 };
2699
2700 // SPILLTOVSRRC Bit set.
2701 const uint8_t SPILLTOVSRRCBits[] = {
2702 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2703 };
2704
2705 // VSFRC Register Class...
2706 const MCPhysReg VSFRC[] = {
2707 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2708 };
2709
2710 // VSFRC Bit set.
2711 const uint8_t VSFRCBits[] = {
2712 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2713 };
2714
2715 // G8RC Register Class...
2716 const MCPhysReg G8RC[] = {
2717 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8,
2718 };
2719
2720 // G8RC Bit set.
2721 const uint8_t G8RCBits[] = {
2722 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2723 };
2724
2725 // G8RC_NOX0 Register Class...
2726 const MCPhysReg G8RC_NOX0[] = {
2727 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8,
2728 };
2729
2730 // G8RC_NOX0 Bit set.
2731 const uint8_t G8RC_NOX0Bits[] = {
2732 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
2733 };
2734
2735 // SPILLTOVSRRC_and_VSFRC Register Class...
2736 const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = {
2737 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2738 };
2739
2740 // SPILLTOVSRRC_and_VSFRC Bit set.
2741 const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = {
2742 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2743 };
2744
2745 // G8RC_and_G8RC_NOX0 Register Class...
2746 const MCPhysReg G8RC_and_G8RC_NOX0[] = {
2747 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8,
2748 };
2749
2750 // G8RC_and_G8RC_NOX0 Bit set.
2751 const uint8_t G8RC_and_G8RC_NOX0Bits[] = {
2752 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2753 };
2754
2755 // F8RC Register Class...
2756 const MCPhysReg F8RC[] = {
2757 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
2758 };
2759
2760 // F8RC Bit set.
2761 const uint8_t F8RCBits[] = {
2762 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2763 };
2764
2765 // FHRC Register Class...
2766 const MCPhysReg FHRC[] = {
2767 PPC::FH0, PPC::FH1, PPC::FH2, PPC::FH3, PPC::FH4, PPC::FH5, PPC::FH6, PPC::FH7, PPC::FH8, PPC::FH9, PPC::FH10, PPC::FH11, PPC::FH12, PPC::FH13, PPC::FH14, PPC::FH15, PPC::FH16, PPC::FH17, PPC::FH18, PPC::FH19, PPC::FH20, PPC::FH21, PPC::FH22, PPC::FH23, PPC::FH24, PPC::FH25, PPC::FH26, PPC::FH27, PPC::FH28, PPC::FH29, PPC::FH30, PPC::FH31,
2768 };
2769
2770 // FHRC Bit set.
2771 const uint8_t FHRCBits[] = {
2772 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2773 };
2774
2775 // SPERC Register Class...
2776 const MCPhysReg SPERC[] = {
2777 PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S0, PPC::S1,
2778 };
2779
2780 // SPERC Bit set.
2781 const uint8_t SPERCBits[] = {
2782 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2783 };
2784
2785 // VFHRC Register Class...
2786 const MCPhysReg VFHRC[] = {
2787 PPC::VFH0, PPC::VFH1, PPC::VFH2, PPC::VFH3, PPC::VFH4, PPC::VFH5, PPC::VFH6, PPC::VFH7, PPC::VFH8, PPC::VFH9, PPC::VFH10, PPC::VFH11, PPC::VFH12, PPC::VFH13, PPC::VFH14, PPC::VFH15, PPC::VFH16, PPC::VFH17, PPC::VFH18, PPC::VFH19, PPC::VFH20, PPC::VFH21, PPC::VFH22, PPC::VFH23, PPC::VFH24, PPC::VFH25, PPC::VFH26, PPC::VFH27, PPC::VFH28, PPC::VFH29, PPC::VFH30, PPC::VFH31,
2788 };
2789
2790 // VFHRC Bit set.
2791 const uint8_t VFHRCBits[] = {
2792 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2793 };
2794
2795 // VFRC Register Class...
2796 const MCPhysReg VFRC[] = {
2797 PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
2798 };
2799
2800 // VFRC Bit set.
2801 const uint8_t VFRCBits[] = {
2802 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2803 };
2804
2805 // SPERC_with_sub_32_in_GPRC_NOR0 Register Class...
2806 const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = {
2807 PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S1,
2808 };
2809
2810 // SPERC_with_sub_32_in_GPRC_NOR0 Bit set.
2811 const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = {
2812 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
2813 };
2814
2815 // SPILLTOVSRRC_and_VFRC Register Class...
2816 const MCPhysReg SPILLTOVSRRC_and_VFRC[] = {
2817 PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
2818 };
2819
2820 // SPILLTOVSRRC_and_VFRC Bit set.
2821 const uint8_t SPILLTOVSRRC_and_VFRCBits[] = {
2822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2823 };
2824
2825 // SPILLTOVSRRC_and_F4RC Register Class...
2826 const MCPhysReg SPILLTOVSRRC_and_F4RC[] = {
2827 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13,
2828 };
2829
2830 // SPILLTOVSRRC_and_F4RC Bit set.
2831 const uint8_t SPILLTOVSRRC_and_F4RCBits[] = {
2832 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f,
2833 };
2834
2835 // CTRRC8 Register Class...
2836 const MCPhysReg CTRRC8[] = {
2837 PPC::CTR8,
2838 };
2839
2840 // CTRRC8 Bit set.
2841 const uint8_t CTRRC8Bits[] = {
2842 0x00, 0x00, 0x00, 0x10,
2843 };
2844
2845 // LR8RC Register Class...
2846 const MCPhysReg LR8RC[] = {
2847 PPC::LR8,
2848 };
2849
2850 // LR8RC Bit set.
2851 const uint8_t LR8RCBits[] = {
2852 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2853 };
2854
2855 // DMRROWRC Register Class...
2856 const MCPhysReg DMRROWRC[] = {
2857 PPC::DMRROW0, PPC::DMRROW1, PPC::DMRROW2, PPC::DMRROW3, PPC::DMRROW4, PPC::DMRROW5, PPC::DMRROW6, PPC::DMRROW7, PPC::DMRROW8, PPC::DMRROW9, PPC::DMRROW10, PPC::DMRROW11, PPC::DMRROW12, PPC::DMRROW13, PPC::DMRROW14, PPC::DMRROW15, PPC::DMRROW16, PPC::DMRROW17, PPC::DMRROW18, PPC::DMRROW19, PPC::DMRROW20, PPC::DMRROW21, PPC::DMRROW22, PPC::DMRROW23, PPC::DMRROW24, PPC::DMRROW25, PPC::DMRROW26, PPC::DMRROW27, PPC::DMRROW28, PPC::DMRROW29, PPC::DMRROW30, PPC::DMRROW31, PPC::DMRROW32, PPC::DMRROW33, PPC::DMRROW34, PPC::DMRROW35, PPC::DMRROW36, PPC::DMRROW37, PPC::DMRROW38, PPC::DMRROW39, PPC::DMRROW40, PPC::DMRROW41, PPC::DMRROW42, PPC::DMRROW43, PPC::DMRROW44, PPC::DMRROW45, PPC::DMRROW46, PPC::DMRROW47, PPC::DMRROW48, PPC::DMRROW49, PPC::DMRROW50, PPC::DMRROW51, PPC::DMRROW52, PPC::DMRROW53, PPC::DMRROW54, PPC::DMRROW55, PPC::DMRROW56, PPC::DMRROW57, PPC::DMRROW58, PPC::DMRROW59, PPC::DMRROW60, PPC::DMRROW61, PPC::DMRROW62, PPC::DMRROW63,
2858 };
2859
2860 // DMRROWRC Bit set.
2861 const uint8_t DMRROWRCBits[] = {
2862 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f,
2863 };
2864
2865 // VSRC Register Class...
2866 const MCPhysReg VSRC[] = {
2867 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
2868 };
2869
2870 // VSRC Bit set.
2871 const uint8_t VSRCBits[] = {
2872 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2873 };
2874
2875 // VSRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2876 const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = {
2877 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2878 };
2879
2880 // VSRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2881 const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2882 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2883 };
2884
2885 // VRRC Register Class...
2886 const MCPhysReg VRRC[] = {
2887 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
2888 };
2889
2890 // VRRC Bit set.
2891 const uint8_t VRRCBits[] = {
2892 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2893 };
2894
2895 // VSLRC Register Class...
2896 const MCPhysReg VSLRC[] = {
2897 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14,
2898 };
2899
2900 // VSLRC Bit set.
2901 const uint8_t VSLRCBits[] = {
2902 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2903 };
2904
2905 // VRRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2906 const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = {
2907 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2908 };
2909
2910 // VRRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2911 const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2912 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
2913 };
2914
2915 // FpRC Register Class...
2916 const MCPhysReg FpRC[] = {
2917 PPC::Fpair0, PPC::Fpair2, PPC::Fpair4, PPC::Fpair6, PPC::Fpair8, PPC::Fpair10, PPC::Fpair12, PPC::Fpair14, PPC::Fpair16, PPC::Fpair18, PPC::Fpair20, PPC::Fpair22, PPC::Fpair24, PPC::Fpair26, PPC::Fpair28, PPC::Fpair30,
2918 };
2919
2920 // FpRC Bit set.
2921 const uint8_t FpRCBits[] = {
2922 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
2923 };
2924
2925 // G8pRC Register Class...
2926 const MCPhysReg G8pRC[] = {
2927 PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0,
2928 };
2929
2930 // G8pRC Bit set.
2931 const uint8_t G8pRCBits[] = {
2932 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2933 };
2934
2935 // G8pRC_with_sub_32_in_GPRC_NOR0 Register Class...
2936 const MCPhysReg G8pRC_with_sub_32_in_GPRC_NOR0[] = {
2937 PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6,
2938 };
2939
2940 // G8pRC_with_sub_32_in_GPRC_NOR0 Bit set.
2941 const uint8_t G8pRC_with_sub_32_in_GPRC_NOR0Bits[] = {
2942 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2943 };
2944
2945 // VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2946 const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = {
2947 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13,
2948 };
2949
2950 // VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2951 const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2952 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
2953 };
2954
2955 // FpRC_with_sub_fp0_in_SPILLTOVSRRC Register Class...
2956 const MCPhysReg FpRC_with_sub_fp0_in_SPILLTOVSRRC[] = {
2957 PPC::Fpair0, PPC::Fpair2, PPC::Fpair4, PPC::Fpair6, PPC::Fpair8, PPC::Fpair10, PPC::Fpair12,
2958 };
2959
2960 // FpRC_with_sub_fp0_in_SPILLTOVSRRC Bit set.
2961 const uint8_t FpRC_with_sub_fp0_in_SPILLTOVSRRCBits[] = {
2962 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
2963 };
2964
2965 // DMRROWpRC Register Class...
2966 const MCPhysReg DMRROWpRC[] = {
2967 PPC::DMRROWp0, PPC::DMRROWp1, PPC::DMRROWp2, PPC::DMRROWp3, PPC::DMRROWp4, PPC::DMRROWp5, PPC::DMRROWp6, PPC::DMRROWp7, PPC::DMRROWp8, PPC::DMRROWp9, PPC::DMRROWp10, PPC::DMRROWp11, PPC::DMRROWp12, PPC::DMRROWp13, PPC::DMRROWp14, PPC::DMRROWp15, PPC::DMRROWp16, PPC::DMRROWp17, PPC::DMRROWp18, PPC::DMRROWp19, PPC::DMRROWp20, PPC::DMRROWp21, PPC::DMRROWp22, PPC::DMRROWp23, PPC::DMRROWp24, PPC::DMRROWp25, PPC::DMRROWp26, PPC::DMRROWp27, PPC::DMRROWp28, PPC::DMRROWp29, PPC::DMRROWp30, PPC::DMRROWp31,
2968 };
2969
2970 // DMRROWpRC Bit set.
2971 const uint8_t DMRROWpRCBits[] = {
2972 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2973 };
2974
2975 // VSRpRC Register Class...
2976 const MCPhysReg VSRpRC[] = {
2977 PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7,
2978 };
2979
2980 // VSRpRC Bit set.
2981 const uint8_t VSRpRCBits[] = {
2982 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2983 };
2984
2985 // VSRpRC_with_sub_64_in_SPILLTOVSRRC Register Class...
2986 const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC[] = {
2987 PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6,
2988 };
2989
2990 // VSRpRC_with_sub_64_in_SPILLTOVSRRC Bit set.
2991 const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
2992 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0xf8, 0x1f,
2993 };
2994
2995 // VSRpRC_with_sub_64_in_F4RC Register Class...
2996 const MCPhysReg VSRpRC_with_sub_64_in_F4RC[] = {
2997 PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7,
2998 };
2999
3000 // VSRpRC_with_sub_64_in_F4RC Bit set.
3001 const uint8_t VSRpRC_with_sub_64_in_F4RCBits[] = {
3002 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
3003 };
3004
3005 // VSRpRC_with_sub_64_in_VFRC Register Class...
3006 const MCPhysReg VSRpRC_with_sub_64_in_VFRC[] = {
3007 PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26,
3008 };
3009
3010 // VSRpRC_with_sub_64_in_VFRC Bit set.
3011 const uint8_t VSRpRC_with_sub_64_in_VFRCBits[] = {
3012 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
3013 };
3014
3015 // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Register Class...
3016 const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC[] = {
3017 PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25,
3018 };
3019
3020 // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Bit set.
3021 const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits[] = {
3022 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f,
3023 };
3024
3025 // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Register Class...
3026 const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC[] = {
3027 PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6,
3028 };
3029
3030 // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Bit set.
3031 const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits[] = {
3032 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
3033 };
3034
3035 // ACCRC Register Class...
3036 const MCPhysReg ACCRC[] = {
3037 PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3, PPC::ACC4, PPC::ACC5, PPC::ACC6, PPC::ACC7,
3038 };
3039
3040 // ACCRC Bit set.
3041 const uint8_t ACCRCBits[] = {
3042 0x00, 0xf8, 0x07,
3043 };
3044
3045 // UACCRC Register Class...
3046 const MCPhysReg UACCRC[] = {
3047 PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3, PPC::UACC4, PPC::UACC5, PPC::UACC6, PPC::UACC7,
3048 };
3049
3050 // UACCRC Bit set.
3051 const uint8_t UACCRCBits[] = {
3052 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
3053 };
3054
3055 // WACCRC Register Class...
3056 const MCPhysReg WACCRC[] = {
3057 PPC::WACC0, PPC::WACC1, PPC::WACC2, PPC::WACC3, PPC::WACC4, PPC::WACC5, PPC::WACC6, PPC::WACC7,
3058 };
3059
3060 // WACCRC Bit set.
3061 const uint8_t WACCRCBits[] = {
3062 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
3063 };
3064
3065 // WACC_HIRC Register Class...
3066 const MCPhysReg WACC_HIRC[] = {
3067 PPC::WACC_HI0, PPC::WACC_HI1, PPC::WACC_HI2, PPC::WACC_HI3, PPC::WACC_HI4, PPC::WACC_HI5, PPC::WACC_HI6, PPC::WACC_HI7,
3068 };
3069
3070 // WACC_HIRC Bit set.
3071 const uint8_t WACC_HIRCBits[] = {
3072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
3073 };
3074
3075 // ACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
3076 const MCPhysReg ACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
3077 PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3,
3078 };
3079
3080 // ACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
3081 const uint8_t ACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
3082 0x00, 0x78,
3083 };
3084
3085 // UACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
3086 const MCPhysReg UACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
3087 PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3,
3088 };
3089
3090 // UACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
3091 const uint8_t UACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
3092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
3093 };
3094
3095 // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
3096 const MCPhysReg ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
3097 PPC::ACC0, PPC::ACC1, PPC::ACC2,
3098 };
3099
3100 // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
3101 const uint8_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
3102 0x00, 0x38,
3103 };
3104
3105 // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
3106 const MCPhysReg UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
3107 PPC::UACC0, PPC::UACC1, PPC::UACC2,
3108 };
3109
3110 // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
3111 const uint8_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
3112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
3113 };
3114
3115 // DMRRC Register Class...
3116 const MCPhysReg DMRRC[] = {
3117 PPC::DMR0, PPC::DMR1, PPC::DMR2, PPC::DMR3, PPC::DMR4, PPC::DMR5, PPC::DMR6, PPC::DMR7,
3118 };
3119
3120 // DMRRC Bit set.
3121 const uint8_t DMRRCBits[] = {
3122 0x00, 0x00, 0x00, 0xe0, 0x1f,
3123 };
3124
3125 // DMRpRC Register Class...
3126 const MCPhysReg DMRpRC[] = {
3127 PPC::DMRp0, PPC::DMRp1, PPC::DMRp2, PPC::DMRp3,
3128 };
3129
3130 // DMRpRC Bit set.
3131 const uint8_t DMRpRCBits[] = {
3132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
3133 };
3134
3135} // end anonymous namespace
3136
3137
3138#ifdef __GNUC__
3139#pragma GCC diagnostic push
3140#pragma GCC diagnostic ignored "-Woverlength-strings"
3141#endif
3142extern const char PPCRegClassStrings[] = {
3143 /* 0 */ "GPRC_and_GPRC_NOR0\000"
3144 /* 19 */ "SPERC_with_sub_32_in_GPRC_NOR0\000"
3145 /* 50 */ "G8pRC_with_sub_32_in_GPRC_NOR0\000"
3146 /* 81 */ "G8RC_and_G8RC_NOX0\000"
3147 /* 100 */ "GPRC32\000"
3148 /* 107 */ "CTRRC8\000"
3149 /* 114 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC\000"
3150 /* 158 */ "VSRpRC_with_sub_64_in_F4RC\000"
3151 /* 185 */ "F8RC\000"
3152 /* 190 */ "G8RC\000"
3153 /* 195 */ "LR8RC\000"
3154 /* 201 */ "UACCRC\000"
3155 /* 208 */ "WACCRC\000"
3156 /* 215 */ "SPERC\000"
3157 /* 221 */ "VRSAVERC\000"
3158 /* 230 */ "SPILLTOVSRRC_and_VSFRC\000"
3159 /* 253 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC\000"
3160 /* 297 */ "VSRpRC_with_sub_64_in_VFRC\000"
3161 /* 324 */ "VFHRC\000"
3162 /* 330 */ "WACC_HIRC\000"
3163 /* 340 */ "VSLRC\000"
3164 /* 346 */ "GPRC\000"
3165 /* 351 */ "CRRC\000"
3166 /* 356 */ "LRRC\000"
3167 /* 361 */ "DMRRC\000"
3168 /* 367 */ "FpRC_with_sub_fp0_in_SPILLTOVSRRC\000"
3169 /* 401 */ "UACCRC_with_sub_64_in_SPILLTOVSRRC\000"
3170 /* 436 */ "VSLRC_with_sub_64_in_SPILLTOVSRRC\000"
3171 /* 470 */ "VRRC_with_sub_64_in_SPILLTOVSRRC\000"
3172 /* 503 */ "VSRC_with_sub_64_in_SPILLTOVSRRC\000"
3173 /* 536 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC\000"
3174 /* 571 */ "UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC\000"
3175 /* 621 */ "CTRRC\000"
3176 /* 627 */ "VRRC\000"
3177 /* 632 */ "VSSRC\000"
3178 /* 638 */ "VSRC\000"
3179 /* 643 */ "CRBITRC\000"
3180 /* 651 */ "DMRROWRC\000"
3181 /* 660 */ "CARRYRC\000"
3182 /* 668 */ "G8pRC\000"
3183 /* 674 */ "FpRC\000"
3184 /* 679 */ "DMRpRC\000"
3185 /* 686 */ "VSRpRC\000"
3186 /* 693 */ "DMRROWpRC\000"
3187};
3188#ifdef __GNUC__
3189#pragma GCC diagnostic pop
3190#endif
3191
3192extern const MCRegisterClass PPCMCRegisterClasses[] = {
3193 { VSSRC, VSSRCBits, 632, 64, sizeof(VSSRCBits), PPC::VSSRCRegClassID, 32, 1, true, false },
3194 { GPRC, GPRCBits, 346, 34, sizeof(GPRCBits), PPC::GPRCRegClassID, 32, 1, true, false },
3195 { GPRC_NOR0, GPRC_NOR0Bits, 9, 34, sizeof(GPRC_NOR0Bits), PPC::GPRC_NOR0RegClassID, 32, 1, true, false },
3196 { GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 0, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC::GPRC_and_GPRC_NOR0RegClassID, 32, 1, true, false },
3197 { CRBITRC, CRBITRCBits, 643, 32, sizeof(CRBITRCBits), PPC::CRBITRCRegClassID, 32, 1, true, false },
3198 { F4RC, F4RCBits, 153, 32, sizeof(F4RCBits), PPC::F4RCRegClassID, 32, 1, true, false },
3199 { GPRC32, GPRC32Bits, 100, 32, sizeof(GPRC32Bits), PPC::GPRC32RegClassID, 32, 1, false, false },
3200 { CRRC, CRRCBits, 351, 8, sizeof(CRRCBits), PPC::CRRCRegClassID, 32, 1, true, false },
3201 { CARRYRC, CARRYRCBits, 660, 2, sizeof(CARRYRCBits), PPC::CARRYRCRegClassID, 32, -1, false, false },
3202 { CTRRC, CTRRCBits, 621, 1, sizeof(CTRRCBits), PPC::CTRRCRegClassID, 32, 1, false, false },
3203 { LRRC, LRRCBits, 356, 1, sizeof(LRRCBits), PPC::LRRCRegClassID, 32, 1, false, false },
3204 { VRSAVERC, VRSAVERCBits, 221, 1, sizeof(VRSAVERCBits), PPC::VRSAVERCRegClassID, 32, 1, true, false },
3205 { SPILLTOVSRRC, SPILLTOVSRRCBits, 388, 68, sizeof(SPILLTOVSRRCBits), PPC::SPILLTOVSRRCRegClassID, 64, 1, true, false },
3206 { VSFRC, VSFRCBits, 247, 64, sizeof(VSFRCBits), PPC::VSFRCRegClassID, 64, 1, true, false },
3207 { G8RC, G8RCBits, 190, 34, sizeof(G8RCBits), PPC::G8RCRegClassID, 64, 1, true, false },
3208 { G8RC_NOX0, G8RC_NOX0Bits, 90, 34, sizeof(G8RC_NOX0Bits), PPC::G8RC_NOX0RegClassID, 64, 1, true, false },
3209 { SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, 230, 34, sizeof(SPILLTOVSRRC_and_VSFRCBits), PPC::SPILLTOVSRRC_and_VSFRCRegClassID, 64, 1, true, false },
3210 { G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, 81, 33, sizeof(G8RC_and_G8RC_NOX0Bits), PPC::G8RC_and_G8RC_NOX0RegClassID, 64, 1, true, false },
3211 { F8RC, F8RCBits, 185, 32, sizeof(F8RCBits), PPC::F8RCRegClassID, 64, 1, true, false },
3212 { FHRC, FHRCBits, 325, 32, sizeof(FHRCBits), PPC::FHRCRegClassID, 64, -1, false, false },
3213 { SPERC, SPERCBits, 215, 32, sizeof(SPERCBits), PPC::SPERCRegClassID, 64, 1, true, false },
3214 { VFHRC, VFHRCBits, 324, 32, sizeof(VFHRCBits), PPC::VFHRCRegClassID, 64, -1, false, false },
3215 { VFRC, VFRCBits, 292, 32, sizeof(VFRCBits), PPC::VFRCRegClassID, 64, 1, true, false },
3216 { SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, 19, 31, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits), PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClassID, 64, 1, true, false },
3217 { SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, 275, 20, sizeof(SPILLTOVSRRC_and_VFRCBits), PPC::SPILLTOVSRRC_and_VFRCRegClassID, 64, 1, true, false },
3218 { SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, 136, 14, sizeof(SPILLTOVSRRC_and_F4RCBits), PPC::SPILLTOVSRRC_and_F4RCRegClassID, 64, 1, true, false },
3219 { CTRRC8, CTRRC8Bits, 107, 1, sizeof(CTRRC8Bits), PPC::CTRRC8RegClassID, 64, 1, false, false },
3220 { LR8RC, LR8RCBits, 195, 1, sizeof(LR8RCBits), PPC::LR8RCRegClassID, 64, 1, false, false },
3221 { DMRROWRC, DMRROWRCBits, 651, 64, sizeof(DMRROWRCBits), PPC::DMRROWRCRegClassID, 128, 1, true, false },
3222 { VSRC, VSRCBits, 638, 64, sizeof(VSRCBits), PPC::VSRCRegClassID, 128, 1, true, false },
3223 { VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, 503, 34, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true, false },
3224 { VRRC, VRRCBits, 627, 32, sizeof(VRRCBits), PPC::VRRCRegClassID, 128, 1, true, false },
3225 { VSLRC, VSLRCBits, 340, 32, sizeof(VSLRCBits), PPC::VSLRCRegClassID, 128, 1, true, false },
3226 { VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, 470, 20, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true, false },
3227 { FpRC, FpRCBits, 674, 16, sizeof(FpRCBits), PPC::FpRCRegClassID, 128, 1, true, false },
3228 { G8pRC, G8pRCBits, 668, 16, sizeof(G8pRCBits), PPC::G8pRCRegClassID, 128, 1, true, false },
3229 { G8pRC_with_sub_32_in_GPRC_NOR0, G8pRC_with_sub_32_in_GPRC_NOR0Bits, 50, 15, sizeof(G8pRC_with_sub_32_in_GPRC_NOR0Bits), PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID, 128, 1, true, false },
3230 { VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, 436, 14, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true, false },
3231 { FpRC_with_sub_fp0_in_SPILLTOVSRRC, FpRC_with_sub_fp0_in_SPILLTOVSRRCBits, 367, 7, sizeof(FpRC_with_sub_fp0_in_SPILLTOVSRRCBits), PPC::FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID, 128, 1, true, false },
3232 { DMRROWpRC, DMRROWpRCBits, 693, 32, sizeof(DMRROWpRCBits), PPC::DMRROWpRCRegClassID, 256, 1, true, false },
3233 { VSRpRC, VSRpRCBits, 686, 32, sizeof(VSRpRCBits), PPC::VSRpRCRegClassID, 256, 1, true, false },
3234 { VSRpRC_with_sub_64_in_SPILLTOVSRRC, VSRpRC_with_sub_64_in_SPILLTOVSRRCBits, 536, 17, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 256, 1, true, false },
3235 { VSRpRC_with_sub_64_in_F4RC, VSRpRC_with_sub_64_in_F4RCBits, 158, 16, sizeof(VSRpRC_with_sub_64_in_F4RCBits), PPC::VSRpRC_with_sub_64_in_F4RCRegClassID, 256, 1, true, false },
3236 { VSRpRC_with_sub_64_in_VFRC, VSRpRC_with_sub_64_in_VFRCBits, 297, 16, sizeof(VSRpRC_with_sub_64_in_VFRCBits), PPC::VSRpRC_with_sub_64_in_VFRCRegClassID, 256, 1, true, false },
3237 { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits, 253, 10, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID, 256, 1, true, false },
3238 { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits, 114, 7, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID, 256, 1, true, false },
3239 { ACCRC, ACCRCBits, 202, 8, sizeof(ACCRCBits), PPC::ACCRCRegClassID, 512, 1, true, false },
3240 { UACCRC, UACCRCBits, 201, 8, sizeof(UACCRCBits), PPC::UACCRCRegClassID, 512, 1, true, false },
3241 { WACCRC, WACCRCBits, 208, 8, sizeof(WACCRCBits), PPC::WACCRCRegClassID, 512, 1, true, false },
3242 { WACC_HIRC, WACC_HIRCBits, 330, 8, sizeof(WACC_HIRCBits), PPC::WACC_HIRCRegClassID, 512, 1, true, false },
3243 { ACCRC_with_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_64_in_SPILLTOVSRRCBits, 402, 4, sizeof(ACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true, false },
3244 { UACCRC_with_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_64_in_SPILLTOVSRRCBits, 401, 4, sizeof(UACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true, false },
3245 { ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 572, 3, sizeof(ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true, false },
3246 { UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 571, 3, sizeof(UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true, false },
3247 { DMRRC, DMRRCBits, 361, 8, sizeof(DMRRCBits), PPC::DMRRCRegClassID, 1024, 1, true, false },
3248 { DMRpRC, DMRpRCBits, 679, 4, sizeof(DMRpRCBits), PPC::DMRpRCRegClassID, 2048, 1, true, false },
3249};
3250
3251// PPC Dwarf<->LLVM register mappings.
3252extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[] = {
3253 { 0U, PPC::X0 },
3254 { 1U, PPC::X1 },
3255 { 2U, PPC::X2 },
3256 { 3U, PPC::X3 },
3257 { 4U, PPC::X4 },
3258 { 5U, PPC::X5 },
3259 { 6U, PPC::X6 },
3260 { 7U, PPC::X7 },
3261 { 8U, PPC::X8 },
3262 { 9U, PPC::X9 },
3263 { 10U, PPC::X10 },
3264 { 11U, PPC::X11 },
3265 { 12U, PPC::X12 },
3266 { 13U, PPC::X13 },
3267 { 14U, PPC::X14 },
3268 { 15U, PPC::X15 },
3269 { 16U, PPC::X16 },
3270 { 17U, PPC::X17 },
3271 { 18U, PPC::X18 },
3272 { 19U, PPC::X19 },
3273 { 20U, PPC::X20 },
3274 { 21U, PPC::X21 },
3275 { 22U, PPC::X22 },
3276 { 23U, PPC::X23 },
3277 { 24U, PPC::X24 },
3278 { 25U, PPC::X25 },
3279 { 26U, PPC::X26 },
3280 { 27U, PPC::X27 },
3281 { 28U, PPC::X28 },
3282 { 29U, PPC::X29 },
3283 { 30U, PPC::X30 },
3284 { 31U, PPC::X31 },
3285 { 32U, PPC::F0 },
3286 { 33U, PPC::F1 },
3287 { 34U, PPC::F2 },
3288 { 35U, PPC::F3 },
3289 { 36U, PPC::F4 },
3290 { 37U, PPC::F5 },
3291 { 38U, PPC::F6 },
3292 { 39U, PPC::F7 },
3293 { 40U, PPC::F8 },
3294 { 41U, PPC::F9 },
3295 { 42U, PPC::F10 },
3296 { 43U, PPC::F11 },
3297 { 44U, PPC::F12 },
3298 { 45U, PPC::F13 },
3299 { 46U, PPC::F14 },
3300 { 47U, PPC::F15 },
3301 { 48U, PPC::F16 },
3302 { 49U, PPC::F17 },
3303 { 50U, PPC::F18 },
3304 { 51U, PPC::F19 },
3305 { 52U, PPC::F20 },
3306 { 53U, PPC::F21 },
3307 { 54U, PPC::F22 },
3308 { 55U, PPC::F23 },
3309 { 56U, PPC::F24 },
3310 { 57U, PPC::F25 },
3311 { 58U, PPC::F26 },
3312 { 59U, PPC::F27 },
3313 { 60U, PPC::F28 },
3314 { 61U, PPC::F29 },
3315 { 62U, PPC::F30 },
3316 { 63U, PPC::F31 },
3317 { 65U, PPC::LR8 },
3318 { 66U, PPC::CTR8 },
3319 { 68U, PPC::CR0 },
3320 { 69U, PPC::CR1 },
3321 { 70U, PPC::CR2 },
3322 { 71U, PPC::CR3 },
3323 { 72U, PPC::CR4 },
3324 { 73U, PPC::CR5 },
3325 { 74U, PPC::CR6 },
3326 { 75U, PPC::CR7 },
3327 { 76U, PPC::XER },
3328 { 77U, PPC::VF0 },
3329 { 78U, PPC::VF1 },
3330 { 79U, PPC::VF2 },
3331 { 80U, PPC::VF3 },
3332 { 81U, PPC::VF4 },
3333 { 82U, PPC::VF5 },
3334 { 83U, PPC::VF6 },
3335 { 84U, PPC::VF7 },
3336 { 85U, PPC::VF8 },
3337 { 86U, PPC::VF9 },
3338 { 87U, PPC::VF10 },
3339 { 88U, PPC::VF11 },
3340 { 89U, PPC::VF12 },
3341 { 90U, PPC::VF13 },
3342 { 91U, PPC::VF14 },
3343 { 92U, PPC::VF15 },
3344 { 93U, PPC::VF16 },
3345 { 94U, PPC::VF17 },
3346 { 95U, PPC::VF18 },
3347 { 96U, PPC::VF19 },
3348 { 97U, PPC::VF20 },
3349 { 98U, PPC::VF21 },
3350 { 99U, PPC::VF22 },
3351 { 100U, PPC::VF23 },
3352 { 101U, PPC::VF24 },
3353 { 102U, PPC::VF25 },
3354 { 103U, PPC::VF26 },
3355 { 104U, PPC::VF27 },
3356 { 105U, PPC::VF28 },
3357 { 106U, PPC::VF29 },
3358 { 107U, PPC::VF30 },
3359 { 108U, PPC::VF31 },
3360 { 109U, PPC::VRSAVE },
3361 { 612U, PPC::SPEFSCR },
3362 { 1200U, PPC::S0 },
3363 { 1201U, PPC::S1 },
3364 { 1202U, PPC::S2 },
3365 { 1203U, PPC::S3 },
3366 { 1204U, PPC::S4 },
3367 { 1205U, PPC::S5 },
3368 { 1206U, PPC::S6 },
3369 { 1207U, PPC::S7 },
3370 { 1208U, PPC::S8 },
3371 { 1209U, PPC::S9 },
3372 { 1210U, PPC::S10 },
3373 { 1211U, PPC::S11 },
3374 { 1212U, PPC::S12 },
3375 { 1213U, PPC::S13 },
3376 { 1214U, PPC::S14 },
3377 { 1215U, PPC::S15 },
3378 { 1216U, PPC::S16 },
3379 { 1217U, PPC::S17 },
3380 { 1218U, PPC::S18 },
3381 { 1219U, PPC::S19 },
3382 { 1220U, PPC::S20 },
3383 { 1221U, PPC::S21 },
3384 { 1222U, PPC::S22 },
3385 { 1223U, PPC::S23 },
3386 { 1224U, PPC::S24 },
3387 { 1225U, PPC::S25 },
3388 { 1226U, PPC::S26 },
3389 { 1227U, PPC::S27 },
3390 { 1228U, PPC::S28 },
3391 { 1229U, PPC::S29 },
3392 { 1230U, PPC::S30 },
3393 { 1231U, PPC::S31 },
3394};
3395extern const unsigned PPCDwarfFlavour0Dwarf2LSize = std::size(PPCDwarfFlavour0Dwarf2L);
3396
3397extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[] = {
3398 { 0U, PPC::R0 },
3399 { 1U, PPC::R1 },
3400 { 2U, PPC::R2 },
3401 { 3U, PPC::R3 },
3402 { 4U, PPC::R4 },
3403 { 5U, PPC::R5 },
3404 { 6U, PPC::R6 },
3405 { 7U, PPC::R7 },
3406 { 8U, PPC::R8 },
3407 { 9U, PPC::R9 },
3408 { 10U, PPC::R10 },
3409 { 11U, PPC::R11 },
3410 { 12U, PPC::R12 },
3411 { 13U, PPC::R13 },
3412 { 14U, PPC::R14 },
3413 { 15U, PPC::R15 },
3414 { 16U, PPC::R16 },
3415 { 17U, PPC::R17 },
3416 { 18U, PPC::R18 },
3417 { 19U, PPC::R19 },
3418 { 20U, PPC::R20 },
3419 { 21U, PPC::R21 },
3420 { 22U, PPC::R22 },
3421 { 23U, PPC::R23 },
3422 { 24U, PPC::R24 },
3423 { 25U, PPC::R25 },
3424 { 26U, PPC::R26 },
3425 { 27U, PPC::R27 },
3426 { 28U, PPC::R28 },
3427 { 29U, PPC::R29 },
3428 { 30U, PPC::R30 },
3429 { 31U, PPC::R31 },
3430 { 32U, PPC::F0 },
3431 { 33U, PPC::F1 },
3432 { 34U, PPC::F2 },
3433 { 35U, PPC::F3 },
3434 { 36U, PPC::F4 },
3435 { 37U, PPC::F5 },
3436 { 38U, PPC::F6 },
3437 { 39U, PPC::F7 },
3438 { 40U, PPC::F8 },
3439 { 41U, PPC::F9 },
3440 { 42U, PPC::F10 },
3441 { 43U, PPC::F11 },
3442 { 44U, PPC::F12 },
3443 { 45U, PPC::F13 },
3444 { 46U, PPC::F14 },
3445 { 47U, PPC::F15 },
3446 { 48U, PPC::F16 },
3447 { 49U, PPC::F17 },
3448 { 50U, PPC::F18 },
3449 { 51U, PPC::F19 },
3450 { 52U, PPC::F20 },
3451 { 53U, PPC::F21 },
3452 { 54U, PPC::F22 },
3453 { 55U, PPC::F23 },
3454 { 56U, PPC::F24 },
3455 { 57U, PPC::F25 },
3456 { 58U, PPC::F26 },
3457 { 59U, PPC::F27 },
3458 { 60U, PPC::F28 },
3459 { 61U, PPC::F29 },
3460 { 62U, PPC::F30 },
3461 { 63U, PPC::F31 },
3462 { 65U, PPC::LR },
3463 { 66U, PPC::CTR },
3464 { 68U, PPC::CR0 },
3465 { 69U, PPC::CR1 },
3466 { 70U, PPC::CR2 },
3467 { 71U, PPC::CR3 },
3468 { 72U, PPC::CR4 },
3469 { 73U, PPC::CR5 },
3470 { 74U, PPC::CR6 },
3471 { 75U, PPC::CR7 },
3472 { 77U, PPC::VF0 },
3473 { 78U, PPC::VF1 },
3474 { 79U, PPC::VF2 },
3475 { 80U, PPC::VF3 },
3476 { 81U, PPC::VF4 },
3477 { 82U, PPC::VF5 },
3478 { 83U, PPC::VF6 },
3479 { 84U, PPC::VF7 },
3480 { 85U, PPC::VF8 },
3481 { 86U, PPC::VF9 },
3482 { 87U, PPC::VF10 },
3483 { 88U, PPC::VF11 },
3484 { 89U, PPC::VF12 },
3485 { 90U, PPC::VF13 },
3486 { 91U, PPC::VF14 },
3487 { 92U, PPC::VF15 },
3488 { 93U, PPC::VF16 },
3489 { 94U, PPC::VF17 },
3490 { 95U, PPC::VF18 },
3491 { 96U, PPC::VF19 },
3492 { 97U, PPC::VF20 },
3493 { 98U, PPC::VF21 },
3494 { 99U, PPC::VF22 },
3495 { 100U, PPC::VF23 },
3496 { 101U, PPC::VF24 },
3497 { 102U, PPC::VF25 },
3498 { 103U, PPC::VF26 },
3499 { 104U, PPC::VF27 },
3500 { 105U, PPC::VF28 },
3501 { 106U, PPC::VF29 },
3502 { 107U, PPC::VF30 },
3503 { 108U, PPC::VF31 },
3504 { 112U, PPC::SPEFSCR },
3505 { 1200U, PPC::S0 },
3506 { 1201U, PPC::S1 },
3507 { 1202U, PPC::S2 },
3508 { 1203U, PPC::S3 },
3509 { 1204U, PPC::S4 },
3510 { 1205U, PPC::S5 },
3511 { 1206U, PPC::S6 },
3512 { 1207U, PPC::S7 },
3513 { 1208U, PPC::S8 },
3514 { 1209U, PPC::S9 },
3515 { 1210U, PPC::S10 },
3516 { 1211U, PPC::S11 },
3517 { 1212U, PPC::S12 },
3518 { 1213U, PPC::S13 },
3519 { 1214U, PPC::S14 },
3520 { 1215U, PPC::S15 },
3521 { 1216U, PPC::S16 },
3522 { 1217U, PPC::S17 },
3523 { 1218U, PPC::S18 },
3524 { 1219U, PPC::S19 },
3525 { 1220U, PPC::S20 },
3526 { 1221U, PPC::S21 },
3527 { 1222U, PPC::S22 },
3528 { 1223U, PPC::S23 },
3529 { 1224U, PPC::S24 },
3530 { 1225U, PPC::S25 },
3531 { 1226U, PPC::S26 },
3532 { 1227U, PPC::S27 },
3533 { 1228U, PPC::S28 },
3534 { 1229U, PPC::S29 },
3535 { 1230U, PPC::S30 },
3536 { 1231U, PPC::S31 },
3537};
3538extern const unsigned PPCDwarfFlavour1Dwarf2LSize = std::size(PPCDwarfFlavour1Dwarf2L);
3539
3540extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[] = {
3541 { 0U, PPC::X0 },
3542 { 1U, PPC::X1 },
3543 { 2U, PPC::X2 },
3544 { 3U, PPC::X3 },
3545 { 4U, PPC::X4 },
3546 { 5U, PPC::X5 },
3547 { 6U, PPC::X6 },
3548 { 7U, PPC::X7 },
3549 { 8U, PPC::X8 },
3550 { 9U, PPC::X9 },
3551 { 10U, PPC::X10 },
3552 { 11U, PPC::X11 },
3553 { 12U, PPC::X12 },
3554 { 13U, PPC::X13 },
3555 { 14U, PPC::X14 },
3556 { 15U, PPC::X15 },
3557 { 16U, PPC::X16 },
3558 { 17U, PPC::X17 },
3559 { 18U, PPC::X18 },
3560 { 19U, PPC::X19 },
3561 { 20U, PPC::X20 },
3562 { 21U, PPC::X21 },
3563 { 22U, PPC::X22 },
3564 { 23U, PPC::X23 },
3565 { 24U, PPC::X24 },
3566 { 25U, PPC::X25 },
3567 { 26U, PPC::X26 },
3568 { 27U, PPC::X27 },
3569 { 28U, PPC::X28 },
3570 { 29U, PPC::X29 },
3571 { 30U, PPC::X30 },
3572 { 31U, PPC::X31 },
3573 { 32U, PPC::F0 },
3574 { 33U, PPC::F1 },
3575 { 34U, PPC::F2 },
3576 { 35U, PPC::F3 },
3577 { 36U, PPC::F4 },
3578 { 37U, PPC::F5 },
3579 { 38U, PPC::F6 },
3580 { 39U, PPC::F7 },
3581 { 40U, PPC::F8 },
3582 { 41U, PPC::F9 },
3583 { 42U, PPC::F10 },
3584 { 43U, PPC::F11 },
3585 { 44U, PPC::F12 },
3586 { 45U, PPC::F13 },
3587 { 46U, PPC::F14 },
3588 { 47U, PPC::F15 },
3589 { 48U, PPC::F16 },
3590 { 49U, PPC::F17 },
3591 { 50U, PPC::F18 },
3592 { 51U, PPC::F19 },
3593 { 52U, PPC::F20 },
3594 { 53U, PPC::F21 },
3595 { 54U, PPC::F22 },
3596 { 55U, PPC::F23 },
3597 { 56U, PPC::F24 },
3598 { 57U, PPC::F25 },
3599 { 58U, PPC::F26 },
3600 { 59U, PPC::F27 },
3601 { 60U, PPC::F28 },
3602 { 61U, PPC::F29 },
3603 { 62U, PPC::F30 },
3604 { 63U, PPC::F31 },
3605 { 65U, PPC::LR8 },
3606 { 66U, PPC::CTR8 },
3607 { 68U, PPC::CR0 },
3608 { 69U, PPC::CR1 },
3609 { 70U, PPC::CR2 },
3610 { 71U, PPC::CR3 },
3611 { 72U, PPC::CR4 },
3612 { 73U, PPC::CR5 },
3613 { 74U, PPC::CR6 },
3614 { 75U, PPC::CR7 },
3615 { 76U, PPC::XER },
3616 { 77U, PPC::VF0 },
3617 { 78U, PPC::VF1 },
3618 { 79U, PPC::VF2 },
3619 { 80U, PPC::VF3 },
3620 { 81U, PPC::VF4 },
3621 { 82U, PPC::VF5 },
3622 { 83U, PPC::VF6 },
3623 { 84U, PPC::VF7 },
3624 { 85U, PPC::VF8 },
3625 { 86U, PPC::VF9 },
3626 { 87U, PPC::VF10 },
3627 { 88U, PPC::VF11 },
3628 { 89U, PPC::VF12 },
3629 { 90U, PPC::VF13 },
3630 { 91U, PPC::VF14 },
3631 { 92U, PPC::VF15 },
3632 { 93U, PPC::VF16 },
3633 { 94U, PPC::VF17 },
3634 { 95U, PPC::VF18 },
3635 { 96U, PPC::VF19 },
3636 { 97U, PPC::VF20 },
3637 { 98U, PPC::VF21 },
3638 { 99U, PPC::VF22 },
3639 { 100U, PPC::VF23 },
3640 { 101U, PPC::VF24 },
3641 { 102U, PPC::VF25 },
3642 { 103U, PPC::VF26 },
3643 { 104U, PPC::VF27 },
3644 { 105U, PPC::VF28 },
3645 { 106U, PPC::VF29 },
3646 { 107U, PPC::VF30 },
3647 { 108U, PPC::VF31 },
3648 { 109U, PPC::VRSAVE },
3649 { 612U, PPC::SPEFSCR },
3650 { 1200U, PPC::S0 },
3651 { 1201U, PPC::S1 },
3652 { 1202U, PPC::S2 },
3653 { 1203U, PPC::S3 },
3654 { 1204U, PPC::S4 },
3655 { 1205U, PPC::S5 },
3656 { 1206U, PPC::S6 },
3657 { 1207U, PPC::S7 },
3658 { 1208U, PPC::S8 },
3659 { 1209U, PPC::S9 },
3660 { 1210U, PPC::S10 },
3661 { 1211U, PPC::S11 },
3662 { 1212U, PPC::S12 },
3663 { 1213U, PPC::S13 },
3664 { 1214U, PPC::S14 },
3665 { 1215U, PPC::S15 },
3666 { 1216U, PPC::S16 },
3667 { 1217U, PPC::S17 },
3668 { 1218U, PPC::S18 },
3669 { 1219U, PPC::S19 },
3670 { 1220U, PPC::S20 },
3671 { 1221U, PPC::S21 },
3672 { 1222U, PPC::S22 },
3673 { 1223U, PPC::S23 },
3674 { 1224U, PPC::S24 },
3675 { 1225U, PPC::S25 },
3676 { 1226U, PPC::S26 },
3677 { 1227U, PPC::S27 },
3678 { 1228U, PPC::S28 },
3679 { 1229U, PPC::S29 },
3680 { 1230U, PPC::S30 },
3681 { 1231U, PPC::S31 },
3682};
3683extern const unsigned PPCEHFlavour0Dwarf2LSize = std::size(PPCEHFlavour0Dwarf2L);
3684
3685extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[] = {
3686 { 0U, PPC::R0 },
3687 { 1U, PPC::R1 },
3688 { 2U, PPC::R2 },
3689 { 3U, PPC::R3 },
3690 { 4U, PPC::R4 },
3691 { 5U, PPC::R5 },
3692 { 6U, PPC::R6 },
3693 { 7U, PPC::R7 },
3694 { 8U, PPC::R8 },
3695 { 9U, PPC::R9 },
3696 { 10U, PPC::R10 },
3697 { 11U, PPC::R11 },
3698 { 12U, PPC::R12 },
3699 { 13U, PPC::R13 },
3700 { 14U, PPC::R14 },
3701 { 15U, PPC::R15 },
3702 { 16U, PPC::R16 },
3703 { 17U, PPC::R17 },
3704 { 18U, PPC::R18 },
3705 { 19U, PPC::R19 },
3706 { 20U, PPC::R20 },
3707 { 21U, PPC::R21 },
3708 { 22U, PPC::R22 },
3709 { 23U, PPC::R23 },
3710 { 24U, PPC::R24 },
3711 { 25U, PPC::R25 },
3712 { 26U, PPC::R26 },
3713 { 27U, PPC::R27 },
3714 { 28U, PPC::R28 },
3715 { 29U, PPC::R29 },
3716 { 30U, PPC::R30 },
3717 { 31U, PPC::R31 },
3718 { 32U, PPC::F0 },
3719 { 33U, PPC::F1 },
3720 { 34U, PPC::F2 },
3721 { 35U, PPC::F3 },
3722 { 36U, PPC::F4 },
3723 { 37U, PPC::F5 },
3724 { 38U, PPC::F6 },
3725 { 39U, PPC::F7 },
3726 { 40U, PPC::F8 },
3727 { 41U, PPC::F9 },
3728 { 42U, PPC::F10 },
3729 { 43U, PPC::F11 },
3730 { 44U, PPC::F12 },
3731 { 45U, PPC::F13 },
3732 { 46U, PPC::F14 },
3733 { 47U, PPC::F15 },
3734 { 48U, PPC::F16 },
3735 { 49U, PPC::F17 },
3736 { 50U, PPC::F18 },
3737 { 51U, PPC::F19 },
3738 { 52U, PPC::F20 },
3739 { 53U, PPC::F21 },
3740 { 54U, PPC::F22 },
3741 { 55U, PPC::F23 },
3742 { 56U, PPC::F24 },
3743 { 57U, PPC::F25 },
3744 { 58U, PPC::F26 },
3745 { 59U, PPC::F27 },
3746 { 60U, PPC::F28 },
3747 { 61U, PPC::F29 },
3748 { 62U, PPC::F30 },
3749 { 63U, PPC::F31 },
3750 { 65U, PPC::LR },
3751 { 66U, PPC::CTR },
3752 { 68U, PPC::CR0 },
3753 { 69U, PPC::CR1 },
3754 { 70U, PPC::CR2 },
3755 { 71U, PPC::CR3 },
3756 { 72U, PPC::CR4 },
3757 { 73U, PPC::CR5 },
3758 { 74U, PPC::CR6 },
3759 { 75U, PPC::CR7 },
3760 { 77U, PPC::VF0 },
3761 { 78U, PPC::VF1 },
3762 { 79U, PPC::VF2 },
3763 { 80U, PPC::VF3 },
3764 { 81U, PPC::VF4 },
3765 { 82U, PPC::VF5 },
3766 { 83U, PPC::VF6 },
3767 { 84U, PPC::VF7 },
3768 { 85U, PPC::VF8 },
3769 { 86U, PPC::VF9 },
3770 { 87U, PPC::VF10 },
3771 { 88U, PPC::VF11 },
3772 { 89U, PPC::VF12 },
3773 { 90U, PPC::VF13 },
3774 { 91U, PPC::VF14 },
3775 { 92U, PPC::VF15 },
3776 { 93U, PPC::VF16 },
3777 { 94U, PPC::VF17 },
3778 { 95U, PPC::VF18 },
3779 { 96U, PPC::VF19 },
3780 { 97U, PPC::VF20 },
3781 { 98U, PPC::VF21 },
3782 { 99U, PPC::VF22 },
3783 { 100U, PPC::VF23 },
3784 { 101U, PPC::VF24 },
3785 { 102U, PPC::VF25 },
3786 { 103U, PPC::VF26 },
3787 { 104U, PPC::VF27 },
3788 { 105U, PPC::VF28 },
3789 { 106U, PPC::VF29 },
3790 { 107U, PPC::VF30 },
3791 { 108U, PPC::VF31 },
3792 { 112U, PPC::SPEFSCR },
3793 { 1200U, PPC::S0 },
3794 { 1201U, PPC::S1 },
3795 { 1202U, PPC::S2 },
3796 { 1203U, PPC::S3 },
3797 { 1204U, PPC::S4 },
3798 { 1205U, PPC::S5 },
3799 { 1206U, PPC::S6 },
3800 { 1207U, PPC::S7 },
3801 { 1208U, PPC::S8 },
3802 { 1209U, PPC::S9 },
3803 { 1210U, PPC::S10 },
3804 { 1211U, PPC::S11 },
3805 { 1212U, PPC::S12 },
3806 { 1213U, PPC::S13 },
3807 { 1214U, PPC::S14 },
3808 { 1215U, PPC::S15 },
3809 { 1216U, PPC::S16 },
3810 { 1217U, PPC::S17 },
3811 { 1218U, PPC::S18 },
3812 { 1219U, PPC::S19 },
3813 { 1220U, PPC::S20 },
3814 { 1221U, PPC::S21 },
3815 { 1222U, PPC::S22 },
3816 { 1223U, PPC::S23 },
3817 { 1224U, PPC::S24 },
3818 { 1225U, PPC::S25 },
3819 { 1226U, PPC::S26 },
3820 { 1227U, PPC::S27 },
3821 { 1228U, PPC::S28 },
3822 { 1229U, PPC::S29 },
3823 { 1230U, PPC::S30 },
3824 { 1231U, PPC::S31 },
3825};
3826extern const unsigned PPCEHFlavour1Dwarf2LSize = std::size(PPCEHFlavour1Dwarf2L);
3827
3828extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[] = {
3829 { PPC::CARRY, 76U },
3830 { PPC::CTR, -2U },
3831 { PPC::LR, -2U },
3832 { PPC::SPEFSCR, 612U },
3833 { PPC::VRSAVE, 109U },
3834 { PPC::XER, 76U },
3835 { PPC::ZERO, -2U },
3836 { PPC::CR0, 68U },
3837 { PPC::CR1, 69U },
3838 { PPC::CR2, 70U },
3839 { PPC::CR3, 71U },
3840 { PPC::CR4, 72U },
3841 { PPC::CR5, 73U },
3842 { PPC::CR6, 74U },
3843 { PPC::CR7, 75U },
3844 { PPC::CTR8, 66U },
3845 { PPC::F0, 32U },
3846 { PPC::F1, 33U },
3847 { PPC::F2, 34U },
3848 { PPC::F3, 35U },
3849 { PPC::F4, 36U },
3850 { PPC::F5, 37U },
3851 { PPC::F6, 38U },
3852 { PPC::F7, 39U },
3853 { PPC::F8, 40U },
3854 { PPC::F9, 41U },
3855 { PPC::F10, 42U },
3856 { PPC::F11, 43U },
3857 { PPC::F12, 44U },
3858 { PPC::F13, 45U },
3859 { PPC::F14, 46U },
3860 { PPC::F15, 47U },
3861 { PPC::F16, 48U },
3862 { PPC::F17, 49U },
3863 { PPC::F18, 50U },
3864 { PPC::F19, 51U },
3865 { PPC::F20, 52U },
3866 { PPC::F21, 53U },
3867 { PPC::F22, 54U },
3868 { PPC::F23, 55U },
3869 { PPC::F24, 56U },
3870 { PPC::F25, 57U },
3871 { PPC::F26, 58U },
3872 { PPC::F27, 59U },
3873 { PPC::F28, 60U },
3874 { PPC::F29, 61U },
3875 { PPC::F30, 62U },
3876 { PPC::F31, 63U },
3877 { PPC::LR8, 65U },
3878 { PPC::R0, -2U },
3879 { PPC::R1, -2U },
3880 { PPC::R2, -2U },
3881 { PPC::R3, -2U },
3882 { PPC::R4, -2U },
3883 { PPC::R5, -2U },
3884 { PPC::R6, -2U },
3885 { PPC::R7, -2U },
3886 { PPC::R8, -2U },
3887 { PPC::R9, -2U },
3888 { PPC::R10, -2U },
3889 { PPC::R11, -2U },
3890 { PPC::R12, -2U },
3891 { PPC::R13, -2U },
3892 { PPC::R14, -2U },
3893 { PPC::R15, -2U },
3894 { PPC::R16, -2U },
3895 { PPC::R17, -2U },
3896 { PPC::R18, -2U },
3897 { PPC::R19, -2U },
3898 { PPC::R20, -2U },
3899 { PPC::R21, -2U },
3900 { PPC::R22, -2U },
3901 { PPC::R23, -2U },
3902 { PPC::R24, -2U },
3903 { PPC::R25, -2U },
3904 { PPC::R26, -2U },
3905 { PPC::R27, -2U },
3906 { PPC::R28, -2U },
3907 { PPC::R29, -2U },
3908 { PPC::R30, -2U },
3909 { PPC::R31, -2U },
3910 { PPC::S0, 1200U },
3911 { PPC::S1, 1201U },
3912 { PPC::S2, 1202U },
3913 { PPC::S3, 1203U },
3914 { PPC::S4, 1204U },
3915 { PPC::S5, 1205U },
3916 { PPC::S6, 1206U },
3917 { PPC::S7, 1207U },
3918 { PPC::S8, 1208U },
3919 { PPC::S9, 1209U },
3920 { PPC::S10, 1210U },
3921 { PPC::S11, 1211U },
3922 { PPC::S12, 1212U },
3923 { PPC::S13, 1213U },
3924 { PPC::S14, 1214U },
3925 { PPC::S15, 1215U },
3926 { PPC::S16, 1216U },
3927 { PPC::S17, 1217U },
3928 { PPC::S18, 1218U },
3929 { PPC::S19, 1219U },
3930 { PPC::S20, 1220U },
3931 { PPC::S21, 1221U },
3932 { PPC::S22, 1222U },
3933 { PPC::S23, 1223U },
3934 { PPC::S24, 1224U },
3935 { PPC::S25, 1225U },
3936 { PPC::S26, 1226U },
3937 { PPC::S27, 1227U },
3938 { PPC::S28, 1228U },
3939 { PPC::S29, 1229U },
3940 { PPC::S30, 1230U },
3941 { PPC::S31, 1231U },
3942 { PPC::V0, 77U },
3943 { PPC::V1, 78U },
3944 { PPC::V2, 79U },
3945 { PPC::V3, 80U },
3946 { PPC::V4, 81U },
3947 { PPC::V5, 82U },
3948 { PPC::V6, 83U },
3949 { PPC::V7, 84U },
3950 { PPC::V8, 85U },
3951 { PPC::V9, 86U },
3952 { PPC::V10, 87U },
3953 { PPC::V11, 88U },
3954 { PPC::V12, 89U },
3955 { PPC::V13, 90U },
3956 { PPC::V14, 91U },
3957 { PPC::V15, 92U },
3958 { PPC::V16, 93U },
3959 { PPC::V17, 94U },
3960 { PPC::V18, 95U },
3961 { PPC::V19, 96U },
3962 { PPC::V20, 97U },
3963 { PPC::V21, 98U },
3964 { PPC::V22, 99U },
3965 { PPC::V23, 100U },
3966 { PPC::V24, 101U },
3967 { PPC::V25, 102U },
3968 { PPC::V26, 103U },
3969 { PPC::V27, 104U },
3970 { PPC::V28, 105U },
3971 { PPC::V29, 106U },
3972 { PPC::V30, 107U },
3973 { PPC::V31, 108U },
3974 { PPC::VF0, 77U },
3975 { PPC::VF1, 78U },
3976 { PPC::VF2, 79U },
3977 { PPC::VF3, 80U },
3978 { PPC::VF4, 81U },
3979 { PPC::VF5, 82U },
3980 { PPC::VF6, 83U },
3981 { PPC::VF7, 84U },
3982 { PPC::VF8, 85U },
3983 { PPC::VF9, 86U },
3984 { PPC::VF10, 87U },
3985 { PPC::VF11, 88U },
3986 { PPC::VF12, 89U },
3987 { PPC::VF13, 90U },
3988 { PPC::VF14, 91U },
3989 { PPC::VF15, 92U },
3990 { PPC::VF16, 93U },
3991 { PPC::VF17, 94U },
3992 { PPC::VF18, 95U },
3993 { PPC::VF19, 96U },
3994 { PPC::VF20, 97U },
3995 { PPC::VF21, 98U },
3996 { PPC::VF22, 99U },
3997 { PPC::VF23, 100U },
3998 { PPC::VF24, 101U },
3999 { PPC::VF25, 102U },
4000 { PPC::VF26, 103U },
4001 { PPC::VF27, 104U },
4002 { PPC::VF28, 105U },
4003 { PPC::VF29, 106U },
4004 { PPC::VF30, 107U },
4005 { PPC::VF31, 108U },
4006 { PPC::VSL0, 32U },
4007 { PPC::VSL1, 33U },
4008 { PPC::VSL2, 34U },
4009 { PPC::VSL3, 35U },
4010 { PPC::VSL4, 36U },
4011 { PPC::VSL5, 37U },
4012 { PPC::VSL6, 38U },
4013 { PPC::VSL7, 39U },
4014 { PPC::VSL8, 40U },
4015 { PPC::VSL9, 41U },
4016 { PPC::VSL10, 42U },
4017 { PPC::VSL11, 43U },
4018 { PPC::VSL12, 44U },
4019 { PPC::VSL13, 45U },
4020 { PPC::VSL14, 46U },
4021 { PPC::VSL15, 47U },
4022 { PPC::VSL16, 48U },
4023 { PPC::VSL17, 49U },
4024 { PPC::VSL18, 50U },
4025 { PPC::VSL19, 51U },
4026 { PPC::VSL20, 52U },
4027 { PPC::VSL21, 53U },
4028 { PPC::VSL22, 54U },
4029 { PPC::VSL23, 55U },
4030 { PPC::VSL24, 56U },
4031 { PPC::VSL25, 57U },
4032 { PPC::VSL26, 58U },
4033 { PPC::VSL27, 59U },
4034 { PPC::VSL28, 60U },
4035 { PPC::VSL29, 61U },
4036 { PPC::VSL30, 62U },
4037 { PPC::VSL31, 63U },
4038 { PPC::VSRp16, 77U },
4039 { PPC::VSRp17, 79U },
4040 { PPC::VSRp18, 81U },
4041 { PPC::VSRp19, 83U },
4042 { PPC::VSRp20, 85U },
4043 { PPC::VSRp21, 87U },
4044 { PPC::VSRp22, 89U },
4045 { PPC::VSRp23, 91U },
4046 { PPC::VSRp24, 93U },
4047 { PPC::VSRp25, 95U },
4048 { PPC::VSRp26, 97U },
4049 { PPC::VSRp27, 99U },
4050 { PPC::VSRp28, 101U },
4051 { PPC::VSRp29, 103U },
4052 { PPC::VSRp30, 105U },
4053 { PPC::VSRp31, 107U },
4054 { PPC::X0, 0U },
4055 { PPC::X1, 1U },
4056 { PPC::X2, 2U },
4057 { PPC::X3, 3U },
4058 { PPC::X4, 4U },
4059 { PPC::X5, 5U },
4060 { PPC::X6, 6U },
4061 { PPC::X7, 7U },
4062 { PPC::X8, 8U },
4063 { PPC::X9, 9U },
4064 { PPC::X10, 10U },
4065 { PPC::X11, 11U },
4066 { PPC::X12, 12U },
4067 { PPC::X13, 13U },
4068 { PPC::X14, 14U },
4069 { PPC::X15, 15U },
4070 { PPC::X16, 16U },
4071 { PPC::X17, 17U },
4072 { PPC::X18, 18U },
4073 { PPC::X19, 19U },
4074 { PPC::X20, 20U },
4075 { PPC::X21, 21U },
4076 { PPC::X22, 22U },
4077 { PPC::X23, 23U },
4078 { PPC::X24, 24U },
4079 { PPC::X25, 25U },
4080 { PPC::X26, 26U },
4081 { PPC::X27, 27U },
4082 { PPC::X28, 28U },
4083 { PPC::X29, 29U },
4084 { PPC::X30, 30U },
4085 { PPC::X31, 31U },
4086 { PPC::ZERO8, 0U },
4087};
4088extern const unsigned PPCDwarfFlavour0L2DwarfSize = std::size(PPCDwarfFlavour0L2Dwarf);
4089
4090extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[] = {
4091 { PPC::CTR, 66U },
4092 { PPC::LR, 65U },
4093 { PPC::SPEFSCR, 112U },
4094 { PPC::ZERO, 0U },
4095 { PPC::CR0, 68U },
4096 { PPC::CR1, 69U },
4097 { PPC::CR2, 70U },
4098 { PPC::CR3, 71U },
4099 { PPC::CR4, 72U },
4100 { PPC::CR5, 73U },
4101 { PPC::CR6, 74U },
4102 { PPC::CR7, 75U },
4103 { PPC::CTR8, -2U },
4104 { PPC::F0, 32U },
4105 { PPC::F1, 33U },
4106 { PPC::F2, 34U },
4107 { PPC::F3, 35U },
4108 { PPC::F4, 36U },
4109 { PPC::F5, 37U },
4110 { PPC::F6, 38U },
4111 { PPC::F7, 39U },
4112 { PPC::F8, 40U },
4113 { PPC::F9, 41U },
4114 { PPC::F10, 42U },
4115 { PPC::F11, 43U },
4116 { PPC::F12, 44U },
4117 { PPC::F13, 45U },
4118 { PPC::F14, 46U },
4119 { PPC::F15, 47U },
4120 { PPC::F16, 48U },
4121 { PPC::F17, 49U },
4122 { PPC::F18, 50U },
4123 { PPC::F19, 51U },
4124 { PPC::F20, 52U },
4125 { PPC::F21, 53U },
4126 { PPC::F22, 54U },
4127 { PPC::F23, 55U },
4128 { PPC::F24, 56U },
4129 { PPC::F25, 57U },
4130 { PPC::F26, 58U },
4131 { PPC::F27, 59U },
4132 { PPC::F28, 60U },
4133 { PPC::F29, 61U },
4134 { PPC::F30, 62U },
4135 { PPC::F31, 63U },
4136 { PPC::LR8, -2U },
4137 { PPC::R0, 0U },
4138 { PPC::R1, 1U },
4139 { PPC::R2, 2U },
4140 { PPC::R3, 3U },
4141 { PPC::R4, 4U },
4142 { PPC::R5, 5U },
4143 { PPC::R6, 6U },
4144 { PPC::R7, 7U },
4145 { PPC::R8, 8U },
4146 { PPC::R9, 9U },
4147 { PPC::R10, 10U },
4148 { PPC::R11, 11U },
4149 { PPC::R12, 12U },
4150 { PPC::R13, 13U },
4151 { PPC::R14, 14U },
4152 { PPC::R15, 15U },
4153 { PPC::R16, 16U },
4154 { PPC::R17, 17U },
4155 { PPC::R18, 18U },
4156 { PPC::R19, 19U },
4157 { PPC::R20, 20U },
4158 { PPC::R21, 21U },
4159 { PPC::R22, 22U },
4160 { PPC::R23, 23U },
4161 { PPC::R24, 24U },
4162 { PPC::R25, 25U },
4163 { PPC::R26, 26U },
4164 { PPC::R27, 27U },
4165 { PPC::R28, 28U },
4166 { PPC::R29, 29U },
4167 { PPC::R30, 30U },
4168 { PPC::R31, 31U },
4169 { PPC::S0, 1200U },
4170 { PPC::S1, 1201U },
4171 { PPC::S2, 1202U },
4172 { PPC::S3, 1203U },
4173 { PPC::S4, 1204U },
4174 { PPC::S5, 1205U },
4175 { PPC::S6, 1206U },
4176 { PPC::S7, 1207U },
4177 { PPC::S8, 1208U },
4178 { PPC::S9, 1209U },
4179 { PPC::S10, 1210U },
4180 { PPC::S11, 1211U },
4181 { PPC::S12, 1212U },
4182 { PPC::S13, 1213U },
4183 { PPC::S14, 1214U },
4184 { PPC::S15, 1215U },
4185 { PPC::S16, 1216U },
4186 { PPC::S17, 1217U },
4187 { PPC::S18, 1218U },
4188 { PPC::S19, 1219U },
4189 { PPC::S20, 1220U },
4190 { PPC::S21, 1221U },
4191 { PPC::S22, 1222U },
4192 { PPC::S23, 1223U },
4193 { PPC::S24, 1224U },
4194 { PPC::S25, 1225U },
4195 { PPC::S26, 1226U },
4196 { PPC::S27, 1227U },
4197 { PPC::S28, 1228U },
4198 { PPC::S29, 1229U },
4199 { PPC::S30, 1230U },
4200 { PPC::S31, 1231U },
4201 { PPC::V0, 77U },
4202 { PPC::V1, 78U },
4203 { PPC::V2, 79U },
4204 { PPC::V3, 80U },
4205 { PPC::V4, 81U },
4206 { PPC::V5, 82U },
4207 { PPC::V6, 83U },
4208 { PPC::V7, 84U },
4209 { PPC::V8, 85U },
4210 { PPC::V9, 86U },
4211 { PPC::V10, 87U },
4212 { PPC::V11, 88U },
4213 { PPC::V12, 89U },
4214 { PPC::V13, 90U },
4215 { PPC::V14, 91U },
4216 { PPC::V15, 92U },
4217 { PPC::V16, 93U },
4218 { PPC::V17, 94U },
4219 { PPC::V18, 95U },
4220 { PPC::V19, 96U },
4221 { PPC::V20, 97U },
4222 { PPC::V21, 98U },
4223 { PPC::V22, 99U },
4224 { PPC::V23, 100U },
4225 { PPC::V24, 101U },
4226 { PPC::V25, 102U },
4227 { PPC::V26, 103U },
4228 { PPC::V27, 104U },
4229 { PPC::V28, 105U },
4230 { PPC::V29, 106U },
4231 { PPC::V30, 107U },
4232 { PPC::V31, 108U },
4233 { PPC::VF0, 77U },
4234 { PPC::VF1, 78U },
4235 { PPC::VF2, 79U },
4236 { PPC::VF3, 80U },
4237 { PPC::VF4, 81U },
4238 { PPC::VF5, 82U },
4239 { PPC::VF6, 83U },
4240 { PPC::VF7, 84U },
4241 { PPC::VF8, 85U },
4242 { PPC::VF9, 86U },
4243 { PPC::VF10, 87U },
4244 { PPC::VF11, 88U },
4245 { PPC::VF12, 89U },
4246 { PPC::VF13, 90U },
4247 { PPC::VF14, 91U },
4248 { PPC::VF15, 92U },
4249 { PPC::VF16, 93U },
4250 { PPC::VF17, 94U },
4251 { PPC::VF18, 95U },
4252 { PPC::VF19, 96U },
4253 { PPC::VF20, 97U },
4254 { PPC::VF21, 98U },
4255 { PPC::VF22, 99U },
4256 { PPC::VF23, 100U },
4257 { PPC::VF24, 101U },
4258 { PPC::VF25, 102U },
4259 { PPC::VF26, 103U },
4260 { PPC::VF27, 104U },
4261 { PPC::VF28, 105U },
4262 { PPC::VF29, 106U },
4263 { PPC::VF30, 107U },
4264 { PPC::VF31, 108U },
4265 { PPC::VSL0, 32U },
4266 { PPC::VSL1, 33U },
4267 { PPC::VSL2, 34U },
4268 { PPC::VSL3, 35U },
4269 { PPC::VSL4, 36U },
4270 { PPC::VSL5, 37U },
4271 { PPC::VSL6, 38U },
4272 { PPC::VSL7, 39U },
4273 { PPC::VSL8, 40U },
4274 { PPC::VSL9, 41U },
4275 { PPC::VSL10, 42U },
4276 { PPC::VSL11, 43U },
4277 { PPC::VSL12, 44U },
4278 { PPC::VSL13, 45U },
4279 { PPC::VSL14, 46U },
4280 { PPC::VSL15, 47U },
4281 { PPC::VSL16, 48U },
4282 { PPC::VSL17, 49U },
4283 { PPC::VSL18, 50U },
4284 { PPC::VSL19, 51U },
4285 { PPC::VSL20, 52U },
4286 { PPC::VSL21, 53U },
4287 { PPC::VSL22, 54U },
4288 { PPC::VSL23, 55U },
4289 { PPC::VSL24, 56U },
4290 { PPC::VSL25, 57U },
4291 { PPC::VSL26, 58U },
4292 { PPC::VSL27, 59U },
4293 { PPC::VSL28, 60U },
4294 { PPC::VSL29, 61U },
4295 { PPC::VSL30, 62U },
4296 { PPC::VSL31, 63U },
4297 { PPC::VSRp16, 77U },
4298 { PPC::VSRp17, 79U },
4299 { PPC::VSRp18, 81U },
4300 { PPC::VSRp19, 83U },
4301 { PPC::VSRp20, 85U },
4302 { PPC::VSRp21, 87U },
4303 { PPC::VSRp22, 89U },
4304 { PPC::VSRp23, 91U },
4305 { PPC::VSRp24, 93U },
4306 { PPC::VSRp25, 95U },
4307 { PPC::VSRp26, 97U },
4308 { PPC::VSRp27, 99U },
4309 { PPC::VSRp28, 101U },
4310 { PPC::VSRp29, 103U },
4311 { PPC::VSRp30, 105U },
4312 { PPC::VSRp31, 107U },
4313 { PPC::X0, -2U },
4314 { PPC::X1, -2U },
4315 { PPC::X2, -2U },
4316 { PPC::X3, -2U },
4317 { PPC::X4, -2U },
4318 { PPC::X5, -2U },
4319 { PPC::X6, -2U },
4320 { PPC::X7, -2U },
4321 { PPC::X8, -2U },
4322 { PPC::X9, -2U },
4323 { PPC::X10, -2U },
4324 { PPC::X11, -2U },
4325 { PPC::X12, -2U },
4326 { PPC::X13, -2U },
4327 { PPC::X14, -2U },
4328 { PPC::X15, -2U },
4329 { PPC::X16, -2U },
4330 { PPC::X17, -2U },
4331 { PPC::X18, -2U },
4332 { PPC::X19, -2U },
4333 { PPC::X20, -2U },
4334 { PPC::X21, -2U },
4335 { PPC::X22, -2U },
4336 { PPC::X23, -2U },
4337 { PPC::X24, -2U },
4338 { PPC::X25, -2U },
4339 { PPC::X26, -2U },
4340 { PPC::X27, -2U },
4341 { PPC::X28, -2U },
4342 { PPC::X29, -2U },
4343 { PPC::X30, -2U },
4344 { PPC::X31, -2U },
4345 { PPC::ZERO8, -2U },
4346};
4347extern const unsigned PPCDwarfFlavour1L2DwarfSize = std::size(PPCDwarfFlavour1L2Dwarf);
4348
4349extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[] = {
4350 { PPC::CARRY, 76U },
4351 { PPC::CTR, -2U },
4352 { PPC::LR, -2U },
4353 { PPC::SPEFSCR, 612U },
4354 { PPC::VRSAVE, 109U },
4355 { PPC::XER, 76U },
4356 { PPC::ZERO, -2U },
4357 { PPC::CR0, 68U },
4358 { PPC::CR1, 69U },
4359 { PPC::CR2, 70U },
4360 { PPC::CR3, 71U },
4361 { PPC::CR4, 72U },
4362 { PPC::CR5, 73U },
4363 { PPC::CR6, 74U },
4364 { PPC::CR7, 75U },
4365 { PPC::CTR8, 66U },
4366 { PPC::F0, 32U },
4367 { PPC::F1, 33U },
4368 { PPC::F2, 34U },
4369 { PPC::F3, 35U },
4370 { PPC::F4, 36U },
4371 { PPC::F5, 37U },
4372 { PPC::F6, 38U },
4373 { PPC::F7, 39U },
4374 { PPC::F8, 40U },
4375 { PPC::F9, 41U },
4376 { PPC::F10, 42U },
4377 { PPC::F11, 43U },
4378 { PPC::F12, 44U },
4379 { PPC::F13, 45U },
4380 { PPC::F14, 46U },
4381 { PPC::F15, 47U },
4382 { PPC::F16, 48U },
4383 { PPC::F17, 49U },
4384 { PPC::F18, 50U },
4385 { PPC::F19, 51U },
4386 { PPC::F20, 52U },
4387 { PPC::F21, 53U },
4388 { PPC::F22, 54U },
4389 { PPC::F23, 55U },
4390 { PPC::F24, 56U },
4391 { PPC::F25, 57U },
4392 { PPC::F26, 58U },
4393 { PPC::F27, 59U },
4394 { PPC::F28, 60U },
4395 { PPC::F29, 61U },
4396 { PPC::F30, 62U },
4397 { PPC::F31, 63U },
4398 { PPC::LR8, 65U },
4399 { PPC::R0, -2U },
4400 { PPC::R1, -2U },
4401 { PPC::R2, -2U },
4402 { PPC::R3, -2U },
4403 { PPC::R4, -2U },
4404 { PPC::R5, -2U },
4405 { PPC::R6, -2U },
4406 { PPC::R7, -2U },
4407 { PPC::R8, -2U },
4408 { PPC::R9, -2U },
4409 { PPC::R10, -2U },
4410 { PPC::R11, -2U },
4411 { PPC::R12, -2U },
4412 { PPC::R13, -2U },
4413 { PPC::R14, -2U },
4414 { PPC::R15, -2U },
4415 { PPC::R16, -2U },
4416 { PPC::R17, -2U },
4417 { PPC::R18, -2U },
4418 { PPC::R19, -2U },
4419 { PPC::R20, -2U },
4420 { PPC::R21, -2U },
4421 { PPC::R22, -2U },
4422 { PPC::R23, -2U },
4423 { PPC::R24, -2U },
4424 { PPC::R25, -2U },
4425 { PPC::R26, -2U },
4426 { PPC::R27, -2U },
4427 { PPC::R28, -2U },
4428 { PPC::R29, -2U },
4429 { PPC::R30, -2U },
4430 { PPC::R31, -2U },
4431 { PPC::S0, 1200U },
4432 { PPC::S1, 1201U },
4433 { PPC::S2, 1202U },
4434 { PPC::S3, 1203U },
4435 { PPC::S4, 1204U },
4436 { PPC::S5, 1205U },
4437 { PPC::S6, 1206U },
4438 { PPC::S7, 1207U },
4439 { PPC::S8, 1208U },
4440 { PPC::S9, 1209U },
4441 { PPC::S10, 1210U },
4442 { PPC::S11, 1211U },
4443 { PPC::S12, 1212U },
4444 { PPC::S13, 1213U },
4445 { PPC::S14, 1214U },
4446 { PPC::S15, 1215U },
4447 { PPC::S16, 1216U },
4448 { PPC::S17, 1217U },
4449 { PPC::S18, 1218U },
4450 { PPC::S19, 1219U },
4451 { PPC::S20, 1220U },
4452 { PPC::S21, 1221U },
4453 { PPC::S22, 1222U },
4454 { PPC::S23, 1223U },
4455 { PPC::S24, 1224U },
4456 { PPC::S25, 1225U },
4457 { PPC::S26, 1226U },
4458 { PPC::S27, 1227U },
4459 { PPC::S28, 1228U },
4460 { PPC::S29, 1229U },
4461 { PPC::S30, 1230U },
4462 { PPC::S31, 1231U },
4463 { PPC::V0, 77U },
4464 { PPC::V1, 78U },
4465 { PPC::V2, 79U },
4466 { PPC::V3, 80U },
4467 { PPC::V4, 81U },
4468 { PPC::V5, 82U },
4469 { PPC::V6, 83U },
4470 { PPC::V7, 84U },
4471 { PPC::V8, 85U },
4472 { PPC::V9, 86U },
4473 { PPC::V10, 87U },
4474 { PPC::V11, 88U },
4475 { PPC::V12, 89U },
4476 { PPC::V13, 90U },
4477 { PPC::V14, 91U },
4478 { PPC::V15, 92U },
4479 { PPC::V16, 93U },
4480 { PPC::V17, 94U },
4481 { PPC::V18, 95U },
4482 { PPC::V19, 96U },
4483 { PPC::V20, 97U },
4484 { PPC::V21, 98U },
4485 { PPC::V22, 99U },
4486 { PPC::V23, 100U },
4487 { PPC::V24, 101U },
4488 { PPC::V25, 102U },
4489 { PPC::V26, 103U },
4490 { PPC::V27, 104U },
4491 { PPC::V28, 105U },
4492 { PPC::V29, 106U },
4493 { PPC::V30, 107U },
4494 { PPC::V31, 108U },
4495 { PPC::VF0, 77U },
4496 { PPC::VF1, 78U },
4497 { PPC::VF2, 79U },
4498 { PPC::VF3, 80U },
4499 { PPC::VF4, 81U },
4500 { PPC::VF5, 82U },
4501 { PPC::VF6, 83U },
4502 { PPC::VF7, 84U },
4503 { PPC::VF8, 85U },
4504 { PPC::VF9, 86U },
4505 { PPC::VF10, 87U },
4506 { PPC::VF11, 88U },
4507 { PPC::VF12, 89U },
4508 { PPC::VF13, 90U },
4509 { PPC::VF14, 91U },
4510 { PPC::VF15, 92U },
4511 { PPC::VF16, 93U },
4512 { PPC::VF17, 94U },
4513 { PPC::VF18, 95U },
4514 { PPC::VF19, 96U },
4515 { PPC::VF20, 97U },
4516 { PPC::VF21, 98U },
4517 { PPC::VF22, 99U },
4518 { PPC::VF23, 100U },
4519 { PPC::VF24, 101U },
4520 { PPC::VF25, 102U },
4521 { PPC::VF26, 103U },
4522 { PPC::VF27, 104U },
4523 { PPC::VF28, 105U },
4524 { PPC::VF29, 106U },
4525 { PPC::VF30, 107U },
4526 { PPC::VF31, 108U },
4527 { PPC::VSL0, 32U },
4528 { PPC::VSL1, 33U },
4529 { PPC::VSL2, 34U },
4530 { PPC::VSL3, 35U },
4531 { PPC::VSL4, 36U },
4532 { PPC::VSL5, 37U },
4533 { PPC::VSL6, 38U },
4534 { PPC::VSL7, 39U },
4535 { PPC::VSL8, 40U },
4536 { PPC::VSL9, 41U },
4537 { PPC::VSL10, 42U },
4538 { PPC::VSL11, 43U },
4539 { PPC::VSL12, 44U },
4540 { PPC::VSL13, 45U },
4541 { PPC::VSL14, 46U },
4542 { PPC::VSL15, 47U },
4543 { PPC::VSL16, 48U },
4544 { PPC::VSL17, 49U },
4545 { PPC::VSL18, 50U },
4546 { PPC::VSL19, 51U },
4547 { PPC::VSL20, 52U },
4548 { PPC::VSL21, 53U },
4549 { PPC::VSL22, 54U },
4550 { PPC::VSL23, 55U },
4551 { PPC::VSL24, 56U },
4552 { PPC::VSL25, 57U },
4553 { PPC::VSL26, 58U },
4554 { PPC::VSL27, 59U },
4555 { PPC::VSL28, 60U },
4556 { PPC::VSL29, 61U },
4557 { PPC::VSL30, 62U },
4558 { PPC::VSL31, 63U },
4559 { PPC::VSRp16, 77U },
4560 { PPC::VSRp17, 79U },
4561 { PPC::VSRp18, 81U },
4562 { PPC::VSRp19, 83U },
4563 { PPC::VSRp20, 85U },
4564 { PPC::VSRp21, 87U },
4565 { PPC::VSRp22, 89U },
4566 { PPC::VSRp23, 91U },
4567 { PPC::VSRp24, 93U },
4568 { PPC::VSRp25, 95U },
4569 { PPC::VSRp26, 97U },
4570 { PPC::VSRp27, 99U },
4571 { PPC::VSRp28, 101U },
4572 { PPC::VSRp29, 103U },
4573 { PPC::VSRp30, 105U },
4574 { PPC::VSRp31, 107U },
4575 { PPC::X0, 0U },
4576 { PPC::X1, 1U },
4577 { PPC::X2, 2U },
4578 { PPC::X3, 3U },
4579 { PPC::X4, 4U },
4580 { PPC::X5, 5U },
4581 { PPC::X6, 6U },
4582 { PPC::X7, 7U },
4583 { PPC::X8, 8U },
4584 { PPC::X9, 9U },
4585 { PPC::X10, 10U },
4586 { PPC::X11, 11U },
4587 { PPC::X12, 12U },
4588 { PPC::X13, 13U },
4589 { PPC::X14, 14U },
4590 { PPC::X15, 15U },
4591 { PPC::X16, 16U },
4592 { PPC::X17, 17U },
4593 { PPC::X18, 18U },
4594 { PPC::X19, 19U },
4595 { PPC::X20, 20U },
4596 { PPC::X21, 21U },
4597 { PPC::X22, 22U },
4598 { PPC::X23, 23U },
4599 { PPC::X24, 24U },
4600 { PPC::X25, 25U },
4601 { PPC::X26, 26U },
4602 { PPC::X27, 27U },
4603 { PPC::X28, 28U },
4604 { PPC::X29, 29U },
4605 { PPC::X30, 30U },
4606 { PPC::X31, 31U },
4607 { PPC::ZERO8, 0U },
4608};
4609extern const unsigned PPCEHFlavour0L2DwarfSize = std::size(PPCEHFlavour0L2Dwarf);
4610
4611extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[] = {
4612 { PPC::CTR, 66U },
4613 { PPC::LR, 65U },
4614 { PPC::SPEFSCR, 112U },
4615 { PPC::ZERO, 0U },
4616 { PPC::CR0, 68U },
4617 { PPC::CR1, 69U },
4618 { PPC::CR2, 70U },
4619 { PPC::CR3, 71U },
4620 { PPC::CR4, 72U },
4621 { PPC::CR5, 73U },
4622 { PPC::CR6, 74U },
4623 { PPC::CR7, 75U },
4624 { PPC::CTR8, -2U },
4625 { PPC::F0, 32U },
4626 { PPC::F1, 33U },
4627 { PPC::F2, 34U },
4628 { PPC::F3, 35U },
4629 { PPC::F4, 36U },
4630 { PPC::F5, 37U },
4631 { PPC::F6, 38U },
4632 { PPC::F7, 39U },
4633 { PPC::F8, 40U },
4634 { PPC::F9, 41U },
4635 { PPC::F10, 42U },
4636 { PPC::F11, 43U },
4637 { PPC::F12, 44U },
4638 { PPC::F13, 45U },
4639 { PPC::F14, 46U },
4640 { PPC::F15, 47U },
4641 { PPC::F16, 48U },
4642 { PPC::F17, 49U },
4643 { PPC::F18, 50U },
4644 { PPC::F19, 51U },
4645 { PPC::F20, 52U },
4646 { PPC::F21, 53U },
4647 { PPC::F22, 54U },
4648 { PPC::F23, 55U },
4649 { PPC::F24, 56U },
4650 { PPC::F25, 57U },
4651 { PPC::F26, 58U },
4652 { PPC::F27, 59U },
4653 { PPC::F28, 60U },
4654 { PPC::F29, 61U },
4655 { PPC::F30, 62U },
4656 { PPC::F31, 63U },
4657 { PPC::LR8, -2U },
4658 { PPC::R0, 0U },
4659 { PPC::R1, 1U },
4660 { PPC::R2, 2U },
4661 { PPC::R3, 3U },
4662 { PPC::R4, 4U },
4663 { PPC::R5, 5U },
4664 { PPC::R6, 6U },
4665 { PPC::R7, 7U },
4666 { PPC::R8, 8U },
4667 { PPC::R9, 9U },
4668 { PPC::R10, 10U },
4669 { PPC::R11, 11U },
4670 { PPC::R12, 12U },
4671 { PPC::R13, 13U },
4672 { PPC::R14, 14U },
4673 { PPC::R15, 15U },
4674 { PPC::R16, 16U },
4675 { PPC::R17, 17U },
4676 { PPC::R18, 18U },
4677 { PPC::R19, 19U },
4678 { PPC::R20, 20U },
4679 { PPC::R21, 21U },
4680 { PPC::R22, 22U },
4681 { PPC::R23, 23U },
4682 { PPC::R24, 24U },
4683 { PPC::R25, 25U },
4684 { PPC::R26, 26U },
4685 { PPC::R27, 27U },
4686 { PPC::R28, 28U },
4687 { PPC::R29, 29U },
4688 { PPC::R30, 30U },
4689 { PPC::R31, 31U },
4690 { PPC::S0, 1200U },
4691 { PPC::S1, 1201U },
4692 { PPC::S2, 1202U },
4693 { PPC::S3, 1203U },
4694 { PPC::S4, 1204U },
4695 { PPC::S5, 1205U },
4696 { PPC::S6, 1206U },
4697 { PPC::S7, 1207U },
4698 { PPC::S8, 1208U },
4699 { PPC::S9, 1209U },
4700 { PPC::S10, 1210U },
4701 { PPC::S11, 1211U },
4702 { PPC::S12, 1212U },
4703 { PPC::S13, 1213U },
4704 { PPC::S14, 1214U },
4705 { PPC::S15, 1215U },
4706 { PPC::S16, 1216U },
4707 { PPC::S17, 1217U },
4708 { PPC::S18, 1218U },
4709 { PPC::S19, 1219U },
4710 { PPC::S20, 1220U },
4711 { PPC::S21, 1221U },
4712 { PPC::S22, 1222U },
4713 { PPC::S23, 1223U },
4714 { PPC::S24, 1224U },
4715 { PPC::S25, 1225U },
4716 { PPC::S26, 1226U },
4717 { PPC::S27, 1227U },
4718 { PPC::S28, 1228U },
4719 { PPC::S29, 1229U },
4720 { PPC::S30, 1230U },
4721 { PPC::S31, 1231U },
4722 { PPC::V0, 77U },
4723 { PPC::V1, 78U },
4724 { PPC::V2, 79U },
4725 { PPC::V3, 80U },
4726 { PPC::V4, 81U },
4727 { PPC::V5, 82U },
4728 { PPC::V6, 83U },
4729 { PPC::V7, 84U },
4730 { PPC::V8, 85U },
4731 { PPC::V9, 86U },
4732 { PPC::V10, 87U },
4733 { PPC::V11, 88U },
4734 { PPC::V12, 89U },
4735 { PPC::V13, 90U },
4736 { PPC::V14, 91U },
4737 { PPC::V15, 92U },
4738 { PPC::V16, 93U },
4739 { PPC::V17, 94U },
4740 { PPC::V18, 95U },
4741 { PPC::V19, 96U },
4742 { PPC::V20, 97U },
4743 { PPC::V21, 98U },
4744 { PPC::V22, 99U },
4745 { PPC::V23, 100U },
4746 { PPC::V24, 101U },
4747 { PPC::V25, 102U },
4748 { PPC::V26, 103U },
4749 { PPC::V27, 104U },
4750 { PPC::V28, 105U },
4751 { PPC::V29, 106U },
4752 { PPC::V30, 107U },
4753 { PPC::V31, 108U },
4754 { PPC::VF0, 77U },
4755 { PPC::VF1, 78U },
4756 { PPC::VF2, 79U },
4757 { PPC::VF3, 80U },
4758 { PPC::VF4, 81U },
4759 { PPC::VF5, 82U },
4760 { PPC::VF6, 83U },
4761 { PPC::VF7, 84U },
4762 { PPC::VF8, 85U },
4763 { PPC::VF9, 86U },
4764 { PPC::VF10, 87U },
4765 { PPC::VF11, 88U },
4766 { PPC::VF12, 89U },
4767 { PPC::VF13, 90U },
4768 { PPC::VF14, 91U },
4769 { PPC::VF15, 92U },
4770 { PPC::VF16, 93U },
4771 { PPC::VF17, 94U },
4772 { PPC::VF18, 95U },
4773 { PPC::VF19, 96U },
4774 { PPC::VF20, 97U },
4775 { PPC::VF21, 98U },
4776 { PPC::VF22, 99U },
4777 { PPC::VF23, 100U },
4778 { PPC::VF24, 101U },
4779 { PPC::VF25, 102U },
4780 { PPC::VF26, 103U },
4781 { PPC::VF27, 104U },
4782 { PPC::VF28, 105U },
4783 { PPC::VF29, 106U },
4784 { PPC::VF30, 107U },
4785 { PPC::VF31, 108U },
4786 { PPC::VSL0, 32U },
4787 { PPC::VSL1, 33U },
4788 { PPC::VSL2, 34U },
4789 { PPC::VSL3, 35U },
4790 { PPC::VSL4, 36U },
4791 { PPC::VSL5, 37U },
4792 { PPC::VSL6, 38U },
4793 { PPC::VSL7, 39U },
4794 { PPC::VSL8, 40U },
4795 { PPC::VSL9, 41U },
4796 { PPC::VSL10, 42U },
4797 { PPC::VSL11, 43U },
4798 { PPC::VSL12, 44U },
4799 { PPC::VSL13, 45U },
4800 { PPC::VSL14, 46U },
4801 { PPC::VSL15, 47U },
4802 { PPC::VSL16, 48U },
4803 { PPC::VSL17, 49U },
4804 { PPC::VSL18, 50U },
4805 { PPC::VSL19, 51U },
4806 { PPC::VSL20, 52U },
4807 { PPC::VSL21, 53U },
4808 { PPC::VSL22, 54U },
4809 { PPC::VSL23, 55U },
4810 { PPC::VSL24, 56U },
4811 { PPC::VSL25, 57U },
4812 { PPC::VSL26, 58U },
4813 { PPC::VSL27, 59U },
4814 { PPC::VSL28, 60U },
4815 { PPC::VSL29, 61U },
4816 { PPC::VSL30, 62U },
4817 { PPC::VSL31, 63U },
4818 { PPC::VSRp16, 77U },
4819 { PPC::VSRp17, 79U },
4820 { PPC::VSRp18, 81U },
4821 { PPC::VSRp19, 83U },
4822 { PPC::VSRp20, 85U },
4823 { PPC::VSRp21, 87U },
4824 { PPC::VSRp22, 89U },
4825 { PPC::VSRp23, 91U },
4826 { PPC::VSRp24, 93U },
4827 { PPC::VSRp25, 95U },
4828 { PPC::VSRp26, 97U },
4829 { PPC::VSRp27, 99U },
4830 { PPC::VSRp28, 101U },
4831 { PPC::VSRp29, 103U },
4832 { PPC::VSRp30, 105U },
4833 { PPC::VSRp31, 107U },
4834 { PPC::X0, -2U },
4835 { PPC::X1, -2U },
4836 { PPC::X2, -2U },
4837 { PPC::X3, -2U },
4838 { PPC::X4, -2U },
4839 { PPC::X5, -2U },
4840 { PPC::X6, -2U },
4841 { PPC::X7, -2U },
4842 { PPC::X8, -2U },
4843 { PPC::X9, -2U },
4844 { PPC::X10, -2U },
4845 { PPC::X11, -2U },
4846 { PPC::X12, -2U },
4847 { PPC::X13, -2U },
4848 { PPC::X14, -2U },
4849 { PPC::X15, -2U },
4850 { PPC::X16, -2U },
4851 { PPC::X17, -2U },
4852 { PPC::X18, -2U },
4853 { PPC::X19, -2U },
4854 { PPC::X20, -2U },
4855 { PPC::X21, -2U },
4856 { PPC::X22, -2U },
4857 { PPC::X23, -2U },
4858 { PPC::X24, -2U },
4859 { PPC::X25, -2U },
4860 { PPC::X26, -2U },
4861 { PPC::X27, -2U },
4862 { PPC::X28, -2U },
4863 { PPC::X29, -2U },
4864 { PPC::X30, -2U },
4865 { PPC::X31, -2U },
4866 { PPC::ZERO8, -2U },
4867};
4868extern const unsigned PPCEHFlavour1L2DwarfSize = std::size(PPCEHFlavour1L2Dwarf);
4869
4870extern const uint16_t PPCRegEncodingTable[] = {
4871 0,
4872 0,
4873 1,
4874 9,
4875 0,
4876 8,
4877 0,
4878 512,
4879 256,
4880 1,
4881 0,
4882 0,
4883 1,
4884 2,
4885 3,
4886 4,
4887 5,
4888 6,
4889 7,
4890 0,
4891 0,
4892 1,
4893 2,
4894 3,
4895 4,
4896 5,
4897 6,
4898 7,
4899 9,
4900 0,
4901 1,
4902 2,
4903 3,
4904 4,
4905 5,
4906 6,
4907 7,
4908 0,
4909 1,
4910 2,
4911 3,
4912 4,
4913 5,
4914 6,
4915 7,
4916 8,
4917 9,
4918 10,
4919 11,
4920 12,
4921 13,
4922 14,
4923 15,
4924 16,
4925 17,
4926 18,
4927 19,
4928 20,
4929 21,
4930 22,
4931 23,
4932 24,
4933 25,
4934 26,
4935 27,
4936 28,
4937 29,
4938 30,
4939 31,
4940 32,
4941 33,
4942 34,
4943 35,
4944 36,
4945 37,
4946 38,
4947 39,
4948 40,
4949 41,
4950 42,
4951 43,
4952 44,
4953 45,
4954 46,
4955 47,
4956 48,
4957 49,
4958 50,
4959 51,
4960 52,
4961 53,
4962 54,
4963 55,
4964 56,
4965 57,
4966 58,
4967 59,
4968 60,
4969 61,
4970 62,
4971 63,
4972 0,
4973 1,
4974 2,
4975 3,
4976 4,
4977 5,
4978 6,
4979 7,
4980 8,
4981 9,
4982 10,
4983 11,
4984 12,
4985 13,
4986 14,
4987 15,
4988 16,
4989 17,
4990 18,
4991 19,
4992 20,
4993 21,
4994 22,
4995 23,
4996 24,
4997 25,
4998 26,
4999 27,
5000 28,
5001 29,
5002 30,
5003 31,
5004 0,
5005 1,
5006 2,
5007 3,
5008 0,
5009 1,
5010 2,
5011 3,
5012 4,
5013 5,
5014 6,
5015 7,
5016 8,
5017 9,
5018 10,
5019 11,
5020 12,
5021 13,
5022 14,
5023 15,
5024 16,
5025 17,
5026 18,
5027 19,
5028 20,
5029 21,
5030 22,
5031 23,
5032 24,
5033 25,
5034 26,
5035 27,
5036 28,
5037 29,
5038 30,
5039 31,
5040 31,
5041 31,
5042 31,
5043 31,
5044 31,
5045 31,
5046 31,
5047 31,
5048 31,
5049 31,
5050 31,
5051 31,
5052 31,
5053 31,
5054 31,
5055 31,
5056 31,
5057 31,
5058 31,
5059 31,
5060 31,
5061 31,
5062 31,
5063 31,
5064 31,
5065 31,
5066 31,
5067 31,
5068 31,
5069 31,
5070 31,
5071 31,
5072 0,
5073 0,
5074 2,
5075 4,
5076 6,
5077 8,
5078 10,
5079 12,
5080 14,
5081 16,
5082 18,
5083 20,
5084 22,
5085 24,
5086 26,
5087 28,
5088 30,
5089 31,
5090 31,
5091 31,
5092 31,
5093 31,
5094 31,
5095 31,
5096 31,
5097 31,
5098 31,
5099 31,
5100 31,
5101 31,
5102 31,
5103 31,
5104 31,
5105 31,
5106 31,
5107 31,
5108 31,
5109 31,
5110 31,
5111 31,
5112 31,
5113 31,
5114 31,
5115 31,
5116 31,
5117 31,
5118 31,
5119 31,
5120 31,
5121 8,
5122 0,
5123 1,
5124 2,
5125 3,
5126 4,
5127 5,
5128 6,
5129 7,
5130 8,
5131 9,
5132 10,
5133 11,
5134 12,
5135 13,
5136 14,
5137 15,
5138 16,
5139 17,
5140 18,
5141 19,
5142 20,
5143 21,
5144 22,
5145 23,
5146 24,
5147 25,
5148 26,
5149 27,
5150 28,
5151 29,
5152 30,
5153 31,
5154 0,
5155 1,
5156 2,
5157 3,
5158 4,
5159 5,
5160 6,
5161 7,
5162 8,
5163 9,
5164 10,
5165 11,
5166 12,
5167 13,
5168 14,
5169 15,
5170 16,
5171 17,
5172 18,
5173 19,
5174 20,
5175 21,
5176 22,
5177 23,
5178 24,
5179 25,
5180 26,
5181 27,
5182 28,
5183 29,
5184 30,
5185 31,
5186 0,
5187 1,
5188 2,
5189 3,
5190 4,
5191 5,
5192 6,
5193 7,
5194 0,
5195 1,
5196 2,
5197 3,
5198 4,
5199 5,
5200 6,
5201 7,
5202 8,
5203 9,
5204 10,
5205 11,
5206 12,
5207 13,
5208 14,
5209 15,
5210 16,
5211 17,
5212 18,
5213 19,
5214 20,
5215 21,
5216 22,
5217 23,
5218 24,
5219 25,
5220 26,
5221 27,
5222 28,
5223 29,
5224 30,
5225 31,
5226 32,
5227 33,
5228 34,
5229 35,
5230 36,
5231 37,
5232 38,
5233 39,
5234 40,
5235 41,
5236 42,
5237 43,
5238 44,
5239 45,
5240 46,
5241 47,
5242 48,
5243 49,
5244 50,
5245 51,
5246 52,
5247 53,
5248 54,
5249 55,
5250 56,
5251 57,
5252 58,
5253 59,
5254 60,
5255 61,
5256 62,
5257 63,
5258 63,
5259 63,
5260 63,
5261 63,
5262 63,
5263 63,
5264 63,
5265 63,
5266 63,
5267 63,
5268 63,
5269 63,
5270 63,
5271 63,
5272 63,
5273 63,
5274 63,
5275 63,
5276 63,
5277 63,
5278 63,
5279 63,
5280 63,
5281 63,
5282 63,
5283 63,
5284 63,
5285 63,
5286 63,
5287 63,
5288 63,
5289 63,
5290 0,
5291 1,
5292 2,
5293 3,
5294 4,
5295 5,
5296 6,
5297 7,
5298 8,
5299 9,
5300 10,
5301 11,
5302 12,
5303 13,
5304 14,
5305 15,
5306 16,
5307 17,
5308 18,
5309 19,
5310 20,
5311 21,
5312 22,
5313 23,
5314 24,
5315 25,
5316 26,
5317 27,
5318 28,
5319 29,
5320 30,
5321 31,
5322 0,
5323 1,
5324 2,
5325 3,
5326 4,
5327 5,
5328 6,
5329 7,
5330 8,
5331 9,
5332 10,
5333 11,
5334 12,
5335 13,
5336 14,
5337 15,
5338 16,
5339 17,
5340 18,
5341 19,
5342 20,
5343 21,
5344 22,
5345 23,
5346 24,
5347 25,
5348 26,
5349 27,
5350 28,
5351 29,
5352 30,
5353 31,
5354 32,
5355 33,
5356 34,
5357 35,
5358 36,
5359 37,
5360 38,
5361 39,
5362 40,
5363 41,
5364 42,
5365 43,
5366 44,
5367 45,
5368 46,
5369 47,
5370 48,
5371 49,
5372 50,
5373 51,
5374 52,
5375 53,
5376 54,
5377 55,
5378 56,
5379 57,
5380 58,
5381 59,
5382 60,
5383 61,
5384 62,
5385 63,
5386 0,
5387 1,
5388 2,
5389 3,
5390 4,
5391 5,
5392 6,
5393 7,
5394 0,
5395 1,
5396 2,
5397 3,
5398 4,
5399 5,
5400 6,
5401 7,
5402 0,
5403 1,
5404 2,
5405 3,
5406 4,
5407 5,
5408 6,
5409 7,
5410 8,
5411 9,
5412 10,
5413 11,
5414 12,
5415 13,
5416 14,
5417 15,
5418 16,
5419 17,
5420 18,
5421 19,
5422 20,
5423 21,
5424 22,
5425 23,
5426 24,
5427 25,
5428 26,
5429 27,
5430 28,
5431 29,
5432 30,
5433 31,
5434 0,
5435 2,
5436 6,
5437 10,
5438 14,
5439 18,
5440 22,
5441 26,
5442 30,
5443 1,
5444 5,
5445 9,
5446 13,
5447 17,
5448 21,
5449 25,
5450 29,
5451 0,
5452 4,
5453 8,
5454 12,
5455 16,
5456 20,
5457 24,
5458 28,
5459 3,
5460 7,
5461 11,
5462 15,
5463 19,
5464 23,
5465 27,
5466 31,
5467 0,
5468 2,
5469 4,
5470 6,
5471 8,
5472 10,
5473 12,
5474 14,
5475 16,
5476 18,
5477 20,
5478 22,
5479 24,
5480 26,
5481 28,
5482 30,
5483};
5484static inline void InitPPCMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
5485 RI->InitMCRegisterInfo(PPCRegDesc, 612, RA, PC, PPCMCRegisterClasses, 56, PPCRegUnitRoots, 335, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, PPCSubRegIdxLists, 56,
5486PPCRegEncodingTable);
5487
5488 switch (DwarfFlavour) {
5489 default:
5490 llvm_unreachable("Unknown DWARF flavour");
5491 case 0:
5492 RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
5493 break;
5494 case 1:
5495 RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
5496 break;
5497 }
5498 switch (EHFlavour) {
5499 default:
5500 llvm_unreachable("Unknown DWARF flavour");
5501 case 0:
5502 RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
5503 break;
5504 case 1:
5505 RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
5506 break;
5507 }
5508 switch (DwarfFlavour) {
5509 default:
5510 llvm_unreachable("Unknown DWARF flavour");
5511 case 0:
5512 RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
5513 break;
5514 case 1:
5515 RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
5516 break;
5517 }
5518 switch (EHFlavour) {
5519 default:
5520 llvm_unreachable("Unknown DWARF flavour");
5521 case 0:
5522 RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
5523 break;
5524 case 1:
5525 RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
5526 break;
5527 }
5528}
5529
5530} // end namespace llvm
5531
5532#endif // GET_REGINFO_MC_DESC
5533
5534/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5535|* *|
5536|* Register Information Header Fragment *|
5537|* *|
5538|* Automatically generated file, do not edit! *|
5539|* *|
5540\*===----------------------------------------------------------------------===*/
5541
5542
5543#ifdef GET_REGINFO_HEADER
5544#undef GET_REGINFO_HEADER
5545
5546#include "llvm/CodeGen/TargetRegisterInfo.h"
5547
5548namespace llvm {
5549
5550class PPCFrameLowering;
5551
5552struct PPCGenRegisterInfo : public TargetRegisterInfo {
5553 explicit PPCGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
5554 unsigned PC = 0, unsigned HwMode = 0);
5555 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
5556 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
5557 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5558 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5559 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
5560 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
5561 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5562 unsigned getRegUnitWeight(unsigned RegUnit) const override;
5563 unsigned getNumRegPressureSets() const override;
5564 const char *getRegPressureSetName(unsigned Idx) const override;
5565 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
5566 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5567 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5568 ArrayRef<const char *> getRegMaskNames() const override;
5569 ArrayRef<const uint32_t *> getRegMasks() const override;
5570 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
5571 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
5572 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
5573 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
5574 bool isConstantPhysReg(MCRegister PhysReg) const override final;
5575 /// Devirtualized TargetFrameLowering.
5576 static const PPCFrameLowering *getFrameLowering(
5577 const MachineFunction &MF);
5578};
5579
5580namespace PPC { // Register classes
5581 extern const TargetRegisterClass VSSRCRegClass;
5582 extern const TargetRegisterClass GPRCRegClass;
5583 extern const TargetRegisterClass GPRC_NOR0RegClass;
5584 extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass;
5585 extern const TargetRegisterClass CRBITRCRegClass;
5586 extern const TargetRegisterClass F4RCRegClass;
5587 extern const TargetRegisterClass GPRC32RegClass;
5588 extern const TargetRegisterClass CRRCRegClass;
5589 extern const TargetRegisterClass CARRYRCRegClass;
5590 extern const TargetRegisterClass CTRRCRegClass;
5591 extern const TargetRegisterClass LRRCRegClass;
5592 extern const TargetRegisterClass VRSAVERCRegClass;
5593 extern const TargetRegisterClass SPILLTOVSRRCRegClass;
5594 extern const TargetRegisterClass VSFRCRegClass;
5595 extern const TargetRegisterClass G8RCRegClass;
5596 extern const TargetRegisterClass G8RC_NOX0RegClass;
5597 extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass;
5598 extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass;
5599 extern const TargetRegisterClass F8RCRegClass;
5600 extern const TargetRegisterClass FHRCRegClass;
5601 extern const TargetRegisterClass SPERCRegClass;
5602 extern const TargetRegisterClass VFHRCRegClass;
5603 extern const TargetRegisterClass VFRCRegClass;
5604 extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass;
5605 extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass;
5606 extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass;
5607 extern const TargetRegisterClass CTRRC8RegClass;
5608 extern const TargetRegisterClass LR8RCRegClass;
5609 extern const TargetRegisterClass DMRROWRCRegClass;
5610 extern const TargetRegisterClass VSRCRegClass;
5611 extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5612 extern const TargetRegisterClass VRRCRegClass;
5613 extern const TargetRegisterClass VSLRCRegClass;
5614 extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5615 extern const TargetRegisterClass FpRCRegClass;
5616 extern const TargetRegisterClass G8pRCRegClass;
5617 extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass;
5618 extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5619 extern const TargetRegisterClass FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass;
5620 extern const TargetRegisterClass DMRROWpRCRegClass;
5621 extern const TargetRegisterClass VSRpRCRegClass;
5622 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5623 extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass;
5624 extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass;
5625 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass;
5626 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass;
5627 extern const TargetRegisterClass ACCRCRegClass;
5628 extern const TargetRegisterClass UACCRCRegClass;
5629 extern const TargetRegisterClass WACCRCRegClass;
5630 extern const TargetRegisterClass WACC_HIRCRegClass;
5631 extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5632 extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
5633 extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
5634 extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
5635 extern const TargetRegisterClass DMRRCRegClass;
5636 extern const TargetRegisterClass DMRpRCRegClass;
5637} // end namespace PPC
5638
5639} // end namespace llvm
5640
5641#endif // GET_REGINFO_HEADER
5642
5643/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5644|* *|
5645|* Target Register and Register Classes Information *|
5646|* *|
5647|* Automatically generated file, do not edit! *|
5648|* *|
5649\*===----------------------------------------------------------------------===*/
5650
5651
5652#ifdef GET_REGINFO_TARGET_DESC
5653#undef GET_REGINFO_TARGET_DESC
5654
5655namespace llvm {
5656
5657extern const MCRegisterClass PPCMCRegisterClasses[];
5658
5659static const MVT::SimpleValueType VTLists[] = {
5660 /* 0 */ MVT::i1, MVT::Other,
5661 /* 2 */ MVT::i32, MVT::Other,
5662 /* 4 */ MVT::i64, MVT::Other,
5663 /* 6 */ MVT::i128, MVT::Other,
5664 /* 8 */ MVT::i32, MVT::f32, MVT::Other,
5665 /* 11 */ MVT::i64, MVT::f64, MVT::Other,
5666 /* 14 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v1i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
5667 /* 23 */ MVT::ppcf128, MVT::Other,
5668 /* 25 */ MVT::v128i1, MVT::Other,
5669 /* 27 */ MVT::v256i1, MVT::Other,
5670 /* 29 */ MVT::v512i1, MVT::Other,
5671 /* 31 */ MVT::v1024i1, MVT::Other,
5672 /* 33 */ MVT::v2048i1, MVT::Other,
5673 /* 35 */ MVT::v4i32, MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::Other,
5674};
5675
5676static const char *SubRegIndexNameTable[] = { "sub_32", "sub_32_hi_phony", "sub_64", "sub_64_hi_phony", "sub_dmr0", "sub_dmr1", "sub_dmrrow0", "sub_dmrrow1", "sub_dmrrowp0", "sub_dmrrowp1", "sub_eq", "sub_fp0", "sub_fp1", "sub_gp8_x0", "sub_gp8_x1", "sub_gt", "sub_lt", "sub_pair0", "sub_pair1", "sub_un", "sub_vsx0", "sub_vsx1", "sub_wacc_hi", "sub_wacc_lo", "sub_vsx1_then_sub_64", "sub_vsx1_then_sub_64_hi_phony", "sub_pair1_then_sub_64", "sub_pair1_then_sub_64_hi_phony", "sub_pair1_then_sub_vsx0", "sub_pair1_then_sub_vsx1", "sub_pair1_then_sub_vsx1_then_sub_64", "sub_pair1_then_sub_vsx1_then_sub_64_hi_phony", "sub_dmrrowp1_then_sub_dmrrow0", "sub_dmrrowp1_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrowp0", "sub_wacc_hi_then_sub_dmrrowp1", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrowp0", "sub_dmr1_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi", "sub_dmr1_then_sub_wacc_lo", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_gp8_x1_then_sub_32", "" };
5677
5678static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
5679 { 65535, 65535 },
5680 { 0, 32 }, // sub_32
5681 { 32, 32 }, // sub_32_hi_phony
5682 { 0, 64 }, // sub_64
5683 { 64, 64 }, // sub_64_hi_phony
5684 { 0, 1024 }, // sub_dmr0
5685 { 1024, 1024 }, // sub_dmr1
5686 { 0, 128 }, // sub_dmrrow0
5687 { 128, 128 }, // sub_dmrrow1
5688 { 0, 256 }, // sub_dmrrowp0
5689 { 256, 256 }, // sub_dmrrowp1
5690 { 2, 1 }, // sub_eq
5691 { 0, 64 }, // sub_fp0
5692 { 64, 64 }, // sub_fp1
5693 { 0, 64 }, // sub_gp8_x0
5694 { 64, 64 }, // sub_gp8_x1
5695 { 1, 1 }, // sub_gt
5696 { 0, 1 }, // sub_lt
5697 { 0, 256 }, // sub_pair0
5698 { 256, 256 }, // sub_pair1
5699 { 3, 1 }, // sub_un
5700 { 0, 128 }, // sub_vsx0
5701 { 128, 128 }, // sub_vsx1
5702 { 512, 512 }, // sub_wacc_hi
5703 { 0, 512 }, // sub_wacc_lo
5704 { 128, 64 }, // sub_vsx1_then_sub_64
5705 { 192, 64 }, // sub_vsx1_then_sub_64_hi_phony
5706 { 256, 64 }, // sub_pair1_then_sub_64
5707 { 320, 64 }, // sub_pair1_then_sub_64_hi_phony
5708 { 256, 128 }, // sub_pair1_then_sub_vsx0
5709 { 384, 128 }, // sub_pair1_then_sub_vsx1
5710 { 384, 64 }, // sub_pair1_then_sub_vsx1_then_sub_64
5711 { 448, 64 }, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
5712 { 256, 128 }, // sub_dmrrowp1_then_sub_dmrrow0
5713 { 384, 128 }, // sub_dmrrowp1_then_sub_dmrrow1
5714 { 512, 128 }, // sub_wacc_hi_then_sub_dmrrow0
5715 { 640, 128 }, // sub_wacc_hi_then_sub_dmrrow1
5716 { 512, 256 }, // sub_wacc_hi_then_sub_dmrrowp0
5717 { 768, 256 }, // sub_wacc_hi_then_sub_dmrrowp1
5718 { 768, 128 }, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5719 { 896, 128 }, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5720 { 1024, 128 }, // sub_dmr1_then_sub_dmrrow0
5721 { 1152, 128 }, // sub_dmr1_then_sub_dmrrow1
5722 { 1024, 256 }, // sub_dmr1_then_sub_dmrrowp0
5723 { 1280, 256 }, // sub_dmr1_then_sub_dmrrowp1
5724 { 1536, 512 }, // sub_dmr1_then_sub_wacc_hi
5725 { 1024, 512 }, // sub_dmr1_then_sub_wacc_lo
5726 { 1280, 128 }, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
5727 { 1408, 128 }, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
5728 { 1536, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
5729 { 1664, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
5730 { 1536, 256 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
5731 { 1792, 256 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
5732 { 1792, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5733 { 1920, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5734 { 64, 32 }, // sub_gp8_x1_then_sub_32
5735};
5736
5737
5738static const LaneBitmask SubRegIndexLaneMaskTable[] = {
5739 LaneBitmask::getAll(),
5740 LaneBitmask(0x0000000000000001), // sub_32
5741 LaneBitmask(0x0000000000000002), // sub_32_hi_phony
5742 LaneBitmask(0x0000000000000004), // sub_64
5743 LaneBitmask(0x0000000000000008), // sub_64_hi_phony
5744 LaneBitmask(0x0000000000FC0030), // sub_dmr0
5745 LaneBitmask(0x00000000FF000000), // sub_dmr1
5746 LaneBitmask(0x0000000000000010), // sub_dmrrow0
5747 LaneBitmask(0x0000000000000020), // sub_dmrrow1
5748 LaneBitmask(0x0000000000000030), // sub_dmrrowp0
5749 LaneBitmask(0x00000000000C0000), // sub_dmrrowp1
5750 LaneBitmask(0x0000000000000040), // sub_eq
5751 LaneBitmask(0x0000000000000080), // sub_fp0
5752 LaneBitmask(0x0000000000000100), // sub_fp1
5753 LaneBitmask(0x0000000000000001), // sub_gp8_x0
5754 LaneBitmask(0x0000000100000000), // sub_gp8_x1
5755 LaneBitmask(0x0000000000000200), // sub_gt
5756 LaneBitmask(0x0000000000000400), // sub_lt
5757 LaneBitmask(0x000000000000300C), // sub_pair0
5758 LaneBitmask(0x000000000003C000), // sub_pair1
5759 LaneBitmask(0x0000000000000800), // sub_un
5760 LaneBitmask(0x000000000000000C), // sub_vsx0
5761 LaneBitmask(0x0000000000003000), // sub_vsx1
5762 LaneBitmask(0x0000000000F00000), // sub_wacc_hi
5763 LaneBitmask(0x00000000000C0030), // sub_wacc_lo
5764 LaneBitmask(0x0000000000001000), // sub_vsx1_then_sub_64
5765 LaneBitmask(0x0000000000002000), // sub_vsx1_then_sub_64_hi_phony
5766 LaneBitmask(0x0000000000004000), // sub_pair1_then_sub_64
5767 LaneBitmask(0x0000000000008000), // sub_pair1_then_sub_64_hi_phony
5768 LaneBitmask(0x000000000000C000), // sub_pair1_then_sub_vsx0
5769 LaneBitmask(0x0000000000030000), // sub_pair1_then_sub_vsx1
5770 LaneBitmask(0x0000000000010000), // sub_pair1_then_sub_vsx1_then_sub_64
5771 LaneBitmask(0x0000000000020000), // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
5772 LaneBitmask(0x0000000000040000), // sub_dmrrowp1_then_sub_dmrrow0
5773 LaneBitmask(0x0000000000080000), // sub_dmrrowp1_then_sub_dmrrow1
5774 LaneBitmask(0x0000000000100000), // sub_wacc_hi_then_sub_dmrrow0
5775 LaneBitmask(0x0000000000200000), // sub_wacc_hi_then_sub_dmrrow1
5776 LaneBitmask(0x0000000000300000), // sub_wacc_hi_then_sub_dmrrowp0
5777 LaneBitmask(0x0000000000C00000), // sub_wacc_hi_then_sub_dmrrowp1
5778 LaneBitmask(0x0000000000400000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5779 LaneBitmask(0x0000000000800000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5780 LaneBitmask(0x0000000001000000), // sub_dmr1_then_sub_dmrrow0
5781 LaneBitmask(0x0000000002000000), // sub_dmr1_then_sub_dmrrow1
5782 LaneBitmask(0x0000000003000000), // sub_dmr1_then_sub_dmrrowp0
5783 LaneBitmask(0x000000000C000000), // sub_dmr1_then_sub_dmrrowp1
5784 LaneBitmask(0x00000000F0000000), // sub_dmr1_then_sub_wacc_hi
5785 LaneBitmask(0x000000000F000000), // sub_dmr1_then_sub_wacc_lo
5786 LaneBitmask(0x0000000004000000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
5787 LaneBitmask(0x0000000008000000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
5788 LaneBitmask(0x0000000010000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
5789 LaneBitmask(0x0000000020000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
5790 LaneBitmask(0x0000000030000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
5791 LaneBitmask(0x00000000C0000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
5792 LaneBitmask(0x0000000040000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
5793 LaneBitmask(0x0000000080000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
5794 LaneBitmask(0x0000000100000000), // sub_gp8_x1_then_sub_32
5795 };
5796
5797
5798
5799static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
5800 // Mode = 0 (Default)
5801 { 32, 32, 32, /*VTLists+*/9 }, // VSSRC
5802 { 32, 32, 32, /*VTLists+*/8 }, // GPRC
5803 { 32, 32, 32, /*VTLists+*/8 }, // GPRC_NOR0
5804 { 32, 32, 32, /*VTLists+*/8 }, // GPRC_and_GPRC_NOR0
5805 { 32, 32, 32, /*VTLists+*/0 }, // CRBITRC
5806 { 32, 32, 32, /*VTLists+*/9 }, // F4RC
5807 { 32, 32, 32, /*VTLists+*/8 }, // GPRC32
5808 { 32, 32, 32, /*VTLists+*/2 }, // CRRC
5809 { 32, 32, 32, /*VTLists+*/2 }, // CARRYRC
5810 { 32, 32, 32, /*VTLists+*/2 }, // CTRRC
5811 { 32, 32, 32, /*VTLists+*/2 }, // LRRC
5812 { 32, 32, 32, /*VTLists+*/2 }, // VRSAVERC
5813 { 64, 64, 64, /*VTLists+*/11 }, // SPILLTOVSRRC
5814 { 64, 64, 64, /*VTLists+*/12 }, // VSFRC
5815 { 64, 64, 64, /*VTLists+*/4 }, // G8RC
5816 { 64, 64, 64, /*VTLists+*/4 }, // G8RC_NOX0
5817 { 64, 64, 64, /*VTLists+*/12 }, // SPILLTOVSRRC_and_VSFRC
5818 { 64, 64, 64, /*VTLists+*/4 }, // G8RC_and_G8RC_NOX0
5819 { 64, 64, 64, /*VTLists+*/12 }, // F8RC
5820 { 64, 64, 64, /*VTLists+*/12 }, // FHRC
5821 { 64, 64, 64, /*VTLists+*/12 }, // SPERC
5822 { 64, 64, 64, /*VTLists+*/12 }, // VFHRC
5823 { 64, 64, 64, /*VTLists+*/12 }, // VFRC
5824 { 64, 64, 64, /*VTLists+*/12 }, // SPERC_with_sub_32_in_GPRC_NOR0
5825 { 64, 64, 64, /*VTLists+*/12 }, // SPILLTOVSRRC_and_VFRC
5826 { 64, 64, 64, /*VTLists+*/12 }, // SPILLTOVSRRC_and_F4RC
5827 { 64, 64, 64, /*VTLists+*/4 }, // CTRRC8
5828 { 64, 64, 64, /*VTLists+*/4 }, // LR8RC
5829 { 128, 128, 128, /*VTLists+*/25 }, // DMRROWRC
5830 { 128, 128, 128, /*VTLists+*/35 }, // VSRC
5831 { 128, 128, 128, /*VTLists+*/35 }, // VSRC_with_sub_64_in_SPILLTOVSRRC
5832 { 128, 128, 128, /*VTLists+*/14 }, // VRRC
5833 { 128, 128, 128, /*VTLists+*/35 }, // VSLRC
5834 { 128, 128, 128, /*VTLists+*/14 }, // VRRC_with_sub_64_in_SPILLTOVSRRC
5835 { 128, 128, 128, /*VTLists+*/23 }, // FpRC
5836 { 128, 128, 128, /*VTLists+*/6 }, // G8pRC
5837 { 128, 128, 128, /*VTLists+*/6 }, // G8pRC_with_sub_32_in_GPRC_NOR0
5838 { 128, 128, 128, /*VTLists+*/35 }, // VSLRC_with_sub_64_in_SPILLTOVSRRC
5839 { 128, 128, 128, /*VTLists+*/23 }, // FpRC_with_sub_fp0_in_SPILLTOVSRRC
5840 { 256, 256, 128, /*VTLists+*/27 }, // DMRROWpRC
5841 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC
5842 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC
5843 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_F4RC
5844 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_VFRC
5845 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
5846 { 256, 256, 128, /*VTLists+*/27 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
5847 { 512, 512, 128, /*VTLists+*/29 }, // ACCRC
5848 { 512, 512, 128, /*VTLists+*/29 }, // UACCRC
5849 { 512, 512, 128, /*VTLists+*/29 }, // WACCRC
5850 { 512, 512, 128, /*VTLists+*/29 }, // WACC_HIRC
5851 { 512, 512, 128, /*VTLists+*/29 }, // ACCRC_with_sub_64_in_SPILLTOVSRRC
5852 { 512, 512, 128, /*VTLists+*/29 }, // UACCRC_with_sub_64_in_SPILLTOVSRRC
5853 { 512, 512, 128, /*VTLists+*/29 }, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
5854 { 512, 512, 128, /*VTLists+*/29 }, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
5855 { 1024, 1024, 128, /*VTLists+*/31 }, // DMRRC
5856 { 2048, 2048, 128, /*VTLists+*/33 }, // DMRpRC
5857};
5858static const uint32_t VSSRCSubClassMask[] = {
5859 0x03452021, 0x00000000,
5860 0xe0000000, 0x003cff23, // sub_64
5861 0x00000000, 0x00000044, // sub_fp0
5862 0x00000000, 0x00000044, // sub_fp1
5863 0x00000000, 0x003cff00, // sub_vsx1_then_sub_64
5864 0x00000000, 0x003cc000, // sub_pair1_then_sub_64
5865 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1_then_sub_64
5866};
5867
5868static const uint32_t GPRCSubClassMask[] = {
5869 0x0000000a, 0x00000000,
5870 0x00924000, 0x00000018, // sub_32
5871 0x00000000, 0x00000018, // sub_gp8_x1_then_sub_32
5872};
5873
5874static const uint32_t GPRC_NOR0SubClassMask[] = {
5875 0x0000000c, 0x00000000,
5876 0x00828000, 0x00000010, // sub_32
5877 0x00000000, 0x00000018, // sub_gp8_x1_then_sub_32
5878};
5879
5880static const uint32_t GPRC_and_GPRC_NOR0SubClassMask[] = {
5881 0x00000008, 0x00000000,
5882 0x00820000, 0x00000010, // sub_32
5883 0x00000000, 0x00000018, // sub_gp8_x1_then_sub_32
5884};
5885
5886static const uint32_t CRBITRCSubClassMask[] = {
5887 0x00000010, 0x00000000,
5888 0x00000080, 0x00000000, // sub_eq
5889 0x00000080, 0x00000000, // sub_gt
5890 0x00000080, 0x00000000, // sub_lt
5891 0x00000080, 0x00000000, // sub_un
5892};
5893
5894static const uint32_t F4RCSubClassMask[] = {
5895 0x02040020, 0x00000000,
5896 0x00000000, 0x003ce421, // sub_64
5897 0x00000000, 0x00000044, // sub_fp0
5898 0x00000000, 0x00000044, // sub_fp1
5899 0x00000000, 0x003ce400, // sub_vsx1_then_sub_64
5900 0x00000000, 0x003cc000, // sub_pair1_then_sub_64
5901 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1_then_sub_64
5902};
5903
5904static const uint32_t GPRC32SubClassMask[] = {
5905 0x00000040, 0x00000000,
5906};
5907
5908static const uint32_t CRRCSubClassMask[] = {
5909 0x00000080, 0x00000000,
5910};
5911
5912static const uint32_t CARRYRCSubClassMask[] = {
5913 0x00000100, 0x00000000,
5914};
5915
5916static const uint32_t CTRRCSubClassMask[] = {
5917 0x00000200, 0x00000000,
5918};
5919
5920static const uint32_t LRRCSubClassMask[] = {
5921 0x00000400, 0x00000000,
5922};
5923
5924static const uint32_t VRSAVERCSubClassMask[] = {
5925 0x00000800, 0x00000000,
5926};
5927
5928static const uint32_t SPILLTOVSRRCSubClassMask[] = {
5929 0x03035000, 0x00000000,
5930 0x40000000, 0x003c3222, // sub_64
5931 0x00000000, 0x00000040, // sub_fp0
5932 0x00000000, 0x00000040, // sub_fp1
5933 0x00000000, 0x00000018, // sub_gp8_x0
5934 0x00000000, 0x00000018, // sub_gp8_x1
5935 0x00000000, 0x003c3200, // sub_vsx1_then_sub_64
5936 0x00000000, 0x00300000, // sub_pair1_then_sub_64
5937 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1_then_sub_64
5938};
5939
5940static const uint32_t VSFRCSubClassMask[] = {
5941 0x03452000, 0x00000000,
5942 0xe0000000, 0x003cff23, // sub_64
5943 0x00000000, 0x00000044, // sub_fp0
5944 0x00000000, 0x00000044, // sub_fp1
5945 0x00000000, 0x003cff00, // sub_vsx1_then_sub_64
5946 0x00000000, 0x003cc000, // sub_pair1_then_sub_64
5947 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1_then_sub_64
5948};
5949
5950static const uint32_t G8RCSubClassMask[] = {
5951 0x00024000, 0x00000000,
5952 0x00000000, 0x00000018, // sub_gp8_x0
5953 0x00000000, 0x00000018, // sub_gp8_x1
5954};
5955
5956static const uint32_t G8RC_NOX0SubClassMask[] = {
5957 0x00028000, 0x00000000,
5958 0x00000000, 0x00000010, // sub_gp8_x0
5959 0x00000000, 0x00000018, // sub_gp8_x1
5960};
5961
5962static const uint32_t SPILLTOVSRRC_and_VSFRCSubClassMask[] = {
5963 0x03010000, 0x00000000,
5964 0x40000000, 0x003c3222, // sub_64
5965 0x00000000, 0x00000040, // sub_fp0
5966 0x00000000, 0x00000040, // sub_fp1
5967 0x00000000, 0x003c3200, // sub_vsx1_then_sub_64
5968 0x00000000, 0x00300000, // sub_pair1_then_sub_64
5969 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1_then_sub_64
5970};
5971
5972static const uint32_t G8RC_and_G8RC_NOX0SubClassMask[] = {
5973 0x00020000, 0x00000000,
5974 0x00000000, 0x00000010, // sub_gp8_x0
5975 0x00000000, 0x00000018, // sub_gp8_x1
5976};
5977
5978static const uint32_t F8RCSubClassMask[] = {
5979 0x02040000, 0x00000000,
5980 0x00000000, 0x003ce421, // sub_64
5981 0x00000000, 0x00000044, // sub_fp0
5982 0x00000000, 0x00000044, // sub_fp1
5983 0x00000000, 0x003ce400, // sub_vsx1_then_sub_64
5984 0x00000000, 0x003cc000, // sub_pair1_then_sub_64
5985 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1_then_sub_64
5986};
5987
5988static const uint32_t FHRCSubClassMask[] = {
5989 0x00080000, 0x00000000,
5990};
5991
5992static const uint32_t SPERCSubClassMask[] = {
5993 0x00900000, 0x00000000,
5994};
5995
5996static const uint32_t VFHRCSubClassMask[] = {
5997 0x00200000, 0x00000000,
5998};
5999
6000static const uint32_t VFRCSubClassMask[] = {
6001 0x01400000, 0x00000000,
6002 0x80000000, 0x00001802, // sub_64
6003 0x00000000, 0x00001800, // sub_vsx1_then_sub_64
6004};
6005
6006static const uint32_t SPERC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
6007 0x00800000, 0x00000000,
6008};
6009
6010static const uint32_t SPILLTOVSRRC_and_VFRCSubClassMask[] = {
6011 0x01000000, 0x00000000,
6012 0x00000000, 0x00001002, // sub_64
6013 0x00000000, 0x00001000, // sub_vsx1_then_sub_64
6014};
6015
6016static const uint32_t SPILLTOVSRRC_and_F4RCSubClassMask[] = {
6017 0x02000000, 0x00000000,
6018 0x00000000, 0x003c2020, // sub_64
6019 0x00000000, 0x00000040, // sub_fp0
6020 0x00000000, 0x00000040, // sub_fp1
6021 0x00000000, 0x003c2000, // sub_vsx1_then_sub_64
6022 0x00000000, 0x00300000, // sub_pair1_then_sub_64
6023 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1_then_sub_64
6024};
6025
6026static const uint32_t CTRRC8SubClassMask[] = {
6027 0x04000000, 0x00000000,
6028};
6029
6030static const uint32_t LR8RCSubClassMask[] = {
6031 0x08000000, 0x00000000,
6032};
6033
6034static const uint32_t DMRROWRCSubClassMask[] = {
6035 0x10000000, 0x00000000,
6036 0x00000000, 0x00c30080, // sub_dmrrow0
6037 0x00000000, 0x00c30080, // sub_dmrrow1
6038 0x00000000, 0x00c30000, // sub_dmrrowp1_then_sub_dmrrow0
6039 0x00000000, 0x00c30000, // sub_dmrrowp1_then_sub_dmrrow1
6040 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrow0
6041 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrow1
6042 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6043 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6044 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrow0
6045 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrow1
6046 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
6047 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
6048 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
6049 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
6050 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
6051 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
6052};
6053
6054static const uint32_t VSRCSubClassMask[] = {
6055 0xe0000000, 0x00000023,
6056 0x00000000, 0x003cff00, // sub_vsx0
6057 0x00000000, 0x003cff00, // sub_vsx1
6058 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx0
6059 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1
6060};
6061
6062static const uint32_t VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6063 0x40000000, 0x00000022,
6064 0x00000000, 0x003c3200, // sub_vsx0
6065 0x00000000, 0x003c3200, // sub_vsx1
6066 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx0
6067 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1
6068};
6069
6070static const uint32_t VRRCSubClassMask[] = {
6071 0x80000000, 0x00000002,
6072 0x00000000, 0x00001800, // sub_vsx0
6073 0x00000000, 0x00001800, // sub_vsx1
6074};
6075
6076static const uint32_t VSLRCSubClassMask[] = {
6077 0x00000000, 0x00000021,
6078 0x00000000, 0x003ce400, // sub_vsx0
6079 0x00000000, 0x003ce400, // sub_vsx1
6080 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx0
6081 0x00000000, 0x003cc000, // sub_pair1_then_sub_vsx1
6082};
6083
6084static const uint32_t VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6085 0x00000000, 0x00000002,
6086 0x00000000, 0x00001000, // sub_vsx0
6087 0x00000000, 0x00001000, // sub_vsx1
6088};
6089
6090static const uint32_t FpRCSubClassMask[] = {
6091 0x00000000, 0x00000044,
6092};
6093
6094static const uint32_t G8pRCSubClassMask[] = {
6095 0x00000000, 0x00000018,
6096};
6097
6098static const uint32_t G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
6099 0x00000000, 0x00000010,
6100};
6101
6102static const uint32_t VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6103 0x00000000, 0x00000020,
6104 0x00000000, 0x003c2000, // sub_vsx0
6105 0x00000000, 0x003c2000, // sub_vsx1
6106 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx0
6107 0x00000000, 0x00300000, // sub_pair1_then_sub_vsx1
6108};
6109
6110static const uint32_t FpRC_with_sub_fp0_in_SPILLTOVSRRCSubClassMask[] = {
6111 0x00000000, 0x00000040,
6112};
6113
6114static const uint32_t DMRROWpRCSubClassMask[] = {
6115 0x00000000, 0x00000080,
6116 0x00000000, 0x00c30000, // sub_dmrrowp0
6117 0x00000000, 0x00c30000, // sub_dmrrowp1
6118 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrowp0
6119 0x00000000, 0x00c00000, // sub_wacc_hi_then_sub_dmrrowp1
6120 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrowp0
6121 0x00000000, 0x00800000, // sub_dmr1_then_sub_dmrrowp1
6122 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
6123 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
6124};
6125
6126static const uint32_t VSRpRCSubClassMask[] = {
6127 0x00000000, 0x00003f00,
6128 0x00000000, 0x003cc000, // sub_pair0
6129 0x00000000, 0x003cc000, // sub_pair1
6130};
6131
6132static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6133 0x00000000, 0x00003200,
6134 0x00000000, 0x003c0000, // sub_pair0
6135 0x00000000, 0x00300000, // sub_pair1
6136};
6137
6138static const uint32_t VSRpRC_with_sub_64_in_F4RCSubClassMask[] = {
6139 0x00000000, 0x00002400,
6140 0x00000000, 0x003cc000, // sub_pair0
6141 0x00000000, 0x003cc000, // sub_pair1
6142};
6143
6144static const uint32_t VSRpRC_with_sub_64_in_VFRCSubClassMask[] = {
6145 0x00000000, 0x00001800,
6146};
6147
6148static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask[] = {
6149 0x00000000, 0x00001000,
6150};
6151
6152static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask[] = {
6153 0x00000000, 0x00002000,
6154 0x00000000, 0x003c0000, // sub_pair0
6155 0x00000000, 0x00300000, // sub_pair1
6156};
6157
6158static const uint32_t ACCRCSubClassMask[] = {
6159 0x00000000, 0x00144000,
6160};
6161
6162static const uint32_t UACCRCSubClassMask[] = {
6163 0x00000000, 0x00288000,
6164};
6165
6166static const uint32_t WACCRCSubClassMask[] = {
6167 0x00000000, 0x00010000,
6168 0x00000000, 0x00c00000, // sub_wacc_lo
6169 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_lo
6170};
6171
6172static const uint32_t WACC_HIRCSubClassMask[] = {
6173 0x00000000, 0x00020000,
6174 0x00000000, 0x00c00000, // sub_wacc_hi
6175 0x00000000, 0x00800000, // sub_dmr1_then_sub_wacc_hi
6176};
6177
6178static const uint32_t ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6179 0x00000000, 0x00140000,
6180};
6181
6182static const uint32_t UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6183 0x00000000, 0x00280000,
6184};
6185
6186static const uint32_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6187 0x00000000, 0x00100000,
6188};
6189
6190static const uint32_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
6191 0x00000000, 0x00200000,
6192};
6193
6194static const uint32_t DMRRCSubClassMask[] = {
6195 0x00000000, 0x00400000,
6196 0x00000000, 0x00800000, // sub_dmr0
6197 0x00000000, 0x00800000, // sub_dmr1
6198};
6199
6200static const uint32_t DMRpRCSubClassMask[] = {
6201 0x00000000, 0x00800000,
6202};
6203
6204static const uint16_t SuperRegIdxSeqs[] = {
6205 /* 0 */ 5, 6, 0,
6206 /* 3 */ 14, 15, 0,
6207 /* 6 */ 18, 19, 0,
6208 /* 9 */ 11, 16, 17, 20, 0,
6209 /* 14 */ 21, 22, 0,
6210 /* 17 */ 3, 25, 0,
6211 /* 20 */ 21, 22, 29, 30, 0,
6212 /* 25 */ 3, 12, 13, 25, 27, 31, 0,
6213 /* 32 */ 3, 12, 13, 14, 15, 25, 27, 31, 0,
6214 /* 41 */ 23, 45, 0,
6215 /* 44 */ 24, 46, 0,
6216 /* 47 */ 9, 10, 37, 38, 43, 44, 51, 52, 0,
6217 /* 56 */ 7, 8, 33, 34, 35, 36, 39, 40, 41, 42, 47, 48, 49, 50, 53, 54, 0,
6218 /* 73 */ 1, 55, 0,
6219};
6220
6221static unsigned const GPRC_and_GPRC_NOR0Superclasses[] = {
6222 PPC::GPRCRegClassID,
6223 PPC::GPRC_NOR0RegClassID,
6224};
6225
6226static unsigned const F4RCSuperclasses[] = {
6227 PPC::VSSRCRegClassID,
6228};
6229
6230static unsigned const VSFRCSuperclasses[] = {
6231 PPC::VSSRCRegClassID,
6232};
6233
6234static unsigned const G8RCSuperclasses[] = {
6235 PPC::SPILLTOVSRRCRegClassID,
6236};
6237
6238static unsigned const SPILLTOVSRRC_and_VSFRCSuperclasses[] = {
6239 PPC::VSSRCRegClassID,
6240 PPC::SPILLTOVSRRCRegClassID,
6241 PPC::VSFRCRegClassID,
6242};
6243
6244static unsigned const G8RC_and_G8RC_NOX0Superclasses[] = {
6245 PPC::SPILLTOVSRRCRegClassID,
6246 PPC::G8RCRegClassID,
6247 PPC::G8RC_NOX0RegClassID,
6248};
6249
6250static unsigned const F8RCSuperclasses[] = {
6251 PPC::VSSRCRegClassID,
6252 PPC::F4RCRegClassID,
6253 PPC::VSFRCRegClassID,
6254};
6255
6256static unsigned const VFRCSuperclasses[] = {
6257 PPC::VSSRCRegClassID,
6258 PPC::VSFRCRegClassID,
6259};
6260
6261static unsigned const SPERC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
6262 PPC::SPERCRegClassID,
6263};
6264
6265static unsigned const SPILLTOVSRRC_and_VFRCSuperclasses[] = {
6266 PPC::VSSRCRegClassID,
6267 PPC::SPILLTOVSRRCRegClassID,
6268 PPC::VSFRCRegClassID,
6269 PPC::SPILLTOVSRRC_and_VSFRCRegClassID,
6270 PPC::VFRCRegClassID,
6271};
6272
6273static unsigned const SPILLTOVSRRC_and_F4RCSuperclasses[] = {
6274 PPC::VSSRCRegClassID,
6275 PPC::F4RCRegClassID,
6276 PPC::SPILLTOVSRRCRegClassID,
6277 PPC::VSFRCRegClassID,
6278 PPC::SPILLTOVSRRC_and_VSFRCRegClassID,
6279 PPC::F8RCRegClassID,
6280};
6281
6282static unsigned const VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6283 PPC::VSRCRegClassID,
6284};
6285
6286static unsigned const VRRCSuperclasses[] = {
6287 PPC::VSRCRegClassID,
6288};
6289
6290static unsigned const VSLRCSuperclasses[] = {
6291 PPC::VSRCRegClassID,
6292};
6293
6294static unsigned const VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6295 PPC::VSRCRegClassID,
6296 PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID,
6297 PPC::VRRCRegClassID,
6298};
6299
6300static unsigned const G8pRC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
6301 PPC::G8pRCRegClassID,
6302};
6303
6304static unsigned const VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6305 PPC::VSRCRegClassID,
6306 PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID,
6307 PPC::VSLRCRegClassID,
6308};
6309
6310static unsigned const FpRC_with_sub_fp0_in_SPILLTOVSRRCSuperclasses[] = {
6311 PPC::FpRCRegClassID,
6312};
6313
6314static unsigned const VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6315 PPC::VSRpRCRegClassID,
6316};
6317
6318static unsigned const VSRpRC_with_sub_64_in_F4RCSuperclasses[] = {
6319 PPC::VSRpRCRegClassID,
6320};
6321
6322static unsigned const VSRpRC_with_sub_64_in_VFRCSuperclasses[] = {
6323 PPC::VSRpRCRegClassID,
6324};
6325
6326static unsigned const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses[] = {
6327 PPC::VSRpRCRegClassID,
6328 PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID,
6329 PPC::VSRpRC_with_sub_64_in_VFRCRegClassID,
6330};
6331
6332static unsigned const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses[] = {
6333 PPC::VSRpRCRegClassID,
6334 PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID,
6335 PPC::VSRpRC_with_sub_64_in_F4RCRegClassID,
6336};
6337
6338static unsigned const ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6339 PPC::ACCRCRegClassID,
6340};
6341
6342static unsigned const UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6343 PPC::UACCRCRegClassID,
6344};
6345
6346static unsigned const ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6347 PPC::ACCRCRegClassID,
6348 PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID,
6349};
6350
6351static unsigned const UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
6352 PPC::UACCRCRegClassID,
6353 PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID,
6354};
6355
6356
6357static inline unsigned GPRCAltOrderSelect(const MachineFunction &MF, bool Rev) {
6358 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6359 }
6360
6361static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6362 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
6363 static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R0, PPC::R1, PPC::FP, PPC::BP };
6364 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
6365 const ArrayRef<MCPhysReg> Order[] = {
6366 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6367 ArrayRef(AltOrder1),
6368 ArrayRef(AltOrder2)
6369 };
6370 const unsigned Select = GPRCAltOrderSelect(MF, Rev);
6371 assert(Select < 3);
6372 return Order[Select];
6373}
6374
6375static inline unsigned GPRC_NOR0AltOrderSelect(const MachineFunction &MF, bool Rev) {
6376 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6377 }
6378
6379static ArrayRef<MCPhysReg> GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6380 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, PPC::R2 };
6381 static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO };
6382 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID];
6383 const ArrayRef<MCPhysReg> Order[] = {
6384 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6385 ArrayRef(AltOrder1),
6386 ArrayRef(AltOrder2)
6387 };
6388 const unsigned Select = GPRC_NOR0AltOrderSelect(MF, Rev);
6389 assert(Select < 3);
6390 return Order[Select];
6391}
6392
6393static inline unsigned GPRC_and_GPRC_NOR0AltOrderSelect(const MachineFunction &MF, bool Rev) {
6394 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6395 }
6396
6397static ArrayRef<MCPhysReg> GPRC_and_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6398 static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
6399 static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP };
6400 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_and_GPRC_NOR0RegClassID];
6401 const ArrayRef<MCPhysReg> Order[] = {
6402 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6403 ArrayRef(AltOrder1),
6404 ArrayRef(AltOrder2)
6405 };
6406 const unsigned Select = GPRC_and_GPRC_NOR0AltOrderSelect(MF, Rev);
6407 assert(Select < 3);
6408 return Order[Select];
6409}
6410
6411static inline unsigned CRBITRCAltOrderSelect(const MachineFunction &MF, bool Rev) {
6412 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
6413 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
6414 }
6415
6416static ArrayRef<MCPhysReg> CRBITRCGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6417 static const MCPhysReg AltOrder1[] = { PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN };
6418 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRBITRCRegClassID];
6419 const ArrayRef<MCPhysReg> Order[] = {
6420 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6421 ArrayRef(AltOrder1)
6422 };
6423 const unsigned Select = CRBITRCAltOrderSelect(MF, Rev);
6424 assert(Select < 2);
6425 return Order[Select];
6426}
6427
6428static inline unsigned CRRCAltOrderSelect(const MachineFunction &MF, bool Rev) {
6429 return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
6430 MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
6431 }
6432
6433static ArrayRef<MCPhysReg> CRRCGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6434 static const MCPhysReg AltOrder1[] = { PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 };
6435 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRRCRegClassID];
6436 const ArrayRef<MCPhysReg> Order[] = {
6437 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6438 ArrayRef(AltOrder1)
6439 };
6440 const unsigned Select = CRRCAltOrderSelect(MF, Rev);
6441 assert(Select < 2);
6442 return Order[Select];
6443}
6444
6445static inline unsigned G8RCAltOrderSelect(const MachineFunction &MF, bool Rev) {
6446 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6447 }
6448
6449static ArrayRef<MCPhysReg> G8RCGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6450 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
6451 static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8 };
6452 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID];
6453 const ArrayRef<MCPhysReg> Order[] = {
6454 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6455 ArrayRef(AltOrder1),
6456 ArrayRef(AltOrder2)
6457 };
6458 const unsigned Select = G8RCAltOrderSelect(MF, Rev);
6459 assert(Select < 3);
6460 return Order[Select];
6461}
6462
6463static inline unsigned G8RC_NOX0AltOrderSelect(const MachineFunction &MF, bool Rev) {
6464 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6465 }
6466
6467static ArrayRef<MCPhysReg> G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6468 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, PPC::X2 };
6469 static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8 };
6470 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID];
6471 const ArrayRef<MCPhysReg> Order[] = {
6472 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6473 ArrayRef(AltOrder1),
6474 ArrayRef(AltOrder2)
6475 };
6476 const unsigned Select = G8RC_NOX0AltOrderSelect(MF, Rev);
6477 assert(Select < 3);
6478 return Order[Select];
6479}
6480
6481static inline unsigned G8RC_and_G8RC_NOX0AltOrderSelect(const MachineFunction &MF, bool Rev) {
6482 return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
6483 }
6484
6485static ArrayRef<MCPhysReg> G8RC_and_G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6486 static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
6487 static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8 };
6488 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_and_G8RC_NOX0RegClassID];
6489 const ArrayRef<MCPhysReg> Order[] = {
6490 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6491 ArrayRef(AltOrder1),
6492 ArrayRef(AltOrder2)
6493 };
6494 const unsigned Select = G8RC_and_G8RC_NOX0AltOrderSelect(MF, Rev);
6495 assert(Select < 3);
6496 return Order[Select];
6497}
6498
6499static inline unsigned G8pRCAltOrderSelect(const MachineFunction &MF, bool Rev) {
6500 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
6501 }
6502
6503static ArrayRef<MCPhysReg> G8pRCGetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6504 static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0, PPC::G8p1 };
6505 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRCRegClassID];
6506 const ArrayRef<MCPhysReg> Order[] = {
6507 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6508 ArrayRef(AltOrder1)
6509 };
6510 const unsigned Select = G8pRCAltOrderSelect(MF, Rev);
6511 assert(Select < 2);
6512 return Order[Select];
6513}
6514
6515static inline unsigned G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(const MachineFunction &MF, bool Rev) {
6516 return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
6517 }
6518
6519static ArrayRef<MCPhysReg> G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
6520 static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p1 };
6521 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID];
6522 const ArrayRef<MCPhysReg> Order[] = {
6523 ArrayRef(MCR.begin(), MCR.getNumRegs()),
6524 ArrayRef(AltOrder1)
6525 };
6526 const unsigned Select = G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(MF, Rev);
6527 assert(Select < 2);
6528 return Order[Select];
6529}
6530
6531namespace PPC { // Register class instances
6532 extern const TargetRegisterClass VSSRCRegClass = {
6533 &PPCMCRegisterClasses[VSSRCRegClassID],
6534 VSSRCSubClassMask,
6535 SuperRegIdxSeqs + 25,
6536 LaneBitmask(0x0000000000000001),
6537 0,
6538 false,
6539 0x00, /* TSFlags */
6540 false, /* HasDisjunctSubRegs */
6541 false, /* CoveredBySubRegs */
6542 nullptr, 0,
6543 nullptr
6544 };
6545
6546 extern const TargetRegisterClass GPRCRegClass = {
6547 &PPCMCRegisterClasses[GPRCRegClassID],
6548 GPRCSubClassMask,
6549 SuperRegIdxSeqs + 73,
6550 LaneBitmask(0x0000000000000001),
6551 0,
6552 false,
6553 0x00, /* TSFlags */
6554 false, /* HasDisjunctSubRegs */
6555 false, /* CoveredBySubRegs */
6556 nullptr, 0,
6557 GPRCGetRawAllocationOrder
6558 };
6559
6560 extern const TargetRegisterClass GPRC_NOR0RegClass = {
6561 &PPCMCRegisterClasses[GPRC_NOR0RegClassID],
6562 GPRC_NOR0SubClassMask,
6563 SuperRegIdxSeqs + 73,
6564 LaneBitmask(0x0000000000000001),
6565 0,
6566 false,
6567 0x00, /* TSFlags */
6568 false, /* HasDisjunctSubRegs */
6569 false, /* CoveredBySubRegs */
6570 nullptr, 0,
6571 GPRC_NOR0GetRawAllocationOrder
6572 };
6573
6574 extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass = {
6575 &PPCMCRegisterClasses[GPRC_and_GPRC_NOR0RegClassID],
6576 GPRC_and_GPRC_NOR0SubClassMask,
6577 SuperRegIdxSeqs + 73,
6578 LaneBitmask(0x0000000000000001),
6579 0,
6580 false,
6581 0x00, /* TSFlags */
6582 false, /* HasDisjunctSubRegs */
6583 false, /* CoveredBySubRegs */
6584 GPRC_and_GPRC_NOR0Superclasses, 2,
6585 GPRC_and_GPRC_NOR0GetRawAllocationOrder
6586 };
6587
6588 extern const TargetRegisterClass CRBITRCRegClass = {
6589 &PPCMCRegisterClasses[CRBITRCRegClassID],
6590 CRBITRCSubClassMask,
6591 SuperRegIdxSeqs + 9,
6592 LaneBitmask(0x0000000000000001),
6593 0,
6594 false,
6595 0x00, /* TSFlags */
6596 false, /* HasDisjunctSubRegs */
6597 false, /* CoveredBySubRegs */
6598 nullptr, 0,
6599 CRBITRCGetRawAllocationOrder
6600 };
6601
6602 extern const TargetRegisterClass F4RCRegClass = {
6603 &PPCMCRegisterClasses[F4RCRegClassID],
6604 F4RCSubClassMask,
6605 SuperRegIdxSeqs + 25,
6606 LaneBitmask(0x0000000000000001),
6607 0,
6608 false,
6609 0x00, /* TSFlags */
6610 false, /* HasDisjunctSubRegs */
6611 false, /* CoveredBySubRegs */
6612 F4RCSuperclasses, 1,
6613 nullptr
6614 };
6615
6616 extern const TargetRegisterClass GPRC32RegClass = {
6617 &PPCMCRegisterClasses[GPRC32RegClassID],
6618 GPRC32SubClassMask,
6619 SuperRegIdxSeqs + 2,
6620 LaneBitmask(0x0000000000000001),
6621 0,
6622 false,
6623 0x00, /* TSFlags */
6624 false, /* HasDisjunctSubRegs */
6625 false, /* CoveredBySubRegs */
6626 nullptr, 0,
6627 nullptr
6628 };
6629
6630 extern const TargetRegisterClass CRRCRegClass = {
6631 &PPCMCRegisterClasses[CRRCRegClassID],
6632 CRRCSubClassMask,
6633 SuperRegIdxSeqs + 2,
6634 LaneBitmask(0x0000000000000E40),
6635 0,
6636 false,
6637 0x00, /* TSFlags */
6638 true, /* HasDisjunctSubRegs */
6639 false, /* CoveredBySubRegs */
6640 nullptr, 0,
6641 CRRCGetRawAllocationOrder
6642 };
6643
6644 extern const TargetRegisterClass CARRYRCRegClass = {
6645 &PPCMCRegisterClasses[CARRYRCRegClassID],
6646 CARRYRCSubClassMask,
6647 SuperRegIdxSeqs + 2,
6648 LaneBitmask(0x0000000000000001),
6649 0,
6650 false,
6651 0x00, /* TSFlags */
6652 false, /* HasDisjunctSubRegs */
6653 false, /* CoveredBySubRegs */
6654 nullptr, 0,
6655 nullptr
6656 };
6657
6658 extern const TargetRegisterClass CTRRCRegClass = {
6659 &PPCMCRegisterClasses[CTRRCRegClassID],
6660 CTRRCSubClassMask,
6661 SuperRegIdxSeqs + 2,
6662 LaneBitmask(0x0000000000000001),
6663 0,
6664 false,
6665 0x00, /* TSFlags */
6666 false, /* HasDisjunctSubRegs */
6667 false, /* CoveredBySubRegs */
6668 nullptr, 0,
6669 nullptr
6670 };
6671
6672 extern const TargetRegisterClass LRRCRegClass = {
6673 &PPCMCRegisterClasses[LRRCRegClassID],
6674 LRRCSubClassMask,
6675 SuperRegIdxSeqs + 2,
6676 LaneBitmask(0x0000000000000001),
6677 0,
6678 false,
6679 0x00, /* TSFlags */
6680 false, /* HasDisjunctSubRegs */
6681 false, /* CoveredBySubRegs */
6682 nullptr, 0,
6683 nullptr
6684 };
6685
6686 extern const TargetRegisterClass VRSAVERCRegClass = {
6687 &PPCMCRegisterClasses[VRSAVERCRegClassID],
6688 VRSAVERCSubClassMask,
6689 SuperRegIdxSeqs + 2,
6690 LaneBitmask(0x0000000000000001),
6691 0,
6692 false,
6693 0x00, /* TSFlags */
6694 false, /* HasDisjunctSubRegs */
6695 false, /* CoveredBySubRegs */
6696 nullptr, 0,
6697 nullptr
6698 };
6699
6700 extern const TargetRegisterClass SPILLTOVSRRCRegClass = {
6701 &PPCMCRegisterClasses[SPILLTOVSRRCRegClassID],
6702 SPILLTOVSRRCSubClassMask,
6703 SuperRegIdxSeqs + 32,
6704 LaneBitmask(0x0000000000000001),
6705 0,
6706 false,
6707 0x00, /* TSFlags */
6708 false, /* HasDisjunctSubRegs */
6709 false, /* CoveredBySubRegs */
6710 nullptr, 0,
6711 nullptr
6712 };
6713
6714 extern const TargetRegisterClass VSFRCRegClass = {
6715 &PPCMCRegisterClasses[VSFRCRegClassID],
6716 VSFRCSubClassMask,
6717 SuperRegIdxSeqs + 25,
6718 LaneBitmask(0x0000000000000001),
6719 0,
6720 false,
6721 0x00, /* TSFlags */
6722 false, /* HasDisjunctSubRegs */
6723 false, /* CoveredBySubRegs */
6724 VSFRCSuperclasses, 1,
6725 nullptr
6726 };
6727
6728 extern const TargetRegisterClass G8RCRegClass = {
6729 &PPCMCRegisterClasses[G8RCRegClassID],
6730 G8RCSubClassMask,
6731 SuperRegIdxSeqs + 3,
6732 LaneBitmask(0x0000000000000001),
6733 0,
6734 false,
6735 0x00, /* TSFlags */
6736 false, /* HasDisjunctSubRegs */
6737 false, /* CoveredBySubRegs */
6738 G8RCSuperclasses, 1,
6739 G8RCGetRawAllocationOrder
6740 };
6741
6742 extern const TargetRegisterClass G8RC_NOX0RegClass = {
6743 &PPCMCRegisterClasses[G8RC_NOX0RegClassID],
6744 G8RC_NOX0SubClassMask,
6745 SuperRegIdxSeqs + 3,
6746 LaneBitmask(0x0000000000000001),
6747 0,
6748 false,
6749 0x00, /* TSFlags */
6750 false, /* HasDisjunctSubRegs */
6751 false, /* CoveredBySubRegs */
6752 nullptr, 0,
6753 G8RC_NOX0GetRawAllocationOrder
6754 };
6755
6756 extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass = {
6757 &PPCMCRegisterClasses[SPILLTOVSRRC_and_VSFRCRegClassID],
6758 SPILLTOVSRRC_and_VSFRCSubClassMask,
6759 SuperRegIdxSeqs + 25,
6760 LaneBitmask(0x0000000000000001),
6761 0,
6762 false,
6763 0x00, /* TSFlags */
6764 false, /* HasDisjunctSubRegs */
6765 false, /* CoveredBySubRegs */
6766 SPILLTOVSRRC_and_VSFRCSuperclasses, 3,
6767 nullptr
6768 };
6769
6770 extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass = {
6771 &PPCMCRegisterClasses[G8RC_and_G8RC_NOX0RegClassID],
6772 G8RC_and_G8RC_NOX0SubClassMask,
6773 SuperRegIdxSeqs + 3,
6774 LaneBitmask(0x0000000000000001),
6775 0,
6776 false,
6777 0x00, /* TSFlags */
6778 false, /* HasDisjunctSubRegs */
6779 false, /* CoveredBySubRegs */
6780 G8RC_and_G8RC_NOX0Superclasses, 3,
6781 G8RC_and_G8RC_NOX0GetRawAllocationOrder
6782 };
6783
6784 extern const TargetRegisterClass F8RCRegClass = {
6785 &PPCMCRegisterClasses[F8RCRegClassID],
6786 F8RCSubClassMask,
6787 SuperRegIdxSeqs + 25,
6788 LaneBitmask(0x0000000000000001),
6789 0,
6790 false,
6791 0x00, /* TSFlags */
6792 false, /* HasDisjunctSubRegs */
6793 false, /* CoveredBySubRegs */
6794 F8RCSuperclasses, 3,
6795 nullptr
6796 };
6797
6798 extern const TargetRegisterClass FHRCRegClass = {
6799 &PPCMCRegisterClasses[FHRCRegClassID],
6800 FHRCSubClassMask,
6801 SuperRegIdxSeqs + 2,
6802 LaneBitmask(0x0000000000000001),
6803 0,
6804 false,
6805 0x00, /* TSFlags */
6806 false, /* HasDisjunctSubRegs */
6807 false, /* CoveredBySubRegs */
6808 nullptr, 0,
6809 nullptr
6810 };
6811
6812 extern const TargetRegisterClass SPERCRegClass = {
6813 &PPCMCRegisterClasses[SPERCRegClassID],
6814 SPERCSubClassMask,
6815 SuperRegIdxSeqs + 2,
6816 LaneBitmask(0x0000000000000003),
6817 0,
6818 false,
6819 0x00, /* TSFlags */
6820 true, /* HasDisjunctSubRegs */
6821 true, /* CoveredBySubRegs */
6822 nullptr, 0,
6823 nullptr
6824 };
6825
6826 extern const TargetRegisterClass VFHRCRegClass = {
6827 &PPCMCRegisterClasses[VFHRCRegClassID],
6828 VFHRCSubClassMask,
6829 SuperRegIdxSeqs + 2,
6830 LaneBitmask(0x0000000000000001),
6831 0,
6832 false,
6833 0x00, /* TSFlags */
6834 false, /* HasDisjunctSubRegs */
6835 false, /* CoveredBySubRegs */
6836 nullptr, 0,
6837 nullptr
6838 };
6839
6840 extern const TargetRegisterClass VFRCRegClass = {
6841 &PPCMCRegisterClasses[VFRCRegClassID],
6842 VFRCSubClassMask,
6843 SuperRegIdxSeqs + 17,
6844 LaneBitmask(0x0000000000000001),
6845 0,
6846 false,
6847 0x00, /* TSFlags */
6848 false, /* HasDisjunctSubRegs */
6849 false, /* CoveredBySubRegs */
6850 VFRCSuperclasses, 2,
6851 nullptr
6852 };
6853
6854 extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass = {
6855 &PPCMCRegisterClasses[SPERC_with_sub_32_in_GPRC_NOR0RegClassID],
6856 SPERC_with_sub_32_in_GPRC_NOR0SubClassMask,
6857 SuperRegIdxSeqs + 2,
6858 LaneBitmask(0x0000000000000003),
6859 0,
6860 false,
6861 0x00, /* TSFlags */
6862 true, /* HasDisjunctSubRegs */
6863 true, /* CoveredBySubRegs */
6864 SPERC_with_sub_32_in_GPRC_NOR0Superclasses, 1,
6865 nullptr
6866 };
6867
6868 extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass = {
6869 &PPCMCRegisterClasses[SPILLTOVSRRC_and_VFRCRegClassID],
6870 SPILLTOVSRRC_and_VFRCSubClassMask,
6871 SuperRegIdxSeqs + 17,
6872 LaneBitmask(0x0000000000000001),
6873 0,
6874 false,
6875 0x00, /* TSFlags */
6876 false, /* HasDisjunctSubRegs */
6877 false, /* CoveredBySubRegs */
6878 SPILLTOVSRRC_and_VFRCSuperclasses, 5,
6879 nullptr
6880 };
6881
6882 extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass = {
6883 &PPCMCRegisterClasses[SPILLTOVSRRC_and_F4RCRegClassID],
6884 SPILLTOVSRRC_and_F4RCSubClassMask,
6885 SuperRegIdxSeqs + 25,
6886 LaneBitmask(0x0000000000000001),
6887 0,
6888 false,
6889 0x00, /* TSFlags */
6890 false, /* HasDisjunctSubRegs */
6891 false, /* CoveredBySubRegs */
6892 SPILLTOVSRRC_and_F4RCSuperclasses, 6,
6893 nullptr
6894 };
6895
6896 extern const TargetRegisterClass CTRRC8RegClass = {
6897 &PPCMCRegisterClasses[CTRRC8RegClassID],
6898 CTRRC8SubClassMask,
6899 SuperRegIdxSeqs + 2,
6900 LaneBitmask(0x0000000000000001),
6901 0,
6902 false,
6903 0x00, /* TSFlags */
6904 false, /* HasDisjunctSubRegs */
6905 false, /* CoveredBySubRegs */
6906 nullptr, 0,
6907 nullptr
6908 };
6909
6910 extern const TargetRegisterClass LR8RCRegClass = {
6911 &PPCMCRegisterClasses[LR8RCRegClassID],
6912 LR8RCSubClassMask,
6913 SuperRegIdxSeqs + 2,
6914 LaneBitmask(0x0000000000000001),
6915 0,
6916 false,
6917 0x00, /* TSFlags */
6918 false, /* HasDisjunctSubRegs */
6919 false, /* CoveredBySubRegs */
6920 nullptr, 0,
6921 nullptr
6922 };
6923
6924 extern const TargetRegisterClass DMRROWRCRegClass = {
6925 &PPCMCRegisterClasses[DMRROWRCRegClassID],
6926 DMRROWRCSubClassMask,
6927 SuperRegIdxSeqs + 56,
6928 LaneBitmask(0x0000000000000001),
6929 0,
6930 false,
6931 0x00, /* TSFlags */
6932 false, /* HasDisjunctSubRegs */
6933 false, /* CoveredBySubRegs */
6934 nullptr, 0,
6935 nullptr
6936 };
6937
6938 extern const TargetRegisterClass VSRCRegClass = {
6939 &PPCMCRegisterClasses[VSRCRegClassID],
6940 VSRCSubClassMask,
6941 SuperRegIdxSeqs + 20,
6942 LaneBitmask(0x000000000000000C),
6943 0,
6944 false,
6945 0x00, /* TSFlags */
6946 true, /* HasDisjunctSubRegs */
6947 true, /* CoveredBySubRegs */
6948 nullptr, 0,
6949 nullptr
6950 };
6951
6952 extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6953 &PPCMCRegisterClasses[VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6954 VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6955 SuperRegIdxSeqs + 20,
6956 LaneBitmask(0x000000000000000C),
6957 0,
6958 false,
6959 0x00, /* TSFlags */
6960 true, /* HasDisjunctSubRegs */
6961 true, /* CoveredBySubRegs */
6962 VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, 1,
6963 nullptr
6964 };
6965
6966 extern const TargetRegisterClass VRRCRegClass = {
6967 &PPCMCRegisterClasses[VRRCRegClassID],
6968 VRRCSubClassMask,
6969 SuperRegIdxSeqs + 14,
6970 LaneBitmask(0x000000000000000C),
6971 0,
6972 false,
6973 0x00, /* TSFlags */
6974 true, /* HasDisjunctSubRegs */
6975 true, /* CoveredBySubRegs */
6976 VRRCSuperclasses, 1,
6977 nullptr
6978 };
6979
6980 extern const TargetRegisterClass VSLRCRegClass = {
6981 &PPCMCRegisterClasses[VSLRCRegClassID],
6982 VSLRCSubClassMask,
6983 SuperRegIdxSeqs + 20,
6984 LaneBitmask(0x000000000000000C),
6985 0,
6986 false,
6987 0x00, /* TSFlags */
6988 true, /* HasDisjunctSubRegs */
6989 true, /* CoveredBySubRegs */
6990 VSLRCSuperclasses, 1,
6991 nullptr
6992 };
6993
6994 extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
6995 &PPCMCRegisterClasses[VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
6996 VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
6997 SuperRegIdxSeqs + 14,
6998 LaneBitmask(0x000000000000000C),
6999 0,
7000 false,
7001 0x00, /* TSFlags */
7002 true, /* HasDisjunctSubRegs */
7003 true, /* CoveredBySubRegs */
7004 VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, 3,
7005 nullptr
7006 };
7007
7008 extern const TargetRegisterClass FpRCRegClass = {
7009 &PPCMCRegisterClasses[FpRCRegClassID],
7010 FpRCSubClassMask,
7011 SuperRegIdxSeqs + 2,
7012 LaneBitmask(0x0000000000000180),
7013 0,
7014 false,
7015 0x00, /* TSFlags */
7016 true, /* HasDisjunctSubRegs */
7017 false, /* CoveredBySubRegs */
7018 nullptr, 0,
7019 nullptr
7020 };
7021
7022 extern const TargetRegisterClass G8pRCRegClass = {
7023 &PPCMCRegisterClasses[G8pRCRegClassID],
7024 G8pRCSubClassMask,
7025 SuperRegIdxSeqs + 2,
7026 LaneBitmask(0x0000000100000001),
7027 0,
7028 false,
7029 0x00, /* TSFlags */
7030 true, /* HasDisjunctSubRegs */
7031 false, /* CoveredBySubRegs */
7032 nullptr, 0,
7033 G8pRCGetRawAllocationOrder
7034 };
7035
7036 extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass = {
7037 &PPCMCRegisterClasses[G8pRC_with_sub_32_in_GPRC_NOR0RegClassID],
7038 G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask,
7039 SuperRegIdxSeqs + 2,
7040 LaneBitmask(0x0000000100000001),
7041 0,
7042 false,
7043 0x00, /* TSFlags */
7044 true, /* HasDisjunctSubRegs */
7045 false, /* CoveredBySubRegs */
7046 G8pRC_with_sub_32_in_GPRC_NOR0Superclasses, 1,
7047 G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder
7048 };
7049
7050 extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7051 &PPCMCRegisterClasses[VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7052 VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7053 SuperRegIdxSeqs + 20,
7054 LaneBitmask(0x000000000000000C),
7055 0,
7056 false,
7057 0x00, /* TSFlags */
7058 true, /* HasDisjunctSubRegs */
7059 true, /* CoveredBySubRegs */
7060 VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, 3,
7061 nullptr
7062 };
7063
7064 extern const TargetRegisterClass FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass = {
7065 &PPCMCRegisterClasses[FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID],
7066 FpRC_with_sub_fp0_in_SPILLTOVSRRCSubClassMask,
7067 SuperRegIdxSeqs + 2,
7068 LaneBitmask(0x0000000000000180),
7069 0,
7070 false,
7071 0x00, /* TSFlags */
7072 true, /* HasDisjunctSubRegs */
7073 false, /* CoveredBySubRegs */
7074 FpRC_with_sub_fp0_in_SPILLTOVSRRCSuperclasses, 1,
7075 nullptr
7076 };
7077
7078 extern const TargetRegisterClass DMRROWpRCRegClass = {
7079 &PPCMCRegisterClasses[DMRROWpRCRegClassID],
7080 DMRROWpRCSubClassMask,
7081 SuperRegIdxSeqs + 47,
7082 LaneBitmask(0x0000000000000030),
7083 0,
7084 false,
7085 0x00, /* TSFlags */
7086 true, /* HasDisjunctSubRegs */
7087 false, /* CoveredBySubRegs */
7088 nullptr, 0,
7089 nullptr
7090 };
7091
7092 extern const TargetRegisterClass VSRpRCRegClass = {
7093 &PPCMCRegisterClasses[VSRpRCRegClassID],
7094 VSRpRCSubClassMask,
7095 SuperRegIdxSeqs + 6,
7096 LaneBitmask(0x000000000000300C),
7097 2,
7098 false,
7099 0x00, /* TSFlags */
7100 true, /* HasDisjunctSubRegs */
7101 false, /* CoveredBySubRegs */
7102 nullptr, 0,
7103 nullptr
7104 };
7105
7106 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7107 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7108 VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7109 SuperRegIdxSeqs + 6,
7110 LaneBitmask(0x000000000000300C),
7111 2,
7112 false,
7113 0x00, /* TSFlags */
7114 true, /* HasDisjunctSubRegs */
7115 false, /* CoveredBySubRegs */
7116 VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, 1,
7117 nullptr
7118 };
7119
7120 extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass = {
7121 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_F4RCRegClassID],
7122 VSRpRC_with_sub_64_in_F4RCSubClassMask,
7123 SuperRegIdxSeqs + 6,
7124 LaneBitmask(0x000000000000300C),
7125 2,
7126 false,
7127 0x00, /* TSFlags */
7128 true, /* HasDisjunctSubRegs */
7129 false, /* CoveredBySubRegs */
7130 VSRpRC_with_sub_64_in_F4RCSuperclasses, 1,
7131 nullptr
7132 };
7133
7134 extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass = {
7135 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_VFRCRegClassID],
7136 VSRpRC_with_sub_64_in_VFRCSubClassMask,
7137 SuperRegIdxSeqs + 2,
7138 LaneBitmask(0x000000000000300C),
7139 2,
7140 false,
7141 0x00, /* TSFlags */
7142 true, /* HasDisjunctSubRegs */
7143 false, /* CoveredBySubRegs */
7144 VSRpRC_with_sub_64_in_VFRCSuperclasses, 1,
7145 nullptr
7146 };
7147
7148 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass = {
7149 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID],
7150 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask,
7151 SuperRegIdxSeqs + 2,
7152 LaneBitmask(0x000000000000300C),
7153 2,
7154 false,
7155 0x00, /* TSFlags */
7156 true, /* HasDisjunctSubRegs */
7157 false, /* CoveredBySubRegs */
7158 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses, 3,
7159 nullptr
7160 };
7161
7162 extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass = {
7163 &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID],
7164 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask,
7165 SuperRegIdxSeqs + 6,
7166 LaneBitmask(0x000000000000300C),
7167 2,
7168 false,
7169 0x00, /* TSFlags */
7170 true, /* HasDisjunctSubRegs */
7171 false, /* CoveredBySubRegs */
7172 VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses, 3,
7173 nullptr
7174 };
7175
7176 extern const TargetRegisterClass ACCRCRegClass = {
7177 &PPCMCRegisterClasses[ACCRCRegClassID],
7178 ACCRCSubClassMask,
7179 SuperRegIdxSeqs + 2,
7180 LaneBitmask(0x000000000003F00C),
7181 31,
7182 true,
7183 0x00, /* TSFlags */
7184 true, /* HasDisjunctSubRegs */
7185 false, /* CoveredBySubRegs */
7186 nullptr, 0,
7187 nullptr
7188 };
7189
7190 extern const TargetRegisterClass UACCRCRegClass = {
7191 &PPCMCRegisterClasses[UACCRCRegClassID],
7192 UACCRCSubClassMask,
7193 SuperRegIdxSeqs + 2,
7194 LaneBitmask(0x000000000003F00C),
7195 4,
7196 true,
7197 0x00, /* TSFlags */
7198 true, /* HasDisjunctSubRegs */
7199 false, /* CoveredBySubRegs */
7200 nullptr, 0,
7201 nullptr
7202 };
7203
7204 extern const TargetRegisterClass WACCRCRegClass = {
7205 &PPCMCRegisterClasses[WACCRCRegClassID],
7206 WACCRCSubClassMask,
7207 SuperRegIdxSeqs + 44,
7208 LaneBitmask(0x00000000000C0030),
7209 0,
7210 false,
7211 0x00, /* TSFlags */
7212 true, /* HasDisjunctSubRegs */
7213 false, /* CoveredBySubRegs */
7214 nullptr, 0,
7215 nullptr
7216 };
7217
7218 extern const TargetRegisterClass WACC_HIRCRegClass = {
7219 &PPCMCRegisterClasses[WACC_HIRCRegClassID],
7220 WACC_HIRCSubClassMask,
7221 SuperRegIdxSeqs + 41,
7222 LaneBitmask(0x00000000000C0030),
7223 0,
7224 false,
7225 0x00, /* TSFlags */
7226 true, /* HasDisjunctSubRegs */
7227 false, /* CoveredBySubRegs */
7228 nullptr, 0,
7229 nullptr
7230 };
7231
7232 extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7233 &PPCMCRegisterClasses[ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7234 ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7235 SuperRegIdxSeqs + 2,
7236 LaneBitmask(0x000000000003F00C),
7237 31,
7238 true,
7239 0x00, /* TSFlags */
7240 true, /* HasDisjunctSubRegs */
7241 false, /* CoveredBySubRegs */
7242 ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, 1,
7243 nullptr
7244 };
7245
7246 extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
7247 &PPCMCRegisterClasses[UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
7248 UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
7249 SuperRegIdxSeqs + 2,
7250 LaneBitmask(0x000000000003F00C),
7251 4,
7252 true,
7253 0x00, /* TSFlags */
7254 true, /* HasDisjunctSubRegs */
7255 false, /* CoveredBySubRegs */
7256 UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, 1,
7257 nullptr
7258 };
7259
7260 extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
7261 &PPCMCRegisterClasses[ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
7262 ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
7263 SuperRegIdxSeqs + 2,
7264 LaneBitmask(0x000000000003F00C),
7265 31,
7266 true,
7267 0x00, /* TSFlags */
7268 true, /* HasDisjunctSubRegs */
7269 false, /* CoveredBySubRegs */
7270 ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses, 2,
7271 nullptr
7272 };
7273
7274 extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
7275 &PPCMCRegisterClasses[UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
7276 UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
7277 SuperRegIdxSeqs + 2,
7278 LaneBitmask(0x000000000003F00C),
7279 4,
7280 true,
7281 0x00, /* TSFlags */
7282 true, /* HasDisjunctSubRegs */
7283 false, /* CoveredBySubRegs */
7284 UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses, 2,
7285 nullptr
7286 };
7287
7288 extern const TargetRegisterClass DMRRCRegClass = {
7289 &PPCMCRegisterClasses[DMRRCRegClassID],
7290 DMRRCSubClassMask,
7291 SuperRegIdxSeqs + 0,
7292 LaneBitmask(0x0000000000FC0030),
7293 0,
7294 false,
7295 0x00, /* TSFlags */
7296 true, /* HasDisjunctSubRegs */
7297 false, /* CoveredBySubRegs */
7298 nullptr, 0,
7299 nullptr
7300 };
7301
7302 extern const TargetRegisterClass DMRpRCRegClass = {
7303 &PPCMCRegisterClasses[DMRpRCRegClassID],
7304 DMRpRCSubClassMask,
7305 SuperRegIdxSeqs + 2,
7306 LaneBitmask(0x00000000FFFC0030),
7307 0,
7308 false,
7309 0x00, /* TSFlags */
7310 true, /* HasDisjunctSubRegs */
7311 false, /* CoveredBySubRegs */
7312 nullptr, 0,
7313 nullptr
7314 };
7315
7316} // end namespace PPC
7317
7318namespace {
7319 const TargetRegisterClass *const RegisterClasses[] = {
7320 &PPC::VSSRCRegClass,
7321 &PPC::GPRCRegClass,
7322 &PPC::GPRC_NOR0RegClass,
7323 &PPC::GPRC_and_GPRC_NOR0RegClass,
7324 &PPC::CRBITRCRegClass,
7325 &PPC::F4RCRegClass,
7326 &PPC::GPRC32RegClass,
7327 &PPC::CRRCRegClass,
7328 &PPC::CARRYRCRegClass,
7329 &PPC::CTRRCRegClass,
7330 &PPC::LRRCRegClass,
7331 &PPC::VRSAVERCRegClass,
7332 &PPC::SPILLTOVSRRCRegClass,
7333 &PPC::VSFRCRegClass,
7334 &PPC::G8RCRegClass,
7335 &PPC::G8RC_NOX0RegClass,
7336 &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
7337 &PPC::G8RC_and_G8RC_NOX0RegClass,
7338 &PPC::F8RCRegClass,
7339 &PPC::FHRCRegClass,
7340 &PPC::SPERCRegClass,
7341 &PPC::VFHRCRegClass,
7342 &PPC::VFRCRegClass,
7343 &PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClass,
7344 &PPC::SPILLTOVSRRC_and_VFRCRegClass,
7345 &PPC::SPILLTOVSRRC_and_F4RCRegClass,
7346 &PPC::CTRRC8RegClass,
7347 &PPC::LR8RCRegClass,
7348 &PPC::DMRROWRCRegClass,
7349 &PPC::VSRCRegClass,
7350 &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7351 &PPC::VRRCRegClass,
7352 &PPC::VSLRCRegClass,
7353 &PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7354 &PPC::FpRCRegClass,
7355 &PPC::G8pRCRegClass,
7356 &PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClass,
7357 &PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7358 &PPC::FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass,
7359 &PPC::DMRROWpRCRegClass,
7360 &PPC::VSRpRCRegClass,
7361 &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7362 &PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
7363 &PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
7364 &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass,
7365 &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass,
7366 &PPC::ACCRCRegClass,
7367 &PPC::UACCRCRegClass,
7368 &PPC::WACCRCRegClass,
7369 &PPC::WACC_HIRCRegClass,
7370 &PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7371 &PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
7372 &PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
7373 &PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
7374 &PPC::DMRRCRegClass,
7375 &PPC::DMRpRCRegClass,
7376 };
7377} // end anonymous namespace
7378
7379static const uint8_t CostPerUseTable[] = {
73800, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
7381
7382
7383static const bool InAllocatableClassTable[] = {
7384false, true, false, false, true, false, false, false, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
7385
7386
7387static const TargetRegisterInfoDesc PPCRegInfoDesc = { // Extra Descriptors
7388CostPerUseTable, 1, InAllocatableClassTable};
7389
7390unsigned PPCGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
7391 static const uint8_t RowMap[55] = {
7392 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 2, 3, 0, 0, 0, 0, 0, 1, 3, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 1, 5, 6, 1, 0, 0, 0, 0, 6, 7, 0, 0, 0,
7393 };
7394 static const uint8_t Rows[8][55] = {
7395 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7396 { PPC::sub_gp8_x1_then_sub_32, 0, PPC::sub_pair1_then_sub_64, PPC::sub_pair1_then_sub_64_hi_phony, 0, 0, PPC::sub_dmr1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_pair1_then_sub_vsx0, PPC::sub_pair1_then_sub_vsx1, PPC::sub_dmr1_then_sub_wacc_hi, PPC::sub_dmr1_then_sub_wacc_lo, PPC::sub_pair1_then_sub_vsx1_then_sub_64, PPC::sub_pair1_then_sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7397 { 0, 0, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7398 { 0, 0, PPC::sub_pair1_then_sub_vsx1_then_sub_64, PPC::sub_pair1_then_sub_vsx1_then_sub_64_hi_phony, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7399 { 0, 0, 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7400 { 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7401 { 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7402 { 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7403 };
7404
7405 --IdxA; assert(IdxA < 55); (void) IdxA;
7406 --IdxB; assert(IdxB < 55);
7407 return Rows[RowMap[IdxA]][IdxB];
7408}
7409
7410unsigned PPCGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
7411 static const uint8_t Table[55][55] = {
7412 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7413 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7414 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7415 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7416 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7417 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_32, },
7418 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7419 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7420 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7421 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7422 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7423 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7424 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7425 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7426 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_32, },
7427 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7428 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7429 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7430 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_32, },
7431 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7432 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7433 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7434 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7435 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7436 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7437 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7438 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7439 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7440 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_32, },
7441 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7442 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7443 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7444 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7445 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7446 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7447 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7448 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7449 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7450 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7451 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7452 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7453 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7454 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_32, },
7455 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, },
7456 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, },
7457 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_64, PPC::sub_64_hi_phony, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_32, },
7458 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7459 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7460 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7461 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7462 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, },
7463 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, 0, },
7464 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7465 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7466 { PPC::sub_32, 0, PPC::sub_64, PPC::sub_64_hi_phony, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, PPC::sub_vsx1_then_sub_64_hi_phony, 0, 0, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
7467 };
7468
7469 --IdxA; assert(IdxA < 55);
7470 --IdxB; assert(IdxB < 55);
7471 return Table[IdxA][IdxB];
7472 }
7473
7474 struct MaskRolOp {
7475 LaneBitmask Mask;
7476 uint8_t RotateLeft;
7477 };
7478 static const MaskRolOp LaneMaskComposeSequences[] = {
7479 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
7480 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
7481 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
7482 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
7483 { LaneBitmask(0x0000000000000030), 20 }, { LaneBitmask(0x0000000000FC0000), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
7484 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 11
7485 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 13
7486 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 15
7487 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 17
7488 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 19
7489 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 21
7490 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 32 }, { LaneBitmask::getNone(), 0 }, // Sequence 23
7491 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 25
7492 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 27
7493 { LaneBitmask(0x000000000000000C), 12 }, { LaneBitmask(0x0000000000003000), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 29
7494 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 32
7495 { LaneBitmask(0x0000000000000030), 16 }, { LaneBitmask(0x00000000000C0000), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 34
7496 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 37
7497 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 39
7498 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 41
7499 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 43
7500 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }, // Sequence 45
7501 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 }, // Sequence 47
7502 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 }, // Sequence 49
7503 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 20 }, { LaneBitmask::getNone(), 0 }, // Sequence 51
7504 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 21 }, { LaneBitmask::getNone(), 0 }, // Sequence 53
7505 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 22 }, { LaneBitmask::getNone(), 0 }, // Sequence 55
7506 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 23 }, { LaneBitmask::getNone(), 0 }, // Sequence 57
7507 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 24 }, { LaneBitmask::getNone(), 0 }, // Sequence 59
7508 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 25 }, { LaneBitmask::getNone(), 0 }, // Sequence 61
7509 { LaneBitmask(0x0000000000000030), 24 }, { LaneBitmask(0x00000000000C0000), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 63
7510 { LaneBitmask(0x0000000000000030), 20 }, { LaneBitmask(0x00000000000C0000), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 66
7511 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 26 }, { LaneBitmask::getNone(), 0 }, // Sequence 69
7512 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 27 }, { LaneBitmask::getNone(), 0 }, // Sequence 71
7513 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 28 }, { LaneBitmask::getNone(), 0 }, // Sequence 73
7514 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 29 }, { LaneBitmask::getNone(), 0 }, // Sequence 75
7515 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 30 }, { LaneBitmask::getNone(), 0 }, // Sequence 77
7516 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 31 }, { LaneBitmask::getNone(), 0 } // Sequence 79
7517 };
7518 static const uint8_t CompositeSequences[] = {
7519 0, // to sub_32
7520 2, // to sub_32_hi_phony
7521 4, // to sub_64
7522 6, // to sub_64_hi_phony
7523 0, // to sub_dmr0
7524 8, // to sub_dmr1
7525 11, // to sub_dmrrow0
7526 13, // to sub_dmrrow1
7527 0, // to sub_dmrrowp0
7528 15, // to sub_dmrrowp1
7529 17, // to sub_eq
7530 19, // to sub_fp0
7531 21, // to sub_fp1
7532 0, // to sub_gp8_x0
7533 23, // to sub_gp8_x1
7534 25, // to sub_gt
7535 27, // to sub_lt
7536 0, // to sub_pair0
7537 29, // to sub_pair1
7538 32, // to sub_un
7539 0, // to sub_vsx0
7540 27, // to sub_vsx1
7541 34, // to sub_wacc_hi
7542 0, // to sub_wacc_lo
7543 37, // to sub_vsx1_then_sub_64
7544 39, // to sub_vsx1_then_sub_64_hi_phony
7545 15, // to sub_pair1_then_sub_64
7546 41, // to sub_pair1_then_sub_64_hi_phony
7547 37, // to sub_pair1_then_sub_vsx0
7548 15, // to sub_pair1_then_sub_vsx1
7549 43, // to sub_pair1_then_sub_vsx1_then_sub_64
7550 45, // to sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7551 47, // to sub_dmrrowp1_then_sub_dmrrow0
7552 49, // to sub_dmrrowp1_then_sub_dmrrow1
7553 51, // to sub_wacc_hi_then_sub_dmrrow0
7554 53, // to sub_wacc_hi_then_sub_dmrrow1
7555 43, // to sub_wacc_hi_then_sub_dmrrowp0
7556 47, // to sub_wacc_hi_then_sub_dmrrowp1
7557 55, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7558 57, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7559 59, // to sub_dmr1_then_sub_dmrrow0
7560 61, // to sub_dmr1_then_sub_dmrrow1
7561 51, // to sub_dmr1_then_sub_dmrrowp0
7562 55, // to sub_dmr1_then_sub_dmrrowp1
7563 63, // to sub_dmr1_then_sub_wacc_hi
7564 66, // to sub_dmr1_then_sub_wacc_lo
7565 69, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7566 71, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7567 73, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7568 75, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7569 59, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7570 69, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7571 77, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7572 79, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7573 23 // to sub_gp8_x1_then_sub_32
7574 };
7575
7576LaneBitmask PPCGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
7577 --IdxA; assert(IdxA < 55 && "Subregister index out of bounds");
7578 LaneBitmask Result;
7579 for (const MaskRolOp *Ops =
7580 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
7581 Ops->Mask.any(); ++Ops) {
7582 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
7583 if (unsigned S = Ops->RotateLeft)
7584 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
7585 else
7586 Result |= LaneBitmask(M);
7587 }
7588 return Result;
7589}
7590
7591LaneBitmask PPCGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
7592 LaneMask &= getSubRegIndexLaneMask(IdxA);
7593 --IdxA; assert(IdxA < 55 && "Subregister index out of bounds");
7594 LaneBitmask Result;
7595 for (const MaskRolOp *Ops =
7596 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
7597 Ops->Mask.any(); ++Ops) {
7598 LaneBitmask::Type M = LaneMask.getAsInteger();
7599 if (unsigned S = Ops->RotateLeft)
7600 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
7601 else
7602 Result |= LaneBitmask(M);
7603 }
7604 return Result;
7605}
7606
7607const TargetRegisterClass *PPCGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
7608 static const uint8_t Table[56][55] = {
7609 { // VSSRC
7610 0, // sub_32
7611 0, // sub_32_hi_phony
7612 0, // sub_64
7613 0, // sub_64_hi_phony
7614 0, // sub_dmr0
7615 0, // sub_dmr1
7616 0, // sub_dmrrow0
7617 0, // sub_dmrrow1
7618 0, // sub_dmrrowp0
7619 0, // sub_dmrrowp1
7620 0, // sub_eq
7621 0, // sub_fp0
7622 0, // sub_fp1
7623 0, // sub_gp8_x0
7624 0, // sub_gp8_x1
7625 0, // sub_gt
7626 0, // sub_lt
7627 0, // sub_pair0
7628 0, // sub_pair1
7629 0, // sub_un
7630 0, // sub_vsx0
7631 0, // sub_vsx1
7632 0, // sub_wacc_hi
7633 0, // sub_wacc_lo
7634 0, // sub_vsx1_then_sub_64
7635 0, // sub_vsx1_then_sub_64_hi_phony
7636 0, // sub_pair1_then_sub_64
7637 0, // sub_pair1_then_sub_64_hi_phony
7638 0, // sub_pair1_then_sub_vsx0
7639 0, // sub_pair1_then_sub_vsx1
7640 0, // sub_pair1_then_sub_vsx1_then_sub_64
7641 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7642 0, // sub_dmrrowp1_then_sub_dmrrow0
7643 0, // sub_dmrrowp1_then_sub_dmrrow1
7644 0, // sub_wacc_hi_then_sub_dmrrow0
7645 0, // sub_wacc_hi_then_sub_dmrrow1
7646 0, // sub_wacc_hi_then_sub_dmrrowp0
7647 0, // sub_wacc_hi_then_sub_dmrrowp1
7648 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7649 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7650 0, // sub_dmr1_then_sub_dmrrow0
7651 0, // sub_dmr1_then_sub_dmrrow1
7652 0, // sub_dmr1_then_sub_dmrrowp0
7653 0, // sub_dmr1_then_sub_dmrrowp1
7654 0, // sub_dmr1_then_sub_wacc_hi
7655 0, // sub_dmr1_then_sub_wacc_lo
7656 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7657 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7658 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7659 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7660 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7661 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7662 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7663 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7664 0, // sub_gp8_x1_then_sub_32
7665 },
7666 { // GPRC
7667 0, // sub_32
7668 0, // sub_32_hi_phony
7669 0, // sub_64
7670 0, // sub_64_hi_phony
7671 0, // sub_dmr0
7672 0, // sub_dmr1
7673 0, // sub_dmrrow0
7674 0, // sub_dmrrow1
7675 0, // sub_dmrrowp0
7676 0, // sub_dmrrowp1
7677 0, // sub_eq
7678 0, // sub_fp0
7679 0, // sub_fp1
7680 0, // sub_gp8_x0
7681 0, // sub_gp8_x1
7682 0, // sub_gt
7683 0, // sub_lt
7684 0, // sub_pair0
7685 0, // sub_pair1
7686 0, // sub_un
7687 0, // sub_vsx0
7688 0, // sub_vsx1
7689 0, // sub_wacc_hi
7690 0, // sub_wacc_lo
7691 0, // sub_vsx1_then_sub_64
7692 0, // sub_vsx1_then_sub_64_hi_phony
7693 0, // sub_pair1_then_sub_64
7694 0, // sub_pair1_then_sub_64_hi_phony
7695 0, // sub_pair1_then_sub_vsx0
7696 0, // sub_pair1_then_sub_vsx1
7697 0, // sub_pair1_then_sub_vsx1_then_sub_64
7698 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7699 0, // sub_dmrrowp1_then_sub_dmrrow0
7700 0, // sub_dmrrowp1_then_sub_dmrrow1
7701 0, // sub_wacc_hi_then_sub_dmrrow0
7702 0, // sub_wacc_hi_then_sub_dmrrow1
7703 0, // sub_wacc_hi_then_sub_dmrrowp0
7704 0, // sub_wacc_hi_then_sub_dmrrowp1
7705 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7706 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7707 0, // sub_dmr1_then_sub_dmrrow0
7708 0, // sub_dmr1_then_sub_dmrrow1
7709 0, // sub_dmr1_then_sub_dmrrowp0
7710 0, // sub_dmr1_then_sub_dmrrowp1
7711 0, // sub_dmr1_then_sub_wacc_hi
7712 0, // sub_dmr1_then_sub_wacc_lo
7713 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7714 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7715 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7716 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7717 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7718 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7719 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7720 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7721 0, // sub_gp8_x1_then_sub_32
7722 },
7723 { // GPRC_NOR0
7724 0, // sub_32
7725 0, // sub_32_hi_phony
7726 0, // sub_64
7727 0, // sub_64_hi_phony
7728 0, // sub_dmr0
7729 0, // sub_dmr1
7730 0, // sub_dmrrow0
7731 0, // sub_dmrrow1
7732 0, // sub_dmrrowp0
7733 0, // sub_dmrrowp1
7734 0, // sub_eq
7735 0, // sub_fp0
7736 0, // sub_fp1
7737 0, // sub_gp8_x0
7738 0, // sub_gp8_x1
7739 0, // sub_gt
7740 0, // sub_lt
7741 0, // sub_pair0
7742 0, // sub_pair1
7743 0, // sub_un
7744 0, // sub_vsx0
7745 0, // sub_vsx1
7746 0, // sub_wacc_hi
7747 0, // sub_wacc_lo
7748 0, // sub_vsx1_then_sub_64
7749 0, // sub_vsx1_then_sub_64_hi_phony
7750 0, // sub_pair1_then_sub_64
7751 0, // sub_pair1_then_sub_64_hi_phony
7752 0, // sub_pair1_then_sub_vsx0
7753 0, // sub_pair1_then_sub_vsx1
7754 0, // sub_pair1_then_sub_vsx1_then_sub_64
7755 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7756 0, // sub_dmrrowp1_then_sub_dmrrow0
7757 0, // sub_dmrrowp1_then_sub_dmrrow1
7758 0, // sub_wacc_hi_then_sub_dmrrow0
7759 0, // sub_wacc_hi_then_sub_dmrrow1
7760 0, // sub_wacc_hi_then_sub_dmrrowp0
7761 0, // sub_wacc_hi_then_sub_dmrrowp1
7762 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7763 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7764 0, // sub_dmr1_then_sub_dmrrow0
7765 0, // sub_dmr1_then_sub_dmrrow1
7766 0, // sub_dmr1_then_sub_dmrrowp0
7767 0, // sub_dmr1_then_sub_dmrrowp1
7768 0, // sub_dmr1_then_sub_wacc_hi
7769 0, // sub_dmr1_then_sub_wacc_lo
7770 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7771 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7772 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7773 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7774 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7775 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7776 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7777 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7778 0, // sub_gp8_x1_then_sub_32
7779 },
7780 { // GPRC_and_GPRC_NOR0
7781 0, // sub_32
7782 0, // sub_32_hi_phony
7783 0, // sub_64
7784 0, // sub_64_hi_phony
7785 0, // sub_dmr0
7786 0, // sub_dmr1
7787 0, // sub_dmrrow0
7788 0, // sub_dmrrow1
7789 0, // sub_dmrrowp0
7790 0, // sub_dmrrowp1
7791 0, // sub_eq
7792 0, // sub_fp0
7793 0, // sub_fp1
7794 0, // sub_gp8_x0
7795 0, // sub_gp8_x1
7796 0, // sub_gt
7797 0, // sub_lt
7798 0, // sub_pair0
7799 0, // sub_pair1
7800 0, // sub_un
7801 0, // sub_vsx0
7802 0, // sub_vsx1
7803 0, // sub_wacc_hi
7804 0, // sub_wacc_lo
7805 0, // sub_vsx1_then_sub_64
7806 0, // sub_vsx1_then_sub_64_hi_phony
7807 0, // sub_pair1_then_sub_64
7808 0, // sub_pair1_then_sub_64_hi_phony
7809 0, // sub_pair1_then_sub_vsx0
7810 0, // sub_pair1_then_sub_vsx1
7811 0, // sub_pair1_then_sub_vsx1_then_sub_64
7812 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7813 0, // sub_dmrrowp1_then_sub_dmrrow0
7814 0, // sub_dmrrowp1_then_sub_dmrrow1
7815 0, // sub_wacc_hi_then_sub_dmrrow0
7816 0, // sub_wacc_hi_then_sub_dmrrow1
7817 0, // sub_wacc_hi_then_sub_dmrrowp0
7818 0, // sub_wacc_hi_then_sub_dmrrowp1
7819 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7820 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7821 0, // sub_dmr1_then_sub_dmrrow0
7822 0, // sub_dmr1_then_sub_dmrrow1
7823 0, // sub_dmr1_then_sub_dmrrowp0
7824 0, // sub_dmr1_then_sub_dmrrowp1
7825 0, // sub_dmr1_then_sub_wacc_hi
7826 0, // sub_dmr1_then_sub_wacc_lo
7827 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7828 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7829 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7830 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7831 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7832 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7833 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7834 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7835 0, // sub_gp8_x1_then_sub_32
7836 },
7837 { // CRBITRC
7838 0, // sub_32
7839 0, // sub_32_hi_phony
7840 0, // sub_64
7841 0, // sub_64_hi_phony
7842 0, // sub_dmr0
7843 0, // sub_dmr1
7844 0, // sub_dmrrow0
7845 0, // sub_dmrrow1
7846 0, // sub_dmrrowp0
7847 0, // sub_dmrrowp1
7848 0, // sub_eq
7849 0, // sub_fp0
7850 0, // sub_fp1
7851 0, // sub_gp8_x0
7852 0, // sub_gp8_x1
7853 0, // sub_gt
7854 0, // sub_lt
7855 0, // sub_pair0
7856 0, // sub_pair1
7857 0, // sub_un
7858 0, // sub_vsx0
7859 0, // sub_vsx1
7860 0, // sub_wacc_hi
7861 0, // sub_wacc_lo
7862 0, // sub_vsx1_then_sub_64
7863 0, // sub_vsx1_then_sub_64_hi_phony
7864 0, // sub_pair1_then_sub_64
7865 0, // sub_pair1_then_sub_64_hi_phony
7866 0, // sub_pair1_then_sub_vsx0
7867 0, // sub_pair1_then_sub_vsx1
7868 0, // sub_pair1_then_sub_vsx1_then_sub_64
7869 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7870 0, // sub_dmrrowp1_then_sub_dmrrow0
7871 0, // sub_dmrrowp1_then_sub_dmrrow1
7872 0, // sub_wacc_hi_then_sub_dmrrow0
7873 0, // sub_wacc_hi_then_sub_dmrrow1
7874 0, // sub_wacc_hi_then_sub_dmrrowp0
7875 0, // sub_wacc_hi_then_sub_dmrrowp1
7876 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7877 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7878 0, // sub_dmr1_then_sub_dmrrow0
7879 0, // sub_dmr1_then_sub_dmrrow1
7880 0, // sub_dmr1_then_sub_dmrrowp0
7881 0, // sub_dmr1_then_sub_dmrrowp1
7882 0, // sub_dmr1_then_sub_wacc_hi
7883 0, // sub_dmr1_then_sub_wacc_lo
7884 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7885 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7886 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7887 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7888 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7889 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7890 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7891 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7892 0, // sub_gp8_x1_then_sub_32
7893 },
7894 { // F4RC
7895 0, // sub_32
7896 0, // sub_32_hi_phony
7897 0, // sub_64
7898 0, // sub_64_hi_phony
7899 0, // sub_dmr0
7900 0, // sub_dmr1
7901 0, // sub_dmrrow0
7902 0, // sub_dmrrow1
7903 0, // sub_dmrrowp0
7904 0, // sub_dmrrowp1
7905 0, // sub_eq
7906 0, // sub_fp0
7907 0, // sub_fp1
7908 0, // sub_gp8_x0
7909 0, // sub_gp8_x1
7910 0, // sub_gt
7911 0, // sub_lt
7912 0, // sub_pair0
7913 0, // sub_pair1
7914 0, // sub_un
7915 0, // sub_vsx0
7916 0, // sub_vsx1
7917 0, // sub_wacc_hi
7918 0, // sub_wacc_lo
7919 0, // sub_vsx1_then_sub_64
7920 0, // sub_vsx1_then_sub_64_hi_phony
7921 0, // sub_pair1_then_sub_64
7922 0, // sub_pair1_then_sub_64_hi_phony
7923 0, // sub_pair1_then_sub_vsx0
7924 0, // sub_pair1_then_sub_vsx1
7925 0, // sub_pair1_then_sub_vsx1_then_sub_64
7926 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7927 0, // sub_dmrrowp1_then_sub_dmrrow0
7928 0, // sub_dmrrowp1_then_sub_dmrrow1
7929 0, // sub_wacc_hi_then_sub_dmrrow0
7930 0, // sub_wacc_hi_then_sub_dmrrow1
7931 0, // sub_wacc_hi_then_sub_dmrrowp0
7932 0, // sub_wacc_hi_then_sub_dmrrowp1
7933 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7934 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7935 0, // sub_dmr1_then_sub_dmrrow0
7936 0, // sub_dmr1_then_sub_dmrrow1
7937 0, // sub_dmr1_then_sub_dmrrowp0
7938 0, // sub_dmr1_then_sub_dmrrowp1
7939 0, // sub_dmr1_then_sub_wacc_hi
7940 0, // sub_dmr1_then_sub_wacc_lo
7941 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7942 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
7943 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
7944 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
7945 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
7946 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
7947 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7948 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7949 0, // sub_gp8_x1_then_sub_32
7950 },
7951 { // GPRC32
7952 0, // sub_32
7953 0, // sub_32_hi_phony
7954 0, // sub_64
7955 0, // sub_64_hi_phony
7956 0, // sub_dmr0
7957 0, // sub_dmr1
7958 0, // sub_dmrrow0
7959 0, // sub_dmrrow1
7960 0, // sub_dmrrowp0
7961 0, // sub_dmrrowp1
7962 0, // sub_eq
7963 0, // sub_fp0
7964 0, // sub_fp1
7965 0, // sub_gp8_x0
7966 0, // sub_gp8_x1
7967 0, // sub_gt
7968 0, // sub_lt
7969 0, // sub_pair0
7970 0, // sub_pair1
7971 0, // sub_un
7972 0, // sub_vsx0
7973 0, // sub_vsx1
7974 0, // sub_wacc_hi
7975 0, // sub_wacc_lo
7976 0, // sub_vsx1_then_sub_64
7977 0, // sub_vsx1_then_sub_64_hi_phony
7978 0, // sub_pair1_then_sub_64
7979 0, // sub_pair1_then_sub_64_hi_phony
7980 0, // sub_pair1_then_sub_vsx0
7981 0, // sub_pair1_then_sub_vsx1
7982 0, // sub_pair1_then_sub_vsx1_then_sub_64
7983 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
7984 0, // sub_dmrrowp1_then_sub_dmrrow0
7985 0, // sub_dmrrowp1_then_sub_dmrrow1
7986 0, // sub_wacc_hi_then_sub_dmrrow0
7987 0, // sub_wacc_hi_then_sub_dmrrow1
7988 0, // sub_wacc_hi_then_sub_dmrrowp0
7989 0, // sub_wacc_hi_then_sub_dmrrowp1
7990 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
7991 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
7992 0, // sub_dmr1_then_sub_dmrrow0
7993 0, // sub_dmr1_then_sub_dmrrow1
7994 0, // sub_dmr1_then_sub_dmrrowp0
7995 0, // sub_dmr1_then_sub_dmrrowp1
7996 0, // sub_dmr1_then_sub_wacc_hi
7997 0, // sub_dmr1_then_sub_wacc_lo
7998 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
7999 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8000 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8001 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8002 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8003 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8004 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8005 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8006 0, // sub_gp8_x1_then_sub_32
8007 },
8008 { // CRRC
8009 0, // sub_32
8010 0, // sub_32_hi_phony
8011 0, // sub_64
8012 0, // sub_64_hi_phony
8013 0, // sub_dmr0
8014 0, // sub_dmr1
8015 0, // sub_dmrrow0
8016 0, // sub_dmrrow1
8017 0, // sub_dmrrowp0
8018 0, // sub_dmrrowp1
8019 8, // sub_eq -> CRRC
8020 0, // sub_fp0
8021 0, // sub_fp1
8022 0, // sub_gp8_x0
8023 0, // sub_gp8_x1
8024 8, // sub_gt -> CRRC
8025 8, // sub_lt -> CRRC
8026 0, // sub_pair0
8027 0, // sub_pair1
8028 8, // sub_un -> CRRC
8029 0, // sub_vsx0
8030 0, // sub_vsx1
8031 0, // sub_wacc_hi
8032 0, // sub_wacc_lo
8033 0, // sub_vsx1_then_sub_64
8034 0, // sub_vsx1_then_sub_64_hi_phony
8035 0, // sub_pair1_then_sub_64
8036 0, // sub_pair1_then_sub_64_hi_phony
8037 0, // sub_pair1_then_sub_vsx0
8038 0, // sub_pair1_then_sub_vsx1
8039 0, // sub_pair1_then_sub_vsx1_then_sub_64
8040 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8041 0, // sub_dmrrowp1_then_sub_dmrrow0
8042 0, // sub_dmrrowp1_then_sub_dmrrow1
8043 0, // sub_wacc_hi_then_sub_dmrrow0
8044 0, // sub_wacc_hi_then_sub_dmrrow1
8045 0, // sub_wacc_hi_then_sub_dmrrowp0
8046 0, // sub_wacc_hi_then_sub_dmrrowp1
8047 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8048 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8049 0, // sub_dmr1_then_sub_dmrrow0
8050 0, // sub_dmr1_then_sub_dmrrow1
8051 0, // sub_dmr1_then_sub_dmrrowp0
8052 0, // sub_dmr1_then_sub_dmrrowp1
8053 0, // sub_dmr1_then_sub_wacc_hi
8054 0, // sub_dmr1_then_sub_wacc_lo
8055 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8056 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8057 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8058 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8059 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8060 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8061 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8062 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8063 0, // sub_gp8_x1_then_sub_32
8064 },
8065 { // CARRYRC
8066 0, // sub_32
8067 0, // sub_32_hi_phony
8068 0, // sub_64
8069 0, // sub_64_hi_phony
8070 0, // sub_dmr0
8071 0, // sub_dmr1
8072 0, // sub_dmrrow0
8073 0, // sub_dmrrow1
8074 0, // sub_dmrrowp0
8075 0, // sub_dmrrowp1
8076 0, // sub_eq
8077 0, // sub_fp0
8078 0, // sub_fp1
8079 0, // sub_gp8_x0
8080 0, // sub_gp8_x1
8081 0, // sub_gt
8082 0, // sub_lt
8083 0, // sub_pair0
8084 0, // sub_pair1
8085 0, // sub_un
8086 0, // sub_vsx0
8087 0, // sub_vsx1
8088 0, // sub_wacc_hi
8089 0, // sub_wacc_lo
8090 0, // sub_vsx1_then_sub_64
8091 0, // sub_vsx1_then_sub_64_hi_phony
8092 0, // sub_pair1_then_sub_64
8093 0, // sub_pair1_then_sub_64_hi_phony
8094 0, // sub_pair1_then_sub_vsx0
8095 0, // sub_pair1_then_sub_vsx1
8096 0, // sub_pair1_then_sub_vsx1_then_sub_64
8097 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8098 0, // sub_dmrrowp1_then_sub_dmrrow0
8099 0, // sub_dmrrowp1_then_sub_dmrrow1
8100 0, // sub_wacc_hi_then_sub_dmrrow0
8101 0, // sub_wacc_hi_then_sub_dmrrow1
8102 0, // sub_wacc_hi_then_sub_dmrrowp0
8103 0, // sub_wacc_hi_then_sub_dmrrowp1
8104 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8105 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8106 0, // sub_dmr1_then_sub_dmrrow0
8107 0, // sub_dmr1_then_sub_dmrrow1
8108 0, // sub_dmr1_then_sub_dmrrowp0
8109 0, // sub_dmr1_then_sub_dmrrowp1
8110 0, // sub_dmr1_then_sub_wacc_hi
8111 0, // sub_dmr1_then_sub_wacc_lo
8112 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8113 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8114 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8115 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8116 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8117 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8118 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8119 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8120 0, // sub_gp8_x1_then_sub_32
8121 },
8122 { // CTRRC
8123 0, // sub_32
8124 0, // sub_32_hi_phony
8125 0, // sub_64
8126 0, // sub_64_hi_phony
8127 0, // sub_dmr0
8128 0, // sub_dmr1
8129 0, // sub_dmrrow0
8130 0, // sub_dmrrow1
8131 0, // sub_dmrrowp0
8132 0, // sub_dmrrowp1
8133 0, // sub_eq
8134 0, // sub_fp0
8135 0, // sub_fp1
8136 0, // sub_gp8_x0
8137 0, // sub_gp8_x1
8138 0, // sub_gt
8139 0, // sub_lt
8140 0, // sub_pair0
8141 0, // sub_pair1
8142 0, // sub_un
8143 0, // sub_vsx0
8144 0, // sub_vsx1
8145 0, // sub_wacc_hi
8146 0, // sub_wacc_lo
8147 0, // sub_vsx1_then_sub_64
8148 0, // sub_vsx1_then_sub_64_hi_phony
8149 0, // sub_pair1_then_sub_64
8150 0, // sub_pair1_then_sub_64_hi_phony
8151 0, // sub_pair1_then_sub_vsx0
8152 0, // sub_pair1_then_sub_vsx1
8153 0, // sub_pair1_then_sub_vsx1_then_sub_64
8154 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8155 0, // sub_dmrrowp1_then_sub_dmrrow0
8156 0, // sub_dmrrowp1_then_sub_dmrrow1
8157 0, // sub_wacc_hi_then_sub_dmrrow0
8158 0, // sub_wacc_hi_then_sub_dmrrow1
8159 0, // sub_wacc_hi_then_sub_dmrrowp0
8160 0, // sub_wacc_hi_then_sub_dmrrowp1
8161 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8162 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8163 0, // sub_dmr1_then_sub_dmrrow0
8164 0, // sub_dmr1_then_sub_dmrrow1
8165 0, // sub_dmr1_then_sub_dmrrowp0
8166 0, // sub_dmr1_then_sub_dmrrowp1
8167 0, // sub_dmr1_then_sub_wacc_hi
8168 0, // sub_dmr1_then_sub_wacc_lo
8169 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8170 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8171 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8172 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8173 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8174 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8175 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8176 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8177 0, // sub_gp8_x1_then_sub_32
8178 },
8179 { // LRRC
8180 0, // sub_32
8181 0, // sub_32_hi_phony
8182 0, // sub_64
8183 0, // sub_64_hi_phony
8184 0, // sub_dmr0
8185 0, // sub_dmr1
8186 0, // sub_dmrrow0
8187 0, // sub_dmrrow1
8188 0, // sub_dmrrowp0
8189 0, // sub_dmrrowp1
8190 0, // sub_eq
8191 0, // sub_fp0
8192 0, // sub_fp1
8193 0, // sub_gp8_x0
8194 0, // sub_gp8_x1
8195 0, // sub_gt
8196 0, // sub_lt
8197 0, // sub_pair0
8198 0, // sub_pair1
8199 0, // sub_un
8200 0, // sub_vsx0
8201 0, // sub_vsx1
8202 0, // sub_wacc_hi
8203 0, // sub_wacc_lo
8204 0, // sub_vsx1_then_sub_64
8205 0, // sub_vsx1_then_sub_64_hi_phony
8206 0, // sub_pair1_then_sub_64
8207 0, // sub_pair1_then_sub_64_hi_phony
8208 0, // sub_pair1_then_sub_vsx0
8209 0, // sub_pair1_then_sub_vsx1
8210 0, // sub_pair1_then_sub_vsx1_then_sub_64
8211 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8212 0, // sub_dmrrowp1_then_sub_dmrrow0
8213 0, // sub_dmrrowp1_then_sub_dmrrow1
8214 0, // sub_wacc_hi_then_sub_dmrrow0
8215 0, // sub_wacc_hi_then_sub_dmrrow1
8216 0, // sub_wacc_hi_then_sub_dmrrowp0
8217 0, // sub_wacc_hi_then_sub_dmrrowp1
8218 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8219 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8220 0, // sub_dmr1_then_sub_dmrrow0
8221 0, // sub_dmr1_then_sub_dmrrow1
8222 0, // sub_dmr1_then_sub_dmrrowp0
8223 0, // sub_dmr1_then_sub_dmrrowp1
8224 0, // sub_dmr1_then_sub_wacc_hi
8225 0, // sub_dmr1_then_sub_wacc_lo
8226 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8227 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8228 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8229 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8230 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8231 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8232 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8233 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8234 0, // sub_gp8_x1_then_sub_32
8235 },
8236 { // VRSAVERC
8237 0, // sub_32
8238 0, // sub_32_hi_phony
8239 0, // sub_64
8240 0, // sub_64_hi_phony
8241 0, // sub_dmr0
8242 0, // sub_dmr1
8243 0, // sub_dmrrow0
8244 0, // sub_dmrrow1
8245 0, // sub_dmrrowp0
8246 0, // sub_dmrrowp1
8247 0, // sub_eq
8248 0, // sub_fp0
8249 0, // sub_fp1
8250 0, // sub_gp8_x0
8251 0, // sub_gp8_x1
8252 0, // sub_gt
8253 0, // sub_lt
8254 0, // sub_pair0
8255 0, // sub_pair1
8256 0, // sub_un
8257 0, // sub_vsx0
8258 0, // sub_vsx1
8259 0, // sub_wacc_hi
8260 0, // sub_wacc_lo
8261 0, // sub_vsx1_then_sub_64
8262 0, // sub_vsx1_then_sub_64_hi_phony
8263 0, // sub_pair1_then_sub_64
8264 0, // sub_pair1_then_sub_64_hi_phony
8265 0, // sub_pair1_then_sub_vsx0
8266 0, // sub_pair1_then_sub_vsx1
8267 0, // sub_pair1_then_sub_vsx1_then_sub_64
8268 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8269 0, // sub_dmrrowp1_then_sub_dmrrow0
8270 0, // sub_dmrrowp1_then_sub_dmrrow1
8271 0, // sub_wacc_hi_then_sub_dmrrow0
8272 0, // sub_wacc_hi_then_sub_dmrrow1
8273 0, // sub_wacc_hi_then_sub_dmrrowp0
8274 0, // sub_wacc_hi_then_sub_dmrrowp1
8275 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8276 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8277 0, // sub_dmr1_then_sub_dmrrow0
8278 0, // sub_dmr1_then_sub_dmrrow1
8279 0, // sub_dmr1_then_sub_dmrrowp0
8280 0, // sub_dmr1_then_sub_dmrrowp1
8281 0, // sub_dmr1_then_sub_wacc_hi
8282 0, // sub_dmr1_then_sub_wacc_lo
8283 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8284 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8285 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8286 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8287 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8288 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8289 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8290 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8291 0, // sub_gp8_x1_then_sub_32
8292 },
8293 { // SPILLTOVSRRC
8294 15, // sub_32 -> G8RC
8295 0, // sub_32_hi_phony
8296 0, // sub_64
8297 0, // sub_64_hi_phony
8298 0, // sub_dmr0
8299 0, // sub_dmr1
8300 0, // sub_dmrrow0
8301 0, // sub_dmrrow1
8302 0, // sub_dmrrowp0
8303 0, // sub_dmrrowp1
8304 0, // sub_eq
8305 0, // sub_fp0
8306 0, // sub_fp1
8307 0, // sub_gp8_x0
8308 0, // sub_gp8_x1
8309 0, // sub_gt
8310 0, // sub_lt
8311 0, // sub_pair0
8312 0, // sub_pair1
8313 0, // sub_un
8314 0, // sub_vsx0
8315 0, // sub_vsx1
8316 0, // sub_wacc_hi
8317 0, // sub_wacc_lo
8318 0, // sub_vsx1_then_sub_64
8319 0, // sub_vsx1_then_sub_64_hi_phony
8320 0, // sub_pair1_then_sub_64
8321 0, // sub_pair1_then_sub_64_hi_phony
8322 0, // sub_pair1_then_sub_vsx0
8323 0, // sub_pair1_then_sub_vsx1
8324 0, // sub_pair1_then_sub_vsx1_then_sub_64
8325 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8326 0, // sub_dmrrowp1_then_sub_dmrrow0
8327 0, // sub_dmrrowp1_then_sub_dmrrow1
8328 0, // sub_wacc_hi_then_sub_dmrrow0
8329 0, // sub_wacc_hi_then_sub_dmrrow1
8330 0, // sub_wacc_hi_then_sub_dmrrowp0
8331 0, // sub_wacc_hi_then_sub_dmrrowp1
8332 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8333 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8334 0, // sub_dmr1_then_sub_dmrrow0
8335 0, // sub_dmr1_then_sub_dmrrow1
8336 0, // sub_dmr1_then_sub_dmrrowp0
8337 0, // sub_dmr1_then_sub_dmrrowp1
8338 0, // sub_dmr1_then_sub_wacc_hi
8339 0, // sub_dmr1_then_sub_wacc_lo
8340 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8341 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8342 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8343 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8344 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8345 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8346 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8347 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8348 0, // sub_gp8_x1_then_sub_32
8349 },
8350 { // VSFRC
8351 0, // sub_32
8352 0, // sub_32_hi_phony
8353 0, // sub_64
8354 0, // sub_64_hi_phony
8355 0, // sub_dmr0
8356 0, // sub_dmr1
8357 0, // sub_dmrrow0
8358 0, // sub_dmrrow1
8359 0, // sub_dmrrowp0
8360 0, // sub_dmrrowp1
8361 0, // sub_eq
8362 0, // sub_fp0
8363 0, // sub_fp1
8364 0, // sub_gp8_x0
8365 0, // sub_gp8_x1
8366 0, // sub_gt
8367 0, // sub_lt
8368 0, // sub_pair0
8369 0, // sub_pair1
8370 0, // sub_un
8371 0, // sub_vsx0
8372 0, // sub_vsx1
8373 0, // sub_wacc_hi
8374 0, // sub_wacc_lo
8375 0, // sub_vsx1_then_sub_64
8376 0, // sub_vsx1_then_sub_64_hi_phony
8377 0, // sub_pair1_then_sub_64
8378 0, // sub_pair1_then_sub_64_hi_phony
8379 0, // sub_pair1_then_sub_vsx0
8380 0, // sub_pair1_then_sub_vsx1
8381 0, // sub_pair1_then_sub_vsx1_then_sub_64
8382 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8383 0, // sub_dmrrowp1_then_sub_dmrrow0
8384 0, // sub_dmrrowp1_then_sub_dmrrow1
8385 0, // sub_wacc_hi_then_sub_dmrrow0
8386 0, // sub_wacc_hi_then_sub_dmrrow1
8387 0, // sub_wacc_hi_then_sub_dmrrowp0
8388 0, // sub_wacc_hi_then_sub_dmrrowp1
8389 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8390 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8391 0, // sub_dmr1_then_sub_dmrrow0
8392 0, // sub_dmr1_then_sub_dmrrow1
8393 0, // sub_dmr1_then_sub_dmrrowp0
8394 0, // sub_dmr1_then_sub_dmrrowp1
8395 0, // sub_dmr1_then_sub_wacc_hi
8396 0, // sub_dmr1_then_sub_wacc_lo
8397 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8398 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8399 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8400 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8401 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8402 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8403 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8404 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8405 0, // sub_gp8_x1_then_sub_32
8406 },
8407 { // G8RC
8408 15, // sub_32 -> G8RC
8409 0, // sub_32_hi_phony
8410 0, // sub_64
8411 0, // sub_64_hi_phony
8412 0, // sub_dmr0
8413 0, // sub_dmr1
8414 0, // sub_dmrrow0
8415 0, // sub_dmrrow1
8416 0, // sub_dmrrowp0
8417 0, // sub_dmrrowp1
8418 0, // sub_eq
8419 0, // sub_fp0
8420 0, // sub_fp1
8421 0, // sub_gp8_x0
8422 0, // sub_gp8_x1
8423 0, // sub_gt
8424 0, // sub_lt
8425 0, // sub_pair0
8426 0, // sub_pair1
8427 0, // sub_un
8428 0, // sub_vsx0
8429 0, // sub_vsx1
8430 0, // sub_wacc_hi
8431 0, // sub_wacc_lo
8432 0, // sub_vsx1_then_sub_64
8433 0, // sub_vsx1_then_sub_64_hi_phony
8434 0, // sub_pair1_then_sub_64
8435 0, // sub_pair1_then_sub_64_hi_phony
8436 0, // sub_pair1_then_sub_vsx0
8437 0, // sub_pair1_then_sub_vsx1
8438 0, // sub_pair1_then_sub_vsx1_then_sub_64
8439 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8440 0, // sub_dmrrowp1_then_sub_dmrrow0
8441 0, // sub_dmrrowp1_then_sub_dmrrow1
8442 0, // sub_wacc_hi_then_sub_dmrrow0
8443 0, // sub_wacc_hi_then_sub_dmrrow1
8444 0, // sub_wacc_hi_then_sub_dmrrowp0
8445 0, // sub_wacc_hi_then_sub_dmrrowp1
8446 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8447 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8448 0, // sub_dmr1_then_sub_dmrrow0
8449 0, // sub_dmr1_then_sub_dmrrow1
8450 0, // sub_dmr1_then_sub_dmrrowp0
8451 0, // sub_dmr1_then_sub_dmrrowp1
8452 0, // sub_dmr1_then_sub_wacc_hi
8453 0, // sub_dmr1_then_sub_wacc_lo
8454 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8455 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8456 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8457 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8458 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8459 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8460 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8461 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8462 0, // sub_gp8_x1_then_sub_32
8463 },
8464 { // G8RC_NOX0
8465 16, // sub_32 -> G8RC_NOX0
8466 0, // sub_32_hi_phony
8467 0, // sub_64
8468 0, // sub_64_hi_phony
8469 0, // sub_dmr0
8470 0, // sub_dmr1
8471 0, // sub_dmrrow0
8472 0, // sub_dmrrow1
8473 0, // sub_dmrrowp0
8474 0, // sub_dmrrowp1
8475 0, // sub_eq
8476 0, // sub_fp0
8477 0, // sub_fp1
8478 0, // sub_gp8_x0
8479 0, // sub_gp8_x1
8480 0, // sub_gt
8481 0, // sub_lt
8482 0, // sub_pair0
8483 0, // sub_pair1
8484 0, // sub_un
8485 0, // sub_vsx0
8486 0, // sub_vsx1
8487 0, // sub_wacc_hi
8488 0, // sub_wacc_lo
8489 0, // sub_vsx1_then_sub_64
8490 0, // sub_vsx1_then_sub_64_hi_phony
8491 0, // sub_pair1_then_sub_64
8492 0, // sub_pair1_then_sub_64_hi_phony
8493 0, // sub_pair1_then_sub_vsx0
8494 0, // sub_pair1_then_sub_vsx1
8495 0, // sub_pair1_then_sub_vsx1_then_sub_64
8496 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8497 0, // sub_dmrrowp1_then_sub_dmrrow0
8498 0, // sub_dmrrowp1_then_sub_dmrrow1
8499 0, // sub_wacc_hi_then_sub_dmrrow0
8500 0, // sub_wacc_hi_then_sub_dmrrow1
8501 0, // sub_wacc_hi_then_sub_dmrrowp0
8502 0, // sub_wacc_hi_then_sub_dmrrowp1
8503 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8504 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8505 0, // sub_dmr1_then_sub_dmrrow0
8506 0, // sub_dmr1_then_sub_dmrrow1
8507 0, // sub_dmr1_then_sub_dmrrowp0
8508 0, // sub_dmr1_then_sub_dmrrowp1
8509 0, // sub_dmr1_then_sub_wacc_hi
8510 0, // sub_dmr1_then_sub_wacc_lo
8511 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8512 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8513 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8514 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8515 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8516 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8517 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8518 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8519 0, // sub_gp8_x1_then_sub_32
8520 },
8521 { // SPILLTOVSRRC_and_VSFRC
8522 0, // sub_32
8523 0, // sub_32_hi_phony
8524 0, // sub_64
8525 0, // sub_64_hi_phony
8526 0, // sub_dmr0
8527 0, // sub_dmr1
8528 0, // sub_dmrrow0
8529 0, // sub_dmrrow1
8530 0, // sub_dmrrowp0
8531 0, // sub_dmrrowp1
8532 0, // sub_eq
8533 0, // sub_fp0
8534 0, // sub_fp1
8535 0, // sub_gp8_x0
8536 0, // sub_gp8_x1
8537 0, // sub_gt
8538 0, // sub_lt
8539 0, // sub_pair0
8540 0, // sub_pair1
8541 0, // sub_un
8542 0, // sub_vsx0
8543 0, // sub_vsx1
8544 0, // sub_wacc_hi
8545 0, // sub_wacc_lo
8546 0, // sub_vsx1_then_sub_64
8547 0, // sub_vsx1_then_sub_64_hi_phony
8548 0, // sub_pair1_then_sub_64
8549 0, // sub_pair1_then_sub_64_hi_phony
8550 0, // sub_pair1_then_sub_vsx0
8551 0, // sub_pair1_then_sub_vsx1
8552 0, // sub_pair1_then_sub_vsx1_then_sub_64
8553 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8554 0, // sub_dmrrowp1_then_sub_dmrrow0
8555 0, // sub_dmrrowp1_then_sub_dmrrow1
8556 0, // sub_wacc_hi_then_sub_dmrrow0
8557 0, // sub_wacc_hi_then_sub_dmrrow1
8558 0, // sub_wacc_hi_then_sub_dmrrowp0
8559 0, // sub_wacc_hi_then_sub_dmrrowp1
8560 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8561 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8562 0, // sub_dmr1_then_sub_dmrrow0
8563 0, // sub_dmr1_then_sub_dmrrow1
8564 0, // sub_dmr1_then_sub_dmrrowp0
8565 0, // sub_dmr1_then_sub_dmrrowp1
8566 0, // sub_dmr1_then_sub_wacc_hi
8567 0, // sub_dmr1_then_sub_wacc_lo
8568 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8569 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8570 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8571 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8572 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8573 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8574 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8575 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8576 0, // sub_gp8_x1_then_sub_32
8577 },
8578 { // G8RC_and_G8RC_NOX0
8579 18, // sub_32 -> G8RC_and_G8RC_NOX0
8580 0, // sub_32_hi_phony
8581 0, // sub_64
8582 0, // sub_64_hi_phony
8583 0, // sub_dmr0
8584 0, // sub_dmr1
8585 0, // sub_dmrrow0
8586 0, // sub_dmrrow1
8587 0, // sub_dmrrowp0
8588 0, // sub_dmrrowp1
8589 0, // sub_eq
8590 0, // sub_fp0
8591 0, // sub_fp1
8592 0, // sub_gp8_x0
8593 0, // sub_gp8_x1
8594 0, // sub_gt
8595 0, // sub_lt
8596 0, // sub_pair0
8597 0, // sub_pair1
8598 0, // sub_un
8599 0, // sub_vsx0
8600 0, // sub_vsx1
8601 0, // sub_wacc_hi
8602 0, // sub_wacc_lo
8603 0, // sub_vsx1_then_sub_64
8604 0, // sub_vsx1_then_sub_64_hi_phony
8605 0, // sub_pair1_then_sub_64
8606 0, // sub_pair1_then_sub_64_hi_phony
8607 0, // sub_pair1_then_sub_vsx0
8608 0, // sub_pair1_then_sub_vsx1
8609 0, // sub_pair1_then_sub_vsx1_then_sub_64
8610 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8611 0, // sub_dmrrowp1_then_sub_dmrrow0
8612 0, // sub_dmrrowp1_then_sub_dmrrow1
8613 0, // sub_wacc_hi_then_sub_dmrrow0
8614 0, // sub_wacc_hi_then_sub_dmrrow1
8615 0, // sub_wacc_hi_then_sub_dmrrowp0
8616 0, // sub_wacc_hi_then_sub_dmrrowp1
8617 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8618 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8619 0, // sub_dmr1_then_sub_dmrrow0
8620 0, // sub_dmr1_then_sub_dmrrow1
8621 0, // sub_dmr1_then_sub_dmrrowp0
8622 0, // sub_dmr1_then_sub_dmrrowp1
8623 0, // sub_dmr1_then_sub_wacc_hi
8624 0, // sub_dmr1_then_sub_wacc_lo
8625 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8626 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8627 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8628 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8629 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8630 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8631 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8632 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8633 0, // sub_gp8_x1_then_sub_32
8634 },
8635 { // F8RC
8636 0, // sub_32
8637 0, // sub_32_hi_phony
8638 0, // sub_64
8639 0, // sub_64_hi_phony
8640 0, // sub_dmr0
8641 0, // sub_dmr1
8642 0, // sub_dmrrow0
8643 0, // sub_dmrrow1
8644 0, // sub_dmrrowp0
8645 0, // sub_dmrrowp1
8646 0, // sub_eq
8647 0, // sub_fp0
8648 0, // sub_fp1
8649 0, // sub_gp8_x0
8650 0, // sub_gp8_x1
8651 0, // sub_gt
8652 0, // sub_lt
8653 0, // sub_pair0
8654 0, // sub_pair1
8655 0, // sub_un
8656 0, // sub_vsx0
8657 0, // sub_vsx1
8658 0, // sub_wacc_hi
8659 0, // sub_wacc_lo
8660 0, // sub_vsx1_then_sub_64
8661 0, // sub_vsx1_then_sub_64_hi_phony
8662 0, // sub_pair1_then_sub_64
8663 0, // sub_pair1_then_sub_64_hi_phony
8664 0, // sub_pair1_then_sub_vsx0
8665 0, // sub_pair1_then_sub_vsx1
8666 0, // sub_pair1_then_sub_vsx1_then_sub_64
8667 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8668 0, // sub_dmrrowp1_then_sub_dmrrow0
8669 0, // sub_dmrrowp1_then_sub_dmrrow1
8670 0, // sub_wacc_hi_then_sub_dmrrow0
8671 0, // sub_wacc_hi_then_sub_dmrrow1
8672 0, // sub_wacc_hi_then_sub_dmrrowp0
8673 0, // sub_wacc_hi_then_sub_dmrrowp1
8674 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8675 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8676 0, // sub_dmr1_then_sub_dmrrow0
8677 0, // sub_dmr1_then_sub_dmrrow1
8678 0, // sub_dmr1_then_sub_dmrrowp0
8679 0, // sub_dmr1_then_sub_dmrrowp1
8680 0, // sub_dmr1_then_sub_wacc_hi
8681 0, // sub_dmr1_then_sub_wacc_lo
8682 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8683 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8684 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8685 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8686 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8687 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8688 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8689 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8690 0, // sub_gp8_x1_then_sub_32
8691 },
8692 { // FHRC
8693 0, // sub_32
8694 0, // sub_32_hi_phony
8695 0, // sub_64
8696 0, // sub_64_hi_phony
8697 0, // sub_dmr0
8698 0, // sub_dmr1
8699 0, // sub_dmrrow0
8700 0, // sub_dmrrow1
8701 0, // sub_dmrrowp0
8702 0, // sub_dmrrowp1
8703 0, // sub_eq
8704 0, // sub_fp0
8705 0, // sub_fp1
8706 0, // sub_gp8_x0
8707 0, // sub_gp8_x1
8708 0, // sub_gt
8709 0, // sub_lt
8710 0, // sub_pair0
8711 0, // sub_pair1
8712 0, // sub_un
8713 0, // sub_vsx0
8714 0, // sub_vsx1
8715 0, // sub_wacc_hi
8716 0, // sub_wacc_lo
8717 0, // sub_vsx1_then_sub_64
8718 0, // sub_vsx1_then_sub_64_hi_phony
8719 0, // sub_pair1_then_sub_64
8720 0, // sub_pair1_then_sub_64_hi_phony
8721 0, // sub_pair1_then_sub_vsx0
8722 0, // sub_pair1_then_sub_vsx1
8723 0, // sub_pair1_then_sub_vsx1_then_sub_64
8724 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8725 0, // sub_dmrrowp1_then_sub_dmrrow0
8726 0, // sub_dmrrowp1_then_sub_dmrrow1
8727 0, // sub_wacc_hi_then_sub_dmrrow0
8728 0, // sub_wacc_hi_then_sub_dmrrow1
8729 0, // sub_wacc_hi_then_sub_dmrrowp0
8730 0, // sub_wacc_hi_then_sub_dmrrowp1
8731 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8732 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8733 0, // sub_dmr1_then_sub_dmrrow0
8734 0, // sub_dmr1_then_sub_dmrrow1
8735 0, // sub_dmr1_then_sub_dmrrowp0
8736 0, // sub_dmr1_then_sub_dmrrowp1
8737 0, // sub_dmr1_then_sub_wacc_hi
8738 0, // sub_dmr1_then_sub_wacc_lo
8739 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8740 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8741 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8742 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8743 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8744 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8745 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8746 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8747 0, // sub_gp8_x1_then_sub_32
8748 },
8749 { // SPERC
8750 21, // sub_32 -> SPERC
8751 21, // sub_32_hi_phony -> SPERC
8752 0, // sub_64
8753 0, // sub_64_hi_phony
8754 0, // sub_dmr0
8755 0, // sub_dmr1
8756 0, // sub_dmrrow0
8757 0, // sub_dmrrow1
8758 0, // sub_dmrrowp0
8759 0, // sub_dmrrowp1
8760 0, // sub_eq
8761 0, // sub_fp0
8762 0, // sub_fp1
8763 0, // sub_gp8_x0
8764 0, // sub_gp8_x1
8765 0, // sub_gt
8766 0, // sub_lt
8767 0, // sub_pair0
8768 0, // sub_pair1
8769 0, // sub_un
8770 0, // sub_vsx0
8771 0, // sub_vsx1
8772 0, // sub_wacc_hi
8773 0, // sub_wacc_lo
8774 0, // sub_vsx1_then_sub_64
8775 0, // sub_vsx1_then_sub_64_hi_phony
8776 0, // sub_pair1_then_sub_64
8777 0, // sub_pair1_then_sub_64_hi_phony
8778 0, // sub_pair1_then_sub_vsx0
8779 0, // sub_pair1_then_sub_vsx1
8780 0, // sub_pair1_then_sub_vsx1_then_sub_64
8781 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8782 0, // sub_dmrrowp1_then_sub_dmrrow0
8783 0, // sub_dmrrowp1_then_sub_dmrrow1
8784 0, // sub_wacc_hi_then_sub_dmrrow0
8785 0, // sub_wacc_hi_then_sub_dmrrow1
8786 0, // sub_wacc_hi_then_sub_dmrrowp0
8787 0, // sub_wacc_hi_then_sub_dmrrowp1
8788 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8789 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8790 0, // sub_dmr1_then_sub_dmrrow0
8791 0, // sub_dmr1_then_sub_dmrrow1
8792 0, // sub_dmr1_then_sub_dmrrowp0
8793 0, // sub_dmr1_then_sub_dmrrowp1
8794 0, // sub_dmr1_then_sub_wacc_hi
8795 0, // sub_dmr1_then_sub_wacc_lo
8796 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8797 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8798 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8799 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8800 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8801 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8802 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8803 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8804 0, // sub_gp8_x1_then_sub_32
8805 },
8806 { // VFHRC
8807 0, // sub_32
8808 0, // sub_32_hi_phony
8809 0, // sub_64
8810 0, // sub_64_hi_phony
8811 0, // sub_dmr0
8812 0, // sub_dmr1
8813 0, // sub_dmrrow0
8814 0, // sub_dmrrow1
8815 0, // sub_dmrrowp0
8816 0, // sub_dmrrowp1
8817 0, // sub_eq
8818 0, // sub_fp0
8819 0, // sub_fp1
8820 0, // sub_gp8_x0
8821 0, // sub_gp8_x1
8822 0, // sub_gt
8823 0, // sub_lt
8824 0, // sub_pair0
8825 0, // sub_pair1
8826 0, // sub_un
8827 0, // sub_vsx0
8828 0, // sub_vsx1
8829 0, // sub_wacc_hi
8830 0, // sub_wacc_lo
8831 0, // sub_vsx1_then_sub_64
8832 0, // sub_vsx1_then_sub_64_hi_phony
8833 0, // sub_pair1_then_sub_64
8834 0, // sub_pair1_then_sub_64_hi_phony
8835 0, // sub_pair1_then_sub_vsx0
8836 0, // sub_pair1_then_sub_vsx1
8837 0, // sub_pair1_then_sub_vsx1_then_sub_64
8838 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8839 0, // sub_dmrrowp1_then_sub_dmrrow0
8840 0, // sub_dmrrowp1_then_sub_dmrrow1
8841 0, // sub_wacc_hi_then_sub_dmrrow0
8842 0, // sub_wacc_hi_then_sub_dmrrow1
8843 0, // sub_wacc_hi_then_sub_dmrrowp0
8844 0, // sub_wacc_hi_then_sub_dmrrowp1
8845 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8846 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8847 0, // sub_dmr1_then_sub_dmrrow0
8848 0, // sub_dmr1_then_sub_dmrrow1
8849 0, // sub_dmr1_then_sub_dmrrowp0
8850 0, // sub_dmr1_then_sub_dmrrowp1
8851 0, // sub_dmr1_then_sub_wacc_hi
8852 0, // sub_dmr1_then_sub_wacc_lo
8853 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8854 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8855 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8856 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8857 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8858 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8859 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8860 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8861 0, // sub_gp8_x1_then_sub_32
8862 },
8863 { // VFRC
8864 0, // sub_32
8865 0, // sub_32_hi_phony
8866 0, // sub_64
8867 0, // sub_64_hi_phony
8868 0, // sub_dmr0
8869 0, // sub_dmr1
8870 0, // sub_dmrrow0
8871 0, // sub_dmrrow1
8872 0, // sub_dmrrowp0
8873 0, // sub_dmrrowp1
8874 0, // sub_eq
8875 0, // sub_fp0
8876 0, // sub_fp1
8877 0, // sub_gp8_x0
8878 0, // sub_gp8_x1
8879 0, // sub_gt
8880 0, // sub_lt
8881 0, // sub_pair0
8882 0, // sub_pair1
8883 0, // sub_un
8884 0, // sub_vsx0
8885 0, // sub_vsx1
8886 0, // sub_wacc_hi
8887 0, // sub_wacc_lo
8888 0, // sub_vsx1_then_sub_64
8889 0, // sub_vsx1_then_sub_64_hi_phony
8890 0, // sub_pair1_then_sub_64
8891 0, // sub_pair1_then_sub_64_hi_phony
8892 0, // sub_pair1_then_sub_vsx0
8893 0, // sub_pair1_then_sub_vsx1
8894 0, // sub_pair1_then_sub_vsx1_then_sub_64
8895 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8896 0, // sub_dmrrowp1_then_sub_dmrrow0
8897 0, // sub_dmrrowp1_then_sub_dmrrow1
8898 0, // sub_wacc_hi_then_sub_dmrrow0
8899 0, // sub_wacc_hi_then_sub_dmrrow1
8900 0, // sub_wacc_hi_then_sub_dmrrowp0
8901 0, // sub_wacc_hi_then_sub_dmrrowp1
8902 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8903 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8904 0, // sub_dmr1_then_sub_dmrrow0
8905 0, // sub_dmr1_then_sub_dmrrow1
8906 0, // sub_dmr1_then_sub_dmrrowp0
8907 0, // sub_dmr1_then_sub_dmrrowp1
8908 0, // sub_dmr1_then_sub_wacc_hi
8909 0, // sub_dmr1_then_sub_wacc_lo
8910 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8911 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8912 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8913 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8914 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8915 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8916 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8917 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8918 0, // sub_gp8_x1_then_sub_32
8919 },
8920 { // SPERC_with_sub_32_in_GPRC_NOR0
8921 24, // sub_32 -> SPERC_with_sub_32_in_GPRC_NOR0
8922 24, // sub_32_hi_phony -> SPERC_with_sub_32_in_GPRC_NOR0
8923 0, // sub_64
8924 0, // sub_64_hi_phony
8925 0, // sub_dmr0
8926 0, // sub_dmr1
8927 0, // sub_dmrrow0
8928 0, // sub_dmrrow1
8929 0, // sub_dmrrowp0
8930 0, // sub_dmrrowp1
8931 0, // sub_eq
8932 0, // sub_fp0
8933 0, // sub_fp1
8934 0, // sub_gp8_x0
8935 0, // sub_gp8_x1
8936 0, // sub_gt
8937 0, // sub_lt
8938 0, // sub_pair0
8939 0, // sub_pair1
8940 0, // sub_un
8941 0, // sub_vsx0
8942 0, // sub_vsx1
8943 0, // sub_wacc_hi
8944 0, // sub_wacc_lo
8945 0, // sub_vsx1_then_sub_64
8946 0, // sub_vsx1_then_sub_64_hi_phony
8947 0, // sub_pair1_then_sub_64
8948 0, // sub_pair1_then_sub_64_hi_phony
8949 0, // sub_pair1_then_sub_vsx0
8950 0, // sub_pair1_then_sub_vsx1
8951 0, // sub_pair1_then_sub_vsx1_then_sub_64
8952 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
8953 0, // sub_dmrrowp1_then_sub_dmrrow0
8954 0, // sub_dmrrowp1_then_sub_dmrrow1
8955 0, // sub_wacc_hi_then_sub_dmrrow0
8956 0, // sub_wacc_hi_then_sub_dmrrow1
8957 0, // sub_wacc_hi_then_sub_dmrrowp0
8958 0, // sub_wacc_hi_then_sub_dmrrowp1
8959 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8960 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8961 0, // sub_dmr1_then_sub_dmrrow0
8962 0, // sub_dmr1_then_sub_dmrrow1
8963 0, // sub_dmr1_then_sub_dmrrowp0
8964 0, // sub_dmr1_then_sub_dmrrowp1
8965 0, // sub_dmr1_then_sub_wacc_hi
8966 0, // sub_dmr1_then_sub_wacc_lo
8967 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
8968 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
8969 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
8970 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
8971 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
8972 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
8973 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
8974 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
8975 0, // sub_gp8_x1_then_sub_32
8976 },
8977 { // SPILLTOVSRRC_and_VFRC
8978 0, // sub_32
8979 0, // sub_32_hi_phony
8980 0, // sub_64
8981 0, // sub_64_hi_phony
8982 0, // sub_dmr0
8983 0, // sub_dmr1
8984 0, // sub_dmrrow0
8985 0, // sub_dmrrow1
8986 0, // sub_dmrrowp0
8987 0, // sub_dmrrowp1
8988 0, // sub_eq
8989 0, // sub_fp0
8990 0, // sub_fp1
8991 0, // sub_gp8_x0
8992 0, // sub_gp8_x1
8993 0, // sub_gt
8994 0, // sub_lt
8995 0, // sub_pair0
8996 0, // sub_pair1
8997 0, // sub_un
8998 0, // sub_vsx0
8999 0, // sub_vsx1
9000 0, // sub_wacc_hi
9001 0, // sub_wacc_lo
9002 0, // sub_vsx1_then_sub_64
9003 0, // sub_vsx1_then_sub_64_hi_phony
9004 0, // sub_pair1_then_sub_64
9005 0, // sub_pair1_then_sub_64_hi_phony
9006 0, // sub_pair1_then_sub_vsx0
9007 0, // sub_pair1_then_sub_vsx1
9008 0, // sub_pair1_then_sub_vsx1_then_sub_64
9009 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9010 0, // sub_dmrrowp1_then_sub_dmrrow0
9011 0, // sub_dmrrowp1_then_sub_dmrrow1
9012 0, // sub_wacc_hi_then_sub_dmrrow0
9013 0, // sub_wacc_hi_then_sub_dmrrow1
9014 0, // sub_wacc_hi_then_sub_dmrrowp0
9015 0, // sub_wacc_hi_then_sub_dmrrowp1
9016 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9017 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9018 0, // sub_dmr1_then_sub_dmrrow0
9019 0, // sub_dmr1_then_sub_dmrrow1
9020 0, // sub_dmr1_then_sub_dmrrowp0
9021 0, // sub_dmr1_then_sub_dmrrowp1
9022 0, // sub_dmr1_then_sub_wacc_hi
9023 0, // sub_dmr1_then_sub_wacc_lo
9024 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9025 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9026 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9027 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9028 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9029 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9030 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9031 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9032 0, // sub_gp8_x1_then_sub_32
9033 },
9034 { // SPILLTOVSRRC_and_F4RC
9035 0, // sub_32
9036 0, // sub_32_hi_phony
9037 0, // sub_64
9038 0, // sub_64_hi_phony
9039 0, // sub_dmr0
9040 0, // sub_dmr1
9041 0, // sub_dmrrow0
9042 0, // sub_dmrrow1
9043 0, // sub_dmrrowp0
9044 0, // sub_dmrrowp1
9045 0, // sub_eq
9046 0, // sub_fp0
9047 0, // sub_fp1
9048 0, // sub_gp8_x0
9049 0, // sub_gp8_x1
9050 0, // sub_gt
9051 0, // sub_lt
9052 0, // sub_pair0
9053 0, // sub_pair1
9054 0, // sub_un
9055 0, // sub_vsx0
9056 0, // sub_vsx1
9057 0, // sub_wacc_hi
9058 0, // sub_wacc_lo
9059 0, // sub_vsx1_then_sub_64
9060 0, // sub_vsx1_then_sub_64_hi_phony
9061 0, // sub_pair1_then_sub_64
9062 0, // sub_pair1_then_sub_64_hi_phony
9063 0, // sub_pair1_then_sub_vsx0
9064 0, // sub_pair1_then_sub_vsx1
9065 0, // sub_pair1_then_sub_vsx1_then_sub_64
9066 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9067 0, // sub_dmrrowp1_then_sub_dmrrow0
9068 0, // sub_dmrrowp1_then_sub_dmrrow1
9069 0, // sub_wacc_hi_then_sub_dmrrow0
9070 0, // sub_wacc_hi_then_sub_dmrrow1
9071 0, // sub_wacc_hi_then_sub_dmrrowp0
9072 0, // sub_wacc_hi_then_sub_dmrrowp1
9073 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9074 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9075 0, // sub_dmr1_then_sub_dmrrow0
9076 0, // sub_dmr1_then_sub_dmrrow1
9077 0, // sub_dmr1_then_sub_dmrrowp0
9078 0, // sub_dmr1_then_sub_dmrrowp1
9079 0, // sub_dmr1_then_sub_wacc_hi
9080 0, // sub_dmr1_then_sub_wacc_lo
9081 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9082 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9083 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9084 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9085 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9086 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9087 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9088 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9089 0, // sub_gp8_x1_then_sub_32
9090 },
9091 { // CTRRC8
9092 0, // sub_32
9093 0, // sub_32_hi_phony
9094 0, // sub_64
9095 0, // sub_64_hi_phony
9096 0, // sub_dmr0
9097 0, // sub_dmr1
9098 0, // sub_dmrrow0
9099 0, // sub_dmrrow1
9100 0, // sub_dmrrowp0
9101 0, // sub_dmrrowp1
9102 0, // sub_eq
9103 0, // sub_fp0
9104 0, // sub_fp1
9105 0, // sub_gp8_x0
9106 0, // sub_gp8_x1
9107 0, // sub_gt
9108 0, // sub_lt
9109 0, // sub_pair0
9110 0, // sub_pair1
9111 0, // sub_un
9112 0, // sub_vsx0
9113 0, // sub_vsx1
9114 0, // sub_wacc_hi
9115 0, // sub_wacc_lo
9116 0, // sub_vsx1_then_sub_64
9117 0, // sub_vsx1_then_sub_64_hi_phony
9118 0, // sub_pair1_then_sub_64
9119 0, // sub_pair1_then_sub_64_hi_phony
9120 0, // sub_pair1_then_sub_vsx0
9121 0, // sub_pair1_then_sub_vsx1
9122 0, // sub_pair1_then_sub_vsx1_then_sub_64
9123 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9124 0, // sub_dmrrowp1_then_sub_dmrrow0
9125 0, // sub_dmrrowp1_then_sub_dmrrow1
9126 0, // sub_wacc_hi_then_sub_dmrrow0
9127 0, // sub_wacc_hi_then_sub_dmrrow1
9128 0, // sub_wacc_hi_then_sub_dmrrowp0
9129 0, // sub_wacc_hi_then_sub_dmrrowp1
9130 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9131 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9132 0, // sub_dmr1_then_sub_dmrrow0
9133 0, // sub_dmr1_then_sub_dmrrow1
9134 0, // sub_dmr1_then_sub_dmrrowp0
9135 0, // sub_dmr1_then_sub_dmrrowp1
9136 0, // sub_dmr1_then_sub_wacc_hi
9137 0, // sub_dmr1_then_sub_wacc_lo
9138 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9139 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9140 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9141 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9142 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9143 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9144 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9145 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9146 0, // sub_gp8_x1_then_sub_32
9147 },
9148 { // LR8RC
9149 0, // sub_32
9150 0, // sub_32_hi_phony
9151 0, // sub_64
9152 0, // sub_64_hi_phony
9153 0, // sub_dmr0
9154 0, // sub_dmr1
9155 0, // sub_dmrrow0
9156 0, // sub_dmrrow1
9157 0, // sub_dmrrowp0
9158 0, // sub_dmrrowp1
9159 0, // sub_eq
9160 0, // sub_fp0
9161 0, // sub_fp1
9162 0, // sub_gp8_x0
9163 0, // sub_gp8_x1
9164 0, // sub_gt
9165 0, // sub_lt
9166 0, // sub_pair0
9167 0, // sub_pair1
9168 0, // sub_un
9169 0, // sub_vsx0
9170 0, // sub_vsx1
9171 0, // sub_wacc_hi
9172 0, // sub_wacc_lo
9173 0, // sub_vsx1_then_sub_64
9174 0, // sub_vsx1_then_sub_64_hi_phony
9175 0, // sub_pair1_then_sub_64
9176 0, // sub_pair1_then_sub_64_hi_phony
9177 0, // sub_pair1_then_sub_vsx0
9178 0, // sub_pair1_then_sub_vsx1
9179 0, // sub_pair1_then_sub_vsx1_then_sub_64
9180 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9181 0, // sub_dmrrowp1_then_sub_dmrrow0
9182 0, // sub_dmrrowp1_then_sub_dmrrow1
9183 0, // sub_wacc_hi_then_sub_dmrrow0
9184 0, // sub_wacc_hi_then_sub_dmrrow1
9185 0, // sub_wacc_hi_then_sub_dmrrowp0
9186 0, // sub_wacc_hi_then_sub_dmrrowp1
9187 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9188 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9189 0, // sub_dmr1_then_sub_dmrrow0
9190 0, // sub_dmr1_then_sub_dmrrow1
9191 0, // sub_dmr1_then_sub_dmrrowp0
9192 0, // sub_dmr1_then_sub_dmrrowp1
9193 0, // sub_dmr1_then_sub_wacc_hi
9194 0, // sub_dmr1_then_sub_wacc_lo
9195 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9196 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9197 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9198 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9199 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9200 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9201 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9202 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9203 0, // sub_gp8_x1_then_sub_32
9204 },
9205 { // DMRROWRC
9206 0, // sub_32
9207 0, // sub_32_hi_phony
9208 0, // sub_64
9209 0, // sub_64_hi_phony
9210 0, // sub_dmr0
9211 0, // sub_dmr1
9212 0, // sub_dmrrow0
9213 0, // sub_dmrrow1
9214 0, // sub_dmrrowp0
9215 0, // sub_dmrrowp1
9216 0, // sub_eq
9217 0, // sub_fp0
9218 0, // sub_fp1
9219 0, // sub_gp8_x0
9220 0, // sub_gp8_x1
9221 0, // sub_gt
9222 0, // sub_lt
9223 0, // sub_pair0
9224 0, // sub_pair1
9225 0, // sub_un
9226 0, // sub_vsx0
9227 0, // sub_vsx1
9228 0, // sub_wacc_hi
9229 0, // sub_wacc_lo
9230 0, // sub_vsx1_then_sub_64
9231 0, // sub_vsx1_then_sub_64_hi_phony
9232 0, // sub_pair1_then_sub_64
9233 0, // sub_pair1_then_sub_64_hi_phony
9234 0, // sub_pair1_then_sub_vsx0
9235 0, // sub_pair1_then_sub_vsx1
9236 0, // sub_pair1_then_sub_vsx1_then_sub_64
9237 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9238 0, // sub_dmrrowp1_then_sub_dmrrow0
9239 0, // sub_dmrrowp1_then_sub_dmrrow1
9240 0, // sub_wacc_hi_then_sub_dmrrow0
9241 0, // sub_wacc_hi_then_sub_dmrrow1
9242 0, // sub_wacc_hi_then_sub_dmrrowp0
9243 0, // sub_wacc_hi_then_sub_dmrrowp1
9244 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9245 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9246 0, // sub_dmr1_then_sub_dmrrow0
9247 0, // sub_dmr1_then_sub_dmrrow1
9248 0, // sub_dmr1_then_sub_dmrrowp0
9249 0, // sub_dmr1_then_sub_dmrrowp1
9250 0, // sub_dmr1_then_sub_wacc_hi
9251 0, // sub_dmr1_then_sub_wacc_lo
9252 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9253 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9254 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9255 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9256 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9257 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9258 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9259 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9260 0, // sub_gp8_x1_then_sub_32
9261 },
9262 { // VSRC
9263 0, // sub_32
9264 0, // sub_32_hi_phony
9265 30, // sub_64 -> VSRC
9266 30, // sub_64_hi_phony -> VSRC
9267 0, // sub_dmr0
9268 0, // sub_dmr1
9269 0, // sub_dmrrow0
9270 0, // sub_dmrrow1
9271 0, // sub_dmrrowp0
9272 0, // sub_dmrrowp1
9273 0, // sub_eq
9274 0, // sub_fp0
9275 0, // sub_fp1
9276 0, // sub_gp8_x0
9277 0, // sub_gp8_x1
9278 0, // sub_gt
9279 0, // sub_lt
9280 0, // sub_pair0
9281 0, // sub_pair1
9282 0, // sub_un
9283 0, // sub_vsx0
9284 0, // sub_vsx1
9285 0, // sub_wacc_hi
9286 0, // sub_wacc_lo
9287 0, // sub_vsx1_then_sub_64
9288 0, // sub_vsx1_then_sub_64_hi_phony
9289 0, // sub_pair1_then_sub_64
9290 0, // sub_pair1_then_sub_64_hi_phony
9291 0, // sub_pair1_then_sub_vsx0
9292 0, // sub_pair1_then_sub_vsx1
9293 0, // sub_pair1_then_sub_vsx1_then_sub_64
9294 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9295 0, // sub_dmrrowp1_then_sub_dmrrow0
9296 0, // sub_dmrrowp1_then_sub_dmrrow1
9297 0, // sub_wacc_hi_then_sub_dmrrow0
9298 0, // sub_wacc_hi_then_sub_dmrrow1
9299 0, // sub_wacc_hi_then_sub_dmrrowp0
9300 0, // sub_wacc_hi_then_sub_dmrrowp1
9301 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9302 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9303 0, // sub_dmr1_then_sub_dmrrow0
9304 0, // sub_dmr1_then_sub_dmrrow1
9305 0, // sub_dmr1_then_sub_dmrrowp0
9306 0, // sub_dmr1_then_sub_dmrrowp1
9307 0, // sub_dmr1_then_sub_wacc_hi
9308 0, // sub_dmr1_then_sub_wacc_lo
9309 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9310 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9311 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9312 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9313 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9314 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9315 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9316 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9317 0, // sub_gp8_x1_then_sub_32
9318 },
9319 { // VSRC_with_sub_64_in_SPILLTOVSRRC
9320 0, // sub_32
9321 0, // sub_32_hi_phony
9322 31, // sub_64 -> VSRC_with_sub_64_in_SPILLTOVSRRC
9323 31, // sub_64_hi_phony -> VSRC_with_sub_64_in_SPILLTOVSRRC
9324 0, // sub_dmr0
9325 0, // sub_dmr1
9326 0, // sub_dmrrow0
9327 0, // sub_dmrrow1
9328 0, // sub_dmrrowp0
9329 0, // sub_dmrrowp1
9330 0, // sub_eq
9331 0, // sub_fp0
9332 0, // sub_fp1
9333 0, // sub_gp8_x0
9334 0, // sub_gp8_x1
9335 0, // sub_gt
9336 0, // sub_lt
9337 0, // sub_pair0
9338 0, // sub_pair1
9339 0, // sub_un
9340 0, // sub_vsx0
9341 0, // sub_vsx1
9342 0, // sub_wacc_hi
9343 0, // sub_wacc_lo
9344 0, // sub_vsx1_then_sub_64
9345 0, // sub_vsx1_then_sub_64_hi_phony
9346 0, // sub_pair1_then_sub_64
9347 0, // sub_pair1_then_sub_64_hi_phony
9348 0, // sub_pair1_then_sub_vsx0
9349 0, // sub_pair1_then_sub_vsx1
9350 0, // sub_pair1_then_sub_vsx1_then_sub_64
9351 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9352 0, // sub_dmrrowp1_then_sub_dmrrow0
9353 0, // sub_dmrrowp1_then_sub_dmrrow1
9354 0, // sub_wacc_hi_then_sub_dmrrow0
9355 0, // sub_wacc_hi_then_sub_dmrrow1
9356 0, // sub_wacc_hi_then_sub_dmrrowp0
9357 0, // sub_wacc_hi_then_sub_dmrrowp1
9358 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9359 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9360 0, // sub_dmr1_then_sub_dmrrow0
9361 0, // sub_dmr1_then_sub_dmrrow1
9362 0, // sub_dmr1_then_sub_dmrrowp0
9363 0, // sub_dmr1_then_sub_dmrrowp1
9364 0, // sub_dmr1_then_sub_wacc_hi
9365 0, // sub_dmr1_then_sub_wacc_lo
9366 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9367 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9368 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9369 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9370 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9371 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9372 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9373 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9374 0, // sub_gp8_x1_then_sub_32
9375 },
9376 { // VRRC
9377 0, // sub_32
9378 0, // sub_32_hi_phony
9379 32, // sub_64 -> VRRC
9380 32, // sub_64_hi_phony -> VRRC
9381 0, // sub_dmr0
9382 0, // sub_dmr1
9383 0, // sub_dmrrow0
9384 0, // sub_dmrrow1
9385 0, // sub_dmrrowp0
9386 0, // sub_dmrrowp1
9387 0, // sub_eq
9388 0, // sub_fp0
9389 0, // sub_fp1
9390 0, // sub_gp8_x0
9391 0, // sub_gp8_x1
9392 0, // sub_gt
9393 0, // sub_lt
9394 0, // sub_pair0
9395 0, // sub_pair1
9396 0, // sub_un
9397 0, // sub_vsx0
9398 0, // sub_vsx1
9399 0, // sub_wacc_hi
9400 0, // sub_wacc_lo
9401 0, // sub_vsx1_then_sub_64
9402 0, // sub_vsx1_then_sub_64_hi_phony
9403 0, // sub_pair1_then_sub_64
9404 0, // sub_pair1_then_sub_64_hi_phony
9405 0, // sub_pair1_then_sub_vsx0
9406 0, // sub_pair1_then_sub_vsx1
9407 0, // sub_pair1_then_sub_vsx1_then_sub_64
9408 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9409 0, // sub_dmrrowp1_then_sub_dmrrow0
9410 0, // sub_dmrrowp1_then_sub_dmrrow1
9411 0, // sub_wacc_hi_then_sub_dmrrow0
9412 0, // sub_wacc_hi_then_sub_dmrrow1
9413 0, // sub_wacc_hi_then_sub_dmrrowp0
9414 0, // sub_wacc_hi_then_sub_dmrrowp1
9415 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9416 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9417 0, // sub_dmr1_then_sub_dmrrow0
9418 0, // sub_dmr1_then_sub_dmrrow1
9419 0, // sub_dmr1_then_sub_dmrrowp0
9420 0, // sub_dmr1_then_sub_dmrrowp1
9421 0, // sub_dmr1_then_sub_wacc_hi
9422 0, // sub_dmr1_then_sub_wacc_lo
9423 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9424 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9425 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9426 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9427 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9428 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9429 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9430 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9431 0, // sub_gp8_x1_then_sub_32
9432 },
9433 { // VSLRC
9434 0, // sub_32
9435 0, // sub_32_hi_phony
9436 33, // sub_64 -> VSLRC
9437 33, // sub_64_hi_phony -> VSLRC
9438 0, // sub_dmr0
9439 0, // sub_dmr1
9440 0, // sub_dmrrow0
9441 0, // sub_dmrrow1
9442 0, // sub_dmrrowp0
9443 0, // sub_dmrrowp1
9444 0, // sub_eq
9445 0, // sub_fp0
9446 0, // sub_fp1
9447 0, // sub_gp8_x0
9448 0, // sub_gp8_x1
9449 0, // sub_gt
9450 0, // sub_lt
9451 0, // sub_pair0
9452 0, // sub_pair1
9453 0, // sub_un
9454 0, // sub_vsx0
9455 0, // sub_vsx1
9456 0, // sub_wacc_hi
9457 0, // sub_wacc_lo
9458 0, // sub_vsx1_then_sub_64
9459 0, // sub_vsx1_then_sub_64_hi_phony
9460 0, // sub_pair1_then_sub_64
9461 0, // sub_pair1_then_sub_64_hi_phony
9462 0, // sub_pair1_then_sub_vsx0
9463 0, // sub_pair1_then_sub_vsx1
9464 0, // sub_pair1_then_sub_vsx1_then_sub_64
9465 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9466 0, // sub_dmrrowp1_then_sub_dmrrow0
9467 0, // sub_dmrrowp1_then_sub_dmrrow1
9468 0, // sub_wacc_hi_then_sub_dmrrow0
9469 0, // sub_wacc_hi_then_sub_dmrrow1
9470 0, // sub_wacc_hi_then_sub_dmrrowp0
9471 0, // sub_wacc_hi_then_sub_dmrrowp1
9472 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9473 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9474 0, // sub_dmr1_then_sub_dmrrow0
9475 0, // sub_dmr1_then_sub_dmrrow1
9476 0, // sub_dmr1_then_sub_dmrrowp0
9477 0, // sub_dmr1_then_sub_dmrrowp1
9478 0, // sub_dmr1_then_sub_wacc_hi
9479 0, // sub_dmr1_then_sub_wacc_lo
9480 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9481 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9482 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9483 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9484 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9485 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9486 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9487 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9488 0, // sub_gp8_x1_then_sub_32
9489 },
9490 { // VRRC_with_sub_64_in_SPILLTOVSRRC
9491 0, // sub_32
9492 0, // sub_32_hi_phony
9493 34, // sub_64 -> VRRC_with_sub_64_in_SPILLTOVSRRC
9494 34, // sub_64_hi_phony -> VRRC_with_sub_64_in_SPILLTOVSRRC
9495 0, // sub_dmr0
9496 0, // sub_dmr1
9497 0, // sub_dmrrow0
9498 0, // sub_dmrrow1
9499 0, // sub_dmrrowp0
9500 0, // sub_dmrrowp1
9501 0, // sub_eq
9502 0, // sub_fp0
9503 0, // sub_fp1
9504 0, // sub_gp8_x0
9505 0, // sub_gp8_x1
9506 0, // sub_gt
9507 0, // sub_lt
9508 0, // sub_pair0
9509 0, // sub_pair1
9510 0, // sub_un
9511 0, // sub_vsx0
9512 0, // sub_vsx1
9513 0, // sub_wacc_hi
9514 0, // sub_wacc_lo
9515 0, // sub_vsx1_then_sub_64
9516 0, // sub_vsx1_then_sub_64_hi_phony
9517 0, // sub_pair1_then_sub_64
9518 0, // sub_pair1_then_sub_64_hi_phony
9519 0, // sub_pair1_then_sub_vsx0
9520 0, // sub_pair1_then_sub_vsx1
9521 0, // sub_pair1_then_sub_vsx1_then_sub_64
9522 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9523 0, // sub_dmrrowp1_then_sub_dmrrow0
9524 0, // sub_dmrrowp1_then_sub_dmrrow1
9525 0, // sub_wacc_hi_then_sub_dmrrow0
9526 0, // sub_wacc_hi_then_sub_dmrrow1
9527 0, // sub_wacc_hi_then_sub_dmrrowp0
9528 0, // sub_wacc_hi_then_sub_dmrrowp1
9529 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9530 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9531 0, // sub_dmr1_then_sub_dmrrow0
9532 0, // sub_dmr1_then_sub_dmrrow1
9533 0, // sub_dmr1_then_sub_dmrrowp0
9534 0, // sub_dmr1_then_sub_dmrrowp1
9535 0, // sub_dmr1_then_sub_wacc_hi
9536 0, // sub_dmr1_then_sub_wacc_lo
9537 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9538 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9539 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9540 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9541 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9542 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9543 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9544 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9545 0, // sub_gp8_x1_then_sub_32
9546 },
9547 { // FpRC
9548 0, // sub_32
9549 0, // sub_32_hi_phony
9550 0, // sub_64
9551 0, // sub_64_hi_phony
9552 0, // sub_dmr0
9553 0, // sub_dmr1
9554 0, // sub_dmrrow0
9555 0, // sub_dmrrow1
9556 0, // sub_dmrrowp0
9557 0, // sub_dmrrowp1
9558 0, // sub_eq
9559 35, // sub_fp0 -> FpRC
9560 35, // sub_fp1 -> FpRC
9561 0, // sub_gp8_x0
9562 0, // sub_gp8_x1
9563 0, // sub_gt
9564 0, // sub_lt
9565 0, // sub_pair0
9566 0, // sub_pair1
9567 0, // sub_un
9568 0, // sub_vsx0
9569 0, // sub_vsx1
9570 0, // sub_wacc_hi
9571 0, // sub_wacc_lo
9572 0, // sub_vsx1_then_sub_64
9573 0, // sub_vsx1_then_sub_64_hi_phony
9574 0, // sub_pair1_then_sub_64
9575 0, // sub_pair1_then_sub_64_hi_phony
9576 0, // sub_pair1_then_sub_vsx0
9577 0, // sub_pair1_then_sub_vsx1
9578 0, // sub_pair1_then_sub_vsx1_then_sub_64
9579 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9580 0, // sub_dmrrowp1_then_sub_dmrrow0
9581 0, // sub_dmrrowp1_then_sub_dmrrow1
9582 0, // sub_wacc_hi_then_sub_dmrrow0
9583 0, // sub_wacc_hi_then_sub_dmrrow1
9584 0, // sub_wacc_hi_then_sub_dmrrowp0
9585 0, // sub_wacc_hi_then_sub_dmrrowp1
9586 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9587 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9588 0, // sub_dmr1_then_sub_dmrrow0
9589 0, // sub_dmr1_then_sub_dmrrow1
9590 0, // sub_dmr1_then_sub_dmrrowp0
9591 0, // sub_dmr1_then_sub_dmrrowp1
9592 0, // sub_dmr1_then_sub_wacc_hi
9593 0, // sub_dmr1_then_sub_wacc_lo
9594 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9595 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9596 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9597 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9598 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9599 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9600 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9601 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9602 0, // sub_gp8_x1_then_sub_32
9603 },
9604 { // G8pRC
9605 36, // sub_32 -> G8pRC
9606 0, // sub_32_hi_phony
9607 0, // sub_64
9608 0, // sub_64_hi_phony
9609 0, // sub_dmr0
9610 0, // sub_dmr1
9611 0, // sub_dmrrow0
9612 0, // sub_dmrrow1
9613 0, // sub_dmrrowp0
9614 0, // sub_dmrrowp1
9615 0, // sub_eq
9616 0, // sub_fp0
9617 0, // sub_fp1
9618 36, // sub_gp8_x0 -> G8pRC
9619 36, // sub_gp8_x1 -> G8pRC
9620 0, // sub_gt
9621 0, // sub_lt
9622 0, // sub_pair0
9623 0, // sub_pair1
9624 0, // sub_un
9625 0, // sub_vsx0
9626 0, // sub_vsx1
9627 0, // sub_wacc_hi
9628 0, // sub_wacc_lo
9629 0, // sub_vsx1_then_sub_64
9630 0, // sub_vsx1_then_sub_64_hi_phony
9631 0, // sub_pair1_then_sub_64
9632 0, // sub_pair1_then_sub_64_hi_phony
9633 0, // sub_pair1_then_sub_vsx0
9634 0, // sub_pair1_then_sub_vsx1
9635 0, // sub_pair1_then_sub_vsx1_then_sub_64
9636 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9637 0, // sub_dmrrowp1_then_sub_dmrrow0
9638 0, // sub_dmrrowp1_then_sub_dmrrow1
9639 0, // sub_wacc_hi_then_sub_dmrrow0
9640 0, // sub_wacc_hi_then_sub_dmrrow1
9641 0, // sub_wacc_hi_then_sub_dmrrowp0
9642 0, // sub_wacc_hi_then_sub_dmrrowp1
9643 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9644 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9645 0, // sub_dmr1_then_sub_dmrrow0
9646 0, // sub_dmr1_then_sub_dmrrow1
9647 0, // sub_dmr1_then_sub_dmrrowp0
9648 0, // sub_dmr1_then_sub_dmrrowp1
9649 0, // sub_dmr1_then_sub_wacc_hi
9650 0, // sub_dmr1_then_sub_wacc_lo
9651 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9652 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9653 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9654 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9655 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9656 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9657 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9658 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9659 36, // sub_gp8_x1_then_sub_32 -> G8pRC
9660 },
9661 { // G8pRC_with_sub_32_in_GPRC_NOR0
9662 37, // sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
9663 0, // sub_32_hi_phony
9664 0, // sub_64
9665 0, // sub_64_hi_phony
9666 0, // sub_dmr0
9667 0, // sub_dmr1
9668 0, // sub_dmrrow0
9669 0, // sub_dmrrow1
9670 0, // sub_dmrrowp0
9671 0, // sub_dmrrowp1
9672 0, // sub_eq
9673 0, // sub_fp0
9674 0, // sub_fp1
9675 37, // sub_gp8_x0 -> G8pRC_with_sub_32_in_GPRC_NOR0
9676 37, // sub_gp8_x1 -> G8pRC_with_sub_32_in_GPRC_NOR0
9677 0, // sub_gt
9678 0, // sub_lt
9679 0, // sub_pair0
9680 0, // sub_pair1
9681 0, // sub_un
9682 0, // sub_vsx0
9683 0, // sub_vsx1
9684 0, // sub_wacc_hi
9685 0, // sub_wacc_lo
9686 0, // sub_vsx1_then_sub_64
9687 0, // sub_vsx1_then_sub_64_hi_phony
9688 0, // sub_pair1_then_sub_64
9689 0, // sub_pair1_then_sub_64_hi_phony
9690 0, // sub_pair1_then_sub_vsx0
9691 0, // sub_pair1_then_sub_vsx1
9692 0, // sub_pair1_then_sub_vsx1_then_sub_64
9693 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9694 0, // sub_dmrrowp1_then_sub_dmrrow0
9695 0, // sub_dmrrowp1_then_sub_dmrrow1
9696 0, // sub_wacc_hi_then_sub_dmrrow0
9697 0, // sub_wacc_hi_then_sub_dmrrow1
9698 0, // sub_wacc_hi_then_sub_dmrrowp0
9699 0, // sub_wacc_hi_then_sub_dmrrowp1
9700 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9701 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9702 0, // sub_dmr1_then_sub_dmrrow0
9703 0, // sub_dmr1_then_sub_dmrrow1
9704 0, // sub_dmr1_then_sub_dmrrowp0
9705 0, // sub_dmr1_then_sub_dmrrowp1
9706 0, // sub_dmr1_then_sub_wacc_hi
9707 0, // sub_dmr1_then_sub_wacc_lo
9708 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9709 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9710 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9711 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9712 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9713 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9714 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9715 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9716 37, // sub_gp8_x1_then_sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
9717 },
9718 { // VSLRC_with_sub_64_in_SPILLTOVSRRC
9719 0, // sub_32
9720 0, // sub_32_hi_phony
9721 38, // sub_64 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
9722 38, // sub_64_hi_phony -> VSLRC_with_sub_64_in_SPILLTOVSRRC
9723 0, // sub_dmr0
9724 0, // sub_dmr1
9725 0, // sub_dmrrow0
9726 0, // sub_dmrrow1
9727 0, // sub_dmrrowp0
9728 0, // sub_dmrrowp1
9729 0, // sub_eq
9730 0, // sub_fp0
9731 0, // sub_fp1
9732 0, // sub_gp8_x0
9733 0, // sub_gp8_x1
9734 0, // sub_gt
9735 0, // sub_lt
9736 0, // sub_pair0
9737 0, // sub_pair1
9738 0, // sub_un
9739 0, // sub_vsx0
9740 0, // sub_vsx1
9741 0, // sub_wacc_hi
9742 0, // sub_wacc_lo
9743 0, // sub_vsx1_then_sub_64
9744 0, // sub_vsx1_then_sub_64_hi_phony
9745 0, // sub_pair1_then_sub_64
9746 0, // sub_pair1_then_sub_64_hi_phony
9747 0, // sub_pair1_then_sub_vsx0
9748 0, // sub_pair1_then_sub_vsx1
9749 0, // sub_pair1_then_sub_vsx1_then_sub_64
9750 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9751 0, // sub_dmrrowp1_then_sub_dmrrow0
9752 0, // sub_dmrrowp1_then_sub_dmrrow1
9753 0, // sub_wacc_hi_then_sub_dmrrow0
9754 0, // sub_wacc_hi_then_sub_dmrrow1
9755 0, // sub_wacc_hi_then_sub_dmrrowp0
9756 0, // sub_wacc_hi_then_sub_dmrrowp1
9757 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9758 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9759 0, // sub_dmr1_then_sub_dmrrow0
9760 0, // sub_dmr1_then_sub_dmrrow1
9761 0, // sub_dmr1_then_sub_dmrrowp0
9762 0, // sub_dmr1_then_sub_dmrrowp1
9763 0, // sub_dmr1_then_sub_wacc_hi
9764 0, // sub_dmr1_then_sub_wacc_lo
9765 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9766 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9767 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9768 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9769 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9770 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9771 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9772 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9773 0, // sub_gp8_x1_then_sub_32
9774 },
9775 { // FpRC_with_sub_fp0_in_SPILLTOVSRRC
9776 0, // sub_32
9777 0, // sub_32_hi_phony
9778 0, // sub_64
9779 0, // sub_64_hi_phony
9780 0, // sub_dmr0
9781 0, // sub_dmr1
9782 0, // sub_dmrrow0
9783 0, // sub_dmrrow1
9784 0, // sub_dmrrowp0
9785 0, // sub_dmrrowp1
9786 0, // sub_eq
9787 39, // sub_fp0 -> FpRC_with_sub_fp0_in_SPILLTOVSRRC
9788 39, // sub_fp1 -> FpRC_with_sub_fp0_in_SPILLTOVSRRC
9789 0, // sub_gp8_x0
9790 0, // sub_gp8_x1
9791 0, // sub_gt
9792 0, // sub_lt
9793 0, // sub_pair0
9794 0, // sub_pair1
9795 0, // sub_un
9796 0, // sub_vsx0
9797 0, // sub_vsx1
9798 0, // sub_wacc_hi
9799 0, // sub_wacc_lo
9800 0, // sub_vsx1_then_sub_64
9801 0, // sub_vsx1_then_sub_64_hi_phony
9802 0, // sub_pair1_then_sub_64
9803 0, // sub_pair1_then_sub_64_hi_phony
9804 0, // sub_pair1_then_sub_vsx0
9805 0, // sub_pair1_then_sub_vsx1
9806 0, // sub_pair1_then_sub_vsx1_then_sub_64
9807 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9808 0, // sub_dmrrowp1_then_sub_dmrrow0
9809 0, // sub_dmrrowp1_then_sub_dmrrow1
9810 0, // sub_wacc_hi_then_sub_dmrrow0
9811 0, // sub_wacc_hi_then_sub_dmrrow1
9812 0, // sub_wacc_hi_then_sub_dmrrowp0
9813 0, // sub_wacc_hi_then_sub_dmrrowp1
9814 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9815 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9816 0, // sub_dmr1_then_sub_dmrrow0
9817 0, // sub_dmr1_then_sub_dmrrow1
9818 0, // sub_dmr1_then_sub_dmrrowp0
9819 0, // sub_dmr1_then_sub_dmrrowp1
9820 0, // sub_dmr1_then_sub_wacc_hi
9821 0, // sub_dmr1_then_sub_wacc_lo
9822 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9823 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9824 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9825 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9826 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9827 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9828 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9829 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9830 0, // sub_gp8_x1_then_sub_32
9831 },
9832 { // DMRROWpRC
9833 0, // sub_32
9834 0, // sub_32_hi_phony
9835 0, // sub_64
9836 0, // sub_64_hi_phony
9837 0, // sub_dmr0
9838 0, // sub_dmr1
9839 40, // sub_dmrrow0 -> DMRROWpRC
9840 40, // sub_dmrrow1 -> DMRROWpRC
9841 0, // sub_dmrrowp0
9842 0, // sub_dmrrowp1
9843 0, // sub_eq
9844 0, // sub_fp0
9845 0, // sub_fp1
9846 0, // sub_gp8_x0
9847 0, // sub_gp8_x1
9848 0, // sub_gt
9849 0, // sub_lt
9850 0, // sub_pair0
9851 0, // sub_pair1
9852 0, // sub_un
9853 0, // sub_vsx0
9854 0, // sub_vsx1
9855 0, // sub_wacc_hi
9856 0, // sub_wacc_lo
9857 0, // sub_vsx1_then_sub_64
9858 0, // sub_vsx1_then_sub_64_hi_phony
9859 0, // sub_pair1_then_sub_64
9860 0, // sub_pair1_then_sub_64_hi_phony
9861 0, // sub_pair1_then_sub_vsx0
9862 0, // sub_pair1_then_sub_vsx1
9863 0, // sub_pair1_then_sub_vsx1_then_sub_64
9864 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9865 0, // sub_dmrrowp1_then_sub_dmrrow0
9866 0, // sub_dmrrowp1_then_sub_dmrrow1
9867 0, // sub_wacc_hi_then_sub_dmrrow0
9868 0, // sub_wacc_hi_then_sub_dmrrow1
9869 0, // sub_wacc_hi_then_sub_dmrrowp0
9870 0, // sub_wacc_hi_then_sub_dmrrowp1
9871 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9872 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9873 0, // sub_dmr1_then_sub_dmrrow0
9874 0, // sub_dmr1_then_sub_dmrrow1
9875 0, // sub_dmr1_then_sub_dmrrowp0
9876 0, // sub_dmr1_then_sub_dmrrowp1
9877 0, // sub_dmr1_then_sub_wacc_hi
9878 0, // sub_dmr1_then_sub_wacc_lo
9879 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9880 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9881 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9882 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9883 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9884 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9885 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9886 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9887 0, // sub_gp8_x1_then_sub_32
9888 },
9889 { // VSRpRC
9890 0, // sub_32
9891 0, // sub_32_hi_phony
9892 41, // sub_64 -> VSRpRC
9893 41, // sub_64_hi_phony -> VSRpRC
9894 0, // sub_dmr0
9895 0, // sub_dmr1
9896 0, // sub_dmrrow0
9897 0, // sub_dmrrow1
9898 0, // sub_dmrrowp0
9899 0, // sub_dmrrowp1
9900 0, // sub_eq
9901 0, // sub_fp0
9902 0, // sub_fp1
9903 0, // sub_gp8_x0
9904 0, // sub_gp8_x1
9905 0, // sub_gt
9906 0, // sub_lt
9907 0, // sub_pair0
9908 0, // sub_pair1
9909 0, // sub_un
9910 41, // sub_vsx0 -> VSRpRC
9911 41, // sub_vsx1 -> VSRpRC
9912 0, // sub_wacc_hi
9913 0, // sub_wacc_lo
9914 41, // sub_vsx1_then_sub_64 -> VSRpRC
9915 41, // sub_vsx1_then_sub_64_hi_phony -> VSRpRC
9916 0, // sub_pair1_then_sub_64
9917 0, // sub_pair1_then_sub_64_hi_phony
9918 0, // sub_pair1_then_sub_vsx0
9919 0, // sub_pair1_then_sub_vsx1
9920 0, // sub_pair1_then_sub_vsx1_then_sub_64
9921 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9922 0, // sub_dmrrowp1_then_sub_dmrrow0
9923 0, // sub_dmrrowp1_then_sub_dmrrow1
9924 0, // sub_wacc_hi_then_sub_dmrrow0
9925 0, // sub_wacc_hi_then_sub_dmrrow1
9926 0, // sub_wacc_hi_then_sub_dmrrowp0
9927 0, // sub_wacc_hi_then_sub_dmrrowp1
9928 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9929 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9930 0, // sub_dmr1_then_sub_dmrrow0
9931 0, // sub_dmr1_then_sub_dmrrow1
9932 0, // sub_dmr1_then_sub_dmrrowp0
9933 0, // sub_dmr1_then_sub_dmrrowp1
9934 0, // sub_dmr1_then_sub_wacc_hi
9935 0, // sub_dmr1_then_sub_wacc_lo
9936 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9937 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9938 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9939 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9940 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9941 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9942 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9943 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9944 0, // sub_gp8_x1_then_sub_32
9945 },
9946 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC
9947 0, // sub_32
9948 0, // sub_32_hi_phony
9949 42, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9950 42, // sub_64_hi_phony -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9951 0, // sub_dmr0
9952 0, // sub_dmr1
9953 0, // sub_dmrrow0
9954 0, // sub_dmrrow1
9955 0, // sub_dmrrowp0
9956 0, // sub_dmrrowp1
9957 0, // sub_eq
9958 0, // sub_fp0
9959 0, // sub_fp1
9960 0, // sub_gp8_x0
9961 0, // sub_gp8_x1
9962 0, // sub_gt
9963 0, // sub_lt
9964 0, // sub_pair0
9965 0, // sub_pair1
9966 0, // sub_un
9967 42, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9968 42, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9969 0, // sub_wacc_hi
9970 0, // sub_wacc_lo
9971 42, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9972 42, // sub_vsx1_then_sub_64_hi_phony -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
9973 0, // sub_pair1_then_sub_64
9974 0, // sub_pair1_then_sub_64_hi_phony
9975 0, // sub_pair1_then_sub_vsx0
9976 0, // sub_pair1_then_sub_vsx1
9977 0, // sub_pair1_then_sub_vsx1_then_sub_64
9978 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
9979 0, // sub_dmrrowp1_then_sub_dmrrow0
9980 0, // sub_dmrrowp1_then_sub_dmrrow1
9981 0, // sub_wacc_hi_then_sub_dmrrow0
9982 0, // sub_wacc_hi_then_sub_dmrrow1
9983 0, // sub_wacc_hi_then_sub_dmrrowp0
9984 0, // sub_wacc_hi_then_sub_dmrrowp1
9985 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
9986 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
9987 0, // sub_dmr1_then_sub_dmrrow0
9988 0, // sub_dmr1_then_sub_dmrrow1
9989 0, // sub_dmr1_then_sub_dmrrowp0
9990 0, // sub_dmr1_then_sub_dmrrowp1
9991 0, // sub_dmr1_then_sub_wacc_hi
9992 0, // sub_dmr1_then_sub_wacc_lo
9993 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
9994 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
9995 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
9996 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
9997 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
9998 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
9999 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10000 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10001 0, // sub_gp8_x1_then_sub_32
10002 },
10003 { // VSRpRC_with_sub_64_in_F4RC
10004 0, // sub_32
10005 0, // sub_32_hi_phony
10006 43, // sub_64 -> VSRpRC_with_sub_64_in_F4RC
10007 43, // sub_64_hi_phony -> VSRpRC_with_sub_64_in_F4RC
10008 0, // sub_dmr0
10009 0, // sub_dmr1
10010 0, // sub_dmrrow0
10011 0, // sub_dmrrow1
10012 0, // sub_dmrrowp0
10013 0, // sub_dmrrowp1
10014 0, // sub_eq
10015 0, // sub_fp0
10016 0, // sub_fp1
10017 0, // sub_gp8_x0
10018 0, // sub_gp8_x1
10019 0, // sub_gt
10020 0, // sub_lt
10021 0, // sub_pair0
10022 0, // sub_pair1
10023 0, // sub_un
10024 43, // sub_vsx0 -> VSRpRC_with_sub_64_in_F4RC
10025 43, // sub_vsx1 -> VSRpRC_with_sub_64_in_F4RC
10026 0, // sub_wacc_hi
10027 0, // sub_wacc_lo
10028 43, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_F4RC
10029 43, // sub_vsx1_then_sub_64_hi_phony -> VSRpRC_with_sub_64_in_F4RC
10030 0, // sub_pair1_then_sub_64
10031 0, // sub_pair1_then_sub_64_hi_phony
10032 0, // sub_pair1_then_sub_vsx0
10033 0, // sub_pair1_then_sub_vsx1
10034 0, // sub_pair1_then_sub_vsx1_then_sub_64
10035 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10036 0, // sub_dmrrowp1_then_sub_dmrrow0
10037 0, // sub_dmrrowp1_then_sub_dmrrow1
10038 0, // sub_wacc_hi_then_sub_dmrrow0
10039 0, // sub_wacc_hi_then_sub_dmrrow1
10040 0, // sub_wacc_hi_then_sub_dmrrowp0
10041 0, // sub_wacc_hi_then_sub_dmrrowp1
10042 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10043 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10044 0, // sub_dmr1_then_sub_dmrrow0
10045 0, // sub_dmr1_then_sub_dmrrow1
10046 0, // sub_dmr1_then_sub_dmrrowp0
10047 0, // sub_dmr1_then_sub_dmrrowp1
10048 0, // sub_dmr1_then_sub_wacc_hi
10049 0, // sub_dmr1_then_sub_wacc_lo
10050 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10051 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10052 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10053 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10054 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10055 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10056 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10057 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10058 0, // sub_gp8_x1_then_sub_32
10059 },
10060 { // VSRpRC_with_sub_64_in_VFRC
10061 0, // sub_32
10062 0, // sub_32_hi_phony
10063 44, // sub_64 -> VSRpRC_with_sub_64_in_VFRC
10064 44, // sub_64_hi_phony -> VSRpRC_with_sub_64_in_VFRC
10065 0, // sub_dmr0
10066 0, // sub_dmr1
10067 0, // sub_dmrrow0
10068 0, // sub_dmrrow1
10069 0, // sub_dmrrowp0
10070 0, // sub_dmrrowp1
10071 0, // sub_eq
10072 0, // sub_fp0
10073 0, // sub_fp1
10074 0, // sub_gp8_x0
10075 0, // sub_gp8_x1
10076 0, // sub_gt
10077 0, // sub_lt
10078 0, // sub_pair0
10079 0, // sub_pair1
10080 0, // sub_un
10081 44, // sub_vsx0 -> VSRpRC_with_sub_64_in_VFRC
10082 44, // sub_vsx1 -> VSRpRC_with_sub_64_in_VFRC
10083 0, // sub_wacc_hi
10084 0, // sub_wacc_lo
10085 44, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_VFRC
10086 44, // sub_vsx1_then_sub_64_hi_phony -> VSRpRC_with_sub_64_in_VFRC
10087 0, // sub_pair1_then_sub_64
10088 0, // sub_pair1_then_sub_64_hi_phony
10089 0, // sub_pair1_then_sub_vsx0
10090 0, // sub_pair1_then_sub_vsx1
10091 0, // sub_pair1_then_sub_vsx1_then_sub_64
10092 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10093 0, // sub_dmrrowp1_then_sub_dmrrow0
10094 0, // sub_dmrrowp1_then_sub_dmrrow1
10095 0, // sub_wacc_hi_then_sub_dmrrow0
10096 0, // sub_wacc_hi_then_sub_dmrrow1
10097 0, // sub_wacc_hi_then_sub_dmrrowp0
10098 0, // sub_wacc_hi_then_sub_dmrrowp1
10099 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10100 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10101 0, // sub_dmr1_then_sub_dmrrow0
10102 0, // sub_dmr1_then_sub_dmrrow1
10103 0, // sub_dmr1_then_sub_dmrrowp0
10104 0, // sub_dmr1_then_sub_dmrrowp1
10105 0, // sub_dmr1_then_sub_wacc_hi
10106 0, // sub_dmr1_then_sub_wacc_lo
10107 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10108 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10109 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10110 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10111 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10112 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10113 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10114 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10115 0, // sub_gp8_x1_then_sub_32
10116 },
10117 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10118 0, // sub_32
10119 0, // sub_32_hi_phony
10120 45, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10121 45, // sub_64_hi_phony -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10122 0, // sub_dmr0
10123 0, // sub_dmr1
10124 0, // sub_dmrrow0
10125 0, // sub_dmrrow1
10126 0, // sub_dmrrowp0
10127 0, // sub_dmrrowp1
10128 0, // sub_eq
10129 0, // sub_fp0
10130 0, // sub_fp1
10131 0, // sub_gp8_x0
10132 0, // sub_gp8_x1
10133 0, // sub_gt
10134 0, // sub_lt
10135 0, // sub_pair0
10136 0, // sub_pair1
10137 0, // sub_un
10138 45, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10139 45, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10140 0, // sub_wacc_hi
10141 0, // sub_wacc_lo
10142 45, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10143 45, // sub_vsx1_then_sub_64_hi_phony -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
10144 0, // sub_pair1_then_sub_64
10145 0, // sub_pair1_then_sub_64_hi_phony
10146 0, // sub_pair1_then_sub_vsx0
10147 0, // sub_pair1_then_sub_vsx1
10148 0, // sub_pair1_then_sub_vsx1_then_sub_64
10149 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10150 0, // sub_dmrrowp1_then_sub_dmrrow0
10151 0, // sub_dmrrowp1_then_sub_dmrrow1
10152 0, // sub_wacc_hi_then_sub_dmrrow0
10153 0, // sub_wacc_hi_then_sub_dmrrow1
10154 0, // sub_wacc_hi_then_sub_dmrrowp0
10155 0, // sub_wacc_hi_then_sub_dmrrowp1
10156 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10157 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10158 0, // sub_dmr1_then_sub_dmrrow0
10159 0, // sub_dmr1_then_sub_dmrrow1
10160 0, // sub_dmr1_then_sub_dmrrowp0
10161 0, // sub_dmr1_then_sub_dmrrowp1
10162 0, // sub_dmr1_then_sub_wacc_hi
10163 0, // sub_dmr1_then_sub_wacc_lo
10164 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10165 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10166 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10167 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10168 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10169 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10170 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10171 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10172 0, // sub_gp8_x1_then_sub_32
10173 },
10174 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10175 0, // sub_32
10176 0, // sub_32_hi_phony
10177 46, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10178 46, // sub_64_hi_phony -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10179 0, // sub_dmr0
10180 0, // sub_dmr1
10181 0, // sub_dmrrow0
10182 0, // sub_dmrrow1
10183 0, // sub_dmrrowp0
10184 0, // sub_dmrrowp1
10185 0, // sub_eq
10186 0, // sub_fp0
10187 0, // sub_fp1
10188 0, // sub_gp8_x0
10189 0, // sub_gp8_x1
10190 0, // sub_gt
10191 0, // sub_lt
10192 0, // sub_pair0
10193 0, // sub_pair1
10194 0, // sub_un
10195 46, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10196 46, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10197 0, // sub_wacc_hi
10198 0, // sub_wacc_lo
10199 46, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10200 46, // sub_vsx1_then_sub_64_hi_phony -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
10201 0, // sub_pair1_then_sub_64
10202 0, // sub_pair1_then_sub_64_hi_phony
10203 0, // sub_pair1_then_sub_vsx0
10204 0, // sub_pair1_then_sub_vsx1
10205 0, // sub_pair1_then_sub_vsx1_then_sub_64
10206 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10207 0, // sub_dmrrowp1_then_sub_dmrrow0
10208 0, // sub_dmrrowp1_then_sub_dmrrow1
10209 0, // sub_wacc_hi_then_sub_dmrrow0
10210 0, // sub_wacc_hi_then_sub_dmrrow1
10211 0, // sub_wacc_hi_then_sub_dmrrowp0
10212 0, // sub_wacc_hi_then_sub_dmrrowp1
10213 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10214 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10215 0, // sub_dmr1_then_sub_dmrrow0
10216 0, // sub_dmr1_then_sub_dmrrow1
10217 0, // sub_dmr1_then_sub_dmrrowp0
10218 0, // sub_dmr1_then_sub_dmrrowp1
10219 0, // sub_dmr1_then_sub_wacc_hi
10220 0, // sub_dmr1_then_sub_wacc_lo
10221 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10222 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10223 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10224 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10225 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10226 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10227 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10228 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10229 0, // sub_gp8_x1_then_sub_32
10230 },
10231 { // ACCRC
10232 0, // sub_32
10233 0, // sub_32_hi_phony
10234 47, // sub_64 -> ACCRC
10235 47, // sub_64_hi_phony -> ACCRC
10236 0, // sub_dmr0
10237 0, // sub_dmr1
10238 0, // sub_dmrrow0
10239 0, // sub_dmrrow1
10240 0, // sub_dmrrowp0
10241 0, // sub_dmrrowp1
10242 0, // sub_eq
10243 0, // sub_fp0
10244 0, // sub_fp1
10245 0, // sub_gp8_x0
10246 0, // sub_gp8_x1
10247 0, // sub_gt
10248 0, // sub_lt
10249 47, // sub_pair0 -> ACCRC
10250 47, // sub_pair1 -> ACCRC
10251 0, // sub_un
10252 47, // sub_vsx0 -> ACCRC
10253 47, // sub_vsx1 -> ACCRC
10254 0, // sub_wacc_hi
10255 0, // sub_wacc_lo
10256 47, // sub_vsx1_then_sub_64 -> ACCRC
10257 47, // sub_vsx1_then_sub_64_hi_phony -> ACCRC
10258 47, // sub_pair1_then_sub_64 -> ACCRC
10259 47, // sub_pair1_then_sub_64_hi_phony -> ACCRC
10260 47, // sub_pair1_then_sub_vsx0 -> ACCRC
10261 47, // sub_pair1_then_sub_vsx1 -> ACCRC
10262 47, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC
10263 47, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony -> ACCRC
10264 0, // sub_dmrrowp1_then_sub_dmrrow0
10265 0, // sub_dmrrowp1_then_sub_dmrrow1
10266 0, // sub_wacc_hi_then_sub_dmrrow0
10267 0, // sub_wacc_hi_then_sub_dmrrow1
10268 0, // sub_wacc_hi_then_sub_dmrrowp0
10269 0, // sub_wacc_hi_then_sub_dmrrowp1
10270 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10271 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10272 0, // sub_dmr1_then_sub_dmrrow0
10273 0, // sub_dmr1_then_sub_dmrrow1
10274 0, // sub_dmr1_then_sub_dmrrowp0
10275 0, // sub_dmr1_then_sub_dmrrowp1
10276 0, // sub_dmr1_then_sub_wacc_hi
10277 0, // sub_dmr1_then_sub_wacc_lo
10278 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10279 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10280 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10281 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10282 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10283 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10284 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10285 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10286 0, // sub_gp8_x1_then_sub_32
10287 },
10288 { // UACCRC
10289 0, // sub_32
10290 0, // sub_32_hi_phony
10291 48, // sub_64 -> UACCRC
10292 48, // sub_64_hi_phony -> UACCRC
10293 0, // sub_dmr0
10294 0, // sub_dmr1
10295 0, // sub_dmrrow0
10296 0, // sub_dmrrow1
10297 0, // sub_dmrrowp0
10298 0, // sub_dmrrowp1
10299 0, // sub_eq
10300 0, // sub_fp0
10301 0, // sub_fp1
10302 0, // sub_gp8_x0
10303 0, // sub_gp8_x1
10304 0, // sub_gt
10305 0, // sub_lt
10306 48, // sub_pair0 -> UACCRC
10307 48, // sub_pair1 -> UACCRC
10308 0, // sub_un
10309 48, // sub_vsx0 -> UACCRC
10310 48, // sub_vsx1 -> UACCRC
10311 0, // sub_wacc_hi
10312 0, // sub_wacc_lo
10313 48, // sub_vsx1_then_sub_64 -> UACCRC
10314 48, // sub_vsx1_then_sub_64_hi_phony -> UACCRC
10315 48, // sub_pair1_then_sub_64 -> UACCRC
10316 48, // sub_pair1_then_sub_64_hi_phony -> UACCRC
10317 48, // sub_pair1_then_sub_vsx0 -> UACCRC
10318 48, // sub_pair1_then_sub_vsx1 -> UACCRC
10319 48, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC
10320 48, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony -> UACCRC
10321 0, // sub_dmrrowp1_then_sub_dmrrow0
10322 0, // sub_dmrrowp1_then_sub_dmrrow1
10323 0, // sub_wacc_hi_then_sub_dmrrow0
10324 0, // sub_wacc_hi_then_sub_dmrrow1
10325 0, // sub_wacc_hi_then_sub_dmrrowp0
10326 0, // sub_wacc_hi_then_sub_dmrrowp1
10327 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10328 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10329 0, // sub_dmr1_then_sub_dmrrow0
10330 0, // sub_dmr1_then_sub_dmrrow1
10331 0, // sub_dmr1_then_sub_dmrrowp0
10332 0, // sub_dmr1_then_sub_dmrrowp1
10333 0, // sub_dmr1_then_sub_wacc_hi
10334 0, // sub_dmr1_then_sub_wacc_lo
10335 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10336 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10337 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10338 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10339 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10340 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10341 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10342 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10343 0, // sub_gp8_x1_then_sub_32
10344 },
10345 { // WACCRC
10346 0, // sub_32
10347 0, // sub_32_hi_phony
10348 0, // sub_64
10349 0, // sub_64_hi_phony
10350 0, // sub_dmr0
10351 0, // sub_dmr1
10352 49, // sub_dmrrow0 -> WACCRC
10353 49, // sub_dmrrow1 -> WACCRC
10354 49, // sub_dmrrowp0 -> WACCRC
10355 49, // sub_dmrrowp1 -> WACCRC
10356 0, // sub_eq
10357 0, // sub_fp0
10358 0, // sub_fp1
10359 0, // sub_gp8_x0
10360 0, // sub_gp8_x1
10361 0, // sub_gt
10362 0, // sub_lt
10363 0, // sub_pair0
10364 0, // sub_pair1
10365 0, // sub_un
10366 0, // sub_vsx0
10367 0, // sub_vsx1
10368 0, // sub_wacc_hi
10369 0, // sub_wacc_lo
10370 0, // sub_vsx1_then_sub_64
10371 0, // sub_vsx1_then_sub_64_hi_phony
10372 0, // sub_pair1_then_sub_64
10373 0, // sub_pair1_then_sub_64_hi_phony
10374 0, // sub_pair1_then_sub_vsx0
10375 0, // sub_pair1_then_sub_vsx1
10376 0, // sub_pair1_then_sub_vsx1_then_sub_64
10377 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10378 49, // sub_dmrrowp1_then_sub_dmrrow0 -> WACCRC
10379 49, // sub_dmrrowp1_then_sub_dmrrow1 -> WACCRC
10380 0, // sub_wacc_hi_then_sub_dmrrow0
10381 0, // sub_wacc_hi_then_sub_dmrrow1
10382 0, // sub_wacc_hi_then_sub_dmrrowp0
10383 0, // sub_wacc_hi_then_sub_dmrrowp1
10384 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10385 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10386 0, // sub_dmr1_then_sub_dmrrow0
10387 0, // sub_dmr1_then_sub_dmrrow1
10388 0, // sub_dmr1_then_sub_dmrrowp0
10389 0, // sub_dmr1_then_sub_dmrrowp1
10390 0, // sub_dmr1_then_sub_wacc_hi
10391 0, // sub_dmr1_then_sub_wacc_lo
10392 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10393 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10394 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10395 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10396 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10397 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10398 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10399 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10400 0, // sub_gp8_x1_then_sub_32
10401 },
10402 { // WACC_HIRC
10403 0, // sub_32
10404 0, // sub_32_hi_phony
10405 0, // sub_64
10406 0, // sub_64_hi_phony
10407 0, // sub_dmr0
10408 0, // sub_dmr1
10409 50, // sub_dmrrow0 -> WACC_HIRC
10410 50, // sub_dmrrow1 -> WACC_HIRC
10411 50, // sub_dmrrowp0 -> WACC_HIRC
10412 50, // sub_dmrrowp1 -> WACC_HIRC
10413 0, // sub_eq
10414 0, // sub_fp0
10415 0, // sub_fp1
10416 0, // sub_gp8_x0
10417 0, // sub_gp8_x1
10418 0, // sub_gt
10419 0, // sub_lt
10420 0, // sub_pair0
10421 0, // sub_pair1
10422 0, // sub_un
10423 0, // sub_vsx0
10424 0, // sub_vsx1
10425 0, // sub_wacc_hi
10426 0, // sub_wacc_lo
10427 0, // sub_vsx1_then_sub_64
10428 0, // sub_vsx1_then_sub_64_hi_phony
10429 0, // sub_pair1_then_sub_64
10430 0, // sub_pair1_then_sub_64_hi_phony
10431 0, // sub_pair1_then_sub_vsx0
10432 0, // sub_pair1_then_sub_vsx1
10433 0, // sub_pair1_then_sub_vsx1_then_sub_64
10434 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10435 50, // sub_dmrrowp1_then_sub_dmrrow0 -> WACC_HIRC
10436 50, // sub_dmrrowp1_then_sub_dmrrow1 -> WACC_HIRC
10437 0, // sub_wacc_hi_then_sub_dmrrow0
10438 0, // sub_wacc_hi_then_sub_dmrrow1
10439 0, // sub_wacc_hi_then_sub_dmrrowp0
10440 0, // sub_wacc_hi_then_sub_dmrrowp1
10441 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10442 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10443 0, // sub_dmr1_then_sub_dmrrow0
10444 0, // sub_dmr1_then_sub_dmrrow1
10445 0, // sub_dmr1_then_sub_dmrrowp0
10446 0, // sub_dmr1_then_sub_dmrrowp1
10447 0, // sub_dmr1_then_sub_wacc_hi
10448 0, // sub_dmr1_then_sub_wacc_lo
10449 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10450 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10451 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10452 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10453 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10454 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10455 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10456 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10457 0, // sub_gp8_x1_then_sub_32
10458 },
10459 { // ACCRC_with_sub_64_in_SPILLTOVSRRC
10460 0, // sub_32
10461 0, // sub_32_hi_phony
10462 51, // sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10463 51, // sub_64_hi_phony -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10464 0, // sub_dmr0
10465 0, // sub_dmr1
10466 0, // sub_dmrrow0
10467 0, // sub_dmrrow1
10468 0, // sub_dmrrowp0
10469 0, // sub_dmrrowp1
10470 0, // sub_eq
10471 0, // sub_fp0
10472 0, // sub_fp1
10473 0, // sub_gp8_x0
10474 0, // sub_gp8_x1
10475 0, // sub_gt
10476 0, // sub_lt
10477 51, // sub_pair0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10478 51, // sub_pair1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10479 0, // sub_un
10480 51, // sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10481 51, // sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10482 0, // sub_wacc_hi
10483 0, // sub_wacc_lo
10484 51, // sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10485 51, // sub_vsx1_then_sub_64_hi_phony -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10486 51, // sub_pair1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10487 51, // sub_pair1_then_sub_64_hi_phony -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10488 51, // sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10489 51, // sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10490 51, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10491 51, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony -> ACCRC_with_sub_64_in_SPILLTOVSRRC
10492 0, // sub_dmrrowp1_then_sub_dmrrow0
10493 0, // sub_dmrrowp1_then_sub_dmrrow1
10494 0, // sub_wacc_hi_then_sub_dmrrow0
10495 0, // sub_wacc_hi_then_sub_dmrrow1
10496 0, // sub_wacc_hi_then_sub_dmrrowp0
10497 0, // sub_wacc_hi_then_sub_dmrrowp1
10498 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10499 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10500 0, // sub_dmr1_then_sub_dmrrow0
10501 0, // sub_dmr1_then_sub_dmrrow1
10502 0, // sub_dmr1_then_sub_dmrrowp0
10503 0, // sub_dmr1_then_sub_dmrrowp1
10504 0, // sub_dmr1_then_sub_wacc_hi
10505 0, // sub_dmr1_then_sub_wacc_lo
10506 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10507 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10508 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10509 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10510 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10511 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10512 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10513 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10514 0, // sub_gp8_x1_then_sub_32
10515 },
10516 { // UACCRC_with_sub_64_in_SPILLTOVSRRC
10517 0, // sub_32
10518 0, // sub_32_hi_phony
10519 52, // sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10520 52, // sub_64_hi_phony -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10521 0, // sub_dmr0
10522 0, // sub_dmr1
10523 0, // sub_dmrrow0
10524 0, // sub_dmrrow1
10525 0, // sub_dmrrowp0
10526 0, // sub_dmrrowp1
10527 0, // sub_eq
10528 0, // sub_fp0
10529 0, // sub_fp1
10530 0, // sub_gp8_x0
10531 0, // sub_gp8_x1
10532 0, // sub_gt
10533 0, // sub_lt
10534 52, // sub_pair0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10535 52, // sub_pair1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10536 0, // sub_un
10537 52, // sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10538 52, // sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10539 0, // sub_wacc_hi
10540 0, // sub_wacc_lo
10541 52, // sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10542 52, // sub_vsx1_then_sub_64_hi_phony -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10543 52, // sub_pair1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10544 52, // sub_pair1_then_sub_64_hi_phony -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10545 52, // sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10546 52, // sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10547 52, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10548 52, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony -> UACCRC_with_sub_64_in_SPILLTOVSRRC
10549 0, // sub_dmrrowp1_then_sub_dmrrow0
10550 0, // sub_dmrrowp1_then_sub_dmrrow1
10551 0, // sub_wacc_hi_then_sub_dmrrow0
10552 0, // sub_wacc_hi_then_sub_dmrrow1
10553 0, // sub_wacc_hi_then_sub_dmrrowp0
10554 0, // sub_wacc_hi_then_sub_dmrrowp1
10555 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10556 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10557 0, // sub_dmr1_then_sub_dmrrow0
10558 0, // sub_dmr1_then_sub_dmrrow1
10559 0, // sub_dmr1_then_sub_dmrrowp0
10560 0, // sub_dmr1_then_sub_dmrrowp1
10561 0, // sub_dmr1_then_sub_wacc_hi
10562 0, // sub_dmr1_then_sub_wacc_lo
10563 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10564 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10565 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10566 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10567 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10568 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10569 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10570 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10571 0, // sub_gp8_x1_then_sub_32
10572 },
10573 { // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10574 0, // sub_32
10575 0, // sub_32_hi_phony
10576 53, // sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10577 53, // sub_64_hi_phony -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10578 0, // sub_dmr0
10579 0, // sub_dmr1
10580 0, // sub_dmrrow0
10581 0, // sub_dmrrow1
10582 0, // sub_dmrrowp0
10583 0, // sub_dmrrowp1
10584 0, // sub_eq
10585 0, // sub_fp0
10586 0, // sub_fp1
10587 0, // sub_gp8_x0
10588 0, // sub_gp8_x1
10589 0, // sub_gt
10590 0, // sub_lt
10591 53, // sub_pair0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10592 53, // sub_pair1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10593 0, // sub_un
10594 53, // sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10595 53, // sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10596 0, // sub_wacc_hi
10597 0, // sub_wacc_lo
10598 53, // sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10599 53, // sub_vsx1_then_sub_64_hi_phony -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10600 53, // sub_pair1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10601 53, // sub_pair1_then_sub_64_hi_phony -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10602 53, // sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10603 53, // sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10604 53, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10605 53, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10606 0, // sub_dmrrowp1_then_sub_dmrrow0
10607 0, // sub_dmrrowp1_then_sub_dmrrow1
10608 0, // sub_wacc_hi_then_sub_dmrrow0
10609 0, // sub_wacc_hi_then_sub_dmrrow1
10610 0, // sub_wacc_hi_then_sub_dmrrowp0
10611 0, // sub_wacc_hi_then_sub_dmrrowp1
10612 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10613 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10614 0, // sub_dmr1_then_sub_dmrrow0
10615 0, // sub_dmr1_then_sub_dmrrow1
10616 0, // sub_dmr1_then_sub_dmrrowp0
10617 0, // sub_dmr1_then_sub_dmrrowp1
10618 0, // sub_dmr1_then_sub_wacc_hi
10619 0, // sub_dmr1_then_sub_wacc_lo
10620 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10621 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10622 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10623 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10624 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10625 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10626 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10627 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10628 0, // sub_gp8_x1_then_sub_32
10629 },
10630 { // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10631 0, // sub_32
10632 0, // sub_32_hi_phony
10633 54, // sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10634 54, // sub_64_hi_phony -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10635 0, // sub_dmr0
10636 0, // sub_dmr1
10637 0, // sub_dmrrow0
10638 0, // sub_dmrrow1
10639 0, // sub_dmrrowp0
10640 0, // sub_dmrrowp1
10641 0, // sub_eq
10642 0, // sub_fp0
10643 0, // sub_fp1
10644 0, // sub_gp8_x0
10645 0, // sub_gp8_x1
10646 0, // sub_gt
10647 0, // sub_lt
10648 54, // sub_pair0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10649 54, // sub_pair1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10650 0, // sub_un
10651 54, // sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10652 54, // sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10653 0, // sub_wacc_hi
10654 0, // sub_wacc_lo
10655 54, // sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10656 54, // sub_vsx1_then_sub_64_hi_phony -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10657 54, // sub_pair1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10658 54, // sub_pair1_then_sub_64_hi_phony -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10659 54, // sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10660 54, // sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10661 54, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10662 54, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
10663 0, // sub_dmrrowp1_then_sub_dmrrow0
10664 0, // sub_dmrrowp1_then_sub_dmrrow1
10665 0, // sub_wacc_hi_then_sub_dmrrow0
10666 0, // sub_wacc_hi_then_sub_dmrrow1
10667 0, // sub_wacc_hi_then_sub_dmrrowp0
10668 0, // sub_wacc_hi_then_sub_dmrrowp1
10669 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10670 0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10671 0, // sub_dmr1_then_sub_dmrrow0
10672 0, // sub_dmr1_then_sub_dmrrow1
10673 0, // sub_dmr1_then_sub_dmrrowp0
10674 0, // sub_dmr1_then_sub_dmrrowp1
10675 0, // sub_dmr1_then_sub_wacc_hi
10676 0, // sub_dmr1_then_sub_wacc_lo
10677 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10678 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10679 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10680 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10681 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10682 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10683 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10684 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10685 0, // sub_gp8_x1_then_sub_32
10686 },
10687 { // DMRRC
10688 0, // sub_32
10689 0, // sub_32_hi_phony
10690 0, // sub_64
10691 0, // sub_64_hi_phony
10692 0, // sub_dmr0
10693 0, // sub_dmr1
10694 55, // sub_dmrrow0 -> DMRRC
10695 55, // sub_dmrrow1 -> DMRRC
10696 55, // sub_dmrrowp0 -> DMRRC
10697 55, // sub_dmrrowp1 -> DMRRC
10698 0, // sub_eq
10699 0, // sub_fp0
10700 0, // sub_fp1
10701 0, // sub_gp8_x0
10702 0, // sub_gp8_x1
10703 0, // sub_gt
10704 0, // sub_lt
10705 0, // sub_pair0
10706 0, // sub_pair1
10707 0, // sub_un
10708 0, // sub_vsx0
10709 0, // sub_vsx1
10710 55, // sub_wacc_hi -> DMRRC
10711 55, // sub_wacc_lo -> DMRRC
10712 0, // sub_vsx1_then_sub_64
10713 0, // sub_vsx1_then_sub_64_hi_phony
10714 0, // sub_pair1_then_sub_64
10715 0, // sub_pair1_then_sub_64_hi_phony
10716 0, // sub_pair1_then_sub_vsx0
10717 0, // sub_pair1_then_sub_vsx1
10718 0, // sub_pair1_then_sub_vsx1_then_sub_64
10719 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10720 55, // sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
10721 55, // sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
10722 55, // sub_wacc_hi_then_sub_dmrrow0 -> DMRRC
10723 55, // sub_wacc_hi_then_sub_dmrrow1 -> DMRRC
10724 55, // sub_wacc_hi_then_sub_dmrrowp0 -> DMRRC
10725 55, // sub_wacc_hi_then_sub_dmrrowp1 -> DMRRC
10726 55, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
10727 55, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
10728 0, // sub_dmr1_then_sub_dmrrow0
10729 0, // sub_dmr1_then_sub_dmrrow1
10730 0, // sub_dmr1_then_sub_dmrrowp0
10731 0, // sub_dmr1_then_sub_dmrrowp1
10732 0, // sub_dmr1_then_sub_wacc_hi
10733 0, // sub_dmr1_then_sub_wacc_lo
10734 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10735 0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10736 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10737 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10738 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10739 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10740 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10741 0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10742 0, // sub_gp8_x1_then_sub_32
10743 },
10744 { // DMRpRC
10745 0, // sub_32
10746 0, // sub_32_hi_phony
10747 0, // sub_64
10748 0, // sub_64_hi_phony
10749 56, // sub_dmr0 -> DMRpRC
10750 56, // sub_dmr1 -> DMRpRC
10751 56, // sub_dmrrow0 -> DMRpRC
10752 56, // sub_dmrrow1 -> DMRpRC
10753 56, // sub_dmrrowp0 -> DMRpRC
10754 56, // sub_dmrrowp1 -> DMRpRC
10755 0, // sub_eq
10756 0, // sub_fp0
10757 0, // sub_fp1
10758 0, // sub_gp8_x0
10759 0, // sub_gp8_x1
10760 0, // sub_gt
10761 0, // sub_lt
10762 0, // sub_pair0
10763 0, // sub_pair1
10764 0, // sub_un
10765 0, // sub_vsx0
10766 0, // sub_vsx1
10767 56, // sub_wacc_hi -> DMRpRC
10768 56, // sub_wacc_lo -> DMRpRC
10769 0, // sub_vsx1_then_sub_64
10770 0, // sub_vsx1_then_sub_64_hi_phony
10771 0, // sub_pair1_then_sub_64
10772 0, // sub_pair1_then_sub_64_hi_phony
10773 0, // sub_pair1_then_sub_vsx0
10774 0, // sub_pair1_then_sub_vsx1
10775 0, // sub_pair1_then_sub_vsx1_then_sub_64
10776 0, // sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10777 56, // sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
10778 56, // sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
10779 56, // sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
10780 56, // sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
10781 56, // sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
10782 56, // sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
10783 56, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
10784 56, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
10785 56, // sub_dmr1_then_sub_dmrrow0 -> DMRpRC
10786 56, // sub_dmr1_then_sub_dmrrow1 -> DMRpRC
10787 56, // sub_dmr1_then_sub_dmrrowp0 -> DMRpRC
10788 56, // sub_dmr1_then_sub_dmrrowp1 -> DMRpRC
10789 56, // sub_dmr1_then_sub_wacc_hi -> DMRpRC
10790 56, // sub_dmr1_then_sub_wacc_lo -> DMRpRC
10791 56, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
10792 56, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
10793 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
10794 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
10795 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
10796 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
10797 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
10798 56, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
10799 0, // sub_gp8_x1_then_sub_32
10800 },
10801 };
10802 assert(RC && "Missing regclass");
10803 if (!Idx) return RC;
10804 --Idx;
10805 assert(Idx < 55 && "Bad subreg");
10806 unsigned TV = Table[RC->getID()][Idx];
10807 return TV ? getRegClass(TV - 1) : nullptr;
10808}
10809
10810const TargetRegisterClass *PPCGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
10811 static const uint8_t Table[56][55] = {
10812 { // VSSRC
10813 0, // VSSRC:sub_32
10814 0, // VSSRC:sub_32_hi_phony
10815 0, // VSSRC:sub_64
10816 0, // VSSRC:sub_64_hi_phony
10817 0, // VSSRC:sub_dmr0
10818 0, // VSSRC:sub_dmr1
10819 0, // VSSRC:sub_dmrrow0
10820 0, // VSSRC:sub_dmrrow1
10821 0, // VSSRC:sub_dmrrowp0
10822 0, // VSSRC:sub_dmrrowp1
10823 0, // VSSRC:sub_eq
10824 0, // VSSRC:sub_fp0
10825 0, // VSSRC:sub_fp1
10826 0, // VSSRC:sub_gp8_x0
10827 0, // VSSRC:sub_gp8_x1
10828 0, // VSSRC:sub_gt
10829 0, // VSSRC:sub_lt
10830 0, // VSSRC:sub_pair0
10831 0, // VSSRC:sub_pair1
10832 0, // VSSRC:sub_un
10833 0, // VSSRC:sub_vsx0
10834 0, // VSSRC:sub_vsx1
10835 0, // VSSRC:sub_wacc_hi
10836 0, // VSSRC:sub_wacc_lo
10837 0, // VSSRC:sub_vsx1_then_sub_64
10838 0, // VSSRC:sub_vsx1_then_sub_64_hi_phony
10839 0, // VSSRC:sub_pair1_then_sub_64
10840 0, // VSSRC:sub_pair1_then_sub_64_hi_phony
10841 0, // VSSRC:sub_pair1_then_sub_vsx0
10842 0, // VSSRC:sub_pair1_then_sub_vsx1
10843 0, // VSSRC:sub_pair1_then_sub_vsx1_then_sub_64
10844 0, // VSSRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10845 0, // VSSRC:sub_dmrrowp1_then_sub_dmrrow0
10846 0, // VSSRC:sub_dmrrowp1_then_sub_dmrrow1
10847 0, // VSSRC:sub_wacc_hi_then_sub_dmrrow0
10848 0, // VSSRC:sub_wacc_hi_then_sub_dmrrow1
10849 0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp0
10850 0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1
10851 0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10852 0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10853 0, // VSSRC:sub_dmr1_then_sub_dmrrow0
10854 0, // VSSRC:sub_dmr1_then_sub_dmrrow1
10855 0, // VSSRC:sub_dmr1_then_sub_dmrrowp0
10856 0, // VSSRC:sub_dmr1_then_sub_dmrrowp1
10857 0, // VSSRC:sub_dmr1_then_sub_wacc_hi
10858 0, // VSSRC:sub_dmr1_then_sub_wacc_lo
10859 0, // VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10860 0, // VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10861 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10862 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10863 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10864 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10865 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10866 0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10867 0, // VSSRC:sub_gp8_x1_then_sub_32
10868 },
10869 { // GPRC
10870 0, // GPRC:sub_32
10871 0, // GPRC:sub_32_hi_phony
10872 0, // GPRC:sub_64
10873 0, // GPRC:sub_64_hi_phony
10874 0, // GPRC:sub_dmr0
10875 0, // GPRC:sub_dmr1
10876 0, // GPRC:sub_dmrrow0
10877 0, // GPRC:sub_dmrrow1
10878 0, // GPRC:sub_dmrrowp0
10879 0, // GPRC:sub_dmrrowp1
10880 0, // GPRC:sub_eq
10881 0, // GPRC:sub_fp0
10882 0, // GPRC:sub_fp1
10883 0, // GPRC:sub_gp8_x0
10884 0, // GPRC:sub_gp8_x1
10885 0, // GPRC:sub_gt
10886 0, // GPRC:sub_lt
10887 0, // GPRC:sub_pair0
10888 0, // GPRC:sub_pair1
10889 0, // GPRC:sub_un
10890 0, // GPRC:sub_vsx0
10891 0, // GPRC:sub_vsx1
10892 0, // GPRC:sub_wacc_hi
10893 0, // GPRC:sub_wacc_lo
10894 0, // GPRC:sub_vsx1_then_sub_64
10895 0, // GPRC:sub_vsx1_then_sub_64_hi_phony
10896 0, // GPRC:sub_pair1_then_sub_64
10897 0, // GPRC:sub_pair1_then_sub_64_hi_phony
10898 0, // GPRC:sub_pair1_then_sub_vsx0
10899 0, // GPRC:sub_pair1_then_sub_vsx1
10900 0, // GPRC:sub_pair1_then_sub_vsx1_then_sub_64
10901 0, // GPRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10902 0, // GPRC:sub_dmrrowp1_then_sub_dmrrow0
10903 0, // GPRC:sub_dmrrowp1_then_sub_dmrrow1
10904 0, // GPRC:sub_wacc_hi_then_sub_dmrrow0
10905 0, // GPRC:sub_wacc_hi_then_sub_dmrrow1
10906 0, // GPRC:sub_wacc_hi_then_sub_dmrrowp0
10907 0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1
10908 0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10909 0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10910 0, // GPRC:sub_dmr1_then_sub_dmrrow0
10911 0, // GPRC:sub_dmr1_then_sub_dmrrow1
10912 0, // GPRC:sub_dmr1_then_sub_dmrrowp0
10913 0, // GPRC:sub_dmr1_then_sub_dmrrowp1
10914 0, // GPRC:sub_dmr1_then_sub_wacc_hi
10915 0, // GPRC:sub_dmr1_then_sub_wacc_lo
10916 0, // GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10917 0, // GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10918 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10919 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10920 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10921 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10922 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10923 0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10924 0, // GPRC:sub_gp8_x1_then_sub_32
10925 },
10926 { // GPRC_NOR0
10927 0, // GPRC_NOR0:sub_32
10928 0, // GPRC_NOR0:sub_32_hi_phony
10929 0, // GPRC_NOR0:sub_64
10930 0, // GPRC_NOR0:sub_64_hi_phony
10931 0, // GPRC_NOR0:sub_dmr0
10932 0, // GPRC_NOR0:sub_dmr1
10933 0, // GPRC_NOR0:sub_dmrrow0
10934 0, // GPRC_NOR0:sub_dmrrow1
10935 0, // GPRC_NOR0:sub_dmrrowp0
10936 0, // GPRC_NOR0:sub_dmrrowp1
10937 0, // GPRC_NOR0:sub_eq
10938 0, // GPRC_NOR0:sub_fp0
10939 0, // GPRC_NOR0:sub_fp1
10940 0, // GPRC_NOR0:sub_gp8_x0
10941 0, // GPRC_NOR0:sub_gp8_x1
10942 0, // GPRC_NOR0:sub_gt
10943 0, // GPRC_NOR0:sub_lt
10944 0, // GPRC_NOR0:sub_pair0
10945 0, // GPRC_NOR0:sub_pair1
10946 0, // GPRC_NOR0:sub_un
10947 0, // GPRC_NOR0:sub_vsx0
10948 0, // GPRC_NOR0:sub_vsx1
10949 0, // GPRC_NOR0:sub_wacc_hi
10950 0, // GPRC_NOR0:sub_wacc_lo
10951 0, // GPRC_NOR0:sub_vsx1_then_sub_64
10952 0, // GPRC_NOR0:sub_vsx1_then_sub_64_hi_phony
10953 0, // GPRC_NOR0:sub_pair1_then_sub_64
10954 0, // GPRC_NOR0:sub_pair1_then_sub_64_hi_phony
10955 0, // GPRC_NOR0:sub_pair1_then_sub_vsx0
10956 0, // GPRC_NOR0:sub_pair1_then_sub_vsx1
10957 0, // GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
10958 0, // GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
10959 0, // GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
10960 0, // GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
10961 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
10962 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
10963 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
10964 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
10965 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10966 0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10967 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
10968 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
10969 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
10970 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
10971 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
10972 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
10973 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
10974 0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
10975 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
10976 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
10977 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
10978 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
10979 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
10980 0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
10981 0, // GPRC_NOR0:sub_gp8_x1_then_sub_32
10982 },
10983 { // GPRC_and_GPRC_NOR0
10984 0, // GPRC_and_GPRC_NOR0:sub_32
10985 0, // GPRC_and_GPRC_NOR0:sub_32_hi_phony
10986 0, // GPRC_and_GPRC_NOR0:sub_64
10987 0, // GPRC_and_GPRC_NOR0:sub_64_hi_phony
10988 0, // GPRC_and_GPRC_NOR0:sub_dmr0
10989 0, // GPRC_and_GPRC_NOR0:sub_dmr1
10990 0, // GPRC_and_GPRC_NOR0:sub_dmrrow0
10991 0, // GPRC_and_GPRC_NOR0:sub_dmrrow1
10992 0, // GPRC_and_GPRC_NOR0:sub_dmrrowp0
10993 0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1
10994 0, // GPRC_and_GPRC_NOR0:sub_eq
10995 0, // GPRC_and_GPRC_NOR0:sub_fp0
10996 0, // GPRC_and_GPRC_NOR0:sub_fp1
10997 0, // GPRC_and_GPRC_NOR0:sub_gp8_x0
10998 0, // GPRC_and_GPRC_NOR0:sub_gp8_x1
10999 0, // GPRC_and_GPRC_NOR0:sub_gt
11000 0, // GPRC_and_GPRC_NOR0:sub_lt
11001 0, // GPRC_and_GPRC_NOR0:sub_pair0
11002 0, // GPRC_and_GPRC_NOR0:sub_pair1
11003 0, // GPRC_and_GPRC_NOR0:sub_un
11004 0, // GPRC_and_GPRC_NOR0:sub_vsx0
11005 0, // GPRC_and_GPRC_NOR0:sub_vsx1
11006 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi
11007 0, // GPRC_and_GPRC_NOR0:sub_wacc_lo
11008 0, // GPRC_and_GPRC_NOR0:sub_vsx1_then_sub_64
11009 0, // GPRC_and_GPRC_NOR0:sub_vsx1_then_sub_64_hi_phony
11010 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_64
11011 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_64_hi_phony
11012 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx0
11013 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1
11014 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
11015 0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11016 0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
11017 0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
11018 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
11019 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
11020 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
11021 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
11022 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11023 0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11024 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
11025 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
11026 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
11027 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
11028 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
11029 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
11030 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11031 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11032 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11033 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11034 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11035 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11036 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11037 0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11038 0, // GPRC_and_GPRC_NOR0:sub_gp8_x1_then_sub_32
11039 },
11040 { // CRBITRC
11041 0, // CRBITRC:sub_32
11042 0, // CRBITRC:sub_32_hi_phony
11043 0, // CRBITRC:sub_64
11044 0, // CRBITRC:sub_64_hi_phony
11045 0, // CRBITRC:sub_dmr0
11046 0, // CRBITRC:sub_dmr1
11047 0, // CRBITRC:sub_dmrrow0
11048 0, // CRBITRC:sub_dmrrow1
11049 0, // CRBITRC:sub_dmrrowp0
11050 0, // CRBITRC:sub_dmrrowp1
11051 0, // CRBITRC:sub_eq
11052 0, // CRBITRC:sub_fp0
11053 0, // CRBITRC:sub_fp1
11054 0, // CRBITRC:sub_gp8_x0
11055 0, // CRBITRC:sub_gp8_x1
11056 0, // CRBITRC:sub_gt
11057 0, // CRBITRC:sub_lt
11058 0, // CRBITRC:sub_pair0
11059 0, // CRBITRC:sub_pair1
11060 0, // CRBITRC:sub_un
11061 0, // CRBITRC:sub_vsx0
11062 0, // CRBITRC:sub_vsx1
11063 0, // CRBITRC:sub_wacc_hi
11064 0, // CRBITRC:sub_wacc_lo
11065 0, // CRBITRC:sub_vsx1_then_sub_64
11066 0, // CRBITRC:sub_vsx1_then_sub_64_hi_phony
11067 0, // CRBITRC:sub_pair1_then_sub_64
11068 0, // CRBITRC:sub_pair1_then_sub_64_hi_phony
11069 0, // CRBITRC:sub_pair1_then_sub_vsx0
11070 0, // CRBITRC:sub_pair1_then_sub_vsx1
11071 0, // CRBITRC:sub_pair1_then_sub_vsx1_then_sub_64
11072 0, // CRBITRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11073 0, // CRBITRC:sub_dmrrowp1_then_sub_dmrrow0
11074 0, // CRBITRC:sub_dmrrowp1_then_sub_dmrrow1
11075 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrow0
11076 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrow1
11077 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp0
11078 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1
11079 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11080 0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11081 0, // CRBITRC:sub_dmr1_then_sub_dmrrow0
11082 0, // CRBITRC:sub_dmr1_then_sub_dmrrow1
11083 0, // CRBITRC:sub_dmr1_then_sub_dmrrowp0
11084 0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1
11085 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi
11086 0, // CRBITRC:sub_dmr1_then_sub_wacc_lo
11087 0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11088 0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11089 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11090 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11091 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11092 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11093 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11094 0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11095 0, // CRBITRC:sub_gp8_x1_then_sub_32
11096 },
11097 { // F4RC
11098 0, // F4RC:sub_32
11099 0, // F4RC:sub_32_hi_phony
11100 0, // F4RC:sub_64
11101 0, // F4RC:sub_64_hi_phony
11102 0, // F4RC:sub_dmr0
11103 0, // F4RC:sub_dmr1
11104 0, // F4RC:sub_dmrrow0
11105 0, // F4RC:sub_dmrrow1
11106 0, // F4RC:sub_dmrrowp0
11107 0, // F4RC:sub_dmrrowp1
11108 0, // F4RC:sub_eq
11109 0, // F4RC:sub_fp0
11110 0, // F4RC:sub_fp1
11111 0, // F4RC:sub_gp8_x0
11112 0, // F4RC:sub_gp8_x1
11113 0, // F4RC:sub_gt
11114 0, // F4RC:sub_lt
11115 0, // F4RC:sub_pair0
11116 0, // F4RC:sub_pair1
11117 0, // F4RC:sub_un
11118 0, // F4RC:sub_vsx0
11119 0, // F4RC:sub_vsx1
11120 0, // F4RC:sub_wacc_hi
11121 0, // F4RC:sub_wacc_lo
11122 0, // F4RC:sub_vsx1_then_sub_64
11123 0, // F4RC:sub_vsx1_then_sub_64_hi_phony
11124 0, // F4RC:sub_pair1_then_sub_64
11125 0, // F4RC:sub_pair1_then_sub_64_hi_phony
11126 0, // F4RC:sub_pair1_then_sub_vsx0
11127 0, // F4RC:sub_pair1_then_sub_vsx1
11128 0, // F4RC:sub_pair1_then_sub_vsx1_then_sub_64
11129 0, // F4RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11130 0, // F4RC:sub_dmrrowp1_then_sub_dmrrow0
11131 0, // F4RC:sub_dmrrowp1_then_sub_dmrrow1
11132 0, // F4RC:sub_wacc_hi_then_sub_dmrrow0
11133 0, // F4RC:sub_wacc_hi_then_sub_dmrrow1
11134 0, // F4RC:sub_wacc_hi_then_sub_dmrrowp0
11135 0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1
11136 0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11137 0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11138 0, // F4RC:sub_dmr1_then_sub_dmrrow0
11139 0, // F4RC:sub_dmr1_then_sub_dmrrow1
11140 0, // F4RC:sub_dmr1_then_sub_dmrrowp0
11141 0, // F4RC:sub_dmr1_then_sub_dmrrowp1
11142 0, // F4RC:sub_dmr1_then_sub_wacc_hi
11143 0, // F4RC:sub_dmr1_then_sub_wacc_lo
11144 0, // F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11145 0, // F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11146 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11147 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11148 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11149 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11150 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11151 0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11152 0, // F4RC:sub_gp8_x1_then_sub_32
11153 },
11154 { // GPRC32
11155 0, // GPRC32:sub_32
11156 0, // GPRC32:sub_32_hi_phony
11157 0, // GPRC32:sub_64
11158 0, // GPRC32:sub_64_hi_phony
11159 0, // GPRC32:sub_dmr0
11160 0, // GPRC32:sub_dmr1
11161 0, // GPRC32:sub_dmrrow0
11162 0, // GPRC32:sub_dmrrow1
11163 0, // GPRC32:sub_dmrrowp0
11164 0, // GPRC32:sub_dmrrowp1
11165 0, // GPRC32:sub_eq
11166 0, // GPRC32:sub_fp0
11167 0, // GPRC32:sub_fp1
11168 0, // GPRC32:sub_gp8_x0
11169 0, // GPRC32:sub_gp8_x1
11170 0, // GPRC32:sub_gt
11171 0, // GPRC32:sub_lt
11172 0, // GPRC32:sub_pair0
11173 0, // GPRC32:sub_pair1
11174 0, // GPRC32:sub_un
11175 0, // GPRC32:sub_vsx0
11176 0, // GPRC32:sub_vsx1
11177 0, // GPRC32:sub_wacc_hi
11178 0, // GPRC32:sub_wacc_lo
11179 0, // GPRC32:sub_vsx1_then_sub_64
11180 0, // GPRC32:sub_vsx1_then_sub_64_hi_phony
11181 0, // GPRC32:sub_pair1_then_sub_64
11182 0, // GPRC32:sub_pair1_then_sub_64_hi_phony
11183 0, // GPRC32:sub_pair1_then_sub_vsx0
11184 0, // GPRC32:sub_pair1_then_sub_vsx1
11185 0, // GPRC32:sub_pair1_then_sub_vsx1_then_sub_64
11186 0, // GPRC32:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11187 0, // GPRC32:sub_dmrrowp1_then_sub_dmrrow0
11188 0, // GPRC32:sub_dmrrowp1_then_sub_dmrrow1
11189 0, // GPRC32:sub_wacc_hi_then_sub_dmrrow0
11190 0, // GPRC32:sub_wacc_hi_then_sub_dmrrow1
11191 0, // GPRC32:sub_wacc_hi_then_sub_dmrrowp0
11192 0, // GPRC32:sub_wacc_hi_then_sub_dmrrowp1
11193 0, // GPRC32:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11194 0, // GPRC32:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11195 0, // GPRC32:sub_dmr1_then_sub_dmrrow0
11196 0, // GPRC32:sub_dmr1_then_sub_dmrrow1
11197 0, // GPRC32:sub_dmr1_then_sub_dmrrowp0
11198 0, // GPRC32:sub_dmr1_then_sub_dmrrowp1
11199 0, // GPRC32:sub_dmr1_then_sub_wacc_hi
11200 0, // GPRC32:sub_dmr1_then_sub_wacc_lo
11201 0, // GPRC32:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11202 0, // GPRC32:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11203 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11204 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11205 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11206 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11207 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11208 0, // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11209 0, // GPRC32:sub_gp8_x1_then_sub_32
11210 },
11211 { // CRRC
11212 0, // CRRC:sub_32
11213 0, // CRRC:sub_32_hi_phony
11214 0, // CRRC:sub_64
11215 0, // CRRC:sub_64_hi_phony
11216 0, // CRRC:sub_dmr0
11217 0, // CRRC:sub_dmr1
11218 0, // CRRC:sub_dmrrow0
11219 0, // CRRC:sub_dmrrow1
11220 0, // CRRC:sub_dmrrowp0
11221 0, // CRRC:sub_dmrrowp1
11222 5, // CRRC:sub_eq -> CRBITRC
11223 0, // CRRC:sub_fp0
11224 0, // CRRC:sub_fp1
11225 0, // CRRC:sub_gp8_x0
11226 0, // CRRC:sub_gp8_x1
11227 5, // CRRC:sub_gt -> CRBITRC
11228 5, // CRRC:sub_lt -> CRBITRC
11229 0, // CRRC:sub_pair0
11230 0, // CRRC:sub_pair1
11231 5, // CRRC:sub_un -> CRBITRC
11232 0, // CRRC:sub_vsx0
11233 0, // CRRC:sub_vsx1
11234 0, // CRRC:sub_wacc_hi
11235 0, // CRRC:sub_wacc_lo
11236 0, // CRRC:sub_vsx1_then_sub_64
11237 0, // CRRC:sub_vsx1_then_sub_64_hi_phony
11238 0, // CRRC:sub_pair1_then_sub_64
11239 0, // CRRC:sub_pair1_then_sub_64_hi_phony
11240 0, // CRRC:sub_pair1_then_sub_vsx0
11241 0, // CRRC:sub_pair1_then_sub_vsx1
11242 0, // CRRC:sub_pair1_then_sub_vsx1_then_sub_64
11243 0, // CRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11244 0, // CRRC:sub_dmrrowp1_then_sub_dmrrow0
11245 0, // CRRC:sub_dmrrowp1_then_sub_dmrrow1
11246 0, // CRRC:sub_wacc_hi_then_sub_dmrrow0
11247 0, // CRRC:sub_wacc_hi_then_sub_dmrrow1
11248 0, // CRRC:sub_wacc_hi_then_sub_dmrrowp0
11249 0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1
11250 0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11251 0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11252 0, // CRRC:sub_dmr1_then_sub_dmrrow0
11253 0, // CRRC:sub_dmr1_then_sub_dmrrow1
11254 0, // CRRC:sub_dmr1_then_sub_dmrrowp0
11255 0, // CRRC:sub_dmr1_then_sub_dmrrowp1
11256 0, // CRRC:sub_dmr1_then_sub_wacc_hi
11257 0, // CRRC:sub_dmr1_then_sub_wacc_lo
11258 0, // CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11259 0, // CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11260 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11261 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11262 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11263 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11264 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11265 0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11266 0, // CRRC:sub_gp8_x1_then_sub_32
11267 },
11268 { // CARRYRC
11269 0, // CARRYRC:sub_32
11270 0, // CARRYRC:sub_32_hi_phony
11271 0, // CARRYRC:sub_64
11272 0, // CARRYRC:sub_64_hi_phony
11273 0, // CARRYRC:sub_dmr0
11274 0, // CARRYRC:sub_dmr1
11275 0, // CARRYRC:sub_dmrrow0
11276 0, // CARRYRC:sub_dmrrow1
11277 0, // CARRYRC:sub_dmrrowp0
11278 0, // CARRYRC:sub_dmrrowp1
11279 0, // CARRYRC:sub_eq
11280 0, // CARRYRC:sub_fp0
11281 0, // CARRYRC:sub_fp1
11282 0, // CARRYRC:sub_gp8_x0
11283 0, // CARRYRC:sub_gp8_x1
11284 0, // CARRYRC:sub_gt
11285 0, // CARRYRC:sub_lt
11286 0, // CARRYRC:sub_pair0
11287 0, // CARRYRC:sub_pair1
11288 0, // CARRYRC:sub_un
11289 0, // CARRYRC:sub_vsx0
11290 0, // CARRYRC:sub_vsx1
11291 0, // CARRYRC:sub_wacc_hi
11292 0, // CARRYRC:sub_wacc_lo
11293 0, // CARRYRC:sub_vsx1_then_sub_64
11294 0, // CARRYRC:sub_vsx1_then_sub_64_hi_phony
11295 0, // CARRYRC:sub_pair1_then_sub_64
11296 0, // CARRYRC:sub_pair1_then_sub_64_hi_phony
11297 0, // CARRYRC:sub_pair1_then_sub_vsx0
11298 0, // CARRYRC:sub_pair1_then_sub_vsx1
11299 0, // CARRYRC:sub_pair1_then_sub_vsx1_then_sub_64
11300 0, // CARRYRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11301 0, // CARRYRC:sub_dmrrowp1_then_sub_dmrrow0
11302 0, // CARRYRC:sub_dmrrowp1_then_sub_dmrrow1
11303 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrow0
11304 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrow1
11305 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp0
11306 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1
11307 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11308 0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11309 0, // CARRYRC:sub_dmr1_then_sub_dmrrow0
11310 0, // CARRYRC:sub_dmr1_then_sub_dmrrow1
11311 0, // CARRYRC:sub_dmr1_then_sub_dmrrowp0
11312 0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1
11313 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi
11314 0, // CARRYRC:sub_dmr1_then_sub_wacc_lo
11315 0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11316 0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11317 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11318 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11319 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11320 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11321 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11322 0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11323 0, // CARRYRC:sub_gp8_x1_then_sub_32
11324 },
11325 { // CTRRC
11326 0, // CTRRC:sub_32
11327 0, // CTRRC:sub_32_hi_phony
11328 0, // CTRRC:sub_64
11329 0, // CTRRC:sub_64_hi_phony
11330 0, // CTRRC:sub_dmr0
11331 0, // CTRRC:sub_dmr1
11332 0, // CTRRC:sub_dmrrow0
11333 0, // CTRRC:sub_dmrrow1
11334 0, // CTRRC:sub_dmrrowp0
11335 0, // CTRRC:sub_dmrrowp1
11336 0, // CTRRC:sub_eq
11337 0, // CTRRC:sub_fp0
11338 0, // CTRRC:sub_fp1
11339 0, // CTRRC:sub_gp8_x0
11340 0, // CTRRC:sub_gp8_x1
11341 0, // CTRRC:sub_gt
11342 0, // CTRRC:sub_lt
11343 0, // CTRRC:sub_pair0
11344 0, // CTRRC:sub_pair1
11345 0, // CTRRC:sub_un
11346 0, // CTRRC:sub_vsx0
11347 0, // CTRRC:sub_vsx1
11348 0, // CTRRC:sub_wacc_hi
11349 0, // CTRRC:sub_wacc_lo
11350 0, // CTRRC:sub_vsx1_then_sub_64
11351 0, // CTRRC:sub_vsx1_then_sub_64_hi_phony
11352 0, // CTRRC:sub_pair1_then_sub_64
11353 0, // CTRRC:sub_pair1_then_sub_64_hi_phony
11354 0, // CTRRC:sub_pair1_then_sub_vsx0
11355 0, // CTRRC:sub_pair1_then_sub_vsx1
11356 0, // CTRRC:sub_pair1_then_sub_vsx1_then_sub_64
11357 0, // CTRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11358 0, // CTRRC:sub_dmrrowp1_then_sub_dmrrow0
11359 0, // CTRRC:sub_dmrrowp1_then_sub_dmrrow1
11360 0, // CTRRC:sub_wacc_hi_then_sub_dmrrow0
11361 0, // CTRRC:sub_wacc_hi_then_sub_dmrrow1
11362 0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp0
11363 0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1
11364 0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11365 0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11366 0, // CTRRC:sub_dmr1_then_sub_dmrrow0
11367 0, // CTRRC:sub_dmr1_then_sub_dmrrow1
11368 0, // CTRRC:sub_dmr1_then_sub_dmrrowp0
11369 0, // CTRRC:sub_dmr1_then_sub_dmrrowp1
11370 0, // CTRRC:sub_dmr1_then_sub_wacc_hi
11371 0, // CTRRC:sub_dmr1_then_sub_wacc_lo
11372 0, // CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11373 0, // CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11374 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11375 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11376 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11377 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11378 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11379 0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11380 0, // CTRRC:sub_gp8_x1_then_sub_32
11381 },
11382 { // LRRC
11383 0, // LRRC:sub_32
11384 0, // LRRC:sub_32_hi_phony
11385 0, // LRRC:sub_64
11386 0, // LRRC:sub_64_hi_phony
11387 0, // LRRC:sub_dmr0
11388 0, // LRRC:sub_dmr1
11389 0, // LRRC:sub_dmrrow0
11390 0, // LRRC:sub_dmrrow1
11391 0, // LRRC:sub_dmrrowp0
11392 0, // LRRC:sub_dmrrowp1
11393 0, // LRRC:sub_eq
11394 0, // LRRC:sub_fp0
11395 0, // LRRC:sub_fp1
11396 0, // LRRC:sub_gp8_x0
11397 0, // LRRC:sub_gp8_x1
11398 0, // LRRC:sub_gt
11399 0, // LRRC:sub_lt
11400 0, // LRRC:sub_pair0
11401 0, // LRRC:sub_pair1
11402 0, // LRRC:sub_un
11403 0, // LRRC:sub_vsx0
11404 0, // LRRC:sub_vsx1
11405 0, // LRRC:sub_wacc_hi
11406 0, // LRRC:sub_wacc_lo
11407 0, // LRRC:sub_vsx1_then_sub_64
11408 0, // LRRC:sub_vsx1_then_sub_64_hi_phony
11409 0, // LRRC:sub_pair1_then_sub_64
11410 0, // LRRC:sub_pair1_then_sub_64_hi_phony
11411 0, // LRRC:sub_pair1_then_sub_vsx0
11412 0, // LRRC:sub_pair1_then_sub_vsx1
11413 0, // LRRC:sub_pair1_then_sub_vsx1_then_sub_64
11414 0, // LRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11415 0, // LRRC:sub_dmrrowp1_then_sub_dmrrow0
11416 0, // LRRC:sub_dmrrowp1_then_sub_dmrrow1
11417 0, // LRRC:sub_wacc_hi_then_sub_dmrrow0
11418 0, // LRRC:sub_wacc_hi_then_sub_dmrrow1
11419 0, // LRRC:sub_wacc_hi_then_sub_dmrrowp0
11420 0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1
11421 0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11422 0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11423 0, // LRRC:sub_dmr1_then_sub_dmrrow0
11424 0, // LRRC:sub_dmr1_then_sub_dmrrow1
11425 0, // LRRC:sub_dmr1_then_sub_dmrrowp0
11426 0, // LRRC:sub_dmr1_then_sub_dmrrowp1
11427 0, // LRRC:sub_dmr1_then_sub_wacc_hi
11428 0, // LRRC:sub_dmr1_then_sub_wacc_lo
11429 0, // LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11430 0, // LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11431 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11432 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11433 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11434 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11435 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11436 0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11437 0, // LRRC:sub_gp8_x1_then_sub_32
11438 },
11439 { // VRSAVERC
11440 0, // VRSAVERC:sub_32
11441 0, // VRSAVERC:sub_32_hi_phony
11442 0, // VRSAVERC:sub_64
11443 0, // VRSAVERC:sub_64_hi_phony
11444 0, // VRSAVERC:sub_dmr0
11445 0, // VRSAVERC:sub_dmr1
11446 0, // VRSAVERC:sub_dmrrow0
11447 0, // VRSAVERC:sub_dmrrow1
11448 0, // VRSAVERC:sub_dmrrowp0
11449 0, // VRSAVERC:sub_dmrrowp1
11450 0, // VRSAVERC:sub_eq
11451 0, // VRSAVERC:sub_fp0
11452 0, // VRSAVERC:sub_fp1
11453 0, // VRSAVERC:sub_gp8_x0
11454 0, // VRSAVERC:sub_gp8_x1
11455 0, // VRSAVERC:sub_gt
11456 0, // VRSAVERC:sub_lt
11457 0, // VRSAVERC:sub_pair0
11458 0, // VRSAVERC:sub_pair1
11459 0, // VRSAVERC:sub_un
11460 0, // VRSAVERC:sub_vsx0
11461 0, // VRSAVERC:sub_vsx1
11462 0, // VRSAVERC:sub_wacc_hi
11463 0, // VRSAVERC:sub_wacc_lo
11464 0, // VRSAVERC:sub_vsx1_then_sub_64
11465 0, // VRSAVERC:sub_vsx1_then_sub_64_hi_phony
11466 0, // VRSAVERC:sub_pair1_then_sub_64
11467 0, // VRSAVERC:sub_pair1_then_sub_64_hi_phony
11468 0, // VRSAVERC:sub_pair1_then_sub_vsx0
11469 0, // VRSAVERC:sub_pair1_then_sub_vsx1
11470 0, // VRSAVERC:sub_pair1_then_sub_vsx1_then_sub_64
11471 0, // VRSAVERC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11472 0, // VRSAVERC:sub_dmrrowp1_then_sub_dmrrow0
11473 0, // VRSAVERC:sub_dmrrowp1_then_sub_dmrrow1
11474 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrow0
11475 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrow1
11476 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp0
11477 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1
11478 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11479 0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11480 0, // VRSAVERC:sub_dmr1_then_sub_dmrrow0
11481 0, // VRSAVERC:sub_dmr1_then_sub_dmrrow1
11482 0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp0
11483 0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1
11484 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi
11485 0, // VRSAVERC:sub_dmr1_then_sub_wacc_lo
11486 0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11487 0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11488 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11489 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11490 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11491 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11492 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11493 0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11494 0, // VRSAVERC:sub_gp8_x1_then_sub_32
11495 },
11496 { // SPILLTOVSRRC
11497 2, // SPILLTOVSRRC:sub_32 -> GPRC
11498 0, // SPILLTOVSRRC:sub_32_hi_phony
11499 0, // SPILLTOVSRRC:sub_64
11500 0, // SPILLTOVSRRC:sub_64_hi_phony
11501 0, // SPILLTOVSRRC:sub_dmr0
11502 0, // SPILLTOVSRRC:sub_dmr1
11503 0, // SPILLTOVSRRC:sub_dmrrow0
11504 0, // SPILLTOVSRRC:sub_dmrrow1
11505 0, // SPILLTOVSRRC:sub_dmrrowp0
11506 0, // SPILLTOVSRRC:sub_dmrrowp1
11507 0, // SPILLTOVSRRC:sub_eq
11508 0, // SPILLTOVSRRC:sub_fp0
11509 0, // SPILLTOVSRRC:sub_fp1
11510 0, // SPILLTOVSRRC:sub_gp8_x0
11511 0, // SPILLTOVSRRC:sub_gp8_x1
11512 0, // SPILLTOVSRRC:sub_gt
11513 0, // SPILLTOVSRRC:sub_lt
11514 0, // SPILLTOVSRRC:sub_pair0
11515 0, // SPILLTOVSRRC:sub_pair1
11516 0, // SPILLTOVSRRC:sub_un
11517 0, // SPILLTOVSRRC:sub_vsx0
11518 0, // SPILLTOVSRRC:sub_vsx1
11519 0, // SPILLTOVSRRC:sub_wacc_hi
11520 0, // SPILLTOVSRRC:sub_wacc_lo
11521 0, // SPILLTOVSRRC:sub_vsx1_then_sub_64
11522 0, // SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
11523 0, // SPILLTOVSRRC:sub_pair1_then_sub_64
11524 0, // SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
11525 0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx0
11526 0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx1
11527 0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
11528 0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11529 0, // SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
11530 0, // SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
11531 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
11532 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
11533 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
11534 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
11535 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11536 0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11537 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
11538 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
11539 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
11540 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
11541 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
11542 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
11543 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11544 0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11545 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11546 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11547 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11548 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11549 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11550 0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11551 0, // SPILLTOVSRRC:sub_gp8_x1_then_sub_32
11552 },
11553 { // VSFRC
11554 0, // VSFRC:sub_32
11555 0, // VSFRC:sub_32_hi_phony
11556 0, // VSFRC:sub_64
11557 0, // VSFRC:sub_64_hi_phony
11558 0, // VSFRC:sub_dmr0
11559 0, // VSFRC:sub_dmr1
11560 0, // VSFRC:sub_dmrrow0
11561 0, // VSFRC:sub_dmrrow1
11562 0, // VSFRC:sub_dmrrowp0
11563 0, // VSFRC:sub_dmrrowp1
11564 0, // VSFRC:sub_eq
11565 0, // VSFRC:sub_fp0
11566 0, // VSFRC:sub_fp1
11567 0, // VSFRC:sub_gp8_x0
11568 0, // VSFRC:sub_gp8_x1
11569 0, // VSFRC:sub_gt
11570 0, // VSFRC:sub_lt
11571 0, // VSFRC:sub_pair0
11572 0, // VSFRC:sub_pair1
11573 0, // VSFRC:sub_un
11574 0, // VSFRC:sub_vsx0
11575 0, // VSFRC:sub_vsx1
11576 0, // VSFRC:sub_wacc_hi
11577 0, // VSFRC:sub_wacc_lo
11578 0, // VSFRC:sub_vsx1_then_sub_64
11579 0, // VSFRC:sub_vsx1_then_sub_64_hi_phony
11580 0, // VSFRC:sub_pair1_then_sub_64
11581 0, // VSFRC:sub_pair1_then_sub_64_hi_phony
11582 0, // VSFRC:sub_pair1_then_sub_vsx0
11583 0, // VSFRC:sub_pair1_then_sub_vsx1
11584 0, // VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
11585 0, // VSFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11586 0, // VSFRC:sub_dmrrowp1_then_sub_dmrrow0
11587 0, // VSFRC:sub_dmrrowp1_then_sub_dmrrow1
11588 0, // VSFRC:sub_wacc_hi_then_sub_dmrrow0
11589 0, // VSFRC:sub_wacc_hi_then_sub_dmrrow1
11590 0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp0
11591 0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1
11592 0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11593 0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11594 0, // VSFRC:sub_dmr1_then_sub_dmrrow0
11595 0, // VSFRC:sub_dmr1_then_sub_dmrrow1
11596 0, // VSFRC:sub_dmr1_then_sub_dmrrowp0
11597 0, // VSFRC:sub_dmr1_then_sub_dmrrowp1
11598 0, // VSFRC:sub_dmr1_then_sub_wacc_hi
11599 0, // VSFRC:sub_dmr1_then_sub_wacc_lo
11600 0, // VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11601 0, // VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11602 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11603 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11604 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11605 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11606 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11607 0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11608 0, // VSFRC:sub_gp8_x1_then_sub_32
11609 },
11610 { // G8RC
11611 2, // G8RC:sub_32 -> GPRC
11612 0, // G8RC:sub_32_hi_phony
11613 0, // G8RC:sub_64
11614 0, // G8RC:sub_64_hi_phony
11615 0, // G8RC:sub_dmr0
11616 0, // G8RC:sub_dmr1
11617 0, // G8RC:sub_dmrrow0
11618 0, // G8RC:sub_dmrrow1
11619 0, // G8RC:sub_dmrrowp0
11620 0, // G8RC:sub_dmrrowp1
11621 0, // G8RC:sub_eq
11622 0, // G8RC:sub_fp0
11623 0, // G8RC:sub_fp1
11624 0, // G8RC:sub_gp8_x0
11625 0, // G8RC:sub_gp8_x1
11626 0, // G8RC:sub_gt
11627 0, // G8RC:sub_lt
11628 0, // G8RC:sub_pair0
11629 0, // G8RC:sub_pair1
11630 0, // G8RC:sub_un
11631 0, // G8RC:sub_vsx0
11632 0, // G8RC:sub_vsx1
11633 0, // G8RC:sub_wacc_hi
11634 0, // G8RC:sub_wacc_lo
11635 0, // G8RC:sub_vsx1_then_sub_64
11636 0, // G8RC:sub_vsx1_then_sub_64_hi_phony
11637 0, // G8RC:sub_pair1_then_sub_64
11638 0, // G8RC:sub_pair1_then_sub_64_hi_phony
11639 0, // G8RC:sub_pair1_then_sub_vsx0
11640 0, // G8RC:sub_pair1_then_sub_vsx1
11641 0, // G8RC:sub_pair1_then_sub_vsx1_then_sub_64
11642 0, // G8RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11643 0, // G8RC:sub_dmrrowp1_then_sub_dmrrow0
11644 0, // G8RC:sub_dmrrowp1_then_sub_dmrrow1
11645 0, // G8RC:sub_wacc_hi_then_sub_dmrrow0
11646 0, // G8RC:sub_wacc_hi_then_sub_dmrrow1
11647 0, // G8RC:sub_wacc_hi_then_sub_dmrrowp0
11648 0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1
11649 0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11650 0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11651 0, // G8RC:sub_dmr1_then_sub_dmrrow0
11652 0, // G8RC:sub_dmr1_then_sub_dmrrow1
11653 0, // G8RC:sub_dmr1_then_sub_dmrrowp0
11654 0, // G8RC:sub_dmr1_then_sub_dmrrowp1
11655 0, // G8RC:sub_dmr1_then_sub_wacc_hi
11656 0, // G8RC:sub_dmr1_then_sub_wacc_lo
11657 0, // G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11658 0, // G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11659 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11660 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11661 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11662 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11663 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11664 0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11665 0, // G8RC:sub_gp8_x1_then_sub_32
11666 },
11667 { // G8RC_NOX0
11668 3, // G8RC_NOX0:sub_32 -> GPRC_NOR0
11669 0, // G8RC_NOX0:sub_32_hi_phony
11670 0, // G8RC_NOX0:sub_64
11671 0, // G8RC_NOX0:sub_64_hi_phony
11672 0, // G8RC_NOX0:sub_dmr0
11673 0, // G8RC_NOX0:sub_dmr1
11674 0, // G8RC_NOX0:sub_dmrrow0
11675 0, // G8RC_NOX0:sub_dmrrow1
11676 0, // G8RC_NOX0:sub_dmrrowp0
11677 0, // G8RC_NOX0:sub_dmrrowp1
11678 0, // G8RC_NOX0:sub_eq
11679 0, // G8RC_NOX0:sub_fp0
11680 0, // G8RC_NOX0:sub_fp1
11681 0, // G8RC_NOX0:sub_gp8_x0
11682 0, // G8RC_NOX0:sub_gp8_x1
11683 0, // G8RC_NOX0:sub_gt
11684 0, // G8RC_NOX0:sub_lt
11685 0, // G8RC_NOX0:sub_pair0
11686 0, // G8RC_NOX0:sub_pair1
11687 0, // G8RC_NOX0:sub_un
11688 0, // G8RC_NOX0:sub_vsx0
11689 0, // G8RC_NOX0:sub_vsx1
11690 0, // G8RC_NOX0:sub_wacc_hi
11691 0, // G8RC_NOX0:sub_wacc_lo
11692 0, // G8RC_NOX0:sub_vsx1_then_sub_64
11693 0, // G8RC_NOX0:sub_vsx1_then_sub_64_hi_phony
11694 0, // G8RC_NOX0:sub_pair1_then_sub_64
11695 0, // G8RC_NOX0:sub_pair1_then_sub_64_hi_phony
11696 0, // G8RC_NOX0:sub_pair1_then_sub_vsx0
11697 0, // G8RC_NOX0:sub_pair1_then_sub_vsx1
11698 0, // G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
11699 0, // G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11700 0, // G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
11701 0, // G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
11702 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
11703 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
11704 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
11705 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
11706 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11707 0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11708 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
11709 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
11710 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
11711 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
11712 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
11713 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
11714 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11715 0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11716 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11717 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11718 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11719 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11720 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11721 0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11722 0, // G8RC_NOX0:sub_gp8_x1_then_sub_32
11723 },
11724 { // SPILLTOVSRRC_and_VSFRC
11725 0, // SPILLTOVSRRC_and_VSFRC:sub_32
11726 0, // SPILLTOVSRRC_and_VSFRC:sub_32_hi_phony
11727 0, // SPILLTOVSRRC_and_VSFRC:sub_64
11728 0, // SPILLTOVSRRC_and_VSFRC:sub_64_hi_phony
11729 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr0
11730 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1
11731 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrow0
11732 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrow1
11733 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp0
11734 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1
11735 0, // SPILLTOVSRRC_and_VSFRC:sub_eq
11736 0, // SPILLTOVSRRC_and_VSFRC:sub_fp0
11737 0, // SPILLTOVSRRC_and_VSFRC:sub_fp1
11738 0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x0
11739 0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x1
11740 0, // SPILLTOVSRRC_and_VSFRC:sub_gt
11741 0, // SPILLTOVSRRC_and_VSFRC:sub_lt
11742 0, // SPILLTOVSRRC_and_VSFRC:sub_pair0
11743 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1
11744 0, // SPILLTOVSRRC_and_VSFRC:sub_un
11745 0, // SPILLTOVSRRC_and_VSFRC:sub_vsx0
11746 0, // SPILLTOVSRRC_and_VSFRC:sub_vsx1
11747 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi
11748 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_lo
11749 0, // SPILLTOVSRRC_and_VSFRC:sub_vsx1_then_sub_64
11750 0, // SPILLTOVSRRC_and_VSFRC:sub_vsx1_then_sub_64_hi_phony
11751 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_64
11752 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_64_hi_phony
11753 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx0
11754 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1
11755 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
11756 0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11757 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow0
11758 0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow1
11759 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow0
11760 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow1
11761 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp0
11762 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1
11763 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11764 0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11765 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow0
11766 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow1
11767 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp0
11768 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1
11769 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi
11770 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_lo
11771 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11772 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11773 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11774 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11775 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11776 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11777 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11778 0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11779 0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x1_then_sub_32
11780 },
11781 { // G8RC_and_G8RC_NOX0
11782 4, // G8RC_and_G8RC_NOX0:sub_32 -> GPRC_and_GPRC_NOR0
11783 0, // G8RC_and_G8RC_NOX0:sub_32_hi_phony
11784 0, // G8RC_and_G8RC_NOX0:sub_64
11785 0, // G8RC_and_G8RC_NOX0:sub_64_hi_phony
11786 0, // G8RC_and_G8RC_NOX0:sub_dmr0
11787 0, // G8RC_and_G8RC_NOX0:sub_dmr1
11788 0, // G8RC_and_G8RC_NOX0:sub_dmrrow0
11789 0, // G8RC_and_G8RC_NOX0:sub_dmrrow1
11790 0, // G8RC_and_G8RC_NOX0:sub_dmrrowp0
11791 0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1
11792 0, // G8RC_and_G8RC_NOX0:sub_eq
11793 0, // G8RC_and_G8RC_NOX0:sub_fp0
11794 0, // G8RC_and_G8RC_NOX0:sub_fp1
11795 0, // G8RC_and_G8RC_NOX0:sub_gp8_x0
11796 0, // G8RC_and_G8RC_NOX0:sub_gp8_x1
11797 0, // G8RC_and_G8RC_NOX0:sub_gt
11798 0, // G8RC_and_G8RC_NOX0:sub_lt
11799 0, // G8RC_and_G8RC_NOX0:sub_pair0
11800 0, // G8RC_and_G8RC_NOX0:sub_pair1
11801 0, // G8RC_and_G8RC_NOX0:sub_un
11802 0, // G8RC_and_G8RC_NOX0:sub_vsx0
11803 0, // G8RC_and_G8RC_NOX0:sub_vsx1
11804 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi
11805 0, // G8RC_and_G8RC_NOX0:sub_wacc_lo
11806 0, // G8RC_and_G8RC_NOX0:sub_vsx1_then_sub_64
11807 0, // G8RC_and_G8RC_NOX0:sub_vsx1_then_sub_64_hi_phony
11808 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_64
11809 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_64_hi_phony
11810 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx0
11811 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1
11812 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
11813 0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11814 0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
11815 0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
11816 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
11817 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
11818 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
11819 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
11820 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11821 0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11822 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
11823 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
11824 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
11825 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
11826 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
11827 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
11828 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11829 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11830 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11831 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11832 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11833 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11834 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11835 0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11836 0, // G8RC_and_G8RC_NOX0:sub_gp8_x1_then_sub_32
11837 },
11838 { // F8RC
11839 0, // F8RC:sub_32
11840 0, // F8RC:sub_32_hi_phony
11841 0, // F8RC:sub_64
11842 0, // F8RC:sub_64_hi_phony
11843 0, // F8RC:sub_dmr0
11844 0, // F8RC:sub_dmr1
11845 0, // F8RC:sub_dmrrow0
11846 0, // F8RC:sub_dmrrow1
11847 0, // F8RC:sub_dmrrowp0
11848 0, // F8RC:sub_dmrrowp1
11849 0, // F8RC:sub_eq
11850 0, // F8RC:sub_fp0
11851 0, // F8RC:sub_fp1
11852 0, // F8RC:sub_gp8_x0
11853 0, // F8RC:sub_gp8_x1
11854 0, // F8RC:sub_gt
11855 0, // F8RC:sub_lt
11856 0, // F8RC:sub_pair0
11857 0, // F8RC:sub_pair1
11858 0, // F8RC:sub_un
11859 0, // F8RC:sub_vsx0
11860 0, // F8RC:sub_vsx1
11861 0, // F8RC:sub_wacc_hi
11862 0, // F8RC:sub_wacc_lo
11863 0, // F8RC:sub_vsx1_then_sub_64
11864 0, // F8RC:sub_vsx1_then_sub_64_hi_phony
11865 0, // F8RC:sub_pair1_then_sub_64
11866 0, // F8RC:sub_pair1_then_sub_64_hi_phony
11867 0, // F8RC:sub_pair1_then_sub_vsx0
11868 0, // F8RC:sub_pair1_then_sub_vsx1
11869 0, // F8RC:sub_pair1_then_sub_vsx1_then_sub_64
11870 0, // F8RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11871 0, // F8RC:sub_dmrrowp1_then_sub_dmrrow0
11872 0, // F8RC:sub_dmrrowp1_then_sub_dmrrow1
11873 0, // F8RC:sub_wacc_hi_then_sub_dmrrow0
11874 0, // F8RC:sub_wacc_hi_then_sub_dmrrow1
11875 0, // F8RC:sub_wacc_hi_then_sub_dmrrowp0
11876 0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1
11877 0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11878 0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11879 0, // F8RC:sub_dmr1_then_sub_dmrrow0
11880 0, // F8RC:sub_dmr1_then_sub_dmrrow1
11881 0, // F8RC:sub_dmr1_then_sub_dmrrowp0
11882 0, // F8RC:sub_dmr1_then_sub_dmrrowp1
11883 0, // F8RC:sub_dmr1_then_sub_wacc_hi
11884 0, // F8RC:sub_dmr1_then_sub_wacc_lo
11885 0, // F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11886 0, // F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11887 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11888 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11889 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11890 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11891 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11892 0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11893 0, // F8RC:sub_gp8_x1_then_sub_32
11894 },
11895 { // FHRC
11896 0, // FHRC:sub_32
11897 0, // FHRC:sub_32_hi_phony
11898 0, // FHRC:sub_64
11899 0, // FHRC:sub_64_hi_phony
11900 0, // FHRC:sub_dmr0
11901 0, // FHRC:sub_dmr1
11902 0, // FHRC:sub_dmrrow0
11903 0, // FHRC:sub_dmrrow1
11904 0, // FHRC:sub_dmrrowp0
11905 0, // FHRC:sub_dmrrowp1
11906 0, // FHRC:sub_eq
11907 0, // FHRC:sub_fp0
11908 0, // FHRC:sub_fp1
11909 0, // FHRC:sub_gp8_x0
11910 0, // FHRC:sub_gp8_x1
11911 0, // FHRC:sub_gt
11912 0, // FHRC:sub_lt
11913 0, // FHRC:sub_pair0
11914 0, // FHRC:sub_pair1
11915 0, // FHRC:sub_un
11916 0, // FHRC:sub_vsx0
11917 0, // FHRC:sub_vsx1
11918 0, // FHRC:sub_wacc_hi
11919 0, // FHRC:sub_wacc_lo
11920 0, // FHRC:sub_vsx1_then_sub_64
11921 0, // FHRC:sub_vsx1_then_sub_64_hi_phony
11922 0, // FHRC:sub_pair1_then_sub_64
11923 0, // FHRC:sub_pair1_then_sub_64_hi_phony
11924 0, // FHRC:sub_pair1_then_sub_vsx0
11925 0, // FHRC:sub_pair1_then_sub_vsx1
11926 0, // FHRC:sub_pair1_then_sub_vsx1_then_sub_64
11927 0, // FHRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11928 0, // FHRC:sub_dmrrowp1_then_sub_dmrrow0
11929 0, // FHRC:sub_dmrrowp1_then_sub_dmrrow1
11930 0, // FHRC:sub_wacc_hi_then_sub_dmrrow0
11931 0, // FHRC:sub_wacc_hi_then_sub_dmrrow1
11932 0, // FHRC:sub_wacc_hi_then_sub_dmrrowp0
11933 0, // FHRC:sub_wacc_hi_then_sub_dmrrowp1
11934 0, // FHRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11935 0, // FHRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11936 0, // FHRC:sub_dmr1_then_sub_dmrrow0
11937 0, // FHRC:sub_dmr1_then_sub_dmrrow1
11938 0, // FHRC:sub_dmr1_then_sub_dmrrowp0
11939 0, // FHRC:sub_dmr1_then_sub_dmrrowp1
11940 0, // FHRC:sub_dmr1_then_sub_wacc_hi
11941 0, // FHRC:sub_dmr1_then_sub_wacc_lo
11942 0, // FHRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
11943 0, // FHRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
11944 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
11945 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
11946 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
11947 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
11948 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11949 0, // FHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11950 0, // FHRC:sub_gp8_x1_then_sub_32
11951 },
11952 { // SPERC
11953 2, // SPERC:sub_32 -> GPRC
11954 0, // SPERC:sub_32_hi_phony
11955 0, // SPERC:sub_64
11956 0, // SPERC:sub_64_hi_phony
11957 0, // SPERC:sub_dmr0
11958 0, // SPERC:sub_dmr1
11959 0, // SPERC:sub_dmrrow0
11960 0, // SPERC:sub_dmrrow1
11961 0, // SPERC:sub_dmrrowp0
11962 0, // SPERC:sub_dmrrowp1
11963 0, // SPERC:sub_eq
11964 0, // SPERC:sub_fp0
11965 0, // SPERC:sub_fp1
11966 0, // SPERC:sub_gp8_x0
11967 0, // SPERC:sub_gp8_x1
11968 0, // SPERC:sub_gt
11969 0, // SPERC:sub_lt
11970 0, // SPERC:sub_pair0
11971 0, // SPERC:sub_pair1
11972 0, // SPERC:sub_un
11973 0, // SPERC:sub_vsx0
11974 0, // SPERC:sub_vsx1
11975 0, // SPERC:sub_wacc_hi
11976 0, // SPERC:sub_wacc_lo
11977 0, // SPERC:sub_vsx1_then_sub_64
11978 0, // SPERC:sub_vsx1_then_sub_64_hi_phony
11979 0, // SPERC:sub_pair1_then_sub_64
11980 0, // SPERC:sub_pair1_then_sub_64_hi_phony
11981 0, // SPERC:sub_pair1_then_sub_vsx0
11982 0, // SPERC:sub_pair1_then_sub_vsx1
11983 0, // SPERC:sub_pair1_then_sub_vsx1_then_sub_64
11984 0, // SPERC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
11985 0, // SPERC:sub_dmrrowp1_then_sub_dmrrow0
11986 0, // SPERC:sub_dmrrowp1_then_sub_dmrrow1
11987 0, // SPERC:sub_wacc_hi_then_sub_dmrrow0
11988 0, // SPERC:sub_wacc_hi_then_sub_dmrrow1
11989 0, // SPERC:sub_wacc_hi_then_sub_dmrrowp0
11990 0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1
11991 0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
11992 0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
11993 0, // SPERC:sub_dmr1_then_sub_dmrrow0
11994 0, // SPERC:sub_dmr1_then_sub_dmrrow1
11995 0, // SPERC:sub_dmr1_then_sub_dmrrowp0
11996 0, // SPERC:sub_dmr1_then_sub_dmrrowp1
11997 0, // SPERC:sub_dmr1_then_sub_wacc_hi
11998 0, // SPERC:sub_dmr1_then_sub_wacc_lo
11999 0, // SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12000 0, // SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12001 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12002 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12003 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12004 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12005 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12006 0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12007 0, // SPERC:sub_gp8_x1_then_sub_32
12008 },
12009 { // VFHRC
12010 0, // VFHRC:sub_32
12011 0, // VFHRC:sub_32_hi_phony
12012 0, // VFHRC:sub_64
12013 0, // VFHRC:sub_64_hi_phony
12014 0, // VFHRC:sub_dmr0
12015 0, // VFHRC:sub_dmr1
12016 0, // VFHRC:sub_dmrrow0
12017 0, // VFHRC:sub_dmrrow1
12018 0, // VFHRC:sub_dmrrowp0
12019 0, // VFHRC:sub_dmrrowp1
12020 0, // VFHRC:sub_eq
12021 0, // VFHRC:sub_fp0
12022 0, // VFHRC:sub_fp1
12023 0, // VFHRC:sub_gp8_x0
12024 0, // VFHRC:sub_gp8_x1
12025 0, // VFHRC:sub_gt
12026 0, // VFHRC:sub_lt
12027 0, // VFHRC:sub_pair0
12028 0, // VFHRC:sub_pair1
12029 0, // VFHRC:sub_un
12030 0, // VFHRC:sub_vsx0
12031 0, // VFHRC:sub_vsx1
12032 0, // VFHRC:sub_wacc_hi
12033 0, // VFHRC:sub_wacc_lo
12034 0, // VFHRC:sub_vsx1_then_sub_64
12035 0, // VFHRC:sub_vsx1_then_sub_64_hi_phony
12036 0, // VFHRC:sub_pair1_then_sub_64
12037 0, // VFHRC:sub_pair1_then_sub_64_hi_phony
12038 0, // VFHRC:sub_pair1_then_sub_vsx0
12039 0, // VFHRC:sub_pair1_then_sub_vsx1
12040 0, // VFHRC:sub_pair1_then_sub_vsx1_then_sub_64
12041 0, // VFHRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12042 0, // VFHRC:sub_dmrrowp1_then_sub_dmrrow0
12043 0, // VFHRC:sub_dmrrowp1_then_sub_dmrrow1
12044 0, // VFHRC:sub_wacc_hi_then_sub_dmrrow0
12045 0, // VFHRC:sub_wacc_hi_then_sub_dmrrow1
12046 0, // VFHRC:sub_wacc_hi_then_sub_dmrrowp0
12047 0, // VFHRC:sub_wacc_hi_then_sub_dmrrowp1
12048 0, // VFHRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12049 0, // VFHRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12050 0, // VFHRC:sub_dmr1_then_sub_dmrrow0
12051 0, // VFHRC:sub_dmr1_then_sub_dmrrow1
12052 0, // VFHRC:sub_dmr1_then_sub_dmrrowp0
12053 0, // VFHRC:sub_dmr1_then_sub_dmrrowp1
12054 0, // VFHRC:sub_dmr1_then_sub_wacc_hi
12055 0, // VFHRC:sub_dmr1_then_sub_wacc_lo
12056 0, // VFHRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12057 0, // VFHRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12058 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12059 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12060 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12061 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12062 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12063 0, // VFHRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12064 0, // VFHRC:sub_gp8_x1_then_sub_32
12065 },
12066 { // VFRC
12067 0, // VFRC:sub_32
12068 0, // VFRC:sub_32_hi_phony
12069 0, // VFRC:sub_64
12070 0, // VFRC:sub_64_hi_phony
12071 0, // VFRC:sub_dmr0
12072 0, // VFRC:sub_dmr1
12073 0, // VFRC:sub_dmrrow0
12074 0, // VFRC:sub_dmrrow1
12075 0, // VFRC:sub_dmrrowp0
12076 0, // VFRC:sub_dmrrowp1
12077 0, // VFRC:sub_eq
12078 0, // VFRC:sub_fp0
12079 0, // VFRC:sub_fp1
12080 0, // VFRC:sub_gp8_x0
12081 0, // VFRC:sub_gp8_x1
12082 0, // VFRC:sub_gt
12083 0, // VFRC:sub_lt
12084 0, // VFRC:sub_pair0
12085 0, // VFRC:sub_pair1
12086 0, // VFRC:sub_un
12087 0, // VFRC:sub_vsx0
12088 0, // VFRC:sub_vsx1
12089 0, // VFRC:sub_wacc_hi
12090 0, // VFRC:sub_wacc_lo
12091 0, // VFRC:sub_vsx1_then_sub_64
12092 0, // VFRC:sub_vsx1_then_sub_64_hi_phony
12093 0, // VFRC:sub_pair1_then_sub_64
12094 0, // VFRC:sub_pair1_then_sub_64_hi_phony
12095 0, // VFRC:sub_pair1_then_sub_vsx0
12096 0, // VFRC:sub_pair1_then_sub_vsx1
12097 0, // VFRC:sub_pair1_then_sub_vsx1_then_sub_64
12098 0, // VFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12099 0, // VFRC:sub_dmrrowp1_then_sub_dmrrow0
12100 0, // VFRC:sub_dmrrowp1_then_sub_dmrrow1
12101 0, // VFRC:sub_wacc_hi_then_sub_dmrrow0
12102 0, // VFRC:sub_wacc_hi_then_sub_dmrrow1
12103 0, // VFRC:sub_wacc_hi_then_sub_dmrrowp0
12104 0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1
12105 0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12106 0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12107 0, // VFRC:sub_dmr1_then_sub_dmrrow0
12108 0, // VFRC:sub_dmr1_then_sub_dmrrow1
12109 0, // VFRC:sub_dmr1_then_sub_dmrrowp0
12110 0, // VFRC:sub_dmr1_then_sub_dmrrowp1
12111 0, // VFRC:sub_dmr1_then_sub_wacc_hi
12112 0, // VFRC:sub_dmr1_then_sub_wacc_lo
12113 0, // VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12114 0, // VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12115 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12116 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12117 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12118 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12119 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12120 0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12121 0, // VFRC:sub_gp8_x1_then_sub_32
12122 },
12123 { // SPERC_with_sub_32_in_GPRC_NOR0
12124 4, // SPERC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
12125 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_32_hi_phony
12126 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_64
12127 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_64_hi_phony
12128 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr0
12129 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1
12130 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
12131 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
12132 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
12133 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
12134 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_eq
12135 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_fp0
12136 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_fp1
12137 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0
12138 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1
12139 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gt
12140 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_lt
12141 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair0
12142 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1
12143 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_un
12144 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx0
12145 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1
12146 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
12147 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
12148 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
12149 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64_hi_phony
12150 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
12151 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64_hi_phony
12152 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
12153 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
12154 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
12155 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12156 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
12157 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
12158 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
12159 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
12160 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
12161 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
12162 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12163 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12164 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
12165 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
12166 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
12167 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
12168 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
12169 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
12170 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12171 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12172 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12173 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12174 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12175 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12176 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12177 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12178 0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32
12179 },
12180 { // SPILLTOVSRRC_and_VFRC
12181 0, // SPILLTOVSRRC_and_VFRC:sub_32
12182 0, // SPILLTOVSRRC_and_VFRC:sub_32_hi_phony
12183 0, // SPILLTOVSRRC_and_VFRC:sub_64
12184 0, // SPILLTOVSRRC_and_VFRC:sub_64_hi_phony
12185 0, // SPILLTOVSRRC_and_VFRC:sub_dmr0
12186 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1
12187 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrow0
12188 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrow1
12189 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
12190 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
12191 0, // SPILLTOVSRRC_and_VFRC:sub_eq
12192 0, // SPILLTOVSRRC_and_VFRC:sub_fp0
12193 0, // SPILLTOVSRRC_and_VFRC:sub_fp1
12194 0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x0
12195 0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x1
12196 0, // SPILLTOVSRRC_and_VFRC:sub_gt
12197 0, // SPILLTOVSRRC_and_VFRC:sub_lt
12198 0, // SPILLTOVSRRC_and_VFRC:sub_pair0
12199 0, // SPILLTOVSRRC_and_VFRC:sub_pair1
12200 0, // SPILLTOVSRRC_and_VFRC:sub_un
12201 0, // SPILLTOVSRRC_and_VFRC:sub_vsx0
12202 0, // SPILLTOVSRRC_and_VFRC:sub_vsx1
12203 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi
12204 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_lo
12205 0, // SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64
12206 0, // SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64_hi_phony
12207 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
12208 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64_hi_phony
12209 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
12210 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
12211 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
12212 0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12213 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
12214 0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
12215 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
12216 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
12217 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
12218 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
12219 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12220 0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12221 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
12222 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
12223 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
12224 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
12225 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
12226 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
12227 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12228 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12229 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12230 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12231 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12232 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12233 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12234 0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12235 0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
12236 },
12237 { // SPILLTOVSRRC_and_F4RC
12238 0, // SPILLTOVSRRC_and_F4RC:sub_32
12239 0, // SPILLTOVSRRC_and_F4RC:sub_32_hi_phony
12240 0, // SPILLTOVSRRC_and_F4RC:sub_64
12241 0, // SPILLTOVSRRC_and_F4RC:sub_64_hi_phony
12242 0, // SPILLTOVSRRC_and_F4RC:sub_dmr0
12243 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1
12244 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrow0
12245 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrow1
12246 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
12247 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
12248 0, // SPILLTOVSRRC_and_F4RC:sub_eq
12249 0, // SPILLTOVSRRC_and_F4RC:sub_fp0
12250 0, // SPILLTOVSRRC_and_F4RC:sub_fp1
12251 0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x0
12252 0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x1
12253 0, // SPILLTOVSRRC_and_F4RC:sub_gt
12254 0, // SPILLTOVSRRC_and_F4RC:sub_lt
12255 0, // SPILLTOVSRRC_and_F4RC:sub_pair0
12256 0, // SPILLTOVSRRC_and_F4RC:sub_pair1
12257 0, // SPILLTOVSRRC_and_F4RC:sub_un
12258 0, // SPILLTOVSRRC_and_F4RC:sub_vsx0
12259 0, // SPILLTOVSRRC_and_F4RC:sub_vsx1
12260 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi
12261 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_lo
12262 0, // SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64
12263 0, // SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64_hi_phony
12264 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
12265 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64_hi_phony
12266 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
12267 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
12268 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
12269 0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12270 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
12271 0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
12272 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
12273 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
12274 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
12275 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
12276 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12277 0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12278 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
12279 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
12280 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
12281 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
12282 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
12283 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
12284 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12285 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12286 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12287 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12288 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12289 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12290 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12291 0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12292 0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
12293 },
12294 { // CTRRC8
12295 0, // CTRRC8:sub_32
12296 0, // CTRRC8:sub_32_hi_phony
12297 0, // CTRRC8:sub_64
12298 0, // CTRRC8:sub_64_hi_phony
12299 0, // CTRRC8:sub_dmr0
12300 0, // CTRRC8:sub_dmr1
12301 0, // CTRRC8:sub_dmrrow0
12302 0, // CTRRC8:sub_dmrrow1
12303 0, // CTRRC8:sub_dmrrowp0
12304 0, // CTRRC8:sub_dmrrowp1
12305 0, // CTRRC8:sub_eq
12306 0, // CTRRC8:sub_fp0
12307 0, // CTRRC8:sub_fp1
12308 0, // CTRRC8:sub_gp8_x0
12309 0, // CTRRC8:sub_gp8_x1
12310 0, // CTRRC8:sub_gt
12311 0, // CTRRC8:sub_lt
12312 0, // CTRRC8:sub_pair0
12313 0, // CTRRC8:sub_pair1
12314 0, // CTRRC8:sub_un
12315 0, // CTRRC8:sub_vsx0
12316 0, // CTRRC8:sub_vsx1
12317 0, // CTRRC8:sub_wacc_hi
12318 0, // CTRRC8:sub_wacc_lo
12319 0, // CTRRC8:sub_vsx1_then_sub_64
12320 0, // CTRRC8:sub_vsx1_then_sub_64_hi_phony
12321 0, // CTRRC8:sub_pair1_then_sub_64
12322 0, // CTRRC8:sub_pair1_then_sub_64_hi_phony
12323 0, // CTRRC8:sub_pair1_then_sub_vsx0
12324 0, // CTRRC8:sub_pair1_then_sub_vsx1
12325 0, // CTRRC8:sub_pair1_then_sub_vsx1_then_sub_64
12326 0, // CTRRC8:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12327 0, // CTRRC8:sub_dmrrowp1_then_sub_dmrrow0
12328 0, // CTRRC8:sub_dmrrowp1_then_sub_dmrrow1
12329 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrow0
12330 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrow1
12331 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp0
12332 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1
12333 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12334 0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12335 0, // CTRRC8:sub_dmr1_then_sub_dmrrow0
12336 0, // CTRRC8:sub_dmr1_then_sub_dmrrow1
12337 0, // CTRRC8:sub_dmr1_then_sub_dmrrowp0
12338 0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1
12339 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi
12340 0, // CTRRC8:sub_dmr1_then_sub_wacc_lo
12341 0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12342 0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12343 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12344 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12345 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12346 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12347 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12348 0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12349 0, // CTRRC8:sub_gp8_x1_then_sub_32
12350 },
12351 { // LR8RC
12352 0, // LR8RC:sub_32
12353 0, // LR8RC:sub_32_hi_phony
12354 0, // LR8RC:sub_64
12355 0, // LR8RC:sub_64_hi_phony
12356 0, // LR8RC:sub_dmr0
12357 0, // LR8RC:sub_dmr1
12358 0, // LR8RC:sub_dmrrow0
12359 0, // LR8RC:sub_dmrrow1
12360 0, // LR8RC:sub_dmrrowp0
12361 0, // LR8RC:sub_dmrrowp1
12362 0, // LR8RC:sub_eq
12363 0, // LR8RC:sub_fp0
12364 0, // LR8RC:sub_fp1
12365 0, // LR8RC:sub_gp8_x0
12366 0, // LR8RC:sub_gp8_x1
12367 0, // LR8RC:sub_gt
12368 0, // LR8RC:sub_lt
12369 0, // LR8RC:sub_pair0
12370 0, // LR8RC:sub_pair1
12371 0, // LR8RC:sub_un
12372 0, // LR8RC:sub_vsx0
12373 0, // LR8RC:sub_vsx1
12374 0, // LR8RC:sub_wacc_hi
12375 0, // LR8RC:sub_wacc_lo
12376 0, // LR8RC:sub_vsx1_then_sub_64
12377 0, // LR8RC:sub_vsx1_then_sub_64_hi_phony
12378 0, // LR8RC:sub_pair1_then_sub_64
12379 0, // LR8RC:sub_pair1_then_sub_64_hi_phony
12380 0, // LR8RC:sub_pair1_then_sub_vsx0
12381 0, // LR8RC:sub_pair1_then_sub_vsx1
12382 0, // LR8RC:sub_pair1_then_sub_vsx1_then_sub_64
12383 0, // LR8RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12384 0, // LR8RC:sub_dmrrowp1_then_sub_dmrrow0
12385 0, // LR8RC:sub_dmrrowp1_then_sub_dmrrow1
12386 0, // LR8RC:sub_wacc_hi_then_sub_dmrrow0
12387 0, // LR8RC:sub_wacc_hi_then_sub_dmrrow1
12388 0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp0
12389 0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1
12390 0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12391 0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12392 0, // LR8RC:sub_dmr1_then_sub_dmrrow0
12393 0, // LR8RC:sub_dmr1_then_sub_dmrrow1
12394 0, // LR8RC:sub_dmr1_then_sub_dmrrowp0
12395 0, // LR8RC:sub_dmr1_then_sub_dmrrowp1
12396 0, // LR8RC:sub_dmr1_then_sub_wacc_hi
12397 0, // LR8RC:sub_dmr1_then_sub_wacc_lo
12398 0, // LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12399 0, // LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12400 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12401 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12402 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12403 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12404 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12405 0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12406 0, // LR8RC:sub_gp8_x1_then_sub_32
12407 },
12408 { // DMRROWRC
12409 0, // DMRROWRC:sub_32
12410 0, // DMRROWRC:sub_32_hi_phony
12411 0, // DMRROWRC:sub_64
12412 0, // DMRROWRC:sub_64_hi_phony
12413 0, // DMRROWRC:sub_dmr0
12414 0, // DMRROWRC:sub_dmr1
12415 0, // DMRROWRC:sub_dmrrow0
12416 0, // DMRROWRC:sub_dmrrow1
12417 0, // DMRROWRC:sub_dmrrowp0
12418 0, // DMRROWRC:sub_dmrrowp1
12419 0, // DMRROWRC:sub_eq
12420 0, // DMRROWRC:sub_fp0
12421 0, // DMRROWRC:sub_fp1
12422 0, // DMRROWRC:sub_gp8_x0
12423 0, // DMRROWRC:sub_gp8_x1
12424 0, // DMRROWRC:sub_gt
12425 0, // DMRROWRC:sub_lt
12426 0, // DMRROWRC:sub_pair0
12427 0, // DMRROWRC:sub_pair1
12428 0, // DMRROWRC:sub_un
12429 0, // DMRROWRC:sub_vsx0
12430 0, // DMRROWRC:sub_vsx1
12431 0, // DMRROWRC:sub_wacc_hi
12432 0, // DMRROWRC:sub_wacc_lo
12433 0, // DMRROWRC:sub_vsx1_then_sub_64
12434 0, // DMRROWRC:sub_vsx1_then_sub_64_hi_phony
12435 0, // DMRROWRC:sub_pair1_then_sub_64
12436 0, // DMRROWRC:sub_pair1_then_sub_64_hi_phony
12437 0, // DMRROWRC:sub_pair1_then_sub_vsx0
12438 0, // DMRROWRC:sub_pair1_then_sub_vsx1
12439 0, // DMRROWRC:sub_pair1_then_sub_vsx1_then_sub_64
12440 0, // DMRROWRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12441 0, // DMRROWRC:sub_dmrrowp1_then_sub_dmrrow0
12442 0, // DMRROWRC:sub_dmrrowp1_then_sub_dmrrow1
12443 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrow0
12444 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrow1
12445 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp0
12446 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1
12447 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12448 0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12449 0, // DMRROWRC:sub_dmr1_then_sub_dmrrow0
12450 0, // DMRROWRC:sub_dmr1_then_sub_dmrrow1
12451 0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp0
12452 0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1
12453 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi
12454 0, // DMRROWRC:sub_dmr1_then_sub_wacc_lo
12455 0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12456 0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12457 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12458 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12459 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12460 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12461 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12462 0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12463 0, // DMRROWRC:sub_gp8_x1_then_sub_32
12464 },
12465 { // VSRC
12466 0, // VSRC:sub_32
12467 0, // VSRC:sub_32_hi_phony
12468 1, // VSRC:sub_64 -> VSSRC
12469 0, // VSRC:sub_64_hi_phony
12470 0, // VSRC:sub_dmr0
12471 0, // VSRC:sub_dmr1
12472 0, // VSRC:sub_dmrrow0
12473 0, // VSRC:sub_dmrrow1
12474 0, // VSRC:sub_dmrrowp0
12475 0, // VSRC:sub_dmrrowp1
12476 0, // VSRC:sub_eq
12477 0, // VSRC:sub_fp0
12478 0, // VSRC:sub_fp1
12479 0, // VSRC:sub_gp8_x0
12480 0, // VSRC:sub_gp8_x1
12481 0, // VSRC:sub_gt
12482 0, // VSRC:sub_lt
12483 0, // VSRC:sub_pair0
12484 0, // VSRC:sub_pair1
12485 0, // VSRC:sub_un
12486 0, // VSRC:sub_vsx0
12487 0, // VSRC:sub_vsx1
12488 0, // VSRC:sub_wacc_hi
12489 0, // VSRC:sub_wacc_lo
12490 0, // VSRC:sub_vsx1_then_sub_64
12491 0, // VSRC:sub_vsx1_then_sub_64_hi_phony
12492 0, // VSRC:sub_pair1_then_sub_64
12493 0, // VSRC:sub_pair1_then_sub_64_hi_phony
12494 0, // VSRC:sub_pair1_then_sub_vsx0
12495 0, // VSRC:sub_pair1_then_sub_vsx1
12496 0, // VSRC:sub_pair1_then_sub_vsx1_then_sub_64
12497 0, // VSRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12498 0, // VSRC:sub_dmrrowp1_then_sub_dmrrow0
12499 0, // VSRC:sub_dmrrowp1_then_sub_dmrrow1
12500 0, // VSRC:sub_wacc_hi_then_sub_dmrrow0
12501 0, // VSRC:sub_wacc_hi_then_sub_dmrrow1
12502 0, // VSRC:sub_wacc_hi_then_sub_dmrrowp0
12503 0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1
12504 0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12505 0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12506 0, // VSRC:sub_dmr1_then_sub_dmrrow0
12507 0, // VSRC:sub_dmr1_then_sub_dmrrow1
12508 0, // VSRC:sub_dmr1_then_sub_dmrrowp0
12509 0, // VSRC:sub_dmr1_then_sub_dmrrowp1
12510 0, // VSRC:sub_dmr1_then_sub_wacc_hi
12511 0, // VSRC:sub_dmr1_then_sub_wacc_lo
12512 0, // VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12513 0, // VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12514 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12515 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12516 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12517 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12518 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12519 0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12520 0, // VSRC:sub_gp8_x1_then_sub_32
12521 },
12522 { // VSRC_with_sub_64_in_SPILLTOVSRRC
12523 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_32
12524 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
12525 17, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
12526 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
12527 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
12528 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
12529 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
12530 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
12531 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
12532 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
12533 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
12534 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
12535 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
12536 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
12537 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
12538 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
12539 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
12540 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
12541 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
12542 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_un
12543 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
12544 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
12545 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
12546 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
12547 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
12548 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
12549 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
12550 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
12551 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
12552 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
12553 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
12554 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12555 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
12556 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
12557 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
12558 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
12559 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
12560 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
12561 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12562 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12563 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
12564 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
12565 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
12566 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
12567 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
12568 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
12569 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12570 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12571 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12572 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12573 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12574 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12575 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12576 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12577 0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
12578 },
12579 { // VRRC
12580 0, // VRRC:sub_32
12581 0, // VRRC:sub_32_hi_phony
12582 23, // VRRC:sub_64 -> VFRC
12583 0, // VRRC:sub_64_hi_phony
12584 0, // VRRC:sub_dmr0
12585 0, // VRRC:sub_dmr1
12586 0, // VRRC:sub_dmrrow0
12587 0, // VRRC:sub_dmrrow1
12588 0, // VRRC:sub_dmrrowp0
12589 0, // VRRC:sub_dmrrowp1
12590 0, // VRRC:sub_eq
12591 0, // VRRC:sub_fp0
12592 0, // VRRC:sub_fp1
12593 0, // VRRC:sub_gp8_x0
12594 0, // VRRC:sub_gp8_x1
12595 0, // VRRC:sub_gt
12596 0, // VRRC:sub_lt
12597 0, // VRRC:sub_pair0
12598 0, // VRRC:sub_pair1
12599 0, // VRRC:sub_un
12600 0, // VRRC:sub_vsx0
12601 0, // VRRC:sub_vsx1
12602 0, // VRRC:sub_wacc_hi
12603 0, // VRRC:sub_wacc_lo
12604 0, // VRRC:sub_vsx1_then_sub_64
12605 0, // VRRC:sub_vsx1_then_sub_64_hi_phony
12606 0, // VRRC:sub_pair1_then_sub_64
12607 0, // VRRC:sub_pair1_then_sub_64_hi_phony
12608 0, // VRRC:sub_pair1_then_sub_vsx0
12609 0, // VRRC:sub_pair1_then_sub_vsx1
12610 0, // VRRC:sub_pair1_then_sub_vsx1_then_sub_64
12611 0, // VRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12612 0, // VRRC:sub_dmrrowp1_then_sub_dmrrow0
12613 0, // VRRC:sub_dmrrowp1_then_sub_dmrrow1
12614 0, // VRRC:sub_wacc_hi_then_sub_dmrrow0
12615 0, // VRRC:sub_wacc_hi_then_sub_dmrrow1
12616 0, // VRRC:sub_wacc_hi_then_sub_dmrrowp0
12617 0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1
12618 0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12619 0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12620 0, // VRRC:sub_dmr1_then_sub_dmrrow0
12621 0, // VRRC:sub_dmr1_then_sub_dmrrow1
12622 0, // VRRC:sub_dmr1_then_sub_dmrrowp0
12623 0, // VRRC:sub_dmr1_then_sub_dmrrowp1
12624 0, // VRRC:sub_dmr1_then_sub_wacc_hi
12625 0, // VRRC:sub_dmr1_then_sub_wacc_lo
12626 0, // VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12627 0, // VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12628 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12629 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12630 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12631 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12632 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12633 0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12634 0, // VRRC:sub_gp8_x1_then_sub_32
12635 },
12636 { // VSLRC
12637 0, // VSLRC:sub_32
12638 0, // VSLRC:sub_32_hi_phony
12639 6, // VSLRC:sub_64 -> F4RC
12640 0, // VSLRC:sub_64_hi_phony
12641 0, // VSLRC:sub_dmr0
12642 0, // VSLRC:sub_dmr1
12643 0, // VSLRC:sub_dmrrow0
12644 0, // VSLRC:sub_dmrrow1
12645 0, // VSLRC:sub_dmrrowp0
12646 0, // VSLRC:sub_dmrrowp1
12647 0, // VSLRC:sub_eq
12648 0, // VSLRC:sub_fp0
12649 0, // VSLRC:sub_fp1
12650 0, // VSLRC:sub_gp8_x0
12651 0, // VSLRC:sub_gp8_x1
12652 0, // VSLRC:sub_gt
12653 0, // VSLRC:sub_lt
12654 0, // VSLRC:sub_pair0
12655 0, // VSLRC:sub_pair1
12656 0, // VSLRC:sub_un
12657 0, // VSLRC:sub_vsx0
12658 0, // VSLRC:sub_vsx1
12659 0, // VSLRC:sub_wacc_hi
12660 0, // VSLRC:sub_wacc_lo
12661 0, // VSLRC:sub_vsx1_then_sub_64
12662 0, // VSLRC:sub_vsx1_then_sub_64_hi_phony
12663 0, // VSLRC:sub_pair1_then_sub_64
12664 0, // VSLRC:sub_pair1_then_sub_64_hi_phony
12665 0, // VSLRC:sub_pair1_then_sub_vsx0
12666 0, // VSLRC:sub_pair1_then_sub_vsx1
12667 0, // VSLRC:sub_pair1_then_sub_vsx1_then_sub_64
12668 0, // VSLRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12669 0, // VSLRC:sub_dmrrowp1_then_sub_dmrrow0
12670 0, // VSLRC:sub_dmrrowp1_then_sub_dmrrow1
12671 0, // VSLRC:sub_wacc_hi_then_sub_dmrrow0
12672 0, // VSLRC:sub_wacc_hi_then_sub_dmrrow1
12673 0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp0
12674 0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1
12675 0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12676 0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12677 0, // VSLRC:sub_dmr1_then_sub_dmrrow0
12678 0, // VSLRC:sub_dmr1_then_sub_dmrrow1
12679 0, // VSLRC:sub_dmr1_then_sub_dmrrowp0
12680 0, // VSLRC:sub_dmr1_then_sub_dmrrowp1
12681 0, // VSLRC:sub_dmr1_then_sub_wacc_hi
12682 0, // VSLRC:sub_dmr1_then_sub_wacc_lo
12683 0, // VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12684 0, // VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12685 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12686 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12687 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12688 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12689 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12690 0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12691 0, // VSLRC:sub_gp8_x1_then_sub_32
12692 },
12693 { // VRRC_with_sub_64_in_SPILLTOVSRRC
12694 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_32
12695 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
12696 25, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VFRC
12697 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
12698 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
12699 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
12700 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
12701 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
12702 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
12703 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
12704 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
12705 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
12706 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
12707 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
12708 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
12709 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
12710 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
12711 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
12712 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
12713 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_un
12714 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
12715 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
12716 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
12717 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
12718 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
12719 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
12720 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
12721 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
12722 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
12723 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
12724 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
12725 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12726 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
12727 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
12728 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
12729 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
12730 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
12731 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
12732 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12733 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12734 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
12735 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
12736 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
12737 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
12738 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
12739 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
12740 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12741 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12742 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12743 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12744 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12745 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12746 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12747 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12748 0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
12749 },
12750 { // FpRC
12751 0, // FpRC:sub_32
12752 0, // FpRC:sub_32_hi_phony
12753 0, // FpRC:sub_64
12754 0, // FpRC:sub_64_hi_phony
12755 0, // FpRC:sub_dmr0
12756 0, // FpRC:sub_dmr1
12757 0, // FpRC:sub_dmrrow0
12758 0, // FpRC:sub_dmrrow1
12759 0, // FpRC:sub_dmrrowp0
12760 0, // FpRC:sub_dmrrowp1
12761 0, // FpRC:sub_eq
12762 19, // FpRC:sub_fp0 -> F8RC
12763 19, // FpRC:sub_fp1 -> F8RC
12764 0, // FpRC:sub_gp8_x0
12765 0, // FpRC:sub_gp8_x1
12766 0, // FpRC:sub_gt
12767 0, // FpRC:sub_lt
12768 0, // FpRC:sub_pair0
12769 0, // FpRC:sub_pair1
12770 0, // FpRC:sub_un
12771 0, // FpRC:sub_vsx0
12772 0, // FpRC:sub_vsx1
12773 0, // FpRC:sub_wacc_hi
12774 0, // FpRC:sub_wacc_lo
12775 0, // FpRC:sub_vsx1_then_sub_64
12776 0, // FpRC:sub_vsx1_then_sub_64_hi_phony
12777 0, // FpRC:sub_pair1_then_sub_64
12778 0, // FpRC:sub_pair1_then_sub_64_hi_phony
12779 0, // FpRC:sub_pair1_then_sub_vsx0
12780 0, // FpRC:sub_pair1_then_sub_vsx1
12781 0, // FpRC:sub_pair1_then_sub_vsx1_then_sub_64
12782 0, // FpRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12783 0, // FpRC:sub_dmrrowp1_then_sub_dmrrow0
12784 0, // FpRC:sub_dmrrowp1_then_sub_dmrrow1
12785 0, // FpRC:sub_wacc_hi_then_sub_dmrrow0
12786 0, // FpRC:sub_wacc_hi_then_sub_dmrrow1
12787 0, // FpRC:sub_wacc_hi_then_sub_dmrrowp0
12788 0, // FpRC:sub_wacc_hi_then_sub_dmrrowp1
12789 0, // FpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12790 0, // FpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12791 0, // FpRC:sub_dmr1_then_sub_dmrrow0
12792 0, // FpRC:sub_dmr1_then_sub_dmrrow1
12793 0, // FpRC:sub_dmr1_then_sub_dmrrowp0
12794 0, // FpRC:sub_dmr1_then_sub_dmrrowp1
12795 0, // FpRC:sub_dmr1_then_sub_wacc_hi
12796 0, // FpRC:sub_dmr1_then_sub_wacc_lo
12797 0, // FpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12798 0, // FpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12799 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12800 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12801 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12802 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12803 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12804 0, // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12805 0, // FpRC:sub_gp8_x1_then_sub_32
12806 },
12807 { // G8pRC
12808 2, // G8pRC:sub_32 -> GPRC
12809 0, // G8pRC:sub_32_hi_phony
12810 0, // G8pRC:sub_64
12811 0, // G8pRC:sub_64_hi_phony
12812 0, // G8pRC:sub_dmr0
12813 0, // G8pRC:sub_dmr1
12814 0, // G8pRC:sub_dmrrow0
12815 0, // G8pRC:sub_dmrrow1
12816 0, // G8pRC:sub_dmrrowp0
12817 0, // G8pRC:sub_dmrrowp1
12818 0, // G8pRC:sub_eq
12819 0, // G8pRC:sub_fp0
12820 0, // G8pRC:sub_fp1
12821 15, // G8pRC:sub_gp8_x0 -> G8RC
12822 18, // G8pRC:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
12823 0, // G8pRC:sub_gt
12824 0, // G8pRC:sub_lt
12825 0, // G8pRC:sub_pair0
12826 0, // G8pRC:sub_pair1
12827 0, // G8pRC:sub_un
12828 0, // G8pRC:sub_vsx0
12829 0, // G8pRC:sub_vsx1
12830 0, // G8pRC:sub_wacc_hi
12831 0, // G8pRC:sub_wacc_lo
12832 0, // G8pRC:sub_vsx1_then_sub_64
12833 0, // G8pRC:sub_vsx1_then_sub_64_hi_phony
12834 0, // G8pRC:sub_pair1_then_sub_64
12835 0, // G8pRC:sub_pair1_then_sub_64_hi_phony
12836 0, // G8pRC:sub_pair1_then_sub_vsx0
12837 0, // G8pRC:sub_pair1_then_sub_vsx1
12838 0, // G8pRC:sub_pair1_then_sub_vsx1_then_sub_64
12839 0, // G8pRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12840 0, // G8pRC:sub_dmrrowp1_then_sub_dmrrow0
12841 0, // G8pRC:sub_dmrrowp1_then_sub_dmrrow1
12842 0, // G8pRC:sub_wacc_hi_then_sub_dmrrow0
12843 0, // G8pRC:sub_wacc_hi_then_sub_dmrrow1
12844 0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp0
12845 0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1
12846 0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12847 0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12848 0, // G8pRC:sub_dmr1_then_sub_dmrrow0
12849 0, // G8pRC:sub_dmr1_then_sub_dmrrow1
12850 0, // G8pRC:sub_dmr1_then_sub_dmrrowp0
12851 0, // G8pRC:sub_dmr1_then_sub_dmrrowp1
12852 0, // G8pRC:sub_dmr1_then_sub_wacc_hi
12853 0, // G8pRC:sub_dmr1_then_sub_wacc_lo
12854 0, // G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12855 0, // G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12856 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12857 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12858 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12859 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12860 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12861 0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12862 4, // G8pRC:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
12863 },
12864 { // G8pRC_with_sub_32_in_GPRC_NOR0
12865 4, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
12866 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_32_hi_phony
12867 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_64
12868 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_64_hi_phony
12869 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr0
12870 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1
12871 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
12872 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
12873 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
12874 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
12875 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_eq
12876 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_fp0
12877 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_fp1
12878 18, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0 -> G8RC_and_G8RC_NOX0
12879 18, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
12880 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gt
12881 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_lt
12882 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair0
12883 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1
12884 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_un
12885 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx0
12886 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1
12887 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
12888 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
12889 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
12890 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64_hi_phony
12891 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
12892 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64_hi_phony
12893 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
12894 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
12895 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
12896 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12897 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
12898 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
12899 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
12900 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
12901 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
12902 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
12903 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12904 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12905 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
12906 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
12907 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
12908 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
12909 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
12910 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
12911 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12912 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12913 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12914 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12915 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12916 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12917 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12918 0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12919 4, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
12920 },
12921 { // VSLRC_with_sub_64_in_SPILLTOVSRRC
12922 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_32
12923 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
12924 26, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
12925 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
12926 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
12927 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
12928 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
12929 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
12930 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
12931 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
12932 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
12933 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
12934 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
12935 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
12936 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
12937 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
12938 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
12939 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
12940 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
12941 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_un
12942 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
12943 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
12944 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
12945 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
12946 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
12947 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
12948 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
12949 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
12950 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
12951 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
12952 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
12953 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
12954 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
12955 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
12956 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
12957 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
12958 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
12959 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
12960 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12961 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12962 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
12963 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
12964 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
12965 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
12966 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
12967 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
12968 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
12969 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
12970 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
12971 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
12972 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
12973 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
12974 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
12975 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
12976 0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
12977 },
12978 { // FpRC_with_sub_fp0_in_SPILLTOVSRRC
12979 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_32
12980 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_32_hi_phony
12981 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_64
12982 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_64_hi_phony
12983 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr0
12984 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1
12985 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrow0
12986 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrow1
12987 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp0
12988 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1
12989 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_eq
12990 26, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_fp0 -> SPILLTOVSRRC_and_F4RC
12991 26, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_fp1 -> SPILLTOVSRRC_and_F4RC
12992 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x0
12993 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x1
12994 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gt
12995 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_lt
12996 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair0
12997 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1
12998 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_un
12999 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx0
13000 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx1
13001 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi
13002 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_lo
13003 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
13004 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13005 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_64
13006 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13007 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
13008 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
13009 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
13010 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13011 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13012 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13013 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13014 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13015 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13016 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13017 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13018 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13019 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13020 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13021 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13022 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13023 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13024 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13025 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13026 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13027 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13028 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13029 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13030 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13031 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13032 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13033 0, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13034 },
13035 { // DMRROWpRC
13036 0, // DMRROWpRC:sub_32
13037 0, // DMRROWpRC:sub_32_hi_phony
13038 0, // DMRROWpRC:sub_64
13039 0, // DMRROWpRC:sub_64_hi_phony
13040 0, // DMRROWpRC:sub_dmr0
13041 0, // DMRROWpRC:sub_dmr1
13042 29, // DMRROWpRC:sub_dmrrow0 -> DMRROWRC
13043 29, // DMRROWpRC:sub_dmrrow1 -> DMRROWRC
13044 0, // DMRROWpRC:sub_dmrrowp0
13045 0, // DMRROWpRC:sub_dmrrowp1
13046 0, // DMRROWpRC:sub_eq
13047 0, // DMRROWpRC:sub_fp0
13048 0, // DMRROWpRC:sub_fp1
13049 0, // DMRROWpRC:sub_gp8_x0
13050 0, // DMRROWpRC:sub_gp8_x1
13051 0, // DMRROWpRC:sub_gt
13052 0, // DMRROWpRC:sub_lt
13053 0, // DMRROWpRC:sub_pair0
13054 0, // DMRROWpRC:sub_pair1
13055 0, // DMRROWpRC:sub_un
13056 0, // DMRROWpRC:sub_vsx0
13057 0, // DMRROWpRC:sub_vsx1
13058 0, // DMRROWpRC:sub_wacc_hi
13059 0, // DMRROWpRC:sub_wacc_lo
13060 0, // DMRROWpRC:sub_vsx1_then_sub_64
13061 0, // DMRROWpRC:sub_vsx1_then_sub_64_hi_phony
13062 0, // DMRROWpRC:sub_pair1_then_sub_64
13063 0, // DMRROWpRC:sub_pair1_then_sub_64_hi_phony
13064 0, // DMRROWpRC:sub_pair1_then_sub_vsx0
13065 0, // DMRROWpRC:sub_pair1_then_sub_vsx1
13066 0, // DMRROWpRC:sub_pair1_then_sub_vsx1_then_sub_64
13067 0, // DMRROWpRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13068 0, // DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow0
13069 0, // DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow1
13070 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrow0
13071 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrow1
13072 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp0
13073 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1
13074 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13075 0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13076 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrow0
13077 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrow1
13078 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp0
13079 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1
13080 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi
13081 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_lo
13082 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13083 0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13084 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13085 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13086 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13087 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13088 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13089 0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13090 0, // DMRROWpRC:sub_gp8_x1_then_sub_32
13091 },
13092 { // VSRpRC
13093 0, // VSRpRC:sub_32
13094 0, // VSRpRC:sub_32_hi_phony
13095 14, // VSRpRC:sub_64 -> VSFRC
13096 0, // VSRpRC:sub_64_hi_phony
13097 0, // VSRpRC:sub_dmr0
13098 0, // VSRpRC:sub_dmr1
13099 0, // VSRpRC:sub_dmrrow0
13100 0, // VSRpRC:sub_dmrrow1
13101 0, // VSRpRC:sub_dmrrowp0
13102 0, // VSRpRC:sub_dmrrowp1
13103 0, // VSRpRC:sub_eq
13104 0, // VSRpRC:sub_fp0
13105 0, // VSRpRC:sub_fp1
13106 0, // VSRpRC:sub_gp8_x0
13107 0, // VSRpRC:sub_gp8_x1
13108 0, // VSRpRC:sub_gt
13109 0, // VSRpRC:sub_lt
13110 0, // VSRpRC:sub_pair0
13111 0, // VSRpRC:sub_pair1
13112 0, // VSRpRC:sub_un
13113 30, // VSRpRC:sub_vsx0 -> VSRC
13114 30, // VSRpRC:sub_vsx1 -> VSRC
13115 0, // VSRpRC:sub_wacc_hi
13116 0, // VSRpRC:sub_wacc_lo
13117 14, // VSRpRC:sub_vsx1_then_sub_64 -> VSFRC
13118 0, // VSRpRC:sub_vsx1_then_sub_64_hi_phony
13119 0, // VSRpRC:sub_pair1_then_sub_64
13120 0, // VSRpRC:sub_pair1_then_sub_64_hi_phony
13121 0, // VSRpRC:sub_pair1_then_sub_vsx0
13122 0, // VSRpRC:sub_pair1_then_sub_vsx1
13123 0, // VSRpRC:sub_pair1_then_sub_vsx1_then_sub_64
13124 0, // VSRpRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13125 0, // VSRpRC:sub_dmrrowp1_then_sub_dmrrow0
13126 0, // VSRpRC:sub_dmrrowp1_then_sub_dmrrow1
13127 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrow0
13128 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrow1
13129 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp0
13130 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1
13131 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13132 0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13133 0, // VSRpRC:sub_dmr1_then_sub_dmrrow0
13134 0, // VSRpRC:sub_dmr1_then_sub_dmrrow1
13135 0, // VSRpRC:sub_dmr1_then_sub_dmrrowp0
13136 0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1
13137 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi
13138 0, // VSRpRC:sub_dmr1_then_sub_wacc_lo
13139 0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13140 0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13141 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13142 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13143 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13144 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13145 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13146 0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13147 0, // VSRpRC:sub_gp8_x1_then_sub_32
13148 },
13149 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC
13150 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_32
13151 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13152 17, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
13153 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13154 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
13155 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
13156 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13157 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13158 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13159 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13160 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
13161 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
13162 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
13163 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13164 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13165 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
13166 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
13167 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
13168 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
13169 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_un
13170 31, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSRC_with_sub_64_in_SPILLTOVSRRC
13171 31, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSRC_with_sub_64_in_SPILLTOVSRRC
13172 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13173 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13174 17, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VSFRC
13175 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13176 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
13177 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13178 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
13179 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
13180 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
13181 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13182 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13183 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13184 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13185 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13186 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13187 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13188 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13189 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13190 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13191 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13192 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13193 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13194 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13195 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13196 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13197 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13198 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13199 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13200 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13201 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13202 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13203 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13204 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13205 },
13206 { // VSRpRC_with_sub_64_in_F4RC
13207 0, // VSRpRC_with_sub_64_in_F4RC:sub_32
13208 0, // VSRpRC_with_sub_64_in_F4RC:sub_32_hi_phony
13209 19, // VSRpRC_with_sub_64_in_F4RC:sub_64 -> F8RC
13210 0, // VSRpRC_with_sub_64_in_F4RC:sub_64_hi_phony
13211 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr0
13212 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1
13213 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrow0
13214 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrow1
13215 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp0
13216 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1
13217 0, // VSRpRC_with_sub_64_in_F4RC:sub_eq
13218 0, // VSRpRC_with_sub_64_in_F4RC:sub_fp0
13219 0, // VSRpRC_with_sub_64_in_F4RC:sub_fp1
13220 0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x0
13221 0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1
13222 0, // VSRpRC_with_sub_64_in_F4RC:sub_gt
13223 0, // VSRpRC_with_sub_64_in_F4RC:sub_lt
13224 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair0
13225 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1
13226 0, // VSRpRC_with_sub_64_in_F4RC:sub_un
13227 33, // VSRpRC_with_sub_64_in_F4RC:sub_vsx0 -> VSLRC
13228 33, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1 -> VSLRC
13229 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi
13230 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_lo
13231 19, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1_then_sub_64 -> F8RC
13232 0, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1_then_sub_64_hi_phony
13233 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_64
13234 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_64_hi_phony
13235 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx0
13236 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1
13237 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
13238 0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13239 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow0
13240 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow1
13241 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow0
13242 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow1
13243 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp0
13244 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1
13245 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13246 0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13247 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow0
13248 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow1
13249 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp0
13250 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1
13251 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi
13252 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_lo
13253 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13254 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13255 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13256 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13257 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13258 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13259 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13260 0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13261 0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1_then_sub_32
13262 },
13263 { // VSRpRC_with_sub_64_in_VFRC
13264 0, // VSRpRC_with_sub_64_in_VFRC:sub_32
13265 0, // VSRpRC_with_sub_64_in_VFRC:sub_32_hi_phony
13266 23, // VSRpRC_with_sub_64_in_VFRC:sub_64 -> VFRC
13267 0, // VSRpRC_with_sub_64_in_VFRC:sub_64_hi_phony
13268 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr0
13269 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1
13270 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrow0
13271 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrow1
13272 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp0
13273 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1
13274 0, // VSRpRC_with_sub_64_in_VFRC:sub_eq
13275 0, // VSRpRC_with_sub_64_in_VFRC:sub_fp0
13276 0, // VSRpRC_with_sub_64_in_VFRC:sub_fp1
13277 0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x0
13278 0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1
13279 0, // VSRpRC_with_sub_64_in_VFRC:sub_gt
13280 0, // VSRpRC_with_sub_64_in_VFRC:sub_lt
13281 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair0
13282 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1
13283 0, // VSRpRC_with_sub_64_in_VFRC:sub_un
13284 32, // VSRpRC_with_sub_64_in_VFRC:sub_vsx0 -> VRRC
13285 32, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1 -> VRRC
13286 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi
13287 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_lo
13288 23, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1_then_sub_64 -> VFRC
13289 0, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1_then_sub_64_hi_phony
13290 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_64
13291 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_64_hi_phony
13292 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx0
13293 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1
13294 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
13295 0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13296 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow0
13297 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow1
13298 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow0
13299 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow1
13300 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp0
13301 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1
13302 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13303 0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13304 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow0
13305 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow1
13306 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp0
13307 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1
13308 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi
13309 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_lo
13310 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13311 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13312 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13313 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13314 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13315 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13316 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13317 0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13318 0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1_then_sub_32
13319 },
13320 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
13321 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_32
13322 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_32_hi_phony
13323 25, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_64 -> SPILLTOVSRRC_and_VFRC
13324 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_64_hi_phony
13325 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr0
13326 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1
13327 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow0
13328 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow1
13329 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
13330 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
13331 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_eq
13332 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_fp0
13333 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_fp1
13334 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x0
13335 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1
13336 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gt
13337 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_lt
13338 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair0
13339 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1
13340 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_un
13341 34, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx0 -> VRRC_with_sub_64_in_SPILLTOVSRRC
13342 34, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1 -> VRRC_with_sub_64_in_SPILLTOVSRRC
13343 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi
13344 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_lo
13345 25, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VFRC
13346 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64_hi_phony
13347 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
13348 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64_hi_phony
13349 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
13350 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
13351 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
13352 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13353 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
13354 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
13355 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
13356 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
13357 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
13358 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
13359 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13360 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13361 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
13362 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
13363 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
13364 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
13365 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
13366 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
13367 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13368 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13369 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13370 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13371 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13372 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13373 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13374 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13375 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
13376 },
13377 { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13378 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_32
13379 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_32_hi_phony
13380 26, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_64 -> SPILLTOVSRRC_and_F4RC
13381 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_64_hi_phony
13382 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr0
13383 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1
13384 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow0
13385 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow1
13386 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
13387 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
13388 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_eq
13389 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_fp0
13390 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_fp1
13391 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x0
13392 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1
13393 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gt
13394 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_lt
13395 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair0
13396 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1
13397 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_un
13398 38, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13399 38, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13400 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi
13401 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_lo
13402 26, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13403 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64_hi_phony
13404 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
13405 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64_hi_phony
13406 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
13407 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
13408 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
13409 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13410 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
13411 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
13412 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
13413 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
13414 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
13415 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
13416 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13417 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13418 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
13419 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
13420 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
13421 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
13422 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
13423 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
13424 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13425 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13426 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13427 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13428 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13429 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13430 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13431 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13432 0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
13433 },
13434 { // ACCRC
13435 0, // ACCRC:sub_32
13436 0, // ACCRC:sub_32_hi_phony
13437 19, // ACCRC:sub_64 -> F8RC
13438 0, // ACCRC:sub_64_hi_phony
13439 0, // ACCRC:sub_dmr0
13440 0, // ACCRC:sub_dmr1
13441 0, // ACCRC:sub_dmrrow0
13442 0, // ACCRC:sub_dmrrow1
13443 0, // ACCRC:sub_dmrrowp0
13444 0, // ACCRC:sub_dmrrowp1
13445 0, // ACCRC:sub_eq
13446 0, // ACCRC:sub_fp0
13447 0, // ACCRC:sub_fp1
13448 0, // ACCRC:sub_gp8_x0
13449 0, // ACCRC:sub_gp8_x1
13450 0, // ACCRC:sub_gt
13451 0, // ACCRC:sub_lt
13452 43, // ACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
13453 43, // ACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
13454 0, // ACCRC:sub_un
13455 33, // ACCRC:sub_vsx0 -> VSLRC
13456 33, // ACCRC:sub_vsx1 -> VSLRC
13457 0, // ACCRC:sub_wacc_hi
13458 0, // ACCRC:sub_wacc_lo
13459 19, // ACCRC:sub_vsx1_then_sub_64 -> F8RC
13460 0, // ACCRC:sub_vsx1_then_sub_64_hi_phony
13461 19, // ACCRC:sub_pair1_then_sub_64 -> F8RC
13462 0, // ACCRC:sub_pair1_then_sub_64_hi_phony
13463 33, // ACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
13464 33, // ACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
13465 19, // ACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
13466 0, // ACCRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13467 0, // ACCRC:sub_dmrrowp1_then_sub_dmrrow0
13468 0, // ACCRC:sub_dmrrowp1_then_sub_dmrrow1
13469 0, // ACCRC:sub_wacc_hi_then_sub_dmrrow0
13470 0, // ACCRC:sub_wacc_hi_then_sub_dmrrow1
13471 0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp0
13472 0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1
13473 0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13474 0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13475 0, // ACCRC:sub_dmr1_then_sub_dmrrow0
13476 0, // ACCRC:sub_dmr1_then_sub_dmrrow1
13477 0, // ACCRC:sub_dmr1_then_sub_dmrrowp0
13478 0, // ACCRC:sub_dmr1_then_sub_dmrrowp1
13479 0, // ACCRC:sub_dmr1_then_sub_wacc_hi
13480 0, // ACCRC:sub_dmr1_then_sub_wacc_lo
13481 0, // ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13482 0, // ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13483 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13484 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13485 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13486 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13487 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13488 0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13489 0, // ACCRC:sub_gp8_x1_then_sub_32
13490 },
13491 { // UACCRC
13492 0, // UACCRC:sub_32
13493 0, // UACCRC:sub_32_hi_phony
13494 19, // UACCRC:sub_64 -> F8RC
13495 0, // UACCRC:sub_64_hi_phony
13496 0, // UACCRC:sub_dmr0
13497 0, // UACCRC:sub_dmr1
13498 0, // UACCRC:sub_dmrrow0
13499 0, // UACCRC:sub_dmrrow1
13500 0, // UACCRC:sub_dmrrowp0
13501 0, // UACCRC:sub_dmrrowp1
13502 0, // UACCRC:sub_eq
13503 0, // UACCRC:sub_fp0
13504 0, // UACCRC:sub_fp1
13505 0, // UACCRC:sub_gp8_x0
13506 0, // UACCRC:sub_gp8_x1
13507 0, // UACCRC:sub_gt
13508 0, // UACCRC:sub_lt
13509 43, // UACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
13510 43, // UACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
13511 0, // UACCRC:sub_un
13512 33, // UACCRC:sub_vsx0 -> VSLRC
13513 33, // UACCRC:sub_vsx1 -> VSLRC
13514 0, // UACCRC:sub_wacc_hi
13515 0, // UACCRC:sub_wacc_lo
13516 19, // UACCRC:sub_vsx1_then_sub_64 -> F8RC
13517 0, // UACCRC:sub_vsx1_then_sub_64_hi_phony
13518 19, // UACCRC:sub_pair1_then_sub_64 -> F8RC
13519 0, // UACCRC:sub_pair1_then_sub_64_hi_phony
13520 33, // UACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
13521 33, // UACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
13522 19, // UACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
13523 0, // UACCRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13524 0, // UACCRC:sub_dmrrowp1_then_sub_dmrrow0
13525 0, // UACCRC:sub_dmrrowp1_then_sub_dmrrow1
13526 0, // UACCRC:sub_wacc_hi_then_sub_dmrrow0
13527 0, // UACCRC:sub_wacc_hi_then_sub_dmrrow1
13528 0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp0
13529 0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1
13530 0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13531 0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13532 0, // UACCRC:sub_dmr1_then_sub_dmrrow0
13533 0, // UACCRC:sub_dmr1_then_sub_dmrrow1
13534 0, // UACCRC:sub_dmr1_then_sub_dmrrowp0
13535 0, // UACCRC:sub_dmr1_then_sub_dmrrowp1
13536 0, // UACCRC:sub_dmr1_then_sub_wacc_hi
13537 0, // UACCRC:sub_dmr1_then_sub_wacc_lo
13538 0, // UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13539 0, // UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13540 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13541 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13542 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13543 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13544 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13545 0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13546 0, // UACCRC:sub_gp8_x1_then_sub_32
13547 },
13548 { // WACCRC
13549 0, // WACCRC:sub_32
13550 0, // WACCRC:sub_32_hi_phony
13551 0, // WACCRC:sub_64
13552 0, // WACCRC:sub_64_hi_phony
13553 0, // WACCRC:sub_dmr0
13554 0, // WACCRC:sub_dmr1
13555 29, // WACCRC:sub_dmrrow0 -> DMRROWRC
13556 29, // WACCRC:sub_dmrrow1 -> DMRROWRC
13557 40, // WACCRC:sub_dmrrowp0 -> DMRROWpRC
13558 40, // WACCRC:sub_dmrrowp1 -> DMRROWpRC
13559 0, // WACCRC:sub_eq
13560 0, // WACCRC:sub_fp0
13561 0, // WACCRC:sub_fp1
13562 0, // WACCRC:sub_gp8_x0
13563 0, // WACCRC:sub_gp8_x1
13564 0, // WACCRC:sub_gt
13565 0, // WACCRC:sub_lt
13566 0, // WACCRC:sub_pair0
13567 0, // WACCRC:sub_pair1
13568 0, // WACCRC:sub_un
13569 0, // WACCRC:sub_vsx0
13570 0, // WACCRC:sub_vsx1
13571 0, // WACCRC:sub_wacc_hi
13572 0, // WACCRC:sub_wacc_lo
13573 0, // WACCRC:sub_vsx1_then_sub_64
13574 0, // WACCRC:sub_vsx1_then_sub_64_hi_phony
13575 0, // WACCRC:sub_pair1_then_sub_64
13576 0, // WACCRC:sub_pair1_then_sub_64_hi_phony
13577 0, // WACCRC:sub_pair1_then_sub_vsx0
13578 0, // WACCRC:sub_pair1_then_sub_vsx1
13579 0, // WACCRC:sub_pair1_then_sub_vsx1_then_sub_64
13580 0, // WACCRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13581 29, // WACCRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13582 29, // WACCRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13583 0, // WACCRC:sub_wacc_hi_then_sub_dmrrow0
13584 0, // WACCRC:sub_wacc_hi_then_sub_dmrrow1
13585 0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp0
13586 0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1
13587 0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13588 0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13589 0, // WACCRC:sub_dmr1_then_sub_dmrrow0
13590 0, // WACCRC:sub_dmr1_then_sub_dmrrow1
13591 0, // WACCRC:sub_dmr1_then_sub_dmrrowp0
13592 0, // WACCRC:sub_dmr1_then_sub_dmrrowp1
13593 0, // WACCRC:sub_dmr1_then_sub_wacc_hi
13594 0, // WACCRC:sub_dmr1_then_sub_wacc_lo
13595 0, // WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13596 0, // WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13597 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13598 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13599 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13600 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13601 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13602 0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13603 0, // WACCRC:sub_gp8_x1_then_sub_32
13604 },
13605 { // WACC_HIRC
13606 0, // WACC_HIRC:sub_32
13607 0, // WACC_HIRC:sub_32_hi_phony
13608 0, // WACC_HIRC:sub_64
13609 0, // WACC_HIRC:sub_64_hi_phony
13610 0, // WACC_HIRC:sub_dmr0
13611 0, // WACC_HIRC:sub_dmr1
13612 29, // WACC_HIRC:sub_dmrrow0 -> DMRROWRC
13613 29, // WACC_HIRC:sub_dmrrow1 -> DMRROWRC
13614 40, // WACC_HIRC:sub_dmrrowp0 -> DMRROWpRC
13615 40, // WACC_HIRC:sub_dmrrowp1 -> DMRROWpRC
13616 0, // WACC_HIRC:sub_eq
13617 0, // WACC_HIRC:sub_fp0
13618 0, // WACC_HIRC:sub_fp1
13619 0, // WACC_HIRC:sub_gp8_x0
13620 0, // WACC_HIRC:sub_gp8_x1
13621 0, // WACC_HIRC:sub_gt
13622 0, // WACC_HIRC:sub_lt
13623 0, // WACC_HIRC:sub_pair0
13624 0, // WACC_HIRC:sub_pair1
13625 0, // WACC_HIRC:sub_un
13626 0, // WACC_HIRC:sub_vsx0
13627 0, // WACC_HIRC:sub_vsx1
13628 0, // WACC_HIRC:sub_wacc_hi
13629 0, // WACC_HIRC:sub_wacc_lo
13630 0, // WACC_HIRC:sub_vsx1_then_sub_64
13631 0, // WACC_HIRC:sub_vsx1_then_sub_64_hi_phony
13632 0, // WACC_HIRC:sub_pair1_then_sub_64
13633 0, // WACC_HIRC:sub_pair1_then_sub_64_hi_phony
13634 0, // WACC_HIRC:sub_pair1_then_sub_vsx0
13635 0, // WACC_HIRC:sub_pair1_then_sub_vsx1
13636 0, // WACC_HIRC:sub_pair1_then_sub_vsx1_then_sub_64
13637 0, // WACC_HIRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13638 29, // WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13639 29, // WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13640 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrow0
13641 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrow1
13642 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp0
13643 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1
13644 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13645 0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13646 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrow0
13647 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrow1
13648 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp0
13649 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1
13650 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi
13651 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_lo
13652 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13653 0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13654 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13655 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13656 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13657 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13658 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13659 0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13660 0, // WACC_HIRC:sub_gp8_x1_then_sub_32
13661 },
13662 { // ACCRC_with_sub_64_in_SPILLTOVSRRC
13663 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
13664 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13665 26, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
13666 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13667 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
13668 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
13669 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13670 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13671 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13672 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13673 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
13674 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
13675 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
13676 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13677 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13678 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
13679 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
13680 46, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13681 43, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
13682 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
13683 38, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13684 38, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13685 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13686 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13687 26, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13688 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13689 19, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
13690 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13691 33, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
13692 33, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
13693 19, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
13694 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13695 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13696 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13697 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13698 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13699 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13700 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13701 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13702 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13703 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13704 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13705 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13706 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13707 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13708 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13709 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13710 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13711 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13712 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13713 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13714 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13715 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13716 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13717 0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13718 },
13719 { // UACCRC_with_sub_64_in_SPILLTOVSRRC
13720 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
13721 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13722 26, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
13723 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13724 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
13725 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
13726 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13727 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13728 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13729 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13730 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
13731 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
13732 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
13733 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13734 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13735 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
13736 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
13737 46, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13738 43, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
13739 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
13740 38, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13741 38, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13742 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13743 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13744 26, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13745 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13746 19, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
13747 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13748 33, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
13749 33, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
13750 19, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
13751 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13752 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13753 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13754 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13755 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13756 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13757 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13758 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13759 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13760 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13761 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13762 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13763 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13764 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13765 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13766 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13767 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13768 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13769 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13770 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13771 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13772 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13773 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13774 0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13775 },
13776 { // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
13777 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
13778 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13779 26, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
13780 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13781 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
13782 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
13783 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13784 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13785 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13786 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13787 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
13788 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp0
13789 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp1
13790 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13791 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13792 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
13793 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
13794 46, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13795 46, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13796 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
13797 38, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13798 38, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13799 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13800 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13801 26, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13802 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13803 26, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13804 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13805 38, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13806 38, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13807 26, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13808 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13809 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13810 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13811 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13812 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13813 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13814 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13815 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13816 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13817 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13818 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13819 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13820 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13821 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13822 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13823 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13824 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13825 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13826 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13827 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13828 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13829 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13830 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13831 0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13832 },
13833 { // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
13834 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
13835 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
13836 26, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
13837 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64_hi_phony
13838 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
13839 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
13840 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
13841 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
13842 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
13843 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
13844 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
13845 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp0
13846 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp1
13847 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
13848 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
13849 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
13850 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
13851 46, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13852 46, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
13853 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
13854 38, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13855 38, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13856 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
13857 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
13858 26, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13859 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64_hi_phony
13860 26, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13861 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64_hi_phony
13862 38, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13863 38, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
13864 26, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
13865 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13866 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
13867 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
13868 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
13869 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
13870 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
13871 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
13872 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13873 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13874 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
13875 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
13876 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
13877 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
13878 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
13879 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
13880 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13881 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13882 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13883 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13884 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13885 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13886 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13887 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13888 0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
13889 },
13890 { // DMRRC
13891 0, // DMRRC:sub_32
13892 0, // DMRRC:sub_32_hi_phony
13893 0, // DMRRC:sub_64
13894 0, // DMRRC:sub_64_hi_phony
13895 0, // DMRRC:sub_dmr0
13896 0, // DMRRC:sub_dmr1
13897 29, // DMRRC:sub_dmrrow0 -> DMRROWRC
13898 29, // DMRRC:sub_dmrrow1 -> DMRROWRC
13899 40, // DMRRC:sub_dmrrowp0 -> DMRROWpRC
13900 40, // DMRRC:sub_dmrrowp1 -> DMRROWpRC
13901 0, // DMRRC:sub_eq
13902 0, // DMRRC:sub_fp0
13903 0, // DMRRC:sub_fp1
13904 0, // DMRRC:sub_gp8_x0
13905 0, // DMRRC:sub_gp8_x1
13906 0, // DMRRC:sub_gt
13907 0, // DMRRC:sub_lt
13908 0, // DMRRC:sub_pair0
13909 0, // DMRRC:sub_pair1
13910 0, // DMRRC:sub_un
13911 0, // DMRRC:sub_vsx0
13912 0, // DMRRC:sub_vsx1
13913 50, // DMRRC:sub_wacc_hi -> WACC_HIRC
13914 49, // DMRRC:sub_wacc_lo -> WACCRC
13915 0, // DMRRC:sub_vsx1_then_sub_64
13916 0, // DMRRC:sub_vsx1_then_sub_64_hi_phony
13917 0, // DMRRC:sub_pair1_then_sub_64
13918 0, // DMRRC:sub_pair1_then_sub_64_hi_phony
13919 0, // DMRRC:sub_pair1_then_sub_vsx0
13920 0, // DMRRC:sub_pair1_then_sub_vsx1
13921 0, // DMRRC:sub_pair1_then_sub_vsx1_then_sub_64
13922 0, // DMRRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13923 29, // DMRRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13924 29, // DMRRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13925 29, // DMRRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
13926 29, // DMRRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
13927 40, // DMRRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
13928 40, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
13929 29, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13930 29, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13931 0, // DMRRC:sub_dmr1_then_sub_dmrrow0
13932 0, // DMRRC:sub_dmr1_then_sub_dmrrow1
13933 0, // DMRRC:sub_dmr1_then_sub_dmrrowp0
13934 0, // DMRRC:sub_dmr1_then_sub_dmrrowp1
13935 0, // DMRRC:sub_dmr1_then_sub_wacc_hi
13936 0, // DMRRC:sub_dmr1_then_sub_wacc_lo
13937 0, // DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
13938 0, // DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
13939 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
13940 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
13941 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
13942 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
13943 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
13944 0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
13945 0, // DMRRC:sub_gp8_x1_then_sub_32
13946 },
13947 { // DMRpRC
13948 0, // DMRpRC:sub_32
13949 0, // DMRpRC:sub_32_hi_phony
13950 0, // DMRpRC:sub_64
13951 0, // DMRpRC:sub_64_hi_phony
13952 55, // DMRpRC:sub_dmr0 -> DMRRC
13953 55, // DMRpRC:sub_dmr1 -> DMRRC
13954 29, // DMRpRC:sub_dmrrow0 -> DMRROWRC
13955 29, // DMRpRC:sub_dmrrow1 -> DMRROWRC
13956 40, // DMRpRC:sub_dmrrowp0 -> DMRROWpRC
13957 40, // DMRpRC:sub_dmrrowp1 -> DMRROWpRC
13958 0, // DMRpRC:sub_eq
13959 0, // DMRpRC:sub_fp0
13960 0, // DMRpRC:sub_fp1
13961 0, // DMRpRC:sub_gp8_x0
13962 0, // DMRpRC:sub_gp8_x1
13963 0, // DMRpRC:sub_gt
13964 0, // DMRpRC:sub_lt
13965 0, // DMRpRC:sub_pair0
13966 0, // DMRpRC:sub_pair1
13967 0, // DMRpRC:sub_un
13968 0, // DMRpRC:sub_vsx0
13969 0, // DMRpRC:sub_vsx1
13970 50, // DMRpRC:sub_wacc_hi -> WACC_HIRC
13971 49, // DMRpRC:sub_wacc_lo -> WACCRC
13972 0, // DMRpRC:sub_vsx1_then_sub_64
13973 0, // DMRpRC:sub_vsx1_then_sub_64_hi_phony
13974 0, // DMRpRC:sub_pair1_then_sub_64
13975 0, // DMRpRC:sub_pair1_then_sub_64_hi_phony
13976 0, // DMRpRC:sub_pair1_then_sub_vsx0
13977 0, // DMRpRC:sub_pair1_then_sub_vsx1
13978 0, // DMRpRC:sub_pair1_then_sub_vsx1_then_sub_64
13979 0, // DMRpRC:sub_pair1_then_sub_vsx1_then_sub_64_hi_phony
13980 29, // DMRpRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13981 29, // DMRpRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13982 29, // DMRpRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
13983 29, // DMRpRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
13984 40, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
13985 40, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
13986 29, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13987 29, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13988 29, // DMRpRC:sub_dmr1_then_sub_dmrrow0 -> DMRROWRC
13989 29, // DMRpRC:sub_dmr1_then_sub_dmrrow1 -> DMRROWRC
13990 40, // DMRpRC:sub_dmr1_then_sub_dmrrowp0 -> DMRROWpRC
13991 40, // DMRpRC:sub_dmr1_then_sub_dmrrowp1 -> DMRROWpRC
13992 50, // DMRpRC:sub_dmr1_then_sub_wacc_hi -> WACC_HIRC
13993 49, // DMRpRC:sub_dmr1_then_sub_wacc_lo -> WACCRC
13994 29, // DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
13995 29, // DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
13996 29, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
13997 29, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
13998 40, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
13999 40, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
14000 29, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
14001 29, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
14002 0, // DMRpRC:sub_gp8_x1_then_sub_32
14003 },
14004 };
14005 assert(RC && "Missing regclass");
14006 if (!Idx) return RC;
14007 --Idx;
14008 assert(Idx < 55 && "Bad subreg");
14009 unsigned TV = Table[RC->getID()][Idx];
14010 return TV ? getRegClass(TV - 1) : nullptr;
14011}
14012
14013/// Get the weight in units of pressure for this register class.
14014const RegClassWeight &PPCGenRegisterInfo::
14015getRegClassWeight(const TargetRegisterClass *RC) const {
14016 static const RegClassWeight RCWeightTable[] = {
14017 {1, 64}, // VSSRC
14018 {1, 34}, // GPRC
14019 {1, 34}, // GPRC_NOR0
14020 {1, 33}, // GPRC_and_GPRC_NOR0
14021 {1, 32}, // CRBITRC
14022 {1, 32}, // F4RC
14023 {0, 0}, // GPRC32
14024 {4, 32}, // CRRC
14025 {0, 0}, // CARRYRC
14026 {0, 0}, // CTRRC
14027 {0, 0}, // LRRC
14028 {1, 1}, // VRSAVERC
14029 {1, 68}, // SPILLTOVSRRC
14030 {1, 64}, // VSFRC
14031 {1, 34}, // G8RC
14032 {1, 34}, // G8RC_NOX0
14033 {1, 34}, // SPILLTOVSRRC_and_VSFRC
14034 {1, 33}, // G8RC_and_G8RC_NOX0
14035 {1, 32}, // F8RC
14036 {0, 0}, // FHRC
14037 {1, 32}, // SPERC
14038 {0, 0}, // VFHRC
14039 {1, 32}, // VFRC
14040 {1, 31}, // SPERC_with_sub_32_in_GPRC_NOR0
14041 {1, 20}, // SPILLTOVSRRC_and_VFRC
14042 {1, 14}, // SPILLTOVSRRC_and_F4RC
14043 {0, 0}, // CTRRC8
14044 {0, 0}, // LR8RC
14045 {1, 64}, // DMRROWRC
14046 {1, 64}, // VSRC
14047 {1, 34}, // VSRC_with_sub_64_in_SPILLTOVSRRC
14048 {1, 32}, // VRRC
14049 {1, 32}, // VSLRC
14050 {1, 20}, // VRRC_with_sub_64_in_SPILLTOVSRRC
14051 {2, 32}, // FpRC
14052 {2, 32}, // G8pRC
14053 {2, 30}, // G8pRC_with_sub_32_in_GPRC_NOR0
14054 {1, 14}, // VSLRC_with_sub_64_in_SPILLTOVSRRC
14055 {2, 14}, // FpRC_with_sub_fp0_in_SPILLTOVSRRC
14056 {2, 64}, // DMRROWpRC
14057 {2, 64}, // VSRpRC
14058 {2, 34}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC
14059 {2, 32}, // VSRpRC_with_sub_64_in_F4RC
14060 {2, 32}, // VSRpRC_with_sub_64_in_VFRC
14061 {2, 20}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
14062 {2, 14}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
14063 {4, 32}, // ACCRC
14064 {4, 32}, // UACCRC
14065 {4, 32}, // WACCRC
14066 {4, 32}, // WACC_HIRC
14067 {4, 16}, // ACCRC_with_sub_64_in_SPILLTOVSRRC
14068 {4, 16}, // UACCRC_with_sub_64_in_SPILLTOVSRRC
14069 {4, 12}, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
14070 {4, 12}, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
14071 {8, 64}, // DMRRC
14072 {16, 64}, // DMRpRC
14073 };
14074 return RCWeightTable[RC->getID()];
14075}
14076
14077/// Get the weight in units of pressure for this register unit.
14078unsigned PPCGenRegisterInfo::
14079getRegUnitWeight(unsigned RegUnit) const {
14080 assert(RegUnit < 335 && "invalid register unit");
14081 // All register units have unit weight.
14082 return 1;
14083}
14084
14085
14086// Get the number of dimensions of register pressure.
14087unsigned PPCGenRegisterInfo::getNumRegPressureSets() const {
14088 return 19;
14089}
14090
14091// Get the name of this register unit pressure set.
14092const char *PPCGenRegisterInfo::
14093getRegPressureSetName(unsigned Idx) const {
14094 static const char *PressureNameTable[] = {
14095 "VRSAVERC",
14096 "SPILLTOVSRRC_and_F4RC",
14097 "SPILLTOVSRRC_and_VFRC",
14098 "CRBITRC",
14099 "F4RC",
14100 "VFRC",
14101 "WACCRC",
14102 "WACC_HIRC",
14103 "GPRC",
14104 "SPILLTOVSRRC_and_VSFRC",
14105 "SPILLTOVSRRC_and_VSFRC_with_VFRC",
14106 "F4RC_with_SPILLTOVSRRC_and_VSFRC",
14107 "VSSRC",
14108 "DMRROWRC",
14109 "SPILLTOVSRRC",
14110 "SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC",
14111 "SPILLTOVSRRC_with_VFRC",
14112 "F4RC_with_SPILLTOVSRRC",
14113 "VSSRC_with_SPILLTOVSRRC",
14114 };
14115 return PressureNameTable[Idx];
14116}
14117
14118// Get the register unit pressure limit for this dimension.
14119// This limit must be adjusted dynamically for reserved registers.
14120unsigned PPCGenRegisterInfo::
14121getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
14122 static const uint8_t PressureLimitTable[] = {
14123 1, // 0: VRSAVERC
14124 16, // 1: SPILLTOVSRRC_and_F4RC
14125 20, // 2: SPILLTOVSRRC_and_VFRC
14126 32, // 3: CRBITRC
14127 32, // 4: F4RC
14128 32, // 5: VFRC
14129 32, // 6: WACCRC
14130 32, // 7: WACC_HIRC
14131 35, // 8: GPRC
14132 36, // 9: SPILLTOVSRRC_and_VSFRC
14133 46, // 10: SPILLTOVSRRC_and_VSFRC_with_VFRC
14134 52, // 11: F4RC_with_SPILLTOVSRRC_and_VSFRC
14135 64, // 12: VSSRC
14136 64, // 13: DMRROWRC
14137 69, // 14: SPILLTOVSRRC
14138 70, // 15: SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC
14139 80, // 16: SPILLTOVSRRC_with_VFRC
14140 86, // 17: F4RC_with_SPILLTOVSRRC
14141 98, // 18: VSSRC_with_SPILLTOVSRRC
14142 };
14143 return PressureLimitTable[Idx];
14144}
14145
14146/// Table of pressure sets per register class or unit.
14147static const int RCSetsTable[] = {
14148 /* 0 */ 0, -1,
14149 /* 2 */ 3, -1,
14150 /* 4 */ 6, 13, -1,
14151 /* 7 */ 7, 13, -1,
14152 /* 10 */ 8, 14, -1,
14153 /* 13 */ 12, 18, -1,
14154 /* 16 */ 5, 10, 12, 16, 18, -1,
14155 /* 22 */ 4, 11, 12, 17, 18, -1,
14156 /* 28 */ 1, 4, 9, 11, 12, 15, 17, 18, -1,
14157 /* 37 */ 8, 14, 15, 16, 17, 18, -1,
14158 /* 44 */ 1, 4, 9, 10, 11, 12, 14, 15, 16, 17, 18, -1,
14159 /* 56 */ 2, 5, 9, 10, 11, 12, 14, 15, 16, 17, 18, -1,
14160};
14161
14162/// Get the dimensions of register pressure impacted by this register class.
14163/// Returns a -1 terminated array of pressure set IDs
14164const int *PPCGenRegisterInfo::
14165getRegClassPressureSets(const TargetRegisterClass *RC) const {
14166 static const uint8_t RCSetStartTable[] = {
14167 13,37,10,37,2,22,1,2,1,1,1,0,38,13,37,10,46,37,22,1,37,1,16,37,56,44,1,1,5,13,46,16,22,56,22,37,37,44,44,5,13,46,22,16,56,44,22,22,4,7,28,28,44,44,5,5,};
14168 return &RCSetsTable[RCSetStartTable[RC->getID()]];
14169}
14170
14171/// Get the dimensions of register pressure impacted by this register unit.
14172/// Returns a -1 terminated array of pressure set IDs
14173const int *PPCGenRegisterInfo::
14174getRegUnitPressureSets(unsigned RegUnit) const {
14175 assert(RegUnit < 335 && "invalid register unit");
14176 static const uint8_t RUSetStartTable[] = {
14177 37,1,1,1,1,37,1,1,1,1,0,1,10,44,1,44,1,44,1,44,1,44,1,44,1,44,1,44,1,44,1,44,1,44,1,44,1,44,1,44,1,28,1,28,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,22,1,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,1,4,4,4,4,7,7,7,7,4,4,4,4,7,7,7,7,4,4,4,4,7,7,7,7,4,4,4,4,7,7,7,7,4,4,4,4,7,7,7,7,4,4,4,4,7,7,7,7,4,4,4,4,7,7,7,7,4,4,4,4,7,7,7,7,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,56,1,16,1,16,1,16,1,16,1,16,1,16,1,16,1,16,1,16,1,16,1,16,1,16,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
14178 return &RCSetsTable[RUSetStartTable[RegUnit]];
14179}
14180
14181extern const MCRegisterDesc PPCRegDesc[];
14182extern const int16_t PPCRegDiffLists[];
14183extern const LaneBitmask PPCLaneMaskLists[];
14184extern const char PPCRegStrings[];
14185extern const char PPCRegClassStrings[];
14186extern const MCPhysReg PPCRegUnitRoots[][2];
14187extern const uint16_t PPCSubRegIdxLists[];
14188extern const uint16_t PPCRegEncodingTable[];
14189// PPC Dwarf<->LLVM register mappings.
14190extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[];
14191extern const unsigned PPCDwarfFlavour0Dwarf2LSize;
14192
14193extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[];
14194extern const unsigned PPCDwarfFlavour1Dwarf2LSize;
14195
14196extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[];
14197extern const unsigned PPCEHFlavour0Dwarf2LSize;
14198
14199extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[];
14200extern const unsigned PPCEHFlavour1Dwarf2LSize;
14201
14202extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[];
14203extern const unsigned PPCDwarfFlavour0L2DwarfSize;
14204
14205extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[];
14206extern const unsigned PPCDwarfFlavour1L2DwarfSize;
14207
14208extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[];
14209extern const unsigned PPCEHFlavour0L2DwarfSize;
14210
14211extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[];
14212extern const unsigned PPCEHFlavour1L2DwarfSize;
14213
14214PPCGenRegisterInfo::
14215PPCGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
14216 unsigned PC, unsigned HwMode)
14217 : TargetRegisterInfo(&PPCRegInfoDesc, RegisterClasses, RegisterClasses+56,
14218 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
14219 LaneBitmask(0xFFFFFFFE00000002), RegClassInfos, VTLists, HwMode) {
14220 InitMCRegisterInfo(PPCRegDesc, 612, RA, PC,
14221 PPCMCRegisterClasses, 56,
14222 PPCRegUnitRoots,
14223 335,
14224 PPCRegDiffLists,
14225 PPCLaneMaskLists,
14226 PPCRegStrings,
14227 PPCRegClassStrings,
14228 PPCSubRegIdxLists,
14229 56,
14230 PPCRegEncodingTable);
14231
14232 switch (DwarfFlavour) {
14233 default:
14234 llvm_unreachable("Unknown DWARF flavour");
14235 case 0:
14236 mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
14237 break;
14238 case 1:
14239 mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
14240 break;
14241 }
14242 switch (EHFlavour) {
14243 default:
14244 llvm_unreachable("Unknown DWARF flavour");
14245 case 0:
14246 mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
14247 break;
14248 case 1:
14249 mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
14250 break;
14251 }
14252 switch (DwarfFlavour) {
14253 default:
14254 llvm_unreachable("Unknown DWARF flavour");
14255 case 0:
14256 mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
14257 break;
14258 case 1:
14259 mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
14260 break;
14261 }
14262 switch (EHFlavour) {
14263 default:
14264 llvm_unreachable("Unknown DWARF flavour");
14265 case 0:
14266 mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
14267 break;
14268 case 1:
14269 mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
14270 break;
14271 }
14272}
14273
14274static const MCPhysReg CSR_64_AllRegs_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
14275static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0xc8000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14276static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, 0 };
14277static const uint32_t CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0xc8000000, 0x07fffe3f, 0x00000000, 0x007ffff8, 0x007ffff8, 0x007ffff8, 0x00000000, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14278static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 0 };
14279static const uint32_t CSR_64_AllRegs_AIX_Dflt_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x1fffffff, 0x00000000, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0x007fffff, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14280static const MCPhysReg CSR_64_AllRegs_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14281static const uint32_t CSR_64_AllRegs_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0x00000007, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14282static const MCPhysReg CSR_64_AllRegs_VSRP_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14283static const uint32_t CSR_64_AllRegs_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000007, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14284static const MCPhysReg CSR_64_AllRegs_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 0 };
14285static const uint32_t CSR_64_AllRegs_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000007, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
14286static const MCPhysReg CSR_AIX32_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
14287static const uint32_t CSR_AIX32_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07ffff00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14288static const MCPhysReg CSR_AIX32_Altivec_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14289static const uint32_t CSR_AIX32_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07ffff00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14290static const MCPhysReg CSR_AIX32_VSRP_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14291static const uint32_t CSR_AIX32_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07ffff00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14292static const MCPhysReg CSR_AIX64_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
14293static const uint32_t CSR_AIX64_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14294static const MCPhysReg CSR_AIX64_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14295static const uint32_t CSR_AIX64_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14296static const MCPhysReg CSR_ALL_VSRP_SaveList[] = { PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14297static const uint32_t CSR_ALL_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000007, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14298static const MCPhysReg CSR_Altivec_SaveList[] = { PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14299static const uint32_t CSR_Altivec_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14300static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
14301static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14302static const MCPhysReg CSR_PPC64_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
14303static const uint32_t CSR_PPC64_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14304static const MCPhysReg CSR_PPC64_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14305static const uint32_t CSR_PPC64_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14306static const MCPhysReg CSR_PPC64_R2_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 };
14307static const uint32_t CSR_PPC64_R2_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x20000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14308static const MCPhysReg CSR_PPC64_R2_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
14309static const uint32_t CSR_PPC64_R2_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14310static const MCPhysReg CSR_SPE_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
14311static const uint32_t CSR_SPE_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffff00, 0x03fffe00, 0x03fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14312static const MCPhysReg CSR_SPE_NO_S30_31_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
14313static const uint32_t CSR_SPE_NO_S30_31_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ffff00, 0x01fffe00, 0x01fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14314static const MCPhysReg CSR_SVR32_ColdCC_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
14315static const uint32_t CSR_SVR32_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14316static const MCPhysReg CSR_SVR32_ColdCC_Altivec_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14317static const uint32_t CSR_SVR32_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14318static const MCPhysReg CSR_SVR32_ColdCC_Common_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
14319static const uint32_t CSR_SVR32_ColdCC_Common_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14320static const MCPhysReg CSR_SVR32_ColdCC_SPE_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 };
14321static const uint32_t CSR_SVR32_ColdCC_SPE_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000000, 0x83ffff1f, 0x87fffe3f, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14322static const MCPhysReg CSR_SVR32_ColdCC_VSRP_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14323static const uint32_t CSR_SVR32_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffdf, 0xffffffff, 0xffefffff, 0x00000007, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
14324static const MCPhysReg CSR_SVR64_ColdCC_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
14325static const uint32_t CSR_SVR64_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
14326static const MCPhysReg CSR_SVR64_ColdCC_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14327static const uint32_t CSR_SVR64_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
14328static const MCPhysReg CSR_SVR64_ColdCC_R2_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::X2, 0 };
14329static const uint32_t CSR_SVR64_ColdCC_R2_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0xa0000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
14330static const MCPhysReg CSR_SVR64_ColdCC_R2_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
14331static const uint32_t CSR_SVR64_ColdCC_R2_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x00000000, 0xa0000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
14332static const MCPhysReg CSR_SVR64_ColdCC_R2_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
14333static const uint32_t CSR_SVR64_ColdCC_R2_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0xa0000000, 0x07fffe3f, 0x00000000, 0xffffff98, 0xffffff9f, 0xffffff9f, 0xffffffff, 0xffefffff, 0x00000007, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
14334static const MCPhysReg CSR_SVR64_ColdCC_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14335static const uint32_t CSR_SVR64_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xffffffff, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffff98, 0xffffff9f, 0xffffff9f, 0xffffffff, 0xffefffff, 0x00000007, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
14336static const MCPhysReg CSR_SVR432_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
14337static const uint32_t CSR_SVR432_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14338static const MCPhysReg CSR_SVR432_Altivec_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
14339static const uint32_t CSR_SVR432_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14340static const MCPhysReg CSR_SVR432_COMM_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
14341static const uint32_t CSR_SVR432_COMM_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14342static const MCPhysReg CSR_SVR432_SPE_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
14343static const uint32_t CSR_SVR432_SPE_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffff00, 0x07fffe00, 0x03fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14344static const MCPhysReg CSR_SVR432_SPE_NO_S30_31_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
14345static const uint32_t CSR_SVR432_SPE_NO_S30_31_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ffff00, 0x07fffe00, 0x01fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14346static const MCPhysReg CSR_SVR432_VSRP_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14347static const uint32_t CSR_SVR432_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
14348static const MCPhysReg CSR_SVR464_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
14349static const uint32_t CSR_SVR464_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14350static const MCPhysReg CSR_SVR464_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14351static const uint32_t CSR_SVR464_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
14352static const MCPhysReg CSR_VSRP_SaveList[] = { PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
14353static const uint32_t CSR_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff800007, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
14354
14355
14356ArrayRef<const uint32_t *> PPCGenRegisterInfo::getRegMasks() const {
14357 static const uint32_t *const Masks[] = {
14358 CSR_64_AllRegs_RegMask,
14359 CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask,
14360 CSR_64_AllRegs_AIX_Dflt_VSX_RegMask,
14361 CSR_64_AllRegs_Altivec_RegMask,
14362 CSR_64_AllRegs_VSRP_RegMask,
14363 CSR_64_AllRegs_VSX_RegMask,
14364 CSR_AIX32_RegMask,
14365 CSR_AIX32_Altivec_RegMask,
14366 CSR_AIX32_VSRP_RegMask,
14367 CSR_AIX64_R2_VSRP_RegMask,
14368 CSR_AIX64_VSRP_RegMask,
14369 CSR_ALL_VSRP_RegMask,
14370 CSR_Altivec_RegMask,
14371 CSR_NoRegs_RegMask,
14372 CSR_PPC64_RegMask,
14373 CSR_PPC64_Altivec_RegMask,
14374 CSR_PPC64_R2_RegMask,
14375 CSR_PPC64_R2_Altivec_RegMask,
14376 CSR_SPE_RegMask,
14377 CSR_SPE_NO_S30_31_RegMask,
14378 CSR_SVR32_ColdCC_RegMask,
14379 CSR_SVR32_ColdCC_Altivec_RegMask,
14380 CSR_SVR32_ColdCC_Common_RegMask,
14381 CSR_SVR32_ColdCC_SPE_RegMask,
14382 CSR_SVR32_ColdCC_VSRP_RegMask,
14383 CSR_SVR64_ColdCC_RegMask,
14384 CSR_SVR64_ColdCC_Altivec_RegMask,
14385 CSR_SVR64_ColdCC_R2_RegMask,
14386 CSR_SVR64_ColdCC_R2_Altivec_RegMask,
14387 CSR_SVR64_ColdCC_R2_VSRP_RegMask,
14388 CSR_SVR64_ColdCC_VSRP_RegMask,
14389 CSR_SVR432_RegMask,
14390 CSR_SVR432_Altivec_RegMask,
14391 CSR_SVR432_COMM_RegMask,
14392 CSR_SVR432_SPE_RegMask,
14393 CSR_SVR432_SPE_NO_S30_31_RegMask,
14394 CSR_SVR432_VSRP_RegMask,
14395 CSR_SVR464_R2_VSRP_RegMask,
14396 CSR_SVR464_VSRP_RegMask,
14397 CSR_VSRP_RegMask,
14398 };
14399 return ArrayRef(Masks);
14400}
14401
14402bool PPCGenRegisterInfo::
14403isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14404 return
14405 false;
14406}
14407
14408bool PPCGenRegisterInfo::
14409isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
14410 return
14411 false;
14412}
14413
14414bool PPCGenRegisterInfo::
14415isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14416 return
14417 false;
14418}
14419
14420bool PPCGenRegisterInfo::
14421isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
14422 return
14423 false;
14424}
14425
14426bool PPCGenRegisterInfo::
14427isConstantPhysReg(MCRegister PhysReg) const {
14428 return
14429 PhysReg == PPC::ZERO ||
14430 PhysReg == PPC::ZERO8 ||
14431 false;
14432}
14433
14434ArrayRef<const char *> PPCGenRegisterInfo::getRegMaskNames() const {
14435 static const char *Names[] = {
14436 "CSR_64_AllRegs",
14437 "CSR_64_AllRegs_AIX_Dflt_Altivec",
14438 "CSR_64_AllRegs_AIX_Dflt_VSX",
14439 "CSR_64_AllRegs_Altivec",
14440 "CSR_64_AllRegs_VSRP",
14441 "CSR_64_AllRegs_VSX",
14442 "CSR_AIX32",
14443 "CSR_AIX32_Altivec",
14444 "CSR_AIX32_VSRP",
14445 "CSR_AIX64_R2_VSRP",
14446 "CSR_AIX64_VSRP",
14447 "CSR_ALL_VSRP",
14448 "CSR_Altivec",
14449 "CSR_NoRegs",
14450 "CSR_PPC64",
14451 "CSR_PPC64_Altivec",
14452 "CSR_PPC64_R2",
14453 "CSR_PPC64_R2_Altivec",
14454 "CSR_SPE",
14455 "CSR_SPE_NO_S30_31",
14456 "CSR_SVR32_ColdCC",
14457 "CSR_SVR32_ColdCC_Altivec",
14458 "CSR_SVR32_ColdCC_Common",
14459 "CSR_SVR32_ColdCC_SPE",
14460 "CSR_SVR32_ColdCC_VSRP",
14461 "CSR_SVR64_ColdCC",
14462 "CSR_SVR64_ColdCC_Altivec",
14463 "CSR_SVR64_ColdCC_R2",
14464 "CSR_SVR64_ColdCC_R2_Altivec",
14465 "CSR_SVR64_ColdCC_R2_VSRP",
14466 "CSR_SVR64_ColdCC_VSRP",
14467 "CSR_SVR432",
14468 "CSR_SVR432_Altivec",
14469 "CSR_SVR432_COMM",
14470 "CSR_SVR432_SPE",
14471 "CSR_SVR432_SPE_NO_S30_31",
14472 "CSR_SVR432_VSRP",
14473 "CSR_SVR464_R2_VSRP",
14474 "CSR_SVR464_VSRP",
14475 "CSR_VSRP",
14476 };
14477 return ArrayRef(Names);
14478}
14479
14480const PPCFrameLowering *
14481PPCGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
14482 return static_cast<const PPCFrameLowering *>(
14483 MF.getSubtarget().getFrameLowering());
14484}
14485
14486} // end namespace llvm
14487
14488#endif // GET_REGINFO_TARGET_DESC
14489
14490