1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | |* *| |
3 | |* Macro Fusion Predicators *| |
4 | |* *| |
5 | |* Automatically generated file, do not edit! *| |
6 | |* *| |
7 | \*===----------------------------------------------------------------------===*/ |
8 | |
9 | #ifdef GET_RISCV_MACRO_FUSION_PRED_DECL |
10 | #undef GET_RISCV_MACRO_FUSION_PRED_DECL |
11 | |
12 | namespace llvm { |
13 | bool isTuneAUIPCADDIFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
14 | bool isTuneLDADDFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
15 | bool isTuneLUIADDIFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
16 | bool isTuneShiftedZExtWFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
17 | bool isTuneZExtHFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
18 | bool isTuneZExtWFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); |
19 | } // end namespace llvm |
20 | |
21 | #endif |
22 | |
23 | #ifdef GET_RISCV_MACRO_FUSION_PRED_IMPL |
24 | #undef GET_RISCV_MACRO_FUSION_PRED_IMPL |
25 | |
26 | namespace llvm { |
27 | bool isTuneAUIPCADDIFusion( |
28 | const TargetInstrInfo &TII, |
29 | const TargetSubtargetInfo &STI, |
30 | const MachineInstr *FirstMI, |
31 | const MachineInstr &SecondMI) { |
32 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
33 | { |
34 | const MachineInstr *MI = &SecondMI; |
35 | if (( MI->getOpcode() != RISCV::ADDI )) |
36 | return false; |
37 | } |
38 | if (!FirstMI) |
39 | return true; |
40 | { |
41 | const MachineInstr *MI = FirstMI; |
42 | if (( MI->getOpcode() != RISCV::AUIPC )) |
43 | return false; |
44 | } |
45 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
46 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
47 | return false; |
48 | } |
49 | { |
50 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
51 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
52 | return false; |
53 | } |
54 | if (!(FirstMI->getOperand(0).isReg() && |
55 | SecondMI.getOperand(1).isReg() && |
56 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
57 | return false; |
58 | return true; |
59 | } |
60 | bool isTuneLDADDFusion( |
61 | const TargetInstrInfo &TII, |
62 | const TargetSubtargetInfo &STI, |
63 | const MachineInstr *FirstMI, |
64 | const MachineInstr &SecondMI) { |
65 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
66 | { |
67 | const MachineInstr *MI = &SecondMI; |
68 | if (!( |
69 | ( MI->getOpcode() == RISCV::LD ) |
70 | && MI->getOperand(2).isImm() |
71 | && MI->getOperand(2).getImm() == 0 |
72 | )) |
73 | return false; |
74 | } |
75 | if (!FirstMI) |
76 | return true; |
77 | { |
78 | const MachineInstr *MI = FirstMI; |
79 | if (( MI->getOpcode() != RISCV::ADD )) |
80 | return false; |
81 | } |
82 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
83 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
84 | return false; |
85 | } |
86 | { |
87 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
88 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
89 | return false; |
90 | } |
91 | if (!(FirstMI->getOperand(0).isReg() && |
92 | SecondMI.getOperand(1).isReg() && |
93 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
94 | return false; |
95 | return true; |
96 | } |
97 | bool isTuneLUIADDIFusion( |
98 | const TargetInstrInfo &TII, |
99 | const TargetSubtargetInfo &STI, |
100 | const MachineInstr *FirstMI, |
101 | const MachineInstr &SecondMI) { |
102 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
103 | { |
104 | const MachineInstr *MI = &SecondMI; |
105 | if (!llvm::is_contained({RISCV::ADDI, RISCV::ADDIW}, MI->getOpcode())) |
106 | return false; |
107 | } |
108 | if (!FirstMI) |
109 | return true; |
110 | { |
111 | const MachineInstr *MI = FirstMI; |
112 | if (( MI->getOpcode() != RISCV::LUI )) |
113 | return false; |
114 | } |
115 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
116 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
117 | return false; |
118 | } |
119 | { |
120 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
121 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
122 | return false; |
123 | } |
124 | if (!(FirstMI->getOperand(0).isReg() && |
125 | SecondMI.getOperand(1).isReg() && |
126 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
127 | return false; |
128 | return true; |
129 | } |
130 | bool isTuneShiftedZExtWFusion( |
131 | const TargetInstrInfo &TII, |
132 | const TargetSubtargetInfo &STI, |
133 | const MachineInstr *FirstMI, |
134 | const MachineInstr &SecondMI) { |
135 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
136 | { |
137 | const MachineInstr *MI = &SecondMI; |
138 | if (!( |
139 | ( MI->getOpcode() == RISCV::SRLI ) |
140 | && MI->getOperand(2).isImm() |
141 | && ( |
142 | MI->getOperand(2).getImm() >= 0 |
143 | && MI->getOperand(2).getImm() <= 31 |
144 | ) |
145 | )) |
146 | return false; |
147 | } |
148 | if (!FirstMI) |
149 | return true; |
150 | { |
151 | const MachineInstr *MI = FirstMI; |
152 | if (!( |
153 | ( MI->getOpcode() == RISCV::SLLI ) |
154 | && MI->getOperand(2).isImm() |
155 | && MI->getOperand(2).getImm() == 32 |
156 | )) |
157 | return false; |
158 | } |
159 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
160 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
161 | return false; |
162 | } |
163 | { |
164 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
165 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
166 | return false; |
167 | } |
168 | if (!(FirstMI->getOperand(0).isReg() && |
169 | SecondMI.getOperand(1).isReg() && |
170 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
171 | return false; |
172 | return true; |
173 | } |
174 | bool isTuneZExtHFusion( |
175 | const TargetInstrInfo &TII, |
176 | const TargetSubtargetInfo &STI, |
177 | const MachineInstr *FirstMI, |
178 | const MachineInstr &SecondMI) { |
179 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
180 | { |
181 | const MachineInstr *MI = &SecondMI; |
182 | if (!( |
183 | ( MI->getOpcode() == RISCV::SRLI ) |
184 | && MI->getOperand(2).isImm() |
185 | && MI->getOperand(2).getImm() == 48 |
186 | )) |
187 | return false; |
188 | } |
189 | if (!FirstMI) |
190 | return true; |
191 | { |
192 | const MachineInstr *MI = FirstMI; |
193 | if (!( |
194 | ( MI->getOpcode() == RISCV::SLLI ) |
195 | && MI->getOperand(2).isImm() |
196 | && MI->getOperand(2).getImm() == 48 |
197 | )) |
198 | return false; |
199 | } |
200 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
201 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
202 | return false; |
203 | } |
204 | { |
205 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
206 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
207 | return false; |
208 | } |
209 | if (!(FirstMI->getOperand(0).isReg() && |
210 | SecondMI.getOperand(1).isReg() && |
211 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
212 | return false; |
213 | return true; |
214 | } |
215 | bool isTuneZExtWFusion( |
216 | const TargetInstrInfo &TII, |
217 | const TargetSubtargetInfo &STI, |
218 | const MachineInstr *FirstMI, |
219 | const MachineInstr &SecondMI) { |
220 | [[maybe_unused]] auto &MRI = SecondMI.getMF()->getRegInfo(); |
221 | { |
222 | const MachineInstr *MI = &SecondMI; |
223 | if (!( |
224 | ( MI->getOpcode() == RISCV::SRLI ) |
225 | && MI->getOperand(2).isImm() |
226 | && MI->getOperand(2).getImm() == 32 |
227 | )) |
228 | return false; |
229 | } |
230 | if (!FirstMI) |
231 | return true; |
232 | { |
233 | const MachineInstr *MI = FirstMI; |
234 | if (!( |
235 | ( MI->getOpcode() == RISCV::SLLI ) |
236 | && MI->getOperand(2).isImm() |
237 | && MI->getOperand(2).getImm() == 32 |
238 | )) |
239 | return false; |
240 | } |
241 | if (!SecondMI.getOperand(0).getReg().isVirtual()) { |
242 | if (SecondMI.getOperand(0).getReg() != SecondMI.getOperand(1).getReg()) |
243 | return false; |
244 | } |
245 | { |
246 | Register FirstDest = FirstMI->getOperand(0).getReg(); |
247 | if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest)) |
248 | return false; |
249 | } |
250 | if (!(FirstMI->getOperand(0).isReg() && |
251 | SecondMI.getOperand(1).isReg() && |
252 | FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg())) |
253 | return false; |
254 | return true; |
255 | } |
256 | } // end namespace llvm |
257 | |
258 | #endif |
259 | |