1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace RISCV {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 FPRBRegBankID = 0,
16 GPRBRegBankID = 1,
17 VRBRegBankID = 2,
18 NumRegisterBanks,
19};
20} // end namespace RISCV
21} // end namespace llvm
22#endif // GET_REGBANK_DECLARATIONS
23
24#ifdef GET_TARGET_REGBANK_CLASS
25#undef GET_TARGET_REGBANK_CLASS
26private:
27 static const RegisterBank *RegBanks[];
28 static const unsigned Sizes[];
29
30public:
31 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
32protected:
33 RISCVGenRegisterBankInfo(unsigned HwMode = 0);
34
35#endif // GET_TARGET_REGBANK_CLASS
36
37#ifdef GET_TARGET_REGBANK_IMPL
38#undef GET_TARGET_REGBANK_IMPL
39namespace llvm {
40namespace RISCV {
41const uint32_t FPRBRegBankCoverageData[] = {
42 // 0-31
43 (1u << (RISCV::FPR16RegClassID - 0)) |
44 (1u << (RISCV::FPR32RegClassID - 0)) |
45 (1u << (RISCV::FPR16CRegClassID - 0)) |
46 (1u << (RISCV::FPR32CRegClassID - 0)) |
47 0,
48 // 32-63
49 (1u << (RISCV::FPR64RegClassID - 32)) |
50 0,
51 // 64-95
52 (1u << (RISCV::FPR64CRegClassID - 64)) |
53 0,
54 // 96-127
55 0,
56};
57const uint32_t GPRBRegBankCoverageData[] = {
58 // 0-31
59 (1u << (RISCV::GPRRegClassID - 0)) |
60 (1u << (RISCV::GPRF16RegClassID - 0)) |
61 (1u << (RISCV::GPRF32RegClassID - 0)) |
62 (1u << (RISCV::GPRNoX0RegClassID - 0)) |
63 (1u << (RISCV::GPRF16NoX0RegClassID - 0)) |
64 (1u << (RISCV::GPRF32NoX0RegClassID - 0)) |
65 (1u << (RISCV::GPRNoX0X2RegClassID - 0)) |
66 (1u << (RISCV::GPRNoX0X2_and_GPRNoX31RegClassID - 0)) |
67 (1u << (RISCV::GPRJALR_and_GPRNoX31RegClassID - 0)) |
68 (1u << (RISCV::GPRJALRNonX7_and_GPRNoX31RegClassID - 0)) |
69 (1u << (RISCV::GPRNoX31_and_GPRTCNonX7RegClassID - 0)) |
70 (1u << (RISCV::GPRC_and_GPRTCRegClassID - 0)) |
71 (1u << (RISCV::GPRF16CRegClassID - 0)) |
72 (1u << (RISCV::GPRF32CRegClassID - 0)) |
73 (1u << (RISCV::GPRCRegClassID - 0)) |
74 (1u << (RISCV::SR07RegClassID - 0)) |
75 (1u << (RISCV::GPRNoX31_and_GPRTCRegClassID - 0)) |
76 (1u << (RISCV::GPRJALRRegClassID - 0)) |
77 (1u << (RISCV::GPRJALRNonX7RegClassID - 0)) |
78 (1u << (RISCV::GPRTCNonX7RegClassID - 0)) |
79 (1u << (RISCV::GPRTCRegClassID - 0)) |
80 (1u << (RISCV::GPRNoX0_and_GPRNoX31RegClassID - 0)) |
81 (1u << (RISCV::GPRNoX31RegClassID - 0)) |
82 0,
83 // 32-63
84 (1u << (RISCV::GPRC_and_SR07RegClassID - 32)) |
85 (1u << (RISCV::GPRX7RegClassID - 32)) |
86 (1u << (RISCV::GPRX1X5RegClassID - 32)) |
87 (1u << (RISCV::GPRX1RegClassID - 32)) |
88 (1u << (RISCV::GPRX5RegClassID - 32)) |
89 (1u << (RISCV::SPRegClassID - 32)) |
90 (1u << (RISCV::GPRX0RegClassID - 32)) |
91 0,
92 // 64-95
93 0,
94 // 96-127
95 0,
96};
97const uint32_t VRBRegBankCoverageData[] = {
98 // 0-31
99 0,
100 // 32-63
101 (1u << (RISCV::VMRegClassID - 32)) |
102 (1u << (RISCV::VRRegClassID - 32)) |
103 0,
104 // 64-95
105 (1u << (RISCV::VRNoV0RegClassID - 64)) |
106 (1u << (RISCV::VRM2RegClassID - 64)) |
107 (1u << (RISCV::VRM2NoV0RegClassID - 64)) |
108 (1u << (RISCV::VRM4RegClassID - 64)) |
109 (1u << (RISCV::VRM4NoV0RegClassID - 64)) |
110 (1u << (RISCV::VMV0RegClassID - 64)) |
111 (1u << (RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID - 64)) |
112 (1u << (RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 64)) |
113 0,
114 // 96-127
115 (1u << (RISCV::VRM8RegClassID - 96)) |
116 (1u << (RISCV::VRM8NoV0RegClassID - 96)) |
117 (1u << (RISCV::VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 96)) |
118 0,
119};
120
121constexpr RegisterBank FPRBRegBank(/* ID */ RISCV::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 111);
122constexpr RegisterBank GPRBRegBank(/* ID */ RISCV::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 111);
123constexpr RegisterBank VRBRegBank(/* ID */ RISCV::VRBRegBankID, /* Name */ "VRB", /* CoveredRegClasses */ VRBRegBankCoverageData, /* NumRegClasses */ 111);
124} // end namespace RISCV
125
126const RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = {
127 &RISCV::FPRBRegBank,
128 &RISCV::GPRBRegBank,
129 &RISCV::VRBRegBank,
130};
131
132const unsigned RISCVGenRegisterBankInfo::Sizes[] = {
133 // Mode = 0 (Default)
134 64,
135 32,
136 512,
137 // Mode = 1 (RV64)
138 64,
139 64,
140 512,
141};
142
143RISCVGenRegisterBankInfo::RISCVGenRegisterBankInfo(unsigned HwMode)
144 : RegisterBankInfo(RegBanks, RISCV::NumRegisterBanks, Sizes, HwMode) {
145 // Assert that RegBank indices match their ID's
146#ifndef NDEBUG
147 for (auto RB : enumerate(RegBanks))
148 assert(RB.index() == RB.value()->getID() && "Index != ID");
149#endif // NDEBUG
150}
151const RegisterBank &
152RISCVGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
153 constexpr uint32_t InvalidRegBankID = uint32_t(RISCV::InvalidRegBankID) & 3;
154 static const uint32_t RegClass2RegBank[7] = {
155 (uint32_t(RISCV::FPRBRegBankID) << 0) | // FPR16RegClassID
156 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRF16RegClassID
157 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRF16NoX0RegClassID
158 (uint32_t(RISCV::FPRBRegBankID) << 6) | // FPR16CRegClassID
159 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRF16CRegClassID
160 (uint32_t(InvalidRegBankID) << 10) |
161 (uint32_t(RISCV::FPRBRegBankID) << 12) | // FPR32RegClassID
162 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRRegClassID
163 (uint32_t(RISCV::GPRBRegBankID) << 16) | // GPRF32RegClassID
164 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRF32NoX0RegClassID
165 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRNoX0RegClassID
166 (uint32_t(RISCV::GPRBRegBankID) << 22) | // GPRNoX31RegClassID
167 (uint32_t(RISCV::GPRBRegBankID) << 24) | // GPRNoX0X2RegClassID
168 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRNoX0_and_GPRNoX31RegClassID
169 (uint32_t(RISCV::GPRBRegBankID) << 28) | // GPRNoX0X2_and_GPRNoX31RegClassID
170 (uint32_t(RISCV::GPRBRegBankID) << 30), // GPRJALRRegClassID
171 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRJALRNonX7RegClassID
172 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRJALR_and_GPRNoX31RegClassID
173 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRJALRNonX7_and_GPRNoX31RegClassID
174 (uint32_t(InvalidRegBankID) << 6) |
175 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRTCRegClassID
176 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRNoX31_and_GPRTCRegClassID
177 (uint32_t(RISCV::GPRBRegBankID) << 12) | // GPRTCNonX7RegClassID
178 (uint32_t(RISCV::GPRBRegBankID) << 14) | // GPRNoX31_and_GPRTCNonX7RegClassID
179 (uint32_t(RISCV::FPRBRegBankID) << 16) | // FPR32CRegClassID
180 (uint32_t(RISCV::GPRBRegBankID) << 18) | // GPRCRegClassID
181 (uint32_t(RISCV::GPRBRegBankID) << 20) | // GPRF32CRegClassID
182 (uint32_t(RISCV::GPRBRegBankID) << 22) | // SR07RegClassID
183 (uint32_t(InvalidRegBankID) << 24) |
184 (uint32_t(RISCV::GPRBRegBankID) << 26) | // GPRC_and_GPRTCRegClassID
185 (uint32_t(InvalidRegBankID) << 28) |
186 (uint32_t(InvalidRegBankID) << 30),
187 (uint32_t(RISCV::GPRBRegBankID) << 0) | // GPRC_and_SR07RegClassID
188 (uint32_t(RISCV::GPRBRegBankID) << 2) | // GPRX1X5RegClassID
189 (uint32_t(RISCV::GPRBRegBankID) << 4) | // GPRX0RegClassID
190 (uint32_t(RISCV::GPRBRegBankID) << 6) | // GPRX1RegClassID
191 (uint32_t(RISCV::GPRBRegBankID) << 8) | // GPRX5RegClassID
192 (uint32_t(RISCV::GPRBRegBankID) << 10) | // GPRX7RegClassID
193 (uint32_t(RISCV::GPRBRegBankID) << 12) | // SPRegClassID
194 (uint32_t(InvalidRegBankID) << 14) |
195 (uint32_t(InvalidRegBankID) << 16) |
196 (uint32_t(InvalidRegBankID) << 18) |
197 (uint32_t(InvalidRegBankID) << 20) |
198 (uint32_t(InvalidRegBankID) << 22) |
199 (uint32_t(InvalidRegBankID) << 24) |
200 (uint32_t(InvalidRegBankID) << 26) |
201 (uint32_t(InvalidRegBankID) << 28) |
202 (uint32_t(InvalidRegBankID) << 30),
203 (uint32_t(InvalidRegBankID) << 0) |
204 (uint32_t(InvalidRegBankID) << 2) |
205 (uint32_t(InvalidRegBankID) << 4) |
206 (uint32_t(InvalidRegBankID) << 6) |
207 (uint32_t(InvalidRegBankID) << 8) |
208 (uint32_t(InvalidRegBankID) << 10) |
209 (uint32_t(InvalidRegBankID) << 12) |
210 (uint32_t(InvalidRegBankID) << 14) |
211 (uint32_t(InvalidRegBankID) << 16) |
212 (uint32_t(InvalidRegBankID) << 18) |
213 (uint32_t(InvalidRegBankID) << 20) |
214 (uint32_t(InvalidRegBankID) << 22) |
215 (uint32_t(InvalidRegBankID) << 24) |
216 (uint32_t(RISCV::FPRBRegBankID) << 26) | // FPR64RegClassID
217 (uint32_t(RISCV::VRBRegBankID) << 28) | // VMRegClassID
218 (uint32_t(RISCV::VRBRegBankID) << 30), // VRRegClassID
219 (uint32_t(RISCV::VRBRegBankID) << 0) | // VRNoV0RegClassID
220 (uint32_t(RISCV::FPRBRegBankID) << 2) | // FPR64CRegClassID
221 (uint32_t(RISCV::VRBRegBankID) << 4) | // VMV0RegClassID
222 (uint32_t(InvalidRegBankID) << 6) |
223 (uint32_t(InvalidRegBankID) << 8) |
224 (uint32_t(RISCV::VRBRegBankID) << 10) | // VRM2RegClassID
225 (uint32_t(RISCV::VRBRegBankID) << 12) | // VRM2NoV0RegClassID
226 (uint32_t(RISCV::VRBRegBankID) << 14) | // VRM2_with_sub_vrm1_0_in_VMV0RegClassID
227 (uint32_t(InvalidRegBankID) << 16) |
228 (uint32_t(InvalidRegBankID) << 18) |
229 (uint32_t(InvalidRegBankID) << 20) |
230 (uint32_t(InvalidRegBankID) << 22) |
231 (uint32_t(InvalidRegBankID) << 24) |
232 (uint32_t(InvalidRegBankID) << 26) |
233 (uint32_t(InvalidRegBankID) << 28) |
234 (uint32_t(InvalidRegBankID) << 30),
235 (uint32_t(InvalidRegBankID) << 0) |
236 (uint32_t(InvalidRegBankID) << 2) |
237 (uint32_t(RISCV::VRBRegBankID) << 4) | // VRM4RegClassID
238 (uint32_t(RISCV::VRBRegBankID) << 6) | // VRM4NoV0RegClassID
239 (uint32_t(RISCV::VRBRegBankID) << 8) | // VRM4_with_sub_vrm1_0_in_VMV0RegClassID
240 (uint32_t(InvalidRegBankID) << 10) |
241 (uint32_t(InvalidRegBankID) << 12) |
242 (uint32_t(InvalidRegBankID) << 14) |
243 (uint32_t(InvalidRegBankID) << 16) |
244 (uint32_t(InvalidRegBankID) << 18) |
245 (uint32_t(InvalidRegBankID) << 20) |
246 (uint32_t(InvalidRegBankID) << 22) |
247 (uint32_t(InvalidRegBankID) << 24) |
248 (uint32_t(InvalidRegBankID) << 26) |
249 (uint32_t(InvalidRegBankID) << 28) |
250 (uint32_t(InvalidRegBankID) << 30),
251 (uint32_t(InvalidRegBankID) << 0) |
252 (uint32_t(InvalidRegBankID) << 2) |
253 (uint32_t(InvalidRegBankID) << 4) |
254 (uint32_t(InvalidRegBankID) << 6) |
255 (uint32_t(InvalidRegBankID) << 8) |
256 (uint32_t(InvalidRegBankID) << 10) |
257 (uint32_t(InvalidRegBankID) << 12) |
258 (uint32_t(InvalidRegBankID) << 14) |
259 (uint32_t(InvalidRegBankID) << 16) |
260 (uint32_t(RISCV::VRBRegBankID) << 18) | // VRM8RegClassID
261 (uint32_t(RISCV::VRBRegBankID) << 20) | // VRM8NoV0RegClassID
262 (uint32_t(RISCV::VRBRegBankID) << 22) // VRM8_with_sub_vrm4_0_in_VRM4_with_sub_vrm1_0_in_VMV0RegClassID
263 };
264 const unsigned RegClassID = RC.getID();
265 if (LLVM_LIKELY(RegClassID < 108)) {
266 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
267 if (RegBankID != InvalidRegBankID)
268 return getRegBank(RegBankID);
269 }
270 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
271}
272} // end namespace llvm
273#endif // GET_TARGET_REGBANK_IMPL
274