1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: Sparc.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36 ParseStatus MatchOperandParserImpl(
37 OperandVector &Operands,
38 StringRef Mnemonic,
39 bool ParseForAllFeatures = false);
40 ParseStatus tryCustomParseOperand(
41 OperandVector &Operands,
42 unsigned MCK);
43
44#endif // GET_ASSEMBLER_HEADER
45
46
47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48#undef GET_OPERAND_DIAGNOSTIC_TYPES
49
50#endif // GET_OPERAND_DIAGNOSTIC_TYPES
51
52
53#ifdef GET_REGISTER_MATCHER
54#undef GET_REGISTER_MATCHER
55
56// Bits for subtarget features that participate in instruction matching.
57enum SubtargetFeatureBits : uint8_t {
58 Feature_Is64BitBit = 9,
59 Feature_UseSoftMulDivBit = 10,
60 Feature_HasV9Bit = 5,
61 Feature_HasVISBit = 6,
62 Feature_HasVIS2Bit = 7,
63 Feature_HasVIS3Bit = 8,
64 Feature_HasUA2005Bit = 3,
65 Feature_HasUA2007Bit = 4,
66 Feature_HasOSA2011Bit = 1,
67 Feature_HasCASABit = 0,
68 Feature_HasPWRPSRBit = 2,
69};
70
71static MCRegister MatchRegisterName(StringRef Name) {
72 switch (Name.size()) {
73 default: break;
74 case 1: // 1 string to match.
75 if (Name[0] != 'y')
76 break;
77 return SP::Y; // "y"
78 case 2: // 86 strings to match.
79 switch (Name[0]) {
80 default: break;
81 case 'c': // 16 strings to match.
82 switch (Name[1]) {
83 default: break;
84 case '0': // 2 strings to match.
85 return SP::C0; // "c0"
86 case '1': // 1 string to match.
87 return SP::C1; // "c1"
88 case '2': // 2 strings to match.
89 return SP::C2; // "c2"
90 case '3': // 1 string to match.
91 return SP::C3; // "c3"
92 case '4': // 2 strings to match.
93 return SP::C4; // "c4"
94 case '5': // 1 string to match.
95 return SP::C5; // "c5"
96 case '6': // 2 strings to match.
97 return SP::C6; // "c6"
98 case '7': // 1 string to match.
99 return SP::C7; // "c7"
100 case '8': // 2 strings to match.
101 return SP::C8; // "c8"
102 case '9': // 1 string to match.
103 return SP::C9; // "c9"
104 case 'q': // 1 string to match.
105 return SP::CPQ; // "cq"
106 }
107 break;
108 case 'f': // 20 strings to match.
109 switch (Name[1]) {
110 default: break;
111 case '0': // 3 strings to match.
112 return SP::D0; // "f0"
113 case '1': // 1 string to match.
114 return SP::F1; // "f1"
115 case '2': // 2 strings to match.
116 return SP::D1; // "f2"
117 case '3': // 1 string to match.
118 return SP::F3; // "f3"
119 case '4': // 3 strings to match.
120 return SP::D2; // "f4"
121 case '5': // 1 string to match.
122 return SP::F5; // "f5"
123 case '6': // 2 strings to match.
124 return SP::D3; // "f6"
125 case '7': // 1 string to match.
126 return SP::F7; // "f7"
127 case '8': // 3 strings to match.
128 return SP::D4; // "f8"
129 case '9': // 1 string to match.
130 return SP::F9; // "f9"
131 case 'p': // 1 string to match.
132 return SP::I6; // "fp"
133 case 'q': // 1 string to match.
134 return SP::FQ; // "fq"
135 }
136 break;
137 case 'g': // 13 strings to match.
138 switch (Name[1]) {
139 default: break;
140 case '0': // 2 strings to match.
141 return SP::G0; // "g0"
142 case '1': // 1 string to match.
143 return SP::G1; // "g1"
144 case '2': // 2 strings to match.
145 return SP::G2; // "g2"
146 case '3': // 1 string to match.
147 return SP::G3; // "g3"
148 case '4': // 2 strings to match.
149 return SP::G4; // "g4"
150 case '5': // 1 string to match.
151 return SP::G5; // "g5"
152 case '6': // 2 strings to match.
153 return SP::G6; // "g6"
154 case '7': // 1 string to match.
155 return SP::G7; // "g7"
156 case 'l': // 1 string to match.
157 return SP::GL; // "gl"
158 }
159 break;
160 case 'i': // 11 strings to match.
161 switch (Name[1]) {
162 default: break;
163 case '0': // 2 strings to match.
164 return SP::I0; // "i0"
165 case '1': // 1 string to match.
166 return SP::I1; // "i1"
167 case '2': // 2 strings to match.
168 return SP::I2; // "i2"
169 case '3': // 1 string to match.
170 return SP::I3; // "i3"
171 case '4': // 2 strings to match.
172 return SP::I4; // "i4"
173 case '5': // 1 string to match.
174 return SP::I5; // "i5"
175 case '6': // 1 string to match.
176 return SP::I6_I7; // "i6"
177 case '7': // 1 string to match.
178 return SP::I7; // "i7"
179 }
180 break;
181 case 'l': // 12 strings to match.
182 switch (Name[1]) {
183 default: break;
184 case '0': // 2 strings to match.
185 return SP::L0; // "l0"
186 case '1': // 1 string to match.
187 return SP::L1; // "l1"
188 case '2': // 2 strings to match.
189 return SP::L2; // "l2"
190 case '3': // 1 string to match.
191 return SP::L3; // "l3"
192 case '4': // 2 strings to match.
193 return SP::L4; // "l4"
194 case '5': // 1 string to match.
195 return SP::L5; // "l5"
196 case '6': // 2 strings to match.
197 return SP::L6; // "l6"
198 case '7': // 1 string to match.
199 return SP::L7; // "l7"
200 }
201 break;
202 case 'o': // 11 strings to match.
203 switch (Name[1]) {
204 default: break;
205 case '0': // 2 strings to match.
206 return SP::O0; // "o0"
207 case '1': // 1 string to match.
208 return SP::O1; // "o1"
209 case '2': // 2 strings to match.
210 return SP::O2; // "o2"
211 case '3': // 1 string to match.
212 return SP::O3; // "o3"
213 case '4': // 2 strings to match.
214 return SP::O4; // "o4"
215 case '5': // 1 string to match.
216 return SP::O5; // "o5"
217 case '6': // 1 string to match.
218 return SP::O6_O7; // "o6"
219 case '7': // 1 string to match.
220 return SP::O7; // "o7"
221 }
222 break;
223 case 's': // 1 string to match.
224 if (Name[1] != 'p')
225 break;
226 return SP::O6; // "sp"
227 case 't': // 2 strings to match.
228 switch (Name[1]) {
229 default: break;
230 case 'l': // 1 string to match.
231 return SP::TL; // "tl"
232 case 't': // 1 string to match.
233 return SP::TT; // "tt"
234 }
235 break;
236 }
237 break;
238 case 3: // 106 strings to match.
239 switch (Name[0]) {
240 default: break;
241 case 'c': // 35 strings to match.
242 switch (Name[1]) {
243 default: break;
244 case '1': // 15 strings to match.
245 switch (Name[2]) {
246 default: break;
247 case '0': // 2 strings to match.
248 return SP::C10; // "c10"
249 case '1': // 1 string to match.
250 return SP::C11; // "c11"
251 case '2': // 2 strings to match.
252 return SP::C12; // "c12"
253 case '3': // 1 string to match.
254 return SP::C13; // "c13"
255 case '4': // 2 strings to match.
256 return SP::C14; // "c14"
257 case '5': // 1 string to match.
258 return SP::C15; // "c15"
259 case '6': // 2 strings to match.
260 return SP::C16; // "c16"
261 case '7': // 1 string to match.
262 return SP::C17; // "c17"
263 case '8': // 2 strings to match.
264 return SP::C18; // "c18"
265 case '9': // 1 string to match.
266 return SP::C19; // "c19"
267 }
268 break;
269 case '2': // 15 strings to match.
270 switch (Name[2]) {
271 default: break;
272 case '0': // 2 strings to match.
273 return SP::C20; // "c20"
274 case '1': // 1 string to match.
275 return SP::C21; // "c21"
276 case '2': // 2 strings to match.
277 return SP::C22; // "c22"
278 case '3': // 1 string to match.
279 return SP::C23; // "c23"
280 case '4': // 2 strings to match.
281 return SP::C24; // "c24"
282 case '5': // 1 string to match.
283 return SP::C25; // "c25"
284 case '6': // 2 strings to match.
285 return SP::C26; // "c26"
286 case '7': // 1 string to match.
287 return SP::C27; // "c27"
288 case '8': // 2 strings to match.
289 return SP::C28; // "c28"
290 case '9': // 1 string to match.
291 return SP::C29; // "c29"
292 }
293 break;
294 case '3': // 3 strings to match.
295 switch (Name[2]) {
296 default: break;
297 case '0': // 2 strings to match.
298 return SP::C30; // "c30"
299 case '1': // 1 string to match.
300 return SP::C31; // "c31"
301 }
302 break;
303 case 's': // 1 string to match.
304 if (Name[2] != 'r')
305 break;
306 return SP::CPSR; // "csr"
307 case 'w': // 1 string to match.
308 if (Name[2] != 'p')
309 break;
310 return SP::CWP; // "cwp"
311 }
312 break;
313 case 'f': // 63 strings to match.
314 switch (Name[1]) {
315 default: break;
316 case '1': // 17 strings to match.
317 switch (Name[2]) {
318 default: break;
319 case '0': // 2 strings to match.
320 return SP::D5; // "f10"
321 case '1': // 1 string to match.
322 return SP::F11; // "f11"
323 case '2': // 3 strings to match.
324 return SP::D6; // "f12"
325 case '3': // 1 string to match.
326 return SP::F13; // "f13"
327 case '4': // 2 strings to match.
328 return SP::D7; // "f14"
329 case '5': // 1 string to match.
330 return SP::F15; // "f15"
331 case '6': // 3 strings to match.
332 return SP::D8; // "f16"
333 case '7': // 1 string to match.
334 return SP::F17; // "f17"
335 case '8': // 2 strings to match.
336 return SP::D9; // "f18"
337 case '9': // 1 string to match.
338 return SP::F19; // "f19"
339 }
340 break;
341 case '2': // 18 strings to match.
342 switch (Name[2]) {
343 default: break;
344 case '0': // 3 strings to match.
345 return SP::D10; // "f20"
346 case '1': // 1 string to match.
347 return SP::F21; // "f21"
348 case '2': // 2 strings to match.
349 return SP::D11; // "f22"
350 case '3': // 1 string to match.
351 return SP::F23; // "f23"
352 case '4': // 3 strings to match.
353 return SP::D12; // "f24"
354 case '5': // 1 string to match.
355 return SP::F25; // "f25"
356 case '6': // 2 strings to match.
357 return SP::D13; // "f26"
358 case '7': // 1 string to match.
359 return SP::F27; // "f27"
360 case '8': // 3 strings to match.
361 return SP::D14; // "f28"
362 case '9': // 1 string to match.
363 return SP::F29; // "f29"
364 }
365 break;
366 case '3': // 9 strings to match.
367 switch (Name[2]) {
368 default: break;
369 case '0': // 2 strings to match.
370 return SP::D15; // "f30"
371 case '1': // 1 string to match.
372 return SP::F31; // "f31"
373 case '2': // 2 strings to match.
374 return SP::D16; // "f32"
375 case '4': // 1 string to match.
376 return SP::D17; // "f34"
377 case '6': // 2 strings to match.
378 return SP::D18; // "f36"
379 case '8': // 1 string to match.
380 return SP::D19; // "f38"
381 }
382 break;
383 case '4': // 8 strings to match.
384 switch (Name[2]) {
385 default: break;
386 case '0': // 2 strings to match.
387 return SP::D20; // "f40"
388 case '2': // 1 string to match.
389 return SP::D21; // "f42"
390 case '4': // 2 strings to match.
391 return SP::D22; // "f44"
392 case '6': // 1 string to match.
393 return SP::D23; // "f46"
394 case '8': // 2 strings to match.
395 return SP::D24; // "f48"
396 }
397 break;
398 case '5': // 7 strings to match.
399 switch (Name[2]) {
400 default: break;
401 case '0': // 1 string to match.
402 return SP::D25; // "f50"
403 case '2': // 2 strings to match.
404 return SP::D26; // "f52"
405 case '4': // 1 string to match.
406 return SP::D27; // "f54"
407 case '6': // 2 strings to match.
408 return SP::D28; // "f56"
409 case '8': // 1 string to match.
410 return SP::D29; // "f58"
411 }
412 break;
413 case '6': // 3 strings to match.
414 switch (Name[2]) {
415 default: break;
416 case '0': // 2 strings to match.
417 return SP::D30; // "f60"
418 case '2': // 1 string to match.
419 return SP::D31; // "f62"
420 }
421 break;
422 case 's': // 1 string to match.
423 if (Name[2] != 'r')
424 break;
425 return SP::FSR; // "fsr"
426 }
427 break;
428 case 'i': // 1 string to match.
429 if (memcmp(Name.data()+1, "cc", 2) != 0)
430 break;
431 return SP::ICC; // "icc"
432 case 'p': // 2 strings to match.
433 switch (Name[1]) {
434 default: break;
435 case 'i': // 1 string to match.
436 if (Name[2] != 'l')
437 break;
438 return SP::PIL; // "pil"
439 case 's': // 1 string to match.
440 if (Name[2] != 'r')
441 break;
442 return SP::PSR; // "psr"
443 }
444 break;
445 case 't': // 3 strings to match.
446 switch (Name[1]) {
447 default: break;
448 case 'b': // 2 strings to match.
449 switch (Name[2]) {
450 default: break;
451 case 'a': // 1 string to match.
452 return SP::TBA; // "tba"
453 case 'r': // 1 string to match.
454 return SP::TBR; // "tbr"
455 }
456 break;
457 case 'p': // 1 string to match.
458 if (Name[2] != 'c')
459 break;
460 return SP::TPC; // "tpc"
461 }
462 break;
463 case 'v': // 1 string to match.
464 if (memcmp(Name.data()+1, "er", 2) != 0)
465 break;
466 return SP::VER; // "ver"
467 case 'w': // 1 string to match.
468 if (memcmp(Name.data()+1, "im", 2) != 0)
469 break;
470 return SP::WIM; // "wim"
471 }
472 break;
473 case 4: // 15 strings to match.
474 switch (Name[0]) {
475 default: break;
476 case 'a': // 9 strings to match.
477 if (memcmp(Name.data()+1, "sr", 2) != 0)
478 break;
479 switch (Name[3]) {
480 default: break;
481 case '1': // 1 string to match.
482 return SP::ASR1; // "asr1"
483 case '2': // 1 string to match.
484 return SP::ASR2; // "asr2"
485 case '3': // 1 string to match.
486 return SP::ASR3; // "asr3"
487 case '4': // 1 string to match.
488 return SP::ASR4; // "asr4"
489 case '5': // 1 string to match.
490 return SP::ASR5; // "asr5"
491 case '6': // 1 string to match.
492 return SP::ASR6; // "asr6"
493 case '7': // 1 string to match.
494 return SP::ASR7; // "asr7"
495 case '8': // 1 string to match.
496 return SP::ASR8; // "asr8"
497 case '9': // 1 string to match.
498 return SP::ASR9; // "asr9"
499 }
500 break;
501 case 'f': // 4 strings to match.
502 if (memcmp(Name.data()+1, "cc", 2) != 0)
503 break;
504 switch (Name[3]) {
505 default: break;
506 case '0': // 1 string to match.
507 return SP::FCC0; // "fcc0"
508 case '1': // 1 string to match.
509 return SP::FCC1; // "fcc1"
510 case '2': // 1 string to match.
511 return SP::FCC2; // "fcc2"
512 case '3': // 1 string to match.
513 return SP::FCC3; // "fcc3"
514 }
515 break;
516 case 't': // 2 strings to match.
517 switch (Name[1]) {
518 default: break;
519 case 'i': // 1 string to match.
520 if (memcmp(Name.data()+2, "ck", 2) != 0)
521 break;
522 return SP::TICK; // "tick"
523 case 'n': // 1 string to match.
524 if (memcmp(Name.data()+2, "pc", 2) != 0)
525 break;
526 return SP::TNPC; // "tnpc"
527 }
528 break;
529 }
530 break;
531 case 5: // 22 strings to match.
532 if (memcmp(Name.data()+0, "asr", 3) != 0)
533 break;
534 switch (Name[3]) {
535 default: break;
536 case '1': // 10 strings to match.
537 switch (Name[4]) {
538 default: break;
539 case '0': // 1 string to match.
540 return SP::ASR10; // "asr10"
541 case '1': // 1 string to match.
542 return SP::ASR11; // "asr11"
543 case '2': // 1 string to match.
544 return SP::ASR12; // "asr12"
545 case '3': // 1 string to match.
546 return SP::ASR13; // "asr13"
547 case '4': // 1 string to match.
548 return SP::ASR14; // "asr14"
549 case '5': // 1 string to match.
550 return SP::ASR15; // "asr15"
551 case '6': // 1 string to match.
552 return SP::ASR16; // "asr16"
553 case '7': // 1 string to match.
554 return SP::ASR17; // "asr17"
555 case '8': // 1 string to match.
556 return SP::ASR18; // "asr18"
557 case '9': // 1 string to match.
558 return SP::ASR19; // "asr19"
559 }
560 break;
561 case '2': // 10 strings to match.
562 switch (Name[4]) {
563 default: break;
564 case '0': // 1 string to match.
565 return SP::ASR20; // "asr20"
566 case '1': // 1 string to match.
567 return SP::ASR21; // "asr21"
568 case '2': // 1 string to match.
569 return SP::ASR22; // "asr22"
570 case '3': // 1 string to match.
571 return SP::ASR23; // "asr23"
572 case '4': // 1 string to match.
573 return SP::ASR24; // "asr24"
574 case '5': // 1 string to match.
575 return SP::ASR25; // "asr25"
576 case '6': // 1 string to match.
577 return SP::ASR26; // "asr26"
578 case '7': // 1 string to match.
579 return SP::ASR27; // "asr27"
580 case '8': // 1 string to match.
581 return SP::ASR28; // "asr28"
582 case '9': // 1 string to match.
583 return SP::ASR29; // "asr29"
584 }
585 break;
586 case '3': // 2 strings to match.
587 switch (Name[4]) {
588 default: break;
589 case '0': // 1 string to match.
590 return SP::ASR30; // "asr30"
591 case '1': // 1 string to match.
592 return SP::ASR31; // "asr31"
593 }
594 break;
595 }
596 break;
597 case 6: // 3 strings to match.
598 switch (Name[0]) {
599 default: break;
600 case 'p': // 1 string to match.
601 if (memcmp(Name.data()+1, "state", 5) != 0)
602 break;
603 return SP::PSTATE; // "pstate"
604 case 't': // 1 string to match.
605 if (memcmp(Name.data()+1, "state", 5) != 0)
606 break;
607 return SP::TSTATE; // "tstate"
608 case 'w': // 1 string to match.
609 if (memcmp(Name.data()+1, "state", 5) != 0)
610 break;
611 return SP::WSTATE; // "wstate"
612 }
613 break;
614 case 7: // 1 string to match.
615 if (memcmp(Name.data()+0, "cansave", 7) != 0)
616 break;
617 return SP::CANSAVE; // "cansave"
618 case 8: // 2 strings to match.
619 switch (Name[0]) {
620 default: break;
621 case 'c': // 1 string to match.
622 if (memcmp(Name.data()+1, "leanwin", 7) != 0)
623 break;
624 return SP::CLEANWIN; // "cleanwin"
625 case 'o': // 1 string to match.
626 if (memcmp(Name.data()+1, "therwin", 7) != 0)
627 break;
628 return SP::OTHERWIN; // "otherwin"
629 }
630 break;
631 case 10: // 1 string to match.
632 if (memcmp(Name.data()+0, "canrestore", 10) != 0)
633 break;
634 return SP::CANRESTORE; // "canrestore"
635 }
636 return SP::NoRegister;
637}
638
639static MCRegister MatchRegisterAltName(StringRef Name) {
640 switch (Name.size()) {
641 default: break;
642 case 2: // 1 string to match.
643 if (memcmp(Name.data()+0, "pc", 2) != 0)
644 break;
645 return SP::ASR5; // "pc"
646 case 3: // 2 strings to match.
647 switch (Name[0]) {
648 default: break;
649 case 'a': // 1 string to match.
650 if (memcmp(Name.data()+1, "si", 2) != 0)
651 break;
652 return SP::ASR3; // "asi"
653 case 'c': // 1 string to match.
654 if (memcmp(Name.data()+1, "cr", 2) != 0)
655 break;
656 return SP::ASR2; // "ccr"
657 }
658 break;
659 case 4: // 2 strings to match.
660 switch (Name[0]) {
661 default: break;
662 case 'f': // 1 string to match.
663 if (memcmp(Name.data()+1, "prs", 3) != 0)
664 break;
665 return SP::ASR6; // "fprs"
666 case 't': // 1 string to match.
667 if (memcmp(Name.data()+1, "ick", 3) != 0)
668 break;
669 return SP::ASR4; // "tick"
670 }
671 break;
672 }
673 return SP::NoRegister;
674}
675
676#endif // GET_REGISTER_MATCHER
677
678
679#ifdef GET_SUBTARGET_FEATURE_NAME
680#undef GET_SUBTARGET_FEATURE_NAME
681
682// User-level names for subtarget features that participate in
683// instruction matching.
684static const char *getSubtargetFeatureName(uint64_t Val) {
685 switch(Val) {
686 case Feature_Is64BitBit: return "";
687 case Feature_UseSoftMulDivBit: return "";
688 case Feature_HasV9Bit: return "";
689 case Feature_HasVISBit: return "";
690 case Feature_HasVIS2Bit: return "";
691 case Feature_HasVIS3Bit: return "";
692 case Feature_HasUA2005Bit: return "";
693 case Feature_HasUA2007Bit: return "";
694 case Feature_HasOSA2011Bit: return "";
695 case Feature_HasCASABit: return "";
696 case Feature_HasPWRPSRBit: return "";
697 default: return "(unknown)";
698 }
699}
700
701#endif // GET_SUBTARGET_FEATURE_NAME
702
703
704#ifdef GET_MATCHER_IMPLEMENTATION
705#undef GET_MATCHER_IMPLEMENTATION
706
707static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
708 switch (Mnemonic.size()) {
709 default: break;
710 case 3: // 1 string to match.
711 if (memcmp(Mnemonic.data()+0, "stw", 3) != 0)
712 break;
713 if (Features.test(Feature_HasV9Bit)) // "stw"
714 Mnemonic = "st";
715 return;
716 case 4: // 10 strings to match.
717 switch (Mnemonic[0]) {
718 default: break;
719 case 'a': // 1 string to match.
720 if (memcmp(Mnemonic.data()+1, "ddc", 3) != 0)
721 break;
722 if (Features.test(Feature_HasV9Bit)) // "addc"
723 Mnemonic = "addx";
724 return;
725 case 'l': // 1 string to match.
726 if (memcmp(Mnemonic.data()+1, "duw", 3) != 0)
727 break;
728 if (Features.test(Feature_HasV9Bit)) // "lduw"
729 Mnemonic = "ld";
730 return;
731 case 's': // 8 strings to match.
732 switch (Mnemonic[1]) {
733 default: break;
734 case 't': // 7 strings to match.
735 switch (Mnemonic[2]) {
736 default: break;
737 case 's': // 3 strings to match.
738 switch (Mnemonic[3]) {
739 default: break;
740 case 'b': // 1 string to match.
741 Mnemonic = "stb"; // "stsb"
742 return;
743 case 'h': // 1 string to match.
744 Mnemonic = "sth"; // "stsh"
745 return;
746 case 'w': // 1 string to match.
747 if (Features.test(Feature_HasV9Bit)) // "stsw"
748 Mnemonic = "st";
749 return;
750 }
751 break;
752 case 'u': // 3 strings to match.
753 switch (Mnemonic[3]) {
754 default: break;
755 case 'b': // 1 string to match.
756 Mnemonic = "stb"; // "stub"
757 return;
758 case 'h': // 1 string to match.
759 Mnemonic = "sth"; // "stuh"
760 return;
761 case 'w': // 1 string to match.
762 if (Features.test(Feature_HasV9Bit)) // "stuw"
763 Mnemonic = "st";
764 return;
765 }
766 break;
767 case 'w': // 1 string to match.
768 if (Mnemonic[3] != 'a')
769 break;
770 if (Features.test(Feature_HasV9Bit)) // "stwa"
771 Mnemonic = "sta";
772 return;
773 }
774 break;
775 case 'u': // 1 string to match.
776 if (memcmp(Mnemonic.data()+2, "bc", 2) != 0)
777 break;
778 if (Features.test(Feature_HasV9Bit)) // "subc"
779 Mnemonic = "subx";
780 return;
781 }
782 break;
783 }
784 break;
785 case 5: // 8 strings to match.
786 switch (Mnemonic[0]) {
787 default: break;
788 case 'l': // 1 string to match.
789 if (memcmp(Mnemonic.data()+1, "duwa", 4) != 0)
790 break;
791 if (Features.test(Feature_HasV9Bit)) // "lduwa"
792 Mnemonic = "lda";
793 return;
794 case 's': // 7 strings to match.
795 switch (Mnemonic[1]) {
796 default: break;
797 case 'e': // 1 string to match.
798 if (memcmp(Mnemonic.data()+2, "tuw", 3) != 0)
799 break;
800 if (Features.test(Feature_HasV9Bit)) // "setuw"
801 Mnemonic = "set";
802 return;
803 case 't': // 6 strings to match.
804 switch (Mnemonic[2]) {
805 default: break;
806 case 's': // 3 strings to match.
807 switch (Mnemonic[3]) {
808 default: break;
809 case 'b': // 1 string to match.
810 if (Mnemonic[4] != 'a')
811 break;
812 Mnemonic = "stba"; // "stsba"
813 return;
814 case 'h': // 1 string to match.
815 if (Mnemonic[4] != 'a')
816 break;
817 Mnemonic = "stha"; // "stsha"
818 return;
819 case 'w': // 1 string to match.
820 if (Mnemonic[4] != 'a')
821 break;
822 if (Features.test(Feature_HasV9Bit)) // "stswa"
823 Mnemonic = "sta";
824 return;
825 }
826 break;
827 case 'u': // 3 strings to match.
828 switch (Mnemonic[3]) {
829 default: break;
830 case 'b': // 1 string to match.
831 if (Mnemonic[4] != 'a')
832 break;
833 Mnemonic = "stba"; // "stuba"
834 return;
835 case 'h': // 1 string to match.
836 if (Mnemonic[4] != 'a')
837 break;
838 Mnemonic = "stha"; // "stuha"
839 return;
840 case 'w': // 1 string to match.
841 if (Mnemonic[4] != 'a')
842 break;
843 if (Features.test(Feature_HasV9Bit)) // "stuwa"
844 Mnemonic = "sta";
845 return;
846 }
847 break;
848 }
849 break;
850 }
851 break;
852 }
853 break;
854 case 6: // 4 strings to match.
855 switch (Mnemonic[0]) {
856 default: break;
857 case 'a': // 1 string to match.
858 if (memcmp(Mnemonic.data()+1, "ddccc", 5) != 0)
859 break;
860 if (Features.test(Feature_HasV9Bit)) // "addccc"
861 Mnemonic = "addxcc";
862 return;
863 case 'i': // 1 string to match.
864 if (memcmp(Mnemonic.data()+1, "flush", 5) != 0)
865 break;
866 Mnemonic = "flush"; // "iflush"
867 return;
868 case 'r': // 1 string to match.
869 if (memcmp(Mnemonic.data()+1, "eturn", 5) != 0)
870 break;
871 if (Features.test(Feature_HasV9Bit)) // "return"
872 Mnemonic = "rett";
873 return;
874 case 's': // 1 string to match.
875 if (memcmp(Mnemonic.data()+1, "ubccc", 5) != 0)
876 break;
877 if (Features.test(Feature_HasV9Bit)) // "subccc"
878 Mnemonic = "subxcc";
879 return;
880 }
881 break;
882 case 7: // 1 string to match.
883 if (memcmp(Mnemonic.data()+0, "illtrap", 7) != 0)
884 break;
885 Mnemonic = "unimp"; // "illtrap"
886 return;
887 }
888}
889
890enum {
891 Tie0_1_1,
892 Tie0_3_3,
893 Tie0_5_5,
894};
895
896static const uint8_t TiedAsmOperandTable[][3] = {
897 /* Tie0_1_1 */ { 0, 1, 1 },
898 /* Tie0_3_3 */ { 0, 3, 3 },
899 /* Tie0_5_5 */ { 0, 5, 5 },
900};
901
902namespace {
903enum OperatorConversionKind {
904 CVT_Done,
905 CVT_Reg,
906 CVT_Tied,
907 CVT_95_Reg,
908 CVT_95_addImmOperands,
909 CVT_95_addTailRelocSymOperands,
910 CVT_imm_95_8,
911 CVT_imm_95_13,
912 CVT_imm_95_5,
913 CVT_imm_95_1,
914 CVT_imm_95_10,
915 CVT_imm_95_11,
916 CVT_imm_95_12,
917 CVT_imm_95_3,
918 CVT_imm_95_2,
919 CVT_imm_95_4,
920 CVT_imm_95_0,
921 CVT_imm_95_9,
922 CVT_imm_95_6,
923 CVT_imm_95_14,
924 CVT_imm_95_7,
925 CVT_regG0,
926 CVT_imm_95_15,
927 CVT_95_addCallTargetOperands,
928 CVT_regO7,
929 CVT_95_addMEMriOperands,
930 CVT_95_addMEMrrOperands,
931 CVT_imm_95_128,
932 CVT_95_addASITagOperands,
933 CVT_imm_95_136,
934 CVT_regFCC0,
935 CVT_95_addMembarTagOperands,
936 CVT_regASR27,
937 CVT_95_addPrefetchTagOperands,
938 CVT_95_addShiftAmtImm5Operands,
939 CVT_95_addShiftAmtImm6Operands,
940 CVT_NUM_CONVERTERS
941};
942
943enum InstructionConversionKind {
944 Convert__Reg1_2__Reg1_0__Reg1_1,
945 Convert__Reg1_2__Reg1_0__Imm1_1,
946 Convert__Reg1_2__Reg1_0__Reg1_1__TailRelocSymAdd_TLS1_3,
947 Convert__Reg1_2__Reg1_1__Imm1_0,
948 Convert_NoOperands,
949 Convert__Imm1_0__imm_95_8,
950 Convert__Imm1_1__imm_95_8,
951 Convert__Imm1_1__Imm1_0,
952 Convert__Imm1_2__imm_95_8,
953 Convert__Imm1_2__Imm1_0,
954 Convert__Imm1_3__imm_95_8,
955 Convert__Imm1_3__Imm1_0,
956 Convert__Imm1_4__Imm1_0,
957 Convert__Imm1_0,
958 Convert__Imm1_0__imm_95_13,
959 Convert__Imm1_1__imm_95_13,
960 Convert__Imm1_2__imm_95_13,
961 Convert__Imm1_3__imm_95_13,
962 Convert__Reg1_1__Reg1_1__Reg1_0,
963 Convert__Reg1_1__Reg1_1__Imm1_0,
964 Convert__Imm1_0__imm_95_5,
965 Convert__Imm1_1__imm_95_5,
966 Convert__Imm1_2__imm_95_5,
967 Convert__Imm1_3__imm_95_5,
968 Convert__Imm1_0__imm_95_1,
969 Convert__Imm1_1__imm_95_1,
970 Convert__Imm1_2__imm_95_1,
971 Convert__Imm1_3__imm_95_1,
972 Convert__Imm1_0__imm_95_10,
973 Convert__Imm1_1__imm_95_10,
974 Convert__Imm1_2__imm_95_10,
975 Convert__Imm1_3__imm_95_10,
976 Convert__Imm1_0__imm_95_11,
977 Convert__Imm1_1__imm_95_11,
978 Convert__Imm1_2__imm_95_11,
979 Convert__Imm1_3__imm_95_11,
980 Convert__Imm1_0__imm_95_12,
981 Convert__Imm1_1__imm_95_12,
982 Convert__Imm1_2__imm_95_12,
983 Convert__Imm1_3__imm_95_12,
984 Convert__Imm1_0__imm_95_3,
985 Convert__Imm1_1__imm_95_3,
986 Convert__Imm1_2__imm_95_3,
987 Convert__Imm1_3__imm_95_3,
988 Convert__Imm1_0__imm_95_2,
989 Convert__Imm1_1__imm_95_2,
990 Convert__Imm1_2__imm_95_2,
991 Convert__Imm1_3__imm_95_2,
992 Convert__Imm1_0__imm_95_4,
993 Convert__Imm1_1__imm_95_4,
994 Convert__Imm1_2__imm_95_4,
995 Convert__Imm1_3__imm_95_4,
996 Convert__Imm1_0__imm_95_0,
997 Convert__Imm1_1__imm_95_0,
998 Convert__Imm1_2__imm_95_0,
999 Convert__Imm1_3__imm_95_0,
1000 Convert__Imm1_0__imm_95_9,
1001 Convert__Imm1_1__imm_95_9,
1002 Convert__Imm1_2__imm_95_9,
1003 Convert__Imm1_3__imm_95_9,
1004 Convert__Imm1_0__imm_95_6,
1005 Convert__Imm1_1__imm_95_6,
1006 Convert__Imm1_2__imm_95_6,
1007 Convert__Imm1_3__imm_95_6,
1008 Convert__Imm1_0__imm_95_14,
1009 Convert__Imm1_1__imm_95_14,
1010 Convert__Imm1_2__imm_95_14,
1011 Convert__Imm1_3__imm_95_14,
1012 Convert__Imm1_2__Imm1_0__Reg1_1,
1013 Convert__Imm1_3__Imm1_0__Reg1_2,
1014 Convert__Imm1_4__Imm1_0__Reg1_3,
1015 Convert__Imm1_1__imm_95_1__Reg1_0,
1016 Convert__Imm1_2__imm_95_1__Reg1_1,
1017 Convert__Imm1_3__imm_95_1__Reg1_2,
1018 Convert__Imm1_1__imm_95_7__Reg1_0,
1019 Convert__Imm1_2__imm_95_7__Reg1_1,
1020 Convert__Imm1_3__imm_95_7__Reg1_2,
1021 Convert__Imm1_1__imm_95_6__Reg1_0,
1022 Convert__Imm1_2__imm_95_6__Reg1_1,
1023 Convert__Imm1_3__imm_95_6__Reg1_2,
1024 Convert__Imm1_1__imm_95_2__Reg1_0,
1025 Convert__Imm1_2__imm_95_2__Reg1_1,
1026 Convert__Imm1_3__imm_95_2__Reg1_2,
1027 Convert__Imm1_1__imm_95_3__Reg1_0,
1028 Convert__Imm1_2__imm_95_3__Reg1_1,
1029 Convert__Imm1_3__imm_95_3__Reg1_2,
1030 Convert__Imm1_1__imm_95_5__Reg1_0,
1031 Convert__Imm1_2__imm_95_5__Reg1_1,
1032 Convert__Imm1_3__imm_95_5__Reg1_2,
1033 Convert__regG0__Reg1_1__Reg1_0,
1034 Convert__regG0__Reg1_1__Imm1_0,
1035 Convert__Imm1_0__imm_95_15,
1036 Convert__Imm1_1__imm_95_15,
1037 Convert__Imm1_2__imm_95_15,
1038 Convert__Imm1_3__imm_95_15,
1039 Convert__Imm1_0__imm_95_7,
1040 Convert__Imm1_1__imm_95_7,
1041 Convert__Imm1_2__imm_95_7,
1042 Convert__Imm1_3__imm_95_7,
1043 Convert__CallTarget1_0,
1044 Convert__regO7__MEMri2_0,
1045 Convert__regO7__MEMrr2_0,
1046 Convert__CallTarget1_0__Imm1_1,
1047 Convert__CallTarget1_0__TailRelocSymCall_TLS1_1,
1048 Convert__MEMri2_0__Imm1_1,
1049 Convert__MEMrr2_0__Imm1_1,
1050 Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_128,
1051 Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1,
1052 Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1__ASITag1_3,
1053 Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_136,
1054 Convert__Reg1_0__regG0__regG0,
1055 Convert__MEMri2_1__regG0,
1056 Convert__MEMrr2_1__regG0,
1057 Convert__Reg1_0,
1058 Convert__regG0__Reg1_0__Reg1_1,
1059 Convert__regG0__Reg1_0__Imm1_1,
1060 Convert__Imm1_3__Imm1_0__Reg1_1__Reg1_2,
1061 Convert__Imm1_3__Imm1_0__Reg1_1__Imm1_2,
1062 Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1,
1063 Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1,
1064 Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1,
1065 Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1,
1066 Convert__Imm1_2__imm_95_1__Reg1_0__Reg1_1,
1067 Convert__Imm1_2__imm_95_1__Reg1_0__Imm1_1,
1068 Convert__Imm1_2__imm_95_10__Reg1_0__Reg1_1,
1069 Convert__Imm1_2__imm_95_10__Reg1_0__Imm1_1,
1070 Convert__Imm1_2__imm_95_11__Reg1_0__Reg1_1,
1071 Convert__Imm1_2__imm_95_11__Reg1_0__Imm1_1,
1072 Convert__Imm1_2__imm_95_12__Reg1_0__Reg1_1,
1073 Convert__Imm1_2__imm_95_12__Reg1_0__Imm1_1,
1074 Convert__Imm1_2__imm_95_3__Reg1_0__Reg1_1,
1075 Convert__Imm1_2__imm_95_3__Reg1_0__Imm1_1,
1076 Convert__Imm1_2__imm_95_2__Reg1_0__Reg1_1,
1077 Convert__Imm1_2__imm_95_2__Reg1_0__Imm1_1,
1078 Convert__Imm1_2__imm_95_4__Reg1_0__Reg1_1,
1079 Convert__Imm1_2__imm_95_4__Reg1_0__Imm1_1,
1080 Convert__Imm1_2__imm_95_9__Reg1_0__Reg1_1,
1081 Convert__Imm1_2__imm_95_9__Reg1_0__Imm1_1,
1082 Convert__Imm1_2__imm_95_6__Reg1_0__Reg1_1,
1083 Convert__Imm1_2__imm_95_6__Reg1_0__Imm1_1,
1084 Convert__Imm1_2__imm_95_14__Reg1_0__Reg1_1,
1085 Convert__Imm1_2__imm_95_14__Reg1_0__Imm1_1,
1086 Convert__Imm1_2__imm_95_15__Reg1_0__Reg1_1,
1087 Convert__Imm1_2__imm_95_15__Reg1_0__Imm1_1,
1088 Convert__Imm1_2__imm_95_7__Reg1_0__Reg1_1,
1089 Convert__Imm1_2__imm_95_7__Reg1_0__Imm1_1,
1090 Convert__Reg1_0__Reg1_0__imm_95_1,
1091 Convert__Reg1_1__Reg1_0,
1092 Convert__Imm1_1__imm_95_8__Reg1_0,
1093 Convert__Imm1_2__imm_95_8__Reg1_1,
1094 Convert__Imm1_3__imm_95_8__Reg1_2,
1095 Convert__Imm1_1__imm_95_9__Reg1_0,
1096 Convert__Imm1_2__imm_95_9__Reg1_1,
1097 Convert__Imm1_3__imm_95_9__Reg1_2,
1098 Convert__Imm1_1__imm_95_11__Reg1_0,
1099 Convert__Imm1_2__imm_95_11__Reg1_1,
1100 Convert__Imm1_3__imm_95_11__Reg1_2,
1101 Convert__Imm1_1__imm_95_4__Reg1_0,
1102 Convert__Imm1_2__imm_95_4__Reg1_1,
1103 Convert__Imm1_3__imm_95_4__Reg1_2,
1104 Convert__Imm1_1__imm_95_13__Reg1_0,
1105 Convert__Imm1_2__imm_95_13__Reg1_1,
1106 Convert__Imm1_3__imm_95_13__Reg1_2,
1107 Convert__Imm1_1__imm_95_0__Reg1_0,
1108 Convert__Imm1_2__imm_95_0__Reg1_1,
1109 Convert__Imm1_3__imm_95_0__Reg1_2,
1110 Convert__Imm1_1__imm_95_15__Reg1_0,
1111 Convert__Imm1_2__imm_95_15__Reg1_1,
1112 Convert__Imm1_3__imm_95_15__Reg1_2,
1113 Convert__Imm1_1__imm_95_10__Reg1_0,
1114 Convert__Imm1_2__imm_95_10__Reg1_1,
1115 Convert__Imm1_3__imm_95_10__Reg1_2,
1116 Convert__Imm1_1__imm_95_12__Reg1_0,
1117 Convert__Imm1_2__imm_95_12__Reg1_1,
1118 Convert__Imm1_3__imm_95_12__Reg1_2,
1119 Convert__Imm1_1__imm_95_14__Reg1_0,
1120 Convert__Imm1_2__imm_95_14__Reg1_1,
1121 Convert__Imm1_3__imm_95_14__Reg1_2,
1122 Convert__regFCC0__Reg1_0__Reg1_1,
1123 Convert__Reg1_0__Reg1_1__Reg1_2,
1124 Convert__MEMri2_0,
1125 Convert__MEMrr2_0,
1126 Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2,
1127 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8,
1128 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8,
1129 Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0,
1130 Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0,
1131 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13,
1132 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5,
1133 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1,
1134 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9,
1135 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10,
1136 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6,
1137 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11,
1138 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11,
1139 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12,
1140 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3,
1141 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4,
1142 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2,
1143 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13,
1144 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4,
1145 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2,
1146 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0,
1147 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0,
1148 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9,
1149 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1,
1150 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6,
1151 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15,
1152 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14,
1153 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7,
1154 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10,
1155 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5,
1156 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12,
1157 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3,
1158 Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14,
1159 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15,
1160 Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7,
1161 Convert__regG0__MEMri2_0,
1162 Convert__regG0__MEMrr2_0,
1163 Convert__Reg1_1__MEMri2_0,
1164 Convert__Reg1_1__MEMrr2_0,
1165 Convert__MEMri2_1,
1166 Convert__Reg1_3__MEMri2_1,
1167 Convert__MEMrr2_1,
1168 Convert__Reg1_3__MEMrr2_1,
1169 Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_GOT1_4,
1170 Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_TLS1_4,
1171 Convert__Reg1_4__MEMri2_1,
1172 Convert__Reg1_4__MEMrr2_1__ASITag1_3,
1173 Convert__MembarTag1_0,
1174 Convert__Reg1_1,
1175 Convert__regG0__Reg1_0,
1176 Convert__Reg1_1__regG0__Reg1_0,
1177 Convert__regG0__Imm1_0,
1178 Convert__Reg1_1__regG0__Imm1_0,
1179 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8,
1180 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_8,
1181 Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0,
1182 Convert__Reg1_3__Reg1_1__Imm1_2__Tie0_1_1__Imm1_0,
1183 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13,
1184 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5,
1185 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1,
1186 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_9,
1187 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10,
1188 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_6,
1189 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11,
1190 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_11,
1191 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12,
1192 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3,
1193 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_4,
1194 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2,
1195 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_13,
1196 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4,
1197 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_2,
1198 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0,
1199 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_0,
1200 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9,
1201 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1,
1202 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6,
1203 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_15,
1204 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14,
1205 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_7,
1206 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_3,
1207 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5,
1208 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_10,
1209 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_12,
1210 Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_14,
1211 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15,
1212 Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7,
1213 Convert__Reg1_0__regG0__Reg1_0,
1214 Convert__Reg1_0__Reg1_0__regG0,
1215 Convert__Reg1_1__Reg1_0__regG0,
1216 Convert__regASR27__regG0__Reg1_0,
1217 Convert__regASR27__regG0__Imm1_0,
1218 Convert__MEMri2_1__PrefetchTag1_3,
1219 Convert__MEMrr2_1__PrefetchTag1_3,
1220 Convert__MEMri2_1__PrefetchTag1_4,
1221 Convert__MEMrr2_1__ASITag1_3__PrefetchTag1_4,
1222 Convert__Reg1_0__Reg1_1,
1223 Convert__Reg1_0__Imm1_1,
1224 Convert__regG0__regG0__regG0,
1225 Convert__imm_95_8,
1226 Convert__Reg1_1__Imm1_0,
1227 Convert__Reg1_2__Imm1_0__Reg1_1,
1228 Convert__imm_95_0,
1229 Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1,
1230 Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1,
1231 Convert__Reg1_2__Reg1_0__Reg1_1__imm_95_0,
1232 Convert__Reg1_2__Reg1_0__Imm1_1__imm_95_0,
1233 Convert__MEMri2_2,
1234 Convert__MEMrr2_2,
1235 Convert__MEMri2_2__Reg1_0,
1236 Convert__MEMrr2_2__Reg1_0,
1237 Convert__MEMrr2_2__Reg1_0__ASITag1_4,
1238 Convert__Reg1_3__MEMri2_1__Tie0_1_1,
1239 Convert__Reg1_3__MEMrr2_1__Tie0_1_1,
1240 Convert__Reg1_4__MEMri2_1__Tie0_1_1,
1241 Convert__Reg1_4__MEMrr2_1__ASITag1_3__Tie0_1_1,
1242 Convert__regG0__Reg1_0__imm_95_8,
1243 Convert__regG0__Imm1_0__imm_95_8,
1244 Convert__regG0__Reg1_1__imm_95_8,
1245 Convert__regG0__Imm1_1__imm_95_8,
1246 Convert__Reg1_0__Reg1_2__imm_95_8,
1247 Convert__Reg1_0__Imm1_2__imm_95_8,
1248 Convert__Reg1_1__Reg1_3__imm_95_8,
1249 Convert__Reg1_1__Imm1_3__imm_95_8,
1250 Convert__Reg1_1__Reg1_3__Imm1_0,
1251 Convert__Reg1_1__Imm1_3__Imm1_0,
1252 Convert__Reg1_2__Reg1_4__Imm1_0,
1253 Convert__Reg1_2__Imm1_4__Imm1_0,
1254 Convert__regG0__Reg1_0__imm_95_13,
1255 Convert__regG0__Imm1_0__imm_95_13,
1256 Convert__regG0__Reg1_1__imm_95_13,
1257 Convert__regG0__Imm1_1__imm_95_13,
1258 Convert__Reg1_0__Reg1_2__imm_95_13,
1259 Convert__Reg1_0__Imm1_2__imm_95_13,
1260 Convert__Reg1_1__Reg1_3__imm_95_13,
1261 Convert__Reg1_1__Imm1_3__imm_95_13,
1262 Convert__regG0__Reg1_0__imm_95_5,
1263 Convert__regG0__Imm1_0__imm_95_5,
1264 Convert__regG0__Reg1_1__imm_95_5,
1265 Convert__regG0__Imm1_1__imm_95_5,
1266 Convert__Reg1_0__Reg1_2__imm_95_5,
1267 Convert__Reg1_0__Imm1_2__imm_95_5,
1268 Convert__Reg1_1__Reg1_3__imm_95_5,
1269 Convert__Reg1_1__Imm1_3__imm_95_5,
1270 Convert__regG0__Reg1_0__imm_95_1,
1271 Convert__regG0__Imm1_0__imm_95_1,
1272 Convert__regG0__Reg1_1__imm_95_1,
1273 Convert__regG0__Imm1_1__imm_95_1,
1274 Convert__Reg1_0__Reg1_2__imm_95_1,
1275 Convert__Reg1_0__Imm1_2__imm_95_1,
1276 Convert__Reg1_1__Reg1_3__imm_95_1,
1277 Convert__Reg1_1__Imm1_3__imm_95_1,
1278 Convert__regG0__Reg1_0__imm_95_10,
1279 Convert__regG0__Imm1_0__imm_95_10,
1280 Convert__regG0__Reg1_1__imm_95_10,
1281 Convert__regG0__Imm1_1__imm_95_10,
1282 Convert__Reg1_0__Reg1_2__imm_95_10,
1283 Convert__Reg1_0__Imm1_2__imm_95_10,
1284 Convert__Reg1_1__Reg1_3__imm_95_10,
1285 Convert__Reg1_1__Imm1_3__imm_95_10,
1286 Convert__regG0__Reg1_0__imm_95_11,
1287 Convert__regG0__Imm1_0__imm_95_11,
1288 Convert__regG0__Reg1_1__imm_95_11,
1289 Convert__regG0__Imm1_1__imm_95_11,
1290 Convert__Reg1_0__Reg1_2__imm_95_11,
1291 Convert__Reg1_0__Imm1_2__imm_95_11,
1292 Convert__Reg1_1__Reg1_3__imm_95_11,
1293 Convert__Reg1_1__Imm1_3__imm_95_11,
1294 Convert__regG0__Reg1_0__imm_95_12,
1295 Convert__regG0__Imm1_0__imm_95_12,
1296 Convert__regG0__Reg1_1__imm_95_12,
1297 Convert__regG0__Imm1_1__imm_95_12,
1298 Convert__Reg1_0__Reg1_2__imm_95_12,
1299 Convert__Reg1_0__Imm1_2__imm_95_12,
1300 Convert__Reg1_1__Reg1_3__imm_95_12,
1301 Convert__Reg1_1__Imm1_3__imm_95_12,
1302 Convert__regG0__Reg1_0__imm_95_3,
1303 Convert__regG0__Imm1_0__imm_95_3,
1304 Convert__regG0__Reg1_1__imm_95_3,
1305 Convert__regG0__Imm1_1__imm_95_3,
1306 Convert__Reg1_0__Reg1_2__imm_95_3,
1307 Convert__Reg1_0__Imm1_2__imm_95_3,
1308 Convert__Reg1_1__Reg1_3__imm_95_3,
1309 Convert__Reg1_1__Imm1_3__imm_95_3,
1310 Convert__regG0__Reg1_0__imm_95_2,
1311 Convert__regG0__Imm1_0__imm_95_2,
1312 Convert__regG0__Reg1_1__imm_95_2,
1313 Convert__regG0__Imm1_1__imm_95_2,
1314 Convert__Reg1_0__Reg1_2__imm_95_2,
1315 Convert__Reg1_0__Imm1_2__imm_95_2,
1316 Convert__Reg1_1__Reg1_3__imm_95_2,
1317 Convert__Reg1_1__Imm1_3__imm_95_2,
1318 Convert__regG0__Reg1_0__imm_95_4,
1319 Convert__regG0__Imm1_0__imm_95_4,
1320 Convert__regG0__Reg1_1__imm_95_4,
1321 Convert__regG0__Imm1_1__imm_95_4,
1322 Convert__Reg1_0__Reg1_2__imm_95_4,
1323 Convert__Reg1_0__Imm1_2__imm_95_4,
1324 Convert__Reg1_1__Reg1_3__imm_95_4,
1325 Convert__Reg1_1__Imm1_3__imm_95_4,
1326 Convert__regG0__Reg1_0__imm_95_0,
1327 Convert__regG0__Imm1_0__imm_95_0,
1328 Convert__regG0__Reg1_1__imm_95_0,
1329 Convert__regG0__Imm1_1__imm_95_0,
1330 Convert__Reg1_0__Reg1_2__imm_95_0,
1331 Convert__Reg1_0__Imm1_2__imm_95_0,
1332 Convert__Reg1_1__Reg1_3__imm_95_0,
1333 Convert__Reg1_1__Imm1_3__imm_95_0,
1334 Convert__regG0__Reg1_0__imm_95_9,
1335 Convert__regG0__Imm1_0__imm_95_9,
1336 Convert__regG0__Reg1_1__imm_95_9,
1337 Convert__regG0__Imm1_1__imm_95_9,
1338 Convert__Reg1_0__Reg1_2__imm_95_9,
1339 Convert__Reg1_0__Imm1_2__imm_95_9,
1340 Convert__Reg1_1__Reg1_3__imm_95_9,
1341 Convert__Reg1_1__Imm1_3__imm_95_9,
1342 Convert__regG0__Reg1_0__imm_95_6,
1343 Convert__regG0__Imm1_0__imm_95_6,
1344 Convert__regG0__Reg1_1__imm_95_6,
1345 Convert__regG0__Imm1_1__imm_95_6,
1346 Convert__Reg1_0__Reg1_2__imm_95_6,
1347 Convert__Reg1_0__Imm1_2__imm_95_6,
1348 Convert__Reg1_1__Reg1_3__imm_95_6,
1349 Convert__Reg1_1__Imm1_3__imm_95_6,
1350 Convert__regG0__Reg1_0__imm_95_14,
1351 Convert__regG0__Imm1_0__imm_95_14,
1352 Convert__regG0__Reg1_1__imm_95_14,
1353 Convert__regG0__Imm1_1__imm_95_14,
1354 Convert__Reg1_0__Reg1_2__imm_95_14,
1355 Convert__Reg1_0__Imm1_2__imm_95_14,
1356 Convert__Reg1_1__Reg1_3__imm_95_14,
1357 Convert__Reg1_1__Imm1_3__imm_95_14,
1358 Convert__regG0__Reg1_0__regG0,
1359 Convert__regG0__Reg1_0__imm_95_15,
1360 Convert__regG0__Imm1_0__imm_95_15,
1361 Convert__regG0__Reg1_1__imm_95_15,
1362 Convert__regG0__Imm1_1__imm_95_15,
1363 Convert__Reg1_0__Reg1_2__imm_95_15,
1364 Convert__Reg1_0__Imm1_2__imm_95_15,
1365 Convert__Reg1_1__Reg1_3__imm_95_15,
1366 Convert__Reg1_1__Imm1_3__imm_95_15,
1367 Convert__regG0__Reg1_0__imm_95_7,
1368 Convert__regG0__Imm1_0__imm_95_7,
1369 Convert__regG0__Reg1_1__imm_95_7,
1370 Convert__regG0__Imm1_1__imm_95_7,
1371 Convert__Reg1_0__Reg1_2__imm_95_7,
1372 Convert__Reg1_0__Imm1_2__imm_95_7,
1373 Convert__Reg1_1__Reg1_3__imm_95_7,
1374 Convert__Reg1_1__Imm1_3__imm_95_7,
1375 CVT_NUM_SIGNATURES
1376};
1377
1378} // end anonymous namespace
1379
1380static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
1381 // Convert__Reg1_2__Reg1_0__Reg1_1
1382 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1383 // Convert__Reg1_2__Reg1_0__Imm1_1
1384 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1385 // Convert__Reg1_2__Reg1_0__Reg1_1__TailRelocSymAdd_TLS1_3
1386 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addTailRelocSymOperands, 4, CVT_Done },
1387 // Convert__Reg1_2__Reg1_1__Imm1_0
1388 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
1389 // Convert_NoOperands
1390 { CVT_Done },
1391 // Convert__Imm1_0__imm_95_8
1392 { CVT_95_addImmOperands, 1, CVT_imm_95_8, 0, CVT_Done },
1393 // Convert__Imm1_1__imm_95_8
1394 { CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_Done },
1395 // Convert__Imm1_1__Imm1_0
1396 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
1397 // Convert__Imm1_2__imm_95_8
1398 { CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_Done },
1399 // Convert__Imm1_2__Imm1_0
1400 { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
1401 // Convert__Imm1_3__imm_95_8
1402 { CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_Done },
1403 // Convert__Imm1_3__Imm1_0
1404 { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
1405 // Convert__Imm1_4__Imm1_0
1406 { CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
1407 // Convert__Imm1_0
1408 { CVT_95_addImmOperands, 1, CVT_Done },
1409 // Convert__Imm1_0__imm_95_13
1410 { CVT_95_addImmOperands, 1, CVT_imm_95_13, 0, CVT_Done },
1411 // Convert__Imm1_1__imm_95_13
1412 { CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_Done },
1413 // Convert__Imm1_2__imm_95_13
1414 { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_Done },
1415 // Convert__Imm1_3__imm_95_13
1416 { CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_Done },
1417 // Convert__Reg1_1__Reg1_1__Reg1_0
1418 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
1419 // Convert__Reg1_1__Reg1_1__Imm1_0
1420 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
1421 // Convert__Imm1_0__imm_95_5
1422 { CVT_95_addImmOperands, 1, CVT_imm_95_5, 0, CVT_Done },
1423 // Convert__Imm1_1__imm_95_5
1424 { CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_Done },
1425 // Convert__Imm1_2__imm_95_5
1426 { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_Done },
1427 // Convert__Imm1_3__imm_95_5
1428 { CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_Done },
1429 // Convert__Imm1_0__imm_95_1
1430 { CVT_95_addImmOperands, 1, CVT_imm_95_1, 0, CVT_Done },
1431 // Convert__Imm1_1__imm_95_1
1432 { CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
1433 // Convert__Imm1_2__imm_95_1
1434 { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_Done },
1435 // Convert__Imm1_3__imm_95_1
1436 { CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_Done },
1437 // Convert__Imm1_0__imm_95_10
1438 { CVT_95_addImmOperands, 1, CVT_imm_95_10, 0, CVT_Done },
1439 // Convert__Imm1_1__imm_95_10
1440 { CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_Done },
1441 // Convert__Imm1_2__imm_95_10
1442 { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_Done },
1443 // Convert__Imm1_3__imm_95_10
1444 { CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_Done },
1445 // Convert__Imm1_0__imm_95_11
1446 { CVT_95_addImmOperands, 1, CVT_imm_95_11, 0, CVT_Done },
1447 // Convert__Imm1_1__imm_95_11
1448 { CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_Done },
1449 // Convert__Imm1_2__imm_95_11
1450 { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_Done },
1451 // Convert__Imm1_3__imm_95_11
1452 { CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_Done },
1453 // Convert__Imm1_0__imm_95_12
1454 { CVT_95_addImmOperands, 1, CVT_imm_95_12, 0, CVT_Done },
1455 // Convert__Imm1_1__imm_95_12
1456 { CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_Done },
1457 // Convert__Imm1_2__imm_95_12
1458 { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_Done },
1459 // Convert__Imm1_3__imm_95_12
1460 { CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_Done },
1461 // Convert__Imm1_0__imm_95_3
1462 { CVT_95_addImmOperands, 1, CVT_imm_95_3, 0, CVT_Done },
1463 // Convert__Imm1_1__imm_95_3
1464 { CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_Done },
1465 // Convert__Imm1_2__imm_95_3
1466 { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_Done },
1467 // Convert__Imm1_3__imm_95_3
1468 { CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_Done },
1469 // Convert__Imm1_0__imm_95_2
1470 { CVT_95_addImmOperands, 1, CVT_imm_95_2, 0, CVT_Done },
1471 // Convert__Imm1_1__imm_95_2
1472 { CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_Done },
1473 // Convert__Imm1_2__imm_95_2
1474 { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_Done },
1475 // Convert__Imm1_3__imm_95_2
1476 { CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_Done },
1477 // Convert__Imm1_0__imm_95_4
1478 { CVT_95_addImmOperands, 1, CVT_imm_95_4, 0, CVT_Done },
1479 // Convert__Imm1_1__imm_95_4
1480 { CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_Done },
1481 // Convert__Imm1_2__imm_95_4
1482 { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_Done },
1483 // Convert__Imm1_3__imm_95_4
1484 { CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_Done },
1485 // Convert__Imm1_0__imm_95_0
1486 { CVT_95_addImmOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1487 // Convert__Imm1_1__imm_95_0
1488 { CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1489 // Convert__Imm1_2__imm_95_0
1490 { CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
1491 // Convert__Imm1_3__imm_95_0
1492 { CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_Done },
1493 // Convert__Imm1_0__imm_95_9
1494 { CVT_95_addImmOperands, 1, CVT_imm_95_9, 0, CVT_Done },
1495 // Convert__Imm1_1__imm_95_9
1496 { CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_Done },
1497 // Convert__Imm1_2__imm_95_9
1498 { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_Done },
1499 // Convert__Imm1_3__imm_95_9
1500 { CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_Done },
1501 // Convert__Imm1_0__imm_95_6
1502 { CVT_95_addImmOperands, 1, CVT_imm_95_6, 0, CVT_Done },
1503 // Convert__Imm1_1__imm_95_6
1504 { CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_Done },
1505 // Convert__Imm1_2__imm_95_6
1506 { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_Done },
1507 // Convert__Imm1_3__imm_95_6
1508 { CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_Done },
1509 // Convert__Imm1_0__imm_95_14
1510 { CVT_95_addImmOperands, 1, CVT_imm_95_14, 0, CVT_Done },
1511 // Convert__Imm1_1__imm_95_14
1512 { CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_Done },
1513 // Convert__Imm1_2__imm_95_14
1514 { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_Done },
1515 // Convert__Imm1_3__imm_95_14
1516 { CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_Done },
1517 // Convert__Imm1_2__Imm1_0__Reg1_1
1518 { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
1519 // Convert__Imm1_3__Imm1_0__Reg1_2
1520 { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_Done },
1521 // Convert__Imm1_4__Imm1_0__Reg1_3
1522 { CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_95_Reg, 4, CVT_Done },
1523 // Convert__Imm1_1__imm_95_1__Reg1_0
1524 { CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
1525 // Convert__Imm1_2__imm_95_1__Reg1_1
1526 { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
1527 // Convert__Imm1_3__imm_95_1__Reg1_2
1528 { CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_95_Reg, 3, CVT_Done },
1529 // Convert__Imm1_1__imm_95_7__Reg1_0
1530 { CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_95_Reg, 1, CVT_Done },
1531 // Convert__Imm1_2__imm_95_7__Reg1_1
1532 { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_95_Reg, 2, CVT_Done },
1533 // Convert__Imm1_3__imm_95_7__Reg1_2
1534 { CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_95_Reg, 3, CVT_Done },
1535 // Convert__Imm1_1__imm_95_6__Reg1_0
1536 { CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_95_Reg, 1, CVT_Done },
1537 // Convert__Imm1_2__imm_95_6__Reg1_1
1538 { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_95_Reg, 2, CVT_Done },
1539 // Convert__Imm1_3__imm_95_6__Reg1_2
1540 { CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_95_Reg, 3, CVT_Done },
1541 // Convert__Imm1_1__imm_95_2__Reg1_0
1542 { CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
1543 // Convert__Imm1_2__imm_95_2__Reg1_1
1544 { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
1545 // Convert__Imm1_3__imm_95_2__Reg1_2
1546 { CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_95_Reg, 3, CVT_Done },
1547 // Convert__Imm1_1__imm_95_3__Reg1_0
1548 { CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
1549 // Convert__Imm1_2__imm_95_3__Reg1_1
1550 { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
1551 // Convert__Imm1_3__imm_95_3__Reg1_2
1552 { CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_95_Reg, 3, CVT_Done },
1553 // Convert__Imm1_1__imm_95_5__Reg1_0
1554 { CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_95_Reg, 1, CVT_Done },
1555 // Convert__Imm1_2__imm_95_5__Reg1_1
1556 { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_95_Reg, 2, CVT_Done },
1557 // Convert__Imm1_3__imm_95_5__Reg1_2
1558 { CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_95_Reg, 3, CVT_Done },
1559 // Convert__regG0__Reg1_1__Reg1_0
1560 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
1561 // Convert__regG0__Reg1_1__Imm1_0
1562 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
1563 // Convert__Imm1_0__imm_95_15
1564 { CVT_95_addImmOperands, 1, CVT_imm_95_15, 0, CVT_Done },
1565 // Convert__Imm1_1__imm_95_15
1566 { CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_Done },
1567 // Convert__Imm1_2__imm_95_15
1568 { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_Done },
1569 // Convert__Imm1_3__imm_95_15
1570 { CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_Done },
1571 // Convert__Imm1_0__imm_95_7
1572 { CVT_95_addImmOperands, 1, CVT_imm_95_7, 0, CVT_Done },
1573 // Convert__Imm1_1__imm_95_7
1574 { CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_Done },
1575 // Convert__Imm1_2__imm_95_7
1576 { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_Done },
1577 // Convert__Imm1_3__imm_95_7
1578 { CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_Done },
1579 // Convert__CallTarget1_0
1580 { CVT_95_addCallTargetOperands, 1, CVT_Done },
1581 // Convert__regO7__MEMri2_0
1582 { CVT_regO7, 0, CVT_95_addMEMriOperands, 1, CVT_Done },
1583 // Convert__regO7__MEMrr2_0
1584 { CVT_regO7, 0, CVT_95_addMEMrrOperands, 1, CVT_Done },
1585 // Convert__CallTarget1_0__Imm1_1
1586 { CVT_95_addCallTargetOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1587 // Convert__CallTarget1_0__TailRelocSymCall_TLS1_1
1588 { CVT_95_addCallTargetOperands, 1, CVT_95_addTailRelocSymOperands, 2, CVT_Done },
1589 // Convert__MEMri2_0__Imm1_1
1590 { CVT_95_addMEMriOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1591 // Convert__MEMrr2_0__Imm1_1
1592 { CVT_95_addMEMrrOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1593 // Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_128
1594 { CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_5_5, CVT_imm_95_128, 0, CVT_Done },
1595 // Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1
1596 { CVT_95_Reg, 6, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Done },
1597 // Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1__ASITag1_3
1598 { CVT_95_Reg, 6, CVT_95_Reg, 2, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_addASITagOperands, 4, CVT_Done },
1599 // Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_136
1600 { CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_5_5, CVT_imm_95_136, 0, CVT_Done },
1601 // Convert__Reg1_0__regG0__regG0
1602 { CVT_95_Reg, 1, CVT_regG0, 0, CVT_regG0, 0, CVT_Done },
1603 // Convert__MEMri2_1__regG0
1604 { CVT_95_addMEMriOperands, 2, CVT_regG0, 0, CVT_Done },
1605 // Convert__MEMrr2_1__regG0
1606 { CVT_95_addMEMrrOperands, 2, CVT_regG0, 0, CVT_Done },
1607 // Convert__Reg1_0
1608 { CVT_95_Reg, 1, CVT_Done },
1609 // Convert__regG0__Reg1_0__Reg1_1
1610 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1611 // Convert__regG0__Reg1_0__Imm1_1
1612 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1613 // Convert__Imm1_3__Imm1_0__Reg1_1__Reg1_2
1614 { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1615 // Convert__Imm1_3__Imm1_0__Reg1_1__Imm1_2
1616 { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
1617 // Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1
1618 { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1619 // Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1
1620 { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1621 // Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1
1622 { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1623 // Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1
1624 { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1625 // Convert__Imm1_2__imm_95_1__Reg1_0__Reg1_1
1626 { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1627 // Convert__Imm1_2__imm_95_1__Reg1_0__Imm1_1
1628 { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1629 // Convert__Imm1_2__imm_95_10__Reg1_0__Reg1_1
1630 { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1631 // Convert__Imm1_2__imm_95_10__Reg1_0__Imm1_1
1632 { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1633 // Convert__Imm1_2__imm_95_11__Reg1_0__Reg1_1
1634 { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1635 // Convert__Imm1_2__imm_95_11__Reg1_0__Imm1_1
1636 { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1637 // Convert__Imm1_2__imm_95_12__Reg1_0__Reg1_1
1638 { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1639 // Convert__Imm1_2__imm_95_12__Reg1_0__Imm1_1
1640 { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1641 // Convert__Imm1_2__imm_95_3__Reg1_0__Reg1_1
1642 { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1643 // Convert__Imm1_2__imm_95_3__Reg1_0__Imm1_1
1644 { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1645 // Convert__Imm1_2__imm_95_2__Reg1_0__Reg1_1
1646 { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1647 // Convert__Imm1_2__imm_95_2__Reg1_0__Imm1_1
1648 { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1649 // Convert__Imm1_2__imm_95_4__Reg1_0__Reg1_1
1650 { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1651 // Convert__Imm1_2__imm_95_4__Reg1_0__Imm1_1
1652 { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1653 // Convert__Imm1_2__imm_95_9__Reg1_0__Reg1_1
1654 { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1655 // Convert__Imm1_2__imm_95_9__Reg1_0__Imm1_1
1656 { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1657 // Convert__Imm1_2__imm_95_6__Reg1_0__Reg1_1
1658 { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1659 // Convert__Imm1_2__imm_95_6__Reg1_0__Imm1_1
1660 { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1661 // Convert__Imm1_2__imm_95_14__Reg1_0__Reg1_1
1662 { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1663 // Convert__Imm1_2__imm_95_14__Reg1_0__Imm1_1
1664 { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1665 // Convert__Imm1_2__imm_95_15__Reg1_0__Reg1_1
1666 { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1667 // Convert__Imm1_2__imm_95_15__Reg1_0__Imm1_1
1668 { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1669 // Convert__Imm1_2__imm_95_7__Reg1_0__Reg1_1
1670 { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1671 // Convert__Imm1_2__imm_95_7__Reg1_0__Imm1_1
1672 { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1673 // Convert__Reg1_0__Reg1_0__imm_95_1
1674 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
1675 // Convert__Reg1_1__Reg1_0
1676 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
1677 // Convert__Imm1_1__imm_95_8__Reg1_0
1678 { CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_95_Reg, 1, CVT_Done },
1679 // Convert__Imm1_2__imm_95_8__Reg1_1
1680 { CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_95_Reg, 2, CVT_Done },
1681 // Convert__Imm1_3__imm_95_8__Reg1_2
1682 { CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_95_Reg, 3, CVT_Done },
1683 // Convert__Imm1_1__imm_95_9__Reg1_0
1684 { CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_95_Reg, 1, CVT_Done },
1685 // Convert__Imm1_2__imm_95_9__Reg1_1
1686 { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_95_Reg, 2, CVT_Done },
1687 // Convert__Imm1_3__imm_95_9__Reg1_2
1688 { CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_95_Reg, 3, CVT_Done },
1689 // Convert__Imm1_1__imm_95_11__Reg1_0
1690 { CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_95_Reg, 1, CVT_Done },
1691 // Convert__Imm1_2__imm_95_11__Reg1_1
1692 { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_95_Reg, 2, CVT_Done },
1693 // Convert__Imm1_3__imm_95_11__Reg1_2
1694 { CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_95_Reg, 3, CVT_Done },
1695 // Convert__Imm1_1__imm_95_4__Reg1_0
1696 { CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_95_Reg, 1, CVT_Done },
1697 // Convert__Imm1_2__imm_95_4__Reg1_1
1698 { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_95_Reg, 2, CVT_Done },
1699 // Convert__Imm1_3__imm_95_4__Reg1_2
1700 { CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_95_Reg, 3, CVT_Done },
1701 // Convert__Imm1_1__imm_95_13__Reg1_0
1702 { CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_95_Reg, 1, CVT_Done },
1703 // Convert__Imm1_2__imm_95_13__Reg1_1
1704 { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_95_Reg, 2, CVT_Done },
1705 // Convert__Imm1_3__imm_95_13__Reg1_2
1706 { CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_95_Reg, 3, CVT_Done },
1707 // Convert__Imm1_1__imm_95_0__Reg1_0
1708 { CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_Done },
1709 // Convert__Imm1_2__imm_95_0__Reg1_1
1710 { CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_Done },
1711 // Convert__Imm1_3__imm_95_0__Reg1_2
1712 { CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_Done },
1713 // Convert__Imm1_1__imm_95_15__Reg1_0
1714 { CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_95_Reg, 1, CVT_Done },
1715 // Convert__Imm1_2__imm_95_15__Reg1_1
1716 { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_95_Reg, 2, CVT_Done },
1717 // Convert__Imm1_3__imm_95_15__Reg1_2
1718 { CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_95_Reg, 3, CVT_Done },
1719 // Convert__Imm1_1__imm_95_10__Reg1_0
1720 { CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_95_Reg, 1, CVT_Done },
1721 // Convert__Imm1_2__imm_95_10__Reg1_1
1722 { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_95_Reg, 2, CVT_Done },
1723 // Convert__Imm1_3__imm_95_10__Reg1_2
1724 { CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_95_Reg, 3, CVT_Done },
1725 // Convert__Imm1_1__imm_95_12__Reg1_0
1726 { CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_95_Reg, 1, CVT_Done },
1727 // Convert__Imm1_2__imm_95_12__Reg1_1
1728 { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_95_Reg, 2, CVT_Done },
1729 // Convert__Imm1_3__imm_95_12__Reg1_2
1730 { CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_95_Reg, 3, CVT_Done },
1731 // Convert__Imm1_1__imm_95_14__Reg1_0
1732 { CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_95_Reg, 1, CVT_Done },
1733 // Convert__Imm1_2__imm_95_14__Reg1_1
1734 { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_95_Reg, 2, CVT_Done },
1735 // Convert__Imm1_3__imm_95_14__Reg1_2
1736 { CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_95_Reg, 3, CVT_Done },
1737 // Convert__regFCC0__Reg1_0__Reg1_1
1738 { CVT_regFCC0, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1739 // Convert__Reg1_0__Reg1_1__Reg1_2
1740 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1741 // Convert__MEMri2_0
1742 { CVT_95_addMEMriOperands, 1, CVT_Done },
1743 // Convert__MEMrr2_0
1744 { CVT_95_addMEMrrOperands, 1, CVT_Done },
1745 // Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2
1746 { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
1747 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8
1748 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_8, 0, CVT_Done },
1749 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8
1750 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_8, 0, CVT_Done },
1751 // Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0
1752 { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
1753 // Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0
1754 { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
1755 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13
1756 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_13, 0, CVT_Done },
1757 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5
1758 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_5, 0, CVT_Done },
1759 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1
1760 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_1, 0, CVT_Done },
1761 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9
1762 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_9, 0, CVT_Done },
1763 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10
1764 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_10, 0, CVT_Done },
1765 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6
1766 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_6, 0, CVT_Done },
1767 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11
1768 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_11, 0, CVT_Done },
1769 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11
1770 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_11, 0, CVT_Done },
1771 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12
1772 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_12, 0, CVT_Done },
1773 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3
1774 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_3, 0, CVT_Done },
1775 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4
1776 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_4, 0, CVT_Done },
1777 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2
1778 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_2, 0, CVT_Done },
1779 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13
1780 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_13, 0, CVT_Done },
1781 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4
1782 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_4, 0, CVT_Done },
1783 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2
1784 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_2, 0, CVT_Done },
1785 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0
1786 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_0, 0, CVT_Done },
1787 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0
1788 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_0, 0, CVT_Done },
1789 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9
1790 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_9, 0, CVT_Done },
1791 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1
1792 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_1, 0, CVT_Done },
1793 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6
1794 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_6, 0, CVT_Done },
1795 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15
1796 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_15, 0, CVT_Done },
1797 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14
1798 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_14, 0, CVT_Done },
1799 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7
1800 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_7, 0, CVT_Done },
1801 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10
1802 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_10, 0, CVT_Done },
1803 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5
1804 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_5, 0, CVT_Done },
1805 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12
1806 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_12, 0, CVT_Done },
1807 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3
1808 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_3, 0, CVT_Done },
1809 // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14
1810 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_14, 0, CVT_Done },
1811 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15
1812 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_15, 0, CVT_Done },
1813 // Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7
1814 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_7, 0, CVT_Done },
1815 // Convert__regG0__MEMri2_0
1816 { CVT_regG0, 0, CVT_95_addMEMriOperands, 1, CVT_Done },
1817 // Convert__regG0__MEMrr2_0
1818 { CVT_regG0, 0, CVT_95_addMEMrrOperands, 1, CVT_Done },
1819 // Convert__Reg1_1__MEMri2_0
1820 { CVT_95_Reg, 2, CVT_95_addMEMriOperands, 1, CVT_Done },
1821 // Convert__Reg1_1__MEMrr2_0
1822 { CVT_95_Reg, 2, CVT_95_addMEMrrOperands, 1, CVT_Done },
1823 // Convert__MEMri2_1
1824 { CVT_95_addMEMriOperands, 2, CVT_Done },
1825 // Convert__Reg1_3__MEMri2_1
1826 { CVT_95_Reg, 4, CVT_95_addMEMriOperands, 2, CVT_Done },
1827 // Convert__MEMrr2_1
1828 { CVT_95_addMEMrrOperands, 2, CVT_Done },
1829 // Convert__Reg1_3__MEMrr2_1
1830 { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_Done },
1831 // Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_GOT1_4
1832 { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_95_addTailRelocSymOperands, 5, CVT_Done },
1833 // Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_TLS1_4
1834 { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_95_addTailRelocSymOperands, 5, CVT_Done },
1835 // Convert__Reg1_4__MEMri2_1
1836 { CVT_95_Reg, 5, CVT_95_addMEMriOperands, 2, CVT_Done },
1837 // Convert__Reg1_4__MEMrr2_1__ASITag1_3
1838 { CVT_95_Reg, 5, CVT_95_addMEMrrOperands, 2, CVT_95_addASITagOperands, 4, CVT_Done },
1839 // Convert__MembarTag1_0
1840 { CVT_95_addMembarTagOperands, 1, CVT_Done },
1841 // Convert__Reg1_1
1842 { CVT_95_Reg, 2, CVT_Done },
1843 // Convert__regG0__Reg1_0
1844 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
1845 // Convert__Reg1_1__regG0__Reg1_0
1846 { CVT_95_Reg, 2, CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
1847 // Convert__regG0__Imm1_0
1848 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1849 // Convert__Reg1_1__regG0__Imm1_0
1850 { CVT_95_Reg, 2, CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1851 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8
1852 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_8, 0, CVT_Done },
1853 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_8
1854 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_8, 0, CVT_Done },
1855 // Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0
1856 { CVT_95_Reg, 4, CVT_95_addImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
1857 // Convert__Reg1_3__Reg1_1__Imm1_2__Tie0_1_1__Imm1_0
1858 { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
1859 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13
1860 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_13, 0, CVT_Done },
1861 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5
1862 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_5, 0, CVT_Done },
1863 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1
1864 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_1, 0, CVT_Done },
1865 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_9
1866 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_9, 0, CVT_Done },
1867 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10
1868 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_10, 0, CVT_Done },
1869 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_6
1870 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_6, 0, CVT_Done },
1871 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11
1872 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_11, 0, CVT_Done },
1873 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_11
1874 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_11, 0, CVT_Done },
1875 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12
1876 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_12, 0, CVT_Done },
1877 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3
1878 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_3, 0, CVT_Done },
1879 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_4
1880 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_4, 0, CVT_Done },
1881 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2
1882 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_2, 0, CVT_Done },
1883 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_13
1884 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_13, 0, CVT_Done },
1885 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4
1886 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_4, 0, CVT_Done },
1887 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_2
1888 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_2, 0, CVT_Done },
1889 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0
1890 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_0, 0, CVT_Done },
1891 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_0
1892 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_0, 0, CVT_Done },
1893 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9
1894 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_9, 0, CVT_Done },
1895 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1
1896 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_1, 0, CVT_Done },
1897 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6
1898 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_6, 0, CVT_Done },
1899 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_15
1900 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_15, 0, CVT_Done },
1901 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14
1902 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_14, 0, CVT_Done },
1903 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_7
1904 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_7, 0, CVT_Done },
1905 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_3
1906 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_3, 0, CVT_Done },
1907 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5
1908 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_5, 0, CVT_Done },
1909 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_10
1910 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_10, 0, CVT_Done },
1911 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_12
1912 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_12, 0, CVT_Done },
1913 // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_14
1914 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_14, 0, CVT_Done },
1915 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15
1916 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_15, 0, CVT_Done },
1917 // Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7
1918 { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, Tie0_3_3, CVT_imm_95_7, 0, CVT_Done },
1919 // Convert__Reg1_0__regG0__Reg1_0
1920 { CVT_95_Reg, 1, CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
1921 // Convert__Reg1_0__Reg1_0__regG0
1922 { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
1923 // Convert__Reg1_1__Reg1_0__regG0
1924 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
1925 // Convert__regASR27__regG0__Reg1_0
1926 { CVT_regASR27, 0, CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
1927 // Convert__regASR27__regG0__Imm1_0
1928 { CVT_regASR27, 0, CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_Done },
1929 // Convert__MEMri2_1__PrefetchTag1_3
1930 { CVT_95_addMEMriOperands, 2, CVT_95_addPrefetchTagOperands, 4, CVT_Done },
1931 // Convert__MEMrr2_1__PrefetchTag1_3
1932 { CVT_95_addMEMrrOperands, 2, CVT_95_addPrefetchTagOperands, 4, CVT_Done },
1933 // Convert__MEMri2_1__PrefetchTag1_4
1934 { CVT_95_addMEMriOperands, 2, CVT_95_addPrefetchTagOperands, 5, CVT_Done },
1935 // Convert__MEMrr2_1__ASITag1_3__PrefetchTag1_4
1936 { CVT_95_addMEMrrOperands, 2, CVT_95_addASITagOperands, 4, CVT_95_addPrefetchTagOperands, 5, CVT_Done },
1937 // Convert__Reg1_0__Reg1_1
1938 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
1939 // Convert__Reg1_0__Imm1_1
1940 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
1941 // Convert__regG0__regG0__regG0
1942 { CVT_regG0, 0, CVT_regG0, 0, CVT_regG0, 0, CVT_Done },
1943 // Convert__imm_95_8
1944 { CVT_imm_95_8, 0, CVT_Done },
1945 // Convert__Reg1_1__Imm1_0
1946 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
1947 // Convert__Reg1_2__Imm1_0__Reg1_1
1948 { CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
1949 // Convert__imm_95_0
1950 { CVT_imm_95_0, 0, CVT_Done },
1951 // Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1
1952 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addShiftAmtImm5Operands, 2, CVT_Done },
1953 // Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1
1954 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addShiftAmtImm6Operands, 2, CVT_Done },
1955 // Convert__Reg1_2__Reg1_0__Reg1_1__imm_95_0
1956 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
1957 // Convert__Reg1_2__Reg1_0__Imm1_1__imm_95_0
1958 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1959 // Convert__MEMri2_2
1960 { CVT_95_addMEMriOperands, 3, CVT_Done },
1961 // Convert__MEMrr2_2
1962 { CVT_95_addMEMrrOperands, 3, CVT_Done },
1963 // Convert__MEMri2_2__Reg1_0
1964 { CVT_95_addMEMriOperands, 3, CVT_95_Reg, 1, CVT_Done },
1965 // Convert__MEMrr2_2__Reg1_0
1966 { CVT_95_addMEMrrOperands, 3, CVT_95_Reg, 1, CVT_Done },
1967 // Convert__MEMrr2_2__Reg1_0__ASITag1_4
1968 { CVT_95_addMEMrrOperands, 3, CVT_95_Reg, 1, CVT_95_addASITagOperands, 5, CVT_Done },
1969 // Convert__Reg1_3__MEMri2_1__Tie0_1_1
1970 { CVT_95_Reg, 4, CVT_95_addMEMriOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1971 // Convert__Reg1_3__MEMrr2_1__Tie0_1_1
1972 { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1973 // Convert__Reg1_4__MEMri2_1__Tie0_1_1
1974 { CVT_95_Reg, 5, CVT_95_addMEMriOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1975 // Convert__Reg1_4__MEMrr2_1__ASITag1_3__Tie0_1_1
1976 { CVT_95_Reg, 5, CVT_95_addMEMrrOperands, 2, CVT_95_addASITagOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1977 // Convert__regG0__Reg1_0__imm_95_8
1978 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_8, 0, CVT_Done },
1979 // Convert__regG0__Imm1_0__imm_95_8
1980 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_8, 0, CVT_Done },
1981 // Convert__regG0__Reg1_1__imm_95_8
1982 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_8, 0, CVT_Done },
1983 // Convert__regG0__Imm1_1__imm_95_8
1984 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_Done },
1985 // Convert__Reg1_0__Reg1_2__imm_95_8
1986 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_8, 0, CVT_Done },
1987 // Convert__Reg1_0__Imm1_2__imm_95_8
1988 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_Done },
1989 // Convert__Reg1_1__Reg1_3__imm_95_8
1990 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_8, 0, CVT_Done },
1991 // Convert__Reg1_1__Imm1_3__imm_95_8
1992 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_Done },
1993 // Convert__Reg1_1__Reg1_3__Imm1_0
1994 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
1995 // Convert__Reg1_1__Imm1_3__Imm1_0
1996 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
1997 // Convert__Reg1_2__Reg1_4__Imm1_0
1998 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 1, CVT_Done },
1999 // Convert__Reg1_2__Imm1_4__Imm1_0
2000 { CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
2001 // Convert__regG0__Reg1_0__imm_95_13
2002 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_13, 0, CVT_Done },
2003 // Convert__regG0__Imm1_0__imm_95_13
2004 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_13, 0, CVT_Done },
2005 // Convert__regG0__Reg1_1__imm_95_13
2006 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_13, 0, CVT_Done },
2007 // Convert__regG0__Imm1_1__imm_95_13
2008 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_Done },
2009 // Convert__Reg1_0__Reg1_2__imm_95_13
2010 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_13, 0, CVT_Done },
2011 // Convert__Reg1_0__Imm1_2__imm_95_13
2012 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_Done },
2013 // Convert__Reg1_1__Reg1_3__imm_95_13
2014 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_13, 0, CVT_Done },
2015 // Convert__Reg1_1__Imm1_3__imm_95_13
2016 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_Done },
2017 // Convert__regG0__Reg1_0__imm_95_5
2018 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_5, 0, CVT_Done },
2019 // Convert__regG0__Imm1_0__imm_95_5
2020 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_5, 0, CVT_Done },
2021 // Convert__regG0__Reg1_1__imm_95_5
2022 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_5, 0, CVT_Done },
2023 // Convert__regG0__Imm1_1__imm_95_5
2024 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_Done },
2025 // Convert__Reg1_0__Reg1_2__imm_95_5
2026 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_5, 0, CVT_Done },
2027 // Convert__Reg1_0__Imm1_2__imm_95_5
2028 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_Done },
2029 // Convert__Reg1_1__Reg1_3__imm_95_5
2030 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_5, 0, CVT_Done },
2031 // Convert__Reg1_1__Imm1_3__imm_95_5
2032 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_Done },
2033 // Convert__regG0__Reg1_0__imm_95_1
2034 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
2035 // Convert__regG0__Imm1_0__imm_95_1
2036 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_1, 0, CVT_Done },
2037 // Convert__regG0__Reg1_1__imm_95_1
2038 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
2039 // Convert__regG0__Imm1_1__imm_95_1
2040 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
2041 // Convert__Reg1_0__Reg1_2__imm_95_1
2042 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_Done },
2043 // Convert__Reg1_0__Imm1_2__imm_95_1
2044 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_Done },
2045 // Convert__Reg1_1__Reg1_3__imm_95_1
2046 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_1, 0, CVT_Done },
2047 // Convert__Reg1_1__Imm1_3__imm_95_1
2048 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_Done },
2049 // Convert__regG0__Reg1_0__imm_95_10
2050 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_10, 0, CVT_Done },
2051 // Convert__regG0__Imm1_0__imm_95_10
2052 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_10, 0, CVT_Done },
2053 // Convert__regG0__Reg1_1__imm_95_10
2054 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_10, 0, CVT_Done },
2055 // Convert__regG0__Imm1_1__imm_95_10
2056 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_Done },
2057 // Convert__Reg1_0__Reg1_2__imm_95_10
2058 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_10, 0, CVT_Done },
2059 // Convert__Reg1_0__Imm1_2__imm_95_10
2060 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_Done },
2061 // Convert__Reg1_1__Reg1_3__imm_95_10
2062 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_10, 0, CVT_Done },
2063 // Convert__Reg1_1__Imm1_3__imm_95_10
2064 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_Done },
2065 // Convert__regG0__Reg1_0__imm_95_11
2066 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_11, 0, CVT_Done },
2067 // Convert__regG0__Imm1_0__imm_95_11
2068 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_11, 0, CVT_Done },
2069 // Convert__regG0__Reg1_1__imm_95_11
2070 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_11, 0, CVT_Done },
2071 // Convert__regG0__Imm1_1__imm_95_11
2072 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_Done },
2073 // Convert__Reg1_0__Reg1_2__imm_95_11
2074 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_11, 0, CVT_Done },
2075 // Convert__Reg1_0__Imm1_2__imm_95_11
2076 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_Done },
2077 // Convert__Reg1_1__Reg1_3__imm_95_11
2078 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_11, 0, CVT_Done },
2079 // Convert__Reg1_1__Imm1_3__imm_95_11
2080 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_Done },
2081 // Convert__regG0__Reg1_0__imm_95_12
2082 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_12, 0, CVT_Done },
2083 // Convert__regG0__Imm1_0__imm_95_12
2084 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_12, 0, CVT_Done },
2085 // Convert__regG0__Reg1_1__imm_95_12
2086 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_12, 0, CVT_Done },
2087 // Convert__regG0__Imm1_1__imm_95_12
2088 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_Done },
2089 // Convert__Reg1_0__Reg1_2__imm_95_12
2090 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_12, 0, CVT_Done },
2091 // Convert__Reg1_0__Imm1_2__imm_95_12
2092 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_Done },
2093 // Convert__Reg1_1__Reg1_3__imm_95_12
2094 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_12, 0, CVT_Done },
2095 // Convert__Reg1_1__Imm1_3__imm_95_12
2096 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_Done },
2097 // Convert__regG0__Reg1_0__imm_95_3
2098 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_Done },
2099 // Convert__regG0__Imm1_0__imm_95_3
2100 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_3, 0, CVT_Done },
2101 // Convert__regG0__Reg1_1__imm_95_3
2102 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_3, 0, CVT_Done },
2103 // Convert__regG0__Imm1_1__imm_95_3
2104 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_Done },
2105 // Convert__Reg1_0__Reg1_2__imm_95_3
2106 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_3, 0, CVT_Done },
2107 // Convert__Reg1_0__Imm1_2__imm_95_3
2108 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_Done },
2109 // Convert__Reg1_1__Reg1_3__imm_95_3
2110 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_3, 0, CVT_Done },
2111 // Convert__Reg1_1__Imm1_3__imm_95_3
2112 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_Done },
2113 // Convert__regG0__Reg1_0__imm_95_2
2114 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_Done },
2115 // Convert__regG0__Imm1_0__imm_95_2
2116 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_2, 0, CVT_Done },
2117 // Convert__regG0__Reg1_1__imm_95_2
2118 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_2, 0, CVT_Done },
2119 // Convert__regG0__Imm1_1__imm_95_2
2120 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_Done },
2121 // Convert__Reg1_0__Reg1_2__imm_95_2
2122 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_2, 0, CVT_Done },
2123 // Convert__Reg1_0__Imm1_2__imm_95_2
2124 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_Done },
2125 // Convert__Reg1_1__Reg1_3__imm_95_2
2126 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_2, 0, CVT_Done },
2127 // Convert__Reg1_1__Imm1_3__imm_95_2
2128 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_Done },
2129 // Convert__regG0__Reg1_0__imm_95_4
2130 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_4, 0, CVT_Done },
2131 // Convert__regG0__Imm1_0__imm_95_4
2132 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_4, 0, CVT_Done },
2133 // Convert__regG0__Reg1_1__imm_95_4
2134 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_4, 0, CVT_Done },
2135 // Convert__regG0__Imm1_1__imm_95_4
2136 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_Done },
2137 // Convert__Reg1_0__Reg1_2__imm_95_4
2138 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_4, 0, CVT_Done },
2139 // Convert__Reg1_0__Imm1_2__imm_95_4
2140 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_Done },
2141 // Convert__Reg1_1__Reg1_3__imm_95_4
2142 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_4, 0, CVT_Done },
2143 // Convert__Reg1_1__Imm1_3__imm_95_4
2144 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_Done },
2145 // Convert__regG0__Reg1_0__imm_95_0
2146 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
2147 // Convert__regG0__Imm1_0__imm_95_0
2148 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_0, 0, CVT_Done },
2149 // Convert__regG0__Reg1_1__imm_95_0
2150 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
2151 // Convert__regG0__Imm1_1__imm_95_0
2152 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2153 // Convert__Reg1_0__Reg1_2__imm_95_0
2154 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
2155 // Convert__Reg1_0__Imm1_2__imm_95_0
2156 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
2157 // Convert__Reg1_1__Reg1_3__imm_95_0
2158 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
2159 // Convert__Reg1_1__Imm1_3__imm_95_0
2160 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_Done },
2161 // Convert__regG0__Reg1_0__imm_95_9
2162 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_9, 0, CVT_Done },
2163 // Convert__regG0__Imm1_0__imm_95_9
2164 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_9, 0, CVT_Done },
2165 // Convert__regG0__Reg1_1__imm_95_9
2166 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_9, 0, CVT_Done },
2167 // Convert__regG0__Imm1_1__imm_95_9
2168 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_Done },
2169 // Convert__Reg1_0__Reg1_2__imm_95_9
2170 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_9, 0, CVT_Done },
2171 // Convert__Reg1_0__Imm1_2__imm_95_9
2172 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_Done },
2173 // Convert__Reg1_1__Reg1_3__imm_95_9
2174 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_9, 0, CVT_Done },
2175 // Convert__Reg1_1__Imm1_3__imm_95_9
2176 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_Done },
2177 // Convert__regG0__Reg1_0__imm_95_6
2178 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_6, 0, CVT_Done },
2179 // Convert__regG0__Imm1_0__imm_95_6
2180 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_6, 0, CVT_Done },
2181 // Convert__regG0__Reg1_1__imm_95_6
2182 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_6, 0, CVT_Done },
2183 // Convert__regG0__Imm1_1__imm_95_6
2184 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_Done },
2185 // Convert__Reg1_0__Reg1_2__imm_95_6
2186 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_6, 0, CVT_Done },
2187 // Convert__Reg1_0__Imm1_2__imm_95_6
2188 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_Done },
2189 // Convert__Reg1_1__Reg1_3__imm_95_6
2190 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_6, 0, CVT_Done },
2191 // Convert__Reg1_1__Imm1_3__imm_95_6
2192 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_Done },
2193 // Convert__regG0__Reg1_0__imm_95_14
2194 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_14, 0, CVT_Done },
2195 // Convert__regG0__Imm1_0__imm_95_14
2196 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_14, 0, CVT_Done },
2197 // Convert__regG0__Reg1_1__imm_95_14
2198 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_14, 0, CVT_Done },
2199 // Convert__regG0__Imm1_1__imm_95_14
2200 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_Done },
2201 // Convert__Reg1_0__Reg1_2__imm_95_14
2202 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_14, 0, CVT_Done },
2203 // Convert__Reg1_0__Imm1_2__imm_95_14
2204 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_Done },
2205 // Convert__Reg1_1__Reg1_3__imm_95_14
2206 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_14, 0, CVT_Done },
2207 // Convert__Reg1_1__Imm1_3__imm_95_14
2208 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_Done },
2209 // Convert__regG0__Reg1_0__regG0
2210 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
2211 // Convert__regG0__Reg1_0__imm_95_15
2212 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_15, 0, CVT_Done },
2213 // Convert__regG0__Imm1_0__imm_95_15
2214 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_15, 0, CVT_Done },
2215 // Convert__regG0__Reg1_1__imm_95_15
2216 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_15, 0, CVT_Done },
2217 // Convert__regG0__Imm1_1__imm_95_15
2218 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_Done },
2219 // Convert__Reg1_0__Reg1_2__imm_95_15
2220 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_15, 0, CVT_Done },
2221 // Convert__Reg1_0__Imm1_2__imm_95_15
2222 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_Done },
2223 // Convert__Reg1_1__Reg1_3__imm_95_15
2224 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_15, 0, CVT_Done },
2225 // Convert__Reg1_1__Imm1_3__imm_95_15
2226 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_Done },
2227 // Convert__regG0__Reg1_0__imm_95_7
2228 { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_7, 0, CVT_Done },
2229 // Convert__regG0__Imm1_0__imm_95_7
2230 { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_7, 0, CVT_Done },
2231 // Convert__regG0__Reg1_1__imm_95_7
2232 { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done },
2233 // Convert__regG0__Imm1_1__imm_95_7
2234 { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_Done },
2235 // Convert__Reg1_0__Reg1_2__imm_95_7
2236 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_7, 0, CVT_Done },
2237 // Convert__Reg1_0__Imm1_2__imm_95_7
2238 { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_Done },
2239 // Convert__Reg1_1__Reg1_3__imm_95_7
2240 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_7, 0, CVT_Done },
2241 // Convert__Reg1_1__Imm1_3__imm_95_7
2242 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_Done },
2243};
2244
2245void SparcAsmParser::
2246convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2247 const OperandVector &Operands) {
2248 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2249 const uint8_t *Converter = ConversionTable[Kind];
2250 Inst.setOpcode(Opcode);
2251 for (const uint8_t *p = Converter; *p; p += 2) {
2252 unsigned OpIdx = *(p + 1);
2253 switch (*p) {
2254 default: llvm_unreachable("invalid conversion entry!");
2255 case CVT_Reg:
2256 static_cast<SparcOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2257 break;
2258 case CVT_Tied: {
2259 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
2260 std::begin(TiedAsmOperandTable)) &&
2261 "Tied operand not found");
2262 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
2263 if (TiedResOpnd != (uint8_t)-1)
2264 Inst.addOperand(Inst.getOperand(TiedResOpnd));
2265 break;
2266 }
2267 case CVT_95_Reg:
2268 static_cast<SparcOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2269 break;
2270 case CVT_95_addImmOperands:
2271 static_cast<SparcOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2272 break;
2273 case CVT_95_addTailRelocSymOperands:
2274 static_cast<SparcOperand &>(*Operands[OpIdx]).addTailRelocSymOperands(Inst, 1);
2275 break;
2276 case CVT_imm_95_8:
2277 Inst.addOperand(MCOperand::createImm(8));
2278 break;
2279 case CVT_imm_95_13:
2280 Inst.addOperand(MCOperand::createImm(13));
2281 break;
2282 case CVT_imm_95_5:
2283 Inst.addOperand(MCOperand::createImm(5));
2284 break;
2285 case CVT_imm_95_1:
2286 Inst.addOperand(MCOperand::createImm(1));
2287 break;
2288 case CVT_imm_95_10:
2289 Inst.addOperand(MCOperand::createImm(10));
2290 break;
2291 case CVT_imm_95_11:
2292 Inst.addOperand(MCOperand::createImm(11));
2293 break;
2294 case CVT_imm_95_12:
2295 Inst.addOperand(MCOperand::createImm(12));
2296 break;
2297 case CVT_imm_95_3:
2298 Inst.addOperand(MCOperand::createImm(3));
2299 break;
2300 case CVT_imm_95_2:
2301 Inst.addOperand(MCOperand::createImm(2));
2302 break;
2303 case CVT_imm_95_4:
2304 Inst.addOperand(MCOperand::createImm(4));
2305 break;
2306 case CVT_imm_95_0:
2307 Inst.addOperand(MCOperand::createImm(0));
2308 break;
2309 case CVT_imm_95_9:
2310 Inst.addOperand(MCOperand::createImm(9));
2311 break;
2312 case CVT_imm_95_6:
2313 Inst.addOperand(MCOperand::createImm(6));
2314 break;
2315 case CVT_imm_95_14:
2316 Inst.addOperand(MCOperand::createImm(14));
2317 break;
2318 case CVT_imm_95_7:
2319 Inst.addOperand(MCOperand::createImm(7));
2320 break;
2321 case CVT_regG0:
2322 Inst.addOperand(MCOperand::createReg(SP::G0));
2323 break;
2324 case CVT_imm_95_15:
2325 Inst.addOperand(MCOperand::createImm(15));
2326 break;
2327 case CVT_95_addCallTargetOperands:
2328 static_cast<SparcOperand &>(*Operands[OpIdx]).addCallTargetOperands(Inst, 1);
2329 break;
2330 case CVT_regO7:
2331 Inst.addOperand(MCOperand::createReg(SP::O7));
2332 break;
2333 case CVT_95_addMEMriOperands:
2334 static_cast<SparcOperand &>(*Operands[OpIdx]).addMEMriOperands(Inst, 2);
2335 break;
2336 case CVT_95_addMEMrrOperands:
2337 static_cast<SparcOperand &>(*Operands[OpIdx]).addMEMrrOperands(Inst, 2);
2338 break;
2339 case CVT_imm_95_128:
2340 Inst.addOperand(MCOperand::createImm(128));
2341 break;
2342 case CVT_95_addASITagOperands:
2343 static_cast<SparcOperand &>(*Operands[OpIdx]).addASITagOperands(Inst, 1);
2344 break;
2345 case CVT_imm_95_136:
2346 Inst.addOperand(MCOperand::createImm(136));
2347 break;
2348 case CVT_regFCC0:
2349 Inst.addOperand(MCOperand::createReg(SP::FCC0));
2350 break;
2351 case CVT_95_addMembarTagOperands:
2352 static_cast<SparcOperand &>(*Operands[OpIdx]).addMembarTagOperands(Inst, 1);
2353 break;
2354 case CVT_regASR27:
2355 Inst.addOperand(MCOperand::createReg(SP::ASR27));
2356 break;
2357 case CVT_95_addPrefetchTagOperands:
2358 static_cast<SparcOperand &>(*Operands[OpIdx]).addPrefetchTagOperands(Inst, 1);
2359 break;
2360 case CVT_95_addShiftAmtImm5Operands:
2361 static_cast<SparcOperand &>(*Operands[OpIdx]).addShiftAmtImm5Operands(Inst, 1);
2362 break;
2363 case CVT_95_addShiftAmtImm6Operands:
2364 static_cast<SparcOperand &>(*Operands[OpIdx]).addShiftAmtImm6Operands(Inst, 1);
2365 break;
2366 }
2367 }
2368}
2369
2370void SparcAsmParser::
2371convertToMapAndConstraints(unsigned Kind,
2372 const OperandVector &Operands) {
2373 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2374 unsigned NumMCOperands = 0;
2375 const uint8_t *Converter = ConversionTable[Kind];
2376 for (const uint8_t *p = Converter; *p; p += 2) {
2377 switch (*p) {
2378 default: llvm_unreachable("invalid conversion entry!");
2379 case CVT_Reg:
2380 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2381 Operands[*(p + 1)]->setConstraint("r");
2382 ++NumMCOperands;
2383 break;
2384 case CVT_Tied:
2385 ++NumMCOperands;
2386 break;
2387 case CVT_95_Reg:
2388 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2389 Operands[*(p + 1)]->setConstraint("r");
2390 NumMCOperands += 1;
2391 break;
2392 case CVT_95_addImmOperands:
2393 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2394 Operands[*(p + 1)]->setConstraint("m");
2395 NumMCOperands += 1;
2396 break;
2397 case CVT_95_addTailRelocSymOperands:
2398 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2399 Operands[*(p + 1)]->setConstraint("m");
2400 NumMCOperands += 1;
2401 break;
2402 case CVT_imm_95_8:
2403 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2404 Operands[*(p + 1)]->setConstraint("");
2405 ++NumMCOperands;
2406 break;
2407 case CVT_imm_95_13:
2408 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2409 Operands[*(p + 1)]->setConstraint("");
2410 ++NumMCOperands;
2411 break;
2412 case CVT_imm_95_5:
2413 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2414 Operands[*(p + 1)]->setConstraint("");
2415 ++NumMCOperands;
2416 break;
2417 case CVT_imm_95_1:
2418 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2419 Operands[*(p + 1)]->setConstraint("");
2420 ++NumMCOperands;
2421 break;
2422 case CVT_imm_95_10:
2423 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2424 Operands[*(p + 1)]->setConstraint("");
2425 ++NumMCOperands;
2426 break;
2427 case CVT_imm_95_11:
2428 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2429 Operands[*(p + 1)]->setConstraint("");
2430 ++NumMCOperands;
2431 break;
2432 case CVT_imm_95_12:
2433 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2434 Operands[*(p + 1)]->setConstraint("");
2435 ++NumMCOperands;
2436 break;
2437 case CVT_imm_95_3:
2438 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2439 Operands[*(p + 1)]->setConstraint("");
2440 ++NumMCOperands;
2441 break;
2442 case CVT_imm_95_2:
2443 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2444 Operands[*(p + 1)]->setConstraint("");
2445 ++NumMCOperands;
2446 break;
2447 case CVT_imm_95_4:
2448 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2449 Operands[*(p + 1)]->setConstraint("");
2450 ++NumMCOperands;
2451 break;
2452 case CVT_imm_95_0:
2453 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2454 Operands[*(p + 1)]->setConstraint("");
2455 ++NumMCOperands;
2456 break;
2457 case CVT_imm_95_9:
2458 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2459 Operands[*(p + 1)]->setConstraint("");
2460 ++NumMCOperands;
2461 break;
2462 case CVT_imm_95_6:
2463 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2464 Operands[*(p + 1)]->setConstraint("");
2465 ++NumMCOperands;
2466 break;
2467 case CVT_imm_95_14:
2468 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2469 Operands[*(p + 1)]->setConstraint("");
2470 ++NumMCOperands;
2471 break;
2472 case CVT_imm_95_7:
2473 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2474 Operands[*(p + 1)]->setConstraint("");
2475 ++NumMCOperands;
2476 break;
2477 case CVT_regG0:
2478 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2479 Operands[*(p + 1)]->setConstraint("m");
2480 ++NumMCOperands;
2481 break;
2482 case CVT_imm_95_15:
2483 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2484 Operands[*(p + 1)]->setConstraint("");
2485 ++NumMCOperands;
2486 break;
2487 case CVT_95_addCallTargetOperands:
2488 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2489 Operands[*(p + 1)]->setConstraint("m");
2490 NumMCOperands += 1;
2491 break;
2492 case CVT_regO7:
2493 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2494 Operands[*(p + 1)]->setConstraint("m");
2495 ++NumMCOperands;
2496 break;
2497 case CVT_95_addMEMriOperands:
2498 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2499 Operands[*(p + 1)]->setConstraint("m");
2500 NumMCOperands += 2;
2501 break;
2502 case CVT_95_addMEMrrOperands:
2503 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2504 Operands[*(p + 1)]->setConstraint("m");
2505 NumMCOperands += 2;
2506 break;
2507 case CVT_imm_95_128:
2508 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2509 Operands[*(p + 1)]->setConstraint("");
2510 ++NumMCOperands;
2511 break;
2512 case CVT_95_addASITagOperands:
2513 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2514 Operands[*(p + 1)]->setConstraint("m");
2515 NumMCOperands += 1;
2516 break;
2517 case CVT_imm_95_136:
2518 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2519 Operands[*(p + 1)]->setConstraint("");
2520 ++NumMCOperands;
2521 break;
2522 case CVT_regFCC0:
2523 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2524 Operands[*(p + 1)]->setConstraint("m");
2525 ++NumMCOperands;
2526 break;
2527 case CVT_95_addMembarTagOperands:
2528 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2529 Operands[*(p + 1)]->setConstraint("m");
2530 NumMCOperands += 1;
2531 break;
2532 case CVT_regASR27:
2533 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2534 Operands[*(p + 1)]->setConstraint("m");
2535 ++NumMCOperands;
2536 break;
2537 case CVT_95_addPrefetchTagOperands:
2538 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2539 Operands[*(p + 1)]->setConstraint("m");
2540 NumMCOperands += 1;
2541 break;
2542 case CVT_95_addShiftAmtImm5Operands:
2543 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2544 Operands[*(p + 1)]->setConstraint("m");
2545 NumMCOperands += 1;
2546 break;
2547 case CVT_95_addShiftAmtImm6Operands:
2548 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2549 Operands[*(p + 1)]->setConstraint("m");
2550 NumMCOperands += 1;
2551 break;
2552 }
2553 }
2554}
2555
2556namespace {
2557
2558/// MatchClassKind - The kinds of classes which participate in
2559/// instruction matching.
2560enum MatchClassKind {
2561 InvalidMatchClass = 0,
2562 OptionalMatchClass = 1,
2563 MCK__PCT_asi, // '%asi'
2564 MCK__PCT_xcc, // '%xcc'
2565 MCK__43_, // '+'
2566 MCK_1, // '1'
2567 MCK_3, // '3'
2568 MCK_5, // '5'
2569 MCK__91_, // '['
2570 MCK__93_, // ']'
2571 MCK_a, // 'a'
2572 MCK_pn, // 'pn'
2573 MCK_pt, // 'pt'
2574 MCK_LAST_TOKEN = MCK_pt,
2575 MCK_Reg12, // derived register class
2576 MCK_CPQ, // register class 'CPQ'
2577 MCK_CPSR, // register class 'CPSR'
2578 MCK_FCC0, // register class 'FCC0'
2579 MCK_FQ, // register class 'FQ'
2580 MCK_FSR, // register class 'FSR'
2581 MCK_G0, // register class 'G0'
2582 MCK_ICC, // register class 'ICC'
2583 MCK_PSR, // register class 'PSR'
2584 MCK_TBR, // register class 'TBR'
2585 MCK_WIM, // register class 'WIM'
2586 MCK_Reg25, // derived register class
2587 MCK_Reg24, // derived register class
2588 MCK_FCCRegs, // register class 'FCCRegs'
2589 MCK_GPRIncomingArg, // register class 'GPRIncomingArg'
2590 MCK_GPROutgoingArg, // register class 'GPROutgoingArg'
2591 MCK_LowQFPRegs, // register class 'LowQFPRegs'
2592 MCK_CoprocPair, // register class 'CoprocPair'
2593 MCK_IntPair, // register class 'IntPair'
2594 MCK_LowDFPRegs, // register class 'LowDFPRegs'
2595 MCK_QFPRegs, // register class 'QFPRegs'
2596 MCK_PRRegs, // register class 'PRRegs'
2597 MCK_CoprocRegs, // register class 'CoprocRegs'
2598 MCK_DFPRegs, // register class 'DFPRegs'
2599 MCK_FPRegs, // register class 'FPRegs'
2600 MCK_IntRegs, // register class 'IntRegs,I64Regs'
2601 MCK_ASRRegs, // register class 'ASRRegs'
2602 MCK_LAST_REGISTER = MCK_ASRRegs,
2603 MCK_Imm, // user defined class 'ImmAsmOperand'
2604 MCK_ASITag, // user defined class 'SparcASITagAsmOperand'
2605 MCK_CallTarget, // user defined class 'SparcCallTargetAsmOperand'
2606 MCK_MEMri, // user defined class 'SparcMEMriAsmOperand'
2607 MCK_MEMrr, // user defined class 'SparcMEMrrAsmOperand'
2608 MCK_MembarTag, // user defined class 'SparcMembarTagAsmOperand'
2609 MCK_PrefetchTag, // user defined class 'SparcPrefetchTagAsmOperand'
2610 MCK_ShiftAmtImm5, // user defined class 'anonymous_8744'
2611 MCK_ShiftAmtImm6, // user defined class 'anonymous_8745'
2612 MCK_TailRelocSymLoad_GOT, // user defined class 'anonymous_8746'
2613 MCK_TailRelocSymAdd_TLS, // user defined class 'anonymous_8747'
2614 MCK_TailRelocSymLoad_TLS, // user defined class 'anonymous_8748'
2615 MCK_TailRelocSymCall_TLS, // user defined class 'anonymous_8749'
2616 NumMatchClassKinds
2617};
2618
2619} // end anonymous namespace
2620
2621static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2622 return MCTargetAsmParser::Match_InvalidOperand;
2623}
2624
2625static MatchClassKind matchTokenString(StringRef Name) {
2626 switch (Name.size()) {
2627 default: break;
2628 case 1: // 7 strings to match.
2629 switch (Name[0]) {
2630 default: break;
2631 case '+': // 1 string to match.
2632 return MCK__43_; // "+"
2633 case '1': // 1 string to match.
2634 return MCK_1; // "1"
2635 case '3': // 1 string to match.
2636 return MCK_3; // "3"
2637 case '5': // 1 string to match.
2638 return MCK_5; // "5"
2639 case '[': // 1 string to match.
2640 return MCK__91_; // "["
2641 case ']': // 1 string to match.
2642 return MCK__93_; // "]"
2643 case 'a': // 1 string to match.
2644 return MCK_a; // "a"
2645 }
2646 break;
2647 case 2: // 2 strings to match.
2648 if (Name[0] != 'p')
2649 break;
2650 switch (Name[1]) {
2651 default: break;
2652 case 'n': // 1 string to match.
2653 return MCK_pn; // "pn"
2654 case 't': // 1 string to match.
2655 return MCK_pt; // "pt"
2656 }
2657 break;
2658 case 4: // 2 strings to match.
2659 if (Name[0] != '%')
2660 break;
2661 switch (Name[1]) {
2662 default: break;
2663 case 'a': // 1 string to match.
2664 if (memcmp(Name.data()+2, "si", 2) != 0)
2665 break;
2666 return MCK__PCT_asi; // "%asi"
2667 case 'x': // 1 string to match.
2668 if (memcmp(Name.data()+2, "cc", 2) != 0)
2669 break;
2670 return MCK__PCT_xcc; // "%xcc"
2671 }
2672 break;
2673 }
2674 return InvalidMatchClass;
2675}
2676
2677/// isSubclass - Compute whether \p A is a subclass of \p B.
2678static bool isSubclass(MatchClassKind A, MatchClassKind B) {
2679 if (A == B)
2680 return true;
2681
2682 [[maybe_unused]] static constexpr struct {
2683 uint32_t Offset;
2684 uint16_t Start;
2685 uint16_t Length;
2686 } Table[] = {
2687 {0, 0, 0},
2688 {0, 0, 0},
2689 {0, 0, 0},
2690 {0, 0, 0},
2691 {0, 0, 0},
2692 {0, 0, 0},
2693 {0, 0, 0},
2694 {0, 0, 0},
2695 {0, 0, 0},
2696 {0, 0, 0},
2697 {0, 0, 0},
2698 {0, 0, 0},
2699 {0, 0, 0},
2700 {0, 34, 6},
2701 {6, 0, 0},
2702 {6, 0, 0},
2703 {6, 26, 1},
2704 {7, 0, 0},
2705 {7, 0, 0},
2706 {7, 38, 1},
2707 {8, 0, 0},
2708 {8, 0, 0},
2709 {8, 0, 0},
2710 {8, 0, 0},
2711 {8, 31, 1},
2712 {9, 31, 1},
2713 {10, 0, 0},
2714 {10, 38, 1},
2715 {11, 38, 1},
2716 {12, 33, 1},
2717 {13, 0, 0},
2718 {13, 0, 0},
2719 {13, 36, 1},
2720 {14, 0, 0},
2721 {14, 0, 0},
2722 {14, 0, 0},
2723 {14, 0, 0},
2724 {14, 0, 0},
2725 {14, 0, 0},
2726 {14, 0, 0},
2727 {14, 0, 0},
2728 {14, 0, 0},
2729 {14, 0, 0},
2730 {14, 0, 0},
2731 {14, 0, 0},
2732 {14, 0, 0},
2733 {14, 0, 0},
2734 {14, 0, 0},
2735 {14, 0, 0},
2736 {14, 0, 0},
2737 {14, 0, 0},
2738 {14, 0, 0},
2739 {14, 0, 0},
2740 };
2741
2742 static constexpr uint8_t Data[] = {
2743 0xE1,
2744 0x3F,
2745 };
2746
2747 auto &Entry = Table[A];
2748 unsigned Idx = B - Entry.Start;
2749 if (Idx >= Entry.Length)
2750 return false;
2751 Idx += Entry.Offset;
2752 return (Data[Idx / 8] >> (Idx % 8)) & 1;
2753}
2754
2755static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
2756 SparcOperand &Operand = (SparcOperand &)GOp;
2757 if (Kind == InvalidMatchClass)
2758 return MCTargetAsmParser::Match_InvalidOperand;
2759
2760 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
2761 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
2762 MCTargetAsmParser::Match_Success :
2763 MCTargetAsmParser::Match_InvalidOperand;
2764
2765 switch (Kind) {
2766 default: break;
2767 case MCK_Imm: {
2768 DiagnosticPredicate DP(Operand.isImm());
2769 if (DP.isMatch())
2770 return MCTargetAsmParser::Match_Success;
2771 break;
2772 }
2773 case MCK_ASITag: {
2774 DiagnosticPredicate DP(Operand.isASITag());
2775 if (DP.isMatch())
2776 return MCTargetAsmParser::Match_Success;
2777 break;
2778 }
2779 case MCK_CallTarget: {
2780 DiagnosticPredicate DP(Operand.isCallTarget());
2781 if (DP.isMatch())
2782 return MCTargetAsmParser::Match_Success;
2783 break;
2784 }
2785 case MCK_MEMri: {
2786 DiagnosticPredicate DP(Operand.isMEMri());
2787 if (DP.isMatch())
2788 return MCTargetAsmParser::Match_Success;
2789 break;
2790 }
2791 case MCK_MEMrr: {
2792 DiagnosticPredicate DP(Operand.isMEMrr());
2793 if (DP.isMatch())
2794 return MCTargetAsmParser::Match_Success;
2795 break;
2796 }
2797 case MCK_MembarTag: {
2798 DiagnosticPredicate DP(Operand.isMembarTag());
2799 if (DP.isMatch())
2800 return MCTargetAsmParser::Match_Success;
2801 break;
2802 }
2803 case MCK_PrefetchTag: {
2804 DiagnosticPredicate DP(Operand.isPrefetchTag());
2805 if (DP.isMatch())
2806 return MCTargetAsmParser::Match_Success;
2807 break;
2808 }
2809 case MCK_ShiftAmtImm5: {
2810 DiagnosticPredicate DP(Operand.isShiftAmtImm5());
2811 if (DP.isMatch())
2812 return MCTargetAsmParser::Match_Success;
2813 break;
2814 }
2815 case MCK_ShiftAmtImm6: {
2816 DiagnosticPredicate DP(Operand.isShiftAmtImm6());
2817 if (DP.isMatch())
2818 return MCTargetAsmParser::Match_Success;
2819 break;
2820 }
2821 case MCK_TailRelocSymLoad_GOT: {
2822 DiagnosticPredicate DP(Operand.isTailRelocSym());
2823 if (DP.isMatch())
2824 return MCTargetAsmParser::Match_Success;
2825 break;
2826 }
2827 case MCK_TailRelocSymAdd_TLS: {
2828 DiagnosticPredicate DP(Operand.isTailRelocSym());
2829 if (DP.isMatch())
2830 return MCTargetAsmParser::Match_Success;
2831 break;
2832 }
2833 case MCK_TailRelocSymLoad_TLS: {
2834 DiagnosticPredicate DP(Operand.isTailRelocSym());
2835 if (DP.isMatch())
2836 return MCTargetAsmParser::Match_Success;
2837 break;
2838 }
2839 case MCK_TailRelocSymCall_TLS: {
2840 DiagnosticPredicate DP(Operand.isTailRelocSym());
2841 if (DP.isMatch())
2842 return MCTargetAsmParser::Match_Success;
2843 break;
2844 }
2845 } // end switch (Kind)
2846
2847 if (Operand.isReg()) {
2848 static constexpr uint16_t Table[SP::NUM_TARGET_REGS] = {
2849 InvalidMatchClass,
2850 MCK_PRRegs,
2851 MCK_PRRegs,
2852 MCK_PRRegs,
2853 MCK_CPQ,
2854 MCK_CPSR,
2855 MCK_PRRegs,
2856 MCK_FQ,
2857 MCK_FSR,
2858 MCK_PRRegs,
2859 MCK_ICC,
2860 MCK_PRRegs,
2861 MCK_PRRegs,
2862 MCK_PSR,
2863 MCK_PRRegs,
2864 MCK_PRRegs,
2865 MCK_TBR,
2866 MCK_Reg12,
2867 MCK_PRRegs,
2868 MCK_PRRegs,
2869 MCK_PRRegs,
2870 MCK_PRRegs,
2871 MCK_PRRegs,
2872 MCK_PRRegs,
2873 MCK_WIM,
2874 MCK_PRRegs,
2875 MCK_ASRRegs,
2876 MCK_ASRRegs,
2877 MCK_ASRRegs,
2878 MCK_ASRRegs,
2879 MCK_ASRRegs,
2880 MCK_ASRRegs,
2881 MCK_ASRRegs,
2882 MCK_ASRRegs,
2883 MCK_ASRRegs,
2884 MCK_ASRRegs,
2885 MCK_ASRRegs,
2886 MCK_ASRRegs,
2887 MCK_ASRRegs,
2888 MCK_ASRRegs,
2889 MCK_ASRRegs,
2890 MCK_ASRRegs,
2891 MCK_ASRRegs,
2892 MCK_ASRRegs,
2893 MCK_ASRRegs,
2894 MCK_ASRRegs,
2895 MCK_ASRRegs,
2896 MCK_ASRRegs,
2897 MCK_ASRRegs,
2898 MCK_ASRRegs,
2899 MCK_ASRRegs,
2900 MCK_ASRRegs,
2901 MCK_ASRRegs,
2902 MCK_ASRRegs,
2903 MCK_ASRRegs,
2904 MCK_ASRRegs,
2905 MCK_ASRRegs,
2906 MCK_ASRRegs,
2907 MCK_CoprocRegs,
2908 MCK_CoprocRegs,
2909 MCK_CoprocRegs,
2910 MCK_CoprocRegs,
2911 MCK_CoprocRegs,
2912 MCK_CoprocRegs,
2913 MCK_CoprocRegs,
2914 MCK_CoprocRegs,
2915 MCK_CoprocRegs,
2916 MCK_CoprocRegs,
2917 MCK_CoprocRegs,
2918 MCK_CoprocRegs,
2919 MCK_CoprocRegs,
2920 MCK_CoprocRegs,
2921 MCK_CoprocRegs,
2922 MCK_CoprocRegs,
2923 MCK_CoprocRegs,
2924 MCK_CoprocRegs,
2925 MCK_CoprocRegs,
2926 MCK_CoprocRegs,
2927 MCK_CoprocRegs,
2928 MCK_CoprocRegs,
2929 MCK_CoprocRegs,
2930 MCK_CoprocRegs,
2931 MCK_CoprocRegs,
2932 MCK_CoprocRegs,
2933 MCK_CoprocRegs,
2934 MCK_CoprocRegs,
2935 MCK_CoprocRegs,
2936 MCK_CoprocRegs,
2937 MCK_CoprocRegs,
2938 MCK_CoprocRegs,
2939 MCK_LowDFPRegs,
2940 MCK_LowDFPRegs,
2941 MCK_LowDFPRegs,
2942 MCK_LowDFPRegs,
2943 MCK_LowDFPRegs,
2944 MCK_LowDFPRegs,
2945 MCK_LowDFPRegs,
2946 MCK_LowDFPRegs,
2947 MCK_LowDFPRegs,
2948 MCK_LowDFPRegs,
2949 MCK_LowDFPRegs,
2950 MCK_LowDFPRegs,
2951 MCK_LowDFPRegs,
2952 MCK_LowDFPRegs,
2953 MCK_LowDFPRegs,
2954 MCK_LowDFPRegs,
2955 MCK_DFPRegs,
2956 MCK_DFPRegs,
2957 MCK_DFPRegs,
2958 MCK_DFPRegs,
2959 MCK_DFPRegs,
2960 MCK_DFPRegs,
2961 MCK_DFPRegs,
2962 MCK_DFPRegs,
2963 MCK_DFPRegs,
2964 MCK_DFPRegs,
2965 MCK_DFPRegs,
2966 MCK_DFPRegs,
2967 MCK_DFPRegs,
2968 MCK_DFPRegs,
2969 MCK_DFPRegs,
2970 MCK_DFPRegs,
2971 MCK_FPRegs,
2972 MCK_FPRegs,
2973 MCK_FPRegs,
2974 MCK_FPRegs,
2975 MCK_FPRegs,
2976 MCK_FPRegs,
2977 MCK_FPRegs,
2978 MCK_FPRegs,
2979 MCK_FPRegs,
2980 MCK_FPRegs,
2981 MCK_FPRegs,
2982 MCK_FPRegs,
2983 MCK_FPRegs,
2984 MCK_FPRegs,
2985 MCK_FPRegs,
2986 MCK_FPRegs,
2987 MCK_FPRegs,
2988 MCK_FPRegs,
2989 MCK_FPRegs,
2990 MCK_FPRegs,
2991 MCK_FPRegs,
2992 MCK_FPRegs,
2993 MCK_FPRegs,
2994 MCK_FPRegs,
2995 MCK_FPRegs,
2996 MCK_FPRegs,
2997 MCK_FPRegs,
2998 MCK_FPRegs,
2999 MCK_FPRegs,
3000 MCK_FPRegs,
3001 MCK_FPRegs,
3002 MCK_FPRegs,
3003 MCK_FCC0,
3004 MCK_FCCRegs,
3005 MCK_FCCRegs,
3006 MCK_FCCRegs,
3007 MCK_G0,
3008 MCK_IntRegs,
3009 MCK_IntRegs,
3010 MCK_IntRegs,
3011 MCK_IntRegs,
3012 MCK_IntRegs,
3013 MCK_IntRegs,
3014 MCK_IntRegs,
3015 MCK_GPRIncomingArg,
3016 MCK_GPRIncomingArg,
3017 MCK_GPRIncomingArg,
3018 MCK_GPRIncomingArg,
3019 MCK_GPRIncomingArg,
3020 MCK_GPRIncomingArg,
3021 MCK_IntRegs,
3022 MCK_IntRegs,
3023 MCK_IntRegs,
3024 MCK_IntRegs,
3025 MCK_IntRegs,
3026 MCK_IntRegs,
3027 MCK_IntRegs,
3028 MCK_IntRegs,
3029 MCK_IntRegs,
3030 MCK_IntRegs,
3031 MCK_GPROutgoingArg,
3032 MCK_GPROutgoingArg,
3033 MCK_GPROutgoingArg,
3034 MCK_GPROutgoingArg,
3035 MCK_GPROutgoingArg,
3036 MCK_GPROutgoingArg,
3037 MCK_IntRegs,
3038 MCK_IntRegs,
3039 MCK_LowQFPRegs,
3040 MCK_LowQFPRegs,
3041 MCK_LowQFPRegs,
3042 MCK_LowQFPRegs,
3043 MCK_LowQFPRegs,
3044 MCK_LowQFPRegs,
3045 MCK_LowQFPRegs,
3046 MCK_LowQFPRegs,
3047 MCK_QFPRegs,
3048 MCK_QFPRegs,
3049 MCK_QFPRegs,
3050 MCK_QFPRegs,
3051 MCK_QFPRegs,
3052 MCK_QFPRegs,
3053 MCK_QFPRegs,
3054 MCK_QFPRegs,
3055 MCK_CoprocPair,
3056 MCK_CoprocPair,
3057 MCK_CoprocPair,
3058 MCK_CoprocPair,
3059 MCK_CoprocPair,
3060 MCK_CoprocPair,
3061 MCK_CoprocPair,
3062 MCK_CoprocPair,
3063 MCK_CoprocPair,
3064 MCK_CoprocPair,
3065 MCK_CoprocPair,
3066 MCK_CoprocPair,
3067 MCK_CoprocPair,
3068 MCK_CoprocPair,
3069 MCK_CoprocPair,
3070 MCK_CoprocPair,
3071 MCK_IntPair,
3072 MCK_IntPair,
3073 MCK_IntPair,
3074 MCK_IntPair,
3075 MCK_Reg25,
3076 MCK_Reg25,
3077 MCK_Reg25,
3078 MCK_IntPair,
3079 MCK_IntPair,
3080 MCK_IntPair,
3081 MCK_IntPair,
3082 MCK_IntPair,
3083 MCK_Reg24,
3084 MCK_Reg24,
3085 MCK_Reg24,
3086 MCK_IntPair,
3087 };
3088
3089 MCRegister Reg = Operand.getReg();
3090 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
3091 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
3092 getDiagKindFromRegisterClass(Kind);
3093 }
3094
3095 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
3096 return getDiagKindFromRegisterClass(Kind);
3097
3098 return MCTargetAsmParser::Match_InvalidOperand;
3099}
3100
3101#ifndef NDEBUG
3102const char *getMatchClassName(MatchClassKind Kind) {
3103 switch (Kind) {
3104 case InvalidMatchClass: return "InvalidMatchClass";
3105 case OptionalMatchClass: return "OptionalMatchClass";
3106 case MCK__PCT_asi: return "MCK__PCT_asi";
3107 case MCK__PCT_xcc: return "MCK__PCT_xcc";
3108 case MCK__43_: return "MCK__43_";
3109 case MCK_1: return "MCK_1";
3110 case MCK_3: return "MCK_3";
3111 case MCK_5: return "MCK_5";
3112 case MCK__91_: return "MCK__91_";
3113 case MCK__93_: return "MCK__93_";
3114 case MCK_a: return "MCK_a";
3115 case MCK_pn: return "MCK_pn";
3116 case MCK_pt: return "MCK_pt";
3117 case MCK_Reg12: return "MCK_Reg12";
3118 case MCK_CPQ: return "MCK_CPQ";
3119 case MCK_CPSR: return "MCK_CPSR";
3120 case MCK_FCC0: return "MCK_FCC0";
3121 case MCK_FQ: return "MCK_FQ";
3122 case MCK_FSR: return "MCK_FSR";
3123 case MCK_G0: return "MCK_G0";
3124 case MCK_ICC: return "MCK_ICC";
3125 case MCK_PSR: return "MCK_PSR";
3126 case MCK_TBR: return "MCK_TBR";
3127 case MCK_WIM: return "MCK_WIM";
3128 case MCK_Reg25: return "MCK_Reg25";
3129 case MCK_Reg24: return "MCK_Reg24";
3130 case MCK_FCCRegs: return "MCK_FCCRegs";
3131 case MCK_GPRIncomingArg: return "MCK_GPRIncomingArg";
3132 case MCK_GPROutgoingArg: return "MCK_GPROutgoingArg";
3133 case MCK_LowQFPRegs: return "MCK_LowQFPRegs";
3134 case MCK_CoprocPair: return "MCK_CoprocPair";
3135 case MCK_IntPair: return "MCK_IntPair";
3136 case MCK_LowDFPRegs: return "MCK_LowDFPRegs";
3137 case MCK_QFPRegs: return "MCK_QFPRegs";
3138 case MCK_PRRegs: return "MCK_PRRegs";
3139 case MCK_CoprocRegs: return "MCK_CoprocRegs";
3140 case MCK_DFPRegs: return "MCK_DFPRegs";
3141 case MCK_FPRegs: return "MCK_FPRegs";
3142 case MCK_IntRegs: return "MCK_IntRegs";
3143 case MCK_ASRRegs: return "MCK_ASRRegs";
3144 case MCK_Imm: return "MCK_Imm";
3145 case MCK_ASITag: return "MCK_ASITag";
3146 case MCK_CallTarget: return "MCK_CallTarget";
3147 case MCK_MEMri: return "MCK_MEMri";
3148 case MCK_MEMrr: return "MCK_MEMrr";
3149 case MCK_MembarTag: return "MCK_MembarTag";
3150 case MCK_PrefetchTag: return "MCK_PrefetchTag";
3151 case MCK_ShiftAmtImm5: return "MCK_ShiftAmtImm5";
3152 case MCK_ShiftAmtImm6: return "MCK_ShiftAmtImm6";
3153 case MCK_TailRelocSymLoad_GOT: return "MCK_TailRelocSymLoad_GOT";
3154 case MCK_TailRelocSymAdd_TLS: return "MCK_TailRelocSymAdd_TLS";
3155 case MCK_TailRelocSymLoad_TLS: return "MCK_TailRelocSymLoad_TLS";
3156 case MCK_TailRelocSymCall_TLS: return "MCK_TailRelocSymCall_TLS";
3157 case NumMatchClassKinds: return "NumMatchClassKinds";
3158 }
3159 llvm_unreachable("unhandled MatchClassKind!");
3160}
3161
3162#endif // NDEBUG
3163FeatureBitset SparcAsmParser::
3164ComputeAvailableFeatures(const FeatureBitset &FB) const {
3165 FeatureBitset Features;
3166 if (FB[Sparc::FeatureV9])
3167 Features.set(Feature_Is64BitBit);
3168 if (FB[Sparc::FeatureSoftMulDiv])
3169 Features.set(Feature_UseSoftMulDivBit);
3170 if (FB[Sparc::FeatureV9])
3171 Features.set(Feature_HasV9Bit);
3172 if (FB[Sparc::FeatureVIS])
3173 Features.set(Feature_HasVISBit);
3174 if (FB[Sparc::FeatureVIS2])
3175 Features.set(Feature_HasVIS2Bit);
3176 if (FB[Sparc::FeatureVIS3])
3177 Features.set(Feature_HasVIS3Bit);
3178 if (FB[Sparc::FeatureUA2005])
3179 Features.set(Feature_HasUA2005Bit);
3180 if (FB[Sparc::FeatureUA2007])
3181 Features.set(Feature_HasUA2007Bit);
3182 if (FB[Sparc::FeatureOSA2011])
3183 Features.set(Feature_HasOSA2011Bit);
3184 if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
3185 Features.set(Feature_HasCASABit);
3186 if (FB[Sparc::FeaturePWRPSR])
3187 Features.set(Feature_HasPWRPSRBit);
3188 return Features;
3189}
3190
3191static bool checkAsmTiedOperandConstraints(const SparcAsmParser&AsmParser,
3192 unsigned Kind, const OperandVector &Operands,
3193 uint64_t &ErrorInfo) {
3194 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
3195 const uint8_t *Converter = ConversionTable[Kind];
3196 for (const uint8_t *p = Converter; *p; p += 2) {
3197 switch (*p) {
3198 case CVT_Tied: {
3199 unsigned OpIdx = *(p + 1);
3200 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
3201 std::begin(TiedAsmOperandTable)) &&
3202 "Tied operand not found");
3203 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
3204 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
3205 if (OpndNum1 != OpndNum2) {
3206 auto &SrcOp1 = Operands[OpndNum1];
3207 auto &SrcOp2 = Operands[OpndNum2];
3208 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
3209 ErrorInfo = OpndNum2;
3210 return false;
3211 }
3212 }
3213 break;
3214 }
3215 default:
3216 break;
3217 }
3218 }
3219 return true;
3220}
3221
3222static const char MnemonicTable[] =
3223 "\000\003add\005addcc\004addx\005addxc\006addxcc\007addxccc\talignaddr\n"
3224 "alignaddrl\010allclean\003and\005andcc\004andn\006andncc\007array16\007"
3225 "array32\006array8\001b\002ba\003bcc\004bclr\003bcs\002be\003beq\002bg\003"
3226 "bge\004bgeu\003bgt\003bgu\002bl\003ble\004bleu\003blt\003blu\005bmask\002"
3227 "bn\003bne\004bneg\003bnz\004bpos\002br\003bre\005brgez\004brgz\005brlez"
3228 "\004brlz\004brne\004brnz\003brz\004bset\010bshuffle\004btog\004btst\003"
3229 "bvc\003bvs\002bz\004call\003cas\004casa\004casl\004casx\005casxa\005cas"
3230 "xl\002cb\003cb0\004cb01\005cb012\005cb013\004cb02\005cb023\004cb03\003c"
3231 "b1\004cb12\005cb123\004cb13\003cb2\004cb23\003cb3\003cba\003cbn\003clr\004"
3232 "clrb\004clrh\007cmask16\007cmask32\006cmask8\003cmp\003cwb\005cwbcc\005"
3233 "cwbcs\004cwbe\004cwbg\005cwbge\006cwbgeu\005cwbgu\004cwbl\005cwble\006c"
3234 "wbleu\005cwblu\005cwbne\006cwbneg\006cwbpos\005cwbvc\005cwbvs\003cxb\005"
3235 "cxbcc\005cxbcs\004cxbe\004cxbg\005cxbge\006cxbgeu\005cxbgu\004cxbl\005c"
3236 "xble\006cxbleu\005cxblu\005cxbne\006cxbneg\006cxbpos\005cxbvc\005cxbvs\003"
3237 "dec\005deccc\004done\006edge16\007edge16l\010edge16ln\007edge16n\006edg"
3238 "e32\007edge32l\010edge32ln\007edge32n\005edge8\006edge8l\007edge8ln\006"
3239 "edge8n\005fabsd\005fabsq\005fabss\005faddd\005faddq\005fadds\nfaligndat"
3240 "a\004fand\010fandnot1\tfandnot1s\010fandnot2\tfandnot2s\005fands\002fb\003"
3241 "fba\003fbe\003fbg\004fbge\003fbl\004fble\004fblg\003fbn\004fbne\004fbnz"
3242 "\003fbo\003fbu\004fbue\004fbug\005fbuge\004fbul\005fbule\003fbz\010fchk"
3243 "sm16\005fcmpd\006fcmped\006fcmpeq\010fcmpeq16\010fcmpeq32\006fcmpes\010"
3244 "fcmpgt16\010fcmpgt32\010fcmple16\010fcmple32\010fcmpne16\010fcmpne32\005"
3245 "fcmpq\005fcmps\005fdivd\005fdivq\005fdivs\006fdmulq\005fdtoi\005fdtoq\005"
3246 "fdtos\005fdtox\007fexpand\006fhaddd\006fhadds\006fhsubd\006fhsubs\005fi"
3247 "tod\005fitoq\005fitos\006flcmpd\006flcmps\005flush\006flushw\006fmaddd\006"
3248 "fmadds\007fmean16\005fmovd\006fmovda\007fmovdcc\007fmovdcs\006fmovde\007"
3249 "fmovdeq\006fmovdg\007fmovdge\010fmovdgeu\007fmovdgt\007fmovdgu\006fmovd"
3250 "l\007fmovdle\010fmovdleu\007fmovdlg\007fmovdlt\007fmovdlu\006fmovdn\007"
3251 "fmovdne\010fmovdneg\007fmovdnz\006fmovdo\010fmovdpos\006fmovdu\007fmovd"
3252 "ue\007fmovdug\010fmovduge\007fmovdul\010fmovdule\007fmovdvc\007fmovdvs\006"
3253 "fmovdz\005fmovq\006fmovqa\007fmovqcc\007fmovqcs\006fmovqe\007fmovqeq\006"
3254 "fmovqg\007fmovqge\010fmovqgeu\007fmovqgt\007fmovqgu\006fmovql\007fmovql"
3255 "e\010fmovqleu\007fmovqlg\007fmovqlt\007fmovqlu\006fmovqn\007fmovqne\010"
3256 "fmovqneg\007fmovqnz\006fmovqo\010fmovqpos\006fmovqu\007fmovque\007fmovq"
3257 "ug\010fmovquge\007fmovqul\010fmovqule\007fmovqvc\007fmovqvs\006fmovqz\006"
3258 "fmovrd\007fmovrde\tfmovrdgez\010fmovrdgz\tfmovrdlez\010fmovrdlz\010fmov"
3259 "rdne\010fmovrdnz\007fmovrdz\006fmovrq\007fmovrqe\tfmovrqgez\010fmovrqgz"
3260 "\tfmovrqlez\010fmovrqlz\010fmovrqne\010fmovrqnz\007fmovrqz\006fmovrs\007"
3261 "fmovrse\tfmovrsgez\010fmovrsgz\tfmovrslez\010fmovrslz\010fmovrsne\010fm"
3262 "ovrsnz\007fmovrsz\005fmovs\006fmovsa\007fmovscc\007fmovscs\006fmovse\007"
3263 "fmovseq\006fmovsg\007fmovsge\010fmovsgeu\007fmovsgt\007fmovsgu\006fmovs"
3264 "l\007fmovsle\010fmovsleu\007fmovslg\007fmovslt\007fmovslu\006fmovsn\007"
3265 "fmovsne\010fmovsneg\007fmovsnz\006fmovso\010fmovspos\006fmovsu\007fmovs"
3266 "ue\007fmovsug\010fmovsuge\007fmovsul\010fmovsule\007fmovsvc\007fmovsvs\006"
3267 "fmovsz\006fmsubd\006fmsubs\nfmul8sux16\nfmul8ulx16\010fmul8x16\nfmul8x1"
3268 "6al\nfmul8x16au\005fmuld\013fmuld8sux16\013fmuld8ulx16\005fmulq\005fmul"
3269 "s\006fnaddd\006fnadds\005fnand\006fnands\005fnegd\005fnegq\005fnegs\007"
3270 "fnhaddd\007fnhadds\007fnmaddd\007fnmadds\007fnmsubd\007fnmsubs\006fnmul"
3271 "d\006fnmuls\004fnor\005fnors\005fnot1\006fnot1s\005fnot2\006fnot2s\007f"
3272 "nsmuld\004fone\005fones\003for\007fornot1\010fornot1s\007fornot2\010for"
3273 "not2s\004fors\007fpack16\007fpack32\010fpackfix\007fpadd16\010fpadd16s\007"
3274 "fpadd32\010fpadd32s\007fpadd64\007fpmaddx\tfpmaddxhi\007fpmerge\007fpsu"
3275 "b16\010fpsub16s\007fpsub32\010fpsub32s\005fqtod\005fqtoi\005fqtos\005fq"
3276 "tox\007fslas16\007fslas32\006fsll16\006fsll32\006fsmuld\006fsqrtd\006fs"
3277 "qrtq\006fsqrts\006fsra16\006fsra32\005fsrc1\006fsrc1s\005fsrc2\006fsrc2"
3278 "s\006fsrl16\006fsrl32\005fstod\005fstoi\005fstoq\005fstox\005fsubd\005f"
3279 "subq\005fsubs\005fxnor\006fxnors\004fxor\005fxors\005fxtod\005fxtoq\005"
3280 "fxtos\005fzero\006fzeros\003inc\005inccc\006invalw\003jmp\004jmpl\002ld"
3281 "\003lda\003ldd\004ldda\003ldq\004ldqa\004ldsb\005ldsba\004ldsh\005ldsha"
3282 "\006ldstub\007ldstuba\004ldsw\005ldswa\004ldub\005lduba\004lduh\005lduh"
3283 "a\003ldx\004ldxa\005lzcnt\006membar\003mov\004mova\005movcc\005movcs\007"
3284 "movdtox\004move\005moveq\004movg\005movge\006movgeu\005movgt\005movgu\004"
3285 "movl\005movle\006movleu\005movlg\005movlt\005movlu\004movn\005movne\006"
3286 "movneg\005movnz\004movo\006movpos\004movr\005movre\007movrgez\006movrgz"
3287 "\007movrlez\006movrlz\006movrne\006movrnz\005movrz\010movstosw\010movst"
3288 "ouw\004movu\005movue\005movug\006movuge\005movul\006movule\005movvc\005"
3289 "movvs\007movwtos\007movxtod\004movz\006mulscc\004mulx\003neg\003nop\007"
3290 "normalw\003not\002or\004orcc\003orn\005orncc\006otherw\005pause\005pdis"
3291 "t\006pdistn\004popc\010prefetch\tprefetcha\003pwr\002rd\004rdpr\007rest"
3292 "ore\010restored\003ret\004retl\005retry\004rett\004save\005saved\004sdi"
3293 "v\006sdivcc\005sdivx\003set\005sethi\005setsw\004setx\010shutdown\004si"
3294 "am\005signx\003sir\003sll\004sllx\004smac\004smul\006smulcc\003sra\004s"
3295 "rax\003srl\004srlx\002st\003sta\003stb\004stba\005stbar\003std\004stda\003"
3296 "sth\004stha\003stq\004stqa\003stx\004stxa\003sub\005subcc\004subx\006su"
3297 "bxcc\004swap\005swapa\001t\002ta\006taddcc\010taddcctv\003tcc\003tcs\002"
3298 "te\003teq\002tg\003tge\004tgeu\003tgt\003tgu\002tl\003tle\004tleu\003tl"
3299 "t\003tlu\002tn\003tne\004tneg\003tnz\004tpos\003tst\006tsubcc\010tsubcc"
3300 "tv\003tvc\003tvs\002tz\004udiv\006udivcc\005udivx\004umac\004umul\006um"
3301 "ulcc\007umulxhi\005unimp\002wr\004wrpr\005xmulx\007xmulxhi\004xnor\006x"
3302 "norcc\003xor\005xorcc";
3303
3304// Feature bitsets.
3305enum : uint8_t {
3306 AMFBS_None,
3307 AMFBS_HasCASA,
3308 AMFBS_HasOSA2011,
3309 AMFBS_HasPWRPSR,
3310 AMFBS_HasUA2005,
3311 AMFBS_HasUA2007,
3312 AMFBS_HasV9,
3313 AMFBS_HasVIS,
3314 AMFBS_HasVIS2,
3315 AMFBS_HasVIS3,
3316 AMFBS_Is64Bit,
3317 AMFBS_Is64Bit_HasV9,
3318};
3319
3320static constexpr FeatureBitset FeatureBitsets[] = {
3321 {}, // AMFBS_None
3322 {Feature_HasCASABit, },
3323 {Feature_HasOSA2011Bit, },
3324 {Feature_HasPWRPSRBit, },
3325 {Feature_HasUA2005Bit, },
3326 {Feature_HasUA2007Bit, },
3327 {Feature_HasV9Bit, },
3328 {Feature_HasVISBit, },
3329 {Feature_HasVIS2Bit, },
3330 {Feature_HasVIS3Bit, },
3331 {Feature_Is64BitBit, },
3332 {Feature_Is64BitBit, Feature_HasV9Bit, },
3333};
3334
3335namespace {
3336 struct MatchEntry {
3337 uint16_t Mnemonic;
3338 uint16_t Opcode;
3339 uint16_t ConvertFn;
3340 uint8_t RequiredFeaturesIdx;
3341 uint8_t Classes[6];
3342 StringRef getMnemonic() const {
3343 return StringRef(MnemonicTable + Mnemonic + 1,
3344 MnemonicTable[Mnemonic]);
3345 }
3346 };
3347
3348 // Predicate for searching for an opcode.
3349 struct LessOpcode {
3350 bool operator()(const MatchEntry &LHS, StringRef RHS) {
3351 return LHS.getMnemonic() < RHS;
3352 }
3353 bool operator()(StringRef LHS, const MatchEntry &RHS) {
3354 return LHS < RHS.getMnemonic();
3355 }
3356 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
3357 return LHS.getMnemonic() < RHS.getMnemonic();
3358 }
3359 };
3360} // end anonymous namespace
3361
3362static const MatchEntry MatchTable0[] = {
3363 { 1 /* add */, SP::ADDrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3364 { 1 /* add */, SP::ADDri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3365 { 1 /* add */, SP::TLS_ADDrr, Convert__Reg1_2__Reg1_0__Reg1_1__TailRelocSymAdd_TLS1_3, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs, MCK_TailRelocSymAdd_TLS }, },
3366 { 5 /* addcc */, SP::ADDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3367 { 5 /* addcc */, SP::ADDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3368 { 11 /* addx */, SP::ADDCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3369 { 11 /* addx */, SP::ADDCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3370 { 11 /* addx */, SP::ADDCri, Convert__Reg1_2__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK_IntRegs }, },
3371 { 16 /* addxc */, SP::ADDXC, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3372 { 22 /* addxcc */, SP::ADDErr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3373 { 22 /* addxcc */, SP::ADDEri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3374 { 29 /* addxccc */, SP::ADDXCCC, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3375 { 37 /* alignaddr */, SP::ALIGNADDR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3376 { 47 /* alignaddrl */, SP::ALIGNADDRL, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3377 { 58 /* allclean */, SP::ALLCLEAN, Convert_NoOperands, AMFBS_HasUA2005, { }, },
3378 { 67 /* and */, SP::ANDrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3379 { 67 /* and */, SP::ANDri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3380 { 71 /* andcc */, SP::ANDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3381 { 71 /* andcc */, SP::ANDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3382 { 77 /* andn */, SP::ANDNrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3383 { 77 /* andn */, SP::ANDNri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3384 { 82 /* andncc */, SP::ANDNCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3385 { 82 /* andncc */, SP::ANDNCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3386 { 89 /* array16 */, SP::ARRAY16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3387 { 97 /* array32 */, SP::ARRAY32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3388 { 105 /* array8 */, SP::ARRAY8, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3389 { 112 /* b */, SP::BCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
3390 { 112 /* b */, SP::BPXCC, Convert__Imm1_1__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3391 { 112 /* b */, SP::BCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
3392 { 112 /* b */, SP::BPICC, Convert__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3393 { 112 /* b */, SP::BCOND, Convert__Imm1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Imm }, },
3394 { 112 /* b */, SP::BPXCCA, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3395 { 112 /* b */, SP::BPICCA, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3396 { 112 /* b */, SP::BPXCCNT, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3397 { 112 /* b */, SP::BPICCNT, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3398 { 112 /* b */, SP::BPXCC, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3399 { 112 /* b */, SP::BPICC, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3400 { 112 /* b */, SP::BPXCC, Convert__Imm1_2__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_Imm }, },
3401 { 112 /* b */, SP::BCONDA, Convert__Imm1_2__Imm1_0, AMFBS_None, { MCK_Imm, MCK_a, MCK_Imm }, },
3402 { 112 /* b */, SP::BPICC, Convert__Imm1_2__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_Imm }, },
3403 { 112 /* b */, SP::BPXCCANT, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3404 { 112 /* b */, SP::BPICCANT, Convert__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3405 { 112 /* b */, SP::BPXCCA, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3406 { 112 /* b */, SP::BPICCA, Convert__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3407 { 112 /* b */, SP::BPXCCA, Convert__Imm1_3__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3408 { 112 /* b */, SP::BPICCA, Convert__Imm1_3__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_ICC, MCK_Imm }, },
3409 { 112 /* b */, SP::BPXCCNT, Convert__Imm1_3__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3410 { 112 /* b */, SP::BPICCNT, Convert__Imm1_3__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_pn, MCK_ICC, MCK_Imm }, },
3411 { 112 /* b */, SP::BPXCCANT, Convert__Imm1_4__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3412 { 112 /* b */, SP::BPICCANT, Convert__Imm1_4__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3413 { 114 /* ba */, SP::BA, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
3414 { 114 /* ba */, SP::BCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
3415 { 114 /* ba */, SP::BPXCC, Convert__Imm1_1__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3416 { 114 /* ba */, SP::BCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
3417 { 114 /* ba */, SP::BPICC, Convert__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3418 { 114 /* ba */, SP::BPXCCA, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3419 { 114 /* ba */, SP::BPICCA, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3420 { 114 /* ba */, SP::BPXCCNT, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3421 { 114 /* ba */, SP::BPICCNT, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3422 { 114 /* ba */, SP::BPXCC, Convert__Imm1_2__imm_95_8, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3423 { 114 /* ba */, SP::BPICC, Convert__Imm1_2__imm_95_8, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3424 { 114 /* ba */, SP::BPXCCANT, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3425 { 114 /* ba */, SP::BPICCANT, Convert__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3426 { 114 /* ba */, SP::BPXCCA, Convert__Imm1_3__imm_95_8, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3427 { 114 /* ba */, SP::BPICCA, Convert__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3428 { 117 /* bcc */, SP::BCOND, Convert__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
3429 { 117 /* bcc */, SP::BPXCC, Convert__Imm1_1__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3430 { 117 /* bcc */, SP::BCONDA, Convert__Imm1_1__imm_95_13, AMFBS_None, { MCK_a, MCK_Imm }, },
3431 { 117 /* bcc */, SP::BPICC, Convert__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3432 { 117 /* bcc */, SP::BPXCCA, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3433 { 117 /* bcc */, SP::BPICCA, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3434 { 117 /* bcc */, SP::BPXCCNT, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3435 { 117 /* bcc */, SP::BPICCNT, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3436 { 117 /* bcc */, SP::BPXCC, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3437 { 117 /* bcc */, SP::BPICC, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3438 { 117 /* bcc */, SP::BPXCCANT, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3439 { 117 /* bcc */, SP::BPICCANT, Convert__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3440 { 117 /* bcc */, SP::BPXCCA, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3441 { 117 /* bcc */, SP::BPICCA, Convert__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3442 { 121 /* bclr */, SP::ANDNrr, Convert__Reg1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
3443 { 121 /* bclr */, SP::ANDNri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
3444 { 126 /* bcs */, SP::BCOND, Convert__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
3445 { 126 /* bcs */, SP::BPXCC, Convert__Imm1_1__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3446 { 126 /* bcs */, SP::BCONDA, Convert__Imm1_1__imm_95_5, AMFBS_None, { MCK_a, MCK_Imm }, },
3447 { 126 /* bcs */, SP::BPICC, Convert__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3448 { 126 /* bcs */, SP::BPXCCA, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3449 { 126 /* bcs */, SP::BPICCA, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3450 { 126 /* bcs */, SP::BPXCCNT, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3451 { 126 /* bcs */, SP::BPICCNT, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3452 { 126 /* bcs */, SP::BPXCC, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3453 { 126 /* bcs */, SP::BPICC, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3454 { 126 /* bcs */, SP::BPXCCANT, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3455 { 126 /* bcs */, SP::BPICCANT, Convert__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3456 { 126 /* bcs */, SP::BPXCCA, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3457 { 126 /* bcs */, SP::BPICCA, Convert__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3458 { 130 /* be */, SP::BCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
3459 { 130 /* be */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3460 { 130 /* be */, SP::BCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
3461 { 130 /* be */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3462 { 130 /* be */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3463 { 130 /* be */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3464 { 130 /* be */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3465 { 130 /* be */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3466 { 130 /* be */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3467 { 130 /* be */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3468 { 130 /* be */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3469 { 130 /* be */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3470 { 130 /* be */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3471 { 130 /* be */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3472 { 133 /* beq */, SP::BCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
3473 { 133 /* beq */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3474 { 133 /* beq */, SP::BCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
3475 { 133 /* beq */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3476 { 133 /* beq */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3477 { 133 /* beq */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3478 { 133 /* beq */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3479 { 133 /* beq */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3480 { 133 /* beq */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3481 { 133 /* beq */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3482 { 133 /* beq */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3483 { 133 /* beq */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3484 { 133 /* beq */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3485 { 133 /* beq */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3486 { 137 /* bg */, SP::BCOND, Convert__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
3487 { 137 /* bg */, SP::BPXCC, Convert__Imm1_1__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3488 { 137 /* bg */, SP::BCONDA, Convert__Imm1_1__imm_95_10, AMFBS_None, { MCK_a, MCK_Imm }, },
3489 { 137 /* bg */, SP::BPICC, Convert__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3490 { 137 /* bg */, SP::BPXCCA, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3491 { 137 /* bg */, SP::BPICCA, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3492 { 137 /* bg */, SP::BPXCCNT, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3493 { 137 /* bg */, SP::BPICCNT, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3494 { 137 /* bg */, SP::BPXCC, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3495 { 137 /* bg */, SP::BPICC, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3496 { 137 /* bg */, SP::BPXCCANT, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3497 { 137 /* bg */, SP::BPICCANT, Convert__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3498 { 137 /* bg */, SP::BPXCCA, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3499 { 137 /* bg */, SP::BPICCA, Convert__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3500 { 140 /* bge */, SP::BCOND, Convert__Imm1_0__imm_95_11, AMFBS_None, { MCK_Imm }, },
3501 { 140 /* bge */, SP::BPXCC, Convert__Imm1_1__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3502 { 140 /* bge */, SP::BCONDA, Convert__Imm1_1__imm_95_11, AMFBS_None, { MCK_a, MCK_Imm }, },
3503 { 140 /* bge */, SP::BPICC, Convert__Imm1_1__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3504 { 140 /* bge */, SP::BPXCCA, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3505 { 140 /* bge */, SP::BPICCA, Convert__Imm1_2__imm_95_11, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3506 { 140 /* bge */, SP::BPXCCNT, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3507 { 140 /* bge */, SP::BPICCNT, Convert__Imm1_2__imm_95_11, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3508 { 140 /* bge */, SP::BPXCC, Convert__Imm1_2__imm_95_11, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3509 { 140 /* bge */, SP::BPICC, Convert__Imm1_2__imm_95_11, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3510 { 140 /* bge */, SP::BPXCCANT, Convert__Imm1_3__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3511 { 140 /* bge */, SP::BPICCANT, Convert__Imm1_3__imm_95_11, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3512 { 140 /* bge */, SP::BPXCCA, Convert__Imm1_3__imm_95_11, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3513 { 140 /* bge */, SP::BPICCA, Convert__Imm1_3__imm_95_11, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3514 { 144 /* bgeu */, SP::BCOND, Convert__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
3515 { 144 /* bgeu */, SP::BPXCC, Convert__Imm1_1__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3516 { 144 /* bgeu */, SP::BCONDA, Convert__Imm1_1__imm_95_13, AMFBS_None, { MCK_a, MCK_Imm }, },
3517 { 144 /* bgeu */, SP::BPICC, Convert__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3518 { 144 /* bgeu */, SP::BPXCCA, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3519 { 144 /* bgeu */, SP::BPICCA, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3520 { 144 /* bgeu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3521 { 144 /* bgeu */, SP::BPICCNT, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3522 { 144 /* bgeu */, SP::BPXCC, Convert__Imm1_2__imm_95_13, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3523 { 144 /* bgeu */, SP::BPICC, Convert__Imm1_2__imm_95_13, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3524 { 144 /* bgeu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3525 { 144 /* bgeu */, SP::BPICCANT, Convert__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3526 { 144 /* bgeu */, SP::BPXCCA, Convert__Imm1_3__imm_95_13, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3527 { 144 /* bgeu */, SP::BPICCA, Convert__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3528 { 149 /* bgt */, SP::BCOND, Convert__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
3529 { 149 /* bgt */, SP::BPXCC, Convert__Imm1_1__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3530 { 149 /* bgt */, SP::BCONDA, Convert__Imm1_1__imm_95_10, AMFBS_None, { MCK_a, MCK_Imm }, },
3531 { 149 /* bgt */, SP::BPICC, Convert__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3532 { 149 /* bgt */, SP::BPXCCA, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3533 { 149 /* bgt */, SP::BPICCA, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3534 { 149 /* bgt */, SP::BPXCCNT, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3535 { 149 /* bgt */, SP::BPICCNT, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3536 { 149 /* bgt */, SP::BPXCC, Convert__Imm1_2__imm_95_10, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3537 { 149 /* bgt */, SP::BPICC, Convert__Imm1_2__imm_95_10, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3538 { 149 /* bgt */, SP::BPXCCANT, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3539 { 149 /* bgt */, SP::BPICCANT, Convert__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3540 { 149 /* bgt */, SP::BPXCCA, Convert__Imm1_3__imm_95_10, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3541 { 149 /* bgt */, SP::BPICCA, Convert__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3542 { 153 /* bgu */, SP::BCOND, Convert__Imm1_0__imm_95_12, AMFBS_None, { MCK_Imm }, },
3543 { 153 /* bgu */, SP::BPXCC, Convert__Imm1_1__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3544 { 153 /* bgu */, SP::BCONDA, Convert__Imm1_1__imm_95_12, AMFBS_None, { MCK_a, MCK_Imm }, },
3545 { 153 /* bgu */, SP::BPICC, Convert__Imm1_1__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3546 { 153 /* bgu */, SP::BPXCCA, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3547 { 153 /* bgu */, SP::BPICCA, Convert__Imm1_2__imm_95_12, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3548 { 153 /* bgu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3549 { 153 /* bgu */, SP::BPICCNT, Convert__Imm1_2__imm_95_12, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3550 { 153 /* bgu */, SP::BPXCC, Convert__Imm1_2__imm_95_12, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3551 { 153 /* bgu */, SP::BPICC, Convert__Imm1_2__imm_95_12, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3552 { 153 /* bgu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3553 { 153 /* bgu */, SP::BPICCANT, Convert__Imm1_3__imm_95_12, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3554 { 153 /* bgu */, SP::BPXCCA, Convert__Imm1_3__imm_95_12, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3555 { 153 /* bgu */, SP::BPICCA, Convert__Imm1_3__imm_95_12, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3556 { 157 /* bl */, SP::BCOND, Convert__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
3557 { 157 /* bl */, SP::BPXCC, Convert__Imm1_1__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3558 { 157 /* bl */, SP::BCONDA, Convert__Imm1_1__imm_95_3, AMFBS_None, { MCK_a, MCK_Imm }, },
3559 { 157 /* bl */, SP::BPICC, Convert__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3560 { 157 /* bl */, SP::BPXCCA, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3561 { 157 /* bl */, SP::BPICCA, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3562 { 157 /* bl */, SP::BPXCCNT, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3563 { 157 /* bl */, SP::BPICCNT, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3564 { 157 /* bl */, SP::BPXCC, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3565 { 157 /* bl */, SP::BPICC, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3566 { 157 /* bl */, SP::BPXCCANT, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3567 { 157 /* bl */, SP::BPICCANT, Convert__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3568 { 157 /* bl */, SP::BPXCCA, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3569 { 157 /* bl */, SP::BPICCA, Convert__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3570 { 160 /* ble */, SP::BCOND, Convert__Imm1_0__imm_95_2, AMFBS_None, { MCK_Imm }, },
3571 { 160 /* ble */, SP::BPXCC, Convert__Imm1_1__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3572 { 160 /* ble */, SP::BCONDA, Convert__Imm1_1__imm_95_2, AMFBS_None, { MCK_a, MCK_Imm }, },
3573 { 160 /* ble */, SP::BPICC, Convert__Imm1_1__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3574 { 160 /* ble */, SP::BPXCCA, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3575 { 160 /* ble */, SP::BPICCA, Convert__Imm1_2__imm_95_2, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3576 { 160 /* ble */, SP::BPXCCNT, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3577 { 160 /* ble */, SP::BPICCNT, Convert__Imm1_2__imm_95_2, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3578 { 160 /* ble */, SP::BPXCC, Convert__Imm1_2__imm_95_2, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3579 { 160 /* ble */, SP::BPICC, Convert__Imm1_2__imm_95_2, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3580 { 160 /* ble */, SP::BPXCCANT, Convert__Imm1_3__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3581 { 160 /* ble */, SP::BPICCANT, Convert__Imm1_3__imm_95_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3582 { 160 /* ble */, SP::BPXCCA, Convert__Imm1_3__imm_95_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3583 { 160 /* ble */, SP::BPICCA, Convert__Imm1_3__imm_95_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3584 { 164 /* bleu */, SP::BCOND, Convert__Imm1_0__imm_95_4, AMFBS_None, { MCK_Imm }, },
3585 { 164 /* bleu */, SP::BPXCC, Convert__Imm1_1__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3586 { 164 /* bleu */, SP::BCONDA, Convert__Imm1_1__imm_95_4, AMFBS_None, { MCK_a, MCK_Imm }, },
3587 { 164 /* bleu */, SP::BPICC, Convert__Imm1_1__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3588 { 164 /* bleu */, SP::BPXCCA, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3589 { 164 /* bleu */, SP::BPICCA, Convert__Imm1_2__imm_95_4, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3590 { 164 /* bleu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3591 { 164 /* bleu */, SP::BPICCNT, Convert__Imm1_2__imm_95_4, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3592 { 164 /* bleu */, SP::BPXCC, Convert__Imm1_2__imm_95_4, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3593 { 164 /* bleu */, SP::BPICC, Convert__Imm1_2__imm_95_4, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3594 { 164 /* bleu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3595 { 164 /* bleu */, SP::BPICCANT, Convert__Imm1_3__imm_95_4, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3596 { 164 /* bleu */, SP::BPXCCA, Convert__Imm1_3__imm_95_4, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3597 { 164 /* bleu */, SP::BPICCA, Convert__Imm1_3__imm_95_4, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3598 { 169 /* blt */, SP::BCOND, Convert__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
3599 { 169 /* blt */, SP::BPXCC, Convert__Imm1_1__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3600 { 169 /* blt */, SP::BCONDA, Convert__Imm1_1__imm_95_3, AMFBS_None, { MCK_a, MCK_Imm }, },
3601 { 169 /* blt */, SP::BPICC, Convert__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3602 { 169 /* blt */, SP::BPXCCA, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3603 { 169 /* blt */, SP::BPICCA, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3604 { 169 /* blt */, SP::BPXCCNT, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3605 { 169 /* blt */, SP::BPICCNT, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3606 { 169 /* blt */, SP::BPXCC, Convert__Imm1_2__imm_95_3, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3607 { 169 /* blt */, SP::BPICC, Convert__Imm1_2__imm_95_3, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3608 { 169 /* blt */, SP::BPXCCANT, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3609 { 169 /* blt */, SP::BPICCANT, Convert__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3610 { 169 /* blt */, SP::BPXCCA, Convert__Imm1_3__imm_95_3, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3611 { 169 /* blt */, SP::BPICCA, Convert__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3612 { 173 /* blu */, SP::BCOND, Convert__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
3613 { 173 /* blu */, SP::BPXCC, Convert__Imm1_1__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3614 { 173 /* blu */, SP::BCONDA, Convert__Imm1_1__imm_95_5, AMFBS_None, { MCK_a, MCK_Imm }, },
3615 { 173 /* blu */, SP::BPICC, Convert__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3616 { 173 /* blu */, SP::BPXCCA, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3617 { 173 /* blu */, SP::BPICCA, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3618 { 173 /* blu */, SP::BPXCCNT, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3619 { 173 /* blu */, SP::BPICCNT, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3620 { 173 /* blu */, SP::BPXCC, Convert__Imm1_2__imm_95_5, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3621 { 173 /* blu */, SP::BPICC, Convert__Imm1_2__imm_95_5, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3622 { 173 /* blu */, SP::BPXCCANT, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3623 { 173 /* blu */, SP::BPICCANT, Convert__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3624 { 173 /* blu */, SP::BPXCCA, Convert__Imm1_3__imm_95_5, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3625 { 173 /* blu */, SP::BPICCA, Convert__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3626 { 177 /* bmask */, SP::BMASK, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3627 { 183 /* bn */, SP::BCOND, Convert__Imm1_0__imm_95_0, AMFBS_None, { MCK_Imm }, },
3628 { 183 /* bn */, SP::BPXCC, Convert__Imm1_1__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3629 { 183 /* bn */, SP::BCONDA, Convert__Imm1_1__imm_95_0, AMFBS_None, { MCK_a, MCK_Imm }, },
3630 { 183 /* bn */, SP::BPICC, Convert__Imm1_1__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3631 { 183 /* bn */, SP::BPXCCA, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3632 { 183 /* bn */, SP::BPICCA, Convert__Imm1_2__imm_95_0, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3633 { 183 /* bn */, SP::BPXCCNT, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3634 { 183 /* bn */, SP::BPICCNT, Convert__Imm1_2__imm_95_0, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3635 { 183 /* bn */, SP::BPXCC, Convert__Imm1_2__imm_95_0, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3636 { 183 /* bn */, SP::BPICC, Convert__Imm1_2__imm_95_0, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3637 { 183 /* bn */, SP::BPXCCANT, Convert__Imm1_3__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3638 { 183 /* bn */, SP::BPICCANT, Convert__Imm1_3__imm_95_0, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3639 { 183 /* bn */, SP::BPXCCA, Convert__Imm1_3__imm_95_0, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3640 { 183 /* bn */, SP::BPICCA, Convert__Imm1_3__imm_95_0, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3641 { 186 /* bne */, SP::BCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
3642 { 186 /* bne */, SP::BPXCC, Convert__Imm1_1__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3643 { 186 /* bne */, SP::BCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
3644 { 186 /* bne */, SP::BPICC, Convert__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3645 { 186 /* bne */, SP::BPXCCA, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3646 { 186 /* bne */, SP::BPICCA, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3647 { 186 /* bne */, SP::BPXCCNT, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3648 { 186 /* bne */, SP::BPICCNT, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3649 { 186 /* bne */, SP::BPXCC, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3650 { 186 /* bne */, SP::BPICC, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3651 { 186 /* bne */, SP::BPXCCANT, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3652 { 186 /* bne */, SP::BPICCANT, Convert__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3653 { 186 /* bne */, SP::BPXCCA, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3654 { 186 /* bne */, SP::BPICCA, Convert__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3655 { 190 /* bneg */, SP::BCOND, Convert__Imm1_0__imm_95_6, AMFBS_None, { MCK_Imm }, },
3656 { 190 /* bneg */, SP::BPXCC, Convert__Imm1_1__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3657 { 190 /* bneg */, SP::BCONDA, Convert__Imm1_1__imm_95_6, AMFBS_None, { MCK_a, MCK_Imm }, },
3658 { 190 /* bneg */, SP::BPICC, Convert__Imm1_1__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3659 { 190 /* bneg */, SP::BPXCCA, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3660 { 190 /* bneg */, SP::BPICCA, Convert__Imm1_2__imm_95_6, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3661 { 190 /* bneg */, SP::BPXCCNT, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3662 { 190 /* bneg */, SP::BPICCNT, Convert__Imm1_2__imm_95_6, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3663 { 190 /* bneg */, SP::BPXCC, Convert__Imm1_2__imm_95_6, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3664 { 190 /* bneg */, SP::BPICC, Convert__Imm1_2__imm_95_6, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3665 { 190 /* bneg */, SP::BPXCCANT, Convert__Imm1_3__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3666 { 190 /* bneg */, SP::BPICCANT, Convert__Imm1_3__imm_95_6, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3667 { 190 /* bneg */, SP::BPXCCA, Convert__Imm1_3__imm_95_6, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3668 { 190 /* bneg */, SP::BPICCA, Convert__Imm1_3__imm_95_6, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3669 { 195 /* bnz */, SP::BCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
3670 { 195 /* bnz */, SP::BPXCC, Convert__Imm1_1__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3671 { 195 /* bnz */, SP::BCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
3672 { 195 /* bnz */, SP::BPICC, Convert__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3673 { 195 /* bnz */, SP::BPXCCA, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3674 { 195 /* bnz */, SP::BPICCA, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3675 { 195 /* bnz */, SP::BPXCCNT, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3676 { 195 /* bnz */, SP::BPICCNT, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3677 { 195 /* bnz */, SP::BPXCC, Convert__Imm1_2__imm_95_9, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3678 { 195 /* bnz */, SP::BPICC, Convert__Imm1_2__imm_95_9, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3679 { 195 /* bnz */, SP::BPXCCANT, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3680 { 195 /* bnz */, SP::BPICCANT, Convert__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3681 { 195 /* bnz */, SP::BPXCCA, Convert__Imm1_3__imm_95_9, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3682 { 195 /* bnz */, SP::BPICCA, Convert__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3683 { 199 /* bpos */, SP::BCOND, Convert__Imm1_0__imm_95_14, AMFBS_None, { MCK_Imm }, },
3684 { 199 /* bpos */, SP::BPXCC, Convert__Imm1_1__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3685 { 199 /* bpos */, SP::BCONDA, Convert__Imm1_1__imm_95_14, AMFBS_None, { MCK_a, MCK_Imm }, },
3686 { 199 /* bpos */, SP::BPICC, Convert__Imm1_1__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3687 { 199 /* bpos */, SP::BPXCCA, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3688 { 199 /* bpos */, SP::BPICCA, Convert__Imm1_2__imm_95_14, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3689 { 199 /* bpos */, SP::BPXCCNT, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3690 { 199 /* bpos */, SP::BPICCNT, Convert__Imm1_2__imm_95_14, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3691 { 199 /* bpos */, SP::BPXCC, Convert__Imm1_2__imm_95_14, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3692 { 199 /* bpos */, SP::BPICC, Convert__Imm1_2__imm_95_14, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3693 { 199 /* bpos */, SP::BPXCCANT, Convert__Imm1_3__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3694 { 199 /* bpos */, SP::BPICCANT, Convert__Imm1_3__imm_95_14, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3695 { 199 /* bpos */, SP::BPXCCA, Convert__Imm1_3__imm_95_14, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3696 { 199 /* bpos */, SP::BPICCA, Convert__Imm1_3__imm_95_14, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3697 { 204 /* br */, SP::BPR, Convert__Imm1_2__Imm1_0__Reg1_1, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_Imm }, },
3698 { 204 /* br */, SP::BPRA, Convert__Imm1_3__Imm1_0__Reg1_2, AMFBS_Is64Bit, { MCK_Imm, MCK_a, MCK_IntRegs, MCK_Imm }, },
3699 { 204 /* br */, SP::BPRNT, Convert__Imm1_3__Imm1_0__Reg1_2, AMFBS_Is64Bit, { MCK_Imm, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3700 { 204 /* br */, SP::BPRANT, Convert__Imm1_4__Imm1_0__Reg1_3, AMFBS_Is64Bit, { MCK_Imm, MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3701 { 207 /* bre */, SP::BPR, Convert__Imm1_1__imm_95_1__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
3702 { 207 /* bre */, SP::BPRA, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
3703 { 207 /* bre */, SP::BPRNT, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
3704 { 207 /* bre */, SP::BPR, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
3705 { 207 /* bre */, SP::BPRANT, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3706 { 207 /* bre */, SP::BPRA, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
3707 { 211 /* brgez */, SP::BPR, Convert__Imm1_1__imm_95_7__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
3708 { 211 /* brgez */, SP::BPRA, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
3709 { 211 /* brgez */, SP::BPRNT, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
3710 { 211 /* brgez */, SP::BPR, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
3711 { 211 /* brgez */, SP::BPRANT, Convert__Imm1_3__imm_95_7__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3712 { 211 /* brgez */, SP::BPRA, Convert__Imm1_3__imm_95_7__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
3713 { 217 /* brgz */, SP::BPR, Convert__Imm1_1__imm_95_6__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
3714 { 217 /* brgz */, SP::BPRA, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
3715 { 217 /* brgz */, SP::BPRNT, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
3716 { 217 /* brgz */, SP::BPR, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
3717 { 217 /* brgz */, SP::BPRANT, Convert__Imm1_3__imm_95_6__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3718 { 217 /* brgz */, SP::BPRA, Convert__Imm1_3__imm_95_6__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
3719 { 222 /* brlez */, SP::BPR, Convert__Imm1_1__imm_95_2__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
3720 { 222 /* brlez */, SP::BPRA, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
3721 { 222 /* brlez */, SP::BPRNT, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
3722 { 222 /* brlez */, SP::BPR, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
3723 { 222 /* brlez */, SP::BPRANT, Convert__Imm1_3__imm_95_2__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3724 { 222 /* brlez */, SP::BPRA, Convert__Imm1_3__imm_95_2__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
3725 { 228 /* brlz */, SP::BPR, Convert__Imm1_1__imm_95_3__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
3726 { 228 /* brlz */, SP::BPRA, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
3727 { 228 /* brlz */, SP::BPRNT, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
3728 { 228 /* brlz */, SP::BPR, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
3729 { 228 /* brlz */, SP::BPRANT, Convert__Imm1_3__imm_95_3__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3730 { 228 /* brlz */, SP::BPRA, Convert__Imm1_3__imm_95_3__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
3731 { 233 /* brne */, SP::BPR, Convert__Imm1_1__imm_95_5__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
3732 { 233 /* brne */, SP::BPRA, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
3733 { 233 /* brne */, SP::BPRNT, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
3734 { 233 /* brne */, SP::BPR, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
3735 { 233 /* brne */, SP::BPRANT, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3736 { 233 /* brne */, SP::BPRA, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
3737 { 238 /* brnz */, SP::BPR, Convert__Imm1_1__imm_95_5__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
3738 { 238 /* brnz */, SP::BPRA, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
3739 { 238 /* brnz */, SP::BPRNT, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
3740 { 238 /* brnz */, SP::BPR, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
3741 { 238 /* brnz */, SP::BPRANT, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3742 { 238 /* brnz */, SP::BPRA, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
3743 { 243 /* brz */, SP::BPR, Convert__Imm1_1__imm_95_1__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm }, },
3744 { 243 /* brz */, SP::BPRA, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_a, MCK_IntRegs, MCK_Imm }, },
3745 { 243 /* brz */, SP::BPRNT, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
3746 { 243 /* brz */, SP::BPR, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_Is64Bit, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
3747 { 243 /* brz */, SP::BPRANT, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
3748 { 243 /* brz */, SP::BPRA, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
3749 { 247 /* bset */, SP::ORrr, Convert__Reg1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
3750 { 247 /* bset */, SP::ORri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
3751 { 252 /* bshuffle */, SP::BSHUFFLE, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3752 { 261 /* btog */, SP::XORrr, Convert__Reg1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
3753 { 261 /* btog */, SP::XORri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
3754 { 266 /* btst */, SP::ANDCCrr, Convert__regG0__Reg1_1__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
3755 { 266 /* btst */, SP::ANDCCri, Convert__regG0__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
3756 { 271 /* bvc */, SP::BCOND, Convert__Imm1_0__imm_95_15, AMFBS_None, { MCK_Imm }, },
3757 { 271 /* bvc */, SP::BPXCC, Convert__Imm1_1__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3758 { 271 /* bvc */, SP::BCONDA, Convert__Imm1_1__imm_95_15, AMFBS_None, { MCK_a, MCK_Imm }, },
3759 { 271 /* bvc */, SP::BPICC, Convert__Imm1_1__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3760 { 271 /* bvc */, SP::BPXCCA, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3761 { 271 /* bvc */, SP::BPICCA, Convert__Imm1_2__imm_95_15, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3762 { 271 /* bvc */, SP::BPXCCNT, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3763 { 271 /* bvc */, SP::BPICCNT, Convert__Imm1_2__imm_95_15, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3764 { 271 /* bvc */, SP::BPXCC, Convert__Imm1_2__imm_95_15, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3765 { 271 /* bvc */, SP::BPICC, Convert__Imm1_2__imm_95_15, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3766 { 271 /* bvc */, SP::BPXCCANT, Convert__Imm1_3__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3767 { 271 /* bvc */, SP::BPICCANT, Convert__Imm1_3__imm_95_15, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3768 { 271 /* bvc */, SP::BPXCCA, Convert__Imm1_3__imm_95_15, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3769 { 271 /* bvc */, SP::BPICCA, Convert__Imm1_3__imm_95_15, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3770 { 275 /* bvs */, SP::BCOND, Convert__Imm1_0__imm_95_7, AMFBS_None, { MCK_Imm }, },
3771 { 275 /* bvs */, SP::BPXCC, Convert__Imm1_1__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3772 { 275 /* bvs */, SP::BCONDA, Convert__Imm1_1__imm_95_7, AMFBS_None, { MCK_a, MCK_Imm }, },
3773 { 275 /* bvs */, SP::BPICC, Convert__Imm1_1__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3774 { 275 /* bvs */, SP::BPXCCA, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3775 { 275 /* bvs */, SP::BPICCA, Convert__Imm1_2__imm_95_7, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3776 { 275 /* bvs */, SP::BPXCCNT, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3777 { 275 /* bvs */, SP::BPICCNT, Convert__Imm1_2__imm_95_7, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3778 { 275 /* bvs */, SP::BPXCC, Convert__Imm1_2__imm_95_7, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3779 { 275 /* bvs */, SP::BPICC, Convert__Imm1_2__imm_95_7, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3780 { 275 /* bvs */, SP::BPXCCANT, Convert__Imm1_3__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3781 { 275 /* bvs */, SP::BPICCANT, Convert__Imm1_3__imm_95_7, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3782 { 275 /* bvs */, SP::BPXCCA, Convert__Imm1_3__imm_95_7, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3783 { 275 /* bvs */, SP::BPICCA, Convert__Imm1_3__imm_95_7, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3784 { 279 /* bz */, SP::BCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
3785 { 279 /* bz */, SP::BPXCC, Convert__Imm1_1__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm }, },
3786 { 279 /* bz */, SP::BCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
3787 { 279 /* bz */, SP::BPICC, Convert__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
3788 { 279 /* bz */, SP::BPXCCA, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
3789 { 279 /* bz */, SP::BPICCA, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_ICC, MCK_Imm }, },
3790 { 279 /* bz */, SP::BPXCCNT, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3791 { 279 /* bz */, SP::BPICCNT, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pn, MCK_ICC, MCK_Imm }, },
3792 { 279 /* bz */, SP::BPXCC, Convert__Imm1_2__imm_95_1, AMFBS_Is64Bit, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3793 { 279 /* bz */, SP::BPICC, Convert__Imm1_2__imm_95_1, AMFBS_HasV9, { MCK_pt, MCK_ICC, MCK_Imm }, },
3794 { 279 /* bz */, SP::BPXCCANT, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
3795 { 279 /* bz */, SP::BPICCANT, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_ICC, MCK_Imm }, },
3796 { 279 /* bz */, SP::BPXCCA, Convert__Imm1_3__imm_95_1, AMFBS_Is64Bit, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
3797 { 279 /* bz */, SP::BPICCA, Convert__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_ICC, MCK_Imm }, },
3798 { 282 /* call */, SP::CALL, Convert__CallTarget1_0, AMFBS_None, { MCK_CallTarget }, },
3799 { 282 /* call */, SP::JMPLri, Convert__regO7__MEMri2_0, AMFBS_None, { MCK_MEMri }, },
3800 { 282 /* call */, SP::JMPLrr, Convert__regO7__MEMrr2_0, AMFBS_None, { MCK_MEMrr }, },
3801 { 282 /* call */, SP::CALLi, Convert__CallTarget1_0__Imm1_1, AMFBS_None, { MCK_CallTarget, MCK_Imm }, },
3802 { 282 /* call */, SP::TLS_CALL, Convert__CallTarget1_0__TailRelocSymCall_TLS1_1, AMFBS_None, { MCK_CallTarget, MCK_TailRelocSymCall_TLS }, },
3803 { 282 /* call */, SP::CALLrii, Convert__MEMri2_0__Imm1_1, AMFBS_None, { MCK_MEMri, MCK_Imm }, },
3804 { 282 /* call */, SP::CALLrri, Convert__MEMrr2_0__Imm1_1, AMFBS_None, { MCK_MEMrr, MCK_Imm }, },
3805 { 287 /* cas */, SP::CASArr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_128, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
3806 { 291 /* casa */, SP::CASAri, Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK__PCT_asi, MCK_IntRegs, MCK_IntRegs }, },
3807 { 291 /* casa */, SP::CASArr, Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1__ASITag1_3, AMFBS_HasCASA, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_ASITag, MCK_IntRegs, MCK_IntRegs }, },
3808 { 296 /* casl */, SP::CASArr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_136, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
3809 { 301 /* casx */, SP::CASXArr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_128, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
3810 { 306 /* casxa */, SP::CASXAri, Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1, AMFBS_Is64Bit_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK__PCT_asi, MCK_IntRegs, MCK_IntRegs }, },
3811 { 306 /* casxa */, SP::CASXArr, Convert__Reg1_5__Reg1_1__Reg1_4__Tie0_1_1__ASITag1_3, AMFBS_Is64Bit_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_ASITag, MCK_IntRegs, MCK_IntRegs }, },
3812 { 312 /* casxl */, SP::CASXArr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0_5_5__imm_95_136, AMFBS_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
3813 { 318 /* cb */, SP::CPBCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
3814 { 318 /* cb */, SP::CPBCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
3815 { 318 /* cb */, SP::CPBCOND, Convert__Imm1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Imm }, },
3816 { 318 /* cb */, SP::CPBCONDA, Convert__Imm1_2__Imm1_0, AMFBS_None, { MCK_Imm, MCK_a, MCK_Imm }, },
3817 { 321 /* cb0 */, SP::CPBCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
3818 { 321 /* cb0 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
3819 { 325 /* cb01 */, SP::CPBCOND, Convert__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
3820 { 325 /* cb01 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_13, AMFBS_None, { MCK_a, MCK_Imm }, },
3821 { 330 /* cb012 */, SP::CPBCOND, Convert__Imm1_0__imm_95_15, AMFBS_None, { MCK_Imm }, },
3822 { 330 /* cb012 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_15, AMFBS_None, { MCK_a, MCK_Imm }, },
3823 { 336 /* cb013 */, SP::CPBCOND, Convert__Imm1_0__imm_95_14, AMFBS_None, { MCK_Imm }, },
3824 { 336 /* cb013 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_14, AMFBS_None, { MCK_a, MCK_Imm }, },
3825 { 342 /* cb02 */, SP::CPBCOND, Convert__Imm1_0__imm_95_11, AMFBS_None, { MCK_Imm }, },
3826 { 342 /* cb02 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_11, AMFBS_None, { MCK_a, MCK_Imm }, },
3827 { 347 /* cb023 */, SP::CPBCOND, Convert__Imm1_0__imm_95_12, AMFBS_None, { MCK_Imm }, },
3828 { 347 /* cb023 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_12, AMFBS_None, { MCK_a, MCK_Imm }, },
3829 { 353 /* cb03 */, SP::CPBCOND, Convert__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
3830 { 353 /* cb03 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_10, AMFBS_None, { MCK_a, MCK_Imm }, },
3831 { 358 /* cb1 */, SP::CPBCOND, Convert__Imm1_0__imm_95_4, AMFBS_None, { MCK_Imm }, },
3832 { 358 /* cb1 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_4, AMFBS_None, { MCK_a, MCK_Imm }, },
3833 { 362 /* cb12 */, SP::CPBCOND, Convert__Imm1_0__imm_95_2, AMFBS_None, { MCK_Imm }, },
3834 { 362 /* cb12 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_2, AMFBS_None, { MCK_a, MCK_Imm }, },
3835 { 367 /* cb123 */, SP::CPBCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
3836 { 367 /* cb123 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
3837 { 373 /* cb13 */, SP::CPBCOND, Convert__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
3838 { 373 /* cb13 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_3, AMFBS_None, { MCK_a, MCK_Imm }, },
3839 { 378 /* cb2 */, SP::CPBCOND, Convert__Imm1_0__imm_95_6, AMFBS_None, { MCK_Imm }, },
3840 { 378 /* cb2 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_6, AMFBS_None, { MCK_a, MCK_Imm }, },
3841 { 382 /* cb23 */, SP::CPBCOND, Convert__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
3842 { 382 /* cb23 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_5, AMFBS_None, { MCK_a, MCK_Imm }, },
3843 { 387 /* cb3 */, SP::CPBCOND, Convert__Imm1_0__imm_95_7, AMFBS_None, { MCK_Imm }, },
3844 { 387 /* cb3 */, SP::CPBCONDA, Convert__Imm1_1__imm_95_7, AMFBS_None, { MCK_a, MCK_Imm }, },
3845 { 391 /* cba */, SP::CPBCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
3846 { 391 /* cba */, SP::CPBCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
3847 { 395 /* cbn */, SP::CPBCOND, Convert__Imm1_0__imm_95_0, AMFBS_None, { MCK_Imm }, },
3848 { 395 /* cbn */, SP::CPBCONDA, Convert__Imm1_1__imm_95_0, AMFBS_None, { MCK_a, MCK_Imm }, },
3849 { 399 /* clr */, SP::ORrr, Convert__Reg1_0__regG0__regG0, AMFBS_None, { MCK_IntRegs }, },
3850 { 399 /* clr */, SP::STri, Convert__MEMri2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_ }, },
3851 { 399 /* clr */, SP::STrr, Convert__MEMrr2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
3852 { 403 /* clrb */, SP::STBri, Convert__MEMri2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_ }, },
3853 { 403 /* clrb */, SP::STBrr, Convert__MEMrr2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
3854 { 408 /* clrh */, SP::STHri, Convert__MEMri2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_ }, },
3855 { 408 /* clrh */, SP::STHrr, Convert__MEMrr2_1__regG0, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
3856 { 413 /* cmask16 */, SP::CMASK16, Convert__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs }, },
3857 { 421 /* cmask32 */, SP::CMASK32, Convert__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs }, },
3858 { 429 /* cmask8 */, SP::CMASK8, Convert__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs }, },
3859 { 436 /* cmp */, SP::SUBCCrr, Convert__regG0__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
3860 { 436 /* cmp */, SP::SUBCCri, Convert__regG0__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm }, },
3861 { 440 /* cwb */, SP::CWBCONDrr, Convert__Imm1_3__Imm1_0__Reg1_1__Reg1_2, AMFBS_HasOSA2011, { MCK_Imm, MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3862 { 440 /* cwb */, SP::CWBCONDri, Convert__Imm1_3__Imm1_0__Reg1_1__Imm1_2, AMFBS_HasOSA2011, { MCK_Imm, MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3863 { 444 /* cwbcc */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3864 { 444 /* cwbcc */, SP::CWBCONDri, Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3865 { 450 /* cwbcs */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3866 { 450 /* cwbcs */, SP::CWBCONDri, Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3867 { 456 /* cwbe */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_1__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3868 { 456 /* cwbe */, SP::CWBCONDri, Convert__Imm1_2__imm_95_1__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3869 { 461 /* cwbg */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_10__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3870 { 461 /* cwbg */, SP::CWBCONDri, Convert__Imm1_2__imm_95_10__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3871 { 466 /* cwbge */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_11__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3872 { 466 /* cwbge */, SP::CWBCONDri, Convert__Imm1_2__imm_95_11__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3873 { 472 /* cwbgeu */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3874 { 472 /* cwbgeu */, SP::CWBCONDri, Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3875 { 479 /* cwbgu */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_12__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3876 { 479 /* cwbgu */, SP::CWBCONDri, Convert__Imm1_2__imm_95_12__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3877 { 485 /* cwbl */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_3__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3878 { 485 /* cwbl */, SP::CWBCONDri, Convert__Imm1_2__imm_95_3__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3879 { 490 /* cwble */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_2__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3880 { 490 /* cwble */, SP::CWBCONDri, Convert__Imm1_2__imm_95_2__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3881 { 496 /* cwbleu */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_4__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3882 { 496 /* cwbleu */, SP::CWBCONDri, Convert__Imm1_2__imm_95_4__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3883 { 503 /* cwblu */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3884 { 503 /* cwblu */, SP::CWBCONDri, Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3885 { 509 /* cwbne */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_9__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3886 { 509 /* cwbne */, SP::CWBCONDri, Convert__Imm1_2__imm_95_9__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3887 { 515 /* cwbneg */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_6__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3888 { 515 /* cwbneg */, SP::CWBCONDri, Convert__Imm1_2__imm_95_6__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3889 { 522 /* cwbpos */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_14__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3890 { 522 /* cwbpos */, SP::CWBCONDri, Convert__Imm1_2__imm_95_14__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3891 { 529 /* cwbvc */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_15__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3892 { 529 /* cwbvc */, SP::CWBCONDri, Convert__Imm1_2__imm_95_15__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3893 { 535 /* cwbvs */, SP::CWBCONDrr, Convert__Imm1_2__imm_95_7__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3894 { 535 /* cwbvs */, SP::CWBCONDri, Convert__Imm1_2__imm_95_7__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3895 { 541 /* cxb */, SP::CXBCONDrr, Convert__Imm1_3__Imm1_0__Reg1_1__Reg1_2, AMFBS_HasOSA2011, { MCK_Imm, MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3896 { 541 /* cxb */, SP::CXBCONDri, Convert__Imm1_3__Imm1_0__Reg1_1__Imm1_2, AMFBS_HasOSA2011, { MCK_Imm, MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3897 { 545 /* cxbcc */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3898 { 545 /* cxbcc */, SP::CXBCONDri, Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3899 { 551 /* cxbcs */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3900 { 551 /* cxbcs */, SP::CXBCONDri, Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3901 { 557 /* cxbe */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_1__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3902 { 557 /* cxbe */, SP::CXBCONDri, Convert__Imm1_2__imm_95_1__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3903 { 562 /* cxbg */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_10__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3904 { 562 /* cxbg */, SP::CXBCONDri, Convert__Imm1_2__imm_95_10__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3905 { 567 /* cxbge */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_11__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3906 { 567 /* cxbge */, SP::CXBCONDri, Convert__Imm1_2__imm_95_11__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3907 { 573 /* cxbgeu */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_13__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3908 { 573 /* cxbgeu */, SP::CXBCONDri, Convert__Imm1_2__imm_95_13__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3909 { 580 /* cxbgu */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_12__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3910 { 580 /* cxbgu */, SP::CXBCONDri, Convert__Imm1_2__imm_95_12__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3911 { 586 /* cxbl */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_3__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3912 { 586 /* cxbl */, SP::CXBCONDri, Convert__Imm1_2__imm_95_3__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3913 { 591 /* cxble */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_2__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3914 { 591 /* cxble */, SP::CXBCONDri, Convert__Imm1_2__imm_95_2__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3915 { 597 /* cxbleu */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_4__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3916 { 597 /* cxbleu */, SP::CXBCONDri, Convert__Imm1_2__imm_95_4__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3917 { 604 /* cxblu */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_5__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3918 { 604 /* cxblu */, SP::CXBCONDri, Convert__Imm1_2__imm_95_5__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3919 { 610 /* cxbne */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_9__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3920 { 610 /* cxbne */, SP::CXBCONDri, Convert__Imm1_2__imm_95_9__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3921 { 616 /* cxbneg */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_6__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3922 { 616 /* cxbneg */, SP::CXBCONDri, Convert__Imm1_2__imm_95_6__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3923 { 623 /* cxbpos */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_14__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3924 { 623 /* cxbpos */, SP::CXBCONDri, Convert__Imm1_2__imm_95_14__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3925 { 630 /* cxbvc */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_15__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3926 { 630 /* cxbvc */, SP::CXBCONDri, Convert__Imm1_2__imm_95_15__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3927 { 636 /* cxbvs */, SP::CXBCONDrr, Convert__Imm1_2__imm_95_7__Reg1_0__Reg1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_IntRegs, MCK_Imm }, },
3928 { 636 /* cxbvs */, SP::CXBCONDri, Convert__Imm1_2__imm_95_7__Reg1_0__Imm1_1, AMFBS_HasOSA2011, { MCK_IntRegs, MCK_Imm, MCK_Imm }, },
3929 { 642 /* dec */, SP::SUBri, Convert__Reg1_0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
3930 { 642 /* dec */, SP::SUBri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
3931 { 646 /* deccc */, SP::SUBCCri, Convert__Reg1_0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
3932 { 646 /* deccc */, SP::SUBCCri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
3933 { 652 /* done */, SP::DONE, Convert_NoOperands, AMFBS_HasV9, { }, },
3934 { 657 /* edge16 */, SP::EDGE16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3935 { 664 /* edge16l */, SP::EDGE16L, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3936 { 672 /* edge16ln */, SP::EDGE16LN, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3937 { 681 /* edge16n */, SP::EDGE16N, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3938 { 689 /* edge32 */, SP::EDGE32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3939 { 696 /* edge32l */, SP::EDGE32L, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3940 { 704 /* edge32ln */, SP::EDGE32LN, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3941 { 713 /* edge32n */, SP::EDGE32N, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3942 { 721 /* edge8 */, SP::EDGE8, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3943 { 727 /* edge8l */, SP::EDGE8L, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3944 { 734 /* edge8ln */, SP::EDGE8LN, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3945 { 742 /* edge8n */, SP::EDGE8N, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3946 { 749 /* fabsd */, SP::FABSD, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
3947 { 755 /* fabsq */, SP::FABSQ, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
3948 { 761 /* fabss */, SP::FABSS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
3949 { 767 /* faddd */, SP::FADDD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3950 { 773 /* faddq */, SP::FADDQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
3951 { 779 /* fadds */, SP::FADDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
3952 { 785 /* faligndata */, SP::FALIGNADATA, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3953 { 796 /* fand */, SP::FAND, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3954 { 801 /* fandnot1 */, SP::FANDNOT1, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3955 { 810 /* fandnot1s */, SP::FANDNOT1S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
3956 { 820 /* fandnot2 */, SP::FANDNOT2, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3957 { 829 /* fandnot2s */, SP::FANDNOT2S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
3958 { 839 /* fands */, SP::FANDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
3959 { 845 /* fb */, SP::FBCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
3960 { 845 /* fb */, SP::FBCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
3961 { 845 /* fb */, SP::BPFCC, Convert__Imm1_1__imm_95_8__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
3962 { 845 /* fb */, SP::FBCOND, Convert__Imm1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Imm }, },
3963 { 845 /* fb */, SP::BPFCCA, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
3964 { 845 /* fb */, SP::BPFCCNT, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3965 { 845 /* fb */, SP::BPFCC, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
3966 { 845 /* fb */, SP::FBCONDA, Convert__Imm1_2__Imm1_0, AMFBS_None, { MCK_Imm, MCK_a, MCK_Imm }, },
3967 { 845 /* fb */, SP::FBCOND_V9, Convert__Imm1_2__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_Imm }, },
3968 { 845 /* fb */, SP::BPFCC, Convert__Imm1_2__Imm1_0__Reg1_1, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_Imm }, },
3969 { 845 /* fb */, SP::BPFCCANT, Convert__Imm1_3__imm_95_8__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3970 { 845 /* fb */, SP::BPFCCA, Convert__Imm1_3__imm_95_8__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
3971 { 845 /* fb */, SP::FBCONDA_V9, Convert__Imm1_3__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_FCC0, MCK_Imm }, },
3972 { 845 /* fb */, SP::BPFCCA, Convert__Imm1_3__Imm1_0__Reg1_2, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_FCCRegs, MCK_Imm }, },
3973 { 845 /* fb */, SP::BPFCCNT, Convert__Imm1_3__Imm1_0__Reg1_2, AMFBS_HasV9, { MCK_Imm, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3974 { 845 /* fb */, SP::BPFCCANT, Convert__Imm1_4__Imm1_0__Reg1_3, AMFBS_HasV9, { MCK_Imm, MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3975 { 848 /* fba */, SP::FBCOND, Convert__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
3976 { 848 /* fba */, SP::FBCONDA, Convert__Imm1_1__imm_95_8, AMFBS_None, { MCK_a, MCK_Imm }, },
3977 { 848 /* fba */, SP::BPFCC, Convert__Imm1_1__imm_95_8__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
3978 { 848 /* fba */, SP::BPFCCA, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
3979 { 848 /* fba */, SP::BPFCCNT, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3980 { 848 /* fba */, SP::BPFCC, Convert__Imm1_2__imm_95_8__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
3981 { 848 /* fba */, SP::BPFCCANT, Convert__Imm1_3__imm_95_8__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3982 { 848 /* fba */, SP::BPFCCA, Convert__Imm1_3__imm_95_8__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
3983 { 852 /* fbe */, SP::FBCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
3984 { 852 /* fbe */, SP::FBCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
3985 { 852 /* fbe */, SP::BPFCC, Convert__Imm1_1__imm_95_9__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
3986 { 852 /* fbe */, SP::BPFCCA, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
3987 { 852 /* fbe */, SP::BPFCCNT, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3988 { 852 /* fbe */, SP::BPFCC, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
3989 { 852 /* fbe */, SP::BPFCCANT, Convert__Imm1_3__imm_95_9__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3990 { 852 /* fbe */, SP::BPFCCA, Convert__Imm1_3__imm_95_9__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
3991 { 856 /* fbg */, SP::FBCOND, Convert__Imm1_0__imm_95_6, AMFBS_None, { MCK_Imm }, },
3992 { 856 /* fbg */, SP::FBCONDA, Convert__Imm1_1__imm_95_6, AMFBS_None, { MCK_a, MCK_Imm }, },
3993 { 856 /* fbg */, SP::BPFCC, Convert__Imm1_1__imm_95_6__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
3994 { 856 /* fbg */, SP::BPFCCA, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
3995 { 856 /* fbg */, SP::BPFCCNT, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3996 { 856 /* fbg */, SP::BPFCC, Convert__Imm1_2__imm_95_6__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
3997 { 856 /* fbg */, SP::BPFCCANT, Convert__Imm1_3__imm_95_6__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
3998 { 856 /* fbg */, SP::BPFCCA, Convert__Imm1_3__imm_95_6__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
3999 { 860 /* fbge */, SP::FBCOND, Convert__Imm1_0__imm_95_11, AMFBS_None, { MCK_Imm }, },
4000 { 860 /* fbge */, SP::FBCONDA, Convert__Imm1_1__imm_95_11, AMFBS_None, { MCK_a, MCK_Imm }, },
4001 { 860 /* fbge */, SP::BPFCC, Convert__Imm1_1__imm_95_11__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4002 { 860 /* fbge */, SP::BPFCCA, Convert__Imm1_2__imm_95_11__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4003 { 860 /* fbge */, SP::BPFCCNT, Convert__Imm1_2__imm_95_11__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4004 { 860 /* fbge */, SP::BPFCC, Convert__Imm1_2__imm_95_11__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4005 { 860 /* fbge */, SP::BPFCCANT, Convert__Imm1_3__imm_95_11__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4006 { 860 /* fbge */, SP::BPFCCA, Convert__Imm1_3__imm_95_11__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4007 { 865 /* fbl */, SP::FBCOND, Convert__Imm1_0__imm_95_4, AMFBS_None, { MCK_Imm }, },
4008 { 865 /* fbl */, SP::FBCONDA, Convert__Imm1_1__imm_95_4, AMFBS_None, { MCK_a, MCK_Imm }, },
4009 { 865 /* fbl */, SP::BPFCC, Convert__Imm1_1__imm_95_4__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4010 { 865 /* fbl */, SP::BPFCCA, Convert__Imm1_2__imm_95_4__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4011 { 865 /* fbl */, SP::BPFCCNT, Convert__Imm1_2__imm_95_4__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4012 { 865 /* fbl */, SP::BPFCC, Convert__Imm1_2__imm_95_4__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4013 { 865 /* fbl */, SP::BPFCCANT, Convert__Imm1_3__imm_95_4__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4014 { 865 /* fbl */, SP::BPFCCA, Convert__Imm1_3__imm_95_4__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4015 { 869 /* fble */, SP::FBCOND, Convert__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
4016 { 869 /* fble */, SP::FBCONDA, Convert__Imm1_1__imm_95_13, AMFBS_None, { MCK_a, MCK_Imm }, },
4017 { 869 /* fble */, SP::BPFCC, Convert__Imm1_1__imm_95_13__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4018 { 869 /* fble */, SP::BPFCCA, Convert__Imm1_2__imm_95_13__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4019 { 869 /* fble */, SP::BPFCCNT, Convert__Imm1_2__imm_95_13__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4020 { 869 /* fble */, SP::BPFCC, Convert__Imm1_2__imm_95_13__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4021 { 869 /* fble */, SP::BPFCCANT, Convert__Imm1_3__imm_95_13__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4022 { 869 /* fble */, SP::BPFCCA, Convert__Imm1_3__imm_95_13__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4023 { 874 /* fblg */, SP::FBCOND, Convert__Imm1_0__imm_95_2, AMFBS_None, { MCK_Imm }, },
4024 { 874 /* fblg */, SP::FBCONDA, Convert__Imm1_1__imm_95_2, AMFBS_None, { MCK_a, MCK_Imm }, },
4025 { 874 /* fblg */, SP::BPFCC, Convert__Imm1_1__imm_95_2__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4026 { 874 /* fblg */, SP::BPFCCA, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4027 { 874 /* fblg */, SP::BPFCCNT, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4028 { 874 /* fblg */, SP::BPFCC, Convert__Imm1_2__imm_95_2__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4029 { 874 /* fblg */, SP::BPFCCANT, Convert__Imm1_3__imm_95_2__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4030 { 874 /* fblg */, SP::BPFCCA, Convert__Imm1_3__imm_95_2__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4031 { 879 /* fbn */, SP::FBCOND, Convert__Imm1_0__imm_95_0, AMFBS_None, { MCK_Imm }, },
4032 { 879 /* fbn */, SP::FBCONDA, Convert__Imm1_1__imm_95_0, AMFBS_None, { MCK_a, MCK_Imm }, },
4033 { 879 /* fbn */, SP::BPFCC, Convert__Imm1_1__imm_95_0__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4034 { 879 /* fbn */, SP::BPFCCA, Convert__Imm1_2__imm_95_0__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4035 { 879 /* fbn */, SP::BPFCCNT, Convert__Imm1_2__imm_95_0__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4036 { 879 /* fbn */, SP::BPFCC, Convert__Imm1_2__imm_95_0__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4037 { 879 /* fbn */, SP::BPFCCANT, Convert__Imm1_3__imm_95_0__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4038 { 879 /* fbn */, SP::BPFCCA, Convert__Imm1_3__imm_95_0__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4039 { 883 /* fbne */, SP::FBCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
4040 { 883 /* fbne */, SP::FBCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
4041 { 883 /* fbne */, SP::BPFCC, Convert__Imm1_1__imm_95_1__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4042 { 883 /* fbne */, SP::BPFCCA, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4043 { 883 /* fbne */, SP::BPFCCNT, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4044 { 883 /* fbne */, SP::BPFCC, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4045 { 883 /* fbne */, SP::BPFCCANT, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4046 { 883 /* fbne */, SP::BPFCCA, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4047 { 888 /* fbnz */, SP::FBCOND, Convert__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
4048 { 888 /* fbnz */, SP::FBCONDA, Convert__Imm1_1__imm_95_1, AMFBS_None, { MCK_a, MCK_Imm }, },
4049 { 888 /* fbnz */, SP::BPFCC, Convert__Imm1_1__imm_95_1__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4050 { 888 /* fbnz */, SP::BPFCCA, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4051 { 888 /* fbnz */, SP::BPFCCNT, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4052 { 888 /* fbnz */, SP::BPFCC, Convert__Imm1_2__imm_95_1__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4053 { 888 /* fbnz */, SP::BPFCCANT, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4054 { 888 /* fbnz */, SP::BPFCCA, Convert__Imm1_3__imm_95_1__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4055 { 893 /* fbo */, SP::FBCOND, Convert__Imm1_0__imm_95_15, AMFBS_None, { MCK_Imm }, },
4056 { 893 /* fbo */, SP::FBCONDA, Convert__Imm1_1__imm_95_15, AMFBS_None, { MCK_a, MCK_Imm }, },
4057 { 893 /* fbo */, SP::BPFCC, Convert__Imm1_1__imm_95_15__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4058 { 893 /* fbo */, SP::BPFCCA, Convert__Imm1_2__imm_95_15__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4059 { 893 /* fbo */, SP::BPFCCNT, Convert__Imm1_2__imm_95_15__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4060 { 893 /* fbo */, SP::BPFCC, Convert__Imm1_2__imm_95_15__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4061 { 893 /* fbo */, SP::BPFCCANT, Convert__Imm1_3__imm_95_15__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4062 { 893 /* fbo */, SP::BPFCCA, Convert__Imm1_3__imm_95_15__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4063 { 897 /* fbu */, SP::FBCOND, Convert__Imm1_0__imm_95_7, AMFBS_None, { MCK_Imm }, },
4064 { 897 /* fbu */, SP::FBCONDA, Convert__Imm1_1__imm_95_7, AMFBS_None, { MCK_a, MCK_Imm }, },
4065 { 897 /* fbu */, SP::BPFCC, Convert__Imm1_1__imm_95_7__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4066 { 897 /* fbu */, SP::BPFCCA, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4067 { 897 /* fbu */, SP::BPFCCNT, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4068 { 897 /* fbu */, SP::BPFCC, Convert__Imm1_2__imm_95_7__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4069 { 897 /* fbu */, SP::BPFCCANT, Convert__Imm1_3__imm_95_7__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4070 { 897 /* fbu */, SP::BPFCCA, Convert__Imm1_3__imm_95_7__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4071 { 901 /* fbue */, SP::FBCOND, Convert__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
4072 { 901 /* fbue */, SP::FBCONDA, Convert__Imm1_1__imm_95_10, AMFBS_None, { MCK_a, MCK_Imm }, },
4073 { 901 /* fbue */, SP::BPFCC, Convert__Imm1_1__imm_95_10__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4074 { 901 /* fbue */, SP::BPFCCA, Convert__Imm1_2__imm_95_10__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4075 { 901 /* fbue */, SP::BPFCCNT, Convert__Imm1_2__imm_95_10__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4076 { 901 /* fbue */, SP::BPFCC, Convert__Imm1_2__imm_95_10__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4077 { 901 /* fbue */, SP::BPFCCANT, Convert__Imm1_3__imm_95_10__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4078 { 901 /* fbue */, SP::BPFCCA, Convert__Imm1_3__imm_95_10__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4079 { 906 /* fbug */, SP::FBCOND, Convert__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
4080 { 906 /* fbug */, SP::FBCONDA, Convert__Imm1_1__imm_95_5, AMFBS_None, { MCK_a, MCK_Imm }, },
4081 { 906 /* fbug */, SP::BPFCC, Convert__Imm1_1__imm_95_5__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4082 { 906 /* fbug */, SP::BPFCCA, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4083 { 906 /* fbug */, SP::BPFCCNT, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4084 { 906 /* fbug */, SP::BPFCC, Convert__Imm1_2__imm_95_5__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4085 { 906 /* fbug */, SP::BPFCCANT, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4086 { 906 /* fbug */, SP::BPFCCA, Convert__Imm1_3__imm_95_5__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4087 { 911 /* fbuge */, SP::FBCOND, Convert__Imm1_0__imm_95_12, AMFBS_None, { MCK_Imm }, },
4088 { 911 /* fbuge */, SP::FBCONDA, Convert__Imm1_1__imm_95_12, AMFBS_None, { MCK_a, MCK_Imm }, },
4089 { 911 /* fbuge */, SP::BPFCC, Convert__Imm1_1__imm_95_12__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4090 { 911 /* fbuge */, SP::BPFCCA, Convert__Imm1_2__imm_95_12__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4091 { 911 /* fbuge */, SP::BPFCCNT, Convert__Imm1_2__imm_95_12__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4092 { 911 /* fbuge */, SP::BPFCC, Convert__Imm1_2__imm_95_12__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4093 { 911 /* fbuge */, SP::BPFCCANT, Convert__Imm1_3__imm_95_12__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4094 { 911 /* fbuge */, SP::BPFCCA, Convert__Imm1_3__imm_95_12__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4095 { 917 /* fbul */, SP::FBCOND, Convert__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
4096 { 917 /* fbul */, SP::FBCONDA, Convert__Imm1_1__imm_95_3, AMFBS_None, { MCK_a, MCK_Imm }, },
4097 { 917 /* fbul */, SP::BPFCC, Convert__Imm1_1__imm_95_3__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4098 { 917 /* fbul */, SP::BPFCCA, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4099 { 917 /* fbul */, SP::BPFCCNT, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4100 { 917 /* fbul */, SP::BPFCC, Convert__Imm1_2__imm_95_3__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4101 { 917 /* fbul */, SP::BPFCCANT, Convert__Imm1_3__imm_95_3__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4102 { 917 /* fbul */, SP::BPFCCA, Convert__Imm1_3__imm_95_3__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4103 { 922 /* fbule */, SP::FBCOND, Convert__Imm1_0__imm_95_14, AMFBS_None, { MCK_Imm }, },
4104 { 922 /* fbule */, SP::FBCONDA, Convert__Imm1_1__imm_95_14, AMFBS_None, { MCK_a, MCK_Imm }, },
4105 { 922 /* fbule */, SP::BPFCC, Convert__Imm1_1__imm_95_14__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4106 { 922 /* fbule */, SP::BPFCCA, Convert__Imm1_2__imm_95_14__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4107 { 922 /* fbule */, SP::BPFCCNT, Convert__Imm1_2__imm_95_14__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4108 { 922 /* fbule */, SP::BPFCC, Convert__Imm1_2__imm_95_14__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4109 { 922 /* fbule */, SP::BPFCCANT, Convert__Imm1_3__imm_95_14__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4110 { 922 /* fbule */, SP::BPFCCA, Convert__Imm1_3__imm_95_14__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4111 { 928 /* fbz */, SP::FBCOND, Convert__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
4112 { 928 /* fbz */, SP::FBCONDA, Convert__Imm1_1__imm_95_9, AMFBS_None, { MCK_a, MCK_Imm }, },
4113 { 928 /* fbz */, SP::BPFCC, Convert__Imm1_1__imm_95_9__Reg1_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm }, },
4114 { 928 /* fbz */, SP::BPFCCA, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
4115 { 928 /* fbz */, SP::BPFCCNT, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4116 { 928 /* fbz */, SP::BPFCC, Convert__Imm1_2__imm_95_9__Reg1_1, AMFBS_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4117 { 928 /* fbz */, SP::BPFCCANT, Convert__Imm1_3__imm_95_9__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
4118 { 928 /* fbz */, SP::BPFCCA, Convert__Imm1_3__imm_95_9__Reg1_2, AMFBS_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
4119 { 932 /* fchksm16 */, SP::FCHKSM16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4120 { 941 /* fcmpd */, SP::V9FCMPD, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs }, },
4121 { 941 /* fcmpd */, SP::V9FCMPD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4122 { 947 /* fcmped */, SP::V9FCMPED, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs }, },
4123 { 947 /* fcmped */, SP::V9FCMPED, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4124 { 954 /* fcmpeq */, SP::V9FCMPEQ, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs }, },
4125 { 954 /* fcmpeq */, SP::V9FCMPEQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4126 { 961 /* fcmpeq16 */, SP::FCMPEQ16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4127 { 970 /* fcmpeq32 */, SP::FCMPEQ32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4128 { 979 /* fcmpes */, SP::V9FCMPES, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4129 { 979 /* fcmpes */, SP::V9FCMPES, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4130 { 986 /* fcmpgt16 */, SP::FCMPGT16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4131 { 995 /* fcmpgt32 */, SP::FCMPGT32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4132 { 1004 /* fcmple16 */, SP::FCMPLE16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4133 { 1013 /* fcmple32 */, SP::FCMPLE32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4134 { 1022 /* fcmpne16 */, SP::FCMPNE16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4135 { 1031 /* fcmpne32 */, SP::FCMPNE32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4136 { 1040 /* fcmpq */, SP::V9FCMPQ, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs }, },
4137 { 1040 /* fcmpq */, SP::V9FCMPQ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4138 { 1046 /* fcmps */, SP::V9FCMPS, Convert__regFCC0__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4139 { 1046 /* fcmps */, SP::V9FCMPS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4140 { 1052 /* fdivd */, SP::FDIVD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4141 { 1058 /* fdivq */, SP::FDIVQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4142 { 1064 /* fdivs */, SP::FDIVS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4143 { 1070 /* fdmulq */, SP::FDMULQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_QFPRegs }, },
4144 { 1077 /* fdtoi */, SP::FDTOI, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK_FPRegs }, },
4145 { 1083 /* fdtoq */, SP::FDTOQ, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK_QFPRegs }, },
4146 { 1089 /* fdtos */, SP::FDTOS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK_FPRegs }, },
4147 { 1095 /* fdtox */, SP::FDTOX, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_DFPRegs, MCK_DFPRegs }, },
4148 { 1101 /* fexpand */, SP::FEXPAND, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_DFPRegs }, },
4149 { 1109 /* fhaddd */, SP::FHADDD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4150 { 1116 /* fhadds */, SP::FHADDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4151 { 1123 /* fhsubd */, SP::FHSUBD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4152 { 1130 /* fhsubs */, SP::FHSUBS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4153 { 1137 /* fitod */, SP::FITOD, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_DFPRegs }, },
4154 { 1143 /* fitoq */, SP::FITOQ, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_QFPRegs }, },
4155 { 1149 /* fitos */, SP::FITOS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4156 { 1155 /* flcmpd */, SP::FLCMPD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVIS3, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4157 { 1162 /* flcmps */, SP::FLCMPS, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasVIS3, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4158 { 1169 /* flush */, SP::FLUSH, Convert_NoOperands, AMFBS_None, { }, },
4159 { 1169 /* flush */, SP::FLUSH, Convert_NoOperands, AMFBS_None, { MCK_G0 }, },
4160 { 1169 /* flush */, SP::FLUSHri, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, },
4161 { 1169 /* flush */, SP::FLUSHrr, Convert__MEMrr2_0, AMFBS_None, { MCK_MEMrr }, },
4162 { 1175 /* flushw */, SP::FLUSHW, Convert_NoOperands, AMFBS_HasV9, { }, },
4163 { 1182 /* fmaddd */, SP::FMADDD, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4164 { 1189 /* fmadds */, SP::FMADDS, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4165 { 1196 /* fmean16 */, SP::FMEAN16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4166 { 1204 /* fmovd */, SP::FMOVD, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
4167 { 1204 /* fmovd */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4168 { 1204 /* fmovd */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4169 { 1204 /* fmovd */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4170 { 1204 /* fmovd */, SP::FMOVD_XCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4171 { 1204 /* fmovd */, SP::FMOVD_FCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_DFPRegs, MCK_DFPRegs }, },
4172 { 1204 /* fmovd */, SP::FMOVD_ICC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4173 { 1204 /* fmovd */, SP::V9FMOVD_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4174 { 1210 /* fmovda */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4175 { 1210 /* fmovda */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4176 { 1210 /* fmovda */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4177 { 1217 /* fmovdcc */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4178 { 1217 /* fmovdcc */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4179 { 1225 /* fmovdcs */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4180 { 1225 /* fmovdcs */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4181 { 1233 /* fmovde */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4182 { 1233 /* fmovde */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4183 { 1233 /* fmovde */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4184 { 1240 /* fmovdeq */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4185 { 1240 /* fmovdeq */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4186 { 1248 /* fmovdg */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4187 { 1248 /* fmovdg */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4188 { 1248 /* fmovdg */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4189 { 1255 /* fmovdge */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4190 { 1255 /* fmovdge */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4191 { 1255 /* fmovdge */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4192 { 1263 /* fmovdgeu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4193 { 1263 /* fmovdgeu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4194 { 1272 /* fmovdgt */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4195 { 1272 /* fmovdgt */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4196 { 1280 /* fmovdgu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4197 { 1280 /* fmovdgu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4198 { 1288 /* fmovdl */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4199 { 1288 /* fmovdl */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4200 { 1288 /* fmovdl */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4201 { 1295 /* fmovdle */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4202 { 1295 /* fmovdle */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4203 { 1295 /* fmovdle */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4204 { 1303 /* fmovdleu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4205 { 1303 /* fmovdleu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4206 { 1312 /* fmovdlg */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4207 { 1320 /* fmovdlt */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4208 { 1320 /* fmovdlt */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4209 { 1328 /* fmovdlu */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4210 { 1328 /* fmovdlu */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4211 { 1336 /* fmovdn */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4212 { 1336 /* fmovdn */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4213 { 1336 /* fmovdn */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4214 { 1343 /* fmovdne */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4215 { 1343 /* fmovdne */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4216 { 1343 /* fmovdne */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4217 { 1351 /* fmovdneg */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4218 { 1351 /* fmovdneg */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4219 { 1360 /* fmovdnz */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4220 { 1360 /* fmovdnz */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4221 { 1360 /* fmovdnz */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4222 { 1368 /* fmovdo */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4223 { 1375 /* fmovdpos */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4224 { 1375 /* fmovdpos */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4225 { 1384 /* fmovdu */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4226 { 1391 /* fmovdue */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4227 { 1399 /* fmovdug */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4228 { 1407 /* fmovduge */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4229 { 1416 /* fmovdul */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4230 { 1424 /* fmovdule */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4231 { 1433 /* fmovdvc */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4232 { 1433 /* fmovdvc */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4233 { 1441 /* fmovdvs */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4234 { 1441 /* fmovdvs */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4235 { 1449 /* fmovdz */, SP::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
4236 { 1449 /* fmovdz */, SP::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_DFPRegs, MCK_DFPRegs }, },
4237 { 1449 /* fmovdz */, SP::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4238 { 1456 /* fmovq */, SP::FMOVQ, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
4239 { 1456 /* fmovq */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4240 { 1456 /* fmovq */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4241 { 1456 /* fmovq */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4242 { 1456 /* fmovq */, SP::FMOVQ_XCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4243 { 1456 /* fmovq */, SP::FMOVQ_FCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_QFPRegs, MCK_QFPRegs }, },
4244 { 1456 /* fmovq */, SP::FMOVQ_ICC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4245 { 1456 /* fmovq */, SP::V9FMOVQ_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4246 { 1462 /* fmovqa */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4247 { 1462 /* fmovqa */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4248 { 1462 /* fmovqa */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4249 { 1469 /* fmovqcc */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4250 { 1469 /* fmovqcc */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4251 { 1477 /* fmovqcs */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4252 { 1477 /* fmovqcs */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4253 { 1485 /* fmovqe */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4254 { 1485 /* fmovqe */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4255 { 1485 /* fmovqe */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4256 { 1492 /* fmovqeq */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4257 { 1492 /* fmovqeq */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4258 { 1500 /* fmovqg */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4259 { 1500 /* fmovqg */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4260 { 1500 /* fmovqg */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4261 { 1507 /* fmovqge */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4262 { 1507 /* fmovqge */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4263 { 1507 /* fmovqge */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4264 { 1515 /* fmovqgeu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4265 { 1515 /* fmovqgeu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4266 { 1524 /* fmovqgt */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4267 { 1524 /* fmovqgt */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4268 { 1532 /* fmovqgu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4269 { 1532 /* fmovqgu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4270 { 1540 /* fmovql */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4271 { 1540 /* fmovql */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4272 { 1540 /* fmovql */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4273 { 1547 /* fmovqle */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4274 { 1547 /* fmovqle */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4275 { 1547 /* fmovqle */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4276 { 1555 /* fmovqleu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4277 { 1555 /* fmovqleu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4278 { 1564 /* fmovqlg */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4279 { 1572 /* fmovqlt */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4280 { 1572 /* fmovqlt */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4281 { 1580 /* fmovqlu */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4282 { 1580 /* fmovqlu */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4283 { 1588 /* fmovqn */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4284 { 1588 /* fmovqn */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4285 { 1588 /* fmovqn */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4286 { 1595 /* fmovqne */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4287 { 1595 /* fmovqne */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4288 { 1595 /* fmovqne */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4289 { 1603 /* fmovqneg */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4290 { 1603 /* fmovqneg */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4291 { 1612 /* fmovqnz */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4292 { 1612 /* fmovqnz */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4293 { 1612 /* fmovqnz */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4294 { 1620 /* fmovqo */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4295 { 1627 /* fmovqpos */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4296 { 1627 /* fmovqpos */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4297 { 1636 /* fmovqu */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4298 { 1643 /* fmovque */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4299 { 1651 /* fmovqug */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4300 { 1659 /* fmovquge */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4301 { 1668 /* fmovqul */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4302 { 1676 /* fmovqule */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4303 { 1685 /* fmovqvc */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4304 { 1685 /* fmovqvc */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4305 { 1693 /* fmovqvs */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4306 { 1693 /* fmovqvs */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4307 { 1701 /* fmovqz */, SP::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
4308 { 1701 /* fmovqz */, SP::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_QFPRegs, MCK_QFPRegs }, },
4309 { 1701 /* fmovqz */, SP::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4310 { 1708 /* fmovrd */, SP::FMOVRD, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4311 { 1715 /* fmovrde */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4312 { 1723 /* fmovrdgez */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4313 { 1733 /* fmovrdgz */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4314 { 1742 /* fmovrdlez */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4315 { 1752 /* fmovrdlz */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4316 { 1761 /* fmovrdne */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4317 { 1770 /* fmovrdnz */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4318 { 1779 /* fmovrdz */, SP::FMOVRD, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4319 { 1787 /* fmovrq */, SP::FMOVRQ, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4320 { 1794 /* fmovrqe */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4321 { 1802 /* fmovrqgez */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4322 { 1812 /* fmovrqgz */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4323 { 1821 /* fmovrqlez */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4324 { 1831 /* fmovrqlz */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4325 { 1840 /* fmovrqne */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4326 { 1849 /* fmovrqnz */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4327 { 1858 /* fmovrqz */, SP::FMOVRQ, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4328 { 1866 /* fmovrs */, SP::FMOVRS, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4329 { 1873 /* fmovrse */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4330 { 1881 /* fmovrsgez */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4331 { 1891 /* fmovrsgz */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4332 { 1900 /* fmovrslez */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4333 { 1910 /* fmovrslz */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4334 { 1919 /* fmovrsne */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4335 { 1928 /* fmovrsnz */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4336 { 1937 /* fmovrsz */, SP::FMOVRS, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
4337 { 1945 /* fmovs */, SP::FMOVS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4338 { 1945 /* fmovs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4339 { 1945 /* fmovs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4340 { 1945 /* fmovs */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4341 { 1945 /* fmovs */, SP::FMOVS_XCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4342 { 1945 /* fmovs */, SP::FMOVS_FCC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_FPRegs, MCK_FPRegs }, },
4343 { 1945 /* fmovs */, SP::FMOVS_ICC, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4344 { 1945 /* fmovs */, SP::V9FMOVS_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4345 { 1951 /* fmovsa */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4346 { 1951 /* fmovsa */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4347 { 1951 /* fmovsa */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4348 { 1958 /* fmovscc */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4349 { 1958 /* fmovscc */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4350 { 1966 /* fmovscs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4351 { 1966 /* fmovscs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4352 { 1974 /* fmovse */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4353 { 1974 /* fmovse */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4354 { 1974 /* fmovse */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4355 { 1981 /* fmovseq */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4356 { 1981 /* fmovseq */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4357 { 1989 /* fmovsg */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4358 { 1989 /* fmovsg */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4359 { 1989 /* fmovsg */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4360 { 1996 /* fmovsge */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4361 { 1996 /* fmovsge */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4362 { 1996 /* fmovsge */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4363 { 2004 /* fmovsgeu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4364 { 2004 /* fmovsgeu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4365 { 2013 /* fmovsgt */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4366 { 2013 /* fmovsgt */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4367 { 2021 /* fmovsgu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4368 { 2021 /* fmovsgu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4369 { 2029 /* fmovsl */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4370 { 2029 /* fmovsl */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4371 { 2029 /* fmovsl */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4372 { 2036 /* fmovsle */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4373 { 2036 /* fmovsle */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4374 { 2036 /* fmovsle */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4375 { 2044 /* fmovsleu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4376 { 2044 /* fmovsleu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4377 { 2053 /* fmovslg */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4378 { 2061 /* fmovslt */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4379 { 2061 /* fmovslt */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4380 { 2069 /* fmovslu */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4381 { 2069 /* fmovslu */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4382 { 2077 /* fmovsn */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4383 { 2077 /* fmovsn */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4384 { 2077 /* fmovsn */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4385 { 2084 /* fmovsne */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4386 { 2084 /* fmovsne */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4387 { 2084 /* fmovsne */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4388 { 2092 /* fmovsneg */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4389 { 2092 /* fmovsneg */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4390 { 2101 /* fmovsnz */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4391 { 2101 /* fmovsnz */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4392 { 2101 /* fmovsnz */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4393 { 2109 /* fmovso */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4394 { 2116 /* fmovspos */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4395 { 2116 /* fmovspos */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4396 { 2125 /* fmovsu */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4397 { 2132 /* fmovsue */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4398 { 2140 /* fmovsug */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4399 { 2148 /* fmovsuge */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4400 { 2157 /* fmovsul */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4401 { 2165 /* fmovsule */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4402 { 2174 /* fmovsvc */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4403 { 2174 /* fmovsvc */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4404 { 2182 /* fmovsvs */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4405 { 2182 /* fmovsvs */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4406 { 2190 /* fmovsz */, SP::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
4407 { 2190 /* fmovsz */, SP::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_FPRegs, MCK_FPRegs }, },
4408 { 2190 /* fmovsz */, SP::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
4409 { 2197 /* fmsubd */, SP::FMSUBD, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4410 { 2204 /* fmsubs */, SP::FMSUBS, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4411 { 2211 /* fmul8sux16 */, SP::FMUL8SUX16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4412 { 2222 /* fmul8ulx16 */, SP::FMUL8ULX16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4413 { 2233 /* fmul8x16 */, SP::FMUL8X16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4414 { 2242 /* fmul8x16al */, SP::FMUL8X16AL, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
4415 { 2253 /* fmul8x16au */, SP::FMUL8X16AU, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
4416 { 2264 /* fmuld */, SP::FMULD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4417 { 2270 /* fmuld8sux16 */, SP::FMULD8SUX16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
4418 { 2282 /* fmuld8ulx16 */, SP::FMULD8ULX16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
4419 { 2294 /* fmulq */, SP::FMULQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4420 { 2300 /* fmuls */, SP::FMULS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4421 { 2306 /* fnaddd */, SP::FNADDD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4422 { 2313 /* fnadds */, SP::FNADDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4423 { 2320 /* fnand */, SP::FNAND, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4424 { 2326 /* fnands */, SP::FNANDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4425 { 2333 /* fnegd */, SP::FNEGD, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
4426 { 2339 /* fnegq */, SP::FNEGQ, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
4427 { 2345 /* fnegs */, SP::FNEGS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4428 { 2351 /* fnhaddd */, SP::FNHADDD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4429 { 2359 /* fnhadds */, SP::FNHADDS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4430 { 2367 /* fnmaddd */, SP::FNMADDD, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4431 { 2375 /* fnmadds */, SP::FNMADDS, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4432 { 2383 /* fnmsubd */, SP::FNMSUBD, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4433 { 2391 /* fnmsubs */, SP::FNMSUBS, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasUA2007, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4434 { 2399 /* fnmuld */, SP::FNMULD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4435 { 2406 /* fnmuls */, SP::FNMULS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4436 { 2413 /* fnor */, SP::FNOR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4437 { 2418 /* fnors */, SP::FNORS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4438 { 2424 /* fnot1 */, SP::FNOT1, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
4439 { 2430 /* fnot1s */, SP::FNOT1S, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
4440 { 2437 /* fnot2 */, SP::FNOT2, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
4441 { 2443 /* fnot2s */, SP::FNOT2S, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
4442 { 2450 /* fnsmuld */, SP::FNSMULD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
4443 { 2458 /* fone */, SP::FONE, Convert__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs }, },
4444 { 2463 /* fones */, SP::FONES, Convert__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs }, },
4445 { 2469 /* for */, SP::FOR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4446 { 2473 /* fornot1 */, SP::FORNOT1, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4447 { 2481 /* fornot1s */, SP::FORNOT1S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4448 { 2490 /* fornot2 */, SP::FORNOT2, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4449 { 2498 /* fornot2s */, SP::FORNOT2S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4450 { 2507 /* fors */, SP::FORS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4451 { 2512 /* fpack16 */, SP::FPACK16, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
4452 { 2520 /* fpack32 */, SP::FPACK32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4453 { 2528 /* fpackfix */, SP::FPACKFIX, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_FPRegs }, },
4454 { 2537 /* fpadd16 */, SP::FPADD16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4455 { 2545 /* fpadd16s */, SP::FPADD16S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4456 { 2554 /* fpadd32 */, SP::FPADD32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4457 { 2562 /* fpadd32s */, SP::FPADD32S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4458 { 2571 /* fpadd64 */, SP::FPADD64, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4459 { 2579 /* fpmaddx */, SP::FPMADDX, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasOSA2011, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4460 { 2587 /* fpmaddxhi */, SP::FPMADDXHI, Convert__Reg1_3__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasOSA2011, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4461 { 2597 /* fpmerge */, SP::FPMERGE, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
4462 { 2605 /* fpsub16 */, SP::FPSUB16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4463 { 2613 /* fpsub16s */, SP::FPSUB16S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4464 { 2622 /* fpsub32 */, SP::FPSUB32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4465 { 2630 /* fpsub32s */, SP::FPSUB32S, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4466 { 2639 /* fqtod */, SP::FQTOD, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_QFPRegs, MCK_DFPRegs }, },
4467 { 2645 /* fqtoi */, SP::FQTOI, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_QFPRegs, MCK_FPRegs }, },
4468 { 2651 /* fqtos */, SP::FQTOS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_QFPRegs, MCK_FPRegs }, },
4469 { 2657 /* fqtox */, SP::FQTOX, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_QFPRegs, MCK_DFPRegs }, },
4470 { 2663 /* fslas16 */, SP::FSLAS16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4471 { 2671 /* fslas32 */, SP::FSLAS32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4472 { 2679 /* fsll16 */, SP::FSLL16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4473 { 2686 /* fsll32 */, SP::FSLL32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4474 { 2693 /* fsmuld */, SP::FSMULD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
4475 { 2700 /* fsqrtd */, SP::FSQRTD, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs }, },
4476 { 2707 /* fsqrtq */, SP::FSQRTQ, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs }, },
4477 { 2714 /* fsqrts */, SP::FSQRTS, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4478 { 2721 /* fsra16 */, SP::FSRA16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4479 { 2728 /* fsra32 */, SP::FSRA32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4480 { 2735 /* fsrc1 */, SP::FSRC1, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
4481 { 2741 /* fsrc1s */, SP::FSRC1S, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
4482 { 2748 /* fsrc2 */, SP::FSRC2, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
4483 { 2754 /* fsrc2s */, SP::FSRC2S, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
4484 { 2761 /* fsrl16 */, SP::FSRL16, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4485 { 2768 /* fsrl32 */, SP::FSRL32, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4486 { 2775 /* fstod */, SP::FSTOD, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_DFPRegs }, },
4487 { 2781 /* fstoi */, SP::FSTOI, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_FPRegs }, },
4488 { 2787 /* fstoq */, SP::FSTOQ, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK_QFPRegs }, },
4489 { 2793 /* fstox */, SP::FSTOX, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_FPRegs, MCK_DFPRegs }, },
4490 { 2799 /* fsubd */, SP::FSUBD, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4491 { 2805 /* fsubq */, SP::FSUBQ, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
4492 { 2811 /* fsubs */, SP::FSUBS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4493 { 2817 /* fxnor */, SP::FXNOR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4494 { 2823 /* fxnors */, SP::FXNORS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4495 { 2830 /* fxor */, SP::FXOR, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4496 { 2835 /* fxors */, SP::FXORS, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
4497 { 2841 /* fxtod */, SP::FXTOD, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_DFPRegs, MCK_DFPRegs }, },
4498 { 2847 /* fxtoq */, SP::FXTOQ, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_DFPRegs, MCK_QFPRegs }, },
4499 { 2853 /* fxtos */, SP::FXTOS, Convert__Reg1_1__Reg1_0, AMFBS_Is64Bit, { MCK_DFPRegs, MCK_FPRegs }, },
4500 { 2859 /* fzero */, SP::FZERO, Convert__Reg1_0, AMFBS_HasVIS, { MCK_DFPRegs }, },
4501 { 2865 /* fzeros */, SP::FZEROS, Convert__Reg1_0, AMFBS_HasVIS, { MCK_FPRegs }, },
4502 { 2872 /* inc */, SP::ADDri, Convert__Reg1_0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
4503 { 2872 /* inc */, SP::ADDri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4504 { 2876 /* inccc */, SP::ADDCCri, Convert__Reg1_0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
4505 { 2876 /* inccc */, SP::ADDCCri, Convert__Reg1_1__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4506 { 2882 /* invalw */, SP::INVALW, Convert_NoOperands, AMFBS_HasUA2005, { }, },
4507 { 2889 /* jmp */, SP::JMPLri, Convert__regG0__MEMri2_0, AMFBS_None, { MCK_MEMri }, },
4508 { 2889 /* jmp */, SP::JMPLrr, Convert__regG0__MEMrr2_0, AMFBS_None, { MCK_MEMrr }, },
4509 { 2893 /* jmpl */, SP::JMPLri, Convert__Reg1_1__MEMri2_0, AMFBS_None, { MCK_MEMri, MCK_IntRegs }, },
4510 { 2893 /* jmpl */, SP::JMPLrr, Convert__Reg1_1__MEMrr2_0, AMFBS_None, { MCK_MEMrr, MCK_IntRegs }, },
4511 { 2898 /* ld */, SP::LDCSRri, Convert__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_CPSR }, },
4512 { 2898 /* ld */, SP::LDFSRri, Convert__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_FSR }, },
4513 { 2898 /* ld */, SP::LDCri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_CoprocRegs }, },
4514 { 2898 /* ld */, SP::LDFri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_FPRegs }, },
4515 { 2898 /* ld */, SP::LDri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4516 { 2898 /* ld */, SP::LDCSRrr, Convert__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_CPSR }, },
4517 { 2898 /* ld */, SP::LDFSRrr, Convert__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_FSR }, },
4518 { 2898 /* ld */, SP::LDCrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_CoprocRegs }, },
4519 { 2898 /* ld */, SP::LDFrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_FPRegs }, },
4520 { 2898 /* ld */, SP::LDrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4521 { 2898 /* ld */, SP::GDOP_LDrr, Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_GOT1_4, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs, MCK_TailRelocSymLoad_GOT }, },
4522 { 2898 /* ld */, SP::TLS_LDrr, Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_TLS1_4, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs, MCK_TailRelocSymLoad_TLS }, },
4523 { 2901 /* lda */, SP::LDFAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_FPRegs }, },
4524 { 2901 /* lda */, SP::LDAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4525 { 2901 /* lda */, SP::LDFArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_FPRegs }, },
4526 { 2901 /* lda */, SP::LDArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4527 { 2905 /* ldd */, SP::LDDCri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_CoprocPair }, },
4528 { 2905 /* ldd */, SP::LDDri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntPair }, },
4529 { 2905 /* ldd */, SP::LDDFri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_DFPRegs }, },
4530 { 2905 /* ldd */, SP::LDDCrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_CoprocPair }, },
4531 { 2905 /* ldd */, SP::LDDrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntPair }, },
4532 { 2905 /* ldd */, SP::LDDFrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_DFPRegs }, },
4533 { 2909 /* ldda */, SP::LDDAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntPair }, },
4534 { 2909 /* ldda */, SP::LDDFAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_DFPRegs }, },
4535 { 2909 /* ldda */, SP::LDDArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntPair }, },
4536 { 2909 /* ldda */, SP::LDDFArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_DFPRegs }, },
4537 { 2914 /* ldq */, SP::LDQFri, Convert__Reg1_3__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK_QFPRegs }, },
4538 { 2914 /* ldq */, SP::LDQFrr, Convert__Reg1_3__MEMrr2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_QFPRegs }, },
4539 { 2918 /* ldqa */, SP::LDQFAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_QFPRegs }, },
4540 { 2918 /* ldqa */, SP::LDQFArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_QFPRegs }, },
4541 { 2923 /* ldsb */, SP::LDSBri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4542 { 2923 /* ldsb */, SP::LDSBrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4543 { 2928 /* ldsba */, SP::LDSBAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4544 { 2928 /* ldsba */, SP::LDSBArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4545 { 2934 /* ldsh */, SP::LDSHri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4546 { 2934 /* ldsh */, SP::LDSHrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4547 { 2939 /* ldsha */, SP::LDSHAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4548 { 2939 /* ldsha */, SP::LDSHArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4549 { 2945 /* ldstub */, SP::LDSTUBri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4550 { 2945 /* ldstub */, SP::LDSTUBrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4551 { 2952 /* ldstuba */, SP::LDSTUBAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4552 { 2952 /* ldstuba */, SP::LDSTUBArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4553 { 2960 /* ldsw */, SP::LDSWri, Convert__Reg1_3__MEMri2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4554 { 2960 /* ldsw */, SP::LDSWrr, Convert__Reg1_3__MEMrr2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4555 { 2965 /* ldswa */, SP::LDSWAri, Convert__Reg1_4__MEMri2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4556 { 2965 /* ldswa */, SP::LDSWArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4557 { 2971 /* ldub */, SP::LDUBri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4558 { 2971 /* ldub */, SP::LDUBrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4559 { 2976 /* lduba */, SP::LDUBAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4560 { 2976 /* lduba */, SP::LDUBArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4561 { 2982 /* lduh */, SP::LDUHri, Convert__Reg1_3__MEMri2_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4562 { 2982 /* lduh */, SP::LDUHrr, Convert__Reg1_3__MEMrr2_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4563 { 2987 /* lduha */, SP::LDUHAri, Convert__Reg1_4__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4564 { 2987 /* lduha */, SP::LDUHArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4565 { 2993 /* ldx */, SP::LDXFSRri, Convert__MEMri2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK_FSR }, },
4566 { 2993 /* ldx */, SP::LDXri, Convert__Reg1_3__MEMri2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4567 { 2993 /* ldx */, SP::LDXFSRrr, Convert__MEMrr2_1, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_FSR }, },
4568 { 2993 /* ldx */, SP::LDXrr, Convert__Reg1_3__MEMrr2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4569 { 2993 /* ldx */, SP::GDOP_LDXrr, Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_GOT1_4, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs, MCK_TailRelocSymLoad_GOT }, },
4570 { 2993 /* ldx */, SP::TLS_LDXrr, Convert__Reg1_3__MEMrr2_1__TailRelocSymLoad_TLS1_4, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs, MCK_TailRelocSymLoad_TLS }, },
4571 { 2997 /* ldxa */, SP::LDXAri, Convert__Reg1_4__MEMri2_1, AMFBS_Is64Bit, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4572 { 2997 /* ldxa */, SP::LDXArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3, AMFBS_Is64Bit, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4573 { 3002 /* lzcnt */, SP::LZCNT, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs }, },
4574 { 3008 /* membar */, SP::MEMBARi, Convert__MembarTag1_0, AMFBS_HasV9, { MCK_MembarTag }, },
4575 { 3015 /* mov */, SP::RDPSR, Convert__Reg1_1, AMFBS_None, { MCK_PSR, MCK_IntRegs }, },
4576 { 3015 /* mov */, SP::RDTBR, Convert__Reg1_1, AMFBS_None, { MCK_TBR, MCK_IntRegs }, },
4577 { 3015 /* mov */, SP::RDWIM, Convert__Reg1_1, AMFBS_None, { MCK_WIM, MCK_IntRegs }, },
4578 { 3015 /* mov */, SP::WRPSRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_PSR }, },
4579 { 3015 /* mov */, SP::WRTBRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_TBR }, },
4580 { 3015 /* mov */, SP::WRWIMrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_WIM }, },
4581 { 3015 /* mov */, SP::ORrr, Convert__Reg1_1__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
4582 { 3015 /* mov */, SP::WRASRrr, Convert__Reg1_1__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_ASRRegs }, },
4583 { 3015 /* mov */, SP::RDASR, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_ASRRegs, MCK_IntRegs }, },
4584 { 3015 /* mov */, SP::WRPSRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_PSR }, },
4585 { 3015 /* mov */, SP::WRTBRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_TBR }, },
4586 { 3015 /* mov */, SP::WRWIMri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_WIM }, },
4587 { 3015 /* mov */, SP::ORri, Convert__Reg1_1__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4588 { 3015 /* mov */, SP::WRASRri, Convert__Reg1_1__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_ASRRegs }, },
4589 { 3015 /* mov */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4590 { 3015 /* mov */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4591 { 3015 /* mov */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4592 { 3015 /* mov */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4593 { 3015 /* mov */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4594 { 3015 /* mov */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4595 { 3015 /* mov */, SP::MOVXCCrr, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4596 { 3015 /* mov */, SP::MOVXCCri, Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4597 { 3015 /* mov */, SP::MOVFCCrr, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_IntRegs, MCK_IntRegs }, },
4598 { 3015 /* mov */, SP::MOVFCCri, Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCC0, MCK_Imm, MCK_IntRegs }, },
4599 { 3015 /* mov */, SP::MOVICCrr, Convert__Reg1_3__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4600 { 3015 /* mov */, SP::MOVICCri, Convert__Reg1_3__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4601 { 3015 /* mov */, SP::V9MOVFCCrr, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4602 { 3015 /* mov */, SP::V9MOVFCCri, Convert__Reg1_3__Reg1_1__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4603 { 3019 /* mova */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4604 { 3019 /* mova */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4605 { 3019 /* mova */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4606 { 3019 /* mova */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4607 { 3019 /* mova */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4608 { 3019 /* mova */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_8, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4609 { 3024 /* movcc */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4610 { 3024 /* movcc */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4611 { 3024 /* movcc */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4612 { 3024 /* movcc */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4613 { 3030 /* movcs */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4614 { 3030 /* movcs */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4615 { 3030 /* movcs */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4616 { 3030 /* movcs */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4617 { 3036 /* movdtox */, SP::MOVDTOX, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_IntRegs }, },
4618 { 3044 /* move */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4619 { 3044 /* move */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4620 { 3044 /* move */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4621 { 3044 /* move */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4622 { 3044 /* move */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4623 { 3044 /* move */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4624 { 3049 /* moveq */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4625 { 3049 /* moveq */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4626 { 3049 /* moveq */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4627 { 3049 /* moveq */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4628 { 3055 /* movg */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4629 { 3055 /* movg */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4630 { 3055 /* movg */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4631 { 3055 /* movg */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4632 { 3055 /* movg */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4633 { 3055 /* movg */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4634 { 3060 /* movge */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4635 { 3060 /* movge */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4636 { 3060 /* movge */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4637 { 3060 /* movge */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4638 { 3060 /* movge */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4639 { 3060 /* movge */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_11, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4640 { 3066 /* movgeu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4641 { 3066 /* movgeu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4642 { 3066 /* movgeu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4643 { 3066 /* movgeu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4644 { 3073 /* movgt */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4645 { 3073 /* movgt */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4646 { 3073 /* movgt */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4647 { 3073 /* movgt */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4648 { 3079 /* movgu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4649 { 3079 /* movgu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4650 { 3079 /* movgu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4651 { 3079 /* movgu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4652 { 3085 /* movl */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4653 { 3085 /* movl */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4654 { 3085 /* movl */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4655 { 3085 /* movl */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4656 { 3085 /* movl */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4657 { 3085 /* movl */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4658 { 3090 /* movle */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4659 { 3090 /* movle */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4660 { 3090 /* movle */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4661 { 3090 /* movle */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4662 { 3090 /* movle */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4663 { 3090 /* movle */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_13, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4664 { 3096 /* movleu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4665 { 3096 /* movleu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4666 { 3096 /* movleu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4667 { 3096 /* movleu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4668 { 3103 /* movlg */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4669 { 3103 /* movlg */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4670 { 3109 /* movlt */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4671 { 3109 /* movlt */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4672 { 3109 /* movlt */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4673 { 3109 /* movlt */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4674 { 3115 /* movlu */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4675 { 3115 /* movlu */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4676 { 3115 /* movlu */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4677 { 3115 /* movlu */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4678 { 3121 /* movn */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4679 { 3121 /* movn */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4680 { 3121 /* movn */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4681 { 3121 /* movn */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4682 { 3121 /* movn */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4683 { 3121 /* movn */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_0, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4684 { 3126 /* movne */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4685 { 3126 /* movne */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4686 { 3126 /* movne */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4687 { 3126 /* movne */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4688 { 3126 /* movne */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4689 { 3126 /* movne */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4690 { 3132 /* movneg */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4691 { 3132 /* movneg */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4692 { 3132 /* movneg */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4693 { 3132 /* movneg */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4694 { 3139 /* movnz */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4695 { 3139 /* movnz */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4696 { 3139 /* movnz */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4697 { 3139 /* movnz */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4698 { 3139 /* movnz */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4699 { 3139 /* movnz */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4700 { 3145 /* movo */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4701 { 3145 /* movo */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4702 { 3150 /* movpos */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4703 { 3150 /* movpos */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4704 { 3150 /* movpos */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4705 { 3150 /* movpos */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4706 { 3157 /* movr */, SP::MOVRrr, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4707 { 3157 /* movr */, SP::MOVRri, Convert__Reg1_3__Reg1_1__Imm1_2__Tie0_1_1__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4708 { 3162 /* movre */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4709 { 3162 /* movre */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4710 { 3168 /* movrgez */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4711 { 3168 /* movrgez */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4712 { 3176 /* movrgz */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4713 { 3176 /* movrgz */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_6, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4714 { 3183 /* movrlez */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4715 { 3183 /* movrlez */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_2, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4716 { 3191 /* movrlz */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4717 { 3191 /* movrlz */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4718 { 3198 /* movrne */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4719 { 3198 /* movrne */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4720 { 3205 /* movrnz */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4721 { 3205 /* movrnz */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4722 { 3212 /* movrz */, SP::MOVRrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4723 { 3212 /* movrz */, SP::MOVRri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4724 { 3218 /* movstosw */, SP::MOVSTOSW, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_FPRegs, MCK_IntRegs }, },
4725 { 3227 /* movstouw */, SP::MOVSTOUW, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_FPRegs, MCK_IntRegs }, },
4726 { 3236 /* movu */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4727 { 3236 /* movu */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4728 { 3241 /* movue */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4729 { 3241 /* movue */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_10, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4730 { 3247 /* movug */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4731 { 3247 /* movug */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_5, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4732 { 3253 /* movuge */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4733 { 3253 /* movuge */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_12, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4734 { 3260 /* movul */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4735 { 3260 /* movul */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_3, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4736 { 3266 /* movule */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4737 { 3266 /* movule */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_14, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4738 { 3273 /* movvc */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4739 { 3273 /* movvc */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4740 { 3273 /* movvc */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4741 { 3273 /* movvc */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4742 { 3279 /* movvs */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4743 { 3279 /* movvs */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4744 { 3279 /* movvs */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4745 { 3279 /* movvs */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4746 { 3285 /* movwtos */, SP::MOVWTOS, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs, MCK_FPRegs }, },
4747 { 3293 /* movxtod */, SP::MOVXTOD, Convert__Reg1_1__Reg1_0, AMFBS_HasVIS3, { MCK_IntRegs, MCK_DFPRegs }, },
4748 { 3301 /* movz */, SP::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
4749 { 3301 /* movz */, SP::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_Is64Bit, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
4750 { 3301 /* movz */, SP::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK_IntRegs }, },
4751 { 3301 /* movz */, SP::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0_3_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm, MCK_IntRegs }, },
4752 { 3301 /* movz */, SP::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
4753 { 3301 /* movz */, SP::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0_3_3__imm_95_9, AMFBS_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
4754 { 3306 /* mulscc */, SP::MULSCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4755 { 3306 /* mulscc */, SP::MULSCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4756 { 3313 /* mulx */, SP::MULXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4757 { 3313 /* mulx */, SP::MULXri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4758 { 3318 /* neg */, SP::SUBrr, Convert__Reg1_0__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs }, },
4759 { 3318 /* neg */, SP::SUBrr, Convert__Reg1_1__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
4760 { 3322 /* nop */, SP::NOP, Convert_NoOperands, AMFBS_None, { }, },
4761 { 3326 /* normalw */, SP::NORMALW, Convert_NoOperands, AMFBS_HasUA2005, { }, },
4762 { 3334 /* not */, SP::XNORrr, Convert__Reg1_0__Reg1_0__regG0, AMFBS_None, { MCK_IntRegs }, },
4763 { 3334 /* not */, SP::XNORrr, Convert__Reg1_1__Reg1_0__regG0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs }, },
4764 { 3338 /* or */, SP::ORrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4765 { 3338 /* or */, SP::ORri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4766 { 3338 /* or */, SP::ORri, Convert__Reg1_2__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK_IntRegs }, },
4767 { 3341 /* orcc */, SP::ORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4768 { 3341 /* orcc */, SP::ORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4769 { 3346 /* orn */, SP::ORNrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4770 { 3346 /* orn */, SP::ORNri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4771 { 3350 /* orncc */, SP::ORNCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4772 { 3350 /* orncc */, SP::ORNCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4773 { 3356 /* otherw */, SP::OTHERW, Convert_NoOperands, AMFBS_HasUA2005, { }, },
4774 { 3363 /* pause */, SP::WRASRrr, Convert__regASR27__regG0__Reg1_0, AMFBS_HasOSA2011, { MCK_IntRegs }, },
4775 { 3363 /* pause */, SP::WRASRri, Convert__regASR27__regG0__Imm1_0, AMFBS_HasOSA2011, { MCK_Imm }, },
4776 { 3369 /* pdist */, SP::PDIST, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
4777 { 3375 /* pdistn */, SP::PDISTN, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
4778 { 3382 /* popc */, SP::POPCrr, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_IntRegs, MCK_IntRegs }, },
4779 { 3387 /* prefetch */, SP::PREFETCHi, Convert__MEMri2_1__PrefetchTag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK_PrefetchTag }, },
4780 { 3387 /* prefetch */, SP::PREFETCHr, Convert__MEMrr2_1__PrefetchTag1_3, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_PrefetchTag }, },
4781 { 3396 /* prefetcha */, SP::PREFETCHAi, Convert__MEMri2_1__PrefetchTag1_4, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_PrefetchTag }, },
4782 { 3396 /* prefetcha */, SP::PREFETCHAr, Convert__MEMrr2_1__ASITag1_3__PrefetchTag1_4, AMFBS_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_PrefetchTag }, },
4783 { 3406 /* pwr */, SP::PWRPSRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_PSR }, },
4784 { 3406 /* pwr */, SP::PWRPSRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_PSR }, },
4785 { 3406 /* pwr */, SP::PWRPSRrr, Convert__Reg1_0__Reg1_1, AMFBS_HasPWRPSR, { MCK_IntRegs, MCK_IntRegs, MCK_PSR }, },
4786 { 3406 /* pwr */, SP::PWRPSRri, Convert__Reg1_0__Imm1_1, AMFBS_HasPWRPSR, { MCK_IntRegs, MCK_Imm, MCK_PSR }, },
4787 { 3410 /* rd */, SP::RDPSR, Convert__Reg1_1, AMFBS_None, { MCK_PSR, MCK_IntRegs }, },
4788 { 3410 /* rd */, SP::RDTBR, Convert__Reg1_1, AMFBS_None, { MCK_TBR, MCK_IntRegs }, },
4789 { 3410 /* rd */, SP::RDWIM, Convert__Reg1_1, AMFBS_None, { MCK_WIM, MCK_IntRegs }, },
4790 { 3410 /* rd */, SP::RDASR, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_ASRRegs, MCK_IntRegs }, },
4791 { 3413 /* rdpr */, SP::RDFQ, Convert__Reg1_1, AMFBS_HasV9, { MCK_FQ, MCK_IntRegs }, },
4792 { 3413 /* rdpr */, SP::RDPR, Convert__Reg1_1__Reg1_0, AMFBS_HasV9, { MCK_PRRegs, MCK_IntRegs }, },
4793 { 3418 /* restore */, SP::RESTORErr, Convert__regG0__regG0__regG0, AMFBS_None, { }, },
4794 { 3418 /* restore */, SP::RESTORErr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4795 { 3418 /* restore */, SP::RESTOREri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4796 { 3426 /* restored */, SP::RESTORED, Convert_NoOperands, AMFBS_HasV9, { }, },
4797 { 3435 /* ret */, SP::RET, Convert__imm_95_8, AMFBS_None, { }, },
4798 { 3439 /* retl */, SP::RETL, Convert__imm_95_8, AMFBS_None, { }, },
4799 { 3444 /* retry */, SP::RETRY, Convert_NoOperands, AMFBS_HasV9, { }, },
4800 { 3450 /* rett */, SP::RETTri, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, },
4801 { 3450 /* rett */, SP::RETTrr, Convert__MEMrr2_0, AMFBS_None, { MCK_MEMrr }, },
4802 { 3455 /* save */, SP::SAVErr, Convert__regG0__regG0__regG0, AMFBS_None, { }, },
4803 { 3455 /* save */, SP::SAVErr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4804 { 3455 /* save */, SP::SAVEri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4805 { 3460 /* saved */, SP::SAVED, Convert_NoOperands, AMFBS_HasV9, { }, },
4806 { 3466 /* sdiv */, SP::SDIVrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4807 { 3466 /* sdiv */, SP::SDIVri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4808 { 3471 /* sdivcc */, SP::SDIVCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4809 { 3471 /* sdivcc */, SP::SDIVCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4810 { 3478 /* sdivx */, SP::SDIVXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4811 { 3478 /* sdivx */, SP::SDIVXri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4812 { 3484 /* set */, SP::SET, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4813 { 3488 /* sethi */, SP::SETHIi, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs }, },
4814 { 3494 /* setsw */, SP::SETSW, Convert__Reg1_1__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_IntRegs }, },
4815 { 3500 /* setx */, SP::SETX, Convert__Reg1_2__Imm1_0__Reg1_1, AMFBS_Is64Bit_HasV9, { MCK_Imm, MCK_IntRegs, MCK_IntRegs }, },
4816 { 3505 /* shutdown */, SP::SHUTDOWN, Convert_NoOperands, AMFBS_HasVIS, { }, },
4817 { 3514 /* siam */, SP::SIAM, Convert__Imm1_0, AMFBS_HasVIS2, { MCK_Imm }, },
4818 { 3519 /* signx */, SP::SRArr, Convert__Reg1_0__Reg1_0__regG0, AMFBS_HasV9, { MCK_IntRegs }, },
4819 { 3519 /* signx */, SP::SRArr, Convert__Reg1_1__Reg1_0__regG0, AMFBS_HasV9, { MCK_IntRegs, MCK_IntRegs }, },
4820 { 3525 /* sir */, SP::SIR, Convert__imm_95_0, AMFBS_None, { }, },
4821 { 3525 /* sir */, SP::SIR, Convert__Imm1_0, AMFBS_HasV9, { MCK_Imm }, },
4822 { 3529 /* sll */, SP::SLLrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4823 { 3529 /* sll */, SP::SLLri, Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1, AMFBS_None, { MCK_IntRegs, MCK_ShiftAmtImm5, MCK_IntRegs }, },
4824 { 3533 /* sllx */, SP::SLLXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4825 { 3533 /* sllx */, SP::SLLXri, Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_ShiftAmtImm6, MCK_IntRegs }, },
4826 { 3538 /* smac */, SP::SMACrr, Convert__Reg1_2__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4827 { 3538 /* smac */, SP::SMACri, Convert__Reg1_2__Reg1_0__Imm1_1__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4828 { 3543 /* smul */, SP::SMULrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4829 { 3543 /* smul */, SP::SMULri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4830 { 3548 /* smulcc */, SP::SMULCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4831 { 3548 /* smulcc */, SP::SMULCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4832 { 3555 /* sra */, SP::SRArr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4833 { 3555 /* sra */, SP::SRAri, Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1, AMFBS_None, { MCK_IntRegs, MCK_ShiftAmtImm5, MCK_IntRegs }, },
4834 { 3559 /* srax */, SP::SRAXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4835 { 3559 /* srax */, SP::SRAXri, Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_ShiftAmtImm6, MCK_IntRegs }, },
4836 { 3564 /* srl */, SP::SRLrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4837 { 3564 /* srl */, SP::SRLri, Convert__Reg1_2__Reg1_0__ShiftAmtImm51_1, AMFBS_None, { MCK_IntRegs, MCK_ShiftAmtImm5, MCK_IntRegs }, },
4838 { 3568 /* srlx */, SP::SRLXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4839 { 3568 /* srlx */, SP::SRLXri, Convert__Reg1_2__Reg1_0__ShiftAmtImm61_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_ShiftAmtImm6, MCK_IntRegs }, },
4840 { 3573 /* st */, SP::STCSRri, Convert__MEMri2_2, AMFBS_None, { MCK_CPSR, MCK__91_, MCK_MEMri, MCK__93_ }, },
4841 { 3573 /* st */, SP::STCSRrr, Convert__MEMrr2_2, AMFBS_None, { MCK_CPSR, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4842 { 3573 /* st */, SP::STFSRri, Convert__MEMri2_2, AMFBS_None, { MCK_FSR, MCK__91_, MCK_MEMri, MCK__93_ }, },
4843 { 3573 /* st */, SP::STFSRrr, Convert__MEMrr2_2, AMFBS_None, { MCK_FSR, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4844 { 3573 /* st */, SP::STCri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_CoprocRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
4845 { 3573 /* st */, SP::STCrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_CoprocRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4846 { 3573 /* st */, SP::STFri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
4847 { 3573 /* st */, SP::STFrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_FPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4848 { 3573 /* st */, SP::STri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
4849 { 3573 /* st */, SP::STrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4850 { 3576 /* sta */, SP::STFAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_FPRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
4851 { 3576 /* sta */, SP::STFArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_HasV9, { MCK_FPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
4852 { 3576 /* sta */, SP::STAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
4853 { 3576 /* sta */, SP::STArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
4854 { 3580 /* stb */, SP::STBri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
4855 { 3580 /* stb */, SP::STBrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4856 { 3584 /* stba */, SP::STBAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
4857 { 3584 /* stba */, SP::STBArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
4858 { 3589 /* stbar */, SP::STBAR, Convert_NoOperands, AMFBS_None, { }, },
4859 { 3595 /* std */, SP::STDCQri, Convert__MEMri2_2, AMFBS_None, { MCK_CPQ, MCK__91_, MCK_MEMri, MCK__93_ }, },
4860 { 3595 /* std */, SP::STDCQrr, Convert__MEMrr2_2, AMFBS_None, { MCK_CPQ, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4861 { 3595 /* std */, SP::STDFQri, Convert__MEMri2_2, AMFBS_None, { MCK_FQ, MCK__91_, MCK_MEMri, MCK__93_ }, },
4862 { 3595 /* std */, SP::STDFQrr, Convert__MEMrr2_2, AMFBS_None, { MCK_FQ, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4863 { 3595 /* std */, SP::STDCri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_CoprocPair, MCK__91_, MCK_MEMri, MCK__93_ }, },
4864 { 3595 /* std */, SP::STDCrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_CoprocPair, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4865 { 3595 /* std */, SP::STDri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_IntPair, MCK__91_, MCK_MEMri, MCK__93_ }, },
4866 { 3595 /* std */, SP::STDrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_IntPair, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4867 { 3595 /* std */, SP::STDFri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
4868 { 3595 /* std */, SP::STDFrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_DFPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4869 { 3599 /* stda */, SP::STDAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_IntPair, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
4870 { 3599 /* stda */, SP::STDArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_None, { MCK_IntPair, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
4871 { 3599 /* stda */, SP::STDFAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_DFPRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
4872 { 3599 /* stda */, SP::STDFArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_HasV9, { MCK_DFPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
4873 { 3604 /* sth */, SP::STHri, Convert__MEMri2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
4874 { 3604 /* sth */, SP::STHrr, Convert__MEMrr2_2__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4875 { 3608 /* stha */, SP::STHAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
4876 { 3608 /* stha */, SP::STHArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_None, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
4877 { 3613 /* stq */, SP::STQFri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
4878 { 3613 /* stq */, SP::STQFrr, Convert__MEMrr2_2__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4879 { 3617 /* stqa */, SP::STQFAri, Convert__MEMri2_2__Reg1_0, AMFBS_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
4880 { 3617 /* stqa */, SP::STQFArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
4881 { 3622 /* stx */, SP::STXFSRri, Convert__MEMri2_2, AMFBS_HasV9, { MCK_FSR, MCK__91_, MCK_MEMri, MCK__93_ }, },
4882 { 3622 /* stx */, SP::STXFSRrr, Convert__MEMrr2_2, AMFBS_HasV9, { MCK_FSR, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4883 { 3622 /* stx */, SP::STXri, Convert__MEMri2_2__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
4884 { 3622 /* stx */, SP::STXrr, Convert__MEMrr2_2__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
4885 { 3626 /* stxa */, SP::STXAri, Convert__MEMri2_2__Reg1_0, AMFBS_Is64Bit, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi }, },
4886 { 3626 /* stxa */, SP::STXArr, Convert__MEMrr2_2__Reg1_0__ASITag1_4, AMFBS_Is64Bit, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag }, },
4887 { 3631 /* sub */, SP::SUBrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4888 { 3631 /* sub */, SP::SUBri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4889 { 3635 /* subcc */, SP::SUBCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4890 { 3635 /* subcc */, SP::SUBCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4891 { 3641 /* subx */, SP::SUBCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4892 { 3641 /* subx */, SP::SUBCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4893 { 3646 /* subxcc */, SP::SUBErr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4894 { 3646 /* subxcc */, SP::SUBEri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4895 { 3653 /* swap */, SP::SWAPri, Convert__Reg1_3__MEMri2_1__Tie0_1_1, AMFBS_None, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
4896 { 3653 /* swap */, SP::SWAPrr, Convert__Reg1_3__MEMrr2_1__Tie0_1_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
4897 { 3658 /* swapa */, SP::SWAPAri, Convert__Reg1_4__MEMri2_1__Tie0_1_1, AMFBS_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_asi, MCK_IntRegs }, },
4898 { 3658 /* swapa */, SP::SWAPArr, Convert__Reg1_4__MEMrr2_1__ASITag1_3__Tie0_1_1, AMFBS_None, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_ASITag, MCK_IntRegs }, },
4899 { 3664 /* t */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_8, AMFBS_None, { MCK_IntRegs }, },
4900 { 3664 /* t */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
4901 { 3664 /* t */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
4902 { 3664 /* t */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
4903 { 3664 /* t */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
4904 { 3664 /* t */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4905 { 3664 /* t */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_8, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4906 { 3664 /* t */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_8, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
4907 { 3664 /* t */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4908 { 3664 /* t */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4909 { 3664 /* t */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4910 { 3664 /* t */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4911 { 3664 /* t */, SP::TRAPrr, Convert__Reg1_1__Reg1_3__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4912 { 3664 /* t */, SP::TRAPri, Convert__Reg1_1__Imm1_3__Imm1_0, AMFBS_None, { MCK_Imm, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4913 { 3664 /* t */, SP::TXCCrr, Convert__Reg1_2__Reg1_4__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4914 { 3664 /* t */, SP::TXCCri, Convert__Reg1_2__Imm1_4__Imm1_0, AMFBS_Is64Bit, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4915 { 3664 /* t */, SP::TICCrr, Convert__Reg1_2__Reg1_4__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4916 { 3664 /* t */, SP::TICCri, Convert__Reg1_2__Imm1_4__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4917 { 3666 /* ta */, SP::TA1, Convert_NoOperands, AMFBS_None, { MCK_1 }, },
4918 { 3666 /* ta */, SP::TA3, Convert_NoOperands, AMFBS_None, { MCK_3 }, },
4919 { 3666 /* ta */, SP::TA5, Convert_NoOperands, AMFBS_None, { MCK_5 }, },
4920 { 3666 /* ta */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_8, AMFBS_None, { MCK_IntRegs }, },
4921 { 3666 /* ta */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_8, AMFBS_None, { MCK_Imm }, },
4922 { 3666 /* ta */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
4923 { 3666 /* ta */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
4924 { 3666 /* ta */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
4925 { 3666 /* ta */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4926 { 3666 /* ta */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_8, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4927 { 3666 /* ta */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_8, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
4928 { 3666 /* ta */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4929 { 3666 /* ta */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4930 { 3666 /* ta */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4931 { 3666 /* ta */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_8, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4932 { 3669 /* taddcc */, SP::TADDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4933 { 3669 /* taddcc */, SP::TADDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4934 { 3676 /* taddcctv */, SP::TADDCCTVrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
4935 { 3676 /* taddcctv */, SP::TADDCCTVri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
4936 { 3685 /* tcc */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_13, AMFBS_None, { MCK_IntRegs }, },
4937 { 3685 /* tcc */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
4938 { 3685 /* tcc */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
4939 { 3685 /* tcc */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
4940 { 3685 /* tcc */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
4941 { 3685 /* tcc */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4942 { 3685 /* tcc */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_13, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4943 { 3685 /* tcc */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_13, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
4944 { 3685 /* tcc */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4945 { 3685 /* tcc */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4946 { 3685 /* tcc */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4947 { 3685 /* tcc */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4948 { 3689 /* tcs */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_5, AMFBS_None, { MCK_IntRegs }, },
4949 { 3689 /* tcs */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
4950 { 3689 /* tcs */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
4951 { 3689 /* tcs */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
4952 { 3689 /* tcs */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
4953 { 3689 /* tcs */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4954 { 3689 /* tcs */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_5, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4955 { 3689 /* tcs */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_5, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
4956 { 3689 /* tcs */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4957 { 3689 /* tcs */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4958 { 3689 /* tcs */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4959 { 3689 /* tcs */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4960 { 3693 /* te */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
4961 { 3693 /* te */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
4962 { 3693 /* te */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
4963 { 3693 /* te */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
4964 { 3693 /* te */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
4965 { 3693 /* te */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4966 { 3693 /* te */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4967 { 3693 /* te */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
4968 { 3693 /* te */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4969 { 3693 /* te */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4970 { 3693 /* te */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4971 { 3693 /* te */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4972 { 3696 /* teq */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
4973 { 3696 /* teq */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
4974 { 3696 /* teq */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
4975 { 3696 /* teq */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
4976 { 3696 /* teq */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
4977 { 3696 /* teq */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4978 { 3696 /* teq */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4979 { 3696 /* teq */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
4980 { 3696 /* teq */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4981 { 3696 /* teq */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4982 { 3696 /* teq */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4983 { 3696 /* teq */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4984 { 3700 /* tg */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_10, AMFBS_None, { MCK_IntRegs }, },
4985 { 3700 /* tg */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
4986 { 3700 /* tg */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
4987 { 3700 /* tg */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
4988 { 3700 /* tg */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
4989 { 3700 /* tg */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
4990 { 3700 /* tg */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_10, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4991 { 3700 /* tg */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_10, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
4992 { 3700 /* tg */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4993 { 3700 /* tg */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4994 { 3700 /* tg */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
4995 { 3700 /* tg */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
4996 { 3703 /* tge */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_11, AMFBS_None, { MCK_IntRegs }, },
4997 { 3703 /* tge */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_11, AMFBS_None, { MCK_Imm }, },
4998 { 3703 /* tge */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_11, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
4999 { 3703 /* tge */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_11, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5000 { 3703 /* tge */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5001 { 3703 /* tge */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5002 { 3703 /* tge */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_11, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5003 { 3703 /* tge */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_11, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5004 { 3703 /* tge */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_11, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5005 { 3703 /* tge */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_11, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5006 { 3703 /* tge */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5007 { 3703 /* tge */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_11, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5008 { 3707 /* tgeu */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_13, AMFBS_None, { MCK_IntRegs }, },
5009 { 3707 /* tgeu */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_13, AMFBS_None, { MCK_Imm }, },
5010 { 3707 /* tgeu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5011 { 3707 /* tgeu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5012 { 3707 /* tgeu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5013 { 3707 /* tgeu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5014 { 3707 /* tgeu */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_13, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5015 { 3707 /* tgeu */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_13, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5016 { 3707 /* tgeu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5017 { 3707 /* tgeu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5018 { 3707 /* tgeu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5019 { 3707 /* tgeu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_13, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5020 { 3712 /* tgt */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_10, AMFBS_None, { MCK_IntRegs }, },
5021 { 3712 /* tgt */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_10, AMFBS_None, { MCK_Imm }, },
5022 { 3712 /* tgt */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5023 { 3712 /* tgt */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5024 { 3712 /* tgt */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5025 { 3712 /* tgt */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5026 { 3712 /* tgt */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_10, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5027 { 3712 /* tgt */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_10, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5028 { 3712 /* tgt */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5029 { 3712 /* tgt */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5030 { 3712 /* tgt */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5031 { 3712 /* tgt */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_10, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5032 { 3716 /* tgu */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_12, AMFBS_None, { MCK_IntRegs }, },
5033 { 3716 /* tgu */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_12, AMFBS_None, { MCK_Imm }, },
5034 { 3716 /* tgu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_12, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5035 { 3716 /* tgu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_12, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5036 { 3716 /* tgu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5037 { 3716 /* tgu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5038 { 3716 /* tgu */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_12, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5039 { 3716 /* tgu */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_12, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5040 { 3716 /* tgu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_12, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5041 { 3716 /* tgu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_12, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5042 { 3716 /* tgu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5043 { 3716 /* tgu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_12, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5044 { 3720 /* tl */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_3, AMFBS_None, { MCK_IntRegs }, },
5045 { 3720 /* tl */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
5046 { 3720 /* tl */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5047 { 3720 /* tl */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5048 { 3720 /* tl */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5049 { 3720 /* tl */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5050 { 3720 /* tl */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_3, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5051 { 3720 /* tl */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_3, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5052 { 3720 /* tl */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5053 { 3720 /* tl */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5054 { 3720 /* tl */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5055 { 3720 /* tl */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5056 { 3723 /* tle */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_2, AMFBS_None, { MCK_IntRegs }, },
5057 { 3723 /* tle */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_2, AMFBS_None, { MCK_Imm }, },
5058 { 3723 /* tle */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_2, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5059 { 3723 /* tle */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_2, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5060 { 3723 /* tle */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5061 { 3723 /* tle */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5062 { 3723 /* tle */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_2, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5063 { 3723 /* tle */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_2, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5064 { 3723 /* tle */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_2, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5065 { 3723 /* tle */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_2, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5066 { 3723 /* tle */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5067 { 3723 /* tle */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_2, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5068 { 3727 /* tleu */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_4, AMFBS_None, { MCK_IntRegs }, },
5069 { 3727 /* tleu */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_4, AMFBS_None, { MCK_Imm }, },
5070 { 3727 /* tleu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_4, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5071 { 3727 /* tleu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_4, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5072 { 3727 /* tleu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5073 { 3727 /* tleu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5074 { 3727 /* tleu */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_4, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5075 { 3727 /* tleu */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_4, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5076 { 3727 /* tleu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_4, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5077 { 3727 /* tleu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_4, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5078 { 3727 /* tleu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5079 { 3727 /* tleu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_4, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5080 { 3732 /* tlt */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_3, AMFBS_None, { MCK_IntRegs }, },
5081 { 3732 /* tlt */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_3, AMFBS_None, { MCK_Imm }, },
5082 { 3732 /* tlt */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5083 { 3732 /* tlt */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5084 { 3732 /* tlt */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5085 { 3732 /* tlt */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5086 { 3732 /* tlt */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_3, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5087 { 3732 /* tlt */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_3, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5088 { 3732 /* tlt */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5089 { 3732 /* tlt */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5090 { 3732 /* tlt */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5091 { 3732 /* tlt */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_3, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5092 { 3736 /* tlu */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_5, AMFBS_None, { MCK_IntRegs }, },
5093 { 3736 /* tlu */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_5, AMFBS_None, { MCK_Imm }, },
5094 { 3736 /* tlu */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5095 { 3736 /* tlu */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5096 { 3736 /* tlu */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5097 { 3736 /* tlu */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5098 { 3736 /* tlu */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_5, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5099 { 3736 /* tlu */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_5, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5100 { 3736 /* tlu */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5101 { 3736 /* tlu */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5102 { 3736 /* tlu */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5103 { 3736 /* tlu */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_5, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5104 { 3740 /* tn */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_0, AMFBS_None, { MCK_IntRegs }, },
5105 { 3740 /* tn */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_0, AMFBS_None, { MCK_Imm }, },
5106 { 3740 /* tn */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_0, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5107 { 3740 /* tn */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_0, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5108 { 3740 /* tn */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5109 { 3740 /* tn */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5110 { 3740 /* tn */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5111 { 3740 /* tn */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5112 { 3740 /* tn */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_0, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5113 { 3740 /* tn */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_0, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5114 { 3740 /* tn */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5115 { 3740 /* tn */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_0, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5116 { 3743 /* tne */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_9, AMFBS_None, { MCK_IntRegs }, },
5117 { 3743 /* tne */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
5118 { 3743 /* tne */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5119 { 3743 /* tne */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5120 { 3743 /* tne */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5121 { 3743 /* tne */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5122 { 3743 /* tne */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_9, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5123 { 3743 /* tne */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_9, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5124 { 3743 /* tne */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5125 { 3743 /* tne */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5126 { 3743 /* tne */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5127 { 3743 /* tne */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5128 { 3747 /* tneg */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_6, AMFBS_None, { MCK_IntRegs }, },
5129 { 3747 /* tneg */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_6, AMFBS_None, { MCK_Imm }, },
5130 { 3747 /* tneg */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_6, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5131 { 3747 /* tneg */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_6, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5132 { 3747 /* tneg */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5133 { 3747 /* tneg */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5134 { 3747 /* tneg */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_6, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5135 { 3747 /* tneg */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_6, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5136 { 3747 /* tneg */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_6, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5137 { 3747 /* tneg */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_6, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5138 { 3747 /* tneg */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5139 { 3747 /* tneg */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_6, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5140 { 3752 /* tnz */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_9, AMFBS_None, { MCK_IntRegs }, },
5141 { 3752 /* tnz */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_9, AMFBS_None, { MCK_Imm }, },
5142 { 3752 /* tnz */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5143 { 3752 /* tnz */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5144 { 3752 /* tnz */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5145 { 3752 /* tnz */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5146 { 3752 /* tnz */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_9, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5147 { 3752 /* tnz */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_9, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5148 { 3752 /* tnz */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5149 { 3752 /* tnz */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5150 { 3752 /* tnz */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5151 { 3752 /* tnz */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_9, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5152 { 3756 /* tpos */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_14, AMFBS_None, { MCK_IntRegs }, },
5153 { 3756 /* tpos */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_14, AMFBS_None, { MCK_Imm }, },
5154 { 3756 /* tpos */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_14, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5155 { 3756 /* tpos */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_14, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5156 { 3756 /* tpos */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5157 { 3756 /* tpos */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5158 { 3756 /* tpos */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_14, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5159 { 3756 /* tpos */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_14, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5160 { 3756 /* tpos */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_14, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5161 { 3756 /* tpos */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_14, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5162 { 3756 /* tpos */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5163 { 3756 /* tpos */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_14, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5164 { 3761 /* tst */, SP::ORCCrr, Convert__regG0__Reg1_0__regG0, AMFBS_None, { MCK_IntRegs }, },
5165 { 3765 /* tsubcc */, SP::TSUBCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5166 { 3765 /* tsubcc */, SP::TSUBCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5167 { 3772 /* tsubcctv */, SP::TSUBCCTVrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5168 { 3772 /* tsubcctv */, SP::TSUBCCTVri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5169 { 3781 /* tvc */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_15, AMFBS_None, { MCK_IntRegs }, },
5170 { 3781 /* tvc */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_15, AMFBS_None, { MCK_Imm }, },
5171 { 3781 /* tvc */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_15, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5172 { 3781 /* tvc */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_15, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5173 { 3781 /* tvc */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5174 { 3781 /* tvc */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5175 { 3781 /* tvc */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_15, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5176 { 3781 /* tvc */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_15, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5177 { 3781 /* tvc */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_15, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5178 { 3781 /* tvc */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_15, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5179 { 3781 /* tvc */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5180 { 3781 /* tvc */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_15, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5181 { 3785 /* tvs */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_7, AMFBS_None, { MCK_IntRegs }, },
5182 { 3785 /* tvs */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_7, AMFBS_None, { MCK_Imm }, },
5183 { 3785 /* tvs */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_7, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5184 { 3785 /* tvs */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_7, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5185 { 3785 /* tvs */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5186 { 3785 /* tvs */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5187 { 3785 /* tvs */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_7, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5188 { 3785 /* tvs */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_7, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5189 { 3785 /* tvs */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_7, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5190 { 3785 /* tvs */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_7, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5191 { 3785 /* tvs */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5192 { 3785 /* tvs */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_7, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5193 { 3789 /* tz */, SP::TRAPrr, Convert__regG0__Reg1_0__imm_95_1, AMFBS_None, { MCK_IntRegs }, },
5194 { 3789 /* tz */, SP::TRAPri, Convert__regG0__Imm1_0__imm_95_1, AMFBS_None, { MCK_Imm }, },
5195 { 3789 /* tz */, SP::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
5196 { 3789 /* tz */, SP::TXCCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
5197 { 3789 /* tz */, SP::TICCrr, Convert__regG0__Reg1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs }, },
5198 { 3789 /* tz */, SP::TICCri, Convert__regG0__Imm1_1__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_Imm }, },
5199 { 3789 /* tz */, SP::TRAPrr, Convert__Reg1_0__Reg1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5200 { 3789 /* tz */, SP::TRAPri, Convert__Reg1_0__Imm1_2__imm_95_1, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
5201 { 3789 /* tz */, SP::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5202 { 3789 /* tz */, SP::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5203 { 3789 /* tz */, SP::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
5204 { 3789 /* tz */, SP::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, AMFBS_HasV9, { MCK_ICC, MCK_IntRegs, MCK__43_, MCK_Imm }, },
5205 { 3792 /* udiv */, SP::UDIVrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5206 { 3792 /* udiv */, SP::UDIVri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5207 { 3797 /* udivcc */, SP::UDIVCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5208 { 3797 /* udivcc */, SP::UDIVCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5209 { 3804 /* udivx */, SP::UDIVXrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5210 { 3804 /* udivx */, SP::UDIVXri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_Is64Bit, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5211 { 3810 /* umac */, SP::UMACrr, Convert__Reg1_2__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5212 { 3810 /* umac */, SP::UMACri, Convert__Reg1_2__Reg1_0__Imm1_1__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5213 { 3815 /* umul */, SP::UMULrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5214 { 3815 /* umul */, SP::UMULri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5215 { 3820 /* umulcc */, SP::UMULCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5216 { 3820 /* umulcc */, SP::UMULCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5217 { 3827 /* umulxhi */, SP::UMULXHI, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5218 { 3835 /* unimp */, SP::UNIMP, Convert__imm_95_0, AMFBS_None, { }, },
5219 { 3835 /* unimp */, SP::UNIMP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
5220 { 3841 /* wr */, SP::WRPSRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_PSR }, },
5221 { 3841 /* wr */, SP::WRTBRrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_TBR }, },
5222 { 3841 /* wr */, SP::WRWIMrr, Convert__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_WIM }, },
5223 { 3841 /* wr */, SP::WRASRrr, Convert__Reg1_1__regG0__Reg1_0, AMFBS_None, { MCK_IntRegs, MCK_ASRRegs }, },
5224 { 3841 /* wr */, SP::WRPSRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_PSR }, },
5225 { 3841 /* wr */, SP::WRTBRri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_TBR }, },
5226 { 3841 /* wr */, SP::WRWIMri, Convert__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_WIM }, },
5227 { 3841 /* wr */, SP::WRASRri, Convert__Reg1_1__regG0__Imm1_0, AMFBS_None, { MCK_Imm, MCK_ASRRegs }, },
5228 { 3841 /* wr */, SP::WRPSRrr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_PSR }, },
5229 { 3841 /* wr */, SP::WRTBRrr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_TBR }, },
5230 { 3841 /* wr */, SP::WRWIMrr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_WIM }, },
5231 { 3841 /* wr */, SP::WRASRrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_ASRRegs }, },
5232 { 3841 /* wr */, SP::WRPSRri, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_PSR }, },
5233 { 3841 /* wr */, SP::WRTBRri, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_TBR }, },
5234 { 3841 /* wr */, SP::WRWIMri, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_WIM }, },
5235 { 3841 /* wr */, SP::WRASRri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_ASRRegs }, },
5236 { 3844 /* wrpr */, SP::WRPRrr, Convert__Reg1_1__Reg1_0__regG0, AMFBS_HasV9, { MCK_IntRegs, MCK_PRRegs }, },
5237 { 3844 /* wrpr */, SP::WRPRri, Convert__Reg1_1__regG0__Imm1_0, AMFBS_HasV9, { MCK_Imm, MCK_PRRegs }, },
5238 { 3844 /* wrpr */, SP::WRPRrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasV9, { MCK_IntRegs, MCK_IntRegs, MCK_PRRegs }, },
5239 { 3844 /* wrpr */, SP::WRPRri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_HasV9, { MCK_IntRegs, MCK_Imm, MCK_PRRegs }, },
5240 { 3849 /* xmulx */, SP::XMULX, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5241 { 3855 /* xmulxhi */, SP::XMULXHI, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5242 { 3863 /* xnor */, SP::XNORrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5243 { 3863 /* xnor */, SP::XNORri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5244 { 3868 /* xnorcc */, SP::XNORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5245 { 3868 /* xnorcc */, SP::XNORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5246 { 3875 /* xor */, SP::XORrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5247 { 3875 /* xor */, SP::XORri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5248 { 3879 /* xorcc */, SP::XORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, AMFBS_None, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
5249 { 3879 /* xorcc */, SP::XORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, AMFBS_None, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
5250};
5251
5252#include "llvm/Support/Debug.h"
5253#include "llvm/Support/Format.h"
5254
5255unsigned SparcAsmParser::
5256MatchInstructionImpl(const OperandVector &Operands,
5257 MCInst &Inst,
5258 uint64_t &ErrorInfo,
5259 FeatureBitset &MissingFeatures,
5260 bool matchingInlineAsm, unsigned VariantID) {
5261 // Eliminate obvious mismatches.
5262 if (Operands.size() > 7) {
5263 ErrorInfo = 7;
5264 return Match_InvalidOperand;
5265 }
5266
5267 // Get the current feature set.
5268 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
5269
5270 // Get the instruction mnemonic, which is the first token.
5271 StringRef Mnemonic = ((SparcOperand &)*Operands[0]).getToken();
5272
5273 // Process all MnemonicAliases to remap the mnemonic.
5274 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
5275
5276 // Some state to try to produce better error messages.
5277 bool HadMatchOtherThanFeatures = false;
5278 bool HadMatchOtherThanPredicate = false;
5279 unsigned RetCode = Match_InvalidOperand;
5280 MissingFeatures.set();
5281 // Set ErrorInfo to the operand that mismatches if it is
5282 // wrong for all instances of the instruction.
5283 ErrorInfo = ~0ULL;
5284 // Find the appropriate table for this asm variant.
5285 const MatchEntry *Start, *End;
5286 switch (VariantID) {
5287 default: llvm_unreachable("invalid variant!");
5288 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
5289 }
5290 // Search the table.
5291 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
5292
5293 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
5294 std::distance(MnemonicRange.first, MnemonicRange.second) <<
5295 " encodings with mnemonic '" << Mnemonic << "'\n");
5296
5297 // Return a more specific error code if no mnemonics match.
5298 if (MnemonicRange.first == MnemonicRange.second)
5299 return Match_MnemonicFail;
5300
5301 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
5302 it != ie; ++it) {
5303 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
5304 bool HasRequiredFeatures =
5305 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
5306 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
5307 << MII.getName(it->Opcode) << "\n");
5308 // equal_range guarantees that instruction mnemonic matches.
5309 assert(Mnemonic == it->getMnemonic());
5310 bool OperandsValid = true;
5311 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 6; ++FormalIdx) {
5312 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
5313 DEBUG_WITH_TYPE("asm-matcher",
5314 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
5315 << " against actual operand at index " << ActualIdx);
5316 if (ActualIdx < Operands.size())
5317 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
5318 Operands[ActualIdx]->print(dbgs(), *getContext().getAsmInfo()); dbgs() << "): ");
5319 else
5320 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
5321 if (ActualIdx >= Operands.size()) {
5322 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
5323 if (Formal == InvalidMatchClass) {
5324 break;
5325 }
5326 if (isSubclass(Formal, OptionalMatchClass)) {
5327 continue;
5328 }
5329 OperandsValid = false;
5330 ErrorInfo = ActualIdx;
5331 break;
5332 }
5333 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
5334 unsigned Diag = validateOperandClass(Actual, Formal);
5335 if (Diag == Match_Success) {
5336 DEBUG_WITH_TYPE("asm-matcher",
5337 dbgs() << "match success using generic matcher\n");
5338 ++ActualIdx;
5339 continue;
5340 }
5341 // If the generic handler indicates an invalid operand
5342 // failure, check for a special case.
5343 if (Diag != Match_Success) {
5344 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
5345 if (TargetDiag == Match_Success) {
5346 DEBUG_WITH_TYPE("asm-matcher",
5347 dbgs() << "match success using target matcher\n");
5348 ++ActualIdx;
5349 continue;
5350 }
5351 // If the target matcher returned a specific error code use
5352 // that, else use the one from the generic matcher.
5353 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
5354 Diag = TargetDiag;
5355 }
5356 // If current formal operand wasn't matched and it is optional
5357 // then try to match next formal operand
5358 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
5359 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
5360 continue;
5361 }
5362 // If this operand is broken for all of the instances of this
5363 // mnemonic, keep track of it so we can report loc info.
5364 // If we already had a match that only failed due to a
5365 // target predicate, that diagnostic is preferred.
5366 if (!HadMatchOtherThanPredicate &&
5367 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
5368 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
5369 RetCode = Diag;
5370 ErrorInfo = ActualIdx;
5371 }
5372 // Otherwise, just reject this instance of the mnemonic.
5373 OperandsValid = false;
5374 break;
5375 }
5376
5377 if (!OperandsValid) {
5378 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
5379 "operand mismatches, ignoring "
5380 "this opcode\n");
5381 continue;
5382 }
5383 if (!HasRequiredFeatures) {
5384 HadMatchOtherThanFeatures = true;
5385 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
5386 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
5387 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
5388 if (NewMissingFeatures[I])
5389 dbgs() << ' ' << I;
5390 dbgs() << "\n");
5391 if (NewMissingFeatures.count() <=
5392 MissingFeatures.count())
5393 MissingFeatures = NewMissingFeatures;
5394 continue;
5395 }
5396
5397 Inst.clear();
5398
5399 Inst.setOpcode(it->Opcode);
5400 // We have a potential match but have not rendered the operands.
5401 // Check the target predicate to handle any context sensitive
5402 // constraints.
5403 // For example, Ties that are referenced multiple times must be
5404 // checked here to ensure the input is the same for each match
5405 // constraints. If we leave it any later the ties will have been
5406 // canonicalized
5407 unsigned MatchResult;
5408 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
5409 Inst.clear();
5410 DEBUG_WITH_TYPE(
5411 "asm-matcher",
5412 dbgs() << "Early target match predicate failed with diag code "
5413 << MatchResult << "\n");
5414 RetCode = MatchResult;
5415 HadMatchOtherThanPredicate = true;
5416 continue;
5417 }
5418
5419 if (matchingInlineAsm) {
5420 convertToMapAndConstraints(it->ConvertFn, Operands);
5421 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
5422 ErrorInfo))
5423 return Match_InvalidTiedOperand;
5424
5425 return Match_Success;
5426 }
5427
5428 // We have selected a definite instruction, convert the parsed
5429 // operands into the appropriate MCInst.
5430 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
5431
5432 // We have a potential match. Check the target predicate to
5433 // handle any context sensitive constraints.
5434 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
5435 DEBUG_WITH_TYPE("asm-matcher",
5436 dbgs() << "Target match predicate failed with diag code "
5437 << MatchResult << "\n");
5438 Inst.clear();
5439 RetCode = MatchResult;
5440 HadMatchOtherThanPredicate = true;
5441 continue;
5442 }
5443
5444 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
5445 ErrorInfo))
5446 return Match_InvalidTiedOperand;
5447
5448 DEBUG_WITH_TYPE(
5449 "asm-matcher",
5450 dbgs() << "Opcode result: complete match, selecting this opcode\n");
5451 return Match_Success;
5452 }
5453
5454 // Okay, we had no match. Try to return a useful error code.
5455 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
5456 return RetCode;
5457
5458 ErrorInfo = 0;
5459 return Match_MissingFeature;
5460}
5461
5462namespace {
5463 struct OperandMatchEntry {
5464 uint16_t Mnemonic;
5465 uint8_t OperandMask;
5466 uint8_t Class;
5467 uint8_t RequiredFeaturesIdx;
5468
5469 StringRef getMnemonic() const {
5470 return StringRef(MnemonicTable + Mnemonic + 1,
5471 MnemonicTable[Mnemonic]);
5472 }
5473 };
5474
5475 // Predicate for searching for an opcode.
5476 struct LessOpcodeOperand {
5477 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
5478 return LHS.getMnemonic() < RHS;
5479 }
5480 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
5481 return LHS < RHS.getMnemonic();
5482 }
5483 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
5484 return LHS.getMnemonic() < RHS.getMnemonic();
5485 }
5486 };
5487} // end anonymous namespace
5488
5489static const OperandMatchEntry OperandMatchTable[178] = {
5490 /* Operand List Mnemonic, Mask, Operand Class, Features */
5491 { 1 /* add */, 8 /* 3 */, MCK_TailRelocSymAdd_TLS, AMFBS_None },
5492 { 282 /* call */, 1 /* 0 */, MCK_CallTarget, AMFBS_None },
5493 { 282 /* call */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
5494 { 282 /* call */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
5495 { 282 /* call */, 1 /* 0 */, MCK_CallTarget, AMFBS_None },
5496 { 282 /* call */, 1 /* 0 */, MCK_CallTarget, AMFBS_None },
5497 { 282 /* call */, 2 /* 1 */, MCK_TailRelocSymCall_TLS, AMFBS_None },
5498 { 282 /* call */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
5499 { 282 /* call */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
5500 { 291 /* casa */, 8 /* 3 */, MCK_ASITag, AMFBS_HasCASA },
5501 { 306 /* casxa */, 8 /* 3 */, MCK_ASITag, AMFBS_Is64Bit_HasV9 },
5502 { 399 /* clr */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5503 { 399 /* clr */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5504 { 403 /* clrb */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5505 { 403 /* clrb */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5506 { 408 /* clrh */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5507 { 408 /* clrh */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5508 { 1169 /* flush */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
5509 { 1169 /* flush */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
5510 { 2889 /* jmp */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
5511 { 2889 /* jmp */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
5512 { 2893 /* jmpl */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
5513 { 2893 /* jmpl */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
5514 { 2898 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5515 { 2898 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5516 { 2898 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5517 { 2898 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5518 { 2898 /* ld */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5519 { 2898 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5520 { 2898 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5521 { 2898 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5522 { 2898 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5523 { 2898 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5524 { 2898 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5525 { 2898 /* ld */, 16 /* 4 */, MCK_TailRelocSymLoad_GOT, AMFBS_None },
5526 { 2898 /* ld */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5527 { 2898 /* ld */, 16 /* 4 */, MCK_TailRelocSymLoad_TLS, AMFBS_None },
5528 { 2901 /* lda */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5529 { 2901 /* lda */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5530 { 2901 /* lda */, 8 /* 3 */, MCK_ASITag, AMFBS_HasV9 },
5531 { 2901 /* lda */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
5532 { 2901 /* lda */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
5533 { 2901 /* lda */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5534 { 2905 /* ldd */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5535 { 2905 /* ldd */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5536 { 2905 /* ldd */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5537 { 2905 /* ldd */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5538 { 2905 /* ldd */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5539 { 2905 /* ldd */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5540 { 2909 /* ldda */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5541 { 2909 /* ldda */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5542 { 2909 /* ldda */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
5543 { 2909 /* ldda */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5544 { 2909 /* ldda */, 8 /* 3 */, MCK_ASITag, AMFBS_HasV9 },
5545 { 2909 /* ldda */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
5546 { 2914 /* ldq */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5547 { 2914 /* ldq */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
5548 { 2918 /* ldqa */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5549 { 2918 /* ldqa */, 8 /* 3 */, MCK_ASITag, AMFBS_HasV9 },
5550 { 2918 /* ldqa */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
5551 { 2923 /* ldsb */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5552 { 2923 /* ldsb */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5553 { 2928 /* ldsba */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5554 { 2928 /* ldsba */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
5555 { 2928 /* ldsba */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5556 { 2934 /* ldsh */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5557 { 2934 /* ldsh */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5558 { 2939 /* ldsha */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5559 { 2939 /* ldsha */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
5560 { 2939 /* ldsha */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5561 { 2945 /* ldstub */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5562 { 2945 /* ldstub */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5563 { 2952 /* ldstuba */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5564 { 2952 /* ldstuba */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
5565 { 2952 /* ldstuba */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5566 { 2960 /* ldsw */, 2 /* 1 */, MCK_MEMri, AMFBS_Is64Bit },
5567 { 2960 /* ldsw */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
5568 { 2965 /* ldswa */, 2 /* 1 */, MCK_MEMri, AMFBS_Is64Bit },
5569 { 2965 /* ldswa */, 8 /* 3 */, MCK_ASITag, AMFBS_Is64Bit },
5570 { 2965 /* ldswa */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
5571 { 2971 /* ldub */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5572 { 2971 /* ldub */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5573 { 2976 /* lduba */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5574 { 2976 /* lduba */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
5575 { 2976 /* lduba */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5576 { 2982 /* lduh */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5577 { 2982 /* lduh */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5578 { 2987 /* lduha */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5579 { 2987 /* lduha */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
5580 { 2987 /* lduha */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5581 { 2993 /* ldx */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5582 { 2993 /* ldx */, 2 /* 1 */, MCK_MEMri, AMFBS_Is64Bit },
5583 { 2993 /* ldx */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
5584 { 2993 /* ldx */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
5585 { 2993 /* ldx */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
5586 { 2993 /* ldx */, 16 /* 4 */, MCK_TailRelocSymLoad_GOT, AMFBS_Is64Bit },
5587 { 2993 /* ldx */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
5588 { 2993 /* ldx */, 16 /* 4 */, MCK_TailRelocSymLoad_TLS, AMFBS_Is64Bit },
5589 { 2997 /* ldxa */, 2 /* 1 */, MCK_MEMri, AMFBS_Is64Bit },
5590 { 2997 /* ldxa */, 8 /* 3 */, MCK_ASITag, AMFBS_Is64Bit },
5591 { 2997 /* ldxa */, 2 /* 1 */, MCK_MEMrr, AMFBS_Is64Bit },
5592 { 3008 /* membar */, 1 /* 0 */, MCK_MembarTag, AMFBS_HasV9 },
5593 { 3387 /* prefetch */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5594 { 3387 /* prefetch */, 8 /* 3 */, MCK_PrefetchTag, AMFBS_HasV9 },
5595 { 3387 /* prefetch */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
5596 { 3387 /* prefetch */, 8 /* 3 */, MCK_PrefetchTag, AMFBS_HasV9 },
5597 { 3396 /* prefetcha */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5598 { 3396 /* prefetcha */, 16 /* 4 */, MCK_PrefetchTag, AMFBS_HasV9 },
5599 { 3396 /* prefetcha */, 8 /* 3 */, MCK_ASITag, AMFBS_HasV9 },
5600 { 3396 /* prefetcha */, 2 /* 1 */, MCK_MEMrr, AMFBS_HasV9 },
5601 { 3396 /* prefetcha */, 16 /* 4 */, MCK_PrefetchTag, AMFBS_HasV9 },
5602 { 3450 /* rett */, 1 /* 0 */, MCK_MEMri, AMFBS_None },
5603 { 3450 /* rett */, 1 /* 0 */, MCK_MEMrr, AMFBS_None },
5604 { 3529 /* sll */, 2 /* 1 */, MCK_ShiftAmtImm5, AMFBS_None },
5605 { 3533 /* sllx */, 2 /* 1 */, MCK_ShiftAmtImm6, AMFBS_Is64Bit },
5606 { 3555 /* sra */, 2 /* 1 */, MCK_ShiftAmtImm5, AMFBS_None },
5607 { 3559 /* srax */, 2 /* 1 */, MCK_ShiftAmtImm6, AMFBS_Is64Bit },
5608 { 3564 /* srl */, 2 /* 1 */, MCK_ShiftAmtImm5, AMFBS_None },
5609 { 3568 /* srlx */, 2 /* 1 */, MCK_ShiftAmtImm6, AMFBS_Is64Bit },
5610 { 3573 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5611 { 3573 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5612 { 3573 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5613 { 3573 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5614 { 3573 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5615 { 3573 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5616 { 3573 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5617 { 3573 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5618 { 3573 /* st */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5619 { 3573 /* st */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5620 { 3576 /* sta */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5621 { 3576 /* sta */, 16 /* 4 */, MCK_ASITag, AMFBS_HasV9 },
5622 { 3576 /* sta */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
5623 { 3576 /* sta */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5624 { 3576 /* sta */, 16 /* 4 */, MCK_ASITag, AMFBS_None },
5625 { 3576 /* sta */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5626 { 3580 /* stb */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5627 { 3580 /* stb */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5628 { 3584 /* stba */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5629 { 3584 /* stba */, 16 /* 4 */, MCK_ASITag, AMFBS_None },
5630 { 3584 /* stba */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5631 { 3595 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5632 { 3595 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5633 { 3595 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5634 { 3595 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5635 { 3595 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5636 { 3595 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5637 { 3595 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5638 { 3595 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5639 { 3595 /* std */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5640 { 3595 /* std */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5641 { 3599 /* stda */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5642 { 3599 /* stda */, 16 /* 4 */, MCK_ASITag, AMFBS_None },
5643 { 3599 /* stda */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5644 { 3599 /* stda */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5645 { 3599 /* stda */, 16 /* 4 */, MCK_ASITag, AMFBS_HasV9 },
5646 { 3599 /* stda */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
5647 { 3604 /* sth */, 4 /* 2 */, MCK_MEMri, AMFBS_None },
5648 { 3604 /* sth */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5649 { 3608 /* stha */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5650 { 3608 /* stha */, 16 /* 4 */, MCK_ASITag, AMFBS_None },
5651 { 3608 /* stha */, 4 /* 2 */, MCK_MEMrr, AMFBS_None },
5652 { 3613 /* stq */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5653 { 3613 /* stq */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
5654 { 3617 /* stqa */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5655 { 3617 /* stqa */, 16 /* 4 */, MCK_ASITag, AMFBS_HasV9 },
5656 { 3617 /* stqa */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
5657 { 3622 /* stx */, 4 /* 2 */, MCK_MEMri, AMFBS_HasV9 },
5658 { 3622 /* stx */, 4 /* 2 */, MCK_MEMrr, AMFBS_HasV9 },
5659 { 3622 /* stx */, 4 /* 2 */, MCK_MEMri, AMFBS_Is64Bit },
5660 { 3622 /* stx */, 4 /* 2 */, MCK_MEMrr, AMFBS_Is64Bit },
5661 { 3626 /* stxa */, 4 /* 2 */, MCK_MEMri, AMFBS_Is64Bit },
5662 { 3626 /* stxa */, 16 /* 4 */, MCK_ASITag, AMFBS_Is64Bit },
5663 { 3626 /* stxa */, 4 /* 2 */, MCK_MEMrr, AMFBS_Is64Bit },
5664 { 3653 /* swap */, 2 /* 1 */, MCK_MEMri, AMFBS_None },
5665 { 3653 /* swap */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5666 { 3658 /* swapa */, 2 /* 1 */, MCK_MEMri, AMFBS_HasV9 },
5667 { 3658 /* swapa */, 8 /* 3 */, MCK_ASITag, AMFBS_None },
5668 { 3658 /* swapa */, 2 /* 1 */, MCK_MEMrr, AMFBS_None },
5669};
5670
5671ParseStatus SparcAsmParser::
5672tryCustomParseOperand(OperandVector &Operands,
5673 unsigned MCK) {
5674
5675 switch(MCK) {
5676 case MCK_ASITag:
5677 return parseASITag(Operands);
5678 case MCK_CallTarget:
5679 return parseCallTarget(Operands);
5680 case MCK_MEMri:
5681 return parseMEMOperand(Operands);
5682 case MCK_MEMrr:
5683 return parseMEMOperand(Operands);
5684 case MCK_MembarTag:
5685 return parseMembarTag(Operands);
5686 case MCK_PrefetchTag:
5687 return parsePrefetchTag(Operands);
5688 case MCK_ShiftAmtImm5:
5689 return parseShiftAmtImm<5>(Operands);
5690 case MCK_ShiftAmtImm6:
5691 return parseShiftAmtImm<6>(Operands);
5692 case MCK_TailRelocSymLoad_GOT:
5693 return parseTailRelocSym<TailRelocKind::Load_GOT>(Operands);
5694 case MCK_TailRelocSymAdd_TLS:
5695 return parseTailRelocSym<TailRelocKind::Add_TLS>(Operands);
5696 case MCK_TailRelocSymLoad_TLS:
5697 return parseTailRelocSym<TailRelocKind::Load_TLS>(Operands);
5698 case MCK_TailRelocSymCall_TLS:
5699 return parseTailRelocSym<TailRelocKind::Call_TLS>(Operands);
5700 default:
5701 return ParseStatus::NoMatch;
5702 }
5703 return ParseStatus::NoMatch;
5704}
5705
5706ParseStatus SparcAsmParser::
5707MatchOperandParserImpl(OperandVector &Operands,
5708 StringRef Mnemonic,
5709 bool ParseForAllFeatures) {
5710 // Get the current feature set.
5711 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
5712
5713 // Get the next operand index.
5714 unsigned NextOpNum = Operands.size() - 1;
5715 // Search the table.
5716 auto MnemonicRange =
5717 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
5718 Mnemonic, LessOpcodeOperand());
5719
5720 if (MnemonicRange.first == MnemonicRange.second)
5721 return ParseStatus::NoMatch;
5722
5723 for (const OperandMatchEntry *it = MnemonicRange.first,
5724 *ie = MnemonicRange.second; it != ie; ++it) {
5725 // equal_range guarantees that instruction mnemonic matches.
5726 assert(Mnemonic == it->getMnemonic());
5727
5728 // check if the available features match
5729 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
5730 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
5731 continue;
5732
5733 // check if the operand in question has a custom parser.
5734 if (!(it->OperandMask & (1 << NextOpNum)))
5735 continue;
5736
5737 // call custom parse method to handle the operand
5738 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
5739 if (!Result.isNoMatch())
5740 return Result;
5741 }
5742
5743 // Okay, we had no match.
5744 return ParseStatus::NoMatch;
5745}
5746
5747#endif // GET_MATCHER_IMPLEMENTATION
5748
5749
5750#ifdef GET_MNEMONIC_SPELL_CHECKER
5751#undef GET_MNEMONIC_SPELL_CHECKER
5752
5753static std::string SparcMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
5754 const unsigned MaxEditDist = 2;
5755 std::vector<StringRef> Candidates;
5756 StringRef Prev = "";
5757
5758 // Find the appropriate table for this asm variant.
5759 const MatchEntry *Start, *End;
5760 switch (VariantID) {
5761 default: llvm_unreachable("invalid variant!");
5762 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
5763 }
5764
5765 for (auto I = Start; I < End; I++) {
5766 // Ignore unsupported instructions.
5767 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
5768 if ((FBS & RequiredFeatures) != RequiredFeatures)
5769 continue;
5770
5771 StringRef T = I->getMnemonic();
5772 // Avoid recomputing the edit distance for the same string.
5773 if (T == Prev)
5774 continue;
5775
5776 Prev = T;
5777 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
5778 if (Dist <= MaxEditDist)
5779 Candidates.push_back(T);
5780 }
5781
5782 if (Candidates.empty())
5783 return "";
5784
5785 std::string Res = ", did you mean: ";
5786 unsigned i = 0;
5787 for (; i < Candidates.size() - 1; i++)
5788 Res += Candidates[i].str() + ", ";
5789 return Res + Candidates[i].str() + "?";
5790}
5791
5792#endif // GET_MNEMONIC_SPELL_CHECKER
5793
5794
5795#ifdef GET_MNEMONIC_CHECKER
5796#undef GET_MNEMONIC_CHECKER
5797
5798static bool SparcCheckMnemonic(StringRef Mnemonic,
5799 const FeatureBitset &AvailableFeatures,
5800 unsigned VariantID) {
5801 // Process all MnemonicAliases to remap the mnemonic.
5802 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
5803
5804 // Find the appropriate table for this asm variant.
5805 const MatchEntry *Start, *End;
5806 switch (VariantID) {
5807 default: llvm_unreachable("invalid variant!");
5808 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
5809 }
5810
5811 // Search the table.
5812 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
5813
5814 if (MnemonicRange.first == MnemonicRange.second)
5815 return false;
5816
5817 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
5818 it != ie; ++it) {
5819 const FeatureBitset &RequiredFeatures =
5820 FeatureBitsets[it->RequiredFeaturesIdx];
5821 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
5822 return true;
5823 }
5824 return false;
5825}
5826
5827#endif // GET_MNEMONIC_CHECKER
5828
5829