1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm::SP {
12 enum {
13 PHI = 0,
14 INLINEASM = 1,
15 INLINEASM_BR = 2,
16 CFI_INSTRUCTION = 3,
17 EH_LABEL = 4,
18 GC_LABEL = 5,
19 ANNOTATION_LABEL = 6,
20 KILL = 7,
21 EXTRACT_SUBREG = 8,
22 INSERT_SUBREG = 9,
23 IMPLICIT_DEF = 10,
24 INIT_UNDEF = 11,
25 SUBREG_TO_REG = 12,
26 COPY_TO_REGCLASS = 13,
27 DBG_VALUE = 14,
28 DBG_VALUE_LIST = 15,
29 DBG_INSTR_REF = 16,
30 DBG_PHI = 17,
31 DBG_LABEL = 18,
32 REG_SEQUENCE = 19,
33 COPY = 20,
34 BUNDLE = 21,
35 LIFETIME_START = 22,
36 LIFETIME_END = 23,
37 PSEUDO_PROBE = 24,
38 ARITH_FENCE = 25,
39 STACKMAP = 26,
40 FENTRY_CALL = 27,
41 PATCHPOINT = 28,
42 LOAD_STACK_GUARD = 29,
43 PREALLOCATED_SETUP = 30,
44 PREALLOCATED_ARG = 31,
45 STATEPOINT = 32,
46 LOCAL_ESCAPE = 33,
47 FAULTING_OP = 34,
48 PATCHABLE_OP = 35,
49 PATCHABLE_FUNCTION_ENTER = 36,
50 PATCHABLE_RET = 37,
51 PATCHABLE_FUNCTION_EXIT = 38,
52 PATCHABLE_TAIL_CALL = 39,
53 PATCHABLE_EVENT_CALL = 40,
54 PATCHABLE_TYPED_EVENT_CALL = 41,
55 ICALL_BRANCH_FUNNEL = 42,
56 FAKE_USE = 43,
57 MEMBARRIER = 44,
58 JUMP_TABLE_DEBUG_INFO = 45,
59 CONVERGENCECTRL_ENTRY = 46,
60 CONVERGENCECTRL_ANCHOR = 47,
61 CONVERGENCECTRL_LOOP = 48,
62 CONVERGENCECTRL_GLUE = 49,
63 G_ASSERT_SEXT = 50,
64 G_ASSERT_ZEXT = 51,
65 G_ASSERT_ALIGN = 52,
66 G_ADD = 53,
67 G_SUB = 54,
68 G_MUL = 55,
69 G_SDIV = 56,
70 G_UDIV = 57,
71 G_SREM = 58,
72 G_UREM = 59,
73 G_SDIVREM = 60,
74 G_UDIVREM = 61,
75 G_AND = 62,
76 G_OR = 63,
77 G_XOR = 64,
78 G_ABDS = 65,
79 G_ABDU = 66,
80 G_IMPLICIT_DEF = 67,
81 G_PHI = 68,
82 G_FRAME_INDEX = 69,
83 G_GLOBAL_VALUE = 70,
84 G_PTRAUTH_GLOBAL_VALUE = 71,
85 G_CONSTANT_POOL = 72,
86 G_EXTRACT = 73,
87 G_UNMERGE_VALUES = 74,
88 G_INSERT = 75,
89 G_MERGE_VALUES = 76,
90 G_BUILD_VECTOR = 77,
91 G_BUILD_VECTOR_TRUNC = 78,
92 G_CONCAT_VECTORS = 79,
93 G_PTRTOINT = 80,
94 G_INTTOPTR = 81,
95 G_BITCAST = 82,
96 G_FREEZE = 83,
97 G_CONSTANT_FOLD_BARRIER = 84,
98 G_INTRINSIC_FPTRUNC_ROUND = 85,
99 G_INTRINSIC_TRUNC = 86,
100 G_INTRINSIC_ROUND = 87,
101 G_INTRINSIC_LRINT = 88,
102 G_INTRINSIC_LLRINT = 89,
103 G_INTRINSIC_ROUNDEVEN = 90,
104 G_READCYCLECOUNTER = 91,
105 G_READSTEADYCOUNTER = 92,
106 G_LOAD = 93,
107 G_SEXTLOAD = 94,
108 G_ZEXTLOAD = 95,
109 G_INDEXED_LOAD = 96,
110 G_INDEXED_SEXTLOAD = 97,
111 G_INDEXED_ZEXTLOAD = 98,
112 G_STORE = 99,
113 G_INDEXED_STORE = 100,
114 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101,
115 G_ATOMIC_CMPXCHG = 102,
116 G_ATOMICRMW_XCHG = 103,
117 G_ATOMICRMW_ADD = 104,
118 G_ATOMICRMW_SUB = 105,
119 G_ATOMICRMW_AND = 106,
120 G_ATOMICRMW_NAND = 107,
121 G_ATOMICRMW_OR = 108,
122 G_ATOMICRMW_XOR = 109,
123 G_ATOMICRMW_MAX = 110,
124 G_ATOMICRMW_MIN = 111,
125 G_ATOMICRMW_UMAX = 112,
126 G_ATOMICRMW_UMIN = 113,
127 G_ATOMICRMW_FADD = 114,
128 G_ATOMICRMW_FSUB = 115,
129 G_ATOMICRMW_FMAX = 116,
130 G_ATOMICRMW_FMIN = 117,
131 G_ATOMICRMW_FMAXIMUM = 118,
132 G_ATOMICRMW_FMINIMUM = 119,
133 G_ATOMICRMW_UINC_WRAP = 120,
134 G_ATOMICRMW_UDEC_WRAP = 121,
135 G_ATOMICRMW_USUB_COND = 122,
136 G_ATOMICRMW_USUB_SAT = 123,
137 G_FENCE = 124,
138 G_PREFETCH = 125,
139 G_BRCOND = 126,
140 G_BRINDIRECT = 127,
141 G_INVOKE_REGION_START = 128,
142 G_INTRINSIC = 129,
143 G_INTRINSIC_W_SIDE_EFFECTS = 130,
144 G_INTRINSIC_CONVERGENT = 131,
145 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132,
146 G_ANYEXT = 133,
147 G_TRUNC = 134,
148 G_CONSTANT = 135,
149 G_FCONSTANT = 136,
150 G_VASTART = 137,
151 G_VAARG = 138,
152 G_SEXT = 139,
153 G_SEXT_INREG = 140,
154 G_ZEXT = 141,
155 G_SHL = 142,
156 G_LSHR = 143,
157 G_ASHR = 144,
158 G_FSHL = 145,
159 G_FSHR = 146,
160 G_ROTR = 147,
161 G_ROTL = 148,
162 G_ICMP = 149,
163 G_FCMP = 150,
164 G_SCMP = 151,
165 G_UCMP = 152,
166 G_SELECT = 153,
167 G_UADDO = 154,
168 G_UADDE = 155,
169 G_USUBO = 156,
170 G_USUBE = 157,
171 G_SADDO = 158,
172 G_SADDE = 159,
173 G_SSUBO = 160,
174 G_SSUBE = 161,
175 G_UMULO = 162,
176 G_SMULO = 163,
177 G_UMULH = 164,
178 G_SMULH = 165,
179 G_UADDSAT = 166,
180 G_SADDSAT = 167,
181 G_USUBSAT = 168,
182 G_SSUBSAT = 169,
183 G_USHLSAT = 170,
184 G_SSHLSAT = 171,
185 G_SMULFIX = 172,
186 G_UMULFIX = 173,
187 G_SMULFIXSAT = 174,
188 G_UMULFIXSAT = 175,
189 G_SDIVFIX = 176,
190 G_UDIVFIX = 177,
191 G_SDIVFIXSAT = 178,
192 G_UDIVFIXSAT = 179,
193 G_FADD = 180,
194 G_FSUB = 181,
195 G_FMUL = 182,
196 G_FMA = 183,
197 G_FMAD = 184,
198 G_FDIV = 185,
199 G_FREM = 186,
200 G_FPOW = 187,
201 G_FPOWI = 188,
202 G_FEXP = 189,
203 G_FEXP2 = 190,
204 G_FEXP10 = 191,
205 G_FLOG = 192,
206 G_FLOG2 = 193,
207 G_FLOG10 = 194,
208 G_FLDEXP = 195,
209 G_FFREXP = 196,
210 G_FNEG = 197,
211 G_FPEXT = 198,
212 G_FPTRUNC = 199,
213 G_FPTOSI = 200,
214 G_FPTOUI = 201,
215 G_SITOFP = 202,
216 G_UITOFP = 203,
217 G_FPTOSI_SAT = 204,
218 G_FPTOUI_SAT = 205,
219 G_FABS = 206,
220 G_FCOPYSIGN = 207,
221 G_IS_FPCLASS = 208,
222 G_FCANONICALIZE = 209,
223 G_FMINNUM = 210,
224 G_FMAXNUM = 211,
225 G_FMINNUM_IEEE = 212,
226 G_FMAXNUM_IEEE = 213,
227 G_FMINIMUM = 214,
228 G_FMAXIMUM = 215,
229 G_FMINIMUMNUM = 216,
230 G_FMAXIMUMNUM = 217,
231 G_GET_FPENV = 218,
232 G_SET_FPENV = 219,
233 G_RESET_FPENV = 220,
234 G_GET_FPMODE = 221,
235 G_SET_FPMODE = 222,
236 G_RESET_FPMODE = 223,
237 G_PTR_ADD = 224,
238 G_PTRMASK = 225,
239 G_SMIN = 226,
240 G_SMAX = 227,
241 G_UMIN = 228,
242 G_UMAX = 229,
243 G_ABS = 230,
244 G_LROUND = 231,
245 G_LLROUND = 232,
246 G_BR = 233,
247 G_BRJT = 234,
248 G_VSCALE = 235,
249 G_INSERT_SUBVECTOR = 236,
250 G_EXTRACT_SUBVECTOR = 237,
251 G_INSERT_VECTOR_ELT = 238,
252 G_EXTRACT_VECTOR_ELT = 239,
253 G_SHUFFLE_VECTOR = 240,
254 G_SPLAT_VECTOR = 241,
255 G_STEP_VECTOR = 242,
256 G_VECTOR_COMPRESS = 243,
257 G_CTTZ = 244,
258 G_CTTZ_ZERO_UNDEF = 245,
259 G_CTLZ = 246,
260 G_CTLZ_ZERO_UNDEF = 247,
261 G_CTPOP = 248,
262 G_BSWAP = 249,
263 G_BITREVERSE = 250,
264 G_FCEIL = 251,
265 G_FCOS = 252,
266 G_FSIN = 253,
267 G_FSINCOS = 254,
268 G_FTAN = 255,
269 G_FACOS = 256,
270 G_FASIN = 257,
271 G_FATAN = 258,
272 G_FATAN2 = 259,
273 G_FCOSH = 260,
274 G_FSINH = 261,
275 G_FTANH = 262,
276 G_FSQRT = 263,
277 G_FFLOOR = 264,
278 G_FRINT = 265,
279 G_FNEARBYINT = 266,
280 G_ADDRSPACE_CAST = 267,
281 G_BLOCK_ADDR = 268,
282 G_JUMP_TABLE = 269,
283 G_DYN_STACKALLOC = 270,
284 G_STACKSAVE = 271,
285 G_STACKRESTORE = 272,
286 G_STRICT_FADD = 273,
287 G_STRICT_FSUB = 274,
288 G_STRICT_FMUL = 275,
289 G_STRICT_FDIV = 276,
290 G_STRICT_FREM = 277,
291 G_STRICT_FMA = 278,
292 G_STRICT_FSQRT = 279,
293 G_STRICT_FLDEXP = 280,
294 G_READ_REGISTER = 281,
295 G_WRITE_REGISTER = 282,
296 G_MEMCPY = 283,
297 G_MEMCPY_INLINE = 284,
298 G_MEMMOVE = 285,
299 G_MEMSET = 286,
300 G_BZERO = 287,
301 G_TRAP = 288,
302 G_DEBUGTRAP = 289,
303 G_UBSANTRAP = 290,
304 G_VECREDUCE_SEQ_FADD = 291,
305 G_VECREDUCE_SEQ_FMUL = 292,
306 G_VECREDUCE_FADD = 293,
307 G_VECREDUCE_FMUL = 294,
308 G_VECREDUCE_FMAX = 295,
309 G_VECREDUCE_FMIN = 296,
310 G_VECREDUCE_FMAXIMUM = 297,
311 G_VECREDUCE_FMINIMUM = 298,
312 G_VECREDUCE_ADD = 299,
313 G_VECREDUCE_MUL = 300,
314 G_VECREDUCE_AND = 301,
315 G_VECREDUCE_OR = 302,
316 G_VECREDUCE_XOR = 303,
317 G_VECREDUCE_SMAX = 304,
318 G_VECREDUCE_SMIN = 305,
319 G_VECREDUCE_UMAX = 306,
320 G_VECREDUCE_UMIN = 307,
321 G_SBFX = 308,
322 G_UBFX = 309,
323 ADJCALLSTACKDOWN = 310,
324 ADJCALLSTACKUP = 311,
325 GETPCX = 312,
326 SELECT_CC_DFP_FCC = 313,
327 SELECT_CC_DFP_ICC = 314,
328 SELECT_CC_DFP_XCC = 315,
329 SELECT_CC_FP_FCC = 316,
330 SELECT_CC_FP_ICC = 317,
331 SELECT_CC_FP_XCC = 318,
332 SELECT_CC_Int_FCC = 319,
333 SELECT_CC_Int_ICC = 320,
334 SELECT_CC_Int_XCC = 321,
335 SELECT_CC_QFP_FCC = 322,
336 SELECT_CC_QFP_ICC = 323,
337 SELECT_CC_QFP_XCC = 324,
338 SET = 325,
339 SETSW = 326,
340 SETX = 327,
341 ADDCCri = 328,
342 ADDCCrr = 329,
343 ADDCri = 330,
344 ADDCrr = 331,
345 ADDEri = 332,
346 ADDErr = 333,
347 ADDXC = 334,
348 ADDXCCC = 335,
349 ADDri = 336,
350 ADDrr = 337,
351 ALIGNADDR = 338,
352 ALIGNADDRL = 339,
353 ALLCLEAN = 340,
354 ANDCCri = 341,
355 ANDCCrr = 342,
356 ANDNCCri = 343,
357 ANDNCCrr = 344,
358 ANDNri = 345,
359 ANDNrr = 346,
360 ANDri = 347,
361 ANDrr = 348,
362 ARRAY16 = 349,
363 ARRAY32 = 350,
364 ARRAY8 = 351,
365 BA = 352,
366 BCOND = 353,
367 BCONDA = 354,
368 BINDri = 355,
369 BINDrr = 356,
370 BMASK = 357,
371 BPFCC = 358,
372 BPFCCA = 359,
373 BPFCCANT = 360,
374 BPFCCNT = 361,
375 BPICC = 362,
376 BPICCA = 363,
377 BPICCANT = 364,
378 BPICCNT = 365,
379 BPR = 366,
380 BPRA = 367,
381 BPRANT = 368,
382 BPRNT = 369,
383 BPXCC = 370,
384 BPXCCA = 371,
385 BPXCCANT = 372,
386 BPXCCNT = 373,
387 BSHUFFLE = 374,
388 CALL = 375,
389 CALLi = 376,
390 CALLri = 377,
391 CALLrii = 378,
392 CALLrr = 379,
393 CALLrri = 380,
394 CASAri = 381,
395 CASArr = 382,
396 CASXAri = 383,
397 CASXArr = 384,
398 CMASK16 = 385,
399 CMASK32 = 386,
400 CMASK8 = 387,
401 CPBCOND = 388,
402 CPBCONDA = 389,
403 CWBCONDri = 390,
404 CWBCONDrr = 391,
405 CXBCONDri = 392,
406 CXBCONDrr = 393,
407 DONE = 394,
408 EDGE16 = 395,
409 EDGE16L = 396,
410 EDGE16LN = 397,
411 EDGE16N = 398,
412 EDGE32 = 399,
413 EDGE32L = 400,
414 EDGE32LN = 401,
415 EDGE32N = 402,
416 EDGE8 = 403,
417 EDGE8L = 404,
418 EDGE8LN = 405,
419 EDGE8N = 406,
420 FABSD = 407,
421 FABSQ = 408,
422 FABSS = 409,
423 FADDD = 410,
424 FADDQ = 411,
425 FADDS = 412,
426 FALIGNADATA = 413,
427 FAND = 414,
428 FANDNOT1 = 415,
429 FANDNOT1S = 416,
430 FANDNOT2 = 417,
431 FANDNOT2S = 418,
432 FANDS = 419,
433 FBCOND = 420,
434 FBCONDA = 421,
435 FBCONDA_V9 = 422,
436 FBCOND_V9 = 423,
437 FCHKSM16 = 424,
438 FCMPD = 425,
439 FCMPD_V9 = 426,
440 FCMPEQ16 = 427,
441 FCMPEQ32 = 428,
442 FCMPGT16 = 429,
443 FCMPGT32 = 430,
444 FCMPLE16 = 431,
445 FCMPLE32 = 432,
446 FCMPNE16 = 433,
447 FCMPNE32 = 434,
448 FCMPQ = 435,
449 FCMPQ_V9 = 436,
450 FCMPS = 437,
451 FCMPS_V9 = 438,
452 FDIVD = 439,
453 FDIVQ = 440,
454 FDIVS = 441,
455 FDMULQ = 442,
456 FDTOI = 443,
457 FDTOQ = 444,
458 FDTOS = 445,
459 FDTOX = 446,
460 FEXPAND = 447,
461 FHADDD = 448,
462 FHADDS = 449,
463 FHSUBD = 450,
464 FHSUBS = 451,
465 FITOD = 452,
466 FITOQ = 453,
467 FITOS = 454,
468 FLCMPD = 455,
469 FLCMPS = 456,
470 FLUSH = 457,
471 FLUSHW = 458,
472 FLUSHri = 459,
473 FLUSHrr = 460,
474 FMADDD = 461,
475 FMADDS = 462,
476 FMEAN16 = 463,
477 FMOVD = 464,
478 FMOVD_FCC = 465,
479 FMOVD_ICC = 466,
480 FMOVD_XCC = 467,
481 FMOVQ = 468,
482 FMOVQ_FCC = 469,
483 FMOVQ_ICC = 470,
484 FMOVQ_XCC = 471,
485 FMOVRD = 472,
486 FMOVRQ = 473,
487 FMOVRS = 474,
488 FMOVS = 475,
489 FMOVS_FCC = 476,
490 FMOVS_ICC = 477,
491 FMOVS_XCC = 478,
492 FMSUBD = 479,
493 FMSUBS = 480,
494 FMUL8SUX16 = 481,
495 FMUL8ULX16 = 482,
496 FMUL8X16 = 483,
497 FMUL8X16AL = 484,
498 FMUL8X16AU = 485,
499 FMULD = 486,
500 FMULD8SUX16 = 487,
501 FMULD8ULX16 = 488,
502 FMULQ = 489,
503 FMULS = 490,
504 FNADDD = 491,
505 FNADDS = 492,
506 FNAND = 493,
507 FNANDS = 494,
508 FNEGD = 495,
509 FNEGQ = 496,
510 FNEGS = 497,
511 FNHADDD = 498,
512 FNHADDS = 499,
513 FNMADDD = 500,
514 FNMADDS = 501,
515 FNMSUBD = 502,
516 FNMSUBS = 503,
517 FNMULD = 504,
518 FNMULS = 505,
519 FNOR = 506,
520 FNORS = 507,
521 FNOT1 = 508,
522 FNOT1S = 509,
523 FNOT2 = 510,
524 FNOT2S = 511,
525 FNSMULD = 512,
526 FONE = 513,
527 FONES = 514,
528 FOR = 515,
529 FORNOT1 = 516,
530 FORNOT1S = 517,
531 FORNOT2 = 518,
532 FORNOT2S = 519,
533 FORS = 520,
534 FPACK16 = 521,
535 FPACK32 = 522,
536 FPACKFIX = 523,
537 FPADD16 = 524,
538 FPADD16S = 525,
539 FPADD32 = 526,
540 FPADD32S = 527,
541 FPADD64 = 528,
542 FPMADDX = 529,
543 FPMADDXHI = 530,
544 FPMERGE = 531,
545 FPSUB16 = 532,
546 FPSUB16S = 533,
547 FPSUB32 = 534,
548 FPSUB32S = 535,
549 FQTOD = 536,
550 FQTOI = 537,
551 FQTOS = 538,
552 FQTOX = 539,
553 FSLAS16 = 540,
554 FSLAS32 = 541,
555 FSLL16 = 542,
556 FSLL32 = 543,
557 FSMULD = 544,
558 FSQRTD = 545,
559 FSQRTQ = 546,
560 FSQRTS = 547,
561 FSRA16 = 548,
562 FSRA32 = 549,
563 FSRC1 = 550,
564 FSRC1S = 551,
565 FSRC2 = 552,
566 FSRC2S = 553,
567 FSRL16 = 554,
568 FSRL32 = 555,
569 FSTOD = 556,
570 FSTOI = 557,
571 FSTOQ = 558,
572 FSTOX = 559,
573 FSUBD = 560,
574 FSUBQ = 561,
575 FSUBS = 562,
576 FXNOR = 563,
577 FXNORS = 564,
578 FXOR = 565,
579 FXORS = 566,
580 FXTOD = 567,
581 FXTOQ = 568,
582 FXTOS = 569,
583 FZERO = 570,
584 FZEROS = 571,
585 GDOP_LDXrr = 572,
586 GDOP_LDrr = 573,
587 INVALW = 574,
588 JMPLri = 575,
589 JMPLrr = 576,
590 LDAri = 577,
591 LDArr = 578,
592 LDCSRri = 579,
593 LDCSRrr = 580,
594 LDCri = 581,
595 LDCrr = 582,
596 LDDAri = 583,
597 LDDArr = 584,
598 LDDCri = 585,
599 LDDCrr = 586,
600 LDDFAri = 587,
601 LDDFArr = 588,
602 LDDFri = 589,
603 LDDFrr = 590,
604 LDDri = 591,
605 LDDrr = 592,
606 LDFAri = 593,
607 LDFArr = 594,
608 LDFSRri = 595,
609 LDFSRrr = 596,
610 LDFri = 597,
611 LDFrr = 598,
612 LDQFAri = 599,
613 LDQFArr = 600,
614 LDQFri = 601,
615 LDQFrr = 602,
616 LDSBAri = 603,
617 LDSBArr = 604,
618 LDSBri = 605,
619 LDSBrr = 606,
620 LDSHAri = 607,
621 LDSHArr = 608,
622 LDSHri = 609,
623 LDSHrr = 610,
624 LDSTUBAri = 611,
625 LDSTUBArr = 612,
626 LDSTUBri = 613,
627 LDSTUBrr = 614,
628 LDSWAri = 615,
629 LDSWArr = 616,
630 LDSWri = 617,
631 LDSWrr = 618,
632 LDUBAri = 619,
633 LDUBArr = 620,
634 LDUBri = 621,
635 LDUBrr = 622,
636 LDUHAri = 623,
637 LDUHArr = 624,
638 LDUHri = 625,
639 LDUHrr = 626,
640 LDXAri = 627,
641 LDXArr = 628,
642 LDXFSRri = 629,
643 LDXFSRrr = 630,
644 LDXri = 631,
645 LDXrr = 632,
646 LDri = 633,
647 LDrr = 634,
648 LZCNT = 635,
649 MEMBARi = 636,
650 MOVDTOX = 637,
651 MOVFCCri = 638,
652 MOVFCCrr = 639,
653 MOVICCri = 640,
654 MOVICCrr = 641,
655 MOVRri = 642,
656 MOVRrr = 643,
657 MOVSTOSW = 644,
658 MOVSTOUW = 645,
659 MOVWTOS = 646,
660 MOVXCCri = 647,
661 MOVXCCrr = 648,
662 MOVXTOD = 649,
663 MULSCCri = 650,
664 MULSCCrr = 651,
665 MULXri = 652,
666 MULXrr = 653,
667 NOP = 654,
668 NORMALW = 655,
669 ORCCri = 656,
670 ORCCrr = 657,
671 ORNCCri = 658,
672 ORNCCrr = 659,
673 ORNri = 660,
674 ORNrr = 661,
675 ORri = 662,
676 ORrr = 663,
677 OTHERW = 664,
678 PDIST = 665,
679 PDISTN = 666,
680 POPCrr = 667,
681 PREFETCHAi = 668,
682 PREFETCHAr = 669,
683 PREFETCHi = 670,
684 PREFETCHr = 671,
685 PWRPSRri = 672,
686 PWRPSRrr = 673,
687 RDASR = 674,
688 RDFQ = 675,
689 RDPR = 676,
690 RDPSR = 677,
691 RDTBR = 678,
692 RDWIM = 679,
693 RESTORED = 680,
694 RESTOREri = 681,
695 RESTORErr = 682,
696 RET = 683,
697 RETL = 684,
698 RETRY = 685,
699 RETTri = 686,
700 RETTrr = 687,
701 SAVED = 688,
702 SAVEri = 689,
703 SAVErr = 690,
704 SDIVCCri = 691,
705 SDIVCCrr = 692,
706 SDIVXri = 693,
707 SDIVXrr = 694,
708 SDIVri = 695,
709 SDIVrr = 696,
710 SETHIi = 697,
711 SHUTDOWN = 698,
712 SIAM = 699,
713 SIR = 700,
714 SLLXri = 701,
715 SLLXrr = 702,
716 SLLri = 703,
717 SLLrr = 704,
718 SMACri = 705,
719 SMACrr = 706,
720 SMULCCri = 707,
721 SMULCCrr = 708,
722 SMULri = 709,
723 SMULrr = 710,
724 SRAXri = 711,
725 SRAXrr = 712,
726 SRAri = 713,
727 SRArr = 714,
728 SRLXri = 715,
729 SRLXrr = 716,
730 SRLri = 717,
731 SRLrr = 718,
732 STAri = 719,
733 STArr = 720,
734 STBAR = 721,
735 STBAri = 722,
736 STBArr = 723,
737 STBri = 724,
738 STBrr = 725,
739 STCSRri = 726,
740 STCSRrr = 727,
741 STCri = 728,
742 STCrr = 729,
743 STDAri = 730,
744 STDArr = 731,
745 STDCQri = 732,
746 STDCQrr = 733,
747 STDCri = 734,
748 STDCrr = 735,
749 STDFAri = 736,
750 STDFArr = 737,
751 STDFQri = 738,
752 STDFQrr = 739,
753 STDFri = 740,
754 STDFrr = 741,
755 STDri = 742,
756 STDrr = 743,
757 STFAri = 744,
758 STFArr = 745,
759 STFSRri = 746,
760 STFSRrr = 747,
761 STFri = 748,
762 STFrr = 749,
763 STHAri = 750,
764 STHArr = 751,
765 STHri = 752,
766 STHrr = 753,
767 STQFAri = 754,
768 STQFArr = 755,
769 STQFri = 756,
770 STQFrr = 757,
771 STXAri = 758,
772 STXArr = 759,
773 STXFSRri = 760,
774 STXFSRrr = 761,
775 STXri = 762,
776 STXrr = 763,
777 STri = 764,
778 STrr = 765,
779 SUBCCri = 766,
780 SUBCCrr = 767,
781 SUBCri = 768,
782 SUBCrr = 769,
783 SUBEri = 770,
784 SUBErr = 771,
785 SUBri = 772,
786 SUBrr = 773,
787 SWAPAri = 774,
788 SWAPArr = 775,
789 SWAPri = 776,
790 SWAPrr = 777,
791 TA1 = 778,
792 TA3 = 779,
793 TA5 = 780,
794 TADDCCTVri = 781,
795 TADDCCTVrr = 782,
796 TADDCCri = 783,
797 TADDCCrr = 784,
798 TAIL_CALL = 785,
799 TAIL_CALLri = 786,
800 TICCri = 787,
801 TICCrr = 788,
802 TLS_ADDrr = 789,
803 TLS_CALL = 790,
804 TLS_LDXrr = 791,
805 TLS_LDrr = 792,
806 TRAPri = 793,
807 TRAPrr = 794,
808 TSUBCCTVri = 795,
809 TSUBCCTVrr = 796,
810 TSUBCCri = 797,
811 TSUBCCrr = 798,
812 TXCCri = 799,
813 TXCCrr = 800,
814 UDIVCCri = 801,
815 UDIVCCrr = 802,
816 UDIVXri = 803,
817 UDIVXrr = 804,
818 UDIVri = 805,
819 UDIVrr = 806,
820 UMACri = 807,
821 UMACrr = 808,
822 UMULCCri = 809,
823 UMULCCrr = 810,
824 UMULXHI = 811,
825 UMULri = 812,
826 UMULrr = 813,
827 UNIMP = 814,
828 V9FCMPD = 815,
829 V9FCMPED = 816,
830 V9FCMPEQ = 817,
831 V9FCMPES = 818,
832 V9FCMPQ = 819,
833 V9FCMPS = 820,
834 V9FMOVD_FCC = 821,
835 V9FMOVQ_FCC = 822,
836 V9FMOVS_FCC = 823,
837 V9MOVFCCri = 824,
838 V9MOVFCCrr = 825,
839 WRASRri = 826,
840 WRASRrr = 827,
841 WRPRri = 828,
842 WRPRrr = 829,
843 WRPSRri = 830,
844 WRPSRrr = 831,
845 WRTBRri = 832,
846 WRTBRrr = 833,
847 WRWIMri = 834,
848 WRWIMrr = 835,
849 XMULX = 836,
850 XMULXHI = 837,
851 XNORCCri = 838,
852 XNORCCrr = 839,
853 XNORri = 840,
854 XNORrr = 841,
855 XORCCri = 842,
856 XORCCrr = 843,
857 XORri = 844,
858 XORrr = 845,
859 INSTRUCTION_LIST_END = 846
860 };
861
862} // end namespace llvm::SP
863#endif // GET_INSTRINFO_ENUM
864
865#ifdef GET_INSTRINFO_SCHED_ENUM
866#undef GET_INSTRINFO_SCHED_ENUM
867namespace llvm::SP::Sched {
868
869 enum {
870 NoInstrModel = 0,
871 IIC_iu_instr = 1,
872 IIC_fpu_normal_instr = 2,
873 IIC_jmp_or_call = 3,
874 IIC_fpu_abs = 4,
875 IIC_fpu_fast_instr = 5,
876 IIC_fpu_divd = 6,
877 IIC_fpu_divs = 7,
878 IIC_fpu_muld = 8,
879 IIC_fpu_muls = 9,
880 IIC_fpu_negs = 10,
881 IIC_fpu_sqrtd = 11,
882 IIC_fpu_sqrts = 12,
883 IIC_fpu_stod = 13,
884 IIC_ldd = 14,
885 IIC_iu_or_fpu_instr = 15,
886 IIC_iu_div = 16,
887 IIC_smac_umac = 17,
888 IIC_iu_smul = 18,
889 IIC_st = 19,
890 IIC_std = 20,
891 IIC_iu_umul = 21,
892 SCHED_LIST_END = 22
893 };
894} // end namespace llvm::SP::Sched
895#endif // GET_INSTRINFO_SCHED_ENUM
896
897#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
898namespace llvm {
899
900struct SparcInstrTable {
901 MCInstrDesc Insts[846];
902 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
903 MCOperandInfo OperandInfo[579];
904 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
905 MCPhysReg ImplicitOps[32];
906};
907
908} // end namespace llvm
909#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
910
911#ifdef GET_INSTRINFO_MC_DESC
912#undef GET_INSTRINFO_MC_DESC
913namespace llvm {
914
915static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
916static constexpr unsigned SparcImpOpBase = sizeof SparcInstrTable::OperandInfo / (sizeof(MCPhysReg));
917
918extern const SparcInstrTable SparcDescs = {
919 {
920 { 845, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #845 = XORrr
921 { 844, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #844 = XORri
922 { 843, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #843 = XORCCrr
923 { 842, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #842 = XORCCri
924 { 841, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #841 = XNORrr
925 { 840, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #840 = XNORri
926 { 839, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #839 = XNORCCrr
927 { 838, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #838 = XNORCCri
928 { 837, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #837 = XMULXHI
929 { 836, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #836 = XMULX
930 { 835, 2, 0, 4, 1, 0, 1, 413, SparcImpOpBase + 18, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #835 = WRWIMrr
931 { 834, 2, 0, 4, 1, 0, 1, 168, SparcImpOpBase + 18, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #834 = WRWIMri
932 { 833, 2, 0, 4, 1, 0, 1, 413, SparcImpOpBase + 17, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #833 = WRTBRrr
933 { 832, 2, 0, 4, 1, 0, 1, 168, SparcImpOpBase + 17, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #832 = WRTBRri
934 { 831, 2, 0, 4, 1, 0, 1, 413, SparcImpOpBase + 15, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #831 = WRPSRrr
935 { 830, 2, 0, 4, 1, 0, 1, 168, SparcImpOpBase + 15, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #830 = WRPSRri
936 { 829, 3, 1, 4, 1, 0, 0, 576, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #829 = WRPRrr
937 { 828, 3, 1, 4, 1, 0, 0, 573, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #828 = WRPRri
938 { 827, 3, 1, 4, 1, 0, 0, 570, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #827 = WRASRrr
939 { 826, 3, 1, 4, 1, 0, 0, 567, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #826 = WRASRri
940 { 825, 5, 1, 4, 0, 0, 0, 562, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #825 = V9MOVFCCrr
941 { 824, 5, 1, 4, 0, 0, 0, 557, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #824 = V9MOVFCCri
942 { 823, 5, 1, 4, 0, 0, 0, 552, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #823 = V9FMOVS_FCC
943 { 822, 5, 1, 4, 0, 0, 0, 547, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #822 = V9FMOVQ_FCC
944 { 821, 5, 1, 4, 0, 0, 0, 542, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #821 = V9FMOVD_FCC
945 { 820, 3, 1, 4, 0, 0, 0, 260, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #820 = V9FCMPS
946 { 819, 3, 1, 4, 0, 0, 0, 539, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #819 = V9FCMPQ
947 { 818, 3, 1, 4, 0, 0, 0, 260, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #818 = V9FCMPES
948 { 817, 3, 1, 4, 0, 0, 0, 539, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #817 = V9FCMPEQ
949 { 816, 3, 1, 4, 0, 0, 0, 257, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #816 = V9FCMPED
950 { 815, 3, 1, 4, 0, 0, 0, 257, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #815 = V9FCMPD
951 { 814, 1, 0, 4, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #814 = UNIMP
952 { 813, 3, 1, 4, 21, 0, 1, 176, SparcImpOpBase + 30, 0, 0x0ULL }, // Inst #813 = UMULrr
953 { 812, 3, 1, 4, 21, 0, 1, 173, SparcImpOpBase + 30, 0, 0x0ULL }, // Inst #812 = UMULri
954 { 811, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #811 = UMULXHI
955 { 810, 3, 1, 4, 21, 0, 2, 176, SparcImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #810 = UMULCCrr
956 { 809, 3, 1, 4, 21, 0, 2, 173, SparcImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #809 = UMULCCri
957 { 808, 4, 1, 4, 17, 2, 2, 443, SparcImpOpBase + 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #808 = UMACrr
958 { 807, 4, 1, 4, 17, 2, 2, 439, SparcImpOpBase + 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #807 = UMACri
959 { 806, 3, 1, 4, 16, 1, 1, 176, SparcImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #806 = UDIVrr
960 { 805, 3, 1, 4, 16, 1, 1, 173, SparcImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #805 = UDIVri
961 { 804, 3, 1, 4, 1, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #804 = UDIVXrr
962 { 803, 3, 1, 4, 1, 0, 0, 410, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #803 = UDIVXri
963 { 802, 3, 1, 4, 16, 1, 2, 176, SparcImpOpBase + 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #802 = UDIVCCrr
964 { 801, 3, 1, 4, 16, 1, 2, 173, SparcImpOpBase + 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #801 = UDIVCCri
965 { 800, 3, 0, 4, 0, 1, 0, 436, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #800 = TXCCrr
966 { 799, 3, 0, 4, 0, 1, 0, 532, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #799 = TXCCri
967 { 798, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #798 = TSUBCCrr
968 { 797, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #797 = TSUBCCri
969 { 796, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #796 = TSUBCCTVrr
970 { 795, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #795 = TSUBCCTVri
971 { 794, 3, 0, 4, 0, 1, 0, 436, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #794 = TRAPrr
972 { 793, 3, 0, 4, 0, 1, 0, 532, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #793 = TRAPri
973 { 792, 4, 1, 4, 1, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #792 = TLS_LDrr
974 { 791, 4, 1, 4, 1, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #791 = TLS_LDXrr
975 { 790, 2, 0, 4, 3, 1, 0, 183, SparcImpOpBase + 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #790 = TLS_CALL
976 { 789, 4, 1, 4, 1, 0, 0, 535, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #789 = TLS_ADDrr
977 { 788, 3, 0, 4, 0, 1, 0, 436, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #788 = TICCrr
978 { 787, 3, 0, 4, 0, 1, 0, 532, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #787 = TICCri
979 { 786, 2, 0, 4, 1, 0, 0, 35, SparcImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #786 = TAIL_CALLri
980 { 785, 1, 0, 4, 0, 0, 0, 182, SparcImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #785 = TAIL_CALL
981 { 784, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #784 = TADDCCrr
982 { 783, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #783 = TADDCCri
983 { 782, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #782 = TADDCCTVrr
984 { 781, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #781 = TADDCCTVri
985 { 780, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #780 = TA5
986 { 779, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #779 = TA3
987 { 778, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #778 = TA1
988 { 777, 4, 1, 4, 1, 0, 0, 528, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #777 = SWAPrr
989 { 776, 4, 1, 4, 1, 0, 0, 519, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #776 = SWAPri
990 { 775, 5, 1, 4, 0, 0, 0, 523, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #775 = SWAPArr
991 { 774, 4, 1, 4, 1, 1, 0, 519, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #774 = SWAPAri
992 { 773, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #773 = SUBrr
993 { 772, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #772 = SUBri
994 { 771, 3, 1, 4, 1, 1, 1, 176, SparcImpOpBase + 5, 0, 0x0ULL }, // Inst #771 = SUBErr
995 { 770, 3, 1, 4, 1, 1, 1, 173, SparcImpOpBase + 5, 0, 0x0ULL }, // Inst #770 = SUBEri
996 { 769, 3, 1, 4, 1, 1, 0, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #769 = SUBCrr
997 { 768, 3, 1, 4, 1, 1, 0, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #768 = SUBCri
998 { 767, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #767 = SUBCCrr
999 { 766, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #766 = SUBCCri
1000 { 765, 3, 0, 4, 19, 0, 0, 454, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #765 = STrr
1001 { 764, 3, 0, 4, 19, 0, 0, 447, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #764 = STri
1002 { 763, 3, 0, 4, 19, 0, 0, 516, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #763 = STXrr
1003 { 762, 3, 0, 4, 19, 0, 0, 509, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #762 = STXri
1004 { 761, 2, 0, 4, 1, 1, 0, 185, SparcImpOpBase + 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #761 = STXFSRrr
1005 { 760, 2, 0, 4, 1, 1, 0, 35, SparcImpOpBase + 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #760 = STXFSRri
1006 { 759, 4, 0, 4, 19, 0, 0, 512, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #759 = STXArr
1007 { 758, 3, 0, 4, 19, 1, 0, 509, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #758 = STXAri
1008 { 757, 3, 0, 4, 19, 0, 0, 506, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #757 = STQFrr
1009 { 756, 3, 0, 4, 19, 0, 0, 499, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #756 = STQFri
1010 { 755, 4, 0, 4, 19, 0, 0, 502, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #755 = STQFArr
1011 { 754, 3, 0, 4, 19, 1, 0, 499, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #754 = STQFAri
1012 { 753, 3, 0, 4, 19, 0, 0, 454, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #753 = STHrr
1013 { 752, 3, 0, 4, 19, 0, 0, 447, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #752 = STHri
1014 { 751, 4, 0, 4, 19, 0, 0, 450, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #751 = STHArr
1015 { 750, 3, 0, 4, 19, 1, 0, 447, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #750 = STHAri
1016 { 749, 3, 0, 4, 19, 0, 0, 496, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #749 = STFrr
1017 { 748, 3, 0, 4, 19, 0, 0, 489, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #748 = STFri
1018 { 747, 2, 0, 4, 19, 1, 0, 185, SparcImpOpBase + 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #747 = STFSRrr
1019 { 746, 2, 0, 4, 19, 1, 0, 35, SparcImpOpBase + 10, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #746 = STFSRri
1020 { 745, 4, 0, 4, 19, 0, 0, 492, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #745 = STFArr
1021 { 744, 3, 0, 4, 19, 1, 0, 489, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #744 = STFAri
1022 { 743, 3, 0, 4, 19, 0, 0, 486, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #743 = STDrr
1023 { 742, 3, 0, 4, 19, 0, 0, 463, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #742 = STDri
1024 { 741, 3, 0, 4, 20, 0, 0, 483, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #741 = STDFrr
1025 { 740, 3, 0, 4, 20, 0, 0, 476, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #740 = STDFri
1026 { 739, 2, 0, 4, 20, 0, 1, 185, SparcImpOpBase + 16, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #739 = STDFQrr
1027 { 738, 2, 0, 4, 20, 0, 1, 35, SparcImpOpBase + 16, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #738 = STDFQri
1028 { 737, 4, 0, 4, 19, 0, 0, 479, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #737 = STDFArr
1029 { 736, 3, 0, 4, 19, 1, 0, 476, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #736 = STDFAri
1030 { 735, 3, 0, 4, 20, 0, 0, 473, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #735 = STDCrr
1031 { 734, 3, 0, 4, 20, 0, 0, 470, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #734 = STDCri
1032 { 733, 2, 0, 4, 20, 1, 0, 185, SparcImpOpBase + 31, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #733 = STDCQrr
1033 { 732, 2, 0, 4, 20, 1, 0, 35, SparcImpOpBase + 31, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #732 = STDCQri
1034 { 731, 4, 0, 4, 19, 0, 0, 466, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #731 = STDArr
1035 { 730, 3, 0, 4, 19, 1, 0, 463, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #730 = STDAri
1036 { 729, 3, 0, 4, 19, 0, 0, 460, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #729 = STCrr
1037 { 728, 3, 0, 4, 19, 0, 0, 457, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #728 = STCri
1038 { 727, 2, 0, 4, 19, 1, 0, 185, SparcImpOpBase + 9, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #727 = STCSRrr
1039 { 726, 2, 0, 4, 19, 1, 0, 35, SparcImpOpBase + 9, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #726 = STCSRri
1040 { 725, 3, 0, 4, 19, 0, 0, 454, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #725 = STBrr
1041 { 724, 3, 0, 4, 19, 0, 0, 447, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #724 = STBri
1042 { 723, 4, 0, 4, 19, 0, 0, 450, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #723 = STBArr
1043 { 722, 3, 0, 4, 19, 1, 0, 447, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #722 = STBAri
1044 { 721, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #721 = STBAR
1045 { 720, 4, 0, 4, 19, 0, 0, 450, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #720 = STArr
1046 { 719, 3, 0, 4, 19, 1, 0, 447, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #719 = STAri
1047 { 718, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #718 = SRLrr
1048 { 717, 3, 1, 4, 1, 0, 0, 436, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #717 = SRLri
1049 { 716, 3, 1, 4, 1, 0, 0, 433, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #716 = SRLXrr
1050 { 715, 3, 1, 4, 1, 0, 0, 430, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #715 = SRLXri
1051 { 714, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #714 = SRArr
1052 { 713, 3, 1, 4, 1, 0, 0, 436, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #713 = SRAri
1053 { 712, 3, 1, 4, 1, 0, 0, 433, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #712 = SRAXrr
1054 { 711, 3, 1, 4, 1, 0, 0, 430, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #711 = SRAXri
1055 { 710, 3, 1, 4, 18, 0, 1, 176, SparcImpOpBase + 30, 0, 0x0ULL }, // Inst #710 = SMULrr
1056 { 709, 3, 1, 4, 18, 0, 1, 173, SparcImpOpBase + 30, 0, 0x0ULL }, // Inst #709 = SMULri
1057 { 708, 3, 1, 4, 18, 0, 2, 176, SparcImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #708 = SMULCCrr
1058 { 707, 3, 1, 4, 18, 0, 2, 173, SparcImpOpBase + 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #707 = SMULCCri
1059 { 706, 4, 1, 4, 17, 2, 2, 443, SparcImpOpBase + 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #706 = SMACrr
1060 { 705, 4, 1, 4, 17, 2, 2, 439, SparcImpOpBase + 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #705 = SMACri
1061 { 704, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #704 = SLLrr
1062 { 703, 3, 1, 4, 1, 0, 0, 436, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #703 = SLLri
1063 { 702, 3, 1, 4, 1, 0, 0, 433, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #702 = SLLXrr
1064 { 701, 3, 1, 4, 1, 0, 0, 430, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #701 = SLLXri
1065 { 700, 1, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #700 = SIR
1066 { 699, 1, 0, 4, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #699 = SIAM
1067 { 698, 0, 0, 4, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #698 = SHUTDOWN
1068 { 697, 2, 1, 4, 1, 0, 0, 168, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #697 = SETHIi
1069 { 696, 3, 1, 4, 16, 1, 1, 176, SparcImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #696 = SDIVrr
1070 { 695, 3, 1, 4, 16, 1, 1, 173, SparcImpOpBase + 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #695 = SDIVri
1071 { 694, 3, 1, 4, 1, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = SDIVXrr
1072 { 693, 3, 1, 4, 1, 0, 0, 410, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #693 = SDIVXri
1073 { 692, 3, 1, 4, 16, 1, 2, 176, SparcImpOpBase + 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #692 = SDIVCCrr
1074 { 691, 3, 1, 4, 16, 1, 2, 173, SparcImpOpBase + 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #691 = SDIVCCri
1075 { 690, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = SAVErr
1076 { 689, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = SAVEri
1077 { 688, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #688 = SAVED
1078 { 687, 2, 0, 4, 3, 0, 0, 185, SparcImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = RETTrr
1079 { 686, 2, 0, 4, 3, 0, 0, 35, SparcImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #686 = RETTri
1080 { 685, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = RETRY
1081 { 684, 1, 0, 4, 3, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #684 = RETL
1082 { 683, 1, 0, 4, 3, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = RET
1083 { 682, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = RESTORErr
1084 { 681, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = RESTOREri
1085 { 680, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = RESTORED
1086 { 679, 1, 1, 4, 1, 1, 0, 427, SparcImpOpBase + 18, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #679 = RDWIM
1087 { 678, 1, 1, 4, 1, 1, 0, 427, SparcImpOpBase + 17, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #678 = RDTBR
1088 { 677, 1, 1, 4, 1, 1, 0, 427, SparcImpOpBase + 15, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #677 = RDPSR
1089 { 676, 2, 1, 4, 1, 0, 0, 428, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #676 = RDPR
1090 { 675, 1, 1, 4, 1, 1, 0, 427, SparcImpOpBase + 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #675 = RDFQ
1091 { 674, 2, 1, 4, 1, 0, 0, 425, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #674 = RDASR
1092 { 673, 2, 0, 4, 1, 0, 1, 413, SparcImpOpBase + 15, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #673 = PWRPSRrr
1093 { 672, 2, 0, 4, 1, 0, 1, 168, SparcImpOpBase + 15, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #672 = PWRPSRri
1094 { 671, 3, 0, 4, 1, 0, 0, 422, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #671 = PREFETCHr
1095 { 670, 3, 0, 4, 1, 0, 0, 415, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #670 = PREFETCHi
1096 { 669, 4, 0, 4, 0, 0, 0, 418, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #669 = PREFETCHAr
1097 { 668, 3, 0, 4, 1, 1, 0, 415, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #668 = PREFETCHAi
1098 { 667, 2, 1, 4, 1, 0, 0, 413, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #667 = POPCrr
1099 { 666, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #666 = PDISTN
1100 { 665, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #665 = PDIST
1101 { 664, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #664 = OTHERW
1102 { 663, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #663 = ORrr
1103 { 662, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #662 = ORri
1104 { 661, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #661 = ORNrr
1105 { 660, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #660 = ORNri
1106 { 659, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #659 = ORNCCrr
1107 { 658, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #658 = ORNCCri
1108 { 657, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #657 = ORCCrr
1109 { 656, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #656 = ORCCri
1110 { 655, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #655 = NORMALW
1111 { 654, 0, 0, 4, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = NOP
1112 { 653, 3, 1, 4, 1, 0, 0, 179, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #653 = MULXrr
1113 { 652, 3, 1, 4, 1, 0, 0, 410, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #652 = MULXri
1114 { 651, 3, 1, 4, 1, 2, 2, 176, SparcImpOpBase + 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #651 = MULSCCrr
1115 { 650, 3, 1, 4, 1, 2, 2, 173, SparcImpOpBase + 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #650 = MULSCCri
1116 { 649, 2, 1, 4, 0, 0, 0, 408, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #649 = MOVXTOD
1117 { 648, 4, 1, 4, 0, 1, 0, 390, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #648 = MOVXCCrr
1118 { 647, 4, 1, 4, 0, 1, 0, 386, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #647 = MOVXCCri
1119 { 646, 2, 1, 4, 0, 0, 0, 406, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #646 = MOVWTOS
1120 { 645, 2, 1, 4, 0, 0, 0, 404, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #645 = MOVSTOUW
1121 { 644, 2, 1, 4, 0, 0, 0, 404, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #644 = MOVSTOSW
1122 { 643, 5, 1, 4, 0, 0, 0, 399, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #643 = MOVRrr
1123 { 642, 5, 1, 4, 0, 0, 0, 394, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #642 = MOVRri
1124 { 641, 4, 1, 4, 0, 1, 0, 390, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #641 = MOVICCrr
1125 { 640, 4, 1, 4, 0, 1, 0, 386, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #640 = MOVICCri
1126 { 639, 4, 1, 4, 0, 1, 0, 390, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #639 = MOVFCCrr
1127 { 638, 4, 1, 4, 0, 1, 0, 386, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #638 = MOVFCCri
1128 { 637, 2, 1, 4, 0, 0, 0, 384, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #637 = MOVDTOX
1129 { 636, 1, 0, 4, 1, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #636 = MEMBARi
1130 { 635, 2, 1, 4, 0, 0, 0, 382, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #635 = LZCNT
1131 { 634, 3, 1, 4, 0, 0, 0, 321, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #634 = LDrr
1132 { 633, 3, 1, 4, 0, 0, 0, 318, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #633 = LDri
1133 { 632, 3, 1, 4, 0, 0, 0, 379, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #632 = LDXrr
1134 { 631, 3, 1, 4, 0, 0, 0, 376, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #631 = LDXri
1135 { 630, 2, 0, 4, 1, 0, 1, 185, SparcImpOpBase + 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #630 = LDXFSRrr
1136 { 629, 2, 0, 4, 1, 0, 1, 35, SparcImpOpBase + 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #629 = LDXFSRri
1137 { 628, 4, 1, 4, 0, 0, 0, 310, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #628 = LDXArr
1138 { 627, 3, 1, 4, 1, 1, 0, 376, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #627 = LDXAri
1139 { 626, 3, 1, 4, 0, 0, 0, 321, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #626 = LDUHrr
1140 { 625, 3, 1, 4, 0, 0, 0, 318, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #625 = LDUHri
1141 { 624, 4, 1, 4, 0, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #624 = LDUHArr
1142 { 623, 3, 1, 4, 1, 1, 0, 318, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #623 = LDUHAri
1143 { 622, 3, 1, 4, 0, 0, 0, 321, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #622 = LDUBrr
1144 { 621, 3, 1, 4, 0, 0, 0, 318, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #621 = LDUBri
1145 { 620, 4, 1, 4, 0, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #620 = LDUBArr
1146 { 619, 3, 1, 4, 1, 1, 0, 318, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #619 = LDUBAri
1147 { 618, 3, 1, 4, 0, 0, 0, 379, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #618 = LDSWrr
1148 { 617, 3, 1, 4, 0, 0, 0, 376, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #617 = LDSWri
1149 { 616, 4, 1, 4, 0, 0, 0, 310, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #616 = LDSWArr
1150 { 615, 3, 1, 4, 1, 1, 0, 376, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #615 = LDSWAri
1151 { 614, 3, 1, 4, 1, 0, 0, 321, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #614 = LDSTUBrr
1152 { 613, 3, 1, 4, 1, 0, 0, 318, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #613 = LDSTUBri
1153 { 612, 4, 1, 4, 0, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #612 = LDSTUBArr
1154 { 611, 3, 1, 4, 1, 1, 0, 318, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #611 = LDSTUBAri
1155 { 610, 3, 1, 4, 0, 0, 0, 321, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #610 = LDSHrr
1156 { 609, 3, 1, 4, 0, 0, 0, 318, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #609 = LDSHri
1157 { 608, 4, 1, 4, 0, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #608 = LDSHArr
1158 { 607, 3, 1, 4, 1, 1, 0, 318, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #607 = LDSHAri
1159 { 606, 3, 1, 4, 0, 0, 0, 321, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #606 = LDSBrr
1160 { 605, 3, 1, 4, 0, 0, 0, 318, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #605 = LDSBri
1161 { 604, 4, 1, 4, 0, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #604 = LDSBArr
1162 { 603, 3, 1, 4, 1, 1, 0, 318, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #603 = LDSBAri
1163 { 602, 3, 1, 4, 0, 0, 0, 373, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #602 = LDQFrr
1164 { 601, 3, 1, 4, 0, 0, 0, 366, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #601 = LDQFri
1165 { 600, 4, 1, 4, 0, 0, 0, 369, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #600 = LDQFArr
1166 { 599, 3, 1, 4, 1, 1, 0, 366, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #599 = LDQFAri
1167 { 598, 3, 1, 4, 15, 0, 0, 363, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #598 = LDFrr
1168 { 597, 3, 1, 4, 15, 0, 0, 356, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #597 = LDFri
1169 { 596, 2, 0, 4, 15, 0, 1, 185, SparcImpOpBase + 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #596 = LDFSRrr
1170 { 595, 2, 0, 4, 15, 0, 1, 35, SparcImpOpBase + 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #595 = LDFSRri
1171 { 594, 4, 1, 4, 0, 0, 0, 359, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #594 = LDFArr
1172 { 593, 3, 1, 4, 1, 1, 0, 356, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #593 = LDFAri
1173 { 592, 3, 1, 4, 14, 0, 0, 353, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #592 = LDDrr
1174 { 591, 3, 1, 4, 14, 0, 0, 330, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #591 = LDDri
1175 { 590, 3, 1, 4, 14, 0, 0, 350, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #590 = LDDFrr
1176 { 589, 3, 1, 4, 14, 0, 0, 343, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #589 = LDDFri
1177 { 588, 4, 1, 4, 0, 0, 0, 346, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #588 = LDDFArr
1178 { 587, 3, 1, 4, 1, 1, 0, 343, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #587 = LDDFAri
1179 { 586, 3, 1, 4, 14, 0, 0, 340, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #586 = LDDCrr
1180 { 585, 3, 1, 4, 14, 0, 0, 337, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #585 = LDDCri
1181 { 584, 4, 1, 4, 0, 0, 0, 333, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #584 = LDDArr
1182 { 583, 3, 1, 4, 1, 1, 0, 330, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #583 = LDDAri
1183 { 582, 3, 1, 4, 1, 0, 0, 327, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #582 = LDCrr
1184 { 581, 3, 1, 4, 1, 0, 0, 324, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #581 = LDCri
1185 { 580, 2, 0, 4, 1, 0, 1, 185, SparcImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #580 = LDCSRrr
1186 { 579, 2, 0, 4, 1, 0, 1, 35, SparcImpOpBase + 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #579 = LDCSRri
1187 { 578, 4, 1, 4, 0, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #578 = LDArr
1188 { 577, 3, 1, 4, 1, 1, 0, 318, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #577 = LDAri
1189 { 576, 3, 1, 4, 3, 0, 0, 321, SparcImpOpBase + 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #576 = JMPLrr
1190 { 575, 3, 1, 4, 3, 0, 0, 318, SparcImpOpBase + 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #575 = JMPLri
1191 { 574, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #574 = INVALW
1192 { 573, 4, 1, 4, 1, 0, 0, 314, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #573 = GDOP_LDrr
1193 { 572, 4, 1, 4, 1, 0, 0, 310, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #572 = GDOP_LDXrr
1194 { 571, 1, 1, 4, 0, 0, 0, 305, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #571 = FZEROS
1195 { 570, 1, 1, 4, 0, 0, 0, 304, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #570 = FZERO
1196 { 569, 2, 1, 4, 0, 0, 0, 249, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #569 = FXTOS
1197 { 568, 2, 1, 4, 0, 0, 0, 251, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #568 = FXTOQ
1198 { 567, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #567 = FXTOD
1199 { 566, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #566 = FXORS
1200 { 565, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #565 = FXOR
1201 { 564, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #564 = FXNORS
1202 { 563, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #563 = FXNOR
1203 { 562, 3, 1, 4, 5, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #562 = FSUBS
1204 { 561, 3, 1, 4, 0, 0, 0, 237, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #561 = FSUBQ
1205 { 560, 3, 1, 4, 5, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #560 = FSUBD
1206 { 559, 2, 1, 4, 0, 0, 0, 253, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #559 = FSTOX
1207 { 558, 2, 1, 4, 0, 0, 0, 255, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #558 = FSTOQ
1208 { 557, 2, 1, 4, 5, 0, 0, 235, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #557 = FSTOI
1209 { 556, 2, 1, 4, 13, 0, 0, 253, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #556 = FSTOD
1210 { 555, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #555 = FSRL32
1211 { 554, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #554 = FSRL16
1212 { 553, 2, 1, 4, 0, 0, 0, 235, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #553 = FSRC2S
1213 { 552, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #552 = FSRC2
1214 { 551, 2, 1, 4, 0, 0, 0, 235, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #551 = FSRC1S
1215 { 550, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #550 = FSRC1
1216 { 549, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #549 = FSRA32
1217 { 548, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #548 = FSRA16
1218 { 547, 2, 1, 4, 12, 0, 0, 235, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #547 = FSQRTS
1219 { 546, 2, 1, 4, 0, 0, 0, 233, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #546 = FSQRTQ
1220 { 545, 2, 1, 4, 11, 0, 0, 231, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #545 = FSQRTD
1221 { 544, 3, 1, 4, 8, 0, 0, 301, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #544 = FSMULD
1222 { 543, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #543 = FSLL32
1223 { 542, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #542 = FSLL16
1224 { 541, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #541 = FSLAS32
1225 { 540, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #540 = FSLAS16
1226 { 539, 2, 1, 4, 0, 0, 0, 306, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #539 = FQTOX
1227 { 538, 2, 1, 4, 0, 0, 0, 308, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #538 = FQTOS
1228 { 537, 2, 1, 4, 0, 0, 0, 308, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #537 = FQTOI
1229 { 536, 2, 1, 4, 0, 0, 0, 306, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #536 = FQTOD
1230 { 535, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #535 = FPSUB32S
1231 { 534, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #534 = FPSUB32
1232 { 533, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #533 = FPSUB16S
1233 { 532, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #532 = FPSUB16
1234 { 531, 3, 1, 4, 0, 0, 0, 301, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = FPMERGE
1235 { 530, 4, 1, 4, 0, 0, 0, 263, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = FPMADDXHI
1236 { 529, 4, 1, 4, 0, 0, 0, 263, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #529 = FPMADDX
1237 { 528, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #528 = FPADD64
1238 { 527, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #527 = FPADD32S
1239 { 526, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #526 = FPADD32
1240 { 525, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #525 = FPADD16S
1241 { 524, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #524 = FPADD16
1242 { 523, 2, 1, 4, 0, 0, 0, 249, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #523 = FPACKFIX
1243 { 522, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #522 = FPACK32
1244 { 521, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #521 = FPACK16
1245 { 520, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = FORS
1246 { 519, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #519 = FORNOT2S
1247 { 518, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #518 = FORNOT2
1248 { 517, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #517 = FORNOT1S
1249 { 516, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #516 = FORNOT1
1250 { 515, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #515 = FOR
1251 { 514, 1, 1, 4, 0, 0, 0, 305, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #514 = FONES
1252 { 513, 1, 1, 4, 0, 0, 0, 304, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #513 = FONE
1253 { 512, 3, 1, 4, 0, 0, 0, 301, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #512 = FNSMULD
1254 { 511, 2, 1, 4, 0, 0, 0, 235, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #511 = FNOT2S
1255 { 510, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #510 = FNOT2
1256 { 509, 2, 1, 4, 0, 0, 0, 235, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #509 = FNOT1S
1257 { 508, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #508 = FNOT1
1258 { 507, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #507 = FNORS
1259 { 506, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #506 = FNOR
1260 { 505, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #505 = FNMULS
1261 { 504, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #504 = FNMULD
1262 { 503, 4, 1, 4, 0, 0, 0, 267, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #503 = FNMSUBS
1263 { 502, 4, 1, 4, 0, 0, 0, 263, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #502 = FNMSUBD
1264 { 501, 4, 1, 4, 0, 0, 0, 267, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #501 = FNMADDS
1265 { 500, 4, 1, 4, 0, 0, 0, 263, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #500 = FNMADDD
1266 { 499, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #499 = FNHADDS
1267 { 498, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #498 = FNHADDD
1268 { 497, 2, 1, 4, 10, 0, 0, 235, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #497 = FNEGS
1269 { 496, 2, 1, 4, 0, 0, 0, 233, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #496 = FNEGQ
1270 { 495, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #495 = FNEGD
1271 { 494, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #494 = FNANDS
1272 { 493, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #493 = FNAND
1273 { 492, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #492 = FNADDS
1274 { 491, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #491 = FNADDD
1275 { 490, 3, 1, 4, 9, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #490 = FMULS
1276 { 489, 3, 1, 4, 0, 0, 0, 237, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #489 = FMULQ
1277 { 488, 3, 1, 4, 0, 0, 0, 301, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #488 = FMULD8ULX16
1278 { 487, 3, 1, 4, 0, 0, 0, 301, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #487 = FMULD8SUX16
1279 { 486, 3, 1, 4, 8, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #486 = FMULD
1280 { 485, 3, 1, 4, 0, 0, 0, 301, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #485 = FMUL8X16AU
1281 { 484, 3, 1, 4, 0, 0, 0, 301, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #484 = FMUL8X16AL
1282 { 483, 3, 1, 4, 0, 0, 0, 298, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #483 = FMUL8X16
1283 { 482, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #482 = FMUL8ULX16
1284 { 481, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #481 = FMUL8SUX16
1285 { 480, 4, 1, 4, 0, 0, 0, 267, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #480 = FMSUBS
1286 { 479, 4, 1, 4, 0, 0, 0, 263, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #479 = FMSUBD
1287 { 478, 4, 1, 4, 0, 1, 0, 294, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #478 = FMOVS_XCC
1288 { 477, 4, 1, 4, 0, 1, 0, 294, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #477 = FMOVS_ICC
1289 { 476, 4, 1, 4, 0, 1, 0, 294, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #476 = FMOVS_FCC
1290 { 475, 2, 1, 4, 0, 0, 0, 235, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #475 = FMOVS
1291 { 474, 5, 1, 4, 0, 0, 0, 289, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #474 = FMOVRS
1292 { 473, 5, 1, 4, 0, 0, 0, 284, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #473 = FMOVRQ
1293 { 472, 5, 1, 4, 0, 0, 0, 279, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #472 = FMOVRD
1294 { 471, 4, 1, 4, 0, 1, 0, 275, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #471 = FMOVQ_XCC
1295 { 470, 4, 1, 4, 0, 1, 0, 275, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #470 = FMOVQ_ICC
1296 { 469, 4, 1, 4, 0, 1, 0, 275, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #469 = FMOVQ_FCC
1297 { 468, 2, 1, 4, 0, 0, 0, 233, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #468 = FMOVQ
1298 { 467, 4, 1, 4, 0, 1, 0, 271, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #467 = FMOVD_XCC
1299 { 466, 4, 1, 4, 0, 1, 0, 271, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #466 = FMOVD_ICC
1300 { 465, 4, 1, 4, 0, 1, 0, 271, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #465 = FMOVD_FCC
1301 { 464, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #464 = FMOVD
1302 { 463, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #463 = FMEAN16
1303 { 462, 4, 1, 4, 0, 0, 0, 267, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #462 = FMADDS
1304 { 461, 4, 1, 4, 0, 0, 0, 263, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #461 = FMADDD
1305 { 460, 2, 0, 4, 1, 0, 0, 185, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #460 = FLUSHrr
1306 { 459, 2, 0, 4, 1, 0, 0, 35, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #459 = FLUSHri
1307 { 458, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #458 = FLUSHW
1308 { 457, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #457 = FLUSH
1309 { 456, 3, 1, 4, 0, 0, 0, 260, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = FLCMPS
1310 { 455, 3, 1, 4, 0, 0, 0, 257, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #455 = FLCMPD
1311 { 454, 2, 1, 4, 5, 0, 0, 235, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #454 = FITOS
1312 { 453, 2, 1, 4, 0, 0, 0, 255, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #453 = FITOQ
1313 { 452, 2, 1, 4, 5, 0, 0, 253, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #452 = FITOD
1314 { 451, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #451 = FHSUBS
1315 { 450, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #450 = FHSUBD
1316 { 449, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #449 = FHADDS
1317 { 448, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #448 = FHADDD
1318 { 447, 2, 1, 4, 0, 0, 0, 253, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #447 = FEXPAND
1319 { 446, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #446 = FDTOX
1320 { 445, 2, 1, 4, 5, 0, 0, 249, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #445 = FDTOS
1321 { 444, 2, 1, 4, 0, 0, 0, 251, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #444 = FDTOQ
1322 { 443, 2, 1, 4, 5, 0, 0, 249, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #443 = FDTOI
1323 { 442, 3, 1, 4, 0, 0, 0, 246, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #442 = FDMULQ
1324 { 441, 3, 1, 4, 7, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #441 = FDIVS
1325 { 440, 3, 1, 4, 0, 0, 0, 237, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #440 = FDIVQ
1326 { 439, 3, 1, 4, 6, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #439 = FDIVD
1327 { 438, 2, 0, 4, 5, 0, 1, 235, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #438 = FCMPS_V9
1328 { 437, 2, 0, 4, 5, 0, 1, 235, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #437 = FCMPS
1329 { 436, 2, 0, 4, 0, 0, 1, 233, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #436 = FCMPQ_V9
1330 { 435, 2, 0, 4, 0, 0, 1, 233, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #435 = FCMPQ
1331 { 434, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #434 = FCMPNE32
1332 { 433, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #433 = FCMPNE16
1333 { 432, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #432 = FCMPLE32
1334 { 431, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #431 = FCMPLE16
1335 { 430, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #430 = FCMPGT32
1336 { 429, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #429 = FCMPGT16
1337 { 428, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #428 = FCMPEQ32
1338 { 427, 3, 1, 4, 0, 0, 0, 243, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #427 = FCMPEQ16
1339 { 426, 2, 0, 4, 5, 0, 1, 231, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #426 = FCMPD_V9
1340 { 425, 2, 0, 4, 5, 0, 1, 231, SparcImpOpBase + 3, 0, 0x0ULL }, // Inst #425 = FCMPD
1341 { 424, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #424 = FCHKSM16
1342 { 423, 2, 0, 4, 2, 1, 0, 183, SparcImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #423 = FBCOND_V9
1343 { 422, 2, 0, 4, 2, 1, 0, 183, SparcImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #422 = FBCONDA_V9
1344 { 421, 2, 0, 4, 2, 1, 0, 183, SparcImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #421 = FBCONDA
1345 { 420, 2, 0, 4, 2, 1, 0, 183, SparcImpOpBase + 3, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #420 = FBCOND
1346 { 419, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #419 = FANDS
1347 { 418, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #418 = FANDNOT2S
1348 { 417, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #417 = FANDNOT2
1349 { 416, 3, 1, 4, 0, 0, 0, 240, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #416 = FANDNOT1S
1350 { 415, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #415 = FANDNOT1
1351 { 414, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #414 = FAND
1352 { 413, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #413 = FALIGNADATA
1353 { 412, 3, 1, 4, 5, 0, 0, 240, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #412 = FADDS
1354 { 411, 3, 1, 4, 0, 0, 0, 237, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #411 = FADDQ
1355 { 410, 3, 1, 4, 5, 0, 0, 193, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #410 = FADDD
1356 { 409, 2, 1, 4, 4, 0, 0, 235, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #409 = FABSS
1357 { 408, 2, 1, 4, 0, 0, 0, 233, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #408 = FABSQ
1358 { 407, 2, 1, 4, 0, 0, 0, 231, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #407 = FABSD
1359 { 406, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #406 = EDGE8N
1360 { 405, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #405 = EDGE8LN
1361 { 404, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #404 = EDGE8L
1362 { 403, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #403 = EDGE8
1363 { 402, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #402 = EDGE32N
1364 { 401, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #401 = EDGE32LN
1365 { 400, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #400 = EDGE32L
1366 { 399, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #399 = EDGE32
1367 { 398, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #398 = EDGE16N
1368 { 397, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #397 = EDGE16LN
1369 { 396, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #396 = EDGE16L
1370 { 395, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #395 = EDGE16
1371 { 394, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #394 = DONE
1372 { 393, 4, 0, 4, 0, 0, 0, 227, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #393 = CXBCONDrr
1373 { 392, 4, 0, 4, 0, 0, 0, 223, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #392 = CXBCONDri
1374 { 391, 4, 0, 4, 0, 0, 0, 227, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #391 = CWBCONDrr
1375 { 390, 4, 0, 4, 0, 0, 0, 223, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #390 = CWBCONDri
1376 { 389, 2, 0, 4, 0, 0, 0, 183, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #389 = CPBCONDA
1377 { 388, 2, 0, 4, 0, 0, 0, 183, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #388 = CPBCOND
1378 { 387, 1, 0, 4, 0, 0, 0, 222, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #387 = CMASK8
1379 { 386, 1, 0, 4, 0, 0, 0, 222, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #386 = CMASK32
1380 { 385, 1, 0, 4, 0, 0, 0, 222, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #385 = CMASK16
1381 { 384, 5, 1, 4, 0, 0, 0, 217, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #384 = CASXArr
1382 { 383, 4, 1, 4, 0, 1, 0, 213, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #383 = CASXAri
1383 { 382, 5, 1, 4, 0, 0, 0, 208, SparcImpOpBase + 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #382 = CASArr
1384 { 381, 4, 1, 4, 0, 1, 0, 204, SparcImpOpBase + 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #381 = CASAri
1385 { 380, 3, 0, 4, 1, 1, 0, 201, SparcImpOpBase + 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #380 = CALLrri
1386 { 379, 2, 0, 4, 3, 1, 0, 185, SparcImpOpBase + 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #379 = CALLrr
1387 { 378, 3, 0, 4, 1, 1, 0, 198, SparcImpOpBase + 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #378 = CALLrii
1388 { 377, 2, 0, 4, 3, 1, 0, 35, SparcImpOpBase + 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #377 = CALLri
1389 { 376, 2, 0, 4, 0, 1, 0, 196, SparcImpOpBase + 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #376 = CALLi
1390 { 375, 1, 0, 4, 3, 1, 0, 182, SparcImpOpBase + 7, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #375 = CALL
1391 { 374, 3, 1, 4, 0, 0, 0, 193, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #374 = BSHUFFLE
1392 { 373, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #373 = BPXCCNT
1393 { 372, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #372 = BPXCCANT
1394 { 371, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #371 = BPXCCA
1395 { 370, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #370 = BPXCC
1396 { 369, 3, 0, 4, 0, 0, 0, 190, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #369 = BPRNT
1397 { 368, 3, 0, 4, 0, 0, 0, 190, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #368 = BPRANT
1398 { 367, 3, 0, 4, 0, 0, 0, 190, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #367 = BPRA
1399 { 366, 3, 0, 4, 0, 0, 0, 190, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #366 = BPR
1400 { 365, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #365 = BPICCNT
1401 { 364, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #364 = BPICCANT
1402 { 363, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #363 = BPICCA
1403 { 362, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #362 = BPICC
1404 { 361, 3, 0, 4, 2, 0, 0, 187, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #361 = BPFCCNT
1405 { 360, 3, 0, 4, 2, 0, 0, 187, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #360 = BPFCCANT
1406 { 359, 3, 0, 4, 2, 0, 0, 187, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #359 = BPFCCA
1407 { 358, 3, 0, 4, 2, 0, 0, 187, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #358 = BPFCC
1408 { 357, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #357 = BMASK
1409 { 356, 2, 0, 4, 1, 0, 0, 185, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #356 = BINDrr
1410 { 355, 2, 0, 4, 1, 0, 0, 35, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #355 = BINDri
1411 { 354, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #354 = BCONDA
1412 { 353, 2, 0, 4, 1, 1, 0, 183, SparcImpOpBase + 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #353 = BCOND
1413 { 352, 1, 0, 4, 0, 0, 0, 182, SparcImpOpBase + 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #352 = BA
1414 { 351, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #351 = ARRAY8
1415 { 350, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #350 = ARRAY32
1416 { 349, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #349 = ARRAY16
1417 { 348, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #348 = ANDrr
1418 { 347, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #347 = ANDri
1419 { 346, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #346 = ANDNrr
1420 { 345, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #345 = ANDNri
1421 { 344, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #344 = ANDNCCrr
1422 { 343, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #343 = ANDNCCri
1423 { 342, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #342 = ANDCCrr
1424 { 341, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #341 = ANDCCri
1425 { 340, 0, 0, 4, 1, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #340 = ALLCLEAN
1426 { 339, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #339 = ALIGNADDRL
1427 { 338, 3, 1, 4, 0, 0, 0, 179, SparcImpOpBase + 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #338 = ALIGNADDR
1428 { 337, 3, 1, 4, 1, 0, 0, 176, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #337 = ADDrr
1429 { 336, 3, 1, 4, 1, 0, 0, 173, SparcImpOpBase + 0, 0, 0x0ULL }, // Inst #336 = ADDri
1430 { 335, 3, 1, 4, 0, 1, 1, 179, SparcImpOpBase + 5, 0, 0x0ULL }, // Inst #335 = ADDXCCC
1431 { 334, 3, 1, 4, 0, 1, 0, 179, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #334 = ADDXC
1432 { 333, 3, 1, 4, 1, 1, 1, 176, SparcImpOpBase + 5, 0, 0x0ULL }, // Inst #333 = ADDErr
1433 { 332, 3, 1, 4, 1, 1, 1, 173, SparcImpOpBase + 5, 0, 0x0ULL }, // Inst #332 = ADDEri
1434 { 331, 3, 1, 4, 1, 1, 0, 176, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #331 = ADDCrr
1435 { 330, 3, 1, 4, 1, 1, 0, 173, SparcImpOpBase + 4, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #330 = ADDCri
1436 { 329, 3, 1, 4, 1, 0, 1, 176, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #329 = ADDCCrr
1437 { 328, 3, 1, 4, 1, 0, 1, 173, SparcImpOpBase + 4, 0, 0x0ULL }, // Inst #328 = ADDCCri
1438 { 327, 3, 1, 4, 0, 0, 0, 170, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #327 = SETX
1439 { 326, 2, 1, 4, 0, 0, 0, 168, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #326 = SETSW
1440 { 325, 2, 1, 4, 0, 0, 0, 168, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #325 = SET
1441 { 324, 4, 1, 4, 0, 1, 0, 164, SparcImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #324 = SELECT_CC_QFP_XCC
1442 { 323, 4, 1, 4, 0, 1, 0, 164, SparcImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #323 = SELECT_CC_QFP_ICC
1443 { 322, 4, 1, 4, 0, 1, 0, 164, SparcImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #322 = SELECT_CC_QFP_FCC
1444 { 321, 4, 1, 4, 0, 1, 0, 160, SparcImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #321 = SELECT_CC_Int_XCC
1445 { 320, 4, 1, 4, 0, 1, 0, 160, SparcImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #320 = SELECT_CC_Int_ICC
1446 { 319, 4, 1, 4, 0, 1, 0, 160, SparcImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #319 = SELECT_CC_Int_FCC
1447 { 318, 4, 1, 4, 0, 1, 0, 156, SparcImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #318 = SELECT_CC_FP_XCC
1448 { 317, 4, 1, 4, 0, 1, 0, 156, SparcImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #317 = SELECT_CC_FP_ICC
1449 { 316, 4, 1, 4, 0, 1, 0, 156, SparcImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #316 = SELECT_CC_FP_FCC
1450 { 315, 4, 1, 4, 0, 1, 0, 152, SparcImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #315 = SELECT_CC_DFP_XCC
1451 { 314, 4, 1, 4, 0, 1, 0, 152, SparcImpOpBase + 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #314 = SELECT_CC_DFP_ICC
1452 { 313, 4, 1, 4, 0, 1, 0, 152, SparcImpOpBase + 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #313 = SELECT_CC_DFP_FCC
1453 { 312, 1, 1, 4, 0, 0, 1, 0, SparcImpOpBase + 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #312 = GETPCX
1454 { 311, 2, 0, 4, 0, 1, 1, 21, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #311 = ADJCALLSTACKUP
1455 { 310, 2, 0, 4, 0, 1, 1, 21, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #310 = ADJCALLSTACKDOWN
1456 { 309, 4, 1, 0, 0, 0, 0, 148, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #309 = G_UBFX
1457 { 308, 4, 1, 0, 0, 0, 0, 148, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #308 = G_SBFX
1458 { 307, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #307 = G_VECREDUCE_UMIN
1459 { 306, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #306 = G_VECREDUCE_UMAX
1460 { 305, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #305 = G_VECREDUCE_SMIN
1461 { 304, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #304 = G_VECREDUCE_SMAX
1462 { 303, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #303 = G_VECREDUCE_XOR
1463 { 302, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #302 = G_VECREDUCE_OR
1464 { 301, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #301 = G_VECREDUCE_AND
1465 { 300, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #300 = G_VECREDUCE_MUL
1466 { 299, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = G_VECREDUCE_ADD
1467 { 298, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = G_VECREDUCE_FMINIMUM
1468 { 297, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = G_VECREDUCE_FMAXIMUM
1469 { 296, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = G_VECREDUCE_FMIN
1470 { 295, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_VECREDUCE_FMAX
1471 { 294, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_VECREDUCE_FMUL
1472 { 293, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_FADD
1473 { 292, 3, 1, 0, 0, 0, 0, 131, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_SEQ_FMUL
1474 { 291, 3, 1, 0, 0, 0, 0, 131, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SEQ_FADD
1475 { 290, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #290 = G_UBSANTRAP
1476 { 289, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #289 = G_DEBUGTRAP
1477 { 288, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #288 = G_TRAP
1478 { 287, 3, 0, 0, 0, 0, 0, 58, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #287 = G_BZERO
1479 { 286, 4, 0, 0, 0, 0, 0, 144, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #286 = G_MEMSET
1480 { 285, 4, 0, 0, 0, 0, 0, 144, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #285 = G_MEMMOVE
1481 { 284, 3, 0, 0, 0, 0, 0, 131, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #284 = G_MEMCPY_INLINE
1482 { 283, 4, 0, 0, 0, 0, 0, 144, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #283 = G_MEMCPY
1483 { 282, 2, 0, 0, 0, 0, 0, 142, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #282 = G_WRITE_REGISTER
1484 { 281, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #281 = G_READ_REGISTER
1485 { 280, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = G_STRICT_FLDEXP
1486 { 279, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #279 = G_STRICT_FSQRT
1487 { 278, 4, 1, 0, 0, 0, 0, 46, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #278 = G_STRICT_FMA
1488 { 277, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #277 = G_STRICT_FREM
1489 { 276, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_STRICT_FDIV
1490 { 275, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_STRICT_FMUL
1491 { 274, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_STRICT_FSUB
1492 { 273, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_STRICT_FADD
1493 { 272, 1, 0, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #272 = G_STACKRESTORE
1494 { 271, 1, 1, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = G_STACKSAVE
1495 { 270, 3, 1, 0, 0, 0, 0, 69, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #270 = G_DYN_STACKALLOC
1496 { 269, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #269 = G_JUMP_TABLE
1497 { 268, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #268 = G_BLOCK_ADDR
1498 { 267, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #267 = G_ADDRSPACE_CAST
1499 { 266, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #266 = G_FNEARBYINT
1500 { 265, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #265 = G_FRINT
1501 { 264, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #264 = G_FFLOOR
1502 { 263, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #263 = G_FSQRT
1503 { 262, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #262 = G_FTANH
1504 { 261, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #261 = G_FSINH
1505 { 260, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_FCOSH
1506 { 259, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_FATAN2
1507 { 258, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_FATAN
1508 { 257, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_FASIN
1509 { 256, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_FACOS
1510 { 255, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_FTAN
1511 { 254, 3, 2, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_FSINCOS
1512 { 253, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_FSIN
1513 { 252, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FCOS
1514 { 251, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FCEIL
1515 { 250, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_BITREVERSE
1516 { 249, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_BSWAP
1517 { 248, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_CTPOP
1518 { 247, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_CTLZ_ZERO_UNDEF
1519 { 246, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_CTLZ
1520 { 245, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_CTTZ_ZERO_UNDEF
1521 { 244, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_CTTZ
1522 { 243, 4, 1, 0, 0, 0, 0, 138, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_VECTOR_COMPRESS
1523 { 242, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_STEP_VECTOR
1524 { 241, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_SPLAT_VECTOR
1525 { 240, 4, 1, 0, 0, 0, 0, 134, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_SHUFFLE_VECTOR
1526 { 239, 3, 1, 0, 0, 0, 0, 131, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_EXTRACT_VECTOR_ELT
1527 { 238, 4, 1, 0, 0, 0, 0, 127, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_INSERT_VECTOR_ELT
1528 { 237, 3, 1, 0, 0, 0, 0, 58, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_EXTRACT_SUBVECTOR
1529 { 236, 4, 1, 0, 0, 0, 0, 63, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_INSERT_SUBVECTOR
1530 { 235, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_VSCALE
1531 { 234, 3, 0, 0, 0, 0, 0, 124, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #234 = G_BRJT
1532 { 233, 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #233 = G_BR
1533 { 232, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_LLROUND
1534 { 231, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_LROUND
1535 { 230, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_ABS
1536 { 229, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #229 = G_UMAX
1537 { 228, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #228 = G_UMIN
1538 { 227, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #227 = G_SMAX
1539 { 226, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #226 = G_SMIN
1540 { 225, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_PTRMASK
1541 { 224, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_PTR_ADD
1542 { 223, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #223 = G_RESET_FPMODE
1543 { 222, 1, 0, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #222 = G_SET_FPMODE
1544 { 221, 1, 1, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #221 = G_GET_FPMODE
1545 { 220, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #220 = G_RESET_FPENV
1546 { 219, 1, 0, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #219 = G_SET_FPENV
1547 { 218, 1, 1, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #218 = G_GET_FPENV
1548 { 217, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_FMAXIMUMNUM
1549 { 216, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_FMINIMUMNUM
1550 { 215, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_FMAXIMUM
1551 { 214, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_FMINIMUM
1552 { 213, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #213 = G_FMAXNUM_IEEE
1553 { 212, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #212 = G_FMINNUM_IEEE
1554 { 211, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #211 = G_FMAXNUM
1555 { 210, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #210 = G_FMINNUM
1556 { 209, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #209 = G_FCANONICALIZE
1557 { 208, 3, 1, 0, 0, 0, 0, 98, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #208 = G_IS_FPCLASS
1558 { 207, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #207 = G_FCOPYSIGN
1559 { 206, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #206 = G_FABS
1560 { 205, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #205 = G_FPTOUI_SAT
1561 { 204, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_FPTOSI_SAT
1562 { 203, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_UITOFP
1563 { 202, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #202 = G_SITOFP
1564 { 201, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #201 = G_FPTOUI
1565 { 200, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FPTOSI
1566 { 199, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FPTRUNC
1567 { 198, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FPEXT
1568 { 197, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FNEG
1569 { 196, 3, 2, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FFREXP
1570 { 195, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_FLDEXP
1571 { 194, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FLOG10
1572 { 193, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FLOG2
1573 { 192, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FLOG
1574 { 191, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FEXP10
1575 { 190, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FEXP2
1576 { 189, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FEXP
1577 { 188, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FPOWI
1578 { 187, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FPOW
1579 { 186, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FREM
1580 { 185, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FDIV
1581 { 184, 4, 1, 0, 0, 0, 0, 46, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FMAD
1582 { 183, 4, 1, 0, 0, 0, 0, 46, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FMA
1583 { 182, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #182 = G_FMUL
1584 { 181, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FSUB
1585 { 180, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #180 = G_FADD
1586 { 179, 4, 1, 0, 0, 0, 0, 120, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_UDIVFIXSAT
1587 { 178, 4, 1, 0, 0, 0, 0, 120, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_SDIVFIXSAT
1588 { 177, 4, 1, 0, 0, 0, 0, 120, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_UDIVFIX
1589 { 176, 4, 1, 0, 0, 0, 0, 120, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_SDIVFIX
1590 { 175, 4, 1, 0, 0, 0, 0, 120, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_UMULFIXSAT
1591 { 174, 4, 1, 0, 0, 0, 0, 120, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_SMULFIXSAT
1592 { 173, 4, 1, 0, 0, 0, 0, 120, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_UMULFIX
1593 { 172, 4, 1, 0, 0, 0, 0, 120, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_SMULFIX
1594 { 171, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SSHLSAT
1595 { 170, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_USHLSAT
1596 { 169, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SSUBSAT
1597 { 168, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_USUBSAT
1598 { 167, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SADDSAT
1599 { 166, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UADDSAT
1600 { 165, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULH
1601 { 164, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_UMULH
1602 { 163, 4, 2, 0, 0, 0, 0, 87, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_SMULO
1603 { 162, 4, 2, 0, 0, 0, 0, 87, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #162 = G_UMULO
1604 { 161, 5, 2, 0, 0, 0, 0, 115, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBE
1605 { 160, 4, 2, 0, 0, 0, 0, 87, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_SSUBO
1606 { 159, 5, 2, 0, 0, 0, 0, 115, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #159 = G_SADDE
1607 { 158, 4, 2, 0, 0, 0, 0, 87, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SADDO
1608 { 157, 5, 2, 0, 0, 0, 0, 115, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #157 = G_USUBE
1609 { 156, 4, 2, 0, 0, 0, 0, 87, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #156 = G_USUBO
1610 { 155, 5, 2, 0, 0, 0, 0, 115, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #155 = G_UADDE
1611 { 154, 4, 2, 0, 0, 0, 0, 87, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UADDO
1612 { 153, 4, 1, 0, 0, 0, 0, 87, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SELECT
1613 { 152, 3, 1, 0, 0, 0, 0, 112, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_UCMP
1614 { 151, 3, 1, 0, 0, 0, 0, 112, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SCMP
1615 { 150, 4, 1, 0, 0, 0, 0, 108, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_FCMP
1616 { 149, 4, 1, 0, 0, 0, 0, 108, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_ICMP
1617 { 148, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_ROTL
1618 { 147, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_ROTR
1619 { 146, 4, 1, 0, 0, 0, 0, 104, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_FSHR
1620 { 145, 4, 1, 0, 0, 0, 0, 104, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_FSHL
1621 { 144, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_ASHR
1622 { 143, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_LSHR
1623 { 142, 3, 1, 0, 0, 0, 0, 101, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_SHL
1624 { 141, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ZEXT
1625 { 140, 3, 1, 0, 0, 0, 0, 40, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_SEXT_INREG
1626 { 139, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_SEXT
1627 { 138, 3, 1, 0, 0, 0, 0, 98, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #138 = G_VAARG
1628 { 137, 1, 0, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #137 = G_VASTART
1629 { 136, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_FCONSTANT
1630 { 135, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_CONSTANT
1631 { 134, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_TRUNC
1632 { 133, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ANYEXT
1633 { 132, 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #132 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1634 { 131, 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #131 = G_INTRINSIC_CONVERGENT
1635 { 130, 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #130 = G_INTRINSIC_W_SIDE_EFFECTS
1636 { 129, 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #129 = G_INTRINSIC
1637 { 128, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #128 = G_INVOKE_REGION_START
1638 { 127, 1, 0, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #127 = G_BRINDIRECT
1639 { 126, 2, 0, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #126 = G_BRCOND
1640 { 125, 4, 0, 0, 0, 0, 0, 94, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #125 = G_PREFETCH
1641 { 124, 2, 0, 0, 0, 0, 0, 21, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #124 = G_FENCE
1642 { 123, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #123 = G_ATOMICRMW_USUB_SAT
1643 { 122, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #122 = G_ATOMICRMW_USUB_COND
1644 { 121, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #121 = G_ATOMICRMW_UDEC_WRAP
1645 { 120, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #120 = G_ATOMICRMW_UINC_WRAP
1646 { 119, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #119 = G_ATOMICRMW_FMINIMUM
1647 { 118, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #118 = G_ATOMICRMW_FMAXIMUM
1648 { 117, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #117 = G_ATOMICRMW_FMIN
1649 { 116, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_FMAX
1650 { 115, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_FSUB
1651 { 114, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FADD
1652 { 113, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_UMIN
1653 { 112, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_UMAX
1654 { 111, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_MIN
1655 { 110, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_MAX
1656 { 109, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_XOR
1657 { 108, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_OR
1658 { 107, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_NAND
1659 { 106, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_AND
1660 { 105, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_SUB
1661 { 104, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_ADD
1662 { 103, 3, 1, 0, 0, 0, 0, 91, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_XCHG
1663 { 102, 4, 1, 0, 0, 0, 0, 87, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMIC_CMPXCHG
1664 { 101, 5, 2, 0, 0, 0, 0, 82, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1665 { 100, 5, 1, 0, 0, 0, 0, 77, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_INDEXED_STORE
1666 { 99, 2, 0, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_STORE
1667 { 98, 5, 2, 0, 0, 0, 0, 72, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #98 = G_INDEXED_ZEXTLOAD
1668 { 97, 5, 2, 0, 0, 0, 0, 72, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #97 = G_INDEXED_SEXTLOAD
1669 { 96, 5, 2, 0, 0, 0, 0, 72, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #96 = G_INDEXED_LOAD
1670 { 95, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_ZEXTLOAD
1671 { 94, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_SEXTLOAD
1672 { 93, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_LOAD
1673 { 92, 1, 1, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #92 = G_READSTEADYCOUNTER
1674 { 91, 1, 1, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #91 = G_READCYCLECOUNTER
1675 { 90, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #90 = G_INTRINSIC_ROUNDEVEN
1676 { 89, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #89 = G_INTRINSIC_LLRINT
1677 { 88, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #88 = G_INTRINSIC_LRINT
1678 { 87, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUND
1679 { 86, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_TRUNC
1680 { 85, 3, 1, 0, 0, 0, 0, 69, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_FPTRUNC_ROUND
1681 { 84, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_CONSTANT_FOLD_BARRIER
1682 { 83, 2, 1, 0, 0, 0, 0, 67, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_FREEZE
1683 { 82, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_BITCAST
1684 { 81, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTTOPTR
1685 { 80, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_PTRTOINT
1686 { 79, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #79 = G_CONCAT_VECTORS
1687 { 78, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #78 = G_BUILD_VECTOR_TRUNC
1688 { 77, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #77 = G_BUILD_VECTOR
1689 { 76, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_MERGE_VALUES
1690 { 75, 4, 1, 0, 0, 0, 0, 63, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #75 = G_INSERT
1691 { 74, 2, 1, 0, 0, 0, 0, 61, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_UNMERGE_VALUES
1692 { 73, 3, 1, 0, 0, 0, 0, 58, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_EXTRACT
1693 { 72, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_CONSTANT_POOL
1694 { 71, 5, 1, 0, 0, 0, 0, 53, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_PTRAUTH_GLOBAL_VALUE
1695 { 70, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_GLOBAL_VALUE
1696 { 69, 2, 1, 0, 0, 0, 0, 51, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_FRAME_INDEX
1697 { 68, 1, 1, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #68 = G_PHI
1698 { 67, 1, 1, 0, 0, 0, 0, 50, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_IMPLICIT_DEF
1699 { 66, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #66 = G_ABDU
1700 { 65, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #65 = G_ABDS
1701 { 64, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #64 = G_XOR
1702 { 63, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_OR
1703 { 62, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_AND
1704 { 61, 4, 2, 0, 0, 0, 0, 46, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_UDIVREM
1705 { 60, 4, 2, 0, 0, 0, 0, 46, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_SDIVREM
1706 { 59, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UREM
1707 { 58, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SREM
1708 { 57, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UDIV
1709 { 56, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SDIV
1710 { 55, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #55 = G_MUL
1711 { 54, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SUB
1712 { 53, 3, 1, 0, 0, 0, 0, 43, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_ADD
1713 { 52, 3, 1, 0, 0, 0, 0, 40, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_ASSERT_ALIGN
1714 { 51, 3, 1, 0, 0, 0, 0, 40, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ZEXT
1715 { 50, 3, 1, 0, 0, 0, 0, 40, SparcImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_SEXT
1716 { 49, 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #49 = CONVERGENCECTRL_GLUE
1717 { 48, 2, 1, 0, 0, 0, 0, 13, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_LOOP
1718 { 47, 1, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_ANCHOR
1719 { 46, 1, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ENTRY
1720 { 45, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #45 = JUMP_TABLE_DEBUG_INFO
1721 { 44, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #44 = MEMBARRIER
1722 { 43, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #43 = FAKE_USE
1723 { 42, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = ICALL_BRANCH_FUNNEL
1724 { 41, 3, 0, 0, 0, 0, 0, 37, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = PATCHABLE_TYPED_EVENT_CALL
1725 { 40, 2, 0, 0, 0, 0, 0, 35, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_EVENT_CALL
1726 { 39, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_TAIL_CALL
1727 { 38, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_FUNCTION_EXIT
1728 { 37, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_RET
1729 { 36, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_FUNCTION_ENTER
1730 { 35, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_OP
1731 { 34, 1, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = FAULTING_OP
1732 { 33, 2, 0, 0, 0, 0, 0, 33, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #33 = LOCAL_ESCAPE
1733 { 32, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #32 = STATEPOINT
1734 { 31, 3, 1, 0, 0, 0, 0, 30, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = PREALLOCATED_ARG
1735 { 30, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_SETUP
1736 { 29, 1, 1, 0, 0, 0, 0, 29, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #29 = LOAD_STACK_GUARD
1737 { 28, 6, 1, 0, 0, 0, 0, 23, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #28 = PATCHPOINT
1738 { 27, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = FENTRY_CALL
1739 { 26, 2, 0, 0, 0, 0, 0, 21, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = STACKMAP
1740 { 25, 2, 1, 0, 0, 0, 0, 19, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #25 = ARITH_FENCE
1741 { 24, 4, 0, 0, 0, 0, 0, 15, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #24 = PSEUDO_PROBE
1742 { 23, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #23 = LIFETIME_END
1743 { 22, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_START
1744 { 21, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #21 = BUNDLE
1745 { 20, 2, 1, 0, 0, 0, 0, 13, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #20 = COPY
1746 { 19, 2, 1, 0, 0, 0, 0, 13, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = REG_SEQUENCE
1747 { 18, 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #18 = DBG_LABEL
1748 { 17, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #17 = DBG_PHI
1749 { 16, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_INSTR_REF
1750 { 15, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_VALUE_LIST
1751 { 14, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE
1752 { 13, 3, 1, 0, 0, 0, 0, 2, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #13 = COPY_TO_REGCLASS
1753 { 12, 4, 1, 0, 0, 0, 0, 9, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #12 = SUBREG_TO_REG
1754 { 11, 1, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = INIT_UNDEF
1755 { 10, 1, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1756 { 9, 4, 1, 0, 0, 0, 0, 5, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1757 { 8, 3, 1, 0, 0, 0, 0, 2, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1758 { 7, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
1759 { 6, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1760 { 5, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
1761 { 4, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
1762 { 3, 1, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1763 { 2, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
1764 { 1, 0, 0, 0, 0, 0, 0, 1, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
1765 { 0, 1, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
1766 }, {
1767 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1768 /* 1 */
1769 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1770 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1771 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1772 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1773 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1774 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1775 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1776 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1777 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1778 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1779 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1780 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1781 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1782 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1783 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1784 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1785 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1786 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1787 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1788 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1789 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1790 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1791 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1792 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1793 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1794 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1795 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1796 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1797 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1798 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1799 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1800 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1801 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1802 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1803 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1804 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1805 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1806 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1807 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1808 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1809 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1810 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1811 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1812 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1813 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1814 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1815 /* 152 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1816 /* 156 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1817 /* 160 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1818 /* 164 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1819 /* 168 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1820 /* 170 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1821 /* 173 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1822 /* 176 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1823 /* 179 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1824 /* 182 */ { -1, 0, MCOI::OPERAND_PCREL, 0 },
1825 /* 183 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1826 /* 185 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1827 /* 187 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1828 /* 190 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1829 /* 193 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1830 /* 196 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1831 /* 198 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1832 /* 201 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1833 /* 204 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1834 /* 208 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1835 /* 213 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1836 /* 217 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1837 /* 222 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1838 /* 223 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1839 /* 227 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1840 /* 231 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1841 /* 233 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1842 /* 235 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1843 /* 237 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1844 /* 240 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1845 /* 243 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1846 /* 246 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1847 /* 249 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1848 /* 251 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1849 /* 253 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1850 /* 255 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1851 /* 257 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 260 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1853 /* 263 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1854 /* 267 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1855 /* 271 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1856 /* 275 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1857 /* 279 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1858 /* 284 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1859 /* 289 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1860 /* 294 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1861 /* 298 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1862 /* 301 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1863 /* 304 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1864 /* 305 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1865 /* 306 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1866 /* 308 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1867 /* 310 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1868 /* 314 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1869 /* 318 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1870 /* 321 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1871 /* 324 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1872 /* 327 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1873 /* 330 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1874 /* 333 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1875 /* 337 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1876 /* 340 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1877 /* 343 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1878 /* 346 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1879 /* 350 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1880 /* 353 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1881 /* 356 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1882 /* 359 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1883 /* 363 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1884 /* 366 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1885 /* 369 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1886 /* 373 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1887 /* 376 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1888 /* 379 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1889 /* 382 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1890 /* 384 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1891 /* 386 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1892 /* 390 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1893 /* 394 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1894 /* 399 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1895 /* 404 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1896 /* 406 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1897 /* 408 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1898 /* 410 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1899 /* 413 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1900 /* 415 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1901 /* 418 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1902 /* 422 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1903 /* 425 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1904 /* 427 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1905 /* 428 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1906 /* 430 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1907 /* 433 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1908 /* 436 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1909 /* 439 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1910 /* 443 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1911 /* 447 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1912 /* 450 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1913 /* 454 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1914 /* 457 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1915 /* 460 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1916 /* 463 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1917 /* 466 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1918 /* 470 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1919 /* 473 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1920 /* 476 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1921 /* 479 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1922 /* 483 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1923 /* 486 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1924 /* 489 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1925 /* 492 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1926 /* 496 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1927 /* 499 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1928 /* 502 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1929 /* 506 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1930 /* 509 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1931 /* 512 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1932 /* 516 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1933 /* 519 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1934 /* 523 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1935 /* 528 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1936 /* 532 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1937 /* 535 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1938 /* 539 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1939 /* 542 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1940 /* 547 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1941 /* 552 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1942 /* 557 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1943 /* 562 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1944 /* 567 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1945 /* 570 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1946 /* 573 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1947 /* 576 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1948 }, {
1949 /* 0 */
1950 /* 0 */ SP::O6, SP::O6,
1951 /* 2 */ SP::O7,
1952 /* 3 */ SP::FCC0,
1953 /* 4 */ SP::ICC,
1954 /* 5 */ SP::ICC, SP::ICC,
1955 /* 7 */ SP::O6,
1956 /* 8 */ SP::ASR3,
1957 /* 9 */ SP::CPSR,
1958 /* 10 */ SP::FSR,
1959 /* 11 */ SP::Y, SP::ICC, SP::Y, SP::ICC,
1960 /* 15 */ SP::PSR,
1961 /* 16 */ SP::FQ,
1962 /* 17 */ SP::TBR,
1963 /* 18 */ SP::WIM,
1964 /* 19 */ SP::Y, SP::Y, SP::ICC,
1965 /* 22 */ SP::Y, SP::Y,
1966 /* 24 */ SP::Y, SP::ASR18, SP::Y, SP::ASR18,
1967 /* 28 */ SP::Y, SP::ICC,
1968 /* 30 */ SP::Y,
1969 /* 31 */ SP::CPQ,
1970 }
1971};
1972
1973
1974#ifdef __GNUC__
1975#pragma GCC diagnostic push
1976#pragma GCC diagnostic ignored "-Woverlength-strings"
1977#endif
1978extern const char SparcInstrNameData[] = {
1979 /* 0 */ "G_FLOG10\000"
1980 /* 9 */ "G_FEXP10\000"
1981 /* 18 */ "TA1\000"
1982 /* 22 */ "FSRC1\000"
1983 /* 28 */ "FANDNOT1\000"
1984 /* 37 */ "FNOT1\000"
1985 /* 43 */ "FORNOT1\000"
1986 /* 51 */ "FSRA32\000"
1987 /* 58 */ "FPSUB32\000"
1988 /* 66 */ "FPADD32\000"
1989 /* 74 */ "EDGE32\000"
1990 /* 81 */ "FCMPLE32\000"
1991 /* 90 */ "FCMPNE32\000"
1992 /* 99 */ "FPACK32\000"
1993 /* 107 */ "CMASK32\000"
1994 /* 115 */ "FSLL32\000"
1995 /* 122 */ "FSRL32\000"
1996 /* 129 */ "FCMPEQ32\000"
1997 /* 138 */ "FSLAS32\000"
1998 /* 146 */ "FCMPGT32\000"
1999 /* 155 */ "ARRAY32\000"
2000 /* 163 */ "FSRC2\000"
2001 /* 169 */ "G_FLOG2\000"
2002 /* 177 */ "G_FATAN2\000"
2003 /* 186 */ "G_FEXP2\000"
2004 /* 194 */ "FANDNOT2\000"
2005 /* 203 */ "FNOT2\000"
2006 /* 209 */ "FORNOT2\000"
2007 /* 217 */ "TA3\000"
2008 /* 221 */ "FPADD64\000"
2009 /* 229 */ "TA5\000"
2010 /* 233 */ "FSRA16\000"
2011 /* 240 */ "FPSUB16\000"
2012 /* 248 */ "FPADD16\000"
2013 /* 256 */ "EDGE16\000"
2014 /* 263 */ "FCMPLE16\000"
2015 /* 272 */ "FCMPNE16\000"
2016 /* 281 */ "FPACK16\000"
2017 /* 289 */ "CMASK16\000"
2018 /* 297 */ "FSLL16\000"
2019 /* 304 */ "FSRL16\000"
2020 /* 311 */ "FCHKSM16\000"
2021 /* 320 */ "FMEAN16\000"
2022 /* 328 */ "FCMPEQ16\000"
2023 /* 337 */ "FSLAS16\000"
2024 /* 345 */ "FCMPGT16\000"
2025 /* 354 */ "FMUL8X16\000"
2026 /* 363 */ "FMULD8ULX16\000"
2027 /* 375 */ "FMUL8ULX16\000"
2028 /* 386 */ "FMULD8SUX16\000"
2029 /* 398 */ "FMUL8SUX16\000"
2030 /* 409 */ "ARRAY16\000"
2031 /* 417 */ "EDGE8\000"
2032 /* 423 */ "CMASK8\000"
2033 /* 430 */ "ARRAY8\000"
2034 /* 437 */ "FBCONDA_V9\000"
2035 /* 448 */ "FBCOND_V9\000"
2036 /* 458 */ "FCMPD_V9\000"
2037 /* 467 */ "FCMPQ_V9\000"
2038 /* 476 */ "FCMPS_V9\000"
2039 /* 485 */ "BA\000"
2040 /* 488 */ "BPFCCA\000"
2041 /* 495 */ "BPICCA\000"
2042 /* 502 */ "BPXCCA\000"
2043 /* 509 */ "FBCONDA\000"
2044 /* 517 */ "CPBCONDA\000"
2045 /* 526 */ "G_FMA\000"
2046 /* 532 */ "G_STRICT_FMA\000"
2047 /* 545 */ "BPRA\000"
2048 /* 550 */ "FALIGNADATA\000"
2049 /* 562 */ "G_FSUB\000"
2050 /* 569 */ "G_STRICT_FSUB\000"
2051 /* 583 */ "G_ATOMICRMW_FSUB\000"
2052 /* 600 */ "G_SUB\000"
2053 /* 606 */ "G_ATOMICRMW_SUB\000"
2054 /* 622 */ "ADDXCCC\000"
2055 /* 630 */ "BPFCC\000"
2056 /* 636 */ "V9FMOVD_FCC\000"
2057 /* 648 */ "SELECT_CC_DFP_FCC\000"
2058 /* 666 */ "SELECT_CC_QFP_FCC\000"
2059 /* 684 */ "SELECT_CC_FP_FCC\000"
2060 /* 701 */ "V9FMOVQ_FCC\000"
2061 /* 713 */ "V9FMOVS_FCC\000"
2062 /* 725 */ "SELECT_CC_Int_FCC\000"
2063 /* 743 */ "BPICC\000"
2064 /* 749 */ "FMOVD_ICC\000"
2065 /* 759 */ "SELECT_CC_DFP_ICC\000"
2066 /* 777 */ "SELECT_CC_QFP_ICC\000"
2067 /* 795 */ "SELECT_CC_FP_ICC\000"
2068 /* 812 */ "FMOVQ_ICC\000"
2069 /* 822 */ "FMOVS_ICC\000"
2070 /* 832 */ "SELECT_CC_Int_ICC\000"
2071 /* 850 */ "BPXCC\000"
2072 /* 856 */ "FMOVD_XCC\000"
2073 /* 866 */ "SELECT_CC_DFP_XCC\000"
2074 /* 884 */ "SELECT_CC_QFP_XCC\000"
2075 /* 902 */ "SELECT_CC_FP_XCC\000"
2076 /* 919 */ "FMOVQ_XCC\000"
2077 /* 929 */ "FMOVS_XCC\000"
2078 /* 939 */ "SELECT_CC_Int_XCC\000"
2079 /* 957 */ "G_INTRINSIC\000"
2080 /* 969 */ "G_FPTRUNC\000"
2081 /* 979 */ "G_INTRINSIC_TRUNC\000"
2082 /* 997 */ "G_TRUNC\000"
2083 /* 1005 */ "G_BUILD_VECTOR_TRUNC\000"
2084 /* 1026 */ "G_DYN_STACKALLOC\000"
2085 /* 1043 */ "ADDXC\000"
2086 /* 1049 */ "G_FMAD\000"
2087 /* 1056 */ "G_INDEXED_SEXTLOAD\000"
2088 /* 1075 */ "G_SEXTLOAD\000"
2089 /* 1086 */ "G_INDEXED_ZEXTLOAD\000"
2090 /* 1105 */ "G_ZEXTLOAD\000"
2091 /* 1116 */ "G_INDEXED_LOAD\000"
2092 /* 1131 */ "G_LOAD\000"
2093 /* 1138 */ "FSUBD\000"
2094 /* 1144 */ "FHSUBD\000"
2095 /* 1151 */ "FMSUBD\000"
2096 /* 1158 */ "FNMSUBD\000"
2097 /* 1166 */ "G_VECREDUCE_FADD\000"
2098 /* 1183 */ "G_FADD\000"
2099 /* 1190 */ "G_VECREDUCE_SEQ_FADD\000"
2100 /* 1211 */ "G_STRICT_FADD\000"
2101 /* 1225 */ "G_ATOMICRMW_FADD\000"
2102 /* 1242 */ "G_VECREDUCE_ADD\000"
2103 /* 1258 */ "G_ADD\000"
2104 /* 1264 */ "G_PTR_ADD\000"
2105 /* 1274 */ "G_ATOMICRMW_ADD\000"
2106 /* 1290 */ "FADDD\000"
2107 /* 1296 */ "FHADDD\000"
2108 /* 1303 */ "FNHADDD\000"
2109 /* 1311 */ "FMADDD\000"
2110 /* 1318 */ "FNMADDD\000"
2111 /* 1326 */ "FNADDD\000"
2112 /* 1333 */ "V9FCMPED\000"
2113 /* 1342 */ "RESTORED\000"
2114 /* 1351 */ "SAVED\000"
2115 /* 1357 */ "FNEGD\000"
2116 /* 1363 */ "FMULD\000"
2117 /* 1369 */ "FNMULD\000"
2118 /* 1376 */ "FSMULD\000"
2119 /* 1383 */ "FNSMULD\000"
2120 /* 1391 */ "FAND\000"
2121 /* 1396 */ "FNAND\000"
2122 /* 1402 */ "G_ATOMICRMW_NAND\000"
2123 /* 1419 */ "FEXPAND\000"
2124 /* 1427 */ "G_VECREDUCE_AND\000"
2125 /* 1443 */ "G_AND\000"
2126 /* 1449 */ "G_ATOMICRMW_AND\000"
2127 /* 1465 */ "LIFETIME_END\000"
2128 /* 1478 */ "FBCOND\000"
2129 /* 1485 */ "CPBCOND\000"
2130 /* 1493 */ "G_BRCOND\000"
2131 /* 1502 */ "G_ATOMICRMW_USUB_COND\000"
2132 /* 1524 */ "G_LLROUND\000"
2133 /* 1534 */ "G_LROUND\000"
2134 /* 1543 */ "G_INTRINSIC_ROUND\000"
2135 /* 1561 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
2136 /* 1587 */ "FITOD\000"
2137 /* 1593 */ "FQTOD\000"
2138 /* 1599 */ "FSTOD\000"
2139 /* 1605 */ "FXTOD\000"
2140 /* 1611 */ "MOVXTOD\000"
2141 /* 1619 */ "V9FCMPD\000"
2142 /* 1627 */ "FLCMPD\000"
2143 /* 1634 */ "LOAD_STACK_GUARD\000"
2144 /* 1651 */ "FMOVRD\000"
2145 /* 1658 */ "FABSD\000"
2146 /* 1664 */ "FSQRTD\000"
2147 /* 1671 */ "FDIVD\000"
2148 /* 1677 */ "FMOVD\000"
2149 /* 1683 */ "PSEUDO_PROBE\000"
2150 /* 1696 */ "G_SSUBE\000"
2151 /* 1704 */ "G_USUBE\000"
2152 /* 1712 */ "G_FENCE\000"
2153 /* 1720 */ "ARITH_FENCE\000"
2154 /* 1732 */ "REG_SEQUENCE\000"
2155 /* 1745 */ "G_SADDE\000"
2156 /* 1753 */ "G_UADDE\000"
2157 /* 1761 */ "G_GET_FPMODE\000"
2158 /* 1774 */ "G_RESET_FPMODE\000"
2159 /* 1789 */ "G_SET_FPMODE\000"
2160 /* 1802 */ "G_FMINNUM_IEEE\000"
2161 /* 1817 */ "G_FMAXNUM_IEEE\000"
2162 /* 1832 */ "FPMERGE\000"
2163 /* 1840 */ "G_VSCALE\000"
2164 /* 1849 */ "G_JUMP_TABLE\000"
2165 /* 1862 */ "BUNDLE\000"
2166 /* 1869 */ "BSHUFFLE\000"
2167 /* 1878 */ "G_MEMCPY_INLINE\000"
2168 /* 1894 */ "DONE\000"
2169 /* 1899 */ "FONE\000"
2170 /* 1904 */ "LOCAL_ESCAPE\000"
2171 /* 1917 */ "G_STACKRESTORE\000"
2172 /* 1932 */ "G_INDEXED_STORE\000"
2173 /* 1948 */ "G_STORE\000"
2174 /* 1956 */ "G_BITREVERSE\000"
2175 /* 1969 */ "FAKE_USE\000"
2176 /* 1978 */ "DBG_VALUE\000"
2177 /* 1988 */ "G_GLOBAL_VALUE\000"
2178 /* 2003 */ "G_PTRAUTH_GLOBAL_VALUE\000"
2179 /* 2026 */ "CONVERGENCECTRL_GLUE\000"
2180 /* 2047 */ "G_STACKSAVE\000"
2181 /* 2059 */ "G_MEMMOVE\000"
2182 /* 2069 */ "G_FREEZE\000"
2183 /* 2078 */ "G_FCANONICALIZE\000"
2184 /* 2094 */ "G_CTLZ_ZERO_UNDEF\000"
2185 /* 2112 */ "G_CTTZ_ZERO_UNDEF\000"
2186 /* 2130 */ "INIT_UNDEF\000"
2187 /* 2141 */ "G_IMPLICIT_DEF\000"
2188 /* 2156 */ "DBG_INSTR_REF\000"
2189 /* 2170 */ "G_FNEG\000"
2190 /* 2177 */ "EXTRACT_SUBREG\000"
2191 /* 2192 */ "INSERT_SUBREG\000"
2192 /* 2206 */ "G_SEXT_INREG\000"
2193 /* 2219 */ "SUBREG_TO_REG\000"
2194 /* 2233 */ "G_ATOMIC_CMPXCHG\000"
2195 /* 2250 */ "G_ATOMICRMW_XCHG\000"
2196 /* 2267 */ "G_FLOG\000"
2197 /* 2274 */ "G_VAARG\000"
2198 /* 2282 */ "PREALLOCATED_ARG\000"
2199 /* 2299 */ "G_PREFETCH\000"
2200 /* 2310 */ "G_SMULH\000"
2201 /* 2318 */ "G_UMULH\000"
2202 /* 2326 */ "G_FTANH\000"
2203 /* 2334 */ "G_FSINH\000"
2204 /* 2342 */ "G_FCOSH\000"
2205 /* 2350 */ "FLUSH\000"
2206 /* 2356 */ "DBG_PHI\000"
2207 /* 2364 */ "FPMADDXHI\000"
2208 /* 2374 */ "UMULXHI\000"
2209 /* 2382 */ "XMULXHI\000"
2210 /* 2390 */ "FDTOI\000"
2211 /* 2396 */ "FQTOI\000"
2212 /* 2402 */ "FSTOI\000"
2213 /* 2408 */ "G_FPTOSI\000"
2214 /* 2417 */ "G_FPTOUI\000"
2215 /* 2426 */ "G_FPOWI\000"
2216 /* 2434 */ "BMASK\000"
2217 /* 2440 */ "G_PTRMASK\000"
2218 /* 2450 */ "EDGE32L\000"
2219 /* 2458 */ "EDGE16L\000"
2220 /* 2466 */ "EDGE8L\000"
2221 /* 2473 */ "FMUL8X16AL\000"
2222 /* 2484 */ "GC_LABEL\000"
2223 /* 2493 */ "DBG_LABEL\000"
2224 /* 2503 */ "EH_LABEL\000"
2225 /* 2512 */ "ANNOTATION_LABEL\000"
2226 /* 2529 */ "ICALL_BRANCH_FUNNEL\000"
2227 /* 2549 */ "G_FSHL\000"
2228 /* 2556 */ "G_SHL\000"
2229 /* 2562 */ "G_FCEIL\000"
2230 /* 2570 */ "PATCHABLE_TAIL_CALL\000"
2231 /* 2590 */ "TLS_CALL\000"
2232 /* 2599 */ "PATCHABLE_TYPED_EVENT_CALL\000"
2233 /* 2626 */ "PATCHABLE_EVENT_CALL\000"
2234 /* 2647 */ "FENTRY_CALL\000"
2235 /* 2659 */ "KILL\000"
2236 /* 2664 */ "G_CONSTANT_POOL\000"
2237 /* 2680 */ "ALIGNADDRL\000"
2238 /* 2691 */ "RETL\000"
2239 /* 2696 */ "G_ROTL\000"
2240 /* 2703 */ "G_VECREDUCE_FMUL\000"
2241 /* 2720 */ "G_FMUL\000"
2242 /* 2727 */ "G_VECREDUCE_SEQ_FMUL\000"
2243 /* 2748 */ "G_STRICT_FMUL\000"
2244 /* 2762 */ "G_VECREDUCE_MUL\000"
2245 /* 2778 */ "G_MUL\000"
2246 /* 2784 */ "SIAM\000"
2247 /* 2789 */ "G_FREM\000"
2248 /* 2796 */ "G_STRICT_FREM\000"
2249 /* 2810 */ "G_SREM\000"
2250 /* 2817 */ "G_UREM\000"
2251 /* 2824 */ "G_SDIVREM\000"
2252 /* 2834 */ "G_UDIVREM\000"
2253 /* 2844 */ "RDWIM\000"
2254 /* 2850 */ "INLINEASM\000"
2255 /* 2860 */ "G_VECREDUCE_FMINIMUM\000"
2256 /* 2881 */ "G_FMINIMUM\000"
2257 /* 2892 */ "G_ATOMICRMW_FMINIMUM\000"
2258 /* 2913 */ "G_VECREDUCE_FMAXIMUM\000"
2259 /* 2934 */ "G_FMAXIMUM\000"
2260 /* 2945 */ "G_ATOMICRMW_FMAXIMUM\000"
2261 /* 2966 */ "G_FMINIMUMNUM\000"
2262 /* 2980 */ "G_FMAXIMUMNUM\000"
2263 /* 2994 */ "G_FMINNUM\000"
2264 /* 3004 */ "G_FMAXNUM\000"
2265 /* 3014 */ "EDGE32N\000"
2266 /* 3022 */ "EDGE16N\000"
2267 /* 3030 */ "EDGE8N\000"
2268 /* 3037 */ "ALLCLEAN\000"
2269 /* 3046 */ "G_FATAN\000"
2270 /* 3054 */ "G_FTAN\000"
2271 /* 3061 */ "G_INTRINSIC_ROUNDEVEN\000"
2272 /* 3083 */ "G_ASSERT_ALIGN\000"
2273 /* 3098 */ "G_FCOPYSIGN\000"
2274 /* 3110 */ "G_VECREDUCE_FMIN\000"
2275 /* 3127 */ "G_ATOMICRMW_FMIN\000"
2276 /* 3144 */ "G_VECREDUCE_SMIN\000"
2277 /* 3161 */ "G_SMIN\000"
2278 /* 3168 */ "G_VECREDUCE_UMIN\000"
2279 /* 3185 */ "G_UMIN\000"
2280 /* 3192 */ "G_ATOMICRMW_UMIN\000"
2281 /* 3209 */ "G_ATOMICRMW_MIN\000"
2282 /* 3225 */ "G_FASIN\000"
2283 /* 3233 */ "G_FSIN\000"
2284 /* 3240 */ "EDGE32LN\000"
2285 /* 3249 */ "EDGE16LN\000"
2286 /* 3258 */ "EDGE8LN\000"
2287 /* 3266 */ "CFI_INSTRUCTION\000"
2288 /* 3282 */ "PDISTN\000"
2289 /* 3289 */ "ADJCALLSTACKDOWN\000"
2290 /* 3306 */ "SHUTDOWN\000"
2291 /* 3315 */ "G_SSUBO\000"
2292 /* 3323 */ "G_USUBO\000"
2293 /* 3331 */ "G_SADDO\000"
2294 /* 3339 */ "G_UADDO\000"
2295 /* 3347 */ "JUMP_TABLE_DEBUG_INFO\000"
2296 /* 3369 */ "G_SMULO\000"
2297 /* 3377 */ "G_UMULO\000"
2298 /* 3385 */ "G_BZERO\000"
2299 /* 3393 */ "FZERO\000"
2300 /* 3399 */ "STACKMAP\000"
2301 /* 3408 */ "G_DEBUGTRAP\000"
2302 /* 3420 */ "G_UBSANTRAP\000"
2303 /* 3432 */ "G_TRAP\000"
2304 /* 3439 */ "G_ATOMICRMW_UDEC_WRAP\000"
2305 /* 3461 */ "G_ATOMICRMW_UINC_WRAP\000"
2306 /* 3483 */ "G_BSWAP\000"
2307 /* 3491 */ "G_SITOFP\000"
2308 /* 3500 */ "G_UITOFP\000"
2309 /* 3509 */ "G_FCMP\000"
2310 /* 3516 */ "G_ICMP\000"
2311 /* 3523 */ "G_SCMP\000"
2312 /* 3530 */ "G_UCMP\000"
2313 /* 3537 */ "UNIMP\000"
2314 /* 3543 */ "NOP\000"
2315 /* 3547 */ "CONVERGENCECTRL_LOOP\000"
2316 /* 3568 */ "G_CTPOP\000"
2317 /* 3576 */ "PATCHABLE_OP\000"
2318 /* 3589 */ "FAULTING_OP\000"
2319 /* 3601 */ "ADJCALLSTACKUP\000"
2320 /* 3616 */ "PREALLOCATED_SETUP\000"
2321 /* 3635 */ "G_FLDEXP\000"
2322 /* 3644 */ "G_STRICT_FLDEXP\000"
2323 /* 3660 */ "G_FEXP\000"
2324 /* 3667 */ "G_FFREXP\000"
2325 /* 3676 */ "FSUBQ\000"
2326 /* 3682 */ "FADDQ\000"
2327 /* 3688 */ "V9FCMPEQ\000"
2328 /* 3697 */ "RDFQ\000"
2329 /* 3702 */ "FNEGQ\000"
2330 /* 3708 */ "FDMULQ\000"
2331 /* 3715 */ "FMULQ\000"
2332 /* 3721 */ "FDTOQ\000"
2333 /* 3727 */ "FITOQ\000"
2334 /* 3733 */ "FSTOQ\000"
2335 /* 3739 */ "FXTOQ\000"
2336 /* 3745 */ "V9FCMPQ\000"
2337 /* 3753 */ "FMOVRQ\000"
2338 /* 3760 */ "FABSQ\000"
2339 /* 3766 */ "FSQRTQ\000"
2340 /* 3773 */ "FDIVQ\000"
2341 /* 3779 */ "FMOVQ\000"
2342 /* 3785 */ "STBAR\000"
2343 /* 3791 */ "RDTBR\000"
2344 /* 3797 */ "G_BR\000"
2345 /* 3802 */ "INLINEASM_BR\000"
2346 /* 3815 */ "ALIGNADDR\000"
2347 /* 3825 */ "G_BLOCK_ADDR\000"
2348 /* 3838 */ "MEMBARRIER\000"
2349 /* 3849 */ "G_CONSTANT_FOLD_BARRIER\000"
2350 /* 3873 */ "PATCHABLE_FUNCTION_ENTER\000"
2351 /* 3898 */ "G_READCYCLECOUNTER\000"
2352 /* 3917 */ "G_READSTEADYCOUNTER\000"
2353 /* 3937 */ "G_READ_REGISTER\000"
2354 /* 3953 */ "G_WRITE_REGISTER\000"
2355 /* 3970 */ "G_ASHR\000"
2356 /* 3977 */ "G_FSHR\000"
2357 /* 3984 */ "G_LSHR\000"
2358 /* 3991 */ "SIR\000"
2359 /* 3995 */ "FOR\000"
2360 /* 3999 */ "CONVERGENCECTRL_ANCHOR\000"
2361 /* 4022 */ "FNOR\000"
2362 /* 4027 */ "FXNOR\000"
2363 /* 4033 */ "G_FFLOOR\000"
2364 /* 4042 */ "G_EXTRACT_SUBVECTOR\000"
2365 /* 4062 */ "G_INSERT_SUBVECTOR\000"
2366 /* 4081 */ "G_BUILD_VECTOR\000"
2367 /* 4096 */ "G_SHUFFLE_VECTOR\000"
2368 /* 4113 */ "G_STEP_VECTOR\000"
2369 /* 4127 */ "G_SPLAT_VECTOR\000"
2370 /* 4142 */ "FXOR\000"
2371 /* 4147 */ "G_VECREDUCE_XOR\000"
2372 /* 4163 */ "G_XOR\000"
2373 /* 4169 */ "G_ATOMICRMW_XOR\000"
2374 /* 4185 */ "G_VECREDUCE_OR\000"
2375 /* 4200 */ "G_OR\000"
2376 /* 4205 */ "G_ATOMICRMW_OR\000"
2377 /* 4220 */ "BPR\000"
2378 /* 4224 */ "RDPR\000"
2379 /* 4229 */ "RDASR\000"
2380 /* 4235 */ "RDPSR\000"
2381 /* 4241 */ "G_ROTR\000"
2382 /* 4248 */ "G_INTTOPTR\000"
2383 /* 4259 */ "FSRC1S\000"
2384 /* 4266 */ "FANDNOT1S\000"
2385 /* 4276 */ "FNOT1S\000"
2386 /* 4283 */ "FORNOT1S\000"
2387 /* 4292 */ "FPSUB32S\000"
2388 /* 4301 */ "FPADD32S\000"
2389 /* 4310 */ "FSRC2S\000"
2390 /* 4317 */ "FANDNOT2S\000"
2391 /* 4327 */ "FNOT2S\000"
2392 /* 4334 */ "FORNOT2S\000"
2393 /* 4343 */ "FPSUB16S\000"
2394 /* 4352 */ "FPADD16S\000"
2395 /* 4361 */ "G_FABS\000"
2396 /* 4368 */ "G_ABS\000"
2397 /* 4374 */ "FSUBS\000"
2398 /* 4380 */ "FHSUBS\000"
2399 /* 4387 */ "FMSUBS\000"
2400 /* 4394 */ "FNMSUBS\000"
2401 /* 4402 */ "G_ABDS\000"
2402 /* 4409 */ "FADDS\000"
2403 /* 4415 */ "FHADDS\000"
2404 /* 4422 */ "FNHADDS\000"
2405 /* 4430 */ "FMADDS\000"
2406 /* 4437 */ "FNMADDS\000"
2407 /* 4445 */ "FNADDS\000"
2408 /* 4452 */ "FANDS\000"
2409 /* 4458 */ "FNANDS\000"
2410 /* 4465 */ "FONES\000"
2411 /* 4471 */ "V9FCMPES\000"
2412 /* 4480 */ "G_UNMERGE_VALUES\000"
2413 /* 4497 */ "G_MERGE_VALUES\000"
2414 /* 4512 */ "FNEGS\000"
2415 /* 4518 */ "FMULS\000"
2416 /* 4524 */ "FNMULS\000"
2417 /* 4531 */ "G_FACOS\000"
2418 /* 4539 */ "G_FCOS\000"
2419 /* 4546 */ "G_FSINCOS\000"
2420 /* 4556 */ "FZEROS\000"
2421 /* 4563 */ "FDTOS\000"
2422 /* 4569 */ "FITOS\000"
2423 /* 4575 */ "FQTOS\000"
2424 /* 4581 */ "MOVWTOS\000"
2425 /* 4589 */ "FXTOS\000"
2426 /* 4595 */ "V9FCMPS\000"
2427 /* 4603 */ "FLCMPS\000"
2428 /* 4610 */ "FORS\000"
2429 /* 4615 */ "FNORS\000"
2430 /* 4621 */ "FXNORS\000"
2431 /* 4628 */ "G_CONCAT_VECTORS\000"
2432 /* 4645 */ "FXORS\000"
2433 /* 4651 */ "FMOVRS\000"
2434 /* 4658 */ "COPY_TO_REGCLASS\000"
2435 /* 4675 */ "G_IS_FPCLASS\000"
2436 /* 4688 */ "FABSS\000"
2437 /* 4694 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
2438 /* 4724 */ "G_VECTOR_COMPRESS\000"
2439 /* 4742 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
2440 /* 4769 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
2441 /* 4807 */ "FSQRTS\000"
2442 /* 4814 */ "FDIVS\000"
2443 /* 4820 */ "FMOVS\000"
2444 /* 4826 */ "G_SSUBSAT\000"
2445 /* 4836 */ "G_USUBSAT\000"
2446 /* 4846 */ "G_SADDSAT\000"
2447 /* 4856 */ "G_UADDSAT\000"
2448 /* 4866 */ "G_SSHLSAT\000"
2449 /* 4876 */ "G_USHLSAT\000"
2450 /* 4886 */ "G_SMULFIXSAT\000"
2451 /* 4899 */ "G_UMULFIXSAT\000"
2452 /* 4912 */ "G_SDIVFIXSAT\000"
2453 /* 4925 */ "G_UDIVFIXSAT\000"
2454 /* 4938 */ "G_ATOMICRMW_USUB_SAT\000"
2455 /* 4959 */ "G_FPTOSI_SAT\000"
2456 /* 4972 */ "G_FPTOUI_SAT\000"
2457 /* 4985 */ "G_EXTRACT\000"
2458 /* 4995 */ "G_SELECT\000"
2459 /* 5004 */ "G_BRINDIRECT\000"
2460 /* 5017 */ "PATCHABLE_RET\000"
2461 /* 5031 */ "G_MEMSET\000"
2462 /* 5040 */ "PATCHABLE_FUNCTION_EXIT\000"
2463 /* 5064 */ "G_BRJT\000"
2464 /* 5071 */ "G_EXTRACT_VECTOR_ELT\000"
2465 /* 5092 */ "G_INSERT_VECTOR_ELT\000"
2466 /* 5112 */ "BPFCCANT\000"
2467 /* 5121 */ "BPICCANT\000"
2468 /* 5130 */ "BPXCCANT\000"
2469 /* 5139 */ "BPRANT\000"
2470 /* 5146 */ "G_FCONSTANT\000"
2471 /* 5158 */ "G_CONSTANT\000"
2472 /* 5169 */ "BPFCCNT\000"
2473 /* 5177 */ "BPICCNT\000"
2474 /* 5185 */ "BPXCCNT\000"
2475 /* 5193 */ "LZCNT\000"
2476 /* 5199 */ "G_INTRINSIC_CONVERGENT\000"
2477 /* 5222 */ "STATEPOINT\000"
2478 /* 5233 */ "PATCHPOINT\000"
2479 /* 5244 */ "G_PTRTOINT\000"
2480 /* 5255 */ "G_FRINT\000"
2481 /* 5263 */ "G_INTRINSIC_LLRINT\000"
2482 /* 5282 */ "G_INTRINSIC_LRINT\000"
2483 /* 5300 */ "G_FNEARBYINT\000"
2484 /* 5313 */ "BPRNT\000"
2485 /* 5319 */ "G_VASTART\000"
2486 /* 5329 */ "LIFETIME_START\000"
2487 /* 5344 */ "G_INVOKE_REGION_START\000"
2488 /* 5366 */ "G_INSERT\000"
2489 /* 5375 */ "G_FSQRT\000"
2490 /* 5383 */ "G_STRICT_FSQRT\000"
2491 /* 5398 */ "G_BITCAST\000"
2492 /* 5408 */ "G_ADDRSPACE_CAST\000"
2493 /* 5425 */ "PDIST\000"
2494 /* 5431 */ "DBG_VALUE_LIST\000"
2495 /* 5446 */ "G_FPEXT\000"
2496 /* 5454 */ "G_SEXT\000"
2497 /* 5461 */ "G_ASSERT_SEXT\000"
2498 /* 5475 */ "G_ANYEXT\000"
2499 /* 5484 */ "G_ZEXT\000"
2500 /* 5491 */ "G_ASSERT_ZEXT\000"
2501 /* 5505 */ "FMUL8X16AU\000"
2502 /* 5516 */ "G_ABDU\000"
2503 /* 5523 */ "G_FDIV\000"
2504 /* 5530 */ "G_STRICT_FDIV\000"
2505 /* 5544 */ "G_SDIV\000"
2506 /* 5551 */ "G_UDIV\000"
2507 /* 5558 */ "G_GET_FPENV\000"
2508 /* 5570 */ "G_RESET_FPENV\000"
2509 /* 5584 */ "G_SET_FPENV\000"
2510 /* 5596 */ "FLUSHW\000"
2511 /* 5603 */ "NORMALW\000"
2512 /* 5611 */ "INVALW\000"
2513 /* 5618 */ "G_FPOW\000"
2514 /* 5625 */ "OTHERW\000"
2515 /* 5632 */ "MOVSTOSW\000"
2516 /* 5641 */ "SETSW\000"
2517 /* 5647 */ "MOVSTOUW\000"
2518 /* 5656 */ "G_VECREDUCE_FMAX\000"
2519 /* 5673 */ "G_ATOMICRMW_FMAX\000"
2520 /* 5690 */ "G_VECREDUCE_SMAX\000"
2521 /* 5707 */ "G_SMAX\000"
2522 /* 5714 */ "G_VECREDUCE_UMAX\000"
2523 /* 5731 */ "G_UMAX\000"
2524 /* 5738 */ "G_ATOMICRMW_UMAX\000"
2525 /* 5755 */ "G_ATOMICRMW_MAX\000"
2526 /* 5771 */ "GETPCX\000"
2527 /* 5778 */ "FPMADDX\000"
2528 /* 5786 */ "G_FRAME_INDEX\000"
2529 /* 5800 */ "G_SBFX\000"
2530 /* 5807 */ "G_UBFX\000"
2531 /* 5814 */ "FPACKFIX\000"
2532 /* 5823 */ "G_SMULFIX\000"
2533 /* 5833 */ "G_UMULFIX\000"
2534 /* 5843 */ "G_SDIVFIX\000"
2535 /* 5853 */ "G_UDIVFIX\000"
2536 /* 5863 */ "XMULX\000"
2537 /* 5869 */ "FDTOX\000"
2538 /* 5875 */ "MOVDTOX\000"
2539 /* 5883 */ "FQTOX\000"
2540 /* 5889 */ "FSTOX\000"
2541 /* 5895 */ "SETX\000"
2542 /* 5900 */ "G_MEMCPY\000"
2543 /* 5909 */ "COPY\000"
2544 /* 5914 */ "RETRY\000"
2545 /* 5920 */ "CONVERGENCECTRL_ENTRY\000"
2546 /* 5942 */ "G_CTLZ\000"
2547 /* 5949 */ "G_CTTZ\000"
2548 /* 5956 */ "PREFETCHAi\000"
2549 /* 5967 */ "PREFETCHi\000"
2550 /* 5977 */ "SETHIi\000"
2551 /* 5984 */ "CALLi\000"
2552 /* 5990 */ "MEMBARi\000"
2553 /* 5998 */ "CALLrii\000"
2554 /* 6006 */ "LDSBAri\000"
2555 /* 6014 */ "STBAri\000"
2556 /* 6021 */ "LDUBAri\000"
2557 /* 6029 */ "LDSTUBAri\000"
2558 /* 6039 */ "LDDAri\000"
2559 /* 6046 */ "LDAri\000"
2560 /* 6052 */ "STDAri\000"
2561 /* 6059 */ "LDDFAri\000"
2562 /* 6067 */ "LDFAri\000"
2563 /* 6074 */ "STDFAri\000"
2564 /* 6082 */ "LDQFAri\000"
2565 /* 6090 */ "STQFAri\000"
2566 /* 6098 */ "STFAri\000"
2567 /* 6105 */ "LDSHAri\000"
2568 /* 6113 */ "STHAri\000"
2569 /* 6120 */ "LDUHAri\000"
2570 /* 6128 */ "SWAPAri\000"
2571 /* 6136 */ "SRAri\000"
2572 /* 6142 */ "CASAri\000"
2573 /* 6149 */ "STAri\000"
2574 /* 6155 */ "LDSWAri\000"
2575 /* 6163 */ "LDXAri\000"
2576 /* 6170 */ "CASXAri\000"
2577 /* 6178 */ "STXAri\000"
2578 /* 6185 */ "LDSBri\000"
2579 /* 6192 */ "STBri\000"
2580 /* 6198 */ "LDUBri\000"
2581 /* 6205 */ "SUBri\000"
2582 /* 6211 */ "LDSTUBri\000"
2583 /* 6220 */ "SMACri\000"
2584 /* 6227 */ "UMACri\000"
2585 /* 6234 */ "SUBCri\000"
2586 /* 6241 */ "TSUBCCri\000"
2587 /* 6250 */ "TADDCCri\000"
2588 /* 6259 */ "ANDCCri\000"
2589 /* 6267 */ "V9MOVFCCri\000"
2590 /* 6278 */ "TICCri\000"
2591 /* 6285 */ "MOVICCri\000"
2592 /* 6294 */ "SMULCCri\000"
2593 /* 6303 */ "UMULCCri\000"
2594 /* 6312 */ "ANDNCCri\000"
2595 /* 6321 */ "ORNCCri\000"
2596 /* 6329 */ "XNORCCri\000"
2597 /* 6338 */ "XORCCri\000"
2598 /* 6346 */ "MULSCCri\000"
2599 /* 6355 */ "SDIVCCri\000"
2600 /* 6364 */ "UDIVCCri\000"
2601 /* 6373 */ "TXCCri\000"
2602 /* 6380 */ "MOVXCCri\000"
2603 /* 6389 */ "ADDCri\000"
2604 /* 6396 */ "LDDCri\000"
2605 /* 6403 */ "LDCri\000"
2606 /* 6409 */ "STDCri\000"
2607 /* 6416 */ "STCri\000"
2608 /* 6422 */ "ADDri\000"
2609 /* 6428 */ "LDDri\000"
2610 /* 6434 */ "LDri\000"
2611 /* 6439 */ "ANDri\000"
2612 /* 6445 */ "BINDri\000"
2613 /* 6452 */ "CWBCONDri\000"
2614 /* 6462 */ "CXBCONDri\000"
2615 /* 6472 */ "STDri\000"
2616 /* 6478 */ "SUBEri\000"
2617 /* 6485 */ "ADDEri\000"
2618 /* 6492 */ "RESTOREri\000"
2619 /* 6502 */ "SAVEri\000"
2620 /* 6509 */ "LDDFri\000"
2621 /* 6516 */ "LDFri\000"
2622 /* 6522 */ "STDFri\000"
2623 /* 6529 */ "LDQFri\000"
2624 /* 6536 */ "STQFri\000"
2625 /* 6543 */ "STFri\000"
2626 /* 6549 */ "LDSHri\000"
2627 /* 6556 */ "FLUSHri\000"
2628 /* 6564 */ "STHri\000"
2629 /* 6570 */ "LDUHri\000"
2630 /* 6577 */ "TAIL_CALLri\000"
2631 /* 6589 */ "SLLri\000"
2632 /* 6595 */ "JMPLri\000"
2633 /* 6602 */ "SRLri\000"
2634 /* 6608 */ "SMULri\000"
2635 /* 6615 */ "UMULri\000"
2636 /* 6622 */ "WRWIMri\000"
2637 /* 6630 */ "ANDNri\000"
2638 /* 6637 */ "ORNri\000"
2639 /* 6643 */ "TRAPri\000"
2640 /* 6650 */ "SWAPri\000"
2641 /* 6657 */ "STDCQri\000"
2642 /* 6665 */ "STDFQri\000"
2643 /* 6673 */ "WRTBRri\000"
2644 /* 6681 */ "XNORri\000"
2645 /* 6688 */ "XORri\000"
2646 /* 6694 */ "WRPRri\000"
2647 /* 6701 */ "WRASRri\000"
2648 /* 6709 */ "LDCSRri\000"
2649 /* 6717 */ "STCSRri\000"
2650 /* 6725 */ "LDFSRri\000"
2651 /* 6733 */ "STFSRri\000"
2652 /* 6741 */ "LDXFSRri\000"
2653 /* 6750 */ "STXFSRri\000"
2654 /* 6759 */ "PWRPSRri\000"
2655 /* 6768 */ "MOVRri\000"
2656 /* 6775 */ "STri\000"
2657 /* 6780 */ "RETTri\000"
2658 /* 6787 */ "SDIVri\000"
2659 /* 6794 */ "UDIVri\000"
2660 /* 6801 */ "TSUBCCTVri\000"
2661 /* 6812 */ "TADDCCTVri\000"
2662 /* 6823 */ "LDSWri\000"
2663 /* 6830 */ "SRAXri\000"
2664 /* 6837 */ "LDXri\000"
2665 /* 6843 */ "SLLXri\000"
2666 /* 6850 */ "SRLXri\000"
2667 /* 6857 */ "MULXri\000"
2668 /* 6864 */ "STXri\000"
2669 /* 6870 */ "SDIVXri\000"
2670 /* 6878 */ "UDIVXri\000"
2671 /* 6886 */ "CALLrri\000"
2672 /* 6894 */ "PREFETCHAr\000"
2673 /* 6905 */ "PREFETCHr\000"
2674 /* 6915 */ "LDSBArr\000"
2675 /* 6923 */ "STBArr\000"
2676 /* 6930 */ "LDUBArr\000"
2677 /* 6938 */ "LDSTUBArr\000"
2678 /* 6948 */ "LDDArr\000"
2679 /* 6955 */ "LDArr\000"
2680 /* 6961 */ "STDArr\000"
2681 /* 6968 */ "LDDFArr\000"
2682 /* 6976 */ "LDFArr\000"
2683 /* 6983 */ "STDFArr\000"
2684 /* 6991 */ "LDQFArr\000"
2685 /* 6999 */ "STQFArr\000"
2686 /* 7007 */ "STFArr\000"
2687 /* 7014 */ "LDSHArr\000"
2688 /* 7022 */ "STHArr\000"
2689 /* 7029 */ "LDUHArr\000"
2690 /* 7037 */ "SWAPArr\000"
2691 /* 7045 */ "SRArr\000"
2692 /* 7051 */ "CASArr\000"
2693 /* 7058 */ "STArr\000"
2694 /* 7064 */ "LDSWArr\000"
2695 /* 7072 */ "LDXArr\000"
2696 /* 7079 */ "CASXArr\000"
2697 /* 7087 */ "STXArr\000"
2698 /* 7094 */ "LDSBrr\000"
2699 /* 7101 */ "STBrr\000"
2700 /* 7107 */ "LDUBrr\000"
2701 /* 7114 */ "SUBrr\000"
2702 /* 7120 */ "LDSTUBrr\000"
2703 /* 7129 */ "SMACrr\000"
2704 /* 7136 */ "UMACrr\000"
2705 /* 7143 */ "SUBCrr\000"
2706 /* 7150 */ "TSUBCCrr\000"
2707 /* 7159 */ "TADDCCrr\000"
2708 /* 7168 */ "ANDCCrr\000"
2709 /* 7176 */ "V9MOVFCCrr\000"
2710 /* 7187 */ "TICCrr\000"
2711 /* 7194 */ "MOVICCrr\000"
2712 /* 7203 */ "SMULCCrr\000"
2713 /* 7212 */ "UMULCCrr\000"
2714 /* 7221 */ "ANDNCCrr\000"
2715 /* 7230 */ "ORNCCrr\000"
2716 /* 7238 */ "XNORCCrr\000"
2717 /* 7247 */ "XORCCrr\000"
2718 /* 7255 */ "MULSCCrr\000"
2719 /* 7264 */ "SDIVCCrr\000"
2720 /* 7273 */ "UDIVCCrr\000"
2721 /* 7282 */ "TXCCrr\000"
2722 /* 7289 */ "MOVXCCrr\000"
2723 /* 7298 */ "ADDCrr\000"
2724 /* 7305 */ "LDDCrr\000"
2725 /* 7312 */ "LDCrr\000"
2726 /* 7318 */ "STDCrr\000"
2727 /* 7325 */ "POPCrr\000"
2728 /* 7332 */ "STCrr\000"
2729 /* 7338 */ "TLS_ADDrr\000"
2730 /* 7348 */ "LDDrr\000"
2731 /* 7354 */ "GDOP_LDrr\000"
2732 /* 7364 */ "TLS_LDrr\000"
2733 /* 7373 */ "ANDrr\000"
2734 /* 7379 */ "BINDrr\000"
2735 /* 7386 */ "CWBCONDrr\000"
2736 /* 7396 */ "CXBCONDrr\000"
2737 /* 7406 */ "STDrr\000"
2738 /* 7412 */ "SUBErr\000"
2739 /* 7419 */ "ADDErr\000"
2740 /* 7426 */ "RESTORErr\000"
2741 /* 7436 */ "SAVErr\000"
2742 /* 7443 */ "LDDFrr\000"
2743 /* 7450 */ "LDFrr\000"
2744 /* 7456 */ "STDFrr\000"
2745 /* 7463 */ "LDQFrr\000"
2746 /* 7470 */ "STQFrr\000"
2747 /* 7477 */ "STFrr\000"
2748 /* 7483 */ "LDSHrr\000"
2749 /* 7490 */ "FLUSHrr\000"
2750 /* 7498 */ "STHrr\000"
2751 /* 7504 */ "LDUHrr\000"
2752 /* 7511 */ "CALLrr\000"
2753 /* 7518 */ "SLLrr\000"
2754 /* 7524 */ "JMPLrr\000"
2755 /* 7531 */ "SRLrr\000"
2756 /* 7537 */ "SMULrr\000"
2757 /* 7544 */ "UMULrr\000"
2758 /* 7551 */ "WRWIMrr\000"
2759 /* 7559 */ "ANDNrr\000"
2760 /* 7566 */ "ORNrr\000"
2761 /* 7572 */ "TRAPrr\000"
2762 /* 7579 */ "SWAPrr\000"
2763 /* 7586 */ "STDCQrr\000"
2764 /* 7594 */ "STDFQrr\000"
2765 /* 7602 */ "WRTBRrr\000"
2766 /* 7610 */ "XNORrr\000"
2767 /* 7617 */ "XORrr\000"
2768 /* 7623 */ "WRPRrr\000"
2769 /* 7630 */ "WRASRrr\000"
2770 /* 7638 */ "LDCSRrr\000"
2771 /* 7646 */ "STCSRrr\000"
2772 /* 7654 */ "LDFSRrr\000"
2773 /* 7662 */ "STFSRrr\000"
2774 /* 7670 */ "LDXFSRrr\000"
2775 /* 7679 */ "STXFSRrr\000"
2776 /* 7688 */ "PWRPSRrr\000"
2777 /* 7697 */ "MOVRrr\000"
2778 /* 7704 */ "STrr\000"
2779 /* 7709 */ "RETTrr\000"
2780 /* 7716 */ "SDIVrr\000"
2781 /* 7723 */ "UDIVrr\000"
2782 /* 7730 */ "TSUBCCTVrr\000"
2783 /* 7741 */ "TADDCCTVrr\000"
2784 /* 7752 */ "LDSWrr\000"
2785 /* 7759 */ "SRAXrr\000"
2786 /* 7766 */ "GDOP_LDXrr\000"
2787 /* 7777 */ "TLS_LDXrr\000"
2788 /* 7787 */ "SLLXrr\000"
2789 /* 7794 */ "SRLXrr\000"
2790 /* 7801 */ "MULXrr\000"
2791 /* 7808 */ "STXrr\000"
2792 /* 7814 */ "SDIVXrr\000"
2793 /* 7822 */ "UDIVXrr\000"
2794};
2795#ifdef __GNUC__
2796#pragma GCC diagnostic pop
2797#endif
2798
2799extern const unsigned SparcInstrNameIndices[] = {
2800 2360U, 2850U, 3802U, 3266U, 2503U, 2484U, 2512U, 2659U,
2801 2177U, 2192U, 2143U, 2130U, 2219U, 4658U, 1978U, 5431U,
2802 2156U, 2356U, 2493U, 1732U, 5909U, 1862U, 5329U, 1465U,
2803 1683U, 1720U, 3399U, 2647U, 5233U, 1634U, 3616U, 2282U,
2804 5222U, 1904U, 3589U, 3576U, 3873U, 5017U, 5040U, 2570U,
2805 2626U, 2599U, 2529U, 1969U, 3838U, 3347U, 5920U, 3999U,
2806 3547U, 2026U, 5461U, 5491U, 3083U, 1258U, 600U, 2778U,
2807 5544U, 5551U, 2810U, 2817U, 2824U, 2834U, 1443U, 4200U,
2808 4163U, 4402U, 5516U, 2141U, 2358U, 5786U, 1988U, 2003U,
2809 2664U, 4985U, 4480U, 5366U, 4497U, 4081U, 1005U, 4628U,
2810 5244U, 4248U, 5398U, 2069U, 3849U, 1561U, 979U, 1543U,
2811 5282U, 5263U, 3061U, 3898U, 3917U, 1131U, 1075U, 1105U,
2812 1116U, 1056U, 1086U, 1948U, 1932U, 4694U, 2233U, 2250U,
2813 1274U, 606U, 1449U, 1402U, 4205U, 4169U, 5755U, 3209U,
2814 5738U, 3192U, 1225U, 583U, 5673U, 3127U, 2945U, 2892U,
2815 3461U, 3439U, 1502U, 4938U, 1712U, 2299U, 1493U, 5004U,
2816 5344U, 957U, 4742U, 5199U, 4769U, 5475U, 997U, 5158U,
2817 5146U, 5319U, 2274U, 5454U, 2206U, 5484U, 2556U, 3984U,
2818 3970U, 2549U, 3977U, 4241U, 2696U, 3516U, 3509U, 3523U,
2819 3530U, 4995U, 3339U, 1753U, 3323U, 1704U, 3331U, 1745U,
2820 3315U, 1696U, 3377U, 3369U, 2318U, 2310U, 4856U, 4846U,
2821 4836U, 4826U, 4876U, 4866U, 5823U, 5833U, 4886U, 4899U,
2822 5843U, 5853U, 4912U, 4925U, 1183U, 562U, 2720U, 526U,
2823 1049U, 5523U, 2789U, 5618U, 2426U, 3660U, 186U, 9U,
2824 2267U, 169U, 0U, 3635U, 3667U, 2170U, 5446U, 969U,
2825 2408U, 2417U, 3491U, 3500U, 4959U, 4972U, 4361U, 3098U,
2826 4675U, 2078U, 2994U, 3004U, 1802U, 1817U, 2881U, 2934U,
2827 2966U, 2980U, 5558U, 5584U, 5570U, 1761U, 1789U, 1774U,
2828 1264U, 2440U, 3161U, 5707U, 3185U, 5731U, 4368U, 1534U,
2829 1524U, 3797U, 5064U, 1840U, 4062U, 4042U, 5092U, 5071U,
2830 4096U, 4127U, 4113U, 4724U, 5949U, 2112U, 5942U, 2094U,
2831 3568U, 3483U, 1956U, 2562U, 4539U, 3233U, 4546U, 3054U,
2832 4531U, 3225U, 3046U, 177U, 2342U, 2334U, 2326U, 5375U,
2833 4033U, 5255U, 5300U, 5408U, 3825U, 1849U, 1026U, 2047U,
2834 1917U, 1211U, 569U, 2748U, 5530U, 2796U, 532U, 5383U,
2835 3644U, 3937U, 3953U, 5900U, 1878U, 2059U, 5031U, 3385U,
2836 3432U, 3408U, 3420U, 1190U, 2727U, 1166U, 2703U, 5656U,
2837 3110U, 2913U, 2860U, 1242U, 2762U, 1427U, 4185U, 4147U,
2838 5690U, 3144U, 5714U, 3168U, 5800U, 5807U, 3289U, 3601U,
2839 5771U, 648U, 759U, 866U, 684U, 795U, 902U, 725U,
2840 832U, 939U, 666U, 777U, 884U, 5036U, 5641U, 5895U,
2841 6251U, 7160U, 6389U, 7298U, 6485U, 7419U, 1043U, 622U,
2842 6422U, 7342U, 3815U, 2680U, 3037U, 6259U, 7168U, 6312U,
2843 7221U, 6630U, 7559U, 6439U, 7373U, 409U, 155U, 430U,
2844 485U, 1479U, 510U, 6445U, 7379U, 2434U, 630U, 488U,
2845 5112U, 5169U, 743U, 495U, 5121U, 5177U, 4220U, 545U,
2846 5139U, 5313U, 850U, 502U, 5130U, 5185U, 1869U, 2585U,
2847 5984U, 6582U, 5998U, 7511U, 6886U, 6142U, 7051U, 6170U,
2848 7079U, 289U, 107U, 423U, 1485U, 517U, 6452U, 7386U,
2849 6462U, 7396U, 1894U, 256U, 2458U, 3249U, 3022U, 74U,
2850 2450U, 3240U, 3014U, 417U, 2466U, 3258U, 3030U, 1658U,
2851 3760U, 4688U, 1290U, 3682U, 4409U, 550U, 1391U, 28U,
2852 4266U, 194U, 4317U, 4452U, 1478U, 509U, 437U, 448U,
2853 311U, 1621U, 458U, 328U, 129U, 345U, 146U, 263U,
2854 81U, 272U, 90U, 3747U, 467U, 4597U, 476U, 1671U,
2855 3773U, 4814U, 3708U, 2390U, 3721U, 4563U, 5869U, 1419U,
2856 1296U, 4415U, 1144U, 4380U, 1587U, 3727U, 4569U, 1627U,
2857 4603U, 2350U, 5596U, 6556U, 7490U, 1311U, 4430U, 320U,
2858 1677U, 638U, 749U, 856U, 3779U, 703U, 812U, 919U,
2859 1651U, 3753U, 4651U, 4820U, 715U, 822U, 929U, 1151U,
2860 4387U, 398U, 375U, 354U, 2473U, 5505U, 1363U, 386U,
2861 363U, 3715U, 4518U, 1326U, 4445U, 1396U, 4458U, 1357U,
2862 3702U, 4512U, 1303U, 4422U, 1318U, 4437U, 1158U, 4394U,
2863 1369U, 4524U, 4022U, 4615U, 37U, 4276U, 203U, 4327U,
2864 1383U, 1899U, 4465U, 3995U, 43U, 4283U, 209U, 4334U,
2865 4610U, 281U, 99U, 5814U, 248U, 4352U, 66U, 4301U,
2866 221U, 5778U, 2364U, 1832U, 240U, 4343U, 58U, 4292U,
2867 1593U, 2396U, 4575U, 5883U, 337U, 138U, 297U, 115U,
2868 1376U, 1664U, 3766U, 4807U, 233U, 51U, 22U, 4259U,
2869 163U, 4310U, 304U, 122U, 1599U, 2402U, 3733U, 5889U,
2870 1138U, 3676U, 4374U, 4027U, 4621U, 4142U, 4645U, 1605U,
2871 3739U, 4589U, 3393U, 4556U, 7766U, 7354U, 5611U, 6595U,
2872 7524U, 6046U, 6955U, 6709U, 7638U, 6403U, 7312U, 6039U,
2873 6948U, 6396U, 7305U, 6059U, 6968U, 6509U, 7443U, 6428U,
2874 7348U, 6067U, 6976U, 6725U, 7654U, 6516U, 7450U, 6082U,
2875 6991U, 6529U, 7463U, 6006U, 6915U, 6185U, 7094U, 6105U,
2876 7014U, 6549U, 7483U, 6029U, 6938U, 6211U, 7120U, 6155U,
2877 7064U, 6823U, 7752U, 6021U, 6930U, 6198U, 7107U, 6120U,
2878 7029U, 6570U, 7504U, 6163U, 7072U, 6741U, 7670U, 6837U,
2879 7771U, 6434U, 7359U, 5193U, 5990U, 5875U, 6269U, 7178U,
2880 6285U, 7194U, 6768U, 7697U, 5632U, 5647U, 4581U, 6380U,
2881 7289U, 1611U, 6346U, 7255U, 6857U, 7801U, 3543U, 5603U,
2882 6331U, 7240U, 6321U, 7230U, 6637U, 7566U, 6683U, 7612U,
2883 5625U, 5425U, 3282U, 7325U, 5956U, 6894U, 5967U, 6905U,
2884 6759U, 7688U, 4229U, 3697U, 4224U, 4235U, 3791U, 2844U,
2885 1342U, 6492U, 7426U, 5027U, 2691U, 5914U, 6780U, 7709U,
2886 1351U, 6502U, 7436U, 6355U, 7264U, 6870U, 7814U, 6787U,
2887 7716U, 5977U, 3306U, 2784U, 3991U, 6843U, 7787U, 6589U,
2888 7518U, 6220U, 7129U, 6294U, 7203U, 6608U, 7537U, 6830U,
2889 7759U, 6136U, 7045U, 6850U, 7794U, 6602U, 7531U, 6149U,
2890 7058U, 3785U, 6014U, 6923U, 6192U, 7101U, 6717U, 7646U,
2891 6416U, 7332U, 6052U, 6961U, 6657U, 7586U, 6409U, 7318U,
2892 6074U, 6983U, 6665U, 7594U, 6522U, 7456U, 6472U, 7406U,
2893 6098U, 7007U, 6733U, 7662U, 6543U, 7477U, 6113U, 7022U,
2894 6564U, 7498U, 6090U, 6999U, 6536U, 7470U, 6178U, 7087U,
2895 6750U, 7679U, 6864U, 7808U, 6775U, 7704U, 6242U, 7151U,
2896 6234U, 7143U, 6478U, 7412U, 6205U, 7114U, 6128U, 7037U,
2897 6650U, 7579U, 18U, 217U, 229U, 6812U, 7741U, 6250U,
2898 7159U, 2580U, 6577U, 6278U, 7187U, 7338U, 2590U, 7777U,
2899 7364U, 6643U, 7572U, 6801U, 7730U, 6241U, 7150U, 6373U,
2900 7282U, 6364U, 7273U, 6878U, 7822U, 6794U, 7723U, 6227U,
2901 7136U, 6303U, 7212U, 2374U, 6615U, 7544U, 3537U, 1619U,
2902 1333U, 3688U, 4471U, 3745U, 4595U, 636U, 701U, 713U,
2903 6267U, 7176U, 6701U, 7630U, 6694U, 7623U, 6760U, 7689U,
2904 6673U, 7602U, 6622U, 7551U, 5863U, 2382U, 6329U, 7238U,
2905 6681U, 7610U, 6338U, 7247U, 6688U, 7617U,
2906};
2907
2908static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
2909 II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 846);
2910}
2911
2912} // end namespace llvm
2913#endif // GET_INSTRINFO_MC_DESC
2914
2915#ifdef GET_INSTRINFO_HEADER
2916#undef GET_INSTRINFO_HEADER
2917namespace llvm {
2918struct SparcGenInstrInfo : public TargetInstrInfo {
2919 explicit SparcGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2920 ~SparcGenInstrInfo() override = default;
2921
2922};
2923} // end namespace llvm
2924#endif // GET_INSTRINFO_HEADER
2925
2926#ifdef GET_INSTRINFO_HELPER_DECLS
2927#undef GET_INSTRINFO_HELPER_DECLS
2928
2929
2930#endif // GET_INSTRINFO_HELPER_DECLS
2931
2932#ifdef GET_INSTRINFO_HELPERS
2933#undef GET_INSTRINFO_HELPERS
2934
2935#endif // GET_INSTRINFO_HELPERS
2936
2937#ifdef GET_INSTRINFO_CTOR_DTOR
2938#undef GET_INSTRINFO_CTOR_DTOR
2939namespace llvm {
2940extern const SparcInstrTable SparcDescs;
2941extern const unsigned SparcInstrNameIndices[];
2942extern const char SparcInstrNameData[];
2943SparcGenInstrInfo::SparcGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2944 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2945 InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 846);
2946}
2947} // end namespace llvm
2948#endif // GET_INSTRINFO_CTOR_DTOR
2949
2950#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2951#undef GET_INSTRINFO_MC_HELPER_DECLS
2952
2953namespace llvm {
2954class MCInst;
2955class FeatureBitset;
2956
2957namespace Sparc_MC {
2958
2959void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2960
2961} // end namespace Sparc_MC
2962} // end namespace llvm
2963
2964#endif // GET_INSTRINFO_MC_HELPER_DECLS
2965
2966#ifdef GET_INSTRINFO_MC_HELPERS
2967#undef GET_INSTRINFO_MC_HELPERS
2968
2969namespace llvm::Sparc_MC {
2970} // end namespace llvm::Sparc_MC
2971#endif // GET_GENISTRINFO_MC_HELPERS
2972
2973#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2974 defined(GET_AVAILABLE_OPCODE_CHECKER)
2975#define GET_COMPUTE_FEATURES
2976#endif
2977#ifdef GET_COMPUTE_FEATURES
2978#undef GET_COMPUTE_FEATURES
2979namespace llvm::Sparc_MC {
2980// Bits for subtarget features that participate in instruction matching.
2981enum SubtargetFeatureBits : uint8_t {
2982 Feature_Is64BitBit = 9,
2983 Feature_UseSoftMulDivBit = 10,
2984 Feature_HasV9Bit = 5,
2985 Feature_HasVISBit = 6,
2986 Feature_HasVIS2Bit = 7,
2987 Feature_HasVIS3Bit = 8,
2988 Feature_HasUA2005Bit = 3,
2989 Feature_HasUA2007Bit = 4,
2990 Feature_HasOSA2011Bit = 1,
2991 Feature_HasCASABit = 0,
2992 Feature_HasPWRPSRBit = 2,
2993};
2994
2995inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2996 FeatureBitset Features;
2997 if (FB[Sparc::FeatureV9])
2998 Features.set(Feature_Is64BitBit);
2999 if (FB[Sparc::FeatureSoftMulDiv])
3000 Features.set(Feature_UseSoftMulDivBit);
3001 if (FB[Sparc::FeatureV9])
3002 Features.set(Feature_HasV9Bit);
3003 if (FB[Sparc::FeatureVIS])
3004 Features.set(Feature_HasVISBit);
3005 if (FB[Sparc::FeatureVIS2])
3006 Features.set(Feature_HasVIS2Bit);
3007 if (FB[Sparc::FeatureVIS3])
3008 Features.set(Feature_HasVIS3Bit);
3009 if (FB[Sparc::FeatureUA2005])
3010 Features.set(Feature_HasUA2005Bit);
3011 if (FB[Sparc::FeatureUA2007])
3012 Features.set(Feature_HasUA2007Bit);
3013 if (FB[Sparc::FeatureOSA2011])
3014 Features.set(Feature_HasOSA2011Bit);
3015 if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
3016 Features.set(Feature_HasCASABit);
3017 if (FB[Sparc::FeaturePWRPSR])
3018 Features.set(Feature_HasPWRPSRBit);
3019 return Features;
3020}
3021
3022inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
3023 enum : uint8_t {
3024 CEFBS_None,
3025 CEFBS_HasCASA,
3026 CEFBS_HasOSA2011,
3027 CEFBS_HasPWRPSR,
3028 CEFBS_HasUA2005,
3029 CEFBS_HasUA2007,
3030 CEFBS_HasV9,
3031 CEFBS_HasVIS,
3032 CEFBS_HasVIS2,
3033 CEFBS_HasVIS3,
3034 CEFBS_Is64Bit,
3035 CEFBS_Is64Bit_HasV9,
3036 };
3037
3038 static constexpr FeatureBitset FeatureBitsets[] = {
3039 {}, // CEFBS_None
3040 {Feature_HasCASABit, },
3041 {Feature_HasOSA2011Bit, },
3042 {Feature_HasPWRPSRBit, },
3043 {Feature_HasUA2005Bit, },
3044 {Feature_HasUA2007Bit, },
3045 {Feature_HasV9Bit, },
3046 {Feature_HasVISBit, },
3047 {Feature_HasVIS2Bit, },
3048 {Feature_HasVIS3Bit, },
3049 {Feature_Is64BitBit, },
3050 {Feature_Is64BitBit, Feature_HasV9Bit, },
3051 };
3052 static constexpr uint8_t RequiredFeaturesRefs[] = {
3053 CEFBS_None, // PHI = 0
3054 CEFBS_None, // INLINEASM = 1
3055 CEFBS_None, // INLINEASM_BR = 2
3056 CEFBS_None, // CFI_INSTRUCTION = 3
3057 CEFBS_None, // EH_LABEL = 4
3058 CEFBS_None, // GC_LABEL = 5
3059 CEFBS_None, // ANNOTATION_LABEL = 6
3060 CEFBS_None, // KILL = 7
3061 CEFBS_None, // EXTRACT_SUBREG = 8
3062 CEFBS_None, // INSERT_SUBREG = 9
3063 CEFBS_None, // IMPLICIT_DEF = 10
3064 CEFBS_None, // INIT_UNDEF = 11
3065 CEFBS_None, // SUBREG_TO_REG = 12
3066 CEFBS_None, // COPY_TO_REGCLASS = 13
3067 CEFBS_None, // DBG_VALUE = 14
3068 CEFBS_None, // DBG_VALUE_LIST = 15
3069 CEFBS_None, // DBG_INSTR_REF = 16
3070 CEFBS_None, // DBG_PHI = 17
3071 CEFBS_None, // DBG_LABEL = 18
3072 CEFBS_None, // REG_SEQUENCE = 19
3073 CEFBS_None, // COPY = 20
3074 CEFBS_None, // BUNDLE = 21
3075 CEFBS_None, // LIFETIME_START = 22
3076 CEFBS_None, // LIFETIME_END = 23
3077 CEFBS_None, // PSEUDO_PROBE = 24
3078 CEFBS_None, // ARITH_FENCE = 25
3079 CEFBS_None, // STACKMAP = 26
3080 CEFBS_None, // FENTRY_CALL = 27
3081 CEFBS_None, // PATCHPOINT = 28
3082 CEFBS_None, // LOAD_STACK_GUARD = 29
3083 CEFBS_None, // PREALLOCATED_SETUP = 30
3084 CEFBS_None, // PREALLOCATED_ARG = 31
3085 CEFBS_None, // STATEPOINT = 32
3086 CEFBS_None, // LOCAL_ESCAPE = 33
3087 CEFBS_None, // FAULTING_OP = 34
3088 CEFBS_None, // PATCHABLE_OP = 35
3089 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 36
3090 CEFBS_None, // PATCHABLE_RET = 37
3091 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 38
3092 CEFBS_None, // PATCHABLE_TAIL_CALL = 39
3093 CEFBS_None, // PATCHABLE_EVENT_CALL = 40
3094 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 41
3095 CEFBS_None, // ICALL_BRANCH_FUNNEL = 42
3096 CEFBS_None, // FAKE_USE = 43
3097 CEFBS_None, // MEMBARRIER = 44
3098 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 45
3099 CEFBS_None, // CONVERGENCECTRL_ENTRY = 46
3100 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 47
3101 CEFBS_None, // CONVERGENCECTRL_LOOP = 48
3102 CEFBS_None, // CONVERGENCECTRL_GLUE = 49
3103 CEFBS_None, // G_ASSERT_SEXT = 50
3104 CEFBS_None, // G_ASSERT_ZEXT = 51
3105 CEFBS_None, // G_ASSERT_ALIGN = 52
3106 CEFBS_None, // G_ADD = 53
3107 CEFBS_None, // G_SUB = 54
3108 CEFBS_None, // G_MUL = 55
3109 CEFBS_None, // G_SDIV = 56
3110 CEFBS_None, // G_UDIV = 57
3111 CEFBS_None, // G_SREM = 58
3112 CEFBS_None, // G_UREM = 59
3113 CEFBS_None, // G_SDIVREM = 60
3114 CEFBS_None, // G_UDIVREM = 61
3115 CEFBS_None, // G_AND = 62
3116 CEFBS_None, // G_OR = 63
3117 CEFBS_None, // G_XOR = 64
3118 CEFBS_None, // G_ABDS = 65
3119 CEFBS_None, // G_ABDU = 66
3120 CEFBS_None, // G_IMPLICIT_DEF = 67
3121 CEFBS_None, // G_PHI = 68
3122 CEFBS_None, // G_FRAME_INDEX = 69
3123 CEFBS_None, // G_GLOBAL_VALUE = 70
3124 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 71
3125 CEFBS_None, // G_CONSTANT_POOL = 72
3126 CEFBS_None, // G_EXTRACT = 73
3127 CEFBS_None, // G_UNMERGE_VALUES = 74
3128 CEFBS_None, // G_INSERT = 75
3129 CEFBS_None, // G_MERGE_VALUES = 76
3130 CEFBS_None, // G_BUILD_VECTOR = 77
3131 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 78
3132 CEFBS_None, // G_CONCAT_VECTORS = 79
3133 CEFBS_None, // G_PTRTOINT = 80
3134 CEFBS_None, // G_INTTOPTR = 81
3135 CEFBS_None, // G_BITCAST = 82
3136 CEFBS_None, // G_FREEZE = 83
3137 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 84
3138 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 85
3139 CEFBS_None, // G_INTRINSIC_TRUNC = 86
3140 CEFBS_None, // G_INTRINSIC_ROUND = 87
3141 CEFBS_None, // G_INTRINSIC_LRINT = 88
3142 CEFBS_None, // G_INTRINSIC_LLRINT = 89
3143 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 90
3144 CEFBS_None, // G_READCYCLECOUNTER = 91
3145 CEFBS_None, // G_READSTEADYCOUNTER = 92
3146 CEFBS_None, // G_LOAD = 93
3147 CEFBS_None, // G_SEXTLOAD = 94
3148 CEFBS_None, // G_ZEXTLOAD = 95
3149 CEFBS_None, // G_INDEXED_LOAD = 96
3150 CEFBS_None, // G_INDEXED_SEXTLOAD = 97
3151 CEFBS_None, // G_INDEXED_ZEXTLOAD = 98
3152 CEFBS_None, // G_STORE = 99
3153 CEFBS_None, // G_INDEXED_STORE = 100
3154 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 101
3155 CEFBS_None, // G_ATOMIC_CMPXCHG = 102
3156 CEFBS_None, // G_ATOMICRMW_XCHG = 103
3157 CEFBS_None, // G_ATOMICRMW_ADD = 104
3158 CEFBS_None, // G_ATOMICRMW_SUB = 105
3159 CEFBS_None, // G_ATOMICRMW_AND = 106
3160 CEFBS_None, // G_ATOMICRMW_NAND = 107
3161 CEFBS_None, // G_ATOMICRMW_OR = 108
3162 CEFBS_None, // G_ATOMICRMW_XOR = 109
3163 CEFBS_None, // G_ATOMICRMW_MAX = 110
3164 CEFBS_None, // G_ATOMICRMW_MIN = 111
3165 CEFBS_None, // G_ATOMICRMW_UMAX = 112
3166 CEFBS_None, // G_ATOMICRMW_UMIN = 113
3167 CEFBS_None, // G_ATOMICRMW_FADD = 114
3168 CEFBS_None, // G_ATOMICRMW_FSUB = 115
3169 CEFBS_None, // G_ATOMICRMW_FMAX = 116
3170 CEFBS_None, // G_ATOMICRMW_FMIN = 117
3171 CEFBS_None, // G_ATOMICRMW_FMAXIMUM = 118
3172 CEFBS_None, // G_ATOMICRMW_FMINIMUM = 119
3173 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 120
3174 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 121
3175 CEFBS_None, // G_ATOMICRMW_USUB_COND = 122
3176 CEFBS_None, // G_ATOMICRMW_USUB_SAT = 123
3177 CEFBS_None, // G_FENCE = 124
3178 CEFBS_None, // G_PREFETCH = 125
3179 CEFBS_None, // G_BRCOND = 126
3180 CEFBS_None, // G_BRINDIRECT = 127
3181 CEFBS_None, // G_INVOKE_REGION_START = 128
3182 CEFBS_None, // G_INTRINSIC = 129
3183 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 130
3184 CEFBS_None, // G_INTRINSIC_CONVERGENT = 131
3185 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 132
3186 CEFBS_None, // G_ANYEXT = 133
3187 CEFBS_None, // G_TRUNC = 134
3188 CEFBS_None, // G_CONSTANT = 135
3189 CEFBS_None, // G_FCONSTANT = 136
3190 CEFBS_None, // G_VASTART = 137
3191 CEFBS_None, // G_VAARG = 138
3192 CEFBS_None, // G_SEXT = 139
3193 CEFBS_None, // G_SEXT_INREG = 140
3194 CEFBS_None, // G_ZEXT = 141
3195 CEFBS_None, // G_SHL = 142
3196 CEFBS_None, // G_LSHR = 143
3197 CEFBS_None, // G_ASHR = 144
3198 CEFBS_None, // G_FSHL = 145
3199 CEFBS_None, // G_FSHR = 146
3200 CEFBS_None, // G_ROTR = 147
3201 CEFBS_None, // G_ROTL = 148
3202 CEFBS_None, // G_ICMP = 149
3203 CEFBS_None, // G_FCMP = 150
3204 CEFBS_None, // G_SCMP = 151
3205 CEFBS_None, // G_UCMP = 152
3206 CEFBS_None, // G_SELECT = 153
3207 CEFBS_None, // G_UADDO = 154
3208 CEFBS_None, // G_UADDE = 155
3209 CEFBS_None, // G_USUBO = 156
3210 CEFBS_None, // G_USUBE = 157
3211 CEFBS_None, // G_SADDO = 158
3212 CEFBS_None, // G_SADDE = 159
3213 CEFBS_None, // G_SSUBO = 160
3214 CEFBS_None, // G_SSUBE = 161
3215 CEFBS_None, // G_UMULO = 162
3216 CEFBS_None, // G_SMULO = 163
3217 CEFBS_None, // G_UMULH = 164
3218 CEFBS_None, // G_SMULH = 165
3219 CEFBS_None, // G_UADDSAT = 166
3220 CEFBS_None, // G_SADDSAT = 167
3221 CEFBS_None, // G_USUBSAT = 168
3222 CEFBS_None, // G_SSUBSAT = 169
3223 CEFBS_None, // G_USHLSAT = 170
3224 CEFBS_None, // G_SSHLSAT = 171
3225 CEFBS_None, // G_SMULFIX = 172
3226 CEFBS_None, // G_UMULFIX = 173
3227 CEFBS_None, // G_SMULFIXSAT = 174
3228 CEFBS_None, // G_UMULFIXSAT = 175
3229 CEFBS_None, // G_SDIVFIX = 176
3230 CEFBS_None, // G_UDIVFIX = 177
3231 CEFBS_None, // G_SDIVFIXSAT = 178
3232 CEFBS_None, // G_UDIVFIXSAT = 179
3233 CEFBS_None, // G_FADD = 180
3234 CEFBS_None, // G_FSUB = 181
3235 CEFBS_None, // G_FMUL = 182
3236 CEFBS_None, // G_FMA = 183
3237 CEFBS_None, // G_FMAD = 184
3238 CEFBS_None, // G_FDIV = 185
3239 CEFBS_None, // G_FREM = 186
3240 CEFBS_None, // G_FPOW = 187
3241 CEFBS_None, // G_FPOWI = 188
3242 CEFBS_None, // G_FEXP = 189
3243 CEFBS_None, // G_FEXP2 = 190
3244 CEFBS_None, // G_FEXP10 = 191
3245 CEFBS_None, // G_FLOG = 192
3246 CEFBS_None, // G_FLOG2 = 193
3247 CEFBS_None, // G_FLOG10 = 194
3248 CEFBS_None, // G_FLDEXP = 195
3249 CEFBS_None, // G_FFREXP = 196
3250 CEFBS_None, // G_FNEG = 197
3251 CEFBS_None, // G_FPEXT = 198
3252 CEFBS_None, // G_FPTRUNC = 199
3253 CEFBS_None, // G_FPTOSI = 200
3254 CEFBS_None, // G_FPTOUI = 201
3255 CEFBS_None, // G_SITOFP = 202
3256 CEFBS_None, // G_UITOFP = 203
3257 CEFBS_None, // G_FPTOSI_SAT = 204
3258 CEFBS_None, // G_FPTOUI_SAT = 205
3259 CEFBS_None, // G_FABS = 206
3260 CEFBS_None, // G_FCOPYSIGN = 207
3261 CEFBS_None, // G_IS_FPCLASS = 208
3262 CEFBS_None, // G_FCANONICALIZE = 209
3263 CEFBS_None, // G_FMINNUM = 210
3264 CEFBS_None, // G_FMAXNUM = 211
3265 CEFBS_None, // G_FMINNUM_IEEE = 212
3266 CEFBS_None, // G_FMAXNUM_IEEE = 213
3267 CEFBS_None, // G_FMINIMUM = 214
3268 CEFBS_None, // G_FMAXIMUM = 215
3269 CEFBS_None, // G_FMINIMUMNUM = 216
3270 CEFBS_None, // G_FMAXIMUMNUM = 217
3271 CEFBS_None, // G_GET_FPENV = 218
3272 CEFBS_None, // G_SET_FPENV = 219
3273 CEFBS_None, // G_RESET_FPENV = 220
3274 CEFBS_None, // G_GET_FPMODE = 221
3275 CEFBS_None, // G_SET_FPMODE = 222
3276 CEFBS_None, // G_RESET_FPMODE = 223
3277 CEFBS_None, // G_PTR_ADD = 224
3278 CEFBS_None, // G_PTRMASK = 225
3279 CEFBS_None, // G_SMIN = 226
3280 CEFBS_None, // G_SMAX = 227
3281 CEFBS_None, // G_UMIN = 228
3282 CEFBS_None, // G_UMAX = 229
3283 CEFBS_None, // G_ABS = 230
3284 CEFBS_None, // G_LROUND = 231
3285 CEFBS_None, // G_LLROUND = 232
3286 CEFBS_None, // G_BR = 233
3287 CEFBS_None, // G_BRJT = 234
3288 CEFBS_None, // G_VSCALE = 235
3289 CEFBS_None, // G_INSERT_SUBVECTOR = 236
3290 CEFBS_None, // G_EXTRACT_SUBVECTOR = 237
3291 CEFBS_None, // G_INSERT_VECTOR_ELT = 238
3292 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 239
3293 CEFBS_None, // G_SHUFFLE_VECTOR = 240
3294 CEFBS_None, // G_SPLAT_VECTOR = 241
3295 CEFBS_None, // G_STEP_VECTOR = 242
3296 CEFBS_None, // G_VECTOR_COMPRESS = 243
3297 CEFBS_None, // G_CTTZ = 244
3298 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 245
3299 CEFBS_None, // G_CTLZ = 246
3300 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 247
3301 CEFBS_None, // G_CTPOP = 248
3302 CEFBS_None, // G_BSWAP = 249
3303 CEFBS_None, // G_BITREVERSE = 250
3304 CEFBS_None, // G_FCEIL = 251
3305 CEFBS_None, // G_FCOS = 252
3306 CEFBS_None, // G_FSIN = 253
3307 CEFBS_None, // G_FSINCOS = 254
3308 CEFBS_None, // G_FTAN = 255
3309 CEFBS_None, // G_FACOS = 256
3310 CEFBS_None, // G_FASIN = 257
3311 CEFBS_None, // G_FATAN = 258
3312 CEFBS_None, // G_FATAN2 = 259
3313 CEFBS_None, // G_FCOSH = 260
3314 CEFBS_None, // G_FSINH = 261
3315 CEFBS_None, // G_FTANH = 262
3316 CEFBS_None, // G_FSQRT = 263
3317 CEFBS_None, // G_FFLOOR = 264
3318 CEFBS_None, // G_FRINT = 265
3319 CEFBS_None, // G_FNEARBYINT = 266
3320 CEFBS_None, // G_ADDRSPACE_CAST = 267
3321 CEFBS_None, // G_BLOCK_ADDR = 268
3322 CEFBS_None, // G_JUMP_TABLE = 269
3323 CEFBS_None, // G_DYN_STACKALLOC = 270
3324 CEFBS_None, // G_STACKSAVE = 271
3325 CEFBS_None, // G_STACKRESTORE = 272
3326 CEFBS_None, // G_STRICT_FADD = 273
3327 CEFBS_None, // G_STRICT_FSUB = 274
3328 CEFBS_None, // G_STRICT_FMUL = 275
3329 CEFBS_None, // G_STRICT_FDIV = 276
3330 CEFBS_None, // G_STRICT_FREM = 277
3331 CEFBS_None, // G_STRICT_FMA = 278
3332 CEFBS_None, // G_STRICT_FSQRT = 279
3333 CEFBS_None, // G_STRICT_FLDEXP = 280
3334 CEFBS_None, // G_READ_REGISTER = 281
3335 CEFBS_None, // G_WRITE_REGISTER = 282
3336 CEFBS_None, // G_MEMCPY = 283
3337 CEFBS_None, // G_MEMCPY_INLINE = 284
3338 CEFBS_None, // G_MEMMOVE = 285
3339 CEFBS_None, // G_MEMSET = 286
3340 CEFBS_None, // G_BZERO = 287
3341 CEFBS_None, // G_TRAP = 288
3342 CEFBS_None, // G_DEBUGTRAP = 289
3343 CEFBS_None, // G_UBSANTRAP = 290
3344 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 291
3345 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 292
3346 CEFBS_None, // G_VECREDUCE_FADD = 293
3347 CEFBS_None, // G_VECREDUCE_FMUL = 294
3348 CEFBS_None, // G_VECREDUCE_FMAX = 295
3349 CEFBS_None, // G_VECREDUCE_FMIN = 296
3350 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 297
3351 CEFBS_None, // G_VECREDUCE_FMINIMUM = 298
3352 CEFBS_None, // G_VECREDUCE_ADD = 299
3353 CEFBS_None, // G_VECREDUCE_MUL = 300
3354 CEFBS_None, // G_VECREDUCE_AND = 301
3355 CEFBS_None, // G_VECREDUCE_OR = 302
3356 CEFBS_None, // G_VECREDUCE_XOR = 303
3357 CEFBS_None, // G_VECREDUCE_SMAX = 304
3358 CEFBS_None, // G_VECREDUCE_SMIN = 305
3359 CEFBS_None, // G_VECREDUCE_UMAX = 306
3360 CEFBS_None, // G_VECREDUCE_UMIN = 307
3361 CEFBS_None, // G_SBFX = 308
3362 CEFBS_None, // G_UBFX = 309
3363 CEFBS_None, // ADJCALLSTACKDOWN = 310
3364 CEFBS_None, // ADJCALLSTACKUP = 311
3365 CEFBS_None, // GETPCX = 312
3366 CEFBS_None, // SELECT_CC_DFP_FCC = 313
3367 CEFBS_None, // SELECT_CC_DFP_ICC = 314
3368 CEFBS_None, // SELECT_CC_DFP_XCC = 315
3369 CEFBS_None, // SELECT_CC_FP_FCC = 316
3370 CEFBS_None, // SELECT_CC_FP_ICC = 317
3371 CEFBS_None, // SELECT_CC_FP_XCC = 318
3372 CEFBS_None, // SELECT_CC_Int_FCC = 319
3373 CEFBS_None, // SELECT_CC_Int_ICC = 320
3374 CEFBS_None, // SELECT_CC_Int_XCC = 321
3375 CEFBS_None, // SELECT_CC_QFP_FCC = 322
3376 CEFBS_None, // SELECT_CC_QFP_ICC = 323
3377 CEFBS_None, // SELECT_CC_QFP_XCC = 324
3378 CEFBS_None, // SET = 325
3379 CEFBS_HasV9, // SETSW = 326
3380 CEFBS_Is64Bit_HasV9, // SETX = 327
3381 CEFBS_None, // ADDCCri = 328
3382 CEFBS_None, // ADDCCrr = 329
3383 CEFBS_None, // ADDCri = 330
3384 CEFBS_None, // ADDCrr = 331
3385 CEFBS_None, // ADDEri = 332
3386 CEFBS_None, // ADDErr = 333
3387 CEFBS_HasVIS3, // ADDXC = 334
3388 CEFBS_HasVIS3, // ADDXCCC = 335
3389 CEFBS_None, // ADDri = 336
3390 CEFBS_None, // ADDrr = 337
3391 CEFBS_HasVIS, // ALIGNADDR = 338
3392 CEFBS_HasVIS, // ALIGNADDRL = 339
3393 CEFBS_HasUA2005, // ALLCLEAN = 340
3394 CEFBS_None, // ANDCCri = 341
3395 CEFBS_None, // ANDCCrr = 342
3396 CEFBS_None, // ANDNCCri = 343
3397 CEFBS_None, // ANDNCCrr = 344
3398 CEFBS_None, // ANDNri = 345
3399 CEFBS_None, // ANDNrr = 346
3400 CEFBS_None, // ANDri = 347
3401 CEFBS_None, // ANDrr = 348
3402 CEFBS_HasVIS, // ARRAY16 = 349
3403 CEFBS_HasVIS, // ARRAY32 = 350
3404 CEFBS_HasVIS, // ARRAY8 = 351
3405 CEFBS_None, // BA = 352
3406 CEFBS_None, // BCOND = 353
3407 CEFBS_None, // BCONDA = 354
3408 CEFBS_None, // BINDri = 355
3409 CEFBS_None, // BINDrr = 356
3410 CEFBS_HasVIS2, // BMASK = 357
3411 CEFBS_HasV9, // BPFCC = 358
3412 CEFBS_HasV9, // BPFCCA = 359
3413 CEFBS_HasV9, // BPFCCANT = 360
3414 CEFBS_HasV9, // BPFCCNT = 361
3415 CEFBS_HasV9, // BPICC = 362
3416 CEFBS_HasV9, // BPICCA = 363
3417 CEFBS_HasV9, // BPICCANT = 364
3418 CEFBS_HasV9, // BPICCNT = 365
3419 CEFBS_Is64Bit, // BPR = 366
3420 CEFBS_Is64Bit, // BPRA = 367
3421 CEFBS_Is64Bit, // BPRANT = 368
3422 CEFBS_Is64Bit, // BPRNT = 369
3423 CEFBS_Is64Bit, // BPXCC = 370
3424 CEFBS_Is64Bit, // BPXCCA = 371
3425 CEFBS_Is64Bit, // BPXCCANT = 372
3426 CEFBS_Is64Bit, // BPXCCNT = 373
3427 CEFBS_HasVIS2, // BSHUFFLE = 374
3428 CEFBS_None, // CALL = 375
3429 CEFBS_None, // CALLi = 376
3430 CEFBS_None, // CALLri = 377
3431 CEFBS_None, // CALLrii = 378
3432 CEFBS_None, // CALLrr = 379
3433 CEFBS_None, // CALLrri = 380
3434 CEFBS_HasV9, // CASAri = 381
3435 CEFBS_HasCASA, // CASArr = 382
3436 CEFBS_Is64Bit_HasV9, // CASXAri = 383
3437 CEFBS_Is64Bit_HasV9, // CASXArr = 384
3438 CEFBS_HasVIS3, // CMASK16 = 385
3439 CEFBS_HasVIS3, // CMASK32 = 386
3440 CEFBS_HasVIS3, // CMASK8 = 387
3441 CEFBS_None, // CPBCOND = 388
3442 CEFBS_None, // CPBCONDA = 389
3443 CEFBS_HasOSA2011, // CWBCONDri = 390
3444 CEFBS_HasOSA2011, // CWBCONDrr = 391
3445 CEFBS_HasOSA2011, // CXBCONDri = 392
3446 CEFBS_HasOSA2011, // CXBCONDrr = 393
3447 CEFBS_HasV9, // DONE = 394
3448 CEFBS_HasVIS, // EDGE16 = 395
3449 CEFBS_HasVIS, // EDGE16L = 396
3450 CEFBS_HasVIS2, // EDGE16LN = 397
3451 CEFBS_HasVIS2, // EDGE16N = 398
3452 CEFBS_HasVIS, // EDGE32 = 399
3453 CEFBS_HasVIS, // EDGE32L = 400
3454 CEFBS_HasVIS2, // EDGE32LN = 401
3455 CEFBS_HasVIS2, // EDGE32N = 402
3456 CEFBS_HasVIS, // EDGE8 = 403
3457 CEFBS_HasVIS, // EDGE8L = 404
3458 CEFBS_HasVIS2, // EDGE8LN = 405
3459 CEFBS_HasVIS2, // EDGE8N = 406
3460 CEFBS_HasV9, // FABSD = 407
3461 CEFBS_HasV9, // FABSQ = 408
3462 CEFBS_None, // FABSS = 409
3463 CEFBS_None, // FADDD = 410
3464 CEFBS_None, // FADDQ = 411
3465 CEFBS_None, // FADDS = 412
3466 CEFBS_HasVIS, // FALIGNADATA = 413
3467 CEFBS_HasVIS, // FAND = 414
3468 CEFBS_HasVIS, // FANDNOT1 = 415
3469 CEFBS_HasVIS, // FANDNOT1S = 416
3470 CEFBS_HasVIS, // FANDNOT2 = 417
3471 CEFBS_HasVIS, // FANDNOT2S = 418
3472 CEFBS_HasVIS, // FANDS = 419
3473 CEFBS_None, // FBCOND = 420
3474 CEFBS_None, // FBCONDA = 421
3475 CEFBS_HasV9, // FBCONDA_V9 = 422
3476 CEFBS_HasV9, // FBCOND_V9 = 423
3477 CEFBS_HasVIS3, // FCHKSM16 = 424
3478 CEFBS_None, // FCMPD = 425
3479 CEFBS_HasV9, // FCMPD_V9 = 426
3480 CEFBS_HasVIS, // FCMPEQ16 = 427
3481 CEFBS_HasVIS, // FCMPEQ32 = 428
3482 CEFBS_HasVIS, // FCMPGT16 = 429
3483 CEFBS_HasVIS, // FCMPGT32 = 430
3484 CEFBS_HasVIS, // FCMPLE16 = 431
3485 CEFBS_HasVIS, // FCMPLE32 = 432
3486 CEFBS_HasVIS, // FCMPNE16 = 433
3487 CEFBS_HasVIS, // FCMPNE32 = 434
3488 CEFBS_None, // FCMPQ = 435
3489 CEFBS_HasV9, // FCMPQ_V9 = 436
3490 CEFBS_None, // FCMPS = 437
3491 CEFBS_HasV9, // FCMPS_V9 = 438
3492 CEFBS_None, // FDIVD = 439
3493 CEFBS_None, // FDIVQ = 440
3494 CEFBS_None, // FDIVS = 441
3495 CEFBS_None, // FDMULQ = 442
3496 CEFBS_None, // FDTOI = 443
3497 CEFBS_None, // FDTOQ = 444
3498 CEFBS_None, // FDTOS = 445
3499 CEFBS_Is64Bit, // FDTOX = 446
3500 CEFBS_HasVIS, // FEXPAND = 447
3501 CEFBS_HasVIS3, // FHADDD = 448
3502 CEFBS_HasVIS3, // FHADDS = 449
3503 CEFBS_HasVIS3, // FHSUBD = 450
3504 CEFBS_HasVIS3, // FHSUBS = 451
3505 CEFBS_None, // FITOD = 452
3506 CEFBS_None, // FITOQ = 453
3507 CEFBS_None, // FITOS = 454
3508 CEFBS_HasVIS3, // FLCMPD = 455
3509 CEFBS_HasVIS3, // FLCMPS = 456
3510 CEFBS_None, // FLUSH = 457
3511 CEFBS_HasV9, // FLUSHW = 458
3512 CEFBS_None, // FLUSHri = 459
3513 CEFBS_None, // FLUSHrr = 460
3514 CEFBS_HasUA2007, // FMADDD = 461
3515 CEFBS_HasUA2007, // FMADDS = 462
3516 CEFBS_HasVIS3, // FMEAN16 = 463
3517 CEFBS_HasV9, // FMOVD = 464
3518 CEFBS_HasV9, // FMOVD_FCC = 465
3519 CEFBS_HasV9, // FMOVD_ICC = 466
3520 CEFBS_Is64Bit, // FMOVD_XCC = 467
3521 CEFBS_HasV9, // FMOVQ = 468
3522 CEFBS_HasV9, // FMOVQ_FCC = 469
3523 CEFBS_HasV9, // FMOVQ_ICC = 470
3524 CEFBS_Is64Bit, // FMOVQ_XCC = 471
3525 CEFBS_Is64Bit, // FMOVRD = 472
3526 CEFBS_None, // FMOVRQ = 473
3527 CEFBS_Is64Bit, // FMOVRS = 474
3528 CEFBS_None, // FMOVS = 475
3529 CEFBS_HasV9, // FMOVS_FCC = 476
3530 CEFBS_HasV9, // FMOVS_ICC = 477
3531 CEFBS_Is64Bit, // FMOVS_XCC = 478
3532 CEFBS_HasUA2007, // FMSUBD = 479
3533 CEFBS_HasUA2007, // FMSUBS = 480
3534 CEFBS_HasVIS, // FMUL8SUX16 = 481
3535 CEFBS_HasVIS, // FMUL8ULX16 = 482
3536 CEFBS_HasVIS, // FMUL8X16 = 483
3537 CEFBS_HasVIS, // FMUL8X16AL = 484
3538 CEFBS_HasVIS, // FMUL8X16AU = 485
3539 CEFBS_None, // FMULD = 486
3540 CEFBS_HasVIS, // FMULD8SUX16 = 487
3541 CEFBS_HasVIS, // FMULD8ULX16 = 488
3542 CEFBS_None, // FMULQ = 489
3543 CEFBS_None, // FMULS = 490
3544 CEFBS_HasVIS3, // FNADDD = 491
3545 CEFBS_HasVIS3, // FNADDS = 492
3546 CEFBS_HasVIS, // FNAND = 493
3547 CEFBS_HasVIS, // FNANDS = 494
3548 CEFBS_HasV9, // FNEGD = 495
3549 CEFBS_HasV9, // FNEGQ = 496
3550 CEFBS_None, // FNEGS = 497
3551 CEFBS_HasVIS3, // FNHADDD = 498
3552 CEFBS_HasVIS3, // FNHADDS = 499
3553 CEFBS_HasUA2007, // FNMADDD = 500
3554 CEFBS_HasUA2007, // FNMADDS = 501
3555 CEFBS_HasUA2007, // FNMSUBD = 502
3556 CEFBS_HasUA2007, // FNMSUBS = 503
3557 CEFBS_HasVIS3, // FNMULD = 504
3558 CEFBS_HasVIS3, // FNMULS = 505
3559 CEFBS_HasVIS, // FNOR = 506
3560 CEFBS_HasVIS, // FNORS = 507
3561 CEFBS_HasVIS, // FNOT1 = 508
3562 CEFBS_HasVIS, // FNOT1S = 509
3563 CEFBS_HasVIS, // FNOT2 = 510
3564 CEFBS_HasVIS, // FNOT2S = 511
3565 CEFBS_HasVIS3, // FNSMULD = 512
3566 CEFBS_HasVIS, // FONE = 513
3567 CEFBS_HasVIS, // FONES = 514
3568 CEFBS_HasVIS, // FOR = 515
3569 CEFBS_HasVIS, // FORNOT1 = 516
3570 CEFBS_HasVIS, // FORNOT1S = 517
3571 CEFBS_HasVIS, // FORNOT2 = 518
3572 CEFBS_HasVIS, // FORNOT2S = 519
3573 CEFBS_HasVIS, // FORS = 520
3574 CEFBS_HasVIS, // FPACK16 = 521
3575 CEFBS_HasVIS, // FPACK32 = 522
3576 CEFBS_HasVIS, // FPACKFIX = 523
3577 CEFBS_HasVIS, // FPADD16 = 524
3578 CEFBS_HasVIS, // FPADD16S = 525
3579 CEFBS_HasVIS, // FPADD32 = 526
3580 CEFBS_HasVIS, // FPADD32S = 527
3581 CEFBS_HasVIS3, // FPADD64 = 528
3582 CEFBS_HasOSA2011, // FPMADDX = 529
3583 CEFBS_HasOSA2011, // FPMADDXHI = 530
3584 CEFBS_HasVIS, // FPMERGE = 531
3585 CEFBS_HasVIS, // FPSUB16 = 532
3586 CEFBS_HasVIS, // FPSUB16S = 533
3587 CEFBS_HasVIS, // FPSUB32 = 534
3588 CEFBS_HasVIS, // FPSUB32S = 535
3589 CEFBS_None, // FQTOD = 536
3590 CEFBS_None, // FQTOI = 537
3591 CEFBS_None, // FQTOS = 538
3592 CEFBS_Is64Bit, // FQTOX = 539
3593 CEFBS_HasVIS3, // FSLAS16 = 540
3594 CEFBS_HasVIS3, // FSLAS32 = 541
3595 CEFBS_HasVIS3, // FSLL16 = 542
3596 CEFBS_HasVIS3, // FSLL32 = 543
3597 CEFBS_None, // FSMULD = 544
3598 CEFBS_None, // FSQRTD = 545
3599 CEFBS_None, // FSQRTQ = 546
3600 CEFBS_None, // FSQRTS = 547
3601 CEFBS_HasVIS3, // FSRA16 = 548
3602 CEFBS_HasVIS3, // FSRA32 = 549
3603 CEFBS_HasVIS, // FSRC1 = 550
3604 CEFBS_HasVIS, // FSRC1S = 551
3605 CEFBS_HasVIS, // FSRC2 = 552
3606 CEFBS_HasVIS, // FSRC2S = 553
3607 CEFBS_HasVIS3, // FSRL16 = 554
3608 CEFBS_HasVIS3, // FSRL32 = 555
3609 CEFBS_None, // FSTOD = 556
3610 CEFBS_None, // FSTOI = 557
3611 CEFBS_None, // FSTOQ = 558
3612 CEFBS_Is64Bit, // FSTOX = 559
3613 CEFBS_None, // FSUBD = 560
3614 CEFBS_None, // FSUBQ = 561
3615 CEFBS_None, // FSUBS = 562
3616 CEFBS_HasVIS, // FXNOR = 563
3617 CEFBS_HasVIS, // FXNORS = 564
3618 CEFBS_HasVIS, // FXOR = 565
3619 CEFBS_HasVIS, // FXORS = 566
3620 CEFBS_Is64Bit, // FXTOD = 567
3621 CEFBS_Is64Bit, // FXTOQ = 568
3622 CEFBS_Is64Bit, // FXTOS = 569
3623 CEFBS_HasVIS, // FZERO = 570
3624 CEFBS_HasVIS, // FZEROS = 571
3625 CEFBS_Is64Bit, // GDOP_LDXrr = 572
3626 CEFBS_None, // GDOP_LDrr = 573
3627 CEFBS_HasUA2005, // INVALW = 574
3628 CEFBS_None, // JMPLri = 575
3629 CEFBS_None, // JMPLrr = 576
3630 CEFBS_HasV9, // LDAri = 577
3631 CEFBS_None, // LDArr = 578
3632 CEFBS_None, // LDCSRri = 579
3633 CEFBS_None, // LDCSRrr = 580
3634 CEFBS_None, // LDCri = 581
3635 CEFBS_None, // LDCrr = 582
3636 CEFBS_HasV9, // LDDAri = 583
3637 CEFBS_None, // LDDArr = 584
3638 CEFBS_None, // LDDCri = 585
3639 CEFBS_None, // LDDCrr = 586
3640 CEFBS_HasV9, // LDDFAri = 587
3641 CEFBS_HasV9, // LDDFArr = 588
3642 CEFBS_None, // LDDFri = 589
3643 CEFBS_None, // LDDFrr = 590
3644 CEFBS_None, // LDDri = 591
3645 CEFBS_None, // LDDrr = 592
3646 CEFBS_HasV9, // LDFAri = 593
3647 CEFBS_HasV9, // LDFArr = 594
3648 CEFBS_None, // LDFSRri = 595
3649 CEFBS_None, // LDFSRrr = 596
3650 CEFBS_None, // LDFri = 597
3651 CEFBS_None, // LDFrr = 598
3652 CEFBS_HasV9, // LDQFAri = 599
3653 CEFBS_HasV9, // LDQFArr = 600
3654 CEFBS_HasV9, // LDQFri = 601
3655 CEFBS_HasV9, // LDQFrr = 602
3656 CEFBS_HasV9, // LDSBAri = 603
3657 CEFBS_None, // LDSBArr = 604
3658 CEFBS_None, // LDSBri = 605
3659 CEFBS_None, // LDSBrr = 606
3660 CEFBS_HasV9, // LDSHAri = 607
3661 CEFBS_None, // LDSHArr = 608
3662 CEFBS_None, // LDSHri = 609
3663 CEFBS_None, // LDSHrr = 610
3664 CEFBS_HasV9, // LDSTUBAri = 611
3665 CEFBS_None, // LDSTUBArr = 612
3666 CEFBS_None, // LDSTUBri = 613
3667 CEFBS_None, // LDSTUBrr = 614
3668 CEFBS_Is64Bit, // LDSWAri = 615
3669 CEFBS_Is64Bit, // LDSWArr = 616
3670 CEFBS_Is64Bit, // LDSWri = 617
3671 CEFBS_Is64Bit, // LDSWrr = 618
3672 CEFBS_HasV9, // LDUBAri = 619
3673 CEFBS_None, // LDUBArr = 620
3674 CEFBS_None, // LDUBri = 621
3675 CEFBS_None, // LDUBrr = 622
3676 CEFBS_HasV9, // LDUHAri = 623
3677 CEFBS_None, // LDUHArr = 624
3678 CEFBS_None, // LDUHri = 625
3679 CEFBS_None, // LDUHrr = 626
3680 CEFBS_Is64Bit, // LDXAri = 627
3681 CEFBS_Is64Bit, // LDXArr = 628
3682 CEFBS_HasV9, // LDXFSRri = 629
3683 CEFBS_HasV9, // LDXFSRrr = 630
3684 CEFBS_Is64Bit, // LDXri = 631
3685 CEFBS_Is64Bit, // LDXrr = 632
3686 CEFBS_None, // LDri = 633
3687 CEFBS_None, // LDrr = 634
3688 CEFBS_HasVIS3, // LZCNT = 635
3689 CEFBS_HasV9, // MEMBARi = 636
3690 CEFBS_HasVIS3, // MOVDTOX = 637
3691 CEFBS_HasV9, // MOVFCCri = 638
3692 CEFBS_HasV9, // MOVFCCrr = 639
3693 CEFBS_HasV9, // MOVICCri = 640
3694 CEFBS_HasV9, // MOVICCrr = 641
3695 CEFBS_Is64Bit, // MOVRri = 642
3696 CEFBS_Is64Bit, // MOVRrr = 643
3697 CEFBS_HasVIS3, // MOVSTOSW = 644
3698 CEFBS_HasVIS3, // MOVSTOUW = 645
3699 CEFBS_HasVIS3, // MOVWTOS = 646
3700 CEFBS_Is64Bit, // MOVXCCri = 647
3701 CEFBS_Is64Bit, // MOVXCCrr = 648
3702 CEFBS_HasVIS3, // MOVXTOD = 649
3703 CEFBS_None, // MULSCCri = 650
3704 CEFBS_None, // MULSCCrr = 651
3705 CEFBS_Is64Bit, // MULXri = 652
3706 CEFBS_Is64Bit, // MULXrr = 653
3707 CEFBS_None, // NOP = 654
3708 CEFBS_HasUA2005, // NORMALW = 655
3709 CEFBS_None, // ORCCri = 656
3710 CEFBS_None, // ORCCrr = 657
3711 CEFBS_None, // ORNCCri = 658
3712 CEFBS_None, // ORNCCrr = 659
3713 CEFBS_None, // ORNri = 660
3714 CEFBS_None, // ORNrr = 661
3715 CEFBS_None, // ORri = 662
3716 CEFBS_None, // ORrr = 663
3717 CEFBS_HasUA2005, // OTHERW = 664
3718 CEFBS_HasVIS, // PDIST = 665
3719 CEFBS_HasVIS3, // PDISTN = 666
3720 CEFBS_HasV9, // POPCrr = 667
3721 CEFBS_HasV9, // PREFETCHAi = 668
3722 CEFBS_HasV9, // PREFETCHAr = 669
3723 CEFBS_HasV9, // PREFETCHi = 670
3724 CEFBS_HasV9, // PREFETCHr = 671
3725 CEFBS_HasPWRPSR, // PWRPSRri = 672
3726 CEFBS_HasPWRPSR, // PWRPSRrr = 673
3727 CEFBS_None, // RDASR = 674
3728 CEFBS_HasV9, // RDFQ = 675
3729 CEFBS_HasV9, // RDPR = 676
3730 CEFBS_None, // RDPSR = 677
3731 CEFBS_None, // RDTBR = 678
3732 CEFBS_None, // RDWIM = 679
3733 CEFBS_HasV9, // RESTORED = 680
3734 CEFBS_None, // RESTOREri = 681
3735 CEFBS_None, // RESTORErr = 682
3736 CEFBS_None, // RET = 683
3737 CEFBS_None, // RETL = 684
3738 CEFBS_HasV9, // RETRY = 685
3739 CEFBS_None, // RETTri = 686
3740 CEFBS_None, // RETTrr = 687
3741 CEFBS_HasV9, // SAVED = 688
3742 CEFBS_None, // SAVEri = 689
3743 CEFBS_None, // SAVErr = 690
3744 CEFBS_None, // SDIVCCri = 691
3745 CEFBS_None, // SDIVCCrr = 692
3746 CEFBS_Is64Bit, // SDIVXri = 693
3747 CEFBS_Is64Bit, // SDIVXrr = 694
3748 CEFBS_None, // SDIVri = 695
3749 CEFBS_None, // SDIVrr = 696
3750 CEFBS_None, // SETHIi = 697
3751 CEFBS_HasVIS, // SHUTDOWN = 698
3752 CEFBS_HasVIS2, // SIAM = 699
3753 CEFBS_HasV9, // SIR = 700
3754 CEFBS_Is64Bit, // SLLXri = 701
3755 CEFBS_Is64Bit, // SLLXrr = 702
3756 CEFBS_None, // SLLri = 703
3757 CEFBS_None, // SLLrr = 704
3758 CEFBS_None, // SMACri = 705
3759 CEFBS_None, // SMACrr = 706
3760 CEFBS_None, // SMULCCri = 707
3761 CEFBS_None, // SMULCCrr = 708
3762 CEFBS_None, // SMULri = 709
3763 CEFBS_None, // SMULrr = 710
3764 CEFBS_Is64Bit, // SRAXri = 711
3765 CEFBS_Is64Bit, // SRAXrr = 712
3766 CEFBS_None, // SRAri = 713
3767 CEFBS_None, // SRArr = 714
3768 CEFBS_Is64Bit, // SRLXri = 715
3769 CEFBS_Is64Bit, // SRLXrr = 716
3770 CEFBS_None, // SRLri = 717
3771 CEFBS_None, // SRLrr = 718
3772 CEFBS_HasV9, // STAri = 719
3773 CEFBS_None, // STArr = 720
3774 CEFBS_None, // STBAR = 721
3775 CEFBS_HasV9, // STBAri = 722
3776 CEFBS_None, // STBArr = 723
3777 CEFBS_None, // STBri = 724
3778 CEFBS_None, // STBrr = 725
3779 CEFBS_None, // STCSRri = 726
3780 CEFBS_None, // STCSRrr = 727
3781 CEFBS_None, // STCri = 728
3782 CEFBS_None, // STCrr = 729
3783 CEFBS_HasV9, // STDAri = 730
3784 CEFBS_None, // STDArr = 731
3785 CEFBS_None, // STDCQri = 732
3786 CEFBS_None, // STDCQrr = 733
3787 CEFBS_None, // STDCri = 734
3788 CEFBS_None, // STDCrr = 735
3789 CEFBS_HasV9, // STDFAri = 736
3790 CEFBS_HasV9, // STDFArr = 737
3791 CEFBS_None, // STDFQri = 738
3792 CEFBS_None, // STDFQrr = 739
3793 CEFBS_None, // STDFri = 740
3794 CEFBS_None, // STDFrr = 741
3795 CEFBS_None, // STDri = 742
3796 CEFBS_None, // STDrr = 743
3797 CEFBS_HasV9, // STFAri = 744
3798 CEFBS_HasV9, // STFArr = 745
3799 CEFBS_None, // STFSRri = 746
3800 CEFBS_None, // STFSRrr = 747
3801 CEFBS_None, // STFri = 748
3802 CEFBS_None, // STFrr = 749
3803 CEFBS_HasV9, // STHAri = 750
3804 CEFBS_None, // STHArr = 751
3805 CEFBS_None, // STHri = 752
3806 CEFBS_None, // STHrr = 753
3807 CEFBS_HasV9, // STQFAri = 754
3808 CEFBS_HasV9, // STQFArr = 755
3809 CEFBS_HasV9, // STQFri = 756
3810 CEFBS_HasV9, // STQFrr = 757
3811 CEFBS_Is64Bit, // STXAri = 758
3812 CEFBS_Is64Bit, // STXArr = 759
3813 CEFBS_HasV9, // STXFSRri = 760
3814 CEFBS_HasV9, // STXFSRrr = 761
3815 CEFBS_Is64Bit, // STXri = 762
3816 CEFBS_Is64Bit, // STXrr = 763
3817 CEFBS_None, // STri = 764
3818 CEFBS_None, // STrr = 765
3819 CEFBS_None, // SUBCCri = 766
3820 CEFBS_None, // SUBCCrr = 767
3821 CEFBS_None, // SUBCri = 768
3822 CEFBS_None, // SUBCrr = 769
3823 CEFBS_None, // SUBEri = 770
3824 CEFBS_None, // SUBErr = 771
3825 CEFBS_None, // SUBri = 772
3826 CEFBS_None, // SUBrr = 773
3827 CEFBS_HasV9, // SWAPAri = 774
3828 CEFBS_None, // SWAPArr = 775
3829 CEFBS_None, // SWAPri = 776
3830 CEFBS_None, // SWAPrr = 777
3831 CEFBS_None, // TA1 = 778
3832 CEFBS_None, // TA3 = 779
3833 CEFBS_None, // TA5 = 780
3834 CEFBS_None, // TADDCCTVri = 781
3835 CEFBS_None, // TADDCCTVrr = 782
3836 CEFBS_None, // TADDCCri = 783
3837 CEFBS_None, // TADDCCrr = 784
3838 CEFBS_None, // TAIL_CALL = 785
3839 CEFBS_None, // TAIL_CALLri = 786
3840 CEFBS_HasV9, // TICCri = 787
3841 CEFBS_HasV9, // TICCrr = 788
3842 CEFBS_None, // TLS_ADDrr = 789
3843 CEFBS_None, // TLS_CALL = 790
3844 CEFBS_Is64Bit, // TLS_LDXrr = 791
3845 CEFBS_None, // TLS_LDrr = 792
3846 CEFBS_None, // TRAPri = 793
3847 CEFBS_None, // TRAPrr = 794
3848 CEFBS_None, // TSUBCCTVri = 795
3849 CEFBS_None, // TSUBCCTVrr = 796
3850 CEFBS_None, // TSUBCCri = 797
3851 CEFBS_None, // TSUBCCrr = 798
3852 CEFBS_Is64Bit, // TXCCri = 799
3853 CEFBS_Is64Bit, // TXCCrr = 800
3854 CEFBS_None, // UDIVCCri = 801
3855 CEFBS_None, // UDIVCCrr = 802
3856 CEFBS_Is64Bit, // UDIVXri = 803
3857 CEFBS_Is64Bit, // UDIVXrr = 804
3858 CEFBS_None, // UDIVri = 805
3859 CEFBS_None, // UDIVrr = 806
3860 CEFBS_None, // UMACri = 807
3861 CEFBS_None, // UMACrr = 808
3862 CEFBS_None, // UMULCCri = 809
3863 CEFBS_None, // UMULCCrr = 810
3864 CEFBS_HasVIS3, // UMULXHI = 811
3865 CEFBS_None, // UMULri = 812
3866 CEFBS_None, // UMULrr = 813
3867 CEFBS_None, // UNIMP = 814
3868 CEFBS_None, // V9FCMPD = 815
3869 CEFBS_None, // V9FCMPED = 816
3870 CEFBS_None, // V9FCMPEQ = 817
3871 CEFBS_None, // V9FCMPES = 818
3872 CEFBS_None, // V9FCMPQ = 819
3873 CEFBS_None, // V9FCMPS = 820
3874 CEFBS_HasV9, // V9FMOVD_FCC = 821
3875 CEFBS_HasV9, // V9FMOVQ_FCC = 822
3876 CEFBS_HasV9, // V9FMOVS_FCC = 823
3877 CEFBS_HasV9, // V9MOVFCCri = 824
3878 CEFBS_HasV9, // V9MOVFCCrr = 825
3879 CEFBS_None, // WRASRri = 826
3880 CEFBS_None, // WRASRrr = 827
3881 CEFBS_HasV9, // WRPRri = 828
3882 CEFBS_HasV9, // WRPRrr = 829
3883 CEFBS_None, // WRPSRri = 830
3884 CEFBS_None, // WRPSRrr = 831
3885 CEFBS_None, // WRTBRri = 832
3886 CEFBS_None, // WRTBRrr = 833
3887 CEFBS_None, // WRWIMri = 834
3888 CEFBS_None, // WRWIMrr = 835
3889 CEFBS_HasVIS3, // XMULX = 836
3890 CEFBS_HasVIS3, // XMULXHI = 837
3891 CEFBS_None, // XNORCCri = 838
3892 CEFBS_None, // XNORCCrr = 839
3893 CEFBS_None, // XNORri = 840
3894 CEFBS_None, // XNORrr = 841
3895 CEFBS_None, // XORCCri = 842
3896 CEFBS_None, // XORCCrr = 843
3897 CEFBS_None, // XORri = 844
3898 CEFBS_None, // XORrr = 845
3899 };
3900
3901 assert(Opcode < 846);
3902 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3903}
3904
3905} // end namespace llvm::Sparc_MC
3906#endif // GET_COMPUTE_FEATURES
3907
3908#ifdef GET_AVAILABLE_OPCODE_CHECKER
3909#undef GET_AVAILABLE_OPCODE_CHECKER
3910namespace llvm::Sparc_MC {
3911bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3912 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3913 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3914 FeatureBitset MissingFeatures =
3915 (AvailableFeatures & RequiredFeatures) ^
3916 RequiredFeatures;
3917 return !MissingFeatures.any();
3918}
3919} // end namespace llvm::Sparc_MC
3920#endif // GET_AVAILABLE_OPCODE_CHECKER
3921
3922#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3923#undef ENABLE_INSTR_PREDICATE_VERIFIER
3924#include <sstream>
3925
3926namespace llvm::Sparc_MC {
3927#ifndef NDEBUG
3928static const char *SubtargetFeatureNames[] = {
3929 "Feature_HasCASA",
3930 "Feature_HasOSA2011",
3931 "Feature_HasPWRPSR",
3932 "Feature_HasUA2005",
3933 "Feature_HasUA2007",
3934 "Feature_HasV9",
3935 "Feature_HasVIS",
3936 "Feature_HasVIS2",
3937 "Feature_HasVIS3",
3938 "Feature_Is64Bit",
3939 "Feature_UseSoftMulDiv",
3940 nullptr
3941};
3942
3943#endif // NDEBUG
3944
3945void verifyInstructionPredicates(
3946 unsigned Opcode, const FeatureBitset &Features) {
3947#ifndef NDEBUG
3948 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3949 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3950 FeatureBitset MissingFeatures =
3951 (AvailableFeatures & RequiredFeatures) ^
3952 RequiredFeatures;
3953 if (MissingFeatures.any()) {
3954 std::ostringstream Msg;
3955 Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]]
3956 << " instruction but the ";
3957 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3958 if (MissingFeatures.test(i))
3959 Msg << SubtargetFeatureNames[i] << " ";
3960 Msg << "predicate(s) are not met";
3961 report_fatal_error(Msg.str().c_str());
3962 }
3963#endif // NDEBUG
3964}
3965} // end namespace llvm::Sparc_MC
3966#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3967
3968