1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass SparcMCRegisterClasses[];
17
18namespace SP {
19enum : unsigned {
20 NoRegister,
21 CANRESTORE = 1,
22 CANSAVE = 2,
23 CLEANWIN = 3,
24 CPQ = 4,
25 CPSR = 5,
26 CWP = 6,
27 FQ = 7,
28 FSR = 8,
29 GL = 9,
30 ICC = 10,
31 OTHERWIN = 11,
32 PIL = 12,
33 PSR = 13,
34 PSTATE = 14,
35 TBA = 15,
36 TBR = 16,
37 TICK = 17,
38 TL = 18,
39 TNPC = 19,
40 TPC = 20,
41 TSTATE = 21,
42 TT = 22,
43 VER = 23,
44 WIM = 24,
45 WSTATE = 25,
46 Y = 26,
47 ASR1 = 27,
48 ASR2 = 28,
49 ASR3 = 29,
50 ASR4 = 30,
51 ASR5 = 31,
52 ASR6 = 32,
53 ASR7 = 33,
54 ASR8 = 34,
55 ASR9 = 35,
56 ASR10 = 36,
57 ASR11 = 37,
58 ASR12 = 38,
59 ASR13 = 39,
60 ASR14 = 40,
61 ASR15 = 41,
62 ASR16 = 42,
63 ASR17 = 43,
64 ASR18 = 44,
65 ASR19 = 45,
66 ASR20 = 46,
67 ASR21 = 47,
68 ASR22 = 48,
69 ASR23 = 49,
70 ASR24 = 50,
71 ASR25 = 51,
72 ASR26 = 52,
73 ASR27 = 53,
74 ASR28 = 54,
75 ASR29 = 55,
76 ASR30 = 56,
77 ASR31 = 57,
78 C0 = 58,
79 C1 = 59,
80 C2 = 60,
81 C3 = 61,
82 C4 = 62,
83 C5 = 63,
84 C6 = 64,
85 C7 = 65,
86 C8 = 66,
87 C9 = 67,
88 C10 = 68,
89 C11 = 69,
90 C12 = 70,
91 C13 = 71,
92 C14 = 72,
93 C15 = 73,
94 C16 = 74,
95 C17 = 75,
96 C18 = 76,
97 C19 = 77,
98 C20 = 78,
99 C21 = 79,
100 C22 = 80,
101 C23 = 81,
102 C24 = 82,
103 C25 = 83,
104 C26 = 84,
105 C27 = 85,
106 C28 = 86,
107 C29 = 87,
108 C30 = 88,
109 C31 = 89,
110 D0 = 90,
111 D1 = 91,
112 D2 = 92,
113 D3 = 93,
114 D4 = 94,
115 D5 = 95,
116 D6 = 96,
117 D7 = 97,
118 D8 = 98,
119 D9 = 99,
120 D10 = 100,
121 D11 = 101,
122 D12 = 102,
123 D13 = 103,
124 D14 = 104,
125 D15 = 105,
126 D16 = 106,
127 D17 = 107,
128 D18 = 108,
129 D19 = 109,
130 D20 = 110,
131 D21 = 111,
132 D22 = 112,
133 D23 = 113,
134 D24 = 114,
135 D25 = 115,
136 D26 = 116,
137 D27 = 117,
138 D28 = 118,
139 D29 = 119,
140 D30 = 120,
141 D31 = 121,
142 F0 = 122,
143 F1 = 123,
144 F2 = 124,
145 F3 = 125,
146 F4 = 126,
147 F5 = 127,
148 F6 = 128,
149 F7 = 129,
150 F8 = 130,
151 F9 = 131,
152 F10 = 132,
153 F11 = 133,
154 F12 = 134,
155 F13 = 135,
156 F14 = 136,
157 F15 = 137,
158 F16 = 138,
159 F17 = 139,
160 F18 = 140,
161 F19 = 141,
162 F20 = 142,
163 F21 = 143,
164 F22 = 144,
165 F23 = 145,
166 F24 = 146,
167 F25 = 147,
168 F26 = 148,
169 F27 = 149,
170 F28 = 150,
171 F29 = 151,
172 F30 = 152,
173 F31 = 153,
174 FCC0 = 154,
175 FCC1 = 155,
176 FCC2 = 156,
177 FCC3 = 157,
178 G0 = 158,
179 G1 = 159,
180 G2 = 160,
181 G3 = 161,
182 G4 = 162,
183 G5 = 163,
184 G6 = 164,
185 G7 = 165,
186 I0 = 166,
187 I1 = 167,
188 I2 = 168,
189 I3 = 169,
190 I4 = 170,
191 I5 = 171,
192 I6 = 172,
193 I7 = 173,
194 L0 = 174,
195 L1 = 175,
196 L2 = 176,
197 L3 = 177,
198 L4 = 178,
199 L5 = 179,
200 L6 = 180,
201 L7 = 181,
202 O0 = 182,
203 O1 = 183,
204 O2 = 184,
205 O3 = 185,
206 O4 = 186,
207 O5 = 187,
208 O6 = 188,
209 O7 = 189,
210 Q0 = 190,
211 Q1 = 191,
212 Q2 = 192,
213 Q3 = 193,
214 Q4 = 194,
215 Q5 = 195,
216 Q6 = 196,
217 Q7 = 197,
218 Q8 = 198,
219 Q9 = 199,
220 Q10 = 200,
221 Q11 = 201,
222 Q12 = 202,
223 Q13 = 203,
224 Q14 = 204,
225 Q15 = 205,
226 C0_C1 = 206,
227 C2_C3 = 207,
228 C4_C5 = 208,
229 C6_C7 = 209,
230 C8_C9 = 210,
231 C10_C11 = 211,
232 C12_C13 = 212,
233 C14_C15 = 213,
234 C16_C17 = 214,
235 C18_C19 = 215,
236 C20_C21 = 216,
237 C22_C23 = 217,
238 C24_C25 = 218,
239 C26_C27 = 219,
240 C28_C29 = 220,
241 C30_C31 = 221,
242 G0_G1 = 222,
243 G2_G3 = 223,
244 G4_G5 = 224,
245 G6_G7 = 225,
246 I0_I1 = 226,
247 I2_I3 = 227,
248 I4_I5 = 228,
249 I6_I7 = 229,
250 L0_L1 = 230,
251 L2_L3 = 231,
252 L4_L5 = 232,
253 L6_L7 = 233,
254 O0_O1 = 234,
255 O2_O3 = 235,
256 O4_O5 = 236,
257 O6_O7 = 237,
258 NUM_TARGET_REGS // 238
259};
260} // end namespace SP
261
262// Register classes
263
264namespace SP {
265enum {
266 FCCRegsRegClassID = 0,
267 ASRRegsRegClassID = 1,
268 CoprocRegsRegClassID = 2,
269 FPRegsRegClassID = 3,
270 IntRegsRegClassID = 4,
271 GPRIncomingArgRegClassID = 5,
272 GPROutgoingArgRegClassID = 6,
273 DFPRegsRegClassID = 7,
274 I64RegsRegClassID = 8,
275 PRRegsRegClassID = 9,
276 CoprocPairRegClassID = 10,
277 IntPairRegClassID = 11,
278 LowDFPRegsRegClassID = 12,
279 I64Regs_and_GPRIncomingArgRegClassID = 13,
280 I64Regs_and_GPROutgoingArgRegClassID = 14,
281 IntPair_with_sub_even_in_GPRIncomingArgRegClassID = 15,
282 IntPair_with_sub_even_in_GPROutgoingArgRegClassID = 16,
283 PRRegs_and_ASRRegsRegClassID = 17,
284 QFPRegsRegClassID = 18,
285 LowQFPRegsRegClassID = 19,
286
287};
288} // end namespace SP
289
290
291// Register alternate name indices
292
293namespace SP {
294enum {
295 NoRegAltName, // 0
296 RegNamesStateReg, // 1
297 NUM_TARGET_REG_ALT_NAMES = 2
298};
299} // end namespace SP
300
301
302// Subregister indices
303
304namespace SP {
305enum : uint16_t {
306 NoSubRegister,
307 sub_even, // 1
308 sub_even64, // 2
309 sub_odd, // 3
310 sub_odd64, // 4
311 sub_odd64_then_sub_even, // 5
312 sub_odd64_then_sub_odd, // 6
313 NUM_TARGET_SUBREGS
314};
315} // end namespace SP
316
317// Register pressure sets enum.
318namespace SP {
319enum RegisterPressureSets {
320 PRRegs_and_ASRRegs = 0,
321 FCCRegs = 1,
322 GPRIncomingArg = 2,
323 GPROutgoingArg = 3,
324 PRRegs = 4,
325 FPRegs = 5,
326 IntRegs = 6,
327 DFPRegs = 7,
328};
329} // end namespace SP
330
331} // end namespace llvm
332
333#endif // GET_REGINFO_ENUM
334
335/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
336|* *|
337|* MC Register Information *|
338|* *|
339|* Automatically generated file, do not edit! *|
340|* *|
341\*===----------------------------------------------------------------------===*/
342
343
344#ifdef GET_REGINFO_MC_DESC
345#undef GET_REGINFO_MC_DESC
346
347namespace llvm {
348
349extern const int16_t SparcRegDiffLists[] = {
350 /* 0 */ -148, 1, 0,
351 /* 3 */ -147, 1, 0,
352 /* 6 */ -146, 1, 0,
353 /* 9 */ -145, 1, 0,
354 /* 12 */ -144, 1, 0,
355 /* 15 */ -143, 1, 0,
356 /* 18 */ -142, 1, 0,
357 /* 21 */ -141, 1, 0,
358 /* 24 */ -140, 1, 0,
359 /* 27 */ -139, 1, 0,
360 /* 30 */ -138, 1, 0,
361 /* 33 */ -137, 1, 0,
362 /* 36 */ -136, 1, 0,
363 /* 39 */ -135, 1, 0,
364 /* 42 */ -134, 1, 0,
365 /* 45 */ -133, 1, 0,
366 /* 48 */ -92, 1, 0,
367 /* 51 */ -91, 1, 0,
368 /* 54 */ -90, 1, 0,
369 /* 57 */ -89, 1, 0,
370 /* 60 */ -88, 1, 0,
371 /* 63 */ -87, 1, 0,
372 /* 66 */ -86, 1, 0,
373 /* 69 */ -85, 1, 0,
374 /* 72 */ -64, 1, 0,
375 /* 75 */ -63, 1, 0,
376 /* 78 */ -62, 1, 0,
377 /* 81 */ -61, 1, 0,
378 /* 84 */ -60, 1, 0,
379 /* 87 */ -59, 1, 0,
380 /* 90 */ -58, 1, 0,
381 /* 93 */ -57, 1, 0,
382 /* 96 */ -56, 1, 0,
383 /* 99 */ -55, 1, 0,
384 /* 102 */ -54, 1, 0,
385 /* 105 */ -53, 1, 0,
386 /* 108 */ -52, 1, 0,
387 /* 111 */ -51, 1, 0,
388 /* 114 */ -50, 1, 0,
389 /* 117 */ -49, 1, 0,
390 /* 120 */ 1, 1, 1, 0,
391 /* 124 */ 32, 1, 0,
392 /* 127 */ -100, 32, 1, -32, 33, 1, 0,
393 /* 134 */ 34, 1, 0,
394 /* 137 */ -99, 34, 1, -34, 35, 1, 0,
395 /* 144 */ 36, 1, 0,
396 /* 147 */ -98, 36, 1, -36, 37, 1, 0,
397 /* 154 */ 38, 1, 0,
398 /* 157 */ -97, 38, 1, -38, 39, 1, 0,
399 /* 164 */ 40, 1, 0,
400 /* 167 */ -96, 40, 1, -40, 41, 1, 0,
401 /* 174 */ 42, 1, 0,
402 /* 177 */ -95, 42, 1, -42, 43, 1, 0,
403 /* 184 */ 44, 1, 0,
404 /* 187 */ -94, 44, 1, -44, 45, 1, 0,
405 /* 194 */ 46, 1, 0,
406 /* 197 */ -93, 46, 1, -46, 47, 1, 0,
407 /* 204 */ 48, 0,
408 /* 206 */ 49, 0,
409 /* 208 */ 50, 0,
410 /* 210 */ 51, 0,
411 /* 212 */ 52, 0,
412 /* 214 */ 53, 0,
413 /* 216 */ 54, 0,
414 /* 218 */ 55, 0,
415 /* 220 */ 56, 0,
416 /* 222 */ 57, 0,
417 /* 224 */ 58, 0,
418 /* 226 */ 59, 0,
419 /* 228 */ 60, 0,
420 /* 230 */ 61, 0,
421 /* 232 */ 62, 0,
422 /* 234 */ 63, 0,
423 /* 236 */ 64, 0,
424 /* 238 */ 84, 0,
425 /* 240 */ 85, 0,
426 /* 242 */ 86, 0,
427 /* 244 */ 87, 0,
428 /* 246 */ 88, 0,
429 /* 248 */ 89, 0,
430 /* 250 */ 90, 0,
431 /* 252 */ 91, 0,
432 /* 254 */ -48, 92, 0,
433 /* 257 */ -47, 92, 0,
434 /* 260 */ -47, 93, 0,
435 /* 263 */ -46, 93, 0,
436 /* 266 */ -45, 93, 0,
437 /* 269 */ -45, 94, 0,
438 /* 272 */ -44, 94, 0,
439 /* 275 */ -43, 94, 0,
440 /* 278 */ -43, 95, 0,
441 /* 281 */ -42, 95, 0,
442 /* 284 */ -41, 95, 0,
443 /* 287 */ -41, 96, 0,
444 /* 290 */ -40, 96, 0,
445 /* 293 */ -39, 96, 0,
446 /* 296 */ -39, 97, 0,
447 /* 299 */ -38, 97, 0,
448 /* 302 */ -37, 97, 0,
449 /* 305 */ -37, 98, 0,
450 /* 308 */ -36, 98, 0,
451 /* 311 */ -35, 98, 0,
452 /* 314 */ -35, 99, 0,
453 /* 317 */ -34, 99, 0,
454 /* 320 */ -33, 99, 0,
455 /* 323 */ -33, 100, 0,
456 /* 326 */ -32, 100, 0,
457 /* 329 */ 132, 0,
458 /* 331 */ 133, 0,
459 /* 333 */ 134, 0,
460 /* 335 */ 135, 0,
461 /* 337 */ 136, 0,
462 /* 339 */ 137, 0,
463 /* 341 */ 138, 0,
464 /* 343 */ 139, 0,
465 /* 345 */ 140, 0,
466 /* 347 */ 141, 0,
467 /* 349 */ 142, 0,
468 /* 351 */ 143, 0,
469 /* 353 */ 144, 0,
470 /* 355 */ 145, 0,
471 /* 357 */ 146, 0,
472 /* 359 */ 147, 0,
473 /* 361 */ 148, 0,
474};
475
476extern const LaneBitmask SparcLaneMaskLists[] = {
477 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002),
478 /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008),
479 /* 6 */ LaneBitmask(0x0000000000000003), LaneBitmask(0x000000000000000C),
480 /* 8 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
481};
482
483extern const uint16_t SparcSubRegIdxLists[] = {
484 /* 0 */ 1, 3,
485 /* 2 */ 2, 4,
486 /* 4 */ 2, 1, 3, 4, 5, 6,
487};
488
489
490#ifdef __GNUC__
491#pragma GCC diagnostic push
492#pragma GCC diagnostic ignored "-Woverlength-strings"
493#endif
494extern const char SparcRegStrings[] = {
495 /* 0 */ "C10\000"
496 /* 4 */ "D10\000"
497 /* 8 */ "F10\000"
498 /* 12 */ "Q10\000"
499 /* 16 */ "ASR10\000"
500 /* 22 */ "C20\000"
501 /* 26 */ "D20\000"
502 /* 30 */ "F20\000"
503 /* 34 */ "ASR20\000"
504 /* 40 */ "C30\000"
505 /* 44 */ "D30\000"
506 /* 48 */ "F30\000"
507 /* 52 */ "ASR30\000"
508 /* 58 */ "FCC0\000"
509 /* 63 */ "D0\000"
510 /* 66 */ "F0\000"
511 /* 69 */ "G0\000"
512 /* 72 */ "I0\000"
513 /* 75 */ "L0\000"
514 /* 78 */ "O0\000"
515 /* 81 */ "Q0\000"
516 /* 84 */ "C10_C11\000"
517 /* 92 */ "D11\000"
518 /* 96 */ "F11\000"
519 /* 100 */ "Q11\000"
520 /* 104 */ "ASR11\000"
521 /* 110 */ "C20_C21\000"
522 /* 118 */ "D21\000"
523 /* 122 */ "F21\000"
524 /* 126 */ "ASR21\000"
525 /* 132 */ "C30_C31\000"
526 /* 140 */ "D31\000"
527 /* 144 */ "F31\000"
528 /* 148 */ "ASR31\000"
529 /* 154 */ "FCC1\000"
530 /* 159 */ "C0_C1\000"
531 /* 165 */ "D1\000"
532 /* 168 */ "F1\000"
533 /* 171 */ "G0_G1\000"
534 /* 177 */ "I0_I1\000"
535 /* 183 */ "L0_L1\000"
536 /* 189 */ "O0_O1\000"
537 /* 195 */ "Q1\000"
538 /* 198 */ "ASR1\000"
539 /* 203 */ "C12\000"
540 /* 207 */ "D12\000"
541 /* 211 */ "F12\000"
542 /* 215 */ "Q12\000"
543 /* 219 */ "ASR12\000"
544 /* 225 */ "C22\000"
545 /* 229 */ "D22\000"
546 /* 233 */ "F22\000"
547 /* 237 */ "ASR22\000"
548 /* 243 */ "FCC2\000"
549 /* 248 */ "D2\000"
550 /* 251 */ "F2\000"
551 /* 254 */ "G2\000"
552 /* 257 */ "I2\000"
553 /* 260 */ "L2\000"
554 /* 263 */ "O2\000"
555 /* 266 */ "Q2\000"
556 /* 269 */ "ASR2\000"
557 /* 274 */ "C12_C13\000"
558 /* 282 */ "D13\000"
559 /* 286 */ "F13\000"
560 /* 290 */ "Q13\000"
561 /* 294 */ "ASR13\000"
562 /* 300 */ "C22_C23\000"
563 /* 308 */ "D23\000"
564 /* 312 */ "F23\000"
565 /* 316 */ "ASR23\000"
566 /* 322 */ "FCC3\000"
567 /* 327 */ "C2_C3\000"
568 /* 333 */ "D3\000"
569 /* 336 */ "F3\000"
570 /* 339 */ "G2_G3\000"
571 /* 345 */ "I2_I3\000"
572 /* 351 */ "L2_L3\000"
573 /* 357 */ "O2_O3\000"
574 /* 363 */ "Q3\000"
575 /* 366 */ "ASR3\000"
576 /* 371 */ "C14\000"
577 /* 375 */ "D14\000"
578 /* 379 */ "F14\000"
579 /* 383 */ "Q14\000"
580 /* 387 */ "ASR14\000"
581 /* 393 */ "C24\000"
582 /* 397 */ "D24\000"
583 /* 401 */ "F24\000"
584 /* 405 */ "ASR24\000"
585 /* 411 */ "C4\000"
586 /* 414 */ "D4\000"
587 /* 417 */ "F4\000"
588 /* 420 */ "G4\000"
589 /* 423 */ "I4\000"
590 /* 426 */ "L4\000"
591 /* 429 */ "O4\000"
592 /* 432 */ "Q4\000"
593 /* 435 */ "ASR4\000"
594 /* 440 */ "C14_C15\000"
595 /* 448 */ "D15\000"
596 /* 452 */ "F15\000"
597 /* 456 */ "Q15\000"
598 /* 460 */ "ASR15\000"
599 /* 466 */ "C24_C25\000"
600 /* 474 */ "D25\000"
601 /* 478 */ "F25\000"
602 /* 482 */ "ASR25\000"
603 /* 488 */ "C4_C5\000"
604 /* 494 */ "D5\000"
605 /* 497 */ "F5\000"
606 /* 500 */ "G4_G5\000"
607 /* 506 */ "I4_I5\000"
608 /* 512 */ "L4_L5\000"
609 /* 518 */ "O4_O5\000"
610 /* 524 */ "Q5\000"
611 /* 527 */ "ASR5\000"
612 /* 532 */ "C16\000"
613 /* 536 */ "D16\000"
614 /* 540 */ "F16\000"
615 /* 544 */ "ASR16\000"
616 /* 550 */ "C26\000"
617 /* 554 */ "D26\000"
618 /* 558 */ "F26\000"
619 /* 562 */ "ASR26\000"
620 /* 568 */ "C6\000"
621 /* 571 */ "D6\000"
622 /* 574 */ "F6\000"
623 /* 577 */ "G6\000"
624 /* 580 */ "I6\000"
625 /* 583 */ "L6\000"
626 /* 586 */ "O6\000"
627 /* 589 */ "Q6\000"
628 /* 592 */ "ASR6\000"
629 /* 597 */ "C16_C17\000"
630 /* 605 */ "D17\000"
631 /* 609 */ "F17\000"
632 /* 613 */ "ASR17\000"
633 /* 619 */ "C26_C27\000"
634 /* 627 */ "D27\000"
635 /* 631 */ "F27\000"
636 /* 635 */ "ASR27\000"
637 /* 641 */ "C6_C7\000"
638 /* 647 */ "D7\000"
639 /* 650 */ "F7\000"
640 /* 653 */ "G6_G7\000"
641 /* 659 */ "I6_I7\000"
642 /* 665 */ "L6_L7\000"
643 /* 671 */ "O6_O7\000"
644 /* 677 */ "Q7\000"
645 /* 680 */ "ASR7\000"
646 /* 685 */ "C18\000"
647 /* 689 */ "D18\000"
648 /* 693 */ "F18\000"
649 /* 697 */ "ASR18\000"
650 /* 703 */ "C28\000"
651 /* 707 */ "D28\000"
652 /* 711 */ "F28\000"
653 /* 715 */ "ASR28\000"
654 /* 721 */ "C8\000"
655 /* 724 */ "D8\000"
656 /* 727 */ "F8\000"
657 /* 730 */ "Q8\000"
658 /* 733 */ "ASR8\000"
659 /* 738 */ "C18_C19\000"
660 /* 746 */ "D19\000"
661 /* 750 */ "F19\000"
662 /* 754 */ "ASR19\000"
663 /* 760 */ "C28_C29\000"
664 /* 768 */ "D29\000"
665 /* 772 */ "F29\000"
666 /* 776 */ "ASR29\000"
667 /* 782 */ "C8_C9\000"
668 /* 788 */ "D9\000"
669 /* 791 */ "F9\000"
670 /* 794 */ "Q9\000"
671 /* 797 */ "ASR9\000"
672 /* 802 */ "TBA\000"
673 /* 806 */ "ICC\000"
674 /* 810 */ "TNPC\000"
675 /* 815 */ "TPC\000"
676 /* 819 */ "CANRESTORE\000"
677 /* 830 */ "PSTATE\000"
678 /* 837 */ "TSTATE\000"
679 /* 844 */ "WSTATE\000"
680 /* 851 */ "CANSAVE\000"
681 /* 859 */ "TICK\000"
682 /* 864 */ "GL\000"
683 /* 867 */ "PIL\000"
684 /* 871 */ "TL\000"
685 /* 874 */ "WIM\000"
686 /* 878 */ "CLEANWIN\000"
687 /* 887 */ "OTHERWIN\000"
688 /* 896 */ "CWP\000"
689 /* 900 */ "FQ\000"
690 /* 903 */ "CPQ\000"
691 /* 907 */ "TBR\000"
692 /* 911 */ "VER\000"
693 /* 915 */ "FSR\000"
694 /* 919 */ "CPSR\000"
695 /* 924 */ "TT\000"
696 /* 927 */ "Y\000"
697};
698#ifdef __GNUC__
699#pragma GCC diagnostic pop
700#endif
701
702extern const MCRegisterDesc SparcRegDesc[] = { // Descriptors
703 { 3, 0, 0, 0, 0, 0, 0, 0 },
704 { 819, 2, 2, 2, 8192, 8, 0, 0 },
705 { 851, 2, 2, 2, 8193, 8, 0, 0 },
706 { 878, 2, 2, 2, 8194, 8, 0, 0 },
707 { 903, 2, 2, 2, 8195, 8, 0, 0 },
708 { 919, 2, 2, 2, 8196, 8, 0, 0 },
709 { 896, 2, 2, 2, 8197, 8, 0, 0 },
710 { 900, 2, 2, 2, 8198, 8, 0, 0 },
711 { 915, 2, 2, 2, 8199, 8, 0, 0 },
712 { 864, 2, 2, 2, 8200, 8, 0, 0 },
713 { 806, 2, 2, 2, 8201, 8, 0, 0 },
714 { 887, 2, 2, 2, 8202, 8, 0, 0 },
715 { 867, 2, 2, 2, 8203, 8, 0, 0 },
716 { 920, 2, 2, 2, 8204, 8, 0, 0 },
717 { 830, 2, 2, 2, 8205, 8, 0, 0 },
718 { 802, 2, 2, 2, 8206, 8, 0, 0 },
719 { 907, 2, 2, 2, 8207, 8, 0, 0 },
720 { 859, 2, 2, 2, 8208, 8, 0, 0 },
721 { 871, 2, 2, 2, 8209, 8, 0, 0 },
722 { 810, 2, 2, 2, 8210, 8, 0, 0 },
723 { 815, 2, 2, 2, 8211, 8, 0, 0 },
724 { 837, 2, 2, 2, 8212, 8, 0, 0 },
725 { 924, 2, 2, 2, 8213, 8, 0, 0 },
726 { 911, 2, 2, 2, 8214, 8, 0, 0 },
727 { 874, 2, 2, 2, 8215, 8, 0, 0 },
728 { 844, 2, 2, 2, 8216, 8, 0, 0 },
729 { 927, 2, 2, 2, 8217, 8, 0, 0 },
730 { 198, 2, 2, 2, 8218, 8, 0, 0 },
731 { 269, 2, 2, 2, 8219, 8, 0, 0 },
732 { 366, 2, 2, 2, 8220, 8, 0, 0 },
733 { 435, 2, 2, 2, 8221, 8, 0, 0 },
734 { 527, 2, 2, 2, 8222, 8, 0, 0 },
735 { 592, 2, 2, 2, 8223, 8, 0, 0 },
736 { 680, 2, 2, 2, 8224, 8, 0, 0 },
737 { 733, 2, 2, 2, 8225, 8, 0, 0 },
738 { 797, 2, 2, 2, 8226, 8, 0, 0 },
739 { 16, 2, 2, 2, 8227, 8, 0, 0 },
740 { 104, 2, 2, 2, 8228, 8, 0, 0 },
741 { 219, 2, 2, 2, 8229, 8, 0, 0 },
742 { 294, 2, 2, 2, 8230, 8, 0, 0 },
743 { 387, 2, 2, 2, 8231, 8, 0, 0 },
744 { 460, 2, 2, 2, 8232, 8, 0, 0 },
745 { 544, 2, 2, 2, 8233, 8, 0, 0 },
746 { 613, 2, 2, 2, 8234, 8, 0, 0 },
747 { 697, 2, 2, 2, 8235, 8, 0, 0 },
748 { 754, 2, 2, 2, 8236, 8, 0, 0 },
749 { 34, 2, 2, 2, 8237, 8, 0, 0 },
750 { 126, 2, 2, 2, 8238, 8, 0, 0 },
751 { 237, 2, 2, 2, 8239, 8, 0, 0 },
752 { 316, 2, 2, 2, 8240, 8, 0, 0 },
753 { 405, 2, 2, 2, 8241, 8, 0, 0 },
754 { 482, 2, 2, 2, 8242, 8, 0, 0 },
755 { 562, 2, 2, 2, 8243, 8, 0, 0 },
756 { 635, 2, 2, 2, 8244, 8, 0, 0 },
757 { 715, 2, 2, 2, 8245, 8, 0, 0 },
758 { 776, 2, 2, 2, 8246, 8, 0, 0 },
759 { 52, 2, 2, 2, 8247, 8, 0, 0 },
760 { 148, 2, 2, 2, 8248, 8, 0, 0 },
761 { 60, 2, 361, 2, 8249, 8, 0, 0 },
762 { 156, 2, 359, 2, 8250, 8, 0, 0 },
763 { 245, 2, 359, 2, 8251, 8, 0, 0 },
764 { 324, 2, 357, 2, 8252, 8, 0, 0 },
765 { 411, 2, 357, 2, 8253, 8, 0, 0 },
766 { 491, 2, 355, 2, 8254, 8, 0, 0 },
767 { 568, 2, 355, 2, 8255, 8, 0, 0 },
768 { 644, 2, 353, 2, 8256, 8, 0, 0 },
769 { 721, 2, 353, 2, 8257, 8, 0, 0 },
770 { 785, 2, 351, 2, 8258, 8, 0, 0 },
771 { 0, 2, 351, 2, 8259, 8, 0, 0 },
772 { 88, 2, 349, 2, 8260, 8, 0, 0 },
773 { 203, 2, 349, 2, 8261, 8, 0, 0 },
774 { 278, 2, 347, 2, 8262, 8, 0, 0 },
775 { 371, 2, 347, 2, 8263, 8, 0, 0 },
776 { 444, 2, 345, 2, 8264, 8, 0, 0 },
777 { 532, 2, 345, 2, 8265, 8, 0, 0 },
778 { 601, 2, 343, 2, 8266, 8, 0, 0 },
779 { 685, 2, 343, 2, 8267, 8, 0, 0 },
780 { 742, 2, 341, 2, 8268, 8, 0, 0 },
781 { 22, 2, 341, 2, 8269, 8, 0, 0 },
782 { 114, 2, 339, 2, 8270, 8, 0, 0 },
783 { 225, 2, 339, 2, 8271, 8, 0, 0 },
784 { 304, 2, 337, 2, 8272, 8, 0, 0 },
785 { 393, 2, 337, 2, 8273, 8, 0, 0 },
786 { 470, 2, 335, 2, 8274, 8, 0, 0 },
787 { 550, 2, 335, 2, 8275, 8, 0, 0 },
788 { 623, 2, 333, 2, 8276, 8, 0, 0 },
789 { 703, 2, 333, 2, 8277, 8, 0, 0 },
790 { 764, 2, 331, 2, 8278, 8, 0, 0 },
791 { 40, 2, 331, 2, 8279, 8, 0, 0 },
792 { 136, 2, 329, 2, 8280, 8, 0, 0 },
793 { 63, 124, 324, 0, 4185, 0, 0, 0 },
794 { 165, 131, 315, 0, 4187, 0, 0, 0 },
795 { 248, 134, 315, 0, 4189, 0, 0, 0 },
796 { 333, 141, 306, 0, 4191, 0, 0, 0 },
797 { 414, 144, 306, 0, 4193, 0, 0, 0 },
798 { 494, 151, 297, 0, 4195, 0, 0, 0 },
799 { 571, 154, 297, 0, 4197, 0, 0, 0 },
800 { 647, 161, 288, 0, 4199, 0, 0, 0 },
801 { 724, 164, 288, 0, 4201, 0, 0, 0 },
802 { 788, 171, 279, 0, 4203, 0, 0, 0 },
803 { 4, 174, 279, 0, 4205, 0, 0, 0 },
804 { 92, 181, 270, 0, 4207, 0, 0, 0 },
805 { 207, 184, 270, 0, 4209, 0, 0, 0 },
806 { 282, 191, 261, 0, 4211, 0, 0, 0 },
807 { 375, 194, 261, 0, 4213, 0, 0, 0 },
808 { 448, 201, 255, 0, 4215, 0, 0, 0 },
809 { 536, 2, 255, 2, 8313, 8, 0, 0 },
810 { 605, 2, 252, 2, 8314, 8, 0, 0 },
811 { 689, 2, 252, 2, 8315, 8, 0, 0 },
812 { 746, 2, 250, 2, 8316, 8, 0, 0 },
813 { 26, 2, 250, 2, 8317, 8, 0, 0 },
814 { 118, 2, 248, 2, 8318, 8, 0, 0 },
815 { 229, 2, 248, 2, 8319, 8, 0, 0 },
816 { 308, 2, 246, 2, 8320, 8, 0, 0 },
817 { 397, 2, 246, 2, 8321, 8, 0, 0 },
818 { 474, 2, 244, 2, 8322, 8, 0, 0 },
819 { 554, 2, 244, 2, 8323, 8, 0, 0 },
820 { 627, 2, 242, 2, 8324, 8, 0, 0 },
821 { 707, 2, 242, 2, 8325, 8, 0, 0 },
822 { 768, 2, 240, 2, 8326, 8, 0, 0 },
823 { 44, 2, 240, 2, 8327, 8, 0, 0 },
824 { 140, 2, 238, 2, 8328, 8, 0, 0 },
825 { 66, 2, 326, 2, 8281, 8, 0, 0 },
826 { 168, 2, 323, 2, 8282, 8, 0, 0 },
827 { 251, 2, 320, 2, 8283, 8, 0, 0 },
828 { 336, 2, 317, 2, 8284, 8, 0, 0 },
829 { 417, 2, 317, 2, 8285, 8, 0, 0 },
830 { 497, 2, 314, 2, 8286, 8, 0, 0 },
831 { 574, 2, 311, 2, 8287, 8, 0, 0 },
832 { 650, 2, 308, 2, 8288, 8, 0, 0 },
833 { 727, 2, 308, 2, 8289, 8, 0, 0 },
834 { 791, 2, 305, 2, 8290, 8, 0, 0 },
835 { 8, 2, 302, 2, 8291, 8, 0, 0 },
836 { 96, 2, 299, 2, 8292, 8, 0, 0 },
837 { 211, 2, 299, 2, 8293, 8, 0, 0 },
838 { 286, 2, 296, 2, 8294, 8, 0, 0 },
839 { 379, 2, 293, 2, 8295, 8, 0, 0 },
840 { 452, 2, 290, 2, 8296, 8, 0, 0 },
841 { 540, 2, 290, 2, 8297, 8, 0, 0 },
842 { 609, 2, 287, 2, 8298, 8, 0, 0 },
843 { 693, 2, 284, 2, 8299, 8, 0, 0 },
844 { 750, 2, 281, 2, 8300, 8, 0, 0 },
845 { 30, 2, 281, 2, 8301, 8, 0, 0 },
846 { 122, 2, 278, 2, 8302, 8, 0, 0 },
847 { 233, 2, 275, 2, 8303, 8, 0, 0 },
848 { 312, 2, 272, 2, 8304, 8, 0, 0 },
849 { 401, 2, 272, 2, 8305, 8, 0, 0 },
850 { 478, 2, 269, 2, 8306, 8, 0, 0 },
851 { 558, 2, 266, 2, 8307, 8, 0, 0 },
852 { 631, 2, 263, 2, 8308, 8, 0, 0 },
853 { 711, 2, 263, 2, 8309, 8, 0, 0 },
854 { 772, 2, 260, 2, 8310, 8, 0, 0 },
855 { 48, 2, 257, 2, 8311, 8, 0, 0 },
856 { 144, 2, 254, 2, 8312, 8, 0, 0 },
857 { 58, 2, 2, 2, 8329, 8, 0, 0 },
858 { 154, 2, 2, 2, 8330, 8, 0, 0 },
859 { 243, 2, 2, 2, 8331, 8, 0, 0 },
860 { 322, 2, 2, 2, 8332, 8, 0, 0 },
861 { 69, 2, 236, 2, 8333, 8, 1, 0 },
862 { 174, 2, 234, 2, 8334, 8, 0, 0 },
863 { 254, 2, 234, 2, 8335, 8, 0, 0 },
864 { 342, 2, 232, 2, 8336, 8, 0, 0 },
865 { 420, 2, 232, 2, 8337, 8, 0, 0 },
866 { 503, 2, 230, 2, 8338, 8, 0, 0 },
867 { 577, 2, 230, 2, 8339, 8, 0, 0 },
868 { 656, 2, 228, 2, 8340, 8, 0, 0 },
869 { 72, 2, 228, 2, 8341, 8, 0, 0 },
870 { 180, 2, 226, 2, 8342, 8, 0, 0 },
871 { 257, 2, 226, 2, 8343, 8, 0, 0 },
872 { 348, 2, 224, 2, 8344, 8, 0, 0 },
873 { 423, 2, 224, 2, 8345, 8, 0, 0 },
874 { 509, 2, 222, 2, 8346, 8, 0, 0 },
875 { 580, 2, 222, 2, 8347, 8, 0, 0 },
876 { 662, 2, 220, 2, 8348, 8, 0, 0 },
877 { 75, 2, 220, 2, 8349, 8, 0, 0 },
878 { 186, 2, 218, 2, 8350, 8, 0, 0 },
879 { 260, 2, 218, 2, 8351, 8, 0, 0 },
880 { 354, 2, 216, 2, 8352, 8, 0, 0 },
881 { 426, 2, 216, 2, 8353, 8, 0, 0 },
882 { 515, 2, 214, 2, 8354, 8, 0, 0 },
883 { 583, 2, 214, 2, 8355, 8, 0, 0 },
884 { 668, 2, 212, 2, 8356, 8, 0, 0 },
885 { 78, 2, 212, 2, 8357, 8, 0, 0 },
886 { 192, 2, 210, 2, 8358, 8, 0, 0 },
887 { 263, 2, 210, 2, 8359, 8, 0, 0 },
888 { 360, 2, 208, 2, 8360, 8, 0, 0 },
889 { 429, 2, 208, 2, 8361, 8, 0, 0 },
890 { 521, 2, 206, 2, 8362, 8, 0, 0 },
891 { 586, 2, 206, 2, 8363, 8, 0, 0 },
892 { 674, 2, 204, 2, 8364, 8, 0, 0 },
893 { 81, 127, 2, 4, 491609, 2, 0, 0 },
894 { 195, 137, 2, 4, 491613, 2, 0, 0 },
895 { 266, 147, 2, 4, 491617, 2, 0, 0 },
896 { 363, 157, 2, 4, 491621, 2, 0, 0 },
897 { 432, 167, 2, 4, 491625, 2, 0, 0 },
898 { 524, 177, 2, 4, 491629, 2, 0, 0 },
899 { 589, 187, 2, 4, 491633, 2, 0, 0 },
900 { 677, 197, 2, 4, 491637, 2, 0, 0 },
901 { 730, 48, 2, 2, 4217, 6, 0, 0 },
902 { 794, 51, 2, 2, 4219, 6, 0, 0 },
903 { 12, 54, 2, 2, 4221, 6, 0, 0 },
904 { 100, 57, 2, 2, 4223, 6, 0, 0 },
905 { 215, 60, 2, 2, 4225, 6, 0, 0 },
906 { 290, 63, 2, 2, 4227, 6, 0, 0 },
907 { 383, 66, 2, 2, 4229, 6, 0, 0 },
908 { 456, 69, 2, 2, 4231, 6, 0, 0 },
909 { 159, 0, 2, 0, 4153, 0, 0, 0 },
910 { 327, 3, 2, 0, 4155, 0, 0, 0 },
911 { 488, 6, 2, 0, 4157, 0, 0, 0 },
912 { 641, 9, 2, 0, 4159, 0, 0, 0 },
913 { 782, 12, 2, 0, 4161, 0, 0, 0 },
914 { 84, 15, 2, 0, 4163, 0, 0, 0 },
915 { 274, 18, 2, 0, 4165, 0, 0, 0 },
916 { 440, 21, 2, 0, 4167, 0, 0, 0 },
917 { 597, 24, 2, 0, 4169, 0, 0, 0 },
918 { 738, 27, 2, 0, 4171, 0, 0, 0 },
919 { 110, 30, 2, 0, 4173, 0, 0, 0 },
920 { 300, 33, 2, 0, 4175, 0, 0, 0 },
921 { 466, 36, 2, 0, 4177, 0, 0, 0 },
922 { 619, 39, 2, 0, 4179, 0, 0, 0 },
923 { 760, 42, 2, 0, 4181, 0, 0, 0 },
924 { 132, 45, 2, 0, 4183, 0, 0, 0 },
925 { 171, 72, 2, 0, 4237, 0, 0, 0 },
926 { 339, 75, 2, 0, 4239, 0, 0, 0 },
927 { 500, 78, 2, 0, 4241, 0, 0, 0 },
928 { 653, 81, 2, 0, 4243, 0, 0, 0 },
929 { 177, 84, 2, 0, 4245, 0, 0, 0 },
930 { 345, 87, 2, 0, 4247, 0, 0, 0 },
931 { 506, 90, 2, 0, 4249, 0, 0, 0 },
932 { 659, 93, 2, 0, 4251, 0, 0, 0 },
933 { 183, 96, 2, 0, 4253, 0, 0, 0 },
934 { 351, 99, 2, 0, 4255, 0, 0, 0 },
935 { 512, 102, 2, 0, 4257, 0, 0, 0 },
936 { 665, 105, 2, 0, 4259, 0, 0, 0 },
937 { 189, 108, 2, 0, 4261, 0, 0, 0 },
938 { 357, 111, 2, 0, 4263, 0, 0, 0 },
939 { 518, 114, 2, 0, 4265, 0, 0, 0 },
940 { 671, 117, 2, 0, 4267, 0, 0, 0 },
941};
942
943extern const MCPhysReg SparcRegUnitRoots[][2] = {
944 { SP::CANRESTORE },
945 { SP::CANSAVE },
946 { SP::CLEANWIN },
947 { SP::CPQ },
948 { SP::CPSR },
949 { SP::CWP },
950 { SP::FQ },
951 { SP::FSR },
952 { SP::GL },
953 { SP::ICC },
954 { SP::OTHERWIN },
955 { SP::PIL },
956 { SP::PSR },
957 { SP::PSTATE },
958 { SP::TBA },
959 { SP::TBR },
960 { SP::TICK },
961 { SP::TL },
962 { SP::TNPC },
963 { SP::TPC },
964 { SP::TSTATE },
965 { SP::TT },
966 { SP::VER },
967 { SP::WIM },
968 { SP::WSTATE },
969 { SP::Y },
970 { SP::ASR1 },
971 { SP::ASR2 },
972 { SP::ASR3 },
973 { SP::ASR4 },
974 { SP::ASR5 },
975 { SP::ASR6 },
976 { SP::ASR7 },
977 { SP::ASR8 },
978 { SP::ASR9 },
979 { SP::ASR10 },
980 { SP::ASR11 },
981 { SP::ASR12 },
982 { SP::ASR13 },
983 { SP::ASR14 },
984 { SP::ASR15 },
985 { SP::ASR16 },
986 { SP::ASR17 },
987 { SP::ASR18 },
988 { SP::ASR19 },
989 { SP::ASR20 },
990 { SP::ASR21 },
991 { SP::ASR22 },
992 { SP::ASR23 },
993 { SP::ASR24 },
994 { SP::ASR25 },
995 { SP::ASR26 },
996 { SP::ASR27 },
997 { SP::ASR28 },
998 { SP::ASR29 },
999 { SP::ASR30 },
1000 { SP::ASR31 },
1001 { SP::C0 },
1002 { SP::C1 },
1003 { SP::C2 },
1004 { SP::C3 },
1005 { SP::C4 },
1006 { SP::C5 },
1007 { SP::C6 },
1008 { SP::C7 },
1009 { SP::C8 },
1010 { SP::C9 },
1011 { SP::C10 },
1012 { SP::C11 },
1013 { SP::C12 },
1014 { SP::C13 },
1015 { SP::C14 },
1016 { SP::C15 },
1017 { SP::C16 },
1018 { SP::C17 },
1019 { SP::C18 },
1020 { SP::C19 },
1021 { SP::C20 },
1022 { SP::C21 },
1023 { SP::C22 },
1024 { SP::C23 },
1025 { SP::C24 },
1026 { SP::C25 },
1027 { SP::C26 },
1028 { SP::C27 },
1029 { SP::C28 },
1030 { SP::C29 },
1031 { SP::C30 },
1032 { SP::C31 },
1033 { SP::F0 },
1034 { SP::F1 },
1035 { SP::F2 },
1036 { SP::F3 },
1037 { SP::F4 },
1038 { SP::F5 },
1039 { SP::F6 },
1040 { SP::F7 },
1041 { SP::F8 },
1042 { SP::F9 },
1043 { SP::F10 },
1044 { SP::F11 },
1045 { SP::F12 },
1046 { SP::F13 },
1047 { SP::F14 },
1048 { SP::F15 },
1049 { SP::F16 },
1050 { SP::F17 },
1051 { SP::F18 },
1052 { SP::F19 },
1053 { SP::F20 },
1054 { SP::F21 },
1055 { SP::F22 },
1056 { SP::F23 },
1057 { SP::F24 },
1058 { SP::F25 },
1059 { SP::F26 },
1060 { SP::F27 },
1061 { SP::F28 },
1062 { SP::F29 },
1063 { SP::F30 },
1064 { SP::F31 },
1065 { SP::D16 },
1066 { SP::D17 },
1067 { SP::D18 },
1068 { SP::D19 },
1069 { SP::D20 },
1070 { SP::D21 },
1071 { SP::D22 },
1072 { SP::D23 },
1073 { SP::D24 },
1074 { SP::D25 },
1075 { SP::D26 },
1076 { SP::D27 },
1077 { SP::D28 },
1078 { SP::D29 },
1079 { SP::D30 },
1080 { SP::D31 },
1081 { SP::FCC0 },
1082 { SP::FCC1 },
1083 { SP::FCC2 },
1084 { SP::FCC3 },
1085 { SP::G0 },
1086 { SP::G1 },
1087 { SP::G2 },
1088 { SP::G3 },
1089 { SP::G4 },
1090 { SP::G5 },
1091 { SP::G6 },
1092 { SP::G7 },
1093 { SP::I0 },
1094 { SP::I1 },
1095 { SP::I2 },
1096 { SP::I3 },
1097 { SP::I4 },
1098 { SP::I5 },
1099 { SP::I6 },
1100 { SP::I7 },
1101 { SP::L0 },
1102 { SP::L1 },
1103 { SP::L2 },
1104 { SP::L3 },
1105 { SP::L4 },
1106 { SP::L5 },
1107 { SP::L6 },
1108 { SP::L7 },
1109 { SP::O0 },
1110 { SP::O1 },
1111 { SP::O2 },
1112 { SP::O3 },
1113 { SP::O4 },
1114 { SP::O5 },
1115 { SP::O6 },
1116 { SP::O7 },
1117};
1118
1119namespace { // Register classes...
1120 // FCCRegs Register Class...
1121 const MCPhysReg FCCRegs[] = {
1122 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3,
1123 };
1124
1125 // FCCRegs Bit set.
1126 const uint8_t FCCRegsBits[] = {
1127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1128 };
1129
1130 // ASRRegs Register Class...
1131 const MCPhysReg ASRRegs[] = {
1132 SP::Y, SP::TICK, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31,
1133 };
1134
1135 // ASRRegs Bit set.
1136 const uint8_t ASRRegsBits[] = {
1137 0x00, 0x00, 0x02, 0xfc, 0xff, 0xff, 0xff, 0x03,
1138 };
1139
1140 // CoprocRegs Register Class...
1141 const MCPhysReg CoprocRegs[] = {
1142 SP::C0, SP::C1, SP::C2, SP::C3, SP::C4, SP::C5, SP::C6, SP::C7, SP::C8, SP::C9, SP::C10, SP::C11, SP::C12, SP::C13, SP::C14, SP::C15, SP::C16, SP::C17, SP::C18, SP::C19, SP::C20, SP::C21, SP::C22, SP::C23, SP::C24, SP::C25, SP::C26, SP::C27, SP::C28, SP::C29, SP::C30, SP::C31,
1143 };
1144
1145 // CoprocRegs Bit set.
1146 const uint8_t CoprocRegsBits[] = {
1147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1148 };
1149
1150 // FPRegs Register Class...
1151 const MCPhysReg FPRegs[] = {
1152 SP::F0, SP::F1, SP::F2, SP::F3, SP::F4, SP::F5, SP::F6, SP::F7, SP::F8, SP::F9, SP::F10, SP::F11, SP::F12, SP::F13, SP::F14, SP::F15, SP::F16, SP::F17, SP::F18, SP::F19, SP::F20, SP::F21, SP::F22, SP::F23, SP::F24, SP::F25, SP::F26, SP::F27, SP::F28, SP::F29, SP::F30, SP::F31,
1153 };
1154
1155 // FPRegs Bit set.
1156 const uint8_t FPRegsBits[] = {
1157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1158 };
1159
1160 // IntRegs Register Class...
1161 const MCPhysReg IntRegs[] = {
1162 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1163 };
1164
1165 // IntRegs Bit set.
1166 const uint8_t IntRegsBits[] = {
1167 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1168 };
1169
1170 // GPRIncomingArg Register Class...
1171 const MCPhysReg GPRIncomingArg[] = {
1172 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1173 };
1174
1175 // GPRIncomingArg Bit set.
1176 const uint8_t GPRIncomingArgBits[] = {
1177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1178 };
1179
1180 // GPROutgoingArg Register Class...
1181 const MCPhysReg GPROutgoingArg[] = {
1182 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5,
1183 };
1184
1185 // GPROutgoingArg Bit set.
1186 const uint8_t GPROutgoingArgBits[] = {
1187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1188 };
1189
1190 // DFPRegs Register Class...
1191 const MCPhysReg DFPRegs[] = {
1192 SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31,
1193 };
1194
1195 // DFPRegs Bit set.
1196 const uint8_t DFPRegsBits[] = {
1197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1198 };
1199
1200 // I64Regs Register Class...
1201 const MCPhysReg I64Regs[] = {
1202 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1203 };
1204
1205 // I64Regs Bit set.
1206 const uint8_t I64RegsBits[] = {
1207 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1208 };
1209
1210 // PRRegs Register Class...
1211 const MCPhysReg PRRegs[] = {
1212 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE, SP::GL, SP::VER,
1213 };
1214
1215 // PRRegs Bit set.
1216 const uint8_t PRRegsBits[] = {
1217 0x4e, 0xda, 0xfe, 0x02,
1218 };
1219
1220 // CoprocPair Register Class...
1221 const MCPhysReg CoprocPair[] = {
1222 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31,
1223 };
1224
1225 // CoprocPair Bit set.
1226 const uint8_t CoprocPairBits[] = {
1227 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1228 };
1229
1230 // IntPair Register Class...
1231 const MCPhysReg IntPair[] = {
1232 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
1233 };
1234
1235 // IntPair Bit set.
1236 const uint8_t IntPairBits[] = {
1237 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1238 };
1239
1240 // LowDFPRegs Register Class...
1241 const MCPhysReg LowDFPRegs[] = {
1242 SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15,
1243 };
1244
1245 // LowDFPRegs Bit set.
1246 const uint8_t LowDFPRegsBits[] = {
1247 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
1248 };
1249
1250 // I64Regs_and_GPRIncomingArg Register Class...
1251 const MCPhysReg I64Regs_and_GPRIncomingArg[] = {
1252 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1253 };
1254
1255 // I64Regs_and_GPRIncomingArg Bit set.
1256 const uint8_t I64Regs_and_GPRIncomingArgBits[] = {
1257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1258 };
1259
1260 // I64Regs_and_GPROutgoingArg Register Class...
1261 const MCPhysReg I64Regs_and_GPROutgoingArg[] = {
1262 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5,
1263 };
1264
1265 // I64Regs_and_GPROutgoingArg Bit set.
1266 const uint8_t I64Regs_and_GPROutgoingArgBits[] = {
1267 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1268 };
1269
1270 // IntPair_with_sub_even_in_GPRIncomingArg Register Class...
1271 const MCPhysReg IntPair_with_sub_even_in_GPRIncomingArg[] = {
1272 SP::I0_I1, SP::I2_I3, SP::I4_I5,
1273 };
1274
1275 // IntPair_with_sub_even_in_GPRIncomingArg Bit set.
1276 const uint8_t IntPair_with_sub_even_in_GPRIncomingArgBits[] = {
1277 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
1278 };
1279
1280 // IntPair_with_sub_even_in_GPROutgoingArg Register Class...
1281 const MCPhysReg IntPair_with_sub_even_in_GPROutgoingArg[] = {
1282 SP::O0_O1, SP::O2_O3, SP::O4_O5,
1283 };
1284
1285 // IntPair_with_sub_even_in_GPROutgoingArg Bit set.
1286 const uint8_t IntPair_with_sub_even_in_GPROutgoingArgBits[] = {
1287 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
1288 };
1289
1290 // PRRegs_and_ASRRegs Register Class...
1291 const MCPhysReg PRRegs_and_ASRRegs[] = {
1292 SP::TICK,
1293 };
1294
1295 // PRRegs_and_ASRRegs Bit set.
1296 const uint8_t PRRegs_and_ASRRegsBits[] = {
1297 0x00, 0x00, 0x02,
1298 };
1299
1300 // QFPRegs Register Class...
1301 const MCPhysReg QFPRegs[] = {
1302 SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7, SP::Q8, SP::Q9, SP::Q10, SP::Q11, SP::Q12, SP::Q13, SP::Q14, SP::Q15,
1303 };
1304
1305 // QFPRegs Bit set.
1306 const uint8_t QFPRegsBits[] = {
1307 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1308 };
1309
1310 // LowQFPRegs Register Class...
1311 const MCPhysReg LowQFPRegs[] = {
1312 SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7,
1313 };
1314
1315 // LowQFPRegs Bit set.
1316 const uint8_t LowQFPRegsBits[] = {
1317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1318 };
1319
1320} // end anonymous namespace
1321
1322
1323#ifdef __GNUC__
1324#pragma GCC diagnostic push
1325#pragma GCC diagnostic ignored "-Woverlength-strings"
1326#endif
1327extern const char SparcRegClassStrings[] = {
1328 /* 0 */ "I64Regs_and_GPRIncomingArg\000"
1329 /* 27 */ "IntPair_with_sub_even_in_GPRIncomingArg\000"
1330 /* 67 */ "I64Regs_and_GPROutgoingArg\000"
1331 /* 94 */ "IntPair_with_sub_even_in_GPROutgoingArg\000"
1332 /* 134 */ "CoprocPair\000"
1333 /* 145 */ "IntPair\000"
1334 /* 153 */ "I64Regs\000"
1335 /* 161 */ "FCCRegs\000"
1336 /* 169 */ "LowDFPRegs\000"
1337 /* 180 */ "LowQFPRegs\000"
1338 /* 191 */ "PRRegs\000"
1339 /* 198 */ "PRRegs_and_ASRRegs\000"
1340 /* 217 */ "CoprocRegs\000"
1341 /* 228 */ "IntRegs\000"
1342};
1343#ifdef __GNUC__
1344#pragma GCC diagnostic pop
1345#endif
1346
1347extern const MCRegisterClass SparcMCRegisterClasses[] = {
1348 { FCCRegs, FCCRegsBits, 161, 4, sizeof(FCCRegsBits), SP::FCCRegsRegClassID, 1, 1, true, false },
1349 { ASRRegs, ASRRegsBits, 209, 33, sizeof(ASRRegsBits), SP::ASRRegsRegClassID, 32, 1, false, false },
1350 { CoprocRegs, CoprocRegsBits, 217, 32, sizeof(CoprocRegsBits), SP::CoprocRegsRegClassID, 32, 1, false, false },
1351 { FPRegs, FPRegsBits, 173, 32, sizeof(FPRegsBits), SP::FPRegsRegClassID, 32, 1, true, false },
1352 { IntRegs, IntRegsBits, 228, 32, sizeof(IntRegsBits), SP::IntRegsRegClassID, 32, 1, true, false },
1353 { GPRIncomingArg, GPRIncomingArgBits, 12, 6, sizeof(GPRIncomingArgBits), SP::GPRIncomingArgRegClassID, 32, 1, true, false },
1354 { GPROutgoingArg, GPROutgoingArgBits, 79, 6, sizeof(GPROutgoingArgBits), SP::GPROutgoingArgRegClassID, 32, 1, true, false },
1355 { DFPRegs, DFPRegsBits, 172, 32, sizeof(DFPRegsBits), SP::DFPRegsRegClassID, 64, 1, true, false },
1356 { I64Regs, I64RegsBits, 153, 32, sizeof(I64RegsBits), SP::I64RegsRegClassID, 64, 1, true, false },
1357 { PRRegs, PRRegsBits, 191, 17, sizeof(PRRegsBits), SP::PRRegsRegClassID, 64, 1, true, false },
1358 { CoprocPair, CoprocPairBits, 134, 16, sizeof(CoprocPairBits), SP::CoprocPairRegClassID, 64, 1, false, false },
1359 { IntPair, IntPairBits, 145, 16, sizeof(IntPairBits), SP::IntPairRegClassID, 64, 1, true, false },
1360 { LowDFPRegs, LowDFPRegsBits, 169, 16, sizeof(LowDFPRegsBits), SP::LowDFPRegsRegClassID, 64, 1, true, false },
1361 { I64Regs_and_GPRIncomingArg, I64Regs_and_GPRIncomingArgBits, 0, 6, sizeof(I64Regs_and_GPRIncomingArgBits), SP::I64Regs_and_GPRIncomingArgRegClassID, 64, 1, true, false },
1362 { I64Regs_and_GPROutgoingArg, I64Regs_and_GPROutgoingArgBits, 67, 6, sizeof(I64Regs_and_GPROutgoingArgBits), SP::I64Regs_and_GPROutgoingArgRegClassID, 64, 1, true, false },
1363 { IntPair_with_sub_even_in_GPRIncomingArg, IntPair_with_sub_even_in_GPRIncomingArgBits, 27, 3, sizeof(IntPair_with_sub_even_in_GPRIncomingArgBits), SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, 64, 1, true, false },
1364 { IntPair_with_sub_even_in_GPROutgoingArg, IntPair_with_sub_even_in_GPROutgoingArgBits, 94, 3, sizeof(IntPair_with_sub_even_in_GPROutgoingArgBits), SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, 64, 1, true, false },
1365 { PRRegs_and_ASRRegs, PRRegs_and_ASRRegsBits, 198, 1, sizeof(PRRegs_and_ASRRegsBits), SP::PRRegs_and_ASRRegsRegClassID, 64, 1, true, false },
1366 { QFPRegs, QFPRegsBits, 183, 16, sizeof(QFPRegsBits), SP::QFPRegsRegClassID, 128, 1, true, false },
1367 { LowQFPRegs, LowQFPRegsBits, 180, 8, sizeof(LowQFPRegsBits), SP::LowQFPRegsRegClassID, 128, 1, true, false },
1368};
1369
1370// SP Dwarf<->LLVM register mappings.
1371extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[] = {
1372 { 0U, SP::G0 },
1373 { 1U, SP::G1 },
1374 { 2U, SP::G2 },
1375 { 3U, SP::G3 },
1376 { 4U, SP::G4 },
1377 { 5U, SP::G5 },
1378 { 6U, SP::G6 },
1379 { 7U, SP::G7 },
1380 { 8U, SP::O0 },
1381 { 9U, SP::O1 },
1382 { 10U, SP::O2 },
1383 { 11U, SP::O3 },
1384 { 12U, SP::O4 },
1385 { 13U, SP::O5 },
1386 { 14U, SP::O6 },
1387 { 15U, SP::O7 },
1388 { 16U, SP::L0 },
1389 { 17U, SP::L1 },
1390 { 18U, SP::L2 },
1391 { 19U, SP::L3 },
1392 { 20U, SP::L4 },
1393 { 21U, SP::L5 },
1394 { 22U, SP::L6 },
1395 { 23U, SP::L7 },
1396 { 24U, SP::I0 },
1397 { 25U, SP::I1 },
1398 { 26U, SP::I2 },
1399 { 27U, SP::I3 },
1400 { 28U, SP::I4 },
1401 { 29U, SP::I5 },
1402 { 30U, SP::I6 },
1403 { 31U, SP::I7 },
1404 { 32U, SP::F0 },
1405 { 33U, SP::F1 },
1406 { 34U, SP::F2 },
1407 { 35U, SP::F3 },
1408 { 36U, SP::F4 },
1409 { 37U, SP::F5 },
1410 { 38U, SP::F6 },
1411 { 39U, SP::F7 },
1412 { 40U, SP::F8 },
1413 { 41U, SP::F9 },
1414 { 42U, SP::F10 },
1415 { 43U, SP::F11 },
1416 { 44U, SP::F12 },
1417 { 45U, SP::F13 },
1418 { 46U, SP::F14 },
1419 { 47U, SP::F15 },
1420 { 48U, SP::F16 },
1421 { 49U, SP::F17 },
1422 { 50U, SP::F18 },
1423 { 51U, SP::F19 },
1424 { 52U, SP::F20 },
1425 { 53U, SP::F21 },
1426 { 54U, SP::F22 },
1427 { 55U, SP::F23 },
1428 { 56U, SP::F24 },
1429 { 57U, SP::F25 },
1430 { 58U, SP::F26 },
1431 { 59U, SP::F27 },
1432 { 60U, SP::F28 },
1433 { 61U, SP::F29 },
1434 { 62U, SP::F30 },
1435 { 63U, SP::F31 },
1436 { 64U, SP::Y },
1437 { 72U, SP::D0 },
1438 { 73U, SP::D1 },
1439 { 74U, SP::D2 },
1440 { 75U, SP::D3 },
1441 { 76U, SP::D4 },
1442 { 77U, SP::D5 },
1443 { 78U, SP::D6 },
1444 { 79U, SP::D7 },
1445 { 80U, SP::D8 },
1446 { 81U, SP::D9 },
1447 { 82U, SP::D10 },
1448 { 83U, SP::D11 },
1449 { 84U, SP::D12 },
1450 { 85U, SP::D13 },
1451 { 86U, SP::D14 },
1452 { 87U, SP::D15 },
1453};
1454extern const unsigned SPDwarfFlavour0Dwarf2LSize = std::size(SPDwarfFlavour0Dwarf2L);
1455
1456extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[] = {
1457 { 0U, SP::G0 },
1458 { 1U, SP::G1 },
1459 { 2U, SP::G2 },
1460 { 3U, SP::G3 },
1461 { 4U, SP::G4 },
1462 { 5U, SP::G5 },
1463 { 6U, SP::G6 },
1464 { 7U, SP::G7 },
1465 { 8U, SP::O0 },
1466 { 9U, SP::O1 },
1467 { 10U, SP::O2 },
1468 { 11U, SP::O3 },
1469 { 12U, SP::O4 },
1470 { 13U, SP::O5 },
1471 { 14U, SP::O6 },
1472 { 15U, SP::O7 },
1473 { 16U, SP::L0 },
1474 { 17U, SP::L1 },
1475 { 18U, SP::L2 },
1476 { 19U, SP::L3 },
1477 { 20U, SP::L4 },
1478 { 21U, SP::L5 },
1479 { 22U, SP::L6 },
1480 { 23U, SP::L7 },
1481 { 24U, SP::I0 },
1482 { 25U, SP::I1 },
1483 { 26U, SP::I2 },
1484 { 27U, SP::I3 },
1485 { 28U, SP::I4 },
1486 { 29U, SP::I5 },
1487 { 30U, SP::I6 },
1488 { 31U, SP::I7 },
1489 { 32U, SP::F0 },
1490 { 33U, SP::F1 },
1491 { 34U, SP::F2 },
1492 { 35U, SP::F3 },
1493 { 36U, SP::F4 },
1494 { 37U, SP::F5 },
1495 { 38U, SP::F6 },
1496 { 39U, SP::F7 },
1497 { 40U, SP::F8 },
1498 { 41U, SP::F9 },
1499 { 42U, SP::F10 },
1500 { 43U, SP::F11 },
1501 { 44U, SP::F12 },
1502 { 45U, SP::F13 },
1503 { 46U, SP::F14 },
1504 { 47U, SP::F15 },
1505 { 48U, SP::F16 },
1506 { 49U, SP::F17 },
1507 { 50U, SP::F18 },
1508 { 51U, SP::F19 },
1509 { 52U, SP::F20 },
1510 { 53U, SP::F21 },
1511 { 54U, SP::F22 },
1512 { 55U, SP::F23 },
1513 { 56U, SP::F24 },
1514 { 57U, SP::F25 },
1515 { 58U, SP::F26 },
1516 { 59U, SP::F27 },
1517 { 60U, SP::F28 },
1518 { 61U, SP::F29 },
1519 { 62U, SP::F30 },
1520 { 63U, SP::F31 },
1521 { 64U, SP::Y },
1522 { 72U, SP::D0 },
1523 { 73U, SP::D1 },
1524 { 74U, SP::D2 },
1525 { 75U, SP::D3 },
1526 { 76U, SP::D4 },
1527 { 77U, SP::D5 },
1528 { 78U, SP::D6 },
1529 { 79U, SP::D7 },
1530 { 80U, SP::D8 },
1531 { 81U, SP::D9 },
1532 { 82U, SP::D10 },
1533 { 83U, SP::D11 },
1534 { 84U, SP::D12 },
1535 { 85U, SP::D13 },
1536 { 86U, SP::D14 },
1537 { 87U, SP::D15 },
1538};
1539extern const unsigned SPEHFlavour0Dwarf2LSize = std::size(SPEHFlavour0Dwarf2L);
1540
1541extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[] = {
1542 { SP::Y, 64U },
1543 { SP::D0, 72U },
1544 { SP::D1, 73U },
1545 { SP::D2, 74U },
1546 { SP::D3, 75U },
1547 { SP::D4, 76U },
1548 { SP::D5, 77U },
1549 { SP::D6, 78U },
1550 { SP::D7, 79U },
1551 { SP::D8, 80U },
1552 { SP::D9, 81U },
1553 { SP::D10, 82U },
1554 { SP::D11, 83U },
1555 { SP::D12, 84U },
1556 { SP::D13, 85U },
1557 { SP::D14, 86U },
1558 { SP::D15, 87U },
1559 { SP::F0, 32U },
1560 { SP::F1, 33U },
1561 { SP::F2, 34U },
1562 { SP::F3, 35U },
1563 { SP::F4, 36U },
1564 { SP::F5, 37U },
1565 { SP::F6, 38U },
1566 { SP::F7, 39U },
1567 { SP::F8, 40U },
1568 { SP::F9, 41U },
1569 { SP::F10, 42U },
1570 { SP::F11, 43U },
1571 { SP::F12, 44U },
1572 { SP::F13, 45U },
1573 { SP::F14, 46U },
1574 { SP::F15, 47U },
1575 { SP::F16, 48U },
1576 { SP::F17, 49U },
1577 { SP::F18, 50U },
1578 { SP::F19, 51U },
1579 { SP::F20, 52U },
1580 { SP::F21, 53U },
1581 { SP::F22, 54U },
1582 { SP::F23, 55U },
1583 { SP::F24, 56U },
1584 { SP::F25, 57U },
1585 { SP::F26, 58U },
1586 { SP::F27, 59U },
1587 { SP::F28, 60U },
1588 { SP::F29, 61U },
1589 { SP::F30, 62U },
1590 { SP::F31, 63U },
1591 { SP::G0, 0U },
1592 { SP::G1, 1U },
1593 { SP::G2, 2U },
1594 { SP::G3, 3U },
1595 { SP::G4, 4U },
1596 { SP::G5, 5U },
1597 { SP::G6, 6U },
1598 { SP::G7, 7U },
1599 { SP::I0, 24U },
1600 { SP::I1, 25U },
1601 { SP::I2, 26U },
1602 { SP::I3, 27U },
1603 { SP::I4, 28U },
1604 { SP::I5, 29U },
1605 { SP::I6, 30U },
1606 { SP::I7, 31U },
1607 { SP::L0, 16U },
1608 { SP::L1, 17U },
1609 { SP::L2, 18U },
1610 { SP::L3, 19U },
1611 { SP::L4, 20U },
1612 { SP::L5, 21U },
1613 { SP::L6, 22U },
1614 { SP::L7, 23U },
1615 { SP::O0, 8U },
1616 { SP::O1, 9U },
1617 { SP::O2, 10U },
1618 { SP::O3, 11U },
1619 { SP::O4, 12U },
1620 { SP::O5, 13U },
1621 { SP::O6, 14U },
1622 { SP::O7, 15U },
1623};
1624extern const unsigned SPDwarfFlavour0L2DwarfSize = std::size(SPDwarfFlavour0L2Dwarf);
1625
1626extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[] = {
1627 { SP::Y, 64U },
1628 { SP::D0, 72U },
1629 { SP::D1, 73U },
1630 { SP::D2, 74U },
1631 { SP::D3, 75U },
1632 { SP::D4, 76U },
1633 { SP::D5, 77U },
1634 { SP::D6, 78U },
1635 { SP::D7, 79U },
1636 { SP::D8, 80U },
1637 { SP::D9, 81U },
1638 { SP::D10, 82U },
1639 { SP::D11, 83U },
1640 { SP::D12, 84U },
1641 { SP::D13, 85U },
1642 { SP::D14, 86U },
1643 { SP::D15, 87U },
1644 { SP::F0, 32U },
1645 { SP::F1, 33U },
1646 { SP::F2, 34U },
1647 { SP::F3, 35U },
1648 { SP::F4, 36U },
1649 { SP::F5, 37U },
1650 { SP::F6, 38U },
1651 { SP::F7, 39U },
1652 { SP::F8, 40U },
1653 { SP::F9, 41U },
1654 { SP::F10, 42U },
1655 { SP::F11, 43U },
1656 { SP::F12, 44U },
1657 { SP::F13, 45U },
1658 { SP::F14, 46U },
1659 { SP::F15, 47U },
1660 { SP::F16, 48U },
1661 { SP::F17, 49U },
1662 { SP::F18, 50U },
1663 { SP::F19, 51U },
1664 { SP::F20, 52U },
1665 { SP::F21, 53U },
1666 { SP::F22, 54U },
1667 { SP::F23, 55U },
1668 { SP::F24, 56U },
1669 { SP::F25, 57U },
1670 { SP::F26, 58U },
1671 { SP::F27, 59U },
1672 { SP::F28, 60U },
1673 { SP::F29, 61U },
1674 { SP::F30, 62U },
1675 { SP::F31, 63U },
1676 { SP::G0, 0U },
1677 { SP::G1, 1U },
1678 { SP::G2, 2U },
1679 { SP::G3, 3U },
1680 { SP::G4, 4U },
1681 { SP::G5, 5U },
1682 { SP::G6, 6U },
1683 { SP::G7, 7U },
1684 { SP::I0, 24U },
1685 { SP::I1, 25U },
1686 { SP::I2, 26U },
1687 { SP::I3, 27U },
1688 { SP::I4, 28U },
1689 { SP::I5, 29U },
1690 { SP::I6, 30U },
1691 { SP::I7, 31U },
1692 { SP::L0, 16U },
1693 { SP::L1, 17U },
1694 { SP::L2, 18U },
1695 { SP::L3, 19U },
1696 { SP::L4, 20U },
1697 { SP::L5, 21U },
1698 { SP::L6, 22U },
1699 { SP::L7, 23U },
1700 { SP::O0, 8U },
1701 { SP::O1, 9U },
1702 { SP::O2, 10U },
1703 { SP::O3, 11U },
1704 { SP::O4, 12U },
1705 { SP::O5, 13U },
1706 { SP::O6, 14U },
1707 { SP::O7, 15U },
1708};
1709extern const unsigned SPEHFlavour0L2DwarfSize = std::size(SPEHFlavour0L2Dwarf);
1710
1711extern const uint16_t SparcRegEncodingTable[] = {
1712 0,
1713 11,
1714 10,
1715 12,
1716 0,
1717 0,
1718 9,
1719 0,
1720 0,
1721 16,
1722 0,
1723 13,
1724 8,
1725 0,
1726 6,
1727 5,
1728 0,
1729 4,
1730 7,
1731 1,
1732 0,
1733 2,
1734 3,
1735 31,
1736 0,
1737 14,
1738 0,
1739 1,
1740 2,
1741 3,
1742 4,
1743 5,
1744 6,
1745 7,
1746 8,
1747 9,
1748 10,
1749 11,
1750 12,
1751 13,
1752 14,
1753 15,
1754 16,
1755 17,
1756 18,
1757 19,
1758 20,
1759 21,
1760 22,
1761 23,
1762 24,
1763 25,
1764 26,
1765 27,
1766 28,
1767 29,
1768 30,
1769 31,
1770 0,
1771 1,
1772 2,
1773 3,
1774 4,
1775 5,
1776 6,
1777 7,
1778 8,
1779 9,
1780 10,
1781 11,
1782 12,
1783 13,
1784 14,
1785 15,
1786 16,
1787 17,
1788 18,
1789 19,
1790 20,
1791 21,
1792 22,
1793 23,
1794 24,
1795 25,
1796 26,
1797 27,
1798 28,
1799 29,
1800 30,
1801 31,
1802 0,
1803 2,
1804 4,
1805 6,
1806 8,
1807 10,
1808 12,
1809 14,
1810 16,
1811 18,
1812 20,
1813 22,
1814 24,
1815 26,
1816 28,
1817 30,
1818 1,
1819 3,
1820 5,
1821 7,
1822 9,
1823 11,
1824 13,
1825 15,
1826 17,
1827 19,
1828 21,
1829 23,
1830 25,
1831 27,
1832 29,
1833 31,
1834 0,
1835 1,
1836 2,
1837 3,
1838 4,
1839 5,
1840 6,
1841 7,
1842 8,
1843 9,
1844 10,
1845 11,
1846 12,
1847 13,
1848 14,
1849 15,
1850 16,
1851 17,
1852 18,
1853 19,
1854 20,
1855 21,
1856 22,
1857 23,
1858 24,
1859 25,
1860 26,
1861 27,
1862 28,
1863 29,
1864 30,
1865 31,
1866 0,
1867 1,
1868 2,
1869 3,
1870 0,
1871 1,
1872 2,
1873 3,
1874 4,
1875 5,
1876 6,
1877 7,
1878 24,
1879 25,
1880 26,
1881 27,
1882 28,
1883 29,
1884 30,
1885 31,
1886 16,
1887 17,
1888 18,
1889 19,
1890 20,
1891 21,
1892 22,
1893 23,
1894 8,
1895 9,
1896 10,
1897 11,
1898 12,
1899 13,
1900 14,
1901 15,
1902 0,
1903 4,
1904 8,
1905 12,
1906 16,
1907 20,
1908 24,
1909 28,
1910 1,
1911 5,
1912 9,
1913 13,
1914 17,
1915 21,
1916 25,
1917 29,
1918 0,
1919 2,
1920 4,
1921 6,
1922 8,
1923 10,
1924 12,
1925 14,
1926 16,
1927 18,
1928 20,
1929 22,
1930 24,
1931 26,
1932 28,
1933 30,
1934 0,
1935 2,
1936 4,
1937 6,
1938 24,
1939 26,
1940 28,
1941 30,
1942 16,
1943 18,
1944 20,
1945 22,
1946 8,
1947 10,
1948 12,
1949 14,
1950};
1951static inline void InitSparcMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1952 RI->InitMCRegisterInfo(SparcRegDesc, 238, RA, PC, SparcMCRegisterClasses, 20, SparcRegUnitRoots, 173, SparcRegDiffLists, SparcLaneMaskLists, SparcRegStrings, SparcRegClassStrings, SparcSubRegIdxLists, 7,
1953SparcRegEncodingTable);
1954
1955 switch (DwarfFlavour) {
1956 default:
1957 llvm_unreachable("Unknown DWARF flavour");
1958 case 0:
1959 RI->mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
1960 break;
1961 }
1962 switch (EHFlavour) {
1963 default:
1964 llvm_unreachable("Unknown DWARF flavour");
1965 case 0:
1966 RI->mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
1967 break;
1968 }
1969 switch (DwarfFlavour) {
1970 default:
1971 llvm_unreachable("Unknown DWARF flavour");
1972 case 0:
1973 RI->mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
1974 break;
1975 }
1976 switch (EHFlavour) {
1977 default:
1978 llvm_unreachable("Unknown DWARF flavour");
1979 case 0:
1980 RI->mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
1981 break;
1982 }
1983}
1984
1985} // end namespace llvm
1986
1987#endif // GET_REGINFO_MC_DESC
1988
1989/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1990|* *|
1991|* Register Information Header Fragment *|
1992|* *|
1993|* Automatically generated file, do not edit! *|
1994|* *|
1995\*===----------------------------------------------------------------------===*/
1996
1997
1998#ifdef GET_REGINFO_HEADER
1999#undef GET_REGINFO_HEADER
2000
2001#include "llvm/CodeGen/TargetRegisterInfo.h"
2002
2003namespace llvm {
2004
2005class SparcFrameLowering;
2006
2007struct SparcGenRegisterInfo : public TargetRegisterInfo {
2008 explicit SparcGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
2009 unsigned PC = 0, unsigned HwMode = 0);
2010 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
2011 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
2012 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2013 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2014 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
2015 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
2016 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
2017 unsigned getRegUnitWeight(unsigned RegUnit) const override;
2018 unsigned getNumRegPressureSets() const override;
2019 const char *getRegPressureSetName(unsigned Idx) const override;
2020 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
2021 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
2022 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
2023 ArrayRef<const char *> getRegMaskNames() const override;
2024 ArrayRef<const uint32_t *> getRegMasks() const override;
2025 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
2026 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
2027 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
2028 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
2029 bool isConstantPhysReg(MCRegister PhysReg) const override final;
2030 /// Devirtualized TargetFrameLowering.
2031 static const SparcFrameLowering *getFrameLowering(
2032 const MachineFunction &MF);
2033};
2034
2035namespace SP { // Register classes
2036 extern const TargetRegisterClass FCCRegsRegClass;
2037 extern const TargetRegisterClass ASRRegsRegClass;
2038 extern const TargetRegisterClass CoprocRegsRegClass;
2039 extern const TargetRegisterClass FPRegsRegClass;
2040 extern const TargetRegisterClass IntRegsRegClass;
2041 extern const TargetRegisterClass GPRIncomingArgRegClass;
2042 extern const TargetRegisterClass GPROutgoingArgRegClass;
2043 extern const TargetRegisterClass DFPRegsRegClass;
2044 extern const TargetRegisterClass I64RegsRegClass;
2045 extern const TargetRegisterClass PRRegsRegClass;
2046 extern const TargetRegisterClass CoprocPairRegClass;
2047 extern const TargetRegisterClass IntPairRegClass;
2048 extern const TargetRegisterClass LowDFPRegsRegClass;
2049 extern const TargetRegisterClass I64Regs_and_GPRIncomingArgRegClass;
2050 extern const TargetRegisterClass I64Regs_and_GPROutgoingArgRegClass;
2051 extern const TargetRegisterClass IntPair_with_sub_even_in_GPRIncomingArgRegClass;
2052 extern const TargetRegisterClass IntPair_with_sub_even_in_GPROutgoingArgRegClass;
2053 extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass;
2054 extern const TargetRegisterClass QFPRegsRegClass;
2055 extern const TargetRegisterClass LowQFPRegsRegClass;
2056} // end namespace SP
2057
2058} // end namespace llvm
2059
2060#endif // GET_REGINFO_HEADER
2061
2062/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2063|* *|
2064|* Target Register and Register Classes Information *|
2065|* *|
2066|* Automatically generated file, do not edit! *|
2067|* *|
2068\*===----------------------------------------------------------------------===*/
2069
2070
2071#ifdef GET_REGINFO_TARGET_DESC
2072#undef GET_REGINFO_TARGET_DESC
2073
2074namespace llvm {
2075
2076extern const MCRegisterClass SparcMCRegisterClasses[];
2077
2078static const MVT::SimpleValueType VTLists[] = {
2079 /* 0 */ MVT::i1, MVT::Other,
2080 /* 2 */ MVT::i32, MVT::Other,
2081 /* 4 */ MVT::i32, MVT::i64, MVT::Other,
2082 /* 7 */ MVT::f32, MVT::Other,
2083 /* 9 */ MVT::f64, MVT::Other,
2084 /* 11 */ MVT::f128, MVT::Other,
2085 /* 13 */ MVT::v2i32, MVT::Other,
2086};
2087
2088static const char *SubRegIndexNameTable[] = { "sub_even", "sub_even64", "sub_odd", "sub_odd64", "sub_odd64_then_sub_even", "sub_odd64_then_sub_odd", "" };
2089
2090static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
2091 { 65535, 65535 },
2092 { 0, 32 }, // sub_even
2093 { 0, 64 }, // sub_even64
2094 { 32, 32 }, // sub_odd
2095 { 64, 64 }, // sub_odd64
2096 { 64, 32 }, // sub_odd64_then_sub_even
2097 { 96, 32 }, // sub_odd64_then_sub_odd
2098};
2099
2100
2101static const LaneBitmask SubRegIndexLaneMaskTable[] = {
2102 LaneBitmask::getAll(),
2103 LaneBitmask(0x0000000000000001), // sub_even
2104 LaneBitmask(0x0000000000000003), // sub_even64
2105 LaneBitmask(0x0000000000000002), // sub_odd
2106 LaneBitmask(0x000000000000000C), // sub_odd64
2107 LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
2108 LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
2109 };
2110
2111
2112
2113static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
2114 // Mode = 0 (Default)
2115 { 1, 1, 1, /*VTLists+*/0 }, // FCCRegs
2116 { 32, 32, 32, /*VTLists+*/2 }, // ASRRegs
2117 { 32, 32, 32, /*VTLists+*/2 }, // CoprocRegs
2118 { 32, 32, 32, /*VTLists+*/7 }, // FPRegs
2119 { 32, 32, 32, /*VTLists+*/4 }, // IntRegs
2120 { 32, 32, 32, /*VTLists+*/4 }, // GPRIncomingArg
2121 { 32, 32, 32, /*VTLists+*/4 }, // GPROutgoingArg
2122 { 64, 64, 64, /*VTLists+*/9 }, // DFPRegs
2123 { 64, 64, 64, /*VTLists+*/5 }, // I64Regs
2124 { 64, 64, 64, /*VTLists+*/5 }, // PRRegs
2125 { 64, 64, 64, /*VTLists+*/13 }, // CoprocPair
2126 { 64, 64, 64, /*VTLists+*/13 }, // IntPair
2127 { 64, 64, 64, /*VTLists+*/9 }, // LowDFPRegs
2128 { 64, 64, 64, /*VTLists+*/5 }, // I64Regs_and_GPRIncomingArg
2129 { 64, 64, 64, /*VTLists+*/5 }, // I64Regs_and_GPROutgoingArg
2130 { 64, 64, 64, /*VTLists+*/13 }, // IntPair_with_sub_even_in_GPRIncomingArg
2131 { 64, 64, 64, /*VTLists+*/13 }, // IntPair_with_sub_even_in_GPROutgoingArg
2132 { 64, 64, 64, /*VTLists+*/5 }, // PRRegs_and_ASRRegs
2133 { 128, 128, 128, /*VTLists+*/11 }, // QFPRegs
2134 { 128, 128, 128, /*VTLists+*/11 }, // LowQFPRegs
2135};
2136static const uint32_t FCCRegsSubClassMask[] = {
2137 0x00000001,
2138};
2139
2140static const uint32_t ASRRegsSubClassMask[] = {
2141 0x00020002,
2142};
2143
2144static const uint32_t CoprocRegsSubClassMask[] = {
2145 0x00000004,
2146 0x00000400, // sub_even
2147 0x00000400, // sub_odd
2148};
2149
2150static const uint32_t FPRegsSubClassMask[] = {
2151 0x00000008,
2152 0x00081000, // sub_even
2153 0x00081000, // sub_odd
2154 0x00080000, // sub_odd64_then_sub_even
2155 0x00080000, // sub_odd64_then_sub_odd
2156};
2157
2158static const uint32_t IntRegsSubClassMask[] = {
2159 0x00006170,
2160 0x00018800, // sub_even
2161 0x00018800, // sub_odd
2162};
2163
2164static const uint32_t GPRIncomingArgSubClassMask[] = {
2165 0x00002020,
2166 0x00008000, // sub_even
2167 0x00008000, // sub_odd
2168};
2169
2170static const uint32_t GPROutgoingArgSubClassMask[] = {
2171 0x00004040,
2172 0x00010000, // sub_even
2173 0x00010000, // sub_odd
2174};
2175
2176static const uint32_t DFPRegsSubClassMask[] = {
2177 0x00001080,
2178 0x000c0000, // sub_even64
2179 0x000c0000, // sub_odd64
2180};
2181
2182static const uint32_t I64RegsSubClassMask[] = {
2183 0x00006100,
2184 0x00018800, // sub_even
2185 0x00018800, // sub_odd
2186};
2187
2188static const uint32_t PRRegsSubClassMask[] = {
2189 0x00020200,
2190};
2191
2192static const uint32_t CoprocPairSubClassMask[] = {
2193 0x00000400,
2194};
2195
2196static const uint32_t IntPairSubClassMask[] = {
2197 0x00018800,
2198};
2199
2200static const uint32_t LowDFPRegsSubClassMask[] = {
2201 0x00001000,
2202 0x00080000, // sub_even64
2203 0x00080000, // sub_odd64
2204};
2205
2206static const uint32_t I64Regs_and_GPRIncomingArgSubClassMask[] = {
2207 0x00002000,
2208 0x00008000, // sub_even
2209 0x00008000, // sub_odd
2210};
2211
2212static const uint32_t I64Regs_and_GPROutgoingArgSubClassMask[] = {
2213 0x00004000,
2214 0x00010000, // sub_even
2215 0x00010000, // sub_odd
2216};
2217
2218static const uint32_t IntPair_with_sub_even_in_GPRIncomingArgSubClassMask[] = {
2219 0x00008000,
2220};
2221
2222static const uint32_t IntPair_with_sub_even_in_GPROutgoingArgSubClassMask[] = {
2223 0x00010000,
2224};
2225
2226static const uint32_t PRRegs_and_ASRRegsSubClassMask[] = {
2227 0x00020000,
2228};
2229
2230static const uint32_t QFPRegsSubClassMask[] = {
2231 0x000c0000,
2232};
2233
2234static const uint32_t LowQFPRegsSubClassMask[] = {
2235 0x00080000,
2236};
2237
2238static const uint16_t SuperRegIdxSeqs[] = {
2239 /* 0 */ 1, 3, 0,
2240 /* 3 */ 2, 4, 0,
2241 /* 6 */ 1, 3, 5, 6, 0,
2242};
2243
2244static unsigned const GPRIncomingArgSuperclasses[] = {
2245 SP::IntRegsRegClassID,
2246};
2247
2248static unsigned const GPROutgoingArgSuperclasses[] = {
2249 SP::IntRegsRegClassID,
2250};
2251
2252static unsigned const I64RegsSuperclasses[] = {
2253 SP::IntRegsRegClassID,
2254};
2255
2256static unsigned const LowDFPRegsSuperclasses[] = {
2257 SP::DFPRegsRegClassID,
2258};
2259
2260static unsigned const I64Regs_and_GPRIncomingArgSuperclasses[] = {
2261 SP::IntRegsRegClassID,
2262 SP::GPRIncomingArgRegClassID,
2263 SP::I64RegsRegClassID,
2264};
2265
2266static unsigned const I64Regs_and_GPROutgoingArgSuperclasses[] = {
2267 SP::IntRegsRegClassID,
2268 SP::GPROutgoingArgRegClassID,
2269 SP::I64RegsRegClassID,
2270};
2271
2272static unsigned const IntPair_with_sub_even_in_GPRIncomingArgSuperclasses[] = {
2273 SP::IntPairRegClassID,
2274};
2275
2276static unsigned const IntPair_with_sub_even_in_GPROutgoingArgSuperclasses[] = {
2277 SP::IntPairRegClassID,
2278};
2279
2280static unsigned const PRRegs_and_ASRRegsSuperclasses[] = {
2281 SP::ASRRegsRegClassID,
2282 SP::PRRegsRegClassID,
2283};
2284
2285static unsigned const LowQFPRegsSuperclasses[] = {
2286 SP::QFPRegsRegClassID,
2287};
2288
2289
2290namespace SP { // Register class instances
2291 extern const TargetRegisterClass FCCRegsRegClass = {
2292 &SparcMCRegisterClasses[FCCRegsRegClassID],
2293 FCCRegsSubClassMask,
2294 SuperRegIdxSeqs + 2,
2295 LaneBitmask(0x0000000000000001),
2296 0,
2297 false,
2298 0x00, /* TSFlags */
2299 false, /* HasDisjunctSubRegs */
2300 false, /* CoveredBySubRegs */
2301 nullptr, 0,
2302 nullptr
2303 };
2304
2305 extern const TargetRegisterClass ASRRegsRegClass = {
2306 &SparcMCRegisterClasses[ASRRegsRegClassID],
2307 ASRRegsSubClassMask,
2308 SuperRegIdxSeqs + 2,
2309 LaneBitmask(0x0000000000000001),
2310 0,
2311 false,
2312 0x00, /* TSFlags */
2313 false, /* HasDisjunctSubRegs */
2314 false, /* CoveredBySubRegs */
2315 nullptr, 0,
2316 nullptr
2317 };
2318
2319 extern const TargetRegisterClass CoprocRegsRegClass = {
2320 &SparcMCRegisterClasses[CoprocRegsRegClassID],
2321 CoprocRegsSubClassMask,
2322 SuperRegIdxSeqs + 0,
2323 LaneBitmask(0x0000000000000001),
2324 0,
2325 false,
2326 0x00, /* TSFlags */
2327 false, /* HasDisjunctSubRegs */
2328 false, /* CoveredBySubRegs */
2329 nullptr, 0,
2330 nullptr
2331 };
2332
2333 extern const TargetRegisterClass FPRegsRegClass = {
2334 &SparcMCRegisterClasses[FPRegsRegClassID],
2335 FPRegsSubClassMask,
2336 SuperRegIdxSeqs + 6,
2337 LaneBitmask(0x0000000000000001),
2338 0,
2339 false,
2340 0x00, /* TSFlags */
2341 false, /* HasDisjunctSubRegs */
2342 false, /* CoveredBySubRegs */
2343 nullptr, 0,
2344 nullptr
2345 };
2346
2347 extern const TargetRegisterClass IntRegsRegClass = {
2348 &SparcMCRegisterClasses[IntRegsRegClassID],
2349 IntRegsSubClassMask,
2350 SuperRegIdxSeqs + 0,
2351 LaneBitmask(0x0000000000000001),
2352 0,
2353 false,
2354 0x00, /* TSFlags */
2355 false, /* HasDisjunctSubRegs */
2356 false, /* CoveredBySubRegs */
2357 nullptr, 0,
2358 nullptr
2359 };
2360
2361 extern const TargetRegisterClass GPRIncomingArgRegClass = {
2362 &SparcMCRegisterClasses[GPRIncomingArgRegClassID],
2363 GPRIncomingArgSubClassMask,
2364 SuperRegIdxSeqs + 0,
2365 LaneBitmask(0x0000000000000001),
2366 0,
2367 false,
2368 0x00, /* TSFlags */
2369 false, /* HasDisjunctSubRegs */
2370 false, /* CoveredBySubRegs */
2371 GPRIncomingArgSuperclasses, 1,
2372 nullptr
2373 };
2374
2375 extern const TargetRegisterClass GPROutgoingArgRegClass = {
2376 &SparcMCRegisterClasses[GPROutgoingArgRegClassID],
2377 GPROutgoingArgSubClassMask,
2378 SuperRegIdxSeqs + 0,
2379 LaneBitmask(0x0000000000000001),
2380 0,
2381 false,
2382 0x00, /* TSFlags */
2383 false, /* HasDisjunctSubRegs */
2384 false, /* CoveredBySubRegs */
2385 GPROutgoingArgSuperclasses, 1,
2386 nullptr
2387 };
2388
2389 extern const TargetRegisterClass DFPRegsRegClass = {
2390 &SparcMCRegisterClasses[DFPRegsRegClassID],
2391 DFPRegsSubClassMask,
2392 SuperRegIdxSeqs + 3,
2393 LaneBitmask(0x0000000000000003),
2394 0,
2395 false,
2396 0x00, /* TSFlags */
2397 true, /* HasDisjunctSubRegs */
2398 false, /* CoveredBySubRegs */
2399 nullptr, 0,
2400 nullptr
2401 };
2402
2403 extern const TargetRegisterClass I64RegsRegClass = {
2404 &SparcMCRegisterClasses[I64RegsRegClassID],
2405 I64RegsSubClassMask,
2406 SuperRegIdxSeqs + 0,
2407 LaneBitmask(0x0000000000000001),
2408 0,
2409 false,
2410 0x00, /* TSFlags */
2411 false, /* HasDisjunctSubRegs */
2412 false, /* CoveredBySubRegs */
2413 I64RegsSuperclasses, 1,
2414 nullptr
2415 };
2416
2417 extern const TargetRegisterClass PRRegsRegClass = {
2418 &SparcMCRegisterClasses[PRRegsRegClassID],
2419 PRRegsSubClassMask,
2420 SuperRegIdxSeqs + 2,
2421 LaneBitmask(0x0000000000000001),
2422 0,
2423 false,
2424 0x00, /* TSFlags */
2425 false, /* HasDisjunctSubRegs */
2426 false, /* CoveredBySubRegs */
2427 nullptr, 0,
2428 nullptr
2429 };
2430
2431 extern const TargetRegisterClass CoprocPairRegClass = {
2432 &SparcMCRegisterClasses[CoprocPairRegClassID],
2433 CoprocPairSubClassMask,
2434 SuperRegIdxSeqs + 2,
2435 LaneBitmask(0x0000000000000003),
2436 0,
2437 false,
2438 0x00, /* TSFlags */
2439 true, /* HasDisjunctSubRegs */
2440 true, /* CoveredBySubRegs */
2441 nullptr, 0,
2442 nullptr
2443 };
2444
2445 extern const TargetRegisterClass IntPairRegClass = {
2446 &SparcMCRegisterClasses[IntPairRegClassID],
2447 IntPairSubClassMask,
2448 SuperRegIdxSeqs + 2,
2449 LaneBitmask(0x0000000000000003),
2450 0,
2451 false,
2452 0x00, /* TSFlags */
2453 true, /* HasDisjunctSubRegs */
2454 true, /* CoveredBySubRegs */
2455 nullptr, 0,
2456 nullptr
2457 };
2458
2459 extern const TargetRegisterClass LowDFPRegsRegClass = {
2460 &SparcMCRegisterClasses[LowDFPRegsRegClassID],
2461 LowDFPRegsSubClassMask,
2462 SuperRegIdxSeqs + 3,
2463 LaneBitmask(0x0000000000000003),
2464 0,
2465 false,
2466 0x00, /* TSFlags */
2467 true, /* HasDisjunctSubRegs */
2468 true, /* CoveredBySubRegs */
2469 LowDFPRegsSuperclasses, 1,
2470 nullptr
2471 };
2472
2473 extern const TargetRegisterClass I64Regs_and_GPRIncomingArgRegClass = {
2474 &SparcMCRegisterClasses[I64Regs_and_GPRIncomingArgRegClassID],
2475 I64Regs_and_GPRIncomingArgSubClassMask,
2476 SuperRegIdxSeqs + 0,
2477 LaneBitmask(0x0000000000000001),
2478 0,
2479 false,
2480 0x00, /* TSFlags */
2481 false, /* HasDisjunctSubRegs */
2482 false, /* CoveredBySubRegs */
2483 I64Regs_and_GPRIncomingArgSuperclasses, 3,
2484 nullptr
2485 };
2486
2487 extern const TargetRegisterClass I64Regs_and_GPROutgoingArgRegClass = {
2488 &SparcMCRegisterClasses[I64Regs_and_GPROutgoingArgRegClassID],
2489 I64Regs_and_GPROutgoingArgSubClassMask,
2490 SuperRegIdxSeqs + 0,
2491 LaneBitmask(0x0000000000000001),
2492 0,
2493 false,
2494 0x00, /* TSFlags */
2495 false, /* HasDisjunctSubRegs */
2496 false, /* CoveredBySubRegs */
2497 I64Regs_and_GPROutgoingArgSuperclasses, 3,
2498 nullptr
2499 };
2500
2501 extern const TargetRegisterClass IntPair_with_sub_even_in_GPRIncomingArgRegClass = {
2502 &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPRIncomingArgRegClassID],
2503 IntPair_with_sub_even_in_GPRIncomingArgSubClassMask,
2504 SuperRegIdxSeqs + 2,
2505 LaneBitmask(0x0000000000000003),
2506 0,
2507 false,
2508 0x00, /* TSFlags */
2509 true, /* HasDisjunctSubRegs */
2510 true, /* CoveredBySubRegs */
2511 IntPair_with_sub_even_in_GPRIncomingArgSuperclasses, 1,
2512 nullptr
2513 };
2514
2515 extern const TargetRegisterClass IntPair_with_sub_even_in_GPROutgoingArgRegClass = {
2516 &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPROutgoingArgRegClassID],
2517 IntPair_with_sub_even_in_GPROutgoingArgSubClassMask,
2518 SuperRegIdxSeqs + 2,
2519 LaneBitmask(0x0000000000000003),
2520 0,
2521 false,
2522 0x00, /* TSFlags */
2523 true, /* HasDisjunctSubRegs */
2524 true, /* CoveredBySubRegs */
2525 IntPair_with_sub_even_in_GPROutgoingArgSuperclasses, 1,
2526 nullptr
2527 };
2528
2529 extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass = {
2530 &SparcMCRegisterClasses[PRRegs_and_ASRRegsRegClassID],
2531 PRRegs_and_ASRRegsSubClassMask,
2532 SuperRegIdxSeqs + 2,
2533 LaneBitmask(0x0000000000000001),
2534 0,
2535 false,
2536 0x00, /* TSFlags */
2537 false, /* HasDisjunctSubRegs */
2538 false, /* CoveredBySubRegs */
2539 PRRegs_and_ASRRegsSuperclasses, 2,
2540 nullptr
2541 };
2542
2543 extern const TargetRegisterClass QFPRegsRegClass = {
2544 &SparcMCRegisterClasses[QFPRegsRegClassID],
2545 QFPRegsSubClassMask,
2546 SuperRegIdxSeqs + 2,
2547 LaneBitmask(0x000000000000000F),
2548 0,
2549 false,
2550 0x00, /* TSFlags */
2551 true, /* HasDisjunctSubRegs */
2552 true, /* CoveredBySubRegs */
2553 nullptr, 0,
2554 nullptr
2555 };
2556
2557 extern const TargetRegisterClass LowQFPRegsRegClass = {
2558 &SparcMCRegisterClasses[LowQFPRegsRegClassID],
2559 LowQFPRegsSubClassMask,
2560 SuperRegIdxSeqs + 2,
2561 LaneBitmask(0x000000000000000F),
2562 0,
2563 false,
2564 0x00, /* TSFlags */
2565 true, /* HasDisjunctSubRegs */
2566 true, /* CoveredBySubRegs */
2567 LowQFPRegsSuperclasses, 1,
2568 nullptr
2569 };
2570
2571} // end namespace SP
2572
2573namespace {
2574 const TargetRegisterClass *const RegisterClasses[] = {
2575 &SP::FCCRegsRegClass,
2576 &SP::ASRRegsRegClass,
2577 &SP::CoprocRegsRegClass,
2578 &SP::FPRegsRegClass,
2579 &SP::IntRegsRegClass,
2580 &SP::GPRIncomingArgRegClass,
2581 &SP::GPROutgoingArgRegClass,
2582 &SP::DFPRegsRegClass,
2583 &SP::I64RegsRegClass,
2584 &SP::PRRegsRegClass,
2585 &SP::CoprocPairRegClass,
2586 &SP::IntPairRegClass,
2587 &SP::LowDFPRegsRegClass,
2588 &SP::I64Regs_and_GPRIncomingArgRegClass,
2589 &SP::I64Regs_and_GPROutgoingArgRegClass,
2590 &SP::IntPair_with_sub_even_in_GPRIncomingArgRegClass,
2591 &SP::IntPair_with_sub_even_in_GPROutgoingArgRegClass,
2592 &SP::PRRegs_and_ASRRegsRegClass,
2593 &SP::QFPRegsRegClass,
2594 &SP::LowQFPRegsRegClass,
2595 };
2596} // end anonymous namespace
2597
2598static const uint8_t CostPerUseTable[] = {
25990, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
2600
2601
2602static const bool InAllocatableClassTable[] = {
2603false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
2604
2605
2606static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
2607CostPerUseTable, 1, InAllocatableClassTable};
2608
2609unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2610 static const uint8_t RowMap[6] = {
2611 0, 0, 0, 1, 0, 0,
2612 };
2613 static const uint8_t Rows[2][6] = {
2614 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
2615 { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
2616 };
2617
2618 --IdxA; assert(IdxA < 6); (void) IdxA;
2619 --IdxB; assert(IdxB < 6);
2620 return Rows[RowMap[IdxA]][IdxB];
2621}
2622
2623unsigned SparcGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2624 static const uint8_t Table[6][6] = {
2625 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
2626 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
2627 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
2628 { 0, 0, 0, 0, SP::sub_even, SP::sub_odd, },
2629 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
2630 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
2631 };
2632
2633 --IdxA; assert(IdxA < 6);
2634 --IdxB; assert(IdxB < 6);
2635 return Table[IdxA][IdxB];
2636 }
2637
2638 struct MaskRolOp {
2639 LaneBitmask Mask;
2640 uint8_t RotateLeft;
2641 };
2642 static const MaskRolOp LaneMaskComposeSequences[] = {
2643 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
2644 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
2645 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
2646 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 } // Sequence 6
2647 };
2648 static const uint8_t CompositeSequences[] = {
2649 0, // to sub_even
2650 0, // to sub_even64
2651 2, // to sub_odd
2652 4, // to sub_odd64
2653 4, // to sub_odd64_then_sub_even
2654 6 // to sub_odd64_then_sub_odd
2655 };
2656
2657LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2658 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2659 LaneBitmask Result;
2660 for (const MaskRolOp *Ops =
2661 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2662 Ops->Mask.any(); ++Ops) {
2663 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2664 if (unsigned S = Ops->RotateLeft)
2665 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
2666 else
2667 Result |= LaneBitmask(M);
2668 }
2669 return Result;
2670}
2671
2672LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2673 LaneMask &= getSubRegIndexLaneMask(IdxA);
2674 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2675 LaneBitmask Result;
2676 for (const MaskRolOp *Ops =
2677 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2678 Ops->Mask.any(); ++Ops) {
2679 LaneBitmask::Type M = LaneMask.getAsInteger();
2680 if (unsigned S = Ops->RotateLeft)
2681 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
2682 else
2683 Result |= LaneBitmask(M);
2684 }
2685 return Result;
2686}
2687
2688const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2689 static const uint8_t Table[20][6] = {
2690 { // FCCRegs
2691 0, // sub_even
2692 0, // sub_even64
2693 0, // sub_odd
2694 0, // sub_odd64
2695 0, // sub_odd64_then_sub_even
2696 0, // sub_odd64_then_sub_odd
2697 },
2698 { // ASRRegs
2699 0, // sub_even
2700 0, // sub_even64
2701 0, // sub_odd
2702 0, // sub_odd64
2703 0, // sub_odd64_then_sub_even
2704 0, // sub_odd64_then_sub_odd
2705 },
2706 { // CoprocRegs
2707 0, // sub_even
2708 0, // sub_even64
2709 0, // sub_odd
2710 0, // sub_odd64
2711 0, // sub_odd64_then_sub_even
2712 0, // sub_odd64_then_sub_odd
2713 },
2714 { // FPRegs
2715 0, // sub_even
2716 0, // sub_even64
2717 0, // sub_odd
2718 0, // sub_odd64
2719 0, // sub_odd64_then_sub_even
2720 0, // sub_odd64_then_sub_odd
2721 },
2722 { // IntRegs
2723 0, // sub_even
2724 0, // sub_even64
2725 0, // sub_odd
2726 0, // sub_odd64
2727 0, // sub_odd64_then_sub_even
2728 0, // sub_odd64_then_sub_odd
2729 },
2730 { // GPRIncomingArg
2731 0, // sub_even
2732 0, // sub_even64
2733 0, // sub_odd
2734 0, // sub_odd64
2735 0, // sub_odd64_then_sub_even
2736 0, // sub_odd64_then_sub_odd
2737 },
2738 { // GPROutgoingArg
2739 0, // sub_even
2740 0, // sub_even64
2741 0, // sub_odd
2742 0, // sub_odd64
2743 0, // sub_odd64_then_sub_even
2744 0, // sub_odd64_then_sub_odd
2745 },
2746 { // DFPRegs
2747 13, // sub_even -> LowDFPRegs
2748 0, // sub_even64
2749 13, // sub_odd -> LowDFPRegs
2750 0, // sub_odd64
2751 0, // sub_odd64_then_sub_even
2752 0, // sub_odd64_then_sub_odd
2753 },
2754 { // I64Regs
2755 0, // sub_even
2756 0, // sub_even64
2757 0, // sub_odd
2758 0, // sub_odd64
2759 0, // sub_odd64_then_sub_even
2760 0, // sub_odd64_then_sub_odd
2761 },
2762 { // PRRegs
2763 0, // sub_even
2764 0, // sub_even64
2765 0, // sub_odd
2766 0, // sub_odd64
2767 0, // sub_odd64_then_sub_even
2768 0, // sub_odd64_then_sub_odd
2769 },
2770 { // CoprocPair
2771 11, // sub_even -> CoprocPair
2772 0, // sub_even64
2773 11, // sub_odd -> CoprocPair
2774 0, // sub_odd64
2775 0, // sub_odd64_then_sub_even
2776 0, // sub_odd64_then_sub_odd
2777 },
2778 { // IntPair
2779 12, // sub_even -> IntPair
2780 0, // sub_even64
2781 12, // sub_odd -> IntPair
2782 0, // sub_odd64
2783 0, // sub_odd64_then_sub_even
2784 0, // sub_odd64_then_sub_odd
2785 },
2786 { // LowDFPRegs
2787 13, // sub_even -> LowDFPRegs
2788 0, // sub_even64
2789 13, // sub_odd -> LowDFPRegs
2790 0, // sub_odd64
2791 0, // sub_odd64_then_sub_even
2792 0, // sub_odd64_then_sub_odd
2793 },
2794 { // I64Regs_and_GPRIncomingArg
2795 0, // sub_even
2796 0, // sub_even64
2797 0, // sub_odd
2798 0, // sub_odd64
2799 0, // sub_odd64_then_sub_even
2800 0, // sub_odd64_then_sub_odd
2801 },
2802 { // I64Regs_and_GPROutgoingArg
2803 0, // sub_even
2804 0, // sub_even64
2805 0, // sub_odd
2806 0, // sub_odd64
2807 0, // sub_odd64_then_sub_even
2808 0, // sub_odd64_then_sub_odd
2809 },
2810 { // IntPair_with_sub_even_in_GPRIncomingArg
2811 16, // sub_even -> IntPair_with_sub_even_in_GPRIncomingArg
2812 0, // sub_even64
2813 16, // sub_odd -> IntPair_with_sub_even_in_GPRIncomingArg
2814 0, // sub_odd64
2815 0, // sub_odd64_then_sub_even
2816 0, // sub_odd64_then_sub_odd
2817 },
2818 { // IntPair_with_sub_even_in_GPROutgoingArg
2819 17, // sub_even -> IntPair_with_sub_even_in_GPROutgoingArg
2820 0, // sub_even64
2821 17, // sub_odd -> IntPair_with_sub_even_in_GPROutgoingArg
2822 0, // sub_odd64
2823 0, // sub_odd64_then_sub_even
2824 0, // sub_odd64_then_sub_odd
2825 },
2826 { // PRRegs_and_ASRRegs
2827 0, // sub_even
2828 0, // sub_even64
2829 0, // sub_odd
2830 0, // sub_odd64
2831 0, // sub_odd64_then_sub_even
2832 0, // sub_odd64_then_sub_odd
2833 },
2834 { // QFPRegs
2835 20, // sub_even -> LowQFPRegs
2836 19, // sub_even64 -> QFPRegs
2837 20, // sub_odd -> LowQFPRegs
2838 19, // sub_odd64 -> QFPRegs
2839 20, // sub_odd64_then_sub_even -> LowQFPRegs
2840 20, // sub_odd64_then_sub_odd -> LowQFPRegs
2841 },
2842 { // LowQFPRegs
2843 20, // sub_even -> LowQFPRegs
2844 20, // sub_even64 -> LowQFPRegs
2845 20, // sub_odd -> LowQFPRegs
2846 20, // sub_odd64 -> LowQFPRegs
2847 20, // sub_odd64_then_sub_even -> LowQFPRegs
2848 20, // sub_odd64_then_sub_odd -> LowQFPRegs
2849 },
2850 };
2851 assert(RC && "Missing regclass");
2852 if (!Idx) return RC;
2853 --Idx;
2854 assert(Idx < 6 && "Bad subreg");
2855 unsigned TV = Table[RC->getID()][Idx];
2856 return TV ? getRegClass(TV - 1) : nullptr;
2857}
2858
2859const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
2860 static const uint8_t Table[20][6] = {
2861 { // FCCRegs
2862 0, // FCCRegs:sub_even
2863 0, // FCCRegs:sub_even64
2864 0, // FCCRegs:sub_odd
2865 0, // FCCRegs:sub_odd64
2866 0, // FCCRegs:sub_odd64_then_sub_even
2867 0, // FCCRegs:sub_odd64_then_sub_odd
2868 },
2869 { // ASRRegs
2870 0, // ASRRegs:sub_even
2871 0, // ASRRegs:sub_even64
2872 0, // ASRRegs:sub_odd
2873 0, // ASRRegs:sub_odd64
2874 0, // ASRRegs:sub_odd64_then_sub_even
2875 0, // ASRRegs:sub_odd64_then_sub_odd
2876 },
2877 { // CoprocRegs
2878 0, // CoprocRegs:sub_even
2879 0, // CoprocRegs:sub_even64
2880 0, // CoprocRegs:sub_odd
2881 0, // CoprocRegs:sub_odd64
2882 0, // CoprocRegs:sub_odd64_then_sub_even
2883 0, // CoprocRegs:sub_odd64_then_sub_odd
2884 },
2885 { // FPRegs
2886 0, // FPRegs:sub_even
2887 0, // FPRegs:sub_even64
2888 0, // FPRegs:sub_odd
2889 0, // FPRegs:sub_odd64
2890 0, // FPRegs:sub_odd64_then_sub_even
2891 0, // FPRegs:sub_odd64_then_sub_odd
2892 },
2893 { // IntRegs
2894 0, // IntRegs:sub_even
2895 0, // IntRegs:sub_even64
2896 0, // IntRegs:sub_odd
2897 0, // IntRegs:sub_odd64
2898 0, // IntRegs:sub_odd64_then_sub_even
2899 0, // IntRegs:sub_odd64_then_sub_odd
2900 },
2901 { // GPRIncomingArg
2902 0, // GPRIncomingArg:sub_even
2903 0, // GPRIncomingArg:sub_even64
2904 0, // GPRIncomingArg:sub_odd
2905 0, // GPRIncomingArg:sub_odd64
2906 0, // GPRIncomingArg:sub_odd64_then_sub_even
2907 0, // GPRIncomingArg:sub_odd64_then_sub_odd
2908 },
2909 { // GPROutgoingArg
2910 0, // GPROutgoingArg:sub_even
2911 0, // GPROutgoingArg:sub_even64
2912 0, // GPROutgoingArg:sub_odd
2913 0, // GPROutgoingArg:sub_odd64
2914 0, // GPROutgoingArg:sub_odd64_then_sub_even
2915 0, // GPROutgoingArg:sub_odd64_then_sub_odd
2916 },
2917 { // DFPRegs
2918 4, // DFPRegs:sub_even -> FPRegs
2919 0, // DFPRegs:sub_even64
2920 4, // DFPRegs:sub_odd -> FPRegs
2921 0, // DFPRegs:sub_odd64
2922 0, // DFPRegs:sub_odd64_then_sub_even
2923 0, // DFPRegs:sub_odd64_then_sub_odd
2924 },
2925 { // I64Regs
2926 0, // I64Regs:sub_even
2927 0, // I64Regs:sub_even64
2928 0, // I64Regs:sub_odd
2929 0, // I64Regs:sub_odd64
2930 0, // I64Regs:sub_odd64_then_sub_even
2931 0, // I64Regs:sub_odd64_then_sub_odd
2932 },
2933 { // PRRegs
2934 0, // PRRegs:sub_even
2935 0, // PRRegs:sub_even64
2936 0, // PRRegs:sub_odd
2937 0, // PRRegs:sub_odd64
2938 0, // PRRegs:sub_odd64_then_sub_even
2939 0, // PRRegs:sub_odd64_then_sub_odd
2940 },
2941 { // CoprocPair
2942 3, // CoprocPair:sub_even -> CoprocRegs
2943 0, // CoprocPair:sub_even64
2944 3, // CoprocPair:sub_odd -> CoprocRegs
2945 0, // CoprocPair:sub_odd64
2946 0, // CoprocPair:sub_odd64_then_sub_even
2947 0, // CoprocPair:sub_odd64_then_sub_odd
2948 },
2949 { // IntPair
2950 9, // IntPair:sub_even -> I64Regs
2951 0, // IntPair:sub_even64
2952 9, // IntPair:sub_odd -> I64Regs
2953 0, // IntPair:sub_odd64
2954 0, // IntPair:sub_odd64_then_sub_even
2955 0, // IntPair:sub_odd64_then_sub_odd
2956 },
2957 { // LowDFPRegs
2958 4, // LowDFPRegs:sub_even -> FPRegs
2959 0, // LowDFPRegs:sub_even64
2960 4, // LowDFPRegs:sub_odd -> FPRegs
2961 0, // LowDFPRegs:sub_odd64
2962 0, // LowDFPRegs:sub_odd64_then_sub_even
2963 0, // LowDFPRegs:sub_odd64_then_sub_odd
2964 },
2965 { // I64Regs_and_GPRIncomingArg
2966 0, // I64Regs_and_GPRIncomingArg:sub_even
2967 0, // I64Regs_and_GPRIncomingArg:sub_even64
2968 0, // I64Regs_and_GPRIncomingArg:sub_odd
2969 0, // I64Regs_and_GPRIncomingArg:sub_odd64
2970 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_even
2971 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_odd
2972 },
2973 { // I64Regs_and_GPROutgoingArg
2974 0, // I64Regs_and_GPROutgoingArg:sub_even
2975 0, // I64Regs_and_GPROutgoingArg:sub_even64
2976 0, // I64Regs_and_GPROutgoingArg:sub_odd
2977 0, // I64Regs_and_GPROutgoingArg:sub_odd64
2978 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_even
2979 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_odd
2980 },
2981 { // IntPair_with_sub_even_in_GPRIncomingArg
2982 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even -> I64Regs_and_GPRIncomingArg
2983 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even64
2984 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd -> I64Regs_and_GPRIncomingArg
2985 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64
2986 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_even
2987 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_odd
2988 },
2989 { // IntPair_with_sub_even_in_GPROutgoingArg
2990 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even -> I64Regs_and_GPROutgoingArg
2991 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even64
2992 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd -> I64Regs_and_GPROutgoingArg
2993 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64
2994 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_even
2995 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_odd
2996 },
2997 { // PRRegs_and_ASRRegs
2998 0, // PRRegs_and_ASRRegs:sub_even
2999 0, // PRRegs_and_ASRRegs:sub_even64
3000 0, // PRRegs_and_ASRRegs:sub_odd
3001 0, // PRRegs_and_ASRRegs:sub_odd64
3002 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
3003 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
3004 },
3005 { // QFPRegs
3006 4, // QFPRegs:sub_even -> FPRegs
3007 8, // QFPRegs:sub_even64 -> DFPRegs
3008 4, // QFPRegs:sub_odd -> FPRegs
3009 8, // QFPRegs:sub_odd64 -> DFPRegs
3010 4, // QFPRegs:sub_odd64_then_sub_even -> FPRegs
3011 4, // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
3012 },
3013 { // LowQFPRegs
3014 4, // LowQFPRegs:sub_even -> FPRegs
3015 13, // LowQFPRegs:sub_even64 -> LowDFPRegs
3016 4, // LowQFPRegs:sub_odd -> FPRegs
3017 13, // LowQFPRegs:sub_odd64 -> LowDFPRegs
3018 4, // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
3019 4, // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
3020 },
3021 };
3022 assert(RC && "Missing regclass");
3023 if (!Idx) return RC;
3024 --Idx;
3025 assert(Idx < 6 && "Bad subreg");
3026 unsigned TV = Table[RC->getID()][Idx];
3027 return TV ? getRegClass(TV - 1) : nullptr;
3028}
3029
3030/// Get the weight in units of pressure for this register class.
3031const RegClassWeight &SparcGenRegisterInfo::
3032getRegClassWeight(const TargetRegisterClass *RC) const {
3033 static const RegClassWeight RCWeightTable[] = {
3034 {1, 4}, // FCCRegs
3035 {1, 1}, // ASRRegs
3036 {0, 0}, // CoprocRegs
3037 {1, 32}, // FPRegs
3038 {1, 32}, // IntRegs
3039 {1, 6}, // GPRIncomingArg
3040 {1, 6}, // GPROutgoingArg
3041 {2, 64}, // DFPRegs
3042 {1, 32}, // I64Regs
3043 {1, 17}, // PRRegs
3044 {0, 0}, // CoprocPair
3045 {2, 32}, // IntPair
3046 {2, 32}, // LowDFPRegs
3047 {1, 6}, // I64Regs_and_GPRIncomingArg
3048 {1, 6}, // I64Regs_and_GPROutgoingArg
3049 {2, 6}, // IntPair_with_sub_even_in_GPRIncomingArg
3050 {2, 6}, // IntPair_with_sub_even_in_GPROutgoingArg
3051 {1, 1}, // PRRegs_and_ASRRegs
3052 {4, 64}, // QFPRegs
3053 {4, 32}, // LowQFPRegs
3054 };
3055 return RCWeightTable[RC->getID()];
3056}
3057
3058/// Get the weight in units of pressure for this register unit.
3059unsigned SparcGenRegisterInfo::
3060getRegUnitWeight(unsigned RegUnit) const {
3061 assert(RegUnit < 173 && "invalid register unit");
3062 static const uint8_t RUWeightTable[] = {
3063 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
3064 return RUWeightTable[RegUnit];
3065}
3066
3067
3068// Get the number of dimensions of register pressure.
3069unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
3070 return 8;
3071}
3072
3073// Get the name of this register unit pressure set.
3074const char *SparcGenRegisterInfo::
3075getRegPressureSetName(unsigned Idx) const {
3076 static const char *PressureNameTable[] = {
3077 "PRRegs_and_ASRRegs",
3078 "FCCRegs",
3079 "GPRIncomingArg",
3080 "GPROutgoingArg",
3081 "PRRegs",
3082 "FPRegs",
3083 "IntRegs",
3084 "DFPRegs",
3085 };
3086 return PressureNameTable[Idx];
3087}
3088
3089// Get the register unit pressure limit for this dimension.
3090// This limit must be adjusted dynamically for reserved registers.
3091unsigned SparcGenRegisterInfo::
3092getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3093 static const uint8_t PressureLimitTable[] = {
3094 1, // 0: PRRegs_and_ASRRegs
3095 4, // 1: FCCRegs
3096 6, // 2: GPRIncomingArg
3097 6, // 3: GPROutgoingArg
3098 17, // 4: PRRegs
3099 32, // 5: FPRegs
3100 32, // 6: IntRegs
3101 64, // 7: DFPRegs
3102 };
3103 return PressureLimitTable[Idx];
3104}
3105
3106/// Table of pressure sets per register class or unit.
3107static const int RCSetsTable[] = {
3108 /* 0 */ 1, -1,
3109 /* 2 */ 0, 4, -1,
3110 /* 5 */ 2, 6, -1,
3111 /* 8 */ 3, 6, -1,
3112 /* 11 */ 5, 7, -1,
3113};
3114
3115/// Get the dimensions of register pressure impacted by this register class.
3116/// Returns a -1 terminated array of pressure set IDs
3117const int *SparcGenRegisterInfo::
3118getRegClassPressureSets(const TargetRegisterClass *RC) const {
3119 static const uint8_t RCSetStartTable[] = {
3120 0,1,1,11,6,5,8,12,6,3,1,6,11,5,8,5,8,2,12,11,};
3121 return &RCSetsTable[RCSetStartTable[RC->getID()]];
3122}
3123
3124/// Get the dimensions of register pressure impacted by this register unit.
3125/// Returns a -1 terminated array of pressure set IDs
3126const int *SparcGenRegisterInfo::
3127getRegUnitPressureSets(unsigned RegUnit) const {
3128 assert(RegUnit < 173 && "invalid register unit");
3129 static const uint8_t RUSetStartTable[] = {
3130 3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,0,0,0,0,6,6,6,6,6,6,6,6,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,6,6,};
3131 return &RCSetsTable[RUSetStartTable[RegUnit]];
3132}
3133
3134extern const MCRegisterDesc SparcRegDesc[];
3135extern const int16_t SparcRegDiffLists[];
3136extern const LaneBitmask SparcLaneMaskLists[];
3137extern const char SparcRegStrings[];
3138extern const char SparcRegClassStrings[];
3139extern const MCPhysReg SparcRegUnitRoots[][2];
3140extern const uint16_t SparcSubRegIdxLists[];
3141extern const uint16_t SparcRegEncodingTable[];
3142// SP Dwarf<->LLVM register mappings.
3143extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
3144extern const unsigned SPDwarfFlavour0Dwarf2LSize;
3145
3146extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
3147extern const unsigned SPEHFlavour0Dwarf2LSize;
3148
3149extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
3150extern const unsigned SPDwarfFlavour0L2DwarfSize;
3151
3152extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
3153extern const unsigned SPEHFlavour0L2DwarfSize;
3154
3155SparcGenRegisterInfo::
3156SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3157 unsigned PC, unsigned HwMode)
3158 : TargetRegisterInfo(&SparcRegInfoDesc, RegisterClasses, RegisterClasses+20,
3159 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
3160 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
3161 InitMCRegisterInfo(SparcRegDesc, 238, RA, PC,
3162 SparcMCRegisterClasses, 20,
3163 SparcRegUnitRoots,
3164 173,
3165 SparcRegDiffLists,
3166 SparcLaneMaskLists,
3167 SparcRegStrings,
3168 SparcRegClassStrings,
3169 SparcSubRegIdxLists,
3170 7,
3171 SparcRegEncodingTable);
3172
3173 switch (DwarfFlavour) {
3174 default:
3175 llvm_unreachable("Unknown DWARF flavour");
3176 case 0:
3177 mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
3178 break;
3179 }
3180 switch (EHFlavour) {
3181 default:
3182 llvm_unreachable("Unknown DWARF flavour");
3183 case 0:
3184 mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
3185 break;
3186 }
3187 switch (DwarfFlavour) {
3188 default:
3189 llvm_unreachable("Unknown DWARF flavour");
3190 case 0:
3191 mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
3192 break;
3193 }
3194 switch (EHFlavour) {
3195 default:
3196 llvm_unreachable("Unknown DWARF flavour");
3197 case 0:
3198 mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
3199 break;
3200 }
3201}
3202
3203static const MCPhysReg CSR_SaveList[] = { 0 };
3204static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
3205static const MCPhysReg RTCSR_SaveList[] = { 0 };
3206static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };
3207
3208
3209ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
3210 static const uint32_t *const Masks[] = {
3211 CSR_RegMask,
3212 RTCSR_RegMask,
3213 };
3214 return ArrayRef(Masks);
3215}
3216
3217bool SparcGenRegisterInfo::
3218isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3219 return
3220 false;
3221}
3222
3223bool SparcGenRegisterInfo::
3224isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
3225 return
3226 false;
3227}
3228
3229bool SparcGenRegisterInfo::
3230isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3231 return
3232 false;
3233}
3234
3235bool SparcGenRegisterInfo::
3236isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3237 return
3238 false;
3239}
3240
3241bool SparcGenRegisterInfo::
3242isConstantPhysReg(MCRegister PhysReg) const {
3243 return
3244 PhysReg == SP::G0 ||
3245 false;
3246}
3247
3248ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
3249 static const char *Names[] = {
3250 "CSR",
3251 "RTCSR",
3252 };
3253 return ArrayRef(Names);
3254}
3255
3256const SparcFrameLowering *
3257SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3258 return static_cast<const SparcFrameLowering *>(
3259 MF.getSubtarget().getFrameLowering());
3260}
3261
3262} // end namespace llvm
3263
3264#endif // GET_REGINFO_TARGET_DESC
3265
3266