1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace Sparc {
15enum {
16 DetectRoundChange = 0,
17 FeatureHardQuad = 1,
18 FeatureLeon = 2,
19 FeatureNoFMULS = 3,
20 FeatureNoFSMULD = 4,
21 FeatureOSA2011 = 5,
22 FeaturePWRPSR = 6,
23 FeatureReserveG1 = 7,
24 FeatureReserveG2 = 8,
25 FeatureReserveG3 = 9,
26 FeatureReserveG4 = 10,
27 FeatureReserveG5 = 11,
28 FeatureReserveG6 = 12,
29 FeatureReserveG7 = 13,
30 FeatureReserveI0 = 14,
31 FeatureReserveI1 = 15,
32 FeatureReserveI2 = 16,
33 FeatureReserveI3 = 17,
34 FeatureReserveI4 = 18,
35 FeatureReserveI5 = 19,
36 FeatureReserveL0 = 20,
37 FeatureReserveL1 = 21,
38 FeatureReserveL2 = 22,
39 FeatureReserveL3 = 23,
40 FeatureReserveL4 = 24,
41 FeatureReserveL5 = 25,
42 FeatureReserveL6 = 26,
43 FeatureReserveL7 = 27,
44 FeatureReserveO0 = 28,
45 FeatureReserveO1 = 29,
46 FeatureReserveO2 = 30,
47 FeatureReserveO3 = 31,
48 FeatureReserveO4 = 32,
49 FeatureReserveO5 = 33,
50 FeatureSoftFloat = 34,
51 FeatureSoftMulDiv = 35,
52 FeatureUA2005 = 36,
53 FeatureUA2007 = 37,
54 FeatureV8Deprecated = 38,
55 FeatureV8Plus = 39,
56 FeatureV9 = 40,
57 FeatureVIS = 41,
58 FeatureVIS2 = 42,
59 FeatureVIS3 = 43,
60 FixAllFDIVSQRT = 44,
61 FixTN0009 = 45,
62 FixTN0010 = 46,
63 FixTN0011 = 47,
64 FixTN0012 = 48,
65 FixTN0013 = 49,
66 InsertNOPLoad = 50,
67 LeonCASA = 51,
68 LeonCycleCounter = 52,
69 TuneSlowRDPC = 53,
70 UMACSMACSupport = 54,
71 UsePopc = 55,
72 NumSubtargetFeatures = 56
73};
74} // end namespace Sparc
75} // end namespace llvm
76
77#endif // GET_SUBTARGETINFO_ENUM
78
79
80#ifdef GET_SUBTARGETINFO_MACRO
81GET_SUBTARGETINFO_MACRO(DetectRoundChange, false, detectRoundChange)
82GET_SUBTARGETINFO_MACRO(FixAllFDIVSQRT, false, fixAllFDIVSQRT)
83GET_SUBTARGETINFO_MACRO(FixTN0009, false, fixTN0009)
84GET_SUBTARGETINFO_MACRO(FixTN0010, false, fixTN0010)
85GET_SUBTARGETINFO_MACRO(FixTN0011, false, fixTN0011)
86GET_SUBTARGETINFO_MACRO(FixTN0012, false, fixTN0012)
87GET_SUBTARGETINFO_MACRO(FixTN0013, false, fixTN0013)
88GET_SUBTARGETINFO_MACRO(HasHardQuad, false, hasHardQuad)
89GET_SUBTARGETINFO_MACRO(HasLeonCasa, false, hasLeonCasa)
90GET_SUBTARGETINFO_MACRO(HasLeonCycleCounter, false, hasLeonCycleCounter)
91GET_SUBTARGETINFO_MACRO(HasNoFMULS, false, hasNoFMULS)
92GET_SUBTARGETINFO_MACRO(HasNoFSMULD, false, hasNoFSMULD)
93GET_SUBTARGETINFO_MACRO(HasPWRPSR, false, hasPWRPSR)
94GET_SUBTARGETINFO_MACRO(HasSlowRDPC, false, hasSlowRDPC)
95GET_SUBTARGETINFO_MACRO(HasUmacSmac, false, hasUmacSmac)
96GET_SUBTARGETINFO_MACRO(InsertNOPLoad, false, insertNOPLoad)
97GET_SUBTARGETINFO_MACRO(IsLeon, false, isLeon)
98GET_SUBTARGETINFO_MACRO(IsOSA2011, false, isOSA2011)
99GET_SUBTARGETINFO_MACRO(IsUA2005, false, isUA2005)
100GET_SUBTARGETINFO_MACRO(IsUA2007, false, isUA2007)
101GET_SUBTARGETINFO_MACRO(IsV8Plus, false, isV8Plus)
102GET_SUBTARGETINFO_MACRO(IsV9, false, isV9)
103GET_SUBTARGETINFO_MACRO(IsVIS, false, isVIS)
104GET_SUBTARGETINFO_MACRO(IsVIS2, false, isVIS2)
105GET_SUBTARGETINFO_MACRO(IsVIS3, false, isVIS3)
106GET_SUBTARGETINFO_MACRO(UsePopc, false, usePopc)
107GET_SUBTARGETINFO_MACRO(UseSoftFloat, false, useSoftFloat)
108GET_SUBTARGETINFO_MACRO(UseSoftMulDiv, false, useSoftMulDiv)
109GET_SUBTARGETINFO_MACRO(UseV8DeprecatedInsts, false, useV8DeprecatedInsts)
110#undef GET_SUBTARGETINFO_MACRO
111#endif // GET_SUBTARGETINFO_MACRO
112
113
114#ifdef GET_SUBTARGETINFO_MC_DESC
115#undef GET_SUBTARGETINFO_MC_DESC
116
117namespace llvm {
118// Sorted (by key) array of values for CPU features.
119extern const llvm::SubtargetFeatureKV SparcFeatureKV[] = {
120 { "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", Sparc::FeatureV8Deprecated, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
121 { "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", Sparc::DetectRoundChange, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
122 { "fix-tn0009", "Enable workaround for errata described in GRLIB-TN-0009", Sparc::FixTN0009, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
123 { "fix-tn0010", "Enable workaround for errata described in GRLIB-TN-0010", Sparc::FixTN0010, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
124 { "fix-tn0011", "Enable workaround for errata described in GRLIB-TN-0011", Sparc::FixTN0011, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
125 { "fix-tn0012", "Enable workaround for errata described in GRLIB-TN-0012", Sparc::FixTN0012, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
126 { "fix-tn0013", "Enable workaround for errata described in GRLIB-TN-0013", Sparc::FixTN0013, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
127 { "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", Sparc::FixAllFDIVSQRT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
128 { "hard-quad-float", "Enable quad-word floating point instructions", Sparc::FeatureHardQuad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
129 { "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", Sparc::LeonCASA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
130 { "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", Sparc::UMACSMACSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
131 { "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", Sparc::InsertNOPLoad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { "leon", "Enable LEON extensions", Sparc::FeatureLeon, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { "leoncyclecounter", "Use the Leon cycle counter register", Sparc::LeonCycleCounter, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { "leonpwrpsr", "Enable the PWRPSR instruction", Sparc::FeaturePWRPSR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { "no-fmuls", "Disable the fmuls instruction.", Sparc::FeatureNoFMULS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { "no-fsmuld", "Disable the fsmuld instruction.", Sparc::FeatureNoFSMULD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { "osa2011", "Enable Oracle SPARC Architecture 2011 extensions", Sparc::FeatureOSA2011, { { { 0xf0000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { "popc", "Use the popc (population count) instruction", Sparc::UsePopc, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { "reserve-g1", "Reserve G1, making it unavailable as a GPR", Sparc::FeatureReserveG1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { "reserve-g2", "Reserve G2, making it unavailable as a GPR", Sparc::FeatureReserveG2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { "reserve-g3", "Reserve G3, making it unavailable as a GPR", Sparc::FeatureReserveG3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { "reserve-g4", "Reserve G4, making it unavailable as a GPR", Sparc::FeatureReserveG4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { "reserve-g5", "Reserve G5, making it unavailable as a GPR", Sparc::FeatureReserveG5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { "reserve-g6", "Reserve G6, making it unavailable as a GPR", Sparc::FeatureReserveG6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { "reserve-g7", "Reserve G7, making it unavailable as a GPR", Sparc::FeatureReserveG7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { "reserve-i0", "Reserve I0, making it unavailable as a GPR", Sparc::FeatureReserveI0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { "reserve-i1", "Reserve I1, making it unavailable as a GPR", Sparc::FeatureReserveI1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { "reserve-i2", "Reserve I2, making it unavailable as a GPR", Sparc::FeatureReserveI2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149 { "reserve-i3", "Reserve I3, making it unavailable as a GPR", Sparc::FeatureReserveI3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
150 { "reserve-i4", "Reserve I4, making it unavailable as a GPR", Sparc::FeatureReserveI4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
151 { "reserve-i5", "Reserve I5, making it unavailable as a GPR", Sparc::FeatureReserveI5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
152 { "reserve-l0", "Reserve L0, making it unavailable as a GPR", Sparc::FeatureReserveL0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
153 { "reserve-l1", "Reserve L1, making it unavailable as a GPR", Sparc::FeatureReserveL1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
154 { "reserve-l2", "Reserve L2, making it unavailable as a GPR", Sparc::FeatureReserveL2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
155 { "reserve-l3", "Reserve L3, making it unavailable as a GPR", Sparc::FeatureReserveL3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
156 { "reserve-l4", "Reserve L4, making it unavailable as a GPR", Sparc::FeatureReserveL4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
157 { "reserve-l5", "Reserve L5, making it unavailable as a GPR", Sparc::FeatureReserveL5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
158 { "reserve-l6", "Reserve L6, making it unavailable as a GPR", Sparc::FeatureReserveL6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
159 { "reserve-l7", "Reserve L7, making it unavailable as a GPR", Sparc::FeatureReserveL7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
160 { "reserve-o0", "Reserve O0, making it unavailable as a GPR", Sparc::FeatureReserveO0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
161 { "reserve-o1", "Reserve O1, making it unavailable as a GPR", Sparc::FeatureReserveO1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
162 { "reserve-o2", "Reserve O2, making it unavailable as a GPR", Sparc::FeatureReserveO2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
163 { "reserve-o3", "Reserve O3, making it unavailable as a GPR", Sparc::FeatureReserveO3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
164 { "reserve-o4", "Reserve O4, making it unavailable as a GPR", Sparc::FeatureReserveO4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
165 { "reserve-o5", "Reserve O5, making it unavailable as a GPR", Sparc::FeatureReserveO5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
166 { "slow-rdpc", "rd %pc, %XX is slow", Sparc::TuneSlowRDPC, { { { 0x10000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
167 { "soft-float", "Use software emulation for floating point", Sparc::FeatureSoftFloat, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
168 { "soft-mul-div", "Use software emulation for integer multiply and divide", Sparc::FeatureSoftMulDiv, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
169 { "ua2005", "Enable UltraSPARC Architecture 2005 extensions", Sparc::FeatureUA2005, { { { 0x70000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
170 { "ua2007", "Enable UltraSPARC Architecture 2007 extensions", Sparc::FeatureUA2007, { { { 0x70000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
171 { "v8plus", "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code", Sparc::FeatureV8Plus, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
172 { "v9", "Enable SPARC-V9 instructions", Sparc::FeatureV9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
173 { "vis", "Enable UltraSPARC Visual Instruction Set extensions", Sparc::FeatureVIS, { { { 0x10000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
174 { "vis2", "Enable Visual Instruction Set extensions II", Sparc::FeatureVIS2, { { { 0x10000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
175 { "vis3", "Enable Visual Instruction Set extensions III", Sparc::FeatureVIS3, { { { 0x10000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
176};
177
178#ifdef DBGFIELD
179#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
180#endif
181#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
182#define DBGFIELD(x) x,
183#define DBGVAL_OR_NULLPTR(x) x
184#else
185#define DBGFIELD(x)
186#define DBGVAL_OR_NULLPTR(x) nullptr
187#endif
188
189// Functional units for "LEON2Itineraries"
190namespace LEON2ItinerariesFU {
191 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
192 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
193} // end namespace LEON2ItinerariesFU
194
195// Functional units for "LEON3Itineraries"
196namespace LEON3ItinerariesFU {
197 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
198 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
199} // end namespace LEON3ItinerariesFU
200
201// Functional units for "LEON4Itineraries"
202namespace LEON4ItinerariesFU {
203 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
204 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
205} // end namespace LEON4ItinerariesFU
206
207extern const llvm::InstrStage SparcStages[] = {
208 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
209 { 1, LEON2ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
210 { 1, LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
211 { 1, LEON2ItinerariesFU::LEONIU | LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
212 { 1, LEON3ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
213 { 1, LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
214 { 1, LEON3ItinerariesFU::LEONIU | LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
215 { 1, LEON4ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
216 { 1, LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 8
217 { 1, LEON4ItinerariesFU::LEONIU | LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 9
218 { 0, 0, 0, llvm::InstrStage::Required } // End stages
219};
220extern const unsigned SparcOperandCycles[] = {
221 0, // No itinerary
222 1, 1, // 1-2
223 7, 1, // 3-4
224 2, 1, // 5-6
225 2, 1, // 7-8
226 7, 1, // 9-10
227 36, 1, // 11-12
228 20, 1, // 13-14
229 21, 1, // 15-16
230 16, 1, // 17-18
231 2, 1, // 19-20
232 65, 1, // 21-22
233 37, 1, // 23-24
234 2, 1, // 25-26
235 2, 1, // 27-28
236 1, 1, // 29-30
237 35, 1, // 31-32
238 5, 1, // 33-34
239 2, 1, // 35-36
240 3, 1, // 37-38
241 5, 1, // 39-40
242 1, 1, // 41-42
243 7, 1, // 43-44
244 3, 1, // 45-46
245 2, 1, // 47-48
246 4, 1, // 49-50
247 17, 1, // 51-52
248 16, 1, // 53-54
249 4, 1, // 55-56
250 4, 1, // 57-58
251 2, 1, // 59-60
252 25, 1, // 61-62
253 24, 1, // 63-64
254 4, 1, // 65-66
255 2, 1, // 67-68
256 1, 1, // 69-70
257 35, 1, // 71-72
258 2, 1, // 73-74
259 1, 1, // 75-76
260 4, 1, // 77-78
261 5, 1, // 79-80
262 4, 1, // 81-82
263 1, 1, // 83-84
264 7, 1, // 85-86
265 3, 1, // 87-88
266 2, 1, // 89-90
267 4, 1, // 91-92
268 17, 1, // 93-94
269 16, 1, // 95-96
270 4, 1, // 97-98
271 4, 1, // 99-100
272 2, 1, // 101-102
273 25, 1, // 103-104
274 24, 1, // 105-106
275 4, 1, // 107-108
276 1, 1, // 109-110
277 1, 1, // 111-112
278 35, 1, // 113-114
279 2, 1, // 115-116
280 1, 1, // 117-118
281 1, 1, // 119-120
282 1, 1, // 121-122
283 4, 1, // 123-124
284 0 // End operand cycles
285};
286extern const unsigned SparcForwardingPaths[] = {
287 0, // No itinerary
288 0, 0, // 1-2
289 0, 0, // 3-4
290 0, 0, // 5-6
291 0, 0, // 7-8
292 0, 0, // 9-10
293 0, 0, // 11-12
294 0, 0, // 13-14
295 0, 0, // 15-16
296 0, 0, // 17-18
297 0, 0, // 19-20
298 0, 0, // 21-22
299 0, 0, // 23-24
300 0, 0, // 25-26
301 0, 0, // 27-28
302 0, 0, // 29-30
303 0, 0, // 31-32
304 0, 0, // 33-34
305 0, 0, // 35-36
306 0, 0, // 37-38
307 0, 0, // 39-40
308 0, 0, // 41-42
309 0, 0, // 43-44
310 0, 0, // 45-46
311 0, 0, // 47-48
312 0, 0, // 49-50
313 0, 0, // 51-52
314 0, 0, // 53-54
315 0, 0, // 55-56
316 0, 0, // 57-58
317 0, 0, // 59-60
318 0, 0, // 61-62
319 0, 0, // 63-64
320 0, 0, // 65-66
321 0, 0, // 67-68
322 0, 0, // 69-70
323 0, 0, // 71-72
324 0, 0, // 73-74
325 0, 0, // 75-76
326 0, 0, // 77-78
327 0, 0, // 79-80
328 0, 0, // 81-82
329 0, 0, // 83-84
330 0, 0, // 85-86
331 0, 0, // 87-88
332 0, 0, // 89-90
333 0, 0, // 91-92
334 0, 0, // 93-94
335 0, 0, // 95-96
336 0, 0, // 97-98
337 0, 0, // 99-100
338 0, 0, // 101-102
339 0, 0, // 103-104
340 0, 0, // 105-106
341 0, 0, // 107-108
342 0, 0, // 109-110
343 0, 0, // 111-112
344 0, 0, // 113-114
345 0, 0, // 115-116
346 0, 0, // 117-118
347 0, 0, // 119-120
348 0, 0, // 121-122
349 0, 0, // 123-124
350 0 // End bypass tables
351};
352
353static constexpr llvm::InstrItinerary LEON2Itineraries[] = {
354 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
355 { 1, 1, 2, 1, 3 }, // 1 IIC_iu_instr
356 { 1, 2, 3, 3, 5 }, // 2 IIC_fpu_normal_instr
357 { 1, 3, 4, 5, 7 }, // 3 IIC_jmp_or_call
358 { 1, 2, 3, 7, 9 }, // 4 IIC_fpu_abs
359 { 1, 2, 3, 9, 11 }, // 5 IIC_fpu_fast_instr
360 { 1, 2, 3, 11, 13 }, // 6 IIC_fpu_divd
361 { 1, 2, 3, 13, 15 }, // 7 IIC_fpu_divs
362 { 1, 2, 3, 15, 17 }, // 8 IIC_fpu_muld
363 { 1, 2, 3, 17, 19 }, // 9 IIC_fpu_muls
364 { 1, 2, 3, 19, 21 }, // 10 IIC_fpu_negs
365 { 1, 2, 3, 21, 23 }, // 11 IIC_fpu_sqrtd
366 { 1, 2, 3, 23, 25 }, // 12 IIC_fpu_sqrts
367 { 1, 2, 3, 25, 27 }, // 13 IIC_fpu_stod
368 { 1, 3, 4, 27, 29 }, // 14 IIC_ldd
369 { 1, 3, 4, 29, 31 }, // 15 IIC_iu_or_fpu_instr
370 { 1, 1, 2, 31, 33 }, // 16 IIC_iu_div
371 { 0, 0, 0, 0, 0 }, // 17 IIC_smac_umac
372 { 1, 1, 2, 33, 35 }, // 18 IIC_iu_smul
373 { 1, 3, 4, 35, 37 }, // 19 IIC_st
374 { 1, 3, 4, 37, 39 }, // 20 IIC_std
375 { 1, 1, 2, 39, 41 }, // 21 IIC_iu_umul
376 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
377};
378
379static constexpr llvm::InstrItinerary LEON3Itineraries[] = {
380 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
381 { 1, 4, 5, 41, 43 }, // 1 IIC_iu_instr
382 { 1, 5, 6, 43, 45 }, // 2 IIC_fpu_normal_instr
383 { 1, 6, 7, 45, 47 }, // 3 IIC_jmp_or_call
384 { 1, 5, 6, 47, 49 }, // 4 IIC_fpu_abs
385 { 1, 5, 6, 49, 51 }, // 5 IIC_fpu_fast_instr
386 { 1, 5, 6, 51, 53 }, // 6 IIC_fpu_divd
387 { 1, 5, 6, 53, 55 }, // 7 IIC_fpu_divs
388 { 1, 5, 6, 55, 57 }, // 8 IIC_fpu_muld
389 { 1, 5, 6, 57, 59 }, // 9 IIC_fpu_muls
390 { 1, 5, 6, 59, 61 }, // 10 IIC_fpu_negs
391 { 1, 5, 6, 61, 63 }, // 11 IIC_fpu_sqrtd
392 { 1, 5, 6, 63, 65 }, // 12 IIC_fpu_sqrts
393 { 1, 5, 6, 65, 67 }, // 13 IIC_fpu_stod
394 { 1, 6, 7, 67, 69 }, // 14 IIC_ldd
395 { 1, 6, 7, 69, 71 }, // 15 IIC_iu_or_fpu_instr
396 { 1, 4, 5, 71, 73 }, // 16 IIC_iu_div
397 { 1, 4, 5, 73, 75 }, // 17 IIC_smac_umac
398 { 1, 4, 5, 75, 77 }, // 18 IIC_iu_smul
399 { 1, 6, 7, 77, 79 }, // 19 IIC_st
400 { 1, 6, 7, 79, 81 }, // 20 IIC_std
401 { 1, 4, 5, 81, 83 }, // 21 IIC_iu_umul
402 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
403};
404
405static constexpr llvm::InstrItinerary LEON4Itineraries[] = {
406 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
407 { 1, 7, 8, 83, 85 }, // 1 IIC_iu_instr
408 { 1, 8, 9, 85, 87 }, // 2 IIC_fpu_normal_instr
409 { 1, 9, 10, 87, 89 }, // 3 IIC_jmp_or_call
410 { 1, 8, 9, 89, 91 }, // 4 IIC_fpu_abs
411 { 1, 8, 9, 91, 93 }, // 5 IIC_fpu_fast_instr
412 { 1, 8, 9, 93, 95 }, // 6 IIC_fpu_divd
413 { 1, 8, 9, 95, 97 }, // 7 IIC_fpu_divs
414 { 1, 8, 9, 97, 99 }, // 8 IIC_fpu_muld
415 { 1, 8, 9, 99, 101 }, // 9 IIC_fpu_muls
416 { 1, 8, 9, 101, 103 }, // 10 IIC_fpu_negs
417 { 1, 8, 9, 103, 105 }, // 11 IIC_fpu_sqrtd
418 { 1, 8, 9, 105, 107 }, // 12 IIC_fpu_sqrts
419 { 1, 8, 9, 107, 109 }, // 13 IIC_fpu_stod
420 { 1, 9, 10, 109, 111 }, // 14 IIC_ldd
421 { 1, 9, 10, 111, 113 }, // 15 IIC_iu_or_fpu_instr
422 { 1, 7, 8, 113, 115 }, // 16 IIC_iu_div
423 { 1, 7, 8, 115, 117 }, // 17 IIC_smac_umac
424 { 1, 7, 8, 117, 119 }, // 18 IIC_iu_smul
425 { 1, 9, 10, 119, 121 }, // 19 IIC_st
426 { 1, 9, 10, 121, 123 }, // 20 IIC_std
427 { 1, 7, 8, 123, 125 }, // 21 IIC_iu_umul
428 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
429};
430
431// ===============================================================
432// Data tables for the new per-operand machine model.
433
434// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
435extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[] = {
436 { 0, 0, 0 }, // Invalid
437}; // SparcWriteProcResTable
438
439// {Cycles, WriteResourceID}
440extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[] = {
441 { 0, 0}, // Invalid
442}; // SparcWriteLatencyTable
443
444// {UseIdx, WriteResourceID, Cycles}
445extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[] = {
446 {0, 0, 0}, // Invalid
447}; // SparcReadAdvanceTable
448
449#ifdef __GNUC__
450#pragma GCC diagnostic push
451#pragma GCC diagnostic ignored "-Woverlength-strings"
452#endif
453static constexpr char SparcSchedClassNamesStorage[] =
454 "\0"
455 "InvalidSchedClass\0"
456 ;
457#ifdef __GNUC__
458#pragma GCC diagnostic pop
459#endif
460
461static constexpr llvm::StringTable SparcSchedClassNames =
462 SparcSchedClassNamesStorage;
463
464static const llvm::MCSchedModel NoSchedModel = {
465 MCSchedModel::DefaultIssueWidth,
466 MCSchedModel::DefaultMicroOpBufferSize,
467 MCSchedModel::DefaultLoopMicroOpBufferSize,
468 MCSchedModel::DefaultLoadLatency,
469 MCSchedModel::DefaultHighLatency,
470 MCSchedModel::DefaultMispredictPenalty,
471 false, // PostRAScheduler
472 false, // CompleteModel
473 false, // EnableIntervals
474 0, // Processor ID
475 nullptr, nullptr, 0, 0, // No instruction-level machine model.
476 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
477 nullptr, // No Itinerary
478 nullptr // No extra processor descriptor
479};
480
481static const llvm::MCSchedModel LEON2ItinerariesModel = {
482 MCSchedModel::DefaultIssueWidth,
483 MCSchedModel::DefaultMicroOpBufferSize,
484 MCSchedModel::DefaultLoopMicroOpBufferSize,
485 MCSchedModel::DefaultLoadLatency,
486 MCSchedModel::DefaultHighLatency,
487 MCSchedModel::DefaultMispredictPenalty,
488 false, // PostRAScheduler
489 false, // CompleteModel
490 false, // EnableIntervals
491 1, // Processor ID
492 nullptr, nullptr, 0, 0, // No instruction-level machine model.
493 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
494 LEON2Itineraries,
495 nullptr // No extra processor descriptor
496};
497
498static const llvm::MCSchedModel LEON3ItinerariesModel = {
499 MCSchedModel::DefaultIssueWidth,
500 MCSchedModel::DefaultMicroOpBufferSize,
501 MCSchedModel::DefaultLoopMicroOpBufferSize,
502 MCSchedModel::DefaultLoadLatency,
503 MCSchedModel::DefaultHighLatency,
504 MCSchedModel::DefaultMispredictPenalty,
505 false, // PostRAScheduler
506 false, // CompleteModel
507 false, // EnableIntervals
508 2, // Processor ID
509 nullptr, nullptr, 0, 0, // No instruction-level machine model.
510 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
511 LEON3Itineraries,
512 nullptr // No extra processor descriptor
513};
514
515static const llvm::MCSchedModel LEON4ItinerariesModel = {
516 MCSchedModel::DefaultIssueWidth,
517 MCSchedModel::DefaultMicroOpBufferSize,
518 MCSchedModel::DefaultLoopMicroOpBufferSize,
519 MCSchedModel::DefaultLoadLatency,
520 MCSchedModel::DefaultHighLatency,
521 MCSchedModel::DefaultMispredictPenalty,
522 false, // PostRAScheduler
523 false, // CompleteModel
524 false, // EnableIntervals
525 3, // Processor ID
526 nullptr, nullptr, 0, 0, // No instruction-level machine model.
527 DBGVAL_OR_NULLPTR(&SparcSchedClassNames), // SchedClassNames
528 LEON4Itineraries,
529 nullptr // No extra processor descriptor
530};
531
532#undef DBGFIELD
533
534#undef DBGVAL_OR_NULLPTR
535
536// Sorted (by key) array of values for CPU subtype.
537extern const llvm::SubtargetSubTypeKV SparcSubTypeKV[] = {
538 { "at697e", { { { 0x4000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
539 { "at697f", { { { 0x4000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
540 { "f934", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
541 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
542 { "gr712rc", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
543 { "gr740", { { { 0x58000000000044ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON4ItinerariesModel },
544 { "hypersparc", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
545 { "leon2", { { { 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
546 { "leon3", { { { 0x40000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
547 { "leon4", { { { 0x48000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON4ItinerariesModel },
548 { "ma2080", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
549 { "ma2085", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
550 { "ma2100", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
551 { "ma2150", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
552 { "ma2155", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
553 { "ma2450", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
554 { "ma2455", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
555 { "ma2480", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
556 { "ma2485", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
557 { "ma2x5x", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
558 { "ma2x8x", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
559 { "myriad2", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
560 { "myriad2.1", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
561 { "myriad2.2", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
562 { "myriad2.3", { { { 0x8000000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
563 { "niagara", { { { 0x75000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
564 { "niagara2", { { { 0x80075000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
565 { "niagara3", { { { 0x800f7000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
566 { "niagara4", { { { 0x800f7000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
567 { "sparclet", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
568 { "sparclite", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
569 { "sparclite86x", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
570 { "supersparc", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
571 { "tsc701", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
572 { "ultrasparc", { { { 0x34000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x20000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
573 { "ultrasparc3", { { { 0x74000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x20000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
574 { "ut699", { { { 0x410000000001cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
575 { "v7", { { { 0x800000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
576 { "v8", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
577 { "v9", { { { 0x10000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
578};
579
580// Sorted array of names of CPU subtypes, including aliases.
581extern const llvm::StringRef SparcNames[] = {
582"at697e",
583"at697f",
584"f934",
585"generic",
586"gr712rc",
587"gr740",
588"hypersparc",
589"leon2",
590"leon3",
591"leon4",
592"ma2080",
593"ma2085",
594"ma2100",
595"ma2150",
596"ma2155",
597"ma2450",
598"ma2455",
599"ma2480",
600"ma2485",
601"ma2x5x",
602"ma2x8x",
603"myriad2",
604"myriad2.1",
605"myriad2.2",
606"myriad2.3",
607"niagara",
608"niagara2",
609"niagara3",
610"niagara4",
611"sparclet",
612"sparclite",
613"sparclite86x",
614"supersparc",
615"tsc701",
616"ultrasparc",
617"ultrasparc3",
618"ut699",
619"v7",
620"v8",
621"v9"};
622
623namespace Sparc_MC {
624unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
625 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
626 // Don't know how to resolve this scheduling class.
627 return 0;
628}
629} // end namespace Sparc_MC
630
631struct SparcGenMCSubtargetInfo : public MCSubtargetInfo {
632 SparcGenMCSubtargetInfo(const Triple &TT,
633 StringRef CPU, StringRef TuneCPU, StringRef FS,
634 ArrayRef<StringRef> PN,
635 ArrayRef<SubtargetFeatureKV> PF,
636 ArrayRef<SubtargetSubTypeKV> PD,
637 const MCWriteProcResEntry *WPR,
638 const MCWriteLatencyEntry *WL,
639 const MCReadAdvanceEntry *RA, const InstrStage *IS,
640 const unsigned *OC, const unsigned *FP) :
641 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
642 WPR, WL, RA, IS, OC, FP) { }
643
644 unsigned resolveVariantSchedClass(unsigned SchedClass,
645 const MCInst *MI, const MCInstrInfo *MCII,
646 unsigned CPUID) const override {
647 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
648 }
649};
650
651static inline MCSubtargetInfo *createSparcMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
652 return new SparcGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, SparcNames, SparcFeatureKV, SparcSubTypeKV,
653 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
654 SparcStages, SparcOperandCycles, SparcForwardingPaths);
655}
656
657} // end namespace llvm
658
659#endif // GET_SUBTARGETINFO_MC_DESC
660
661
662#ifdef GET_SUBTARGETINFO_TARGET_DESC
663#undef GET_SUBTARGETINFO_TARGET_DESC
664
665#include "llvm/ADT/BitmaskEnum.h"
666#include "llvm/Support/Debug.h"
667#include "llvm/Support/raw_ostream.h"
668
669// ParseSubtargetFeatures - Parses features string setting specified
670// subtarget options.
671void llvm::SparcSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
672 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
673 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
674 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
675 InitMCProcessorInfo(CPU, TuneCPU, FS);
676 const FeatureBitset &Bits = getFeatureBits();
677 if (Bits[Sparc::DetectRoundChange]) DetectRoundChange = true;
678 if (Bits[Sparc::FeatureHardQuad]) HasHardQuad = true;
679 if (Bits[Sparc::FeatureLeon]) IsLeon = true;
680 if (Bits[Sparc::FeatureNoFMULS]) HasNoFMULS = true;
681 if (Bits[Sparc::FeatureNoFSMULD]) HasNoFSMULD = true;
682 if (Bits[Sparc::FeatureOSA2011]) IsOSA2011 = true;
683 if (Bits[Sparc::FeaturePWRPSR]) HasPWRPSR = true;
684 if (Bits[Sparc::FeatureReserveG1]) ReserveRegister[1 + SP::G0] = true;
685 if (Bits[Sparc::FeatureReserveG2]) ReserveRegister[2 + SP::G0] = true;
686 if (Bits[Sparc::FeatureReserveG3]) ReserveRegister[3 + SP::G0] = true;
687 if (Bits[Sparc::FeatureReserveG4]) ReserveRegister[4 + SP::G0] = true;
688 if (Bits[Sparc::FeatureReserveG5]) ReserveRegister[5 + SP::G0] = true;
689 if (Bits[Sparc::FeatureReserveG6]) ReserveRegister[6 + SP::G0] = true;
690 if (Bits[Sparc::FeatureReserveG7]) ReserveRegister[7 + SP::G0] = true;
691 if (Bits[Sparc::FeatureReserveI0]) ReserveRegister[0 + SP::I0] = true;
692 if (Bits[Sparc::FeatureReserveI1]) ReserveRegister[1 + SP::I0] = true;
693 if (Bits[Sparc::FeatureReserveI2]) ReserveRegister[2 + SP::I0] = true;
694 if (Bits[Sparc::FeatureReserveI3]) ReserveRegister[3 + SP::I0] = true;
695 if (Bits[Sparc::FeatureReserveI4]) ReserveRegister[4 + SP::I0] = true;
696 if (Bits[Sparc::FeatureReserveI5]) ReserveRegister[5 + SP::I0] = true;
697 if (Bits[Sparc::FeatureReserveL0]) ReserveRegister[0 + SP::L0] = true;
698 if (Bits[Sparc::FeatureReserveL1]) ReserveRegister[1 + SP::L0] = true;
699 if (Bits[Sparc::FeatureReserveL2]) ReserveRegister[2 + SP::L0] = true;
700 if (Bits[Sparc::FeatureReserveL3]) ReserveRegister[3 + SP::L0] = true;
701 if (Bits[Sparc::FeatureReserveL4]) ReserveRegister[4 + SP::L0] = true;
702 if (Bits[Sparc::FeatureReserveL5]) ReserveRegister[5 + SP::L0] = true;
703 if (Bits[Sparc::FeatureReserveL6]) ReserveRegister[6 + SP::L0] = true;
704 if (Bits[Sparc::FeatureReserveL7]) ReserveRegister[7 + SP::L0] = true;
705 if (Bits[Sparc::FeatureReserveO0]) ReserveRegister[0 + SP::O0] = true;
706 if (Bits[Sparc::FeatureReserveO1]) ReserveRegister[1 + SP::O0] = true;
707 if (Bits[Sparc::FeatureReserveO2]) ReserveRegister[2 + SP::O0] = true;
708 if (Bits[Sparc::FeatureReserveO3]) ReserveRegister[3 + SP::O0] = true;
709 if (Bits[Sparc::FeatureReserveO4]) ReserveRegister[4 + SP::O0] = true;
710 if (Bits[Sparc::FeatureReserveO5]) ReserveRegister[5 + SP::O0] = true;
711 if (Bits[Sparc::FeatureSoftFloat]) UseSoftFloat = true;
712 if (Bits[Sparc::FeatureSoftMulDiv]) UseSoftMulDiv = true;
713 if (Bits[Sparc::FeatureUA2005]) IsUA2005 = true;
714 if (Bits[Sparc::FeatureUA2007]) IsUA2007 = true;
715 if (Bits[Sparc::FeatureV8Deprecated]) UseV8DeprecatedInsts = true;
716 if (Bits[Sparc::FeatureV8Plus]) IsV8Plus = true;
717 if (Bits[Sparc::FeatureV9]) IsV9 = true;
718 if (Bits[Sparc::FeatureVIS]) IsVIS = true;
719 if (Bits[Sparc::FeatureVIS2]) IsVIS2 = true;
720 if (Bits[Sparc::FeatureVIS3]) IsVIS3 = true;
721 if (Bits[Sparc::FixAllFDIVSQRT]) FixAllFDIVSQRT = true;
722 if (Bits[Sparc::FixTN0009]) FixTN0009 = true;
723 if (Bits[Sparc::FixTN0010]) FixTN0010 = true;
724 if (Bits[Sparc::FixTN0011]) FixTN0011 = true;
725 if (Bits[Sparc::FixTN0012]) FixTN0012 = true;
726 if (Bits[Sparc::FixTN0013]) FixTN0013 = true;
727 if (Bits[Sparc::InsertNOPLoad]) InsertNOPLoad = true;
728 if (Bits[Sparc::LeonCASA]) HasLeonCasa = true;
729 if (Bits[Sparc::LeonCycleCounter]) HasLeonCycleCounter = true;
730 if (Bits[Sparc::TuneSlowRDPC]) HasSlowRDPC = true;
731 if (Bits[Sparc::UMACSMACSupport]) HasUmacSmac = true;
732 if (Bits[Sparc::UsePopc]) UsePopc = true;
733}
734#endif // GET_SUBTARGETINFO_TARGET_DESC
735
736
737#ifdef GET_SUBTARGETINFO_HEADER
738#undef GET_SUBTARGETINFO_HEADER
739
740namespace llvm {
741class DFAPacketizer;
742namespace Sparc_MC {
743unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
744} // end namespace Sparc_MC
745
746struct SparcGenSubtargetInfo : public TargetSubtargetInfo {
747 explicit SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
748public:
749 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
750 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
751 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
752};
753} // end namespace llvm
754
755#endif // GET_SUBTARGETINFO_HEADER
756
757
758#ifdef GET_SUBTARGETINFO_CTOR
759#undef GET_SUBTARGETINFO_CTOR
760
761#include "llvm/CodeGen/TargetSchedule.h"
762
763namespace llvm {
764extern const llvm::StringRef SparcNames[];
765extern const llvm::SubtargetFeatureKV SparcFeatureKV[];
766extern const llvm::SubtargetSubTypeKV SparcSubTypeKV[];
767extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[];
768extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[];
769extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[];
770extern const llvm::InstrStage SparcStages[];
771extern const unsigned SparcOperandCycles[];
772extern const unsigned SparcForwardingPaths[];
773SparcGenSubtargetInfo::SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
774 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(SparcNames, 40), ArrayRef(SparcFeatureKV, 56), ArrayRef(SparcSubTypeKV, 40),
775 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
776 SparcStages, SparcOperandCycles, SparcForwardingPaths) {}
777
778unsigned SparcGenSubtargetInfo
779::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
780 report_fatal_error("Expected a variant SchedClass");
781} // SparcGenSubtargetInfo::resolveSchedClass
782
783unsigned SparcGenSubtargetInfo
784::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
785 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
786} // SparcGenSubtargetInfo::resolveVariantSchedClass
787
788} // end namespace llvm
789
790#endif // GET_SUBTARGETINFO_CTOR
791
792
793#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
794#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
795
796#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
797
798
799#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
800#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
801
802#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
803
804